MICRF221 ® 3.3V, QwikRadio 850 MHz to 950 MHz Receiver General Description Features The MICRF221 is a third generation QwikRadio® • Complete receiver on a chip receiver, offering all the benefits of Micrel's earlier • -109dBm sensitivity, 1kbps, and BER 10-2 QwikRadio® products with significant improvements, • Image rejection mixer including: enhanced sensitivity, automatic duty-cycle feature and RSSI output. • 850MHz to 950MHz frequency range • Low power, 9mA @ 868MHz, continuous on The MICRF221 is a super-heterodyne receiver, designed for OOK and ASK modulation. The down- • Data rates to 10kbps (Manchester Encoded) conversion mixer also provides image rejection. • Auto polling (sleep mode, current < 0.1 mA) The MICRF221 receiver provides a SLEEP Mode for • Analog RSSI output duty-cycle operation and an enhanced, customer • Programmable “low sensitivity” mode programmable "WAKE" function. These features are • No IF filter required further combined into a wholly integrated "self-polling" scheme that is ideal for low and ultra-low power • Excellent selectivity and noise rejection applications, such as RKE and RFID • Low external part count All post-detection data filtering is provided on the • Additional functions programmed through serial MICRF221 receiver. Any one of four filter bandwidths interface may be selected externally by the user in binary steps, from 1.25kHz to 10kHz. The user needs only to program the device with a set of easily determined values based on data rate, code modulation format, and desired duty- cycle operation. Datasheets and support documentation are available on Micrel’s website at: www.micrel.com. Typical Application Figure 1: MICRF221 Receiver 915.0 MHz, 1kHz Baud Rate Example QwikRadio is a registered trademark of Micrel, Inc. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com August 12, 2015 Revision 2.0

Micrel Inc. MICRF221 Ordering Information Part Number Temperature Range Package MICRF221AYQS –40° to +105°C 16-Pin QSOP Pin Configuration 16-Pin QSOP (QS) Pin Description 16-Pin Pin Pin Function QSOP Name Reference Oscillator (input): Reference resonator input connection to pierce oscillator stage. May also be 1 RO1 driven by external reference signal of 1.5V p-p amplitude maximum. 7pF to GND during normal operation. 2 GNDRF Negative supply connection associated with ANT RF input. Antenna (input): RF signal input from antenna. Internally AC coupled. It is recommended a matching network 3 ANT with an inductor-to-RF ground be used to improve ESD protection. 4 GNDRF Negative supply connection associated with ANT RF input. 5 VDD Positive supply connection for all chip functions. Squelch control logic input with an active internal pull-up (3uA typical) pulls the logic-input HIGH when the 6 SQ device is enabled. This feature is not recommended in MICRF221 and this pin should remain floating. Select (input): Logic control input with active 3μA (8μA max) internal pull-up when not in shutdown or SLEEP 7 SEL0 mode. It does not need to be defined in SLEEP mode. Used in conjunction with SEL1 to control D3 bandwidth LSB when serial interface contains default setting. 8 SHDN Shutdown logic control input. Active internal pull-up. 9 GND Negative supply connection for all chip functions except for RF input. Demodulated data (output): May be blanked until bit checking test is acceptable. A current limited CMOS 10 DO output during normal operation this pin is also used as a CMOS Schmitt input for serial interface data. A 25kΩ pull-down is present when device is in shutdown and sleep modes. Select (input): Logic control input with active 3μA (8μA max) internal pull-up when not in shutdown or SLEEP 11 SEL1 mode. It does not need to be defined in SLEEP mode. Used in conjunction with SEL0, to control D4 bandwidth MSB, when serial interface contains default setting. Demodulation threshold voltage integration capacitor. Capacitor-to-GND sets the settling time for the 12 CTH demodulation data slicing level. Values above 1nF are recommended and should be optimized for data rate and data profile. 13 CAGC AGC filter capacitor. A capacitor, normally greater than 0.47μF, is connected from this pin-to-GND Received signal strength indication (output): Output is from a switched capacitor integrating op amp with 14 RSSI 220Ω typical output impedance. Serial interface input clock. CMOS Schmitt input. A 25kΩ pull-down is present when device is in shutdown 15 SCLK mode. 16 RO2 Reference resonator connection. 7pF to GND during normal operation. August 12, 2015 2 Revision 2.0

Micrel Inc. MICRF221 (1) (2) Absolute Maximum Ratings Operating Ratings Supply Voltage (VDD) ................................................ +5V Supply voltage (VDD) ............................ +3.0V to +3.6V Input Voltage. ............................................................. +5V Ambient Temperature (T ) ................. –40°C to +105°C A Junction Temperature ........................................... +150ºC Input Voltage (Vin) ................................................. 3.6V Lead Temperature (soldering, 10sec.) .................... 300°C Maximum Input RF Power ................................ –20dBm Storage Temperature (Ts) ......................–65ºC to +150°C Receive Modulation Duty Cycle(6) .................... 20~80% Maximum Receiver Input Power ......................... +10dBm EDS Rating(3) ..................................................... 2kV HBM Electrical Characteristics Specifications apply for VDD = 3.3V, VSS = 0V, CAGC = 4.7µF, CTH = 0.1µF, fRX = 850MHz to 950MHz unless otherwise noted. Bold values indicate –40°C - TA - 105°C. Symbol Parameter Condition Min Typ Max Units Iss MICRF221 Operating Continuous Operation, fRX = 868MHz 9.0 mA Supply Current Continuous Operation, fRX = 915MHz 9.5 Ishut Shutdown Current 50 nA RF/IF Section Symbol Parameter Condition Min Typ Max Units Image Rejection 20 dB fRX = 868MHz 1.219 1st IF Center Frequency MHz fRX = 915MHz 1.285 Receiver Sensitivity @ fRX = 868MHz (matched to 50Ω) -109 dBm 1kbps(4) fRX = 915MHz (matched to 50Ω) -109 fRX = 868MHz 360 IF Bandwidth kHz fRX = 915MHz 380 fRX = 868MHz 9.4 – j72 Antenna Input Impedance Ω fRX = 915MHz 9 – j67 Receive Modulation Duty Note 6 20 80 % Cycle SIspoularitoiouns(5 R) everse ANT pin, RSC = 50 Ω -78 dBm AGC Attack / Decay Ratio tATTACK / tDECAY 0.1 TA = 25ºC +/-2 AGC Pin Leakage Current nA TA = +105ºC +/-800 August 12, 2015 3 Revision 2.0

Micrel Inc. MICRF221 Electrical Characteristics (Continued) Reference Oscillator Symbol Parameter Condition Min Typ Max Units Reference Oscillator fRX = 868MHz 13.54856 MHz Frequency fRX = 915MHz 14.27643 Reference Oscillator Input RO1 Pin 1500 kΩ Impedance Time to Data From Shutdown 1 ms Reference Oscillator Input With External Drive 0.5 1.5 Vp-p Range Reference Oscillator RO1 Pin, V(REFOSC) = 0V 380 µA Source Current Auto-polling Operation(7) Symbol Parameter Condition Min Typ Max Units Tsleep Programming 10 1300 ms Range Isleep(8) SLEEP Current 2ms on, 1.3s off 15 µA Demodulator Symbol Parameter Condition Min Typ Max Units CTH Source Impedance Frefosc = 14.27643MHz 100 kΩ TA = 25ºC +/-2 CTH Leakage Current nA TA = +105ºC +/-800 Demodulator Filter Programmable, see application section 1712 13000 Hz Bandwidth @ 915MHz Digital / Control Functions Symbol Parameter Condition Min Typ Max Units Input High Voltage Pins SCLK, DO (as input), SHDN 0.8Vdd V Input Low Voltage Pins SCLK, DO (as input), SHDN 0.2Vdd V Output Voltage High DO 0.8Vdd V Output Voltage Low DO 0.2Vdd V As output, source @ 0.8 VDD 260 DO Pin Output Current µA As output, sink @ 0.2 VDD 600 Output Rise and Fall CI = 15 pF, pin DO, 10-90% 2 µs Times August 12, 2015 4 Revision 2.0

Micrel Inc. MICRF221 Electrical Characteristics (Continued) RSSI Symbol Parameter Condition Min Typ Max Units RSSI DC Output Voltage 0.2 to 2.0 V Range RSSI Response Slope -109dBm to -40dBm 26 mV/dB RSSI Output Impedance 220 Ω Notes: 1. Exceeding the absolute maximum rating may damage the device. 2. The device is not guaranteed to function outside its operating rating. 3. Device is ESD sensitive. Use appropriate ESD precautions. Exceeding the absolute maximum rating may damage the device. 4. Sensitivity is defined as the average signal level measured at the input necessary to achieve 10-2 BER (bit error rate). The input signal is defined as a return-to-zero (RZ) waveform with 50% average duty cycle (Manchester encoded). 5. Spurious reverse isolation represents the spurious component which appears on the RF input pin (ANT), measured into 50Ω with an input RF matching network. 6. When data burst does not contain preamble, duty cycle is defined as total duty cycle, including any “quiet” time between data bursts. When data bursts contain preamble sufficient to charge the slice level on capacitor CTH, then duty cycle is the effective duty cycle of the burst alone. [For example, 100msec burst with 50% duty cycle, and 100msec “quiet” time between bursts). If burst includes preamble, duty cycle isTON/(TON + TOFF)= 50%; without preamble, duty cycle is TON/(TON + TOFF + TQUIET) = 50ms/200ms = 25%. TON is the number of 1’s during the burst time × bit time TOFF = TBURST – TON. 7. Auto-polling refers to power-cycling mode of operation where characteristics of the received signal are used to determine the likelihood of an incoming data signal at the beginning of the Ton period. If there is no signal detected within a period programmable by the user, the user can program the number of bits: 0,2,4,8 that must be good for device to wake up. The time will depend on the data rate. If two bad bits are detected this will cause device to revert to SLEEP. If no bits are detected device will revert to SLEEP in 5ms, 10ms, or 20ms depending on selected demodulator bandwidth. Otherwise, the device remains “On” until commanded into SLEEP by an external source e.g., decoder or microprocessor. This technique minimizes the average Ton time. Refer to Serial Interface and Applications sub-sections for further details. 8. Average SLEEP mode current depends on the SLEEP time programmed and the SLEEP oscillator variation which is ~+/-20% independent of ref osc. August 12, 2015 5 Revision 2.0

Micrel Inc. MICRF221 Typical Characteristics Sensitivity Graphs DC Current Selectivity vs. Frequency vs. Frequency Response 12.0 B) 0.0 d T (mA)1101..00 SITIVITY (--2100..00 N N RE 9.0 SE-30.0 R D U E C 8.0 Z-40.0 C LI D A 7.0 RM-50.0 O N 6.6050 750 850 950 1050 -60.890 90 90 91 91 92 92 93 8 3 8 3 8 3 8 3 FREQUENCY (MHz) FREQUENCY (MHz) AGC Voltage vs. Input Power 2.0 1.9 1.8 V)1.7 E (1.6 G A1.5 T L1.4 O V1.3 1.2 1.1 1.0 -130 -80 -30 20 POWER (dBm) August 12, 2015 6 Revision 2.0

Micrel Inc. MICRF221 Functional Diagram CAGC DOWNCUOHVFERTER COLONGTRICOL DESENSE COANGTCROL MIXER LNA -f f IF AMP DETECTOR RSSI RSSI MIXER i fLO RFIMEILJATEGECERT COLONTGRICOL PROGRAMMABLE DEMOODOUKLATOR FILTER SYNTHESIZER SLICER DO' BITCHECK SLEEP SLEEP DO OSCILLATOR TIMER WAKE-UP SQUELCH CTH AUTOPOLL SLICE DO' CONTROL LEVEL DO LOGIC ORSECFEILRLEANTOCRE COLONTGRICOL REFERENCE AND CONTROL Figure 2. Simplified Block Diagram Functional Description Receiver Operation The simplified block diagram, shown in Figure 3, UHF Downconverter illustrates the basic structure of the MICRF221 receiver. It is made of four sub-blocks: The UHF down-converter has six components: LNA, mixers, synthesizer, image reject filter, band pass filter • UHF Down-converter and IF amp. • OOK Demodulator • Reference and Control logic LNA • Auto-poll circuitry. The RF input signal is AC-coupled into the gate circuit of the grounded source LNA input stage. The LNA is a Cascoded NMOS amplifier. The amplified RF signal is Outside the device, the MICRF221 receiver requires then fed to the RF ports of two double balanced just three components to operate: two capacitors mixers. (CTH, and CAGC) and the reference frequency device (usually a quartz crystal). An additional five components are used to improve performance: a power supply decoupling capacitor, two components for the matching network, and two components for the pre-selector band-pass filter. August 12, 2015 7 Revision 2.0

Micrel Inc. MICRF221 pins SEL0 and SEL1, or via serial programming Mixers and Synthesizer through register D3 and D4 The LO port of the mixers are driven by quadrature local oscillators of the synthesizer block. The synthesizer block produces the local oscillator signal D3 D4 Demod BW (@ 915MHz) SEL0 SEL1 on the low side of the desired RF signal with suppression of the image frequency, at twice the IF 0 0 1625Hz frequency below the wanted signal. The local 1 0 3250Hz oscillator is set to 64 times the crystal reference 0 1 6500Hz frequency by way of a phase locked loop synthesizer with a fully integrated loop filter. 1 1 13000Hz - default Image Reject Filter and Band-Pass Filter The IF ports of the mixer produce quadrature down- Slicer and Slicing Level converted IF signals. The IF signal is filtered by the The signal prior to the slicer is still AM. The data slicer image reject filter to remove image frequency converts the AM signal into ones and zeros based components and then follow up with a third order upon the threshold voltage built up in the CTH band-pass filter. The IF center frequency is capacitor. After the slicer, the signal is ASK or OOK 1.285MHz. The IF BW is 380kHz @ 915MHz, and the digital data. IF BW varies with RF operating frequency. The IF BW The slicing threshold defaults at 50%. The slicing can be calculated via direct scaling. threshold can be set via serial programming through register D5 and D6. BWIF = BWIF@ 915MHz × (Oper. Freq (MHz) ÷ 915) D5 D6 Slicing Level 1 0 Slice Level 30% These filters are fully integrated inside the MICRF221. 0 1 Slice Level 40% After filtering, four active gain controlled amplifier 1 1 Slice Level 50% - default stages enhance the IF signal to proper level for 0 0 Slice Level 60% demodulation. OOK Demodulator AGC The demodulator section is comprised of detector, AGC monitors the signal amplitude from the output of programmable low pass filter, slicer, and AGC. the programmable low-pass filter. When the output signal is less than 750mV threshold, AGC increases Detector and Programmable Low-Pass Filter the gain of the mixer and the IF amplifier. When the The demodulation starts with the detector removing output signal is greater than 750mV, the AGC lowers the carrier from the IF signal. Post detection, the the gain of the mixer and the IF amplifier. signal becomes baseband information. The programmable low-pass filter further enhances the baseband information. There are four settings for programmable low-pass filter BW options: 1625Hz, 3250Hz, 6500Hz, 13000Hz. for 915MHz operation. Low pass filter BW will vary with RF Operating Frequency. Filter BW values can easily calculated by direct scaling. See equation below for filter BW calculation: BWOperFreq = BW@915MHz × (Oper. Freq (MHz) ÷ 915) It is very important to choose filter setting that fits best for the intended data rate to minimize data distortion. Demod BW is set at 13000Hz @ 915MHz as default (assuming both SEL0 and SEL1 pins are floating). The low pass filter can be hardware set by external August 12, 2015 8 Revision 2.0

Micrel Inc. MICRF221 Reference Control The reference oscillator in the MICRF221 uses a There are two components in the Reference and basic Pierce crystal oscillator configuration with MOS Control sub-block: 1) Reference Oscillator and 2) transconductor to provide negative resistance. Control Logic, Serial Interface and Parallel Inputs. MICRF221 has built-in load capacitors for the crystal oscillator, shown in Figure 4, even though external Reference Oscillator load capacitors are still needed for tuning to the right frequency. RO1 and RO2 are external pins of the RO2 MICRF221 and are to connect to the reference C oscillator crystal. V BIAS R The reference oscillator crystal frequency can be calculated as follows: RO1 C FREF OSC = FRF/(64 + 1.1/12) For 868.35MHz, Figure 4. MICRF221 Reference Oscillator Circuit FREF OSC = 13.54856 MHz For 915MHz FREF OSC = 14.27643 MHz To operate the MICRF221 with minimum offset, crystal frequencies should be specified with 10pF loading capacitance. August 12, 2015 9 Revision 2.0

Micrel Inc. MICRF221 SQUELCH Decode <=4 Data Edge Pulses S Q Good CLK 8 Stage SQUELCH DOUT Shift Register Disables DO Edge D Detector Window >=7 CLK Counter R Good CLK Decode Decode Good Bad Bits Bit Count Window Decode Good Bit QA1 Bad Bit Returns to D7 D8 SLEEP Select 0, 2, 4, 8 Good CLK Bits BeforeWakeup WATCHDOG Timer Auto Poll WAKEUP Timer (300µs) S R D15 = 0 for Normal Operation Serial Control Register D15 D15 = 1 forAuto Polled Operation Figure 3. MICRF221 Autopoll-Bitcheck-Block Diagram Auto-Polling The auto-poll block (Figure 4) contains a low power must also be set to match the data period. The oscillator to drive the sleep timer when the rest of the default shortest window time gives the least critical device is powered down, plus circuits to check bitcheck action. For better discrimination, the window whether the received bits are good. Auto-polling is setting may be increased up towards the normal controlled by bit D15 in the serial register, in minimum time expected between data edges. Note conjunction with bits D12,13,14 to set the sleep timer that a window time set longer than this will result in all period. Bits D7, D8, are used for control of the bits being tested as bad and the device will remain in bitchecking operation and bits D9, D10, D11 are used sleep polling mode. Now when the serial command is to adjust the sensitivity of the bitcheck action. sent to set bit D15 high the device will go to sleep for For simple auto-polling without bitchecking, send a the timer period, then will start to receive and check serial command with bit 15 set high and bits D12, bits. The device will output data again at DO as soon D13, D14 set to the desired sleep time. The device as the programmed number of good RTZ bits have will go to sleep for the programmed timer duration been received. If a bad bit is seen the device will then wake up to receive data if present. Device will return to sleep mode and poll again for good data stay awake until serial bit D15 is set low then set high after the timeout period. Both high and low periods again to enable a further sleep period. Sleep duty are checked for each RTZ bit. If data transitions are cycle may be controlled by the timing of serial not received the device will return to sleep after the commands. bitcheck watchdog timeout period unless bit D18 has been sent, in which case the device will continue to For polling with bitchecking the serial register bits check bits until sufficient good bits enable the device D7and D8 need to be set for the number of bits to be to wake up, or bad bits return the device to sleep. checked as good, before the receiver outputs data at the DO pin. The bitcheck window bits D9, D10, D11 August 12, 2015 10 Revision 2.0

Micrel Inc. MICRF221 (915MHz) Operation 0 0 0 67µs, 136µs, 270µs, 541µs Trigger pulses are generated from internal D0 edges 1 0 0 64µs, 126µs, 252µs, 505µs and compare with programmable window generated 0 1 0 59µs, 118µs, 234µs, 469µs from the reference clock frequency. If time between 1 1 0 54µs, 108µs, 216µs, 434µs data edges falls within the window data pulse width is 0 0 1 49µs, 100µs, 198µs, 397µs bad. Detected stable bits are counted. Wakeup will 1 0 1 45µs, 90µs, 180µs, 361µs occur allowing data to output if sufficient data bits are 0 1 1 41µs, 82µs, 163µs, 325µs detected. Two bad pulses or lack of pulse cause 1 1 1 36µs, 72µs, 144µs, 289µs device to go to sleep for sleep timer duration. MODE: D12 D13 D14 Sleep Time 0 0 0 10ms Serial Interface 1 0 0 20ms 0 1 0 40ms Control Register Individual Truth Tables: 1 1 0 80ms D0 D1 D2 MODE: Desense 0 0 1 160ms 0 X X No Desense - default 1 0 1 320ms 1 0 0 Not recommended for use 0 1 1 640ms 1 1 0 Not recommended for use 1 1 1 1280ms 1 0 1 Not recommended for use 1 1 1 Not recommended for use D15 MODE: Auto Poll 0 Awake – does not poll - default MODE: 1 Auto-polls with Sleep periods D3 D4 Demod Bandwidth (at 915MHz) 0 0 1625Hz D16 MODE: Demod BW Select 1 0 3250Hz 0 Normal Demod BW’s - default 0 1 6500Hz 1 Fast Demod BW’s 1 1 13000Hz - default D17 D5 D6 MODE 0 Squelch circuit off - default 1 0 Slice Level 30% 1 Should not be used 0 1 Slice Level 40% 1 1 Slice Level 50% - default 0 0 Slice Level 60% D18 MODE Sleep polling watchdog active - default Watchdog time for D3, D4, BW setting: D7 D8 MODE: Bit Check Setting 0 11 01 10 00 0 0 Bitcheck 0 bits - default 5ms 5ms 10ms 20ms 1 0 Bitcheck 2 bits Sleep polling watchdog disabled - unlimited 0 1 Bitcheck 4 bits 1 poll period 1 1 Bitcheck 8 bits D19 MODE 0 RSSI offset 0mV - default MODE: 1 RSSI offset +200mV D9 D10 D11 Bitcheck Window Times August 12, 2015 11 Revision 2.0

Micrel Inc. MICRF221 Application Information Figure 4 – QR221BPF Application Example, 915.0 MHz The MICRF221 receiver can be fully tested by using Table 2 shows the most used frequency values. one of the many evaluation boards designed at Micrel for this device. As an entry level, the QR221BPF Freq (MHz) C8 (pF) L1(nH) (Figure 5) offers a good start for most applications. It has a connector for a whip antenna (ANT1), a band- 868.35 2.7 12 pass filter front end (L1 & C8) as a pre-selector filter, 915.0 2.7 11 and a matching network (C3 & L2). It also includes the 916.5 2.7 11 minimum components required to make the device work, which are: a crystal, C , and C capacitors. AGC TH An RF connector (J2) can be used instead of the whip Table 2. Band-Pass-Filter Front-End Values antenna when tests require an RF signal generator. Figure 5 shows the entire schematic for 915.0MHz. There is no need for the band-pass filter front end in Other frequencies can be used. The values needed applications where it is proven that the outside band for the various components are listed in the tables noise does not cause a problem. The MICRF221 below. receiver incorporates image reject mixers that improve L1 and C8 form the pass-band filter front end. Its the selectivity and rejection of outside band noise purpose is to attenuate undesired outside band noise significantly. which reduces the receiver performance. It is calculated by the parallel resonance equation f = 1/(2×PI×(SQRT L1×C8)) August 12, 2015 12 Revision 2.0

Micrel Inc. MICRF221 Matching Calculations Capacitor C3 and inductor L2 form the L-shaped matching network. The capacitor provides additional attenuation for low frequency outside band noise and the inductor provides additional ESD protection for the antenna pin. Two methods can be used to find these values, which are matched close to 50Ω. One method calculates the values using the equations below, and another by using a Smith chart. The Smith chart is made easier by using software that plots the values of the components C3 and L2, such as WinSmith by Noble Publishing. To calculate matching values, you need to know the input impedance of the device. Table 3 shows the input impedance of the MICRF221 receiver and suggested matching values for the most used frequencies. These suggested values may be different if your layout is different from the layout for the QR221BPF evaluation board. Freq (MHz) C3 (pF) L2(nH) Z device (Ω) 868.35 1.2 9.5, Coilcraft 9.4-j71.8 Figure 5. Device’s Input Impedance, Z = 9.0 – j67.4Ω 915.0 1.2 8.7, Coilcraft 9.0-j67.4 Because stray parasitic elements can be caused by 916.5 1.2 8.7, Coilcraft 8.5-j68.0 both the printed circuit board as well as the components themselves, the values plotted are Table 3. Matching Values for the Most Used slightly different from the calculated ones. Therefore, Frequencies one plots the shunt inductor (8.7nH, from Coilcraft) and the series capacitor (1.2pF) for the desired input For the frequency of 915.0MHz, the input impedance impedance (Figure 7). One can then see the matching is Z = 9.0-j67.4Ω. The matching components are leading to the center of the Smith Chart or close to calculated by: 50Ω. Equivalent parallel = B = 1/Z = 1.95 + j14.6 msiemens Rp = 1 / Re (B); Xp = 1 / Im (B) Rp = 513Ω; Xp = 68.5Ω Q = SQRT (Rp/50 + 1) Q = 3.35 Xm = Rp / Q Xm = 153.1Ω Resonance Method For L-shape Matching Network: Lc = Xp / (2×Pi×f); Lp = Xm / (2×Pi×f) L2 = (Lc×Lp) / (Lc + Lp); C3 = 1 / (2×Pi×f×Xm) L2 = 8.2nH C3 = 1.14pF Doing the same calculation, example with the Smith Chart, it would appear as follows: First, plot the input impedance of the device (Z = 9.0 – j67.4)Ω @ 915.0MHz.(Figure 6). August 12, 2015 13 Revision 2.0

Micrel Inc. MICRF221 RF Ocsillator Calculation Crystal Y1 is the reference clock for all the device’s internal circuits. Internally, the device has a Pierce Oscillator configuration, requiring the external capacitors, C9 and C10, to adjust the crystal center frequency. The exact values for these capacitors depend on the printed circuit board’s stray capacitance. For example, with a top ground plane or longer traces, the value of these capacitors will be less than 10pF since there will be more stray capacitance. If a different layout from the one presented here is used, the capacitor values are optimized by getting the best sensitivity of the device. Crystal characteristics of 10pF load capacitance, 30ppm, ESR < 200Ω, -40ºC to +105ºC temperature range are desired. Table 4 shows the crystal frequencies and two of Micrel’s approved crystal manufactures (www.hib.com.br or www.abracon.com). Crystal frequency is calculated using: REFOSC = RF Carrier/(64+(1.1/12)) The local oscillator is a low side injection type, so for the 915.0MHz carrier, the local oscillator is calculated by: 64 × REFOSC = RF Local OSC 64 × 14.27643MHz = 913.69MHz That is, its frequency is below the RF carrier frequency and the image frequency is below the LO frequency. See Figure 8. The product of the incoming RF signal and local oscillator signal will yield the IF frequency, which is demodulated by the detector circuits. Image Desired Frequency Signal Figure 6. Plotting the Shunt Inductor and Series Capacitor -f f (MHz) LO Figure 7. Low Side Injection Local Oscillator August 12, 2015 14 Revision 2.0

Micrel Inc. MICRF221 REFOSC (MHz) Carrier (MHz) HIB Part Number Abracon Part Number 13.54856 868.35 SA-13.548560-F-10-H-30-30-X ABLS-13.54860MHz-10-J4Y 14.27643 915.0 SA-14.276430-F-10-H-30-30-X ABLS-14.276430MHz-10-J4Y 14.29983 916.5 SA-14.299830-F-10-H-30-30-X ABLS-14.299830MHz-10-J4Y Table 4. Crystal Frequency and Vendors Part Number Demodulation Bandwidth Calculation JP1 and JP2 are used to select the bandwidth for the data packets and if the data pattern has or does not demodulator. To set the bandwidth correctly, it is have a preamble. See Figure 9 for an example of a necessary to know the shortest pulse width of the data profile. encoded data sent in the transmitter. As shown in the example of the data profile in the Figure 9 below, PW2 PW1PW2 PREAMBLE is shorter than PW1, so PW2 should be used for the demodulator bandwidth calculation which is found by HEADER calculating 0.65/shortest pulse width. After this value 1 2 3 4 5 6 7 8 9 10 is found, the setting should be done according to t1 t2 Table 5. PW2 = NARROWEST PULSE WIDTH t1 & t2 = DATA PERIOD For example, if the pulse period is 100µs, 50% duty cycle, the pulse width will be 50µs: Figure 8. Example of a Data Profile (PW = (100µs × 50%) / 100) For best results C4 and C6 should be optimized for the data pattern used. As the baud rate increases, the capacitor values decrease. Table 6 shows suggested So, a bandwidth of 13kHz would be necessary (0.65 / values for Manchester Encoded data at a 50% duty 50µs). However, if this data stream had a pulse period cycle. with 20% duty cycle, the bandwidth required would be 32.5kHz (0.65 / 20µs), which exceeds the maximum bandwidth of the demodulator circuit. If you try to SEL0 SEL1 Demod. CTH CAGC exceed the maximum bandwidth, the pulse will appear JP1 JP2 BW stretched or wider. (hertz) Short Short 1712 100nF 4.7µF SEL0 SEL1 Demod. Shortest Maximum JP1, JP2, BW Pulse baud rate for Open Short 3425 47nF 2.2µF (hertz) (µsec) 50% Duty D3 D4 Short Open 6850 22nF 1µF Cycle (hertz) Open Open 13700 10nF 0.47µF Short Short 1712 380 1316 Table 6. Suggested C6 (CTH) and C4 (CAGC) Values Open Short 3425 190 2632 Short Open 6850 95 5264 The delay at DO output is dependent upon many factors such as RF signal intensity, data profile, data Open Open 13700 47 10528 rate, C and C capacitor values and outside band Table 5. JP1 and JP2 setting, 915 MHz TH AGC noise. See Figures 10 and Figure 11. This device is capable of higher baud rates when the serial bit D16 is programmed high. More detail is provided on the following pages. Other components used include: C5 is a decoupling capacitor for the VDD line. CTH and CAGC Selection R4 should be referenced to ground when a Capacitors C6 (C ) and C4 (C ) provide time base microcontroller connection is not made and TH AGC reference for the data pattern received. These kept low by the microcontroller when not capacitors are selected according to the data profile, programming the device. pulse duty cycle, dead time between two received R3 is the reference for the shutdown pin August 12, 2015 15 Revision 2.0

Micrel Inc. MICRF221 (SHDN = 0, device is operation), which can value. be removed if that pin is connected to a SCLK Pin microcontroller or an external switch. Serial interface input clock is a CMOS Schmitt input. R1 and R2 form a voltage divider for the AGC pin. A 25kΩ pull-down is present when device is in One can purposely decrease the device sensitivity shutdown mode. See “Programming the Device” by forcing a voltage to this AGC pin. Special care section for timing diagram and functional operation is needed when doing this operation, as an external control of the AGC voltage may vary from SHDN (Shut Down) Pin lot-to-lot and may not work the same for several The shut down pin (SHDN) can be used to save devices. energy. If its level is close to V (SHDN = 1), the DD device will not be in operation. Its DC current 5V Operation consumption is less than 1µA (R3 must be removed). 5-volt operation can be obtained by replacing R5, R6, This input pin is designed with a weak pull-up. The and R7 (0Ω resistors) to R5 = 150Ω, R6 = R7 = 33kΩ. pull-up current is decreased once the input has The 5-volt source must be regulated and guaranteed switched above the threshold level, that is, the device never to exceed 5V. DO is equal to VDD levels. is shut down and progressively decreases to levels Four other pins are worthy of comment. They are the below 1μA. DO, RSSI, SHDN, and SCLK pins. When shut down pin is toggling from high to low (getting out of shut down mode), there is some time DO Pin required for the device to come to steady-state mode The DO pin has a driving capability of 0.4mA. This is and some time needed for data to appear at the DO good enough for most of the logic families ICs on the pin. The actual time required is dependent upon market today. It also works as an input when several factors, such as temperature, the crystal used programming the device for the serial register control and if the there is an external oscillator coupled through C2 with faster startup time. Normally RSSI Pin (assuming the suggested crystal vendors are used), The RSSI pin provides a transfer function of RF signal the preamble data will appear at the DO pin at approximately 1msec time, and 2msec over the intensity versus voltage. It is useful to determine the temperature range of the device. signal-to-noise ratio of the RF link, crude range estimate from the transmitter source and AM demodulation, which requires a low C capacitor AGC T6 T7 BIT TIME0 BIT TIME1 BIT TIME2 SCLK T1 T2 T4 T5 T8 T9 T3 “19” “0” “0” “1” DO AS DO INPUT BITS: D19 D18 D17 OUTPUT Figure 9. Serial Interface Start Sequence August 12, 2015 16 Revision 2.0

Micrel Inc. MICRF221 When using an external oscillator or reference SCLK low, then high while DO is low, followed by oscillator signal, the maximum level should not taking DO high, then low while SCLK is high. The exceed 1.5VPP. See Figure 12. Channel 4 is the serial interface is initialized and ready to receive the transmitted data, which is synchronized with the programming data. shutdown shown in the oscilloscope (channel 2). Data Bits are serially programmed starting with the most out is shown on channel 1 and, as seen below, the significant bit (MSB = D19) if all bits are being preamble data starts to appear just over 1ms after the programmed until the least significant bit (LSB =D0) shutdown pin cycle low to high. For instance, if only the bits D0, D1, and D2 are being programmed, then these are the only bits that need to be programmed with the start sequence D2, D1, D0, plus the stop sequence. Or, if only the bit D17 is needed, then the sequence must be from start sequence, D17 through D0 plus the stop sequence, making sure the other bits (besides D17) are programmed as needed. It is recommended that all parallel input pins (SEL0, SEL1, and SQ) be kept high when using the serial interface. After the programming bits are finished, a stop sequence (as shown in Figure 14) is required to end the mode and make the DO pin as an output again. To do so, the SCLK pin is kept high while the DO pin changes from low to high, then low again, followed by the SCLK pin made low. Timing of the programming bits are not critical, but should be kept as shown below: T1 < 0.1µs, Time from SCLK to convert DO to input pin Figure 10. Time-to-Preamble Data after Shut Down Cycle, Room Temperature T6 > 0.1 us, SCLK high time T7 > 0.1 us, SCLK low time Programming the Device T2, T3, T4, T5, T8, T9, T10 > 0.1 us Several additional functions are available by the serial interface. They are: BIT TIME 18 BIT TIME 19 • Desense, not recommended for use SCLK T10 • Slice Level, to further optimize data “1” “0” “1” DO profile demodulation D1 DO DO PIN AS OUTPUT • Autopoll Mode, to wake an external Figure 14. Serial Interface Stop Sequence device through the DO pin toggling from low to data • High Demodulator Bandwidth, for faster baud rates • Parallel input pins SEL0, and SEL1, can be programmed using the serial interface Programming the device is accomplished by the use of pins DO and SCLK. Normally, pin 10 (DO) is outputting data and needs to switch to an input pin made by the start sequence, as shown at Figure 13. A high at the SCLK pin tri-states the DO pin, enabling the external drive into the DO pin with an initial low level. The start sequence is completed by taking August 12, 2015 17 Revision 2.0

Micrel Inc. MICRF221 Serial Interface Examples Autopoll example, Figure 18. All bits (D19 through D0) low (channel 1 is the DO pin, D0 = D1 = D2 = 0, no desense and Channel 2 is the SCLK pin), see Figure 15. D3 = D4 = 0, demodulator bandwidth = 1712Hz, 1kHz baud rate, pulse = 500µs, required demodulator bandwidth is 0.65/500µs = 1300Hz D5 = D6 = 1, Slice level = 50% D7 = 0, D8 = 1, bit check = 4 bits. This is the time the device is ON checking for four consecutive valid windows. D9 = D10 = 1, D11 = 0, data rate is 1kHz, (500µs pulses), window set to 433µs (< 500µs) D12 = D13 = 0, D14 = 1, sleep timer set to 160ms, that is, 4 bit is ON and 160ms is OFF. D15 = 1, device is placed in autopoll D16 = 0, normal demodulator bandwidth D17 = 0, Default Figure 15. All bits 0s. D18 = 1, watchdog timer is OFF All bits (D19 through D0) High, Figure 16. D19 = 0, no RSSI offset From MSB to LSB, see Table 7: D19 D18 D17 D16 D15 D14 D13 D12 0 1 0 0 1 1 0 0 D11 D10 D9 D8 D7 D6 D5 0 1 1 1 0 1 1 D4 D3 D2 D1 D0 0 0 0 0 0 Table 7. Auto-poll Example Bit Sequence Figure 16 All bits 1s. Only bits 19 and 18 High, Figure 17. Figure 18. Autopoll example Figure 17 D19 = D18 = 1. August 12, 2015 18 Revision 2.0

Micrel Inc. MICRF221 Important Note To prevent the erroneous startup, a simple RC A few customers have reported that some MICRF221 network is recommended. The 10Ω resistor and the receiver do not start up correctly. When the issue 4.7µF capacitor provide a delay of about 200µs occurs, DO either chatters or stays at low voltage between VDD and SHDN during power up, thus level. An unusual operating current is observed and ensuring the part enters shutdown stage before the the part cannot receive or demodulate data even part is actually turned on. The 2.2µF capacitor when a strong OOK signal is present. bootstraps the voltage on SHDN, ensuring that SHDN voltage leads the supply voltage on VDD during power Micrel has confirmed that this is the symptom of up. This gives the POR circuit time to set internal incorrect power on reset (POR) of internal register register bits. The SHDN pin can be brought low to bits. The MICRF221 is designed to start up in turn the chip on once the initialization is completed. shutdown mode (SHDN pin must be in logic high The 2.2µF and 100kΩ network form a RC delay of during Vdd ramp up). When the SHDN pin is tied to about 200ms before the SHDN pin is brought to low GND, and if the supply is ramped up slowly, a “test again. The 100kΩ resistor discharges the SHDN pin to bus pull down” circuit may be activated. Once the turn the chip on. chip enters this mode, the POR does not have the chance to set register bits (and hence operating modes) correctly. The test bus pull down acts on the SHDN pin, and can be illustrated in the following diagram. VDD pin 3.3V MICRF2XX 10 ohm (Vdd) pin MICRF2XX Bias 4.7uF control & POR 2.2uF TeCsirtc Muiotsde Cphcioannn agnneed ct thVioed ndSs Hp tDionN SHDN pin Test Bus (SHDN) pin (SHDN) pin 100K prevTehnitsi ndge vPiOceR t furronms osent,t ing operating modes correctly The suggestion provided above will generally serve to prevent the startup issue from happening to the MICRF221 series ASK receiver. However, exact values of the RC network depend on the ramp rate of the supply voltage, and should be determined on a case-by-case basis. August 12, 2015 19 Revision 2.0

Micrel Inc. MICRF221 PCB Layout Recommendations Figures 19 to 22 show some of the printed circuit must be solid and, if possible, without interruptions. layers for the QR221BPF board, refer to Figure 5. Use Avoid a ground plane on the top layer next to the the Gerber files provided (downloadable from the matching element, as it will normally add additional Micrel website at: www.micrel.com), which have the stray capacitance, which changes the matching. remaining layers needed to fabricate this board. When Do not use phenolic material; use only FR4 or better copying or making one’s own boards, make traces as materials, since phenolic material is conductive above short as possible. Long traces alter the matching 200MHz. network and the values suggested are no longer valid. The RF path should be as straight as possible, Suggested Matching Values may vary due to PCB avoiding loops and unnecessary turns. variations. A PCB trace 100 mills (2.5mm) long has about 1.1nH inductance. Separate the ground and VDD lines from other circuits (microcontroller, etc). Optimization should always be done with exhaustive range tests. Known sources of noise should be positioned as far as possible from the RF circuits. Make individual ground connections to the ground plane with a VIA for each ground connection. Do not Avoid thick traces. The higher the frequency, the share VIAs with ground connections. Each ground thinner the trace should be to minimize losses in the connection = one or more VIAs. The ground plane RF path. Figure 19. QR221BPF Top Layer Figure 20. QR221BPF Bottom Layer, Mirror Image August 12, 2015 20 Revision 2.0

Micrel Inc. MICRF221 Figure 21. QR221BPF Top Silkscreen Layer Figure 22. QR221BPF Bottom Silkscreen Layer, Mirror Image Figure 23. QR221BPF Dimensions (inches) August 12, 2015 21 Revision 2.0

Micrel Inc. MICRF221 QR221BPF Bill of Materials, 915.0MHz Item Part Number Manufacturer Description Qty. ANT1 50-Ω Ant 78.7mm (3.1 inches) 20 AWG, rigid wire 1 C3 GRM39COG1R2C50 Murata 1.2pF , 0402/0603 1 C4 Murata / Vishay 4.7µF, 0603/0805 1 C6,C5 Murata / Vishay 0.1µF, 0402/0603 2 C8 GRM39COG2R7C50 Murata 2.7pF, 0402/0603 1 C9,C10 GRM39COG100D50 Murata 10pF, 0402/0603 2 C2 GRM39X7R102K50 Murata (np)1nF, 0402/0603, not placed 1 JP1,JP2 Vishay short, 0402/0603, 0Ω resistor 2 JP3,JP4 open, 0402/0603, not placed 2 J1 CON7 1 J2 (np)SMA, not placed 1 L1 0603CS-11NXGB Coilcraft 11nH 2%, 0402/0603 1 L2 0603CS8N7XJB Coilcraft 8.7nH 5%, 0402/0603 1 R1,R2 (np) 0402/0603, not placed 2 R3,R4 Vishay 100kΩ , 0402/0603 2 R5,R6, Vishay 0Ω , 0402/0603 3 R7 Y1 HC49 www.hib.com.br 14.27643MHz Crystal, 10pF load,, 30ppm, -40 to +105 1 operating temperature www.abracon.com U1 MICRF221AYQS Micrel, Inc. 3.3V, QwikRadio® 850MHz to 950MHz Receiver 1 August 12, 2015 22 Revision 2.0

Micrel Inc. MICRF221 QR221BPF Bill of Materials, 916.5 MHz Item Part Number Manufacturer Description Qty. ANT1 50-Ω Ant 78.7mm (3.1 inches) 20 AWG, rigid wire 1 C3 GRM39COG1R2C50 Murata 1.2pF , 0402/0603 1 C4 Murata / Vishay 4.7µF, 0603/0805 1 C6,C5 Murata / Vishay 0.1µF, 0402/0603 2 C8 GRM39COG2R7C50 Murata 2.7pF, 0402/0603 1 C9,C10 GRM39COG100D50 Murata 10pF, 0402/0603 2 C2 GRM39X7R102K50 Murata (np)1nF, 0402/0603, not placed 1 JP1,JP2 Vishay short, 0402/0603, 0Ω resistor 2 JP3,JP4 open, 0402/0603, not placed 2 J1 CON7 1 J2 (np)SMA, not placed 1 L1 0603CS-11NXGB Coilcraft 11nH 2%, 0402/0603 1 L2 0603CS8N7XJB Coilcraft 8.7nH 5%, 0402/0603 1 R1,R2 (np) 0402/0603, not placed 2 R3,R4 Vishay 100kΩ , 0402/0603 2 R5,R6, Vishay 0Ω , 0402/0603 3 R7 Y1 HC49 www.hib.com.br 14.29983MHz Crystal, 10pF load,, 30ppm, -40 to +105 1 operating temperature www.abracon.com U1 MICRF221AYQS Micrel, Inc. 3.3V, QwikRadio® 850MHz to 950MHz Receiver 1 August 12, 2015 23 Revision 2.0

Micrel Inc. MICRF221 QR221BPF Bill of Materials, 868.35 MHz Item Part Number Manufacturer Description Qty. ANT1 50-Ω Ant 83.8mm (3.3 inches) 20 AWG, rigid wire 1 C3 GRM39COG1R2C50 Murata 1.2pF , 0402/0603 1 C4 Murata / Vishay 4.7µF, 0603/0805 1 C6,C5 Murata / Vishay 0.1µF, 0402/0603 2 C8 GRM39COG2R7C50 Murata 2.7pF, 0402/0603 1 C9,C10 GRM39COG100D50 Murata 10pF, 0402/0603 2 C2 GRM39X7R102K50 Murata (np)1nF, 0402/0603, not placed 1 JP1,JP2 Vishay short, 0402/0603, 0Ω resistor 2 JP3,JP4 open, 0402/0603, not placed 2 J1 CON7 1 J2 (np)SMA, not placed 1 L1 0603CS-12NXGB Coilcraft 12nH 2%, 0402/0603 1 L2 0603CS9N5XJB Coilcraft 9.5nH 5%, 0402/0603 1 R1,R2 (np) 0402/0603, not placed 2 R3,R4 Vishay 100kΩ , 0402/0603 2 R5,R6,R7 Vishay 0Ω , 0402/0603 3 Y1 HC49 www.hib.com.br 13.54856MHz Crystal, 10pF load,, 30ppm, -40 to +105 1 operating temperature www.abracon.com U1 MICRF221AYQS Micrel, Inc. 3.3V, QwikRadio® 850MHz to 950MHz Receiver 1 August 12, 2015 24 Revision 2.0

Micrel Inc. MICRF221 (1) Package Information and Recommended Land Pattern QSOP16 Package Type (AQS16) Note: 1. Package information is correct as of the publication date. For updates and most current information, go to www.micrel.com. August 12, 2015 25 Revision 2.0

Micrel Inc. MICRF221 MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com Micrel, Inc. is a leading global manufacturer of IC solutions for the worldwide high performance linear and power, LAN, and timing & communications markets. The Company’s products include advanced mixed-signal, analog & power semiconductors; high-performance communication, clock management, MEMs-based clock oscillators & crystal-less clock generators, Ethernet switches, and physical layer transceiver ICs. Company customers include leading manufacturers of enterprise, consumer, industrial, mobile, telecommunications, automotive, and computer products. Corporation headquarters and state-of-the-art wafer fabrication facilities are located in San Jose, CA, with regional sales and support offices and advanced technology design centers situated throughout the Americas, Europe, and Asia. Additionally, the Company maintains an extensive network of distributors and reps worldwide. Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this datasheet. This information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry, specifications and descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Micrel’s terms and conditions of sale for such products, Micrel assumes no liability whatsoever, and Micrel disclaims any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2008 Micrel, Incorporated. August 12, 2015 26 Revision 2.0

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrel: MICRF221-915 EV M icrochip: MICRF221AYQS MICRF221-915-EV MICRF221-868-EV MICRF221AYQS-TR