MCP795W1X/MCP795W2X Battery-Backed SPI Real-Time Clock/Calendar with Enhanced Features Device Selection Table User Memory EEPROM Protected • 64-Byte Battery-Backed SRAM Part Number (Kbits) EEPROM • 1 Kbit or 2Kbit EEPROM: MCP795W10 1 Blank - Software write-protect MCP795W20 2 Blank - Page write up to 8 bytes MCP795W11 1 EUI-48™ - Endurance: 1M erase/write cycles MCP795W21 2 EUI-48™ • 128-Bit Protected EEPROM Area: MCP795W12 1 EUI-64™ - Robust write unlock sequence - EUI-48™ MAC address (MCP795WX1) MCP795W22 2 EUI-64™ - EUI-64™ MAC address (MCP795WX2) Timekeeping Features Operating Ranges • Real-Time Clock/Calendar (RTCC): - Hours, minutes, seconds, hundredth of • SPI Serial Interface: seconds, day of week, date, month, year - SPI clock rate up to 5MHz - Leap year compensated to 2399 • Temperature Range: - 12/24-hour modes - Industrial (I): -40°C to +85°C • Oscillator for 32.768kHz Crystals: - Optimized for 6-9pF crystals Packages • On-Chip Digital Trimming/Calibration: • 14-Lead SOIC and TSSOP - ±1ppm resolution - ±259ppm range Package Types (not to scale) • Dual Programmable Alarms • Clock Output Function with Selectable Frequency SOIC/TSSOP • Power-Fail Timestamp: - Time logged on switchover to and from Battery mode X1 1 14 VCC Low-Power Features X2 2 13 CLKOUT • Wide Voltage Range: VBAT 3 12 EVHS - Operating voltage range of 1.8V to 3.6V WDO 4 11 EVLS - Backup voltage range of 1.3V to 3.6V • Low Typical Timekeeping Current: IRQ 5 10 SCK - Operating from VCC: 1.2µA at 3.0V CS 6 9 SI - Operating from VBAT: 1.0µA at 3.0V • Automatic Switchover to Battery Backup VSS 7 8 SO Enhanced Features • Programmable Watchdog Timer: - Dedicated output pin - Cleared via SPI bus or EVHS input • Dual Configurable Event Detect Modules: - High-Speed Digital Event Detect for program- mable pulse count detection - Low-Speed Event Detect for programmable switch debouncing  2011-2018 Microchip Technology Inc. DS20002280E-page 1

MCP795W1X/MCP795W2X Description The MCP795WX1 and MCP795WX2 are preprogrammed with EUI-48 and EUI-64 addresses, The MCP795WXX Real-Time Clock/Calendar (RTCC) respectively. Custom programming is also available. tracks time using internal counters for hours, minutes, seconds, hundredth of seconds, days, months, years Two event detect modules are included on the and day of week. Alarms can be configured on all MCP795WXX. The high-speed event detect module counters up to and including months. For usage and will generate an interrupt after a programmable configuration, the MCP795WXX supports SPI number of pulses have been detected. The low-speed communications up to 5MHz. event detect module can be used to debounce The MCP795WXX is designed to operate using a mechanical switches and includes a selectable 32.768kHz tuning fork crystal with external crystal debounce period. load capacitors. On-chip digital trimming can be used The MCP795WXX also features an integrated to adjust for frequency variance caused by crystal Watchdog Timer peripheral. This allows applications to tolerance and temperature. improve system robustness by moving this SRAM and timekeeping circuitry are powered from the functionality outside of the microcontroller. backup supply when main power is lost, allowing the device to maintain accurate time and the SRAM The MCP795WXX has versatile output options. There contents. The times when the device switches over to is a dedicated pin for outputting a selectable frequency the backup supply and when primary power returns square wave or for use as a general purpose output. are both logged by the power-fail timestamp. Additionally, the alarms can be assigned to either the The MCP795WXX features 128 bits of EEPROM Watchdog Timer interrupt output or the event detect which is only writable after an unlock sequence, interrupt output. making it ideal for storing a unique ID or other critical information. FIGURE 1-1: TYPICAL APPLICATION SCHEMATIC VCC VCC VCC 14 VCC 1 CX1 X1 Z H 6 K CS 8 6 7 10 2 32. CX2 SCK X2 9 3 SI VBAT PIC® MCU MCP795WXX VBAT 8 SO 4 MCLR WDO 5 12 IRQ EVHS EVHS 13 11 CLKOUT EVLS EVLS VSS 7  2011-2018 Microchip Technology Inc. DS20002280E-page 2

MCP795W1X/MCP795W2X FIGURE 1-2: BLOCK DIAGRAM VCC Power Control Power-Fail VSS and Switchover Timestamp VBAT CS Control Logic SCK SPI Interface Configuration SI and Addressing SO Hundredth of SRAM EEPROM Seconds X1 Seconds 32.768 kHz Oscillator Clock Divider Minutes X2 Hours Digital Trimming Day of Week Square Wave CLKOUT Output Date Watchdog WDT WDO Timer Output Logic Month Alarms Year EVHS Event Interrupt IRQ Detect Output Logic EVLS  2011-2018 Microchip Technology Inc. DS20002280E-page 3

MCP795W1X/MCP795W2X 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) VCC.............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS...........................................................................................................-0.6V to VCC+1.0V Storage temperature...............................................................................................................................-65°C to +150°C Ambient temperature under bias...............................................................................................................-40°C to +85°C ESD protection on all pins..........................................................................................................................................4 kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-1: DC CHARACTERISTICS Electrical Characteristics: DC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 3.6V Param. Sym. Characteristic Min. Typ.(2) Max. Units Test Conditions No. D1 VIH High-Level Input Voltage 0.7 VCC — VCC + 1 V D2 VIL Low-Level Input Voltage -0.3 — 0.3VCC V VCC2.5V -0.3 — 0.2VCC VCC < 2.5V D3 VOL Low-Level Output Voltage — — 0.4 V IOL = 2.1mA, VCC 2.5V — — 0.2 IOL = 1.0mA, VCC < 2.5V D4 VOH High-Level Output Voltage VCC - 0.5 — — V IOH = -400µA D5 ILI Input Leakage Current — — ±1 µA CS = VCC, VIN = VSS or VCC D6 ILO Output Leakage Current — — ±1 µA CS = VCC, VOUT = VSS or VCC D7 CINT Pin Capacitance — — 7 pF VCC = 3.6V (Note1) (all inputs and outputs) TA = 25°C, f = 1MHz D8 COSC Oscillator Pin Capacitance — 3 — pF Note1 (X1, X2 pins) D9 ICCEERD EEPROM Operating Current — — 3 mA VCC = 3.6V, FCLK = 5MHz SO = Open ICCEEWR 5 mA VCC = 3.6V D10 ICCREAD SRAM/RTCC Operating — — 3 mA VCC = 3.6V, FCLK = 5MHz Current SO = Open ICCWRITE 3 mA VCC = 3.6V, FCLK = 5MHz D11 ICCDAT Vcc Data Retention Current — — 1 µA VCC = 3.6V (oscillator off) Note1: This parameter is not tested but ensured by characterization. 2: Typical measurements taken at room temperature.  2011-2018 Microchip Technology Inc. DS20002280E-page 4

MCP795W1X/MCP795W2X Electrical Characteristics: DC CHARACTERISTICS (Continued) Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 3.6V Param. Sym. Characteristic Min. Typ.(2) Max. Units Test Conditions No. D12 ICCT Timekeeping Current — — 1.2 µA VCC = 1.8V, CS = VCC, EVHS=VSS, EVLS=VSS (Note1) — 1.2 1.8 µA VCC = 3.0V, CS = VCC, EVHS=VSS, EVLS=VSS (Note1) — — 2.6 µA VCC = 3.6V, CS = VCC, EVHS=VSS, EVLS=VSS (Note1) D13 VTRIP Power-Fail Switchover 1.3 1.5 1.7 V Voltage D14 VBAT Backup Supply Voltage 1.3 — 3.6 V Range D15 IBATT Timekeeping Backup Current — — 850 nA VBAT = 1.3V, VCC=VSS (Note1) — 1000 1200 nA VBAT = 3.0V, VCC=VSS (Note1) — — 2300 nA VBAT = 3.6V, VCC=VSS (Note1) D16 IBATDAT VBAT Data-Retention Current — — 850 nA VBAT = 3.6V, VCC = VSS (oscillator off) Note1: This parameter is not tested but ensured by characterization. 2: Typical measurements taken at room temperature.  2011-2018 Microchip Technology Inc. DS20002280E-page 5

MCP795W1X/MCP795W2X TABLE 1-2: AC CHARACTERISTICS Electrical Characteristics: AC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 3.6V Param. Sym. Characteristic Min. Typ. Max. Units Test Conditions No. 1 FCLK Clock Frequency — — 5 MHz 2.5V Vcc  3.6V — — 3 MHz 1.8V Vcc  2.5V 2 TCSS CS Setup Time 100 — — ns 2.5V Vcc  3.6V 150 — — ns 1.8V Vcc  2.5V 3 TCSH CS Hold Time 100 — — ns 2.5V Vcc  3.6V 150 — — ns 1.8V Vcc  2.5V 4 TCSD CS Disable Time 50 — — ns 5 TSU Data Setup Time 20 — — ns 2.5V Vcc  3.6V 30 — — ns 1.8V Vcc  2.5V 6 THD Data Hold Time 40 — — ns 2.5V Vcc  3.6V 50 — — ns 1.8V Vcc  2.5V 7 TR SCK Rise Time — — 100 ns Note1 8 TF SCK Fall Time — — 100 ns Note1 9 THI Clock High Time 100 — — ns 2.5V Vcc  3.6V 150 — — ns 1.8V Vcc  2.5V 10 TLO Clock Low Time 100 — — ns 2.5V Vcc  3.6V 150 — — ns 1.8V Vcc  2.5V 11 TCLD Clock Delay Time 50 — — ns 12 TCLE Clock Enable Time 50 — — ns 13 TV Output Valid from Clock — — 100 ns 2.5V Vcc  3.6V Low — — 160 ns 1.8V Vcc  2.5V 14 THO Output Hold Time 0 — ns Note1 15 TDIS Output Disable Time — — 80 ns 2.5V Vcc  3.6V (Note1) — — 160 ns 1.8V Vcc  2.5V (Note1) 16 TWC Internal Write Cycle Time — — 5 ms Note2 17 TFVCC VCC Fall Time 300 — — µs Note1 18 TRVCC VCC Rise Time 0 — — µs Note1 19 FOSC Oscillator Frequency — 32.768 — kHz 20 TOSF Oscillator Timeout Period — 1 — ms Note1 21 Endurance 1M — — E/W Page Mode, 25°C cycles VCC = 3.6V (Note1 Note1: This parameter is not tested but ensured by characterization. 2: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle is complete.  2011-2018 Microchip Technology Inc. DS20002280E-page 6

MCP795W1X/MCP795W2X FIGURE 1-1: SERIAL INPUT TIMING 4 CS 12 2 11 7 8 3 10 SCK 9 5 6 SI MSB In LSB In High-Impedance SO FIGURE 1-2: SERIAL OUTPUT TIMING CS 9 10 3 SCK 13 15 14 SO MSB Out LSB Out Don’t Care SI FIGURE 1-3: POWER SUPPLY TRANSITION TIMING VCC VTRIP(MAX) VTRIP(MIN) 17 18  2011-2018 Microchip Technology Inc. DS20002280E-page 7

MCP795W1X/MCP795W2X 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data represented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. FIGURE 2-1: TIMEKEEPING BACKUP FIGURE 2-2: TIMEKEEPING CURRENT CURRENT VS. BACKUP VS. SUPPLY VOLTAGE SUPPLY VOLTAGE 1.6 1.8 1.4 1.6 (cid:882)40TA= -40°C (cid:882)40TA= -40°C A)1.2 2855TTAA== 2855°°CC A)1.4 2855TTAA== 2855°°CC µ µ1.2 nt (1.0 nt (1.0 urre0.8 urre0.8 C0.6 C T T 0.6 BAT 0.4 ICC 0.4 I 0.2 0.2 0.0 0.0 1.30 1.60 1.90 2.20 2.50 2.80 3.10 3.40 1.80 2.10 2.40 2.70 3.00 3.30 3.60 VBATVoltage (V) VCCVoltage (V)  2011-2018 Microchip Technology Inc. DS20002280E-page 8

MCP795W1X/MCP795W2X 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table3-1. TABLE 3-1: PIN FUNCTION TABLE 14-pin 14-pin Name Pin Function SOIC TSSOP X1 1 1 Quartz Crystal Input, External Oscillator Input X2 2 2 Quartz Crystal Output VBAT 3 3 Battery Backup Supply Input WDO 4 4 Watchdog Output IRQ 5 5 Interrupt Output CS 6 6 Chip Select Input VSS 7 7 Ground SO 8 8 Serial Data Output SI 9 9 Serial Data Input SCK 10 10 Serial Clock Input EVHS 11 11 High-Speed Event Detect Input EVLS 12 12 Low-Speed Event Detect Input CLKOUT 13 13 Square Wave Clock Output VCC 14 14 Primary Power Supply 3.1 Chip Select (CS) 3.5 Oscillator Input/Output (X1, X2) A low level on this pin selects the device, whereas a These pins are used as the connections for an external high level deselects the device. A nonvolatile memory 32.768 kHz quartz crystal and load capacitors. X1 is the programming cycle which is already initiated or in crystal oscillator input and X2 is the output. The progress will be completed, regardless of the CS input MCP795WXX is designed to allow for the use of signal. When the device is deselected, SO goes into external load capacitors in order to provide additional the high-impedance state, allowing multiple parts to flexibility when choosing external crystals. The share the same SPI bus. After power-up, a high-to-low MCP795WXX is optimized for crystals with a specified transition on CS is required prior to any sequence load capacitance of 6-9pF. being initiated. X1 also serves as the external clock input when the 3.2 Serial Clock (SCK) MCP795WXX is configured to use an external oscilla- tor. This pin is used to synchronize the communication between a master and the MCP795WXX. Instructions, 3.6 Watchdog Output (WDO) addresses or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO This is an output pin for the Watchdog Timer and, pin is updated after the falling edge of the clock input. optionally, the alarms. During normal operation, the pin remains high. If a Watchdog Timer overflow occurs, the 3.3 Serial Input (SI) pin outputs a low pulse. The width of the pulse is user-selectable. This pin is used to transfer data into the device. It If an alarm output is assigned to the WDO pin, then the receives instructions, addresses and data. Data is pin will output a low pulse when the alarm triggers. latched on the rising edge of the serial clock. The WDO pin is an open-drain output and requires a 3.4 Serial Output (SO) pull-up resistor to VCC (typically 10k). This pin may be left floating if not used. This pin is used to transfer data out of the MCP795WXX. During a read cycle, data is shifted out on this pin after the falling edge of the serial clock.  2011-2018 Microchip Technology Inc. DS20002280E-page 9

MCP795W1X/MCP795W2X 3.7 Interrupt Output (IRQ) This is an output pin for the event detect modules and, optionally, the alarms. If an event is detected by either module, then this pin will output a low signal until the interrupt flag has been cleared. If an alarm output is assigned to the IRQ pin, then the pin will output a low signal when the alarm triggers. The pin will remain low until the alarm interrupt flag has been cleared. The IRQ pin is an open-drain output and requires a pull-up resistor to VCC or VBAT (typically 10k). This pin may be left floating if not used. 3.8 Square Wave Clock Output (CLKOUT) This is the output pin for the square wave output function. This pin may be left floating if not used. 3.9 High-Speed Event Detect Input (EVHS) This pin is used as the input for the high-speed event detect module. If the high-speed event detect module is not being used, the EVHS pin should be connected to VCC or VSS. 3.10 Low-Speed Event Detect Input (EVLS) This pin is used as the input for the low-speed event detect module. If the low-speed event detect module is not being used, the EVLS pin should be connected to VCC or VSS. 3.11 Backup Supply (VBAT) This is the input for a backup supply to maintain the RTCC and SRAM registers during the time when VCC is unavailable. Power should be applied to VCC before VBAT. If the battery backup feature is not being used, the VBAT pin should be connected to VSS.  2011-2018 Microchip Technology Inc. DS20002280E-page 10

MCP795W1X/MCP795W2X 4.0 SPI BUS OPERATION The MCP795WXX contains an 8-bit instruction register. The device is accessed via the SI pin, with data being The MCP795WXX is designed to interface directly with clocked in on the rising edge of SCK. The CS pin must the Serial Peripheral Interface (SPI) port of many of be low for the entire operation. today’s popular microcontroller families, including Microchip’s PIC® microcontrollers. It may also interface Table4-1 contains a list of the possible instruction bytes and format for device operation. All instructions, with microcontrollers that do not have a built-in SPI port addresses, and data are transferred MSb first, LSb last. by using discrete I/O lines programmed properly in software to match the SPI protocol. Data (SI) is sampled on the first rising edge of SCK after CS goes low. TABLE 4-1: INSTRUCTION SET SUMMARY Instruction Name Instruction Format Description EEREAD 0000 0011 Read data from EEPROM array beginning at selected address EEWRITE 0000 0010 Write data to EEPROM array beginning at selected address EEWRDI 0000 0100 Reset the write enable latch (disable write operations) EEWREN 0000 0110 Set the write enable latch (enable write operations) SRREAD 0000 0101 Read STATUS register SRWRITE 0000 0001 Write STATUS register READ 0001 0011 Read data from RTCC/SRAM array beginning at selected address WRITE 0001 0010 Write data to RTCC/SRAM array beginning at selected address UNLOCK 0001 0100 Unlock the protected EEPROM block for a write operation IDWRITE 0011 0010 Write data to the protected EEPROM block beginning at selected address IDREAD 0011 0011 Read data from the protected EEPROM block beginning at the selected address CLRWDT 0100 0100 Clear Watchdog Timer CLRRAM 0101 0100 Clear all SRAM data to ‘0’  2011-2018 Microchip Technology Inc. DS20002280E-page 11

MCP795W1X/MCP795W2X 5.0 FUNCTIONAL DESCRIPTION 5.1 Memory Organization The MCP795WXX is a highly-integrated Real-Time The MCP795WXX features four different blocks of Clock/Calendar (RTCC). Using an on-board, memory: the RTCC registers, general purpose SRAM, low-power oscillator, the current time is maintained in 2Kbit EEPROM (1Kbit for the MCP795W1X) with hundredths of seconds, seconds, minutes, hours, day software write-protect, and protected EEPROM. The of week, date, month, and year. The MCP795WXX also RTCC registers and SRAM share the same address features 64 bytes of general purpose SRAM, either space and are accessed through the READ and WRITE 2Kbits (MCP795W2X) or 1Kbit (MCP795W1X) of instructions. The EEPROM region is accessed using EEPROM, and 16 bytes of protected EEPROM. Two the EEREAD and EEWRITE instructions, and the alarm modules allow interrupts to be generated at protected EEPROM is accessed using the IDREAD and specific times with flexible comparison options. Digital IDWRITE instructions. Unused locations are not trimming can be used to compensate for inaccuracies accessible. The MCP795WXX will not respond if the inherent with crystals. Using the backup supply input address is out of range, as shown in the shaded region and an integrated power switch, the MCP795WXX will of the memory maps in Figure5-1 and Figure5-2. automatically switch to backup power when primary The RTCC registers are contained in addresses power is unavailable, allowing the current time and the 0x00-0x1F. Table5-1 shows the detailed RTCC SRAM contents to be maintained. The timestamp register map. There are 64 bytes of user-accessible module captures the time when primary power is lost SRAM, located in the address range 0x20-0x5F. The and when it is restored. The Watchdog Timer module SRAM is a separate block from the RTCC registers. All can be used to reset an application that has become RTCC registers and SRAM locations are maintained unresponsive. The high-speed event detect module while operating from backup power. can be used to detect pulse signals recovered from communication links, while the low-speed event detect module can be used to debounce switches and detect button presses. The RTCC configuration and STATUS registers are used to access all of the modules featured on the MCP795WXX. FIGURE 5-1: MEMORY MAP FOR MCP795W1X RTCC Registers/SRAM EEPROM 0x00 0x00 Time and Date 0x07 0x08 Configuration and Trimming EEPROM (128 Bytes) 0x0B 0x0C Alarm 0 0x11 0x7F 0x12 0x80 Alarm 1 0x17 0x18 Unimplemented; mapped back to 0x00-0x7F Power-Fail/Power-Up Timestamps 0x1F 0x20 0xFF SRAM (64 Bytes) 0x5F Protected EEPROM 0x60 0x00 Protected EEPROM (16 Bytes) EUI-48/EUI-64 Node Address 0x0F Unimplemented; device does not respond 0x10 Unimplemented; device does not respond 0xFF 0xFF  2011-2018 Microchip Technology Inc. DS20002280E-page 12

MCP795W1X/MCP795W2X FIGURE 5-2: MEMORY MAP FOR MCP795W2X RTCC Registers/SRAM EEPROM 0x00 0x00 Time and Date 0x07 0x08 Configuration and Trimming 0x0B 0x0C Alarm 0 0x11 0x12 EEPROM (256 Bytes) Alarm 1 0x17 0x18 Power-Fail/Power-Up Timestamps 0x1F 0x20 0xFF SRAM (64 Bytes) 0x5F Protected EEPROM 0x60 0x00 Protected EEPROM (16 Bytes) EUI-48/EUI-64 Node Address 0x0F Unimplemented; device does not respond 0x10 Unimplemented; device does not respond 0xFF 0xFF  2011-2018 Microchip Technology Inc. DS20002280E-page 13

MCP795W1X/MCP795W2X TABLE 5-1: DETAILED RTCC REGISTER MAP Addr. Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Section5.3 “Timekeeping” 00h RTCHSEC HSECTEN3 HSECTEN2 HSECTEN1 HSECTEN0 HSECONE3 HSECONE2 HSECONE1 HSECONE0 01h RTCSEC ST SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 02h RTCMIN — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 03h RTCHOUR TRIMSIGN 12/24 AM/PM HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 HRTEN1 04h RTCWKDAY — — OSCRUN PWRFAIL VBATEN WKDAY2 WKDAY1 WKDAY0 05h RTCDATE — — DATETEN1 DATETEN0 DATEONE3 DATEONE2 DATEONE1 DATEONE0 06h RTCMTH — — LPYR MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 07h RTCYEAR YRTEN3 YRTEN2 YRTEN1 YRTEN0 YRONE3 YRONE2 YRONE1 YRONE0 08h CONTROL OUT SQWEN ALM1EN ALM0EN EXTOSC CRSTRIM SQWFS1 SQWFS0 09h OSCTRIM TRIMVAL7 TRIMVAL6 TRIMVAL5 TRIMVAL4 TRIMVAL3 TRIMVAL2 TRIMVAL1 TRIMVAL0 Section5.5 “Watchdog Timer” 0Ah WDTCON WDTEN WDTIF WDTDLYEN WDTPWS WDTPS3 WDTPS2 WDTPS1 WDTPS0 Section5.6 “Event Detection” 0Bh EVDTCON EVHIF EVLIF EVHEN EVLEN EVWDTEN EVLPS EVHCS1 EVHCS0 Section5.4 “Alarms” 0Ch ALM0SEC — SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 0Dh ALM0MIN — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 0Eh ALM0HOUR — 12/24(2) AM/PM HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 HRTEN1 0Fh ALM0WKDAY ALM0PIN ALM0MSK2 ALM0MSK1 ALM0MSK0 ALM0IF WKDAY2 WKDAY1 WKDAY0 10h ALM0DATE — — DATETEN1 DATETEN0 DATEONE3 DATEONE2 DATEONE1 DATEONE0 11h ALM0MTH — — — MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 Section5.4 “Alarms” 12h ALM1HSEC HSECTEN3 HSECTEN2 HSECTEN1 HSECTEN0 HSECONE3 HSECONE2 HSECONE1 HSECONE0 13h ALM1SEC — SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 14h ALM1MIN — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 15h ALM1HOUR — 12/24(2) AM/PM HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 HRTEN1 16h ALM1WKDAY ALM1PIN ALM1MSK2 ALM1MSK1 ALM1MSK0 ALM1IF WKDAY2 WKDAY1 WKDAY0 17h ALM1DATE — — DATETEN1 DATETEN0 DATEONE3 DATEONE2 DATEONE1 DATEONE0 Section5.10.1 “Power-Fail Timestamp” Power-Down Timestamp 18h PWRDNMIN — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 19h PWRDNHOUR — 12/24 AM/PM HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 HRTEN1 1Ah PWRDNDATE — — DATETEN1 DATETEN0 DATEONE3 DATEONE2 DATEONE1 DATEONE0 1Bh PWRDNMTH WKDAY2 WKDAY1 WKDAY0 MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 Power-Up Timestamp 1Ch PWRUPMIN — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 1Dh PWRUPHOUR — 12/24 AM/PM HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 HRTEN1 1Eh PWRUPDATE — — DATETEN1 DATETEN0 DATEONE3 DATEONE2 DATEONE1 DATEONE0 1Fh PWRUPMTH WKDAY2 WKDAY1 WKDAY0 MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 Note 1: Grey areas are unimplemented. 2: The 12/24 bits in the ALMxHOUR registers are read-only and reflect the value of the 12/24 bit in the RTCHOUR register.  2011-2018 Microchip Technology Inc. DS20002280E-page 14

MCP795W1X/MCP795W2X 5.2 Oscillator Configurations EQUATION 5-1: LOAD CAPACITANCE CALCULATION The MCP795WXX can be operated in two different oscillator configurations: using an external crystal or C C using an external clock input. CL = -----X---1-------------X---2--+CSTRAY C +C X1 X2 5.2.1 EXTERNAL CRYSTAL The crystal oscillator circuit on the MCP795WXX is Where: designed to operate with a standard 32.768kHz tuning CL = Effective load capacitance fork crystal and matching external load capacitors. C = Capacitor value on X1+COSC X1 By using external load capacitors, the MCP795WXX C = Capacitor value on X2+COSC X2 allows for a wide selection of crystals. Suitable crystals CSTRAY = PCB stray capacitance have a load capacitance (CL) of 6-9pF. Crystals with a load capacitance of 12.5pF are not recommended. Figure5-3 shows the pin connections when using an 5.2.1.2 Layout Considerations external crystal. The oscillator circuit should be placed on the same side of the board as the device. Place the oscillator FIGURE 5-3: CRYSTAL OPERATION circuit close to the respective oscillator pins. The load capacitors should be placed next to the oscillator MCP795WXX itself, on the same side of the board. Use a grounded copper pour around the oscillator X1 circuit to isolate it from surrounding circuits. The CX1 To Internal grounded copper pour should be routed directly to VSS. Logic Do not run any signal traces or power traces inside the Quartz ST ground pour. Also, if using a two-sided board, avoid any Crystal traces on the other side of the board where the crystal is placed. CX2 X2 Layout suggestions are shown in Figure5-4. In-line packages may be handled with a single-sided layout that completely encompasses the oscillator pins. With fine-pitch packages, it is not always possible to Note1: The ST bit must be set to enable the completely surround the pins and components. A crystal oscillator circuit. suitable solution is to tie the broken guard sections to a mirrored ground layer. In all cases, the guard trace(s) 2: Always verify oscillator performance over must be returned to ground. the voltage and temperature range that is expected for the application. For additional information and design guidance on oscillator circuits, please refer to these Microchip 5.2.1.1 Choosing Load Capacitors Application Notes, available at the corporate website (www.microchip.com): CL is the effective load capacitance as seen by the crystal, and includes the physical load capacitors, pin • AN1365, “Recommended Usage of Microchip capacitance, and stray board capacitance. Equation5-1 Serial RTCC Devices” can be used to calculate CL. • AN1519, “Recommended Crystals for Microchip C and C are the external load capacitors. They Stand-Alone Real-Time Clock Calendar Devices” X1 X2 must be chosen to match the selected crystal’s specified load capacitance. Note: If the load capacitance is not correctly matched to the chosen crystal’s specified value, the crystal may give a frequency outside of the crystal manufacturer’s specifications.  2011-2018 Microchip Technology Inc. DS20002280E-page 15

MCP795W1X/MCP795W2X FIGURE 5-4: SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT Single-Sided and In-line Layouts: Fine-Pitch (Dual-Sided) Layouts: Copper Pour Oscillator Top Layer Copper Pour (tied to ground) Crystal (tied to ground) Bottom Layer Copper Pour (tied to ground) X1 X1 CX1 CX1 X2 Oscillator GND Crystal GND CX2 CX2 ` X2 DEVICE PINS DEVICE PINS 5.2.2 EXTERNAL CLOCK INPUT 5.2.3 OSCILLATOR FAILURE STATUS A 32.768 kHz external clock source can be connected The MCP795WXX features an oscillator failure flag, to the X1 pin (Figure5-5). When using this OSCRUN, that indicates whether or not the oscillator is configuration, the X2 pin should be left floating. running. The OSCRUN bit is automatically set after 32 oscillator cycles are detected. If no oscillator cycles are Note: The EXTOSC bit must be set to enable an detected for more than TOSF, then the OSCRUN bit is external clock source. automatically cleared (Figure5-6). This can occur if the oscillator is stopped by clearing the ST bit or due to FIGURE 5-5: EXTERNAL CLOCK INPUT oscillator failure. OPERATION Clock from X1 MCP795WXX Ext. Source FIGURE 5-6: OSCILLATOR FAILURE STATUS TIMING DIAGRAM X1 32 Clock Cycles < TOSF TOSF OSCRUN Bit TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH OSCILLATOR CONFIGURATION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page RTCSEC ST SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 18 RTCWKDAY — — OSCRUN PWRFAIL VBATEN WKDAY2 WKDAY1 WKDAY0 20 CONTROL OUT SQWEN ALM1EN ALM0EN EXTOSC CRSTRIM SQWFS1 SQWFS0 35 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by oscillator configuration.  2011-2018 Microchip Technology Inc. DS20002280E-page 16

MCP795W1X/MCP795W2X 5.3 Timekeeping 5.3.1 DIGIT CARRY RULES The MCP795WXX maintains the current time and date The following list explains which timer values cause a using an external 32.768kHz crystal or clock source. digit carry when there is a rollover: Separate registers are used for tracking hundredths of • Time of day: from 11:59:59.99 PM to 12:00:00.00 seconds, seconds, minutes, hours, day of week, date, AM (12-hour mode) or 23:59:59.99 to 00:00:00.00 month, and year. The MCP795WXX automatically (24-hour mode), with a carry to the Date and adjusts for months with less than 31 days and Weekday fields compensates for leap years from 2001 to 2399. The • Date: carries to the Month field according to year is stored as a two-digit value. Table5-3 Both 12-hour and 24-hour time formats are supported • Weekday: from 7 to 1 with no carry and are selected using the 12/24 bit. • Month: from 12/31 to 01/01 with a carry to the The day of week value counts from 1 to 7, increments Year field at midnight, and the representation is user-defined (i.e., • Year: from 99 to 00 with no carry the MCP795WXX does not require 1 to equal Sunday, etc.). TABLE 5-3: DAY TO MONTH ROLLOVER All time and date values are stored in the registers as SCHEDULE binary-coded decimal (BCD) values. The Month Name Maximum Date MCP795WXX will continue to maintain the time and 01 January 31 date while operating off the backup supply. 02 February 28 or 29(1) When reading from the timekeeping registers, the 03 March 31 registers are buffered to prevent errors due to rollover of counters. The following events cause the buffers to 04 April 30 be updated: 05 May 31 • When a read is initiated from the RTCC registers 06 June 30 (addresses 0x00 to 0x1F) 07 July 31 • During an RTCC register read operation, when 08 August 31 the register address rolls over from 0x1F to 0x00 09 September 30 The timekeeping registers should be read in a single 10 October 31 operation to utilize the on-board buffers and avoid rollover issues. 11 November 30 Note1: Loading invalid values into the time and 12 December 31 date registers will result in undefined Note 1: 29 during leap years, otherwise 28. operation. 5.3.2 GENERATING HUNDREDTH OF 2: To avoid rollover issues when loading SECONDS new time and date values, the oscillator/clock input should be disabled A special algorithm is required to accurately generate by clearing the ST bit for External Crystal hundredth of seconds. The circuitry utilizes the mode and the EXTOSC bit for External 4.096kHz clock signal and counts 41clock pulses Clock Input mode. After waiting for the each for 24 increments of the hundredth of seconds OSCRUN bit to clear, the new values can count. The circuitry then counts 40 clock pulses for the be loaded and the ST or EXTOSC bit can next increment of the hundredth of second count. This then be re-enabled. results in every 25 hundredth of seconds increments equaling exactly 250ms. Long term, the hundredth of seconds frequency will average the desired 100Hz, while jitter is minimized short term. EQUATION 5-2: HUNDREDTH OF SECONDS GENERATION 41 clocks24 counts+40 clocks1 count --------------------------------------------------------------------------------------------------------------- = 250 ms 4,096 Hz  2011-2018 Microchip Technology Inc. DS20002280E-page 17

MCP795W1X/MCP795W2X REGISTER 5-1: RTCHSEC: TIMEKEEPING HUNDREDTH OF SECONDS VALUE REGISTER (ADDRESS 0x00) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 HSECTEN3 HSECTEN2 HSECTEN1 HSECTEN0 HSECONE3 HSECONE2 HSECONE1 HSECONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown bit 7-4 HSECTEN<3:0>: Binary-Coded Decimal Value of Hundredth of Second’s Tens Digit Contains a value from 0 to 9 bit 3-0 HSECONE<3:0>: Binary-Coded Decimal Value of Hundredth of Second’s Ones Digit Contains a value from 0 to 9 REGISTER 5-2: RTCSEC: TIMEKEEPING SECONDS VALUE REGISTER (ADDRESS 0x01) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ST SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown bit 7 ST: Start Oscillator bit 1 = Oscillator enabled 0 = Oscillator disabled bit 6-4 SECTEN<2:0>: Binary-Coded Decimal Value of Second’s Tens Digit Contains a value from 0 to 5 bit 3-0 SECONE<3:0>: Binary-Coded Decimal Value of Second’s Ones Digit Contains a value from 0 to 9 REGISTER 5-3: RTCMIN: TIMEKEEPING MINUTES VALUE REGISTER (ADDRESS 0x02) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-4 MINTEN<2:0>: Binary-Coded Decimal Value of Minute’s Tens Digit Contains a value from 0 to 5 bit 3-0 MINONE<3:0>: Binary-Coded Decimal Value of Minute’s Ones Digit Contains a value from 0 to 9  2011-2018 Microchip Technology Inc. DS20002280E-page 18

MCP795W1X/MCP795W2X REGISTER 5-4: RTCHOUR: TIMEKEEPING HOURS VALUE REGISTER (ADDRESS 0x03) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TRIMSIGN 12/24 AM/PM HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 HRTEN1 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown If 12/24 = 1 (12-hour format): bit 7 TRIMSIGN: Trim Sign bit 1 = Add clocks to correct for slow time 0 = Subtract clocks to correct for fast time bit 6 12/24: 12 or 24 Hour Time Format bit 1 = 12-hour format 0 = 24-hour format bit 5 AM/PM: AM/PM Indicator bit 1 = PM 0 = AM bit 4 HRTEN0: Binary-Coded Decimal Value of Hour’s Tens Digit Contains a value from 0 to 1 bit 3-0 HRONE<3:0>: Binary-Coded Decimal Value of Hour’s Ones Digit Contains a value from 0 to 9 If 12/24 = 0 (24-hour format): bit 7 TRIMSIGN: Trim Sign bit 1 = Add clocks to correct for slow time 0 = Subtract clocks to correct for fast time bit 6 12/24: 12 or 24 Hour Time Format bit 1 = 12-hour format 0 = 24-hour format bit 5-4 HRTEN<1:0>: Binary-Coded Decimal Value of Hour’s Tens Digit Contains a value from 0 to 2. bit 3-0 HRONE<3:0>: Binary-Coded Decimal Value of Hour’s Ones Digit Contains a value from 0 to 9  2011-2018 Microchip Technology Inc. DS20002280E-page 19

MCP795W1X/MCP795W2X REGISTER 5-5: RTCWKDAY: TIMEKEEPING WEEKDAY VALUE REGISTER (ADDRESS 0x04) U-0 U-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 — — OSCRUN PWRFAIL VBATEN WKDAY2 WKDAY1 WKDAY0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5 OSCRUN: Oscillator Status bit 1 = Oscillator is enabled and running 0 = Oscillator has stopped or has been disabled bit 4 PWRFAIL: Power Failure Status bit(1,2) 1 = Primary power was lost and the power-fail timestamp registers have been loaded (must be cleared in software). Clearing this bit resets the power-fail timestamp registers to ‘0’. 0 = Primary power has not been lost bit 3 VBATEN: External Battery Backup Supply (VBAT) Enable bit 1 = VBAT input is enabled 0 = VBAT input is disabled bit 2-0 WKDAY<2:0>: Binary-Coded Decimal Value of Day of Week Contains a value from 1 to 7. The representation is user-defined. Note 1: The PWRFAIL bit must be cleared to log new timestamp data. This is to ensure previous timestamp data is not lost. 2: The PWRFAIL bit can be cleared by writing a ‘0’. Once cleared, the PWRFAIL bit cannot be written to a ‘1’ in software. REGISTER 5-6: RTCDATE: TIMEKEEPING DATE VALUE REGISTER (ADDRESS 0x05) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 — — DATETEN1 DATETEN0 DATEONE3 DATEONE2 DATEONE1 DATEONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DATETEN<1:0>: Binary-Coded Decimal Value of Date’s Tens Digit Contains a value from 0 to 3 bit 3-0 DATEONE<3:0>: Binary-Coded Decimal Value of Date’s Ones Digit Contains a value from 0 to 9  2011-2018 Microchip Technology Inc. DS20002280E-page 20

MCP795W1X/MCP795W2X REGISTER 5-7: RTCMTH: TIMEKEEPING MONTH VALUE REGISTER (ADDRESS 0x06) U-0 U-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 — — LPYR MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5 LPYR: Leap Year bit 1 = Year is a leap year 0 = Year is not a leap year bit 4 MTHTEN0: Binary-Coded Decimal Value of Month’s Tens Digit Contains a value of 0 or 1 bit 3-0 MTHONE<3:0>: Binary-Coded Decimal Value of Month’s Ones Digit Contains a value from 0 to 9 REGISTER 5-8: RTCYEAR: TIMEKEEPING YEAR VALUE REGISTER (ADDRESS 0x07) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 YRTEN3 YRTEN2 YRTEN1 YRTEN0 YRONE3 YRONE2 YRONE1 YRONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown bit 7-4 YRTEN<3:0>: Binary-Coded Decimal Value of Year’s Tens Digit Contains a value from 0 to 9 bit 3-0 YRONE<3:0>: Binary-Coded Decimal Value of Year’s Ones Digit Contains a value from 0 to 9 TABLE 5-4: SUMMARY OF REGISTERS ASSOCIATED WITH TIMEKEEPING Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page RTCHSEC HSECTEN3 HSECTEN2 HSECTEN1 HSECTEN0 HSECONE3 HSECONE2 HSECONE1 HSECONE0 18 RTCSEC ST SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 18 RTCMIN — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 18 RTCHOUR TRIMSIGN 12/24 AM/PM HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 19 HRTEN1 RTCWKDAY — — OSCRUN PWRFAIL VBATEN WKDAY2 WKDAY1 WKDAY0 20 RTCDATE — — DATETEN1 DATETEN0 DATEONE3 DATEONE2 DATEONE1 DATEONE0 20 RTCMTH — — LPYR MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 21 RTCYEAR YRTEN3 YRTEN2 YRTEN1 YRTEN0 YRONE3 YRONE2 YRONE1 YRONE0 21 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used in timekeeping.  2011-2018 Microchip Technology Inc. DS20002280E-page 21

MCP795W1X/MCP795W2X 5.4 Alarms TABLE 5-6: ALARM 1 MASKS The MCP795WXX features two independent alarms. ALM1MSK<2:0> Alarm 1 Asserts on Match of Each alarm can be used to either generate an interrupt 000 Seconds at a specific time in the future, or to generate a periodic 001 Minutes interrupt every second (Alarm 1 only), minute, hour, day, day of week, or month. 010 Hours There is a separate interrupt flag, ALMxIF, for each 011 Day of Week alarm. The interrupt flags are set by hardware when the 100 Date chosen alarm mask condition matches (Table5-5 and 101 Hundredth of Seconds Table5-6). The interrupt flags must be cleared in 110 Reserved software. 111 Seconds, Minutes, Hours, Day of Each alarm can independently be assigned to either Week, and Date the IRQ pin or the WDO pin by configuring theALMxPIN bits. Refer to Section5.8 “Interrupt Outputs” for details. The alarm interrupt output is Note1: The alarm interrupt flags must be cleared available while operating from the backup power by the user. supply, regardless of the output pin assignments. 2: Loading invalid values into the alarm reg- All time and date values are stored in the registers as isters will result in undefined operation. binary-coded decimal (BCD) values. Note: Throughout this section, references to the register and bit names for the alarm modules are referred to generically by the use of ‘x’ in place of the specific module number. Thus, “ALMxSEC” might refer to the seconds register for Alarm 0 or Alarm1. TABLE 5-5: ALARM 0 MASKS ALM0MSK<2:0> Alarm 0 Asserts on Match of 000 Seconds 001 Minutes 010 Hours 011 Day of Week 100 Date 101 Reserved 110 Reserved 111 Seconds, Minutes, Hours, Day of Week, Date, and Month  2011-2018 Microchip Technology Inc. DS20002280E-page 22

MCP795W1X/MCP795W2X FIGURE 5-7: ALARM BLOCK DIAGRAM Timekeeping Alarm 1 Registers Registers Alarm 0 Registers RTCHSEC ALM1HSEC ALM0SEC RTCSEC ALM1SEC ALM0MIN RTCMIN ALM1MIN ALM0HOUR RTCHOUR ALM1HOUR ALM0WKDAY RTCWKDAY ALM1WKDAY ALM0DATE RTCDATE ALM1DATE ALM0MTH RTCMTH Alarm 0 Mask Comparator Comparator Alarm 1 Mask Set Set ALM0IF ALM1IF ALM0MSK<2:0> IRQ ALM1MSK<2:0> Interrupt Output Logic WDO 5.4.1 CONFIGURING THE ALARM In order to configure the alarm modules, the following steps need to be performed: 1. Load the timekeeping registers and enable the oscillator. 2. Configure the ALMxMSK<2:0> bits to select the desired alarm mask. 3. Set or clear the ALMxPIN bit according to the desired output pin assignment. 4. Ensure the ALMxIF flag is cleared. 5. Based on the selected alarm mask, load the alarm match value into the appropriate register(s). 6. Enable the alarm module by setting the ALMxEN bit.  2011-2018 Microchip Technology Inc. DS20002280E-page 23

MCP795W1X/MCP795W2X REGISTER 5-9: ALM1HSEC: ALARM 1 HUNDREDTHS OF SECONDS VALUE REGISTER (ADDRESS 0x12) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 HSECTEN3 HSECTEN2 HSECTEN1 HSECTEN0 HSECONE3 HSECONE2 HSECONE1 HSECONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown bit 7-4 HSECTEN<3:0>: Binary-Coded Decimal Value of Hundredth of Second’s Tens Digit Contains a value from 0 to 9 bit 3-0 HSECONE<3:0>: Binary-Coded Decimal Value of Hundredth of Second’s Ones Digit Contains a value from 0 to 9 Note 1: Hundredth of seconds matching is only available on Alarm 1. REGISTER 5-10: ALMxSEC: ALARM 0/1 SECONDS VALUE REGISTER (ADDRESSES 0x0C/0x13) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-4 SECTEN<2:0>: Binary-Coded Decimal Value of Second’s Tens Digit Contains a value from 0 to 5 bit 3-0 SECONE<3:0>: Binary-Coded Decimal Value of Second’s Ones Digit Contains a value from 0 to 9  2011-2018 Microchip Technology Inc. DS20002280E-page 24

MCP795W1X/MCP795W2X REGISTER 5-11: ALMxMIN: ALARM 0/1 MINUTES VALUE REGISTER (ADDRESSES 0x0D/0x14) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-4 MINTEN<2:0>: Binary-Coded Decimal Value of Minute’s Tens Digit Contains a value from 0 to 5 bit 3-0 MINONE<3:0>: Binary-Coded Decimal Value of Minute’s Ones Digit Contains a value from 0 to 9 REGISTER 5-12: ALMxHOUR: ALARM 0/1 HOURS VALUE REGISTER (ADDRESSES 0x0E/0x15) U-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — 12/24 AM/PM HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 HRTEN1 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown If 12/24 = 1 (12-hour format): bit 7 Unimplemented: Read as ‘0’ bit 6 12/24: 12 or 24 Hour Time Format bit(1) 1 = 12-hour format 0 = 24-hour format bit 5 AM/PM: AM/PM Indicator bit 1 = PM 0 = AM bit 4 HRTEN0: Binary-Coded Decimal Value of Hour’s Tens Digit Contains a value from 0 to 1 bit 3-0 HRONE<3:0>: Binary-Coded Decimal Value of Hour’s Ones Digit Contains a value from 0 to 9 If 12/24 = 0 (24-hour format): bit 7 Unimplemented: Read as ‘0’ bit 6 12/24: 12 or 24 Hour Time Format bit(1) 1 = 12-hour format 0 = 24-hour format bit 5-4 HRTEN<1:0>: Binary-Coded Decimal Value of Hour’s Tens Digit Contains a value from 0 to 2. bit 3-0 HRONE<3:0>: Binary-Coded Decimal Value of Hour’s Ones Digit Contains a value from 0 to 9 Note 1: This bit is read-only and reflects the value of the 12/24 bit in the RTCHOUR register.  2011-2018 Microchip Technology Inc. DS20002280E-page 25

MCP795W1X/MCP795W2X REGISTER 5-13: ALMxWKDAY: ALARM 0/1 WEEKDAY VALUE REGISTER (ADDRESSES 0x0F/0x16) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 ALMxPIN ALMxMSK2 ALMxMSK1 ALMxMSK0 ALMxIF WKDAY2 WKDAY1 WKDAY0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown bit 7 ALMxPIN: Alarm Interrupt Output Pin Assignment bit 1 = Alarm output is assigned to WDO 0 = Alarm output is assigned to IRQ bit 6-4 ALMxMSK<2:0>: Alarm Mask bits 000 = Seconds match 001 = Minutes match 010 = Hours match (logic takes into account 12-/24-hour operation) 011 = Day of week match 100 = Date match 101 = Hundredth of Seconds(1) 110 = Reserved; do not use 111 = Seconds, Minutes, Hour, Day of Week, Date and Month(2) bit 3 ALMxIF: Alarm Interrupt Flag bit(3) 1 = Alarm match occurred (must be cleared in software) 0 = Alarm match did not occur bit 2-0 WKDAY<2:0>: Binary-Coded Decimal Value of Day bits Contains a value from 1 to 7. The representation is user-defined. Note 1: Hundredth of seconds matching is available on Alarm 1 only. This setting is reserved on Alarm 0. 2: Month matching is available on Alarm 0 only. 3: The ALMxIF bit can be cleared by writing a ‘0’. Once cleared, the ALMxIF bit cannot be written to a ‘1’ in software. REGISTER 5-14: ALMxDATE: ALARM 0/1 DATE VALUE REGISTER (ADDRESSES 0x10/0x17) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 — — DATETEN1 DATETEN0 DATEONE3 DATEONE2 DATEONE1 DATEONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DATETEN<1:0>: Binary-Coded Decimal Value of Date’s Tens Digit Contains a value from 0 to 3 bit 3-0 DATEONE<3:0>: Binary-Coded Decimal Value of Date’s Ones Digit Contains a value from 0 to 9  2011-2018 Microchip Technology Inc. DS20002280E-page 26

MCP795W1X/MCP795W2X REGISTER 5-15: ALM0MTH: ALARM 0 MONTH VALUE REGISTER (ADDRESS 0x11) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 — — — MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 MTHTEN0: Binary-Coded Decimal Value of Month’s Tens Digit Contains a value of 0 or 1 bit 3-0 MTHONE<3:0>: Binary-Coded Decimal Value of Month’s Ones Digit Contains a value from 0 to 9 Note 1: Month matching is only available on Alarm 0. TABLE 5-7: SUMMARY OF REGISTERS ASSOCIATED WITH ALARMS Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ALM0SEC — SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 24 ALM0MIN — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 25 ALM0HOUR — 12/24 AM/PM HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 25 HRTEN1 ALM0WKDAY ALM0PIN ALM0MSK2 ALM0MSK1 ALM0MSK0 ALM0IF WKDAY2 WKDAY1 WKDAY0 26 ALM0DATE — — DATETEN1 DATETEN0 DATEONE3 DATEONE2 DATEONE1 DATEONE0 26 ALM0MTH — — — MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 27 ALM1HSEC HSECTEN3 HSECTEN2 HSECTEN1 HSECTEN0 HSECONE3 HSECONE2 HSECONE1 HSECONE0 24 ALM1SEC — SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 24 ALM1MIN — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 25 ALM1HOUR — 12/24 AM/PM HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 25 HRTEN1 ALM1WKDAY ALM1PIN ALM1MSK2 ALM1MSK1 ALM1MSK0 ALM1IF WKDAY2 WKDAY1 WKDAY0 26 ALM1DATE — — DATETEN1 DATETEN0 DATEONE3 DATEONE2 DATEONE1 DATEONE0 26 CONTROL OUT SQWEN ALM1EN ALM0EN EXTOSC CRSTRIM SQWFS1 SQWFS0 35 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by alarms.  2011-2018 Microchip Technology Inc. DS20002280E-page 27

MCP795W1X/MCP795W2X 5.5 Watchdog Timer The WDT interrupt output will operate regardless of whether or not either alarm module interrupt output is The MCP795WXX features a Watchdog Timer (WDT) assigned to the WDO pin. See Section5.8.2 “WDO module that can be used to enhance the robustness of Interrupt Output” for additional details. an application. The WDT continuously counts up toward a specified time-out period. During normal TABLE 5-9: WATCHDOG TIMER OUTPUT operation, the application would clear the WDT before PULSE WIDTH SELECTION it times out. However, if a failure occurs, the application would not clear the WDT, causing it to time out, set the Pulse Width Nominal Pulse WDTPWS WDTIF interrupt flag, and assert the WDO pin low for a (FOSC Cycles) Width(1) specified pulse width. This can then be used to reset 0 4 cycles 122 µs the application and recover from the failure. 1 4,096 cycles 125 ms The WDT time-out period can be configured by setting the WDTPS<3:0> bits according to Table5-8. Setting Note 1: Nominal period assumes FOSC is 32.768kHz. the WDTDLYEN bit will enable a 64-second nominal start-up delay. With this enabled, every time the WDT 5.5.2 CONFIGURING THE WATCHDOG is restarted or cleared, the WDT will wait for 64 seconds TIMER before starting the time-out period. In order to configure the WDT module, the following Once the WDTIF flag has been set due to a WDT steps need to be performed: time-out, the WDTIF flag must be cleared to restart the WDT. 1. Enable the oscillator. The WDT is driven by the oscillator. If the oscillator is 2. Configure the WDTPS<3:0> bits to select the not running, then the WDT time-out will not occur. desired time-out period. 3. If desired, set the WDTDLYEN bit to enable the Note1: The WDT time-out period should only be 64-second start-up delay. changed while the WDT module is 4. Configure the WDTPWS bit to select the desired disabled. output pulse width. 5. Ensure the WDTIF flag is cleared. TABLE 5-8: WATCHDOG TIMER TIME-OUT PERIOD SELECTION 6. Enable the WDT module by setting the WDTEN bit. Nominal Time-out Period WDTPS<3:0> Time-out 5.5.3 CLEARING THE WATCHDOG TIMER (FOSC Cycles) Period(1) The WDT must be cleared before the time-out period 0000 32 cycles 977 µs occurs in order to prevent it from timing out. The WDT 0001 512 cycles 15.6 ms can be cleared using any of the following methods: 0010 2,048 cycles 62.5 ms 1. Executing a CLRWDT instruction. 0011 4,096 cycles 125 ms 2. Toggling the EVHS pin with the EVWDTEN bit set. 0100 32,768 cycles 1 second 3. Disabling/re-enabling the WDT module. 0101 524,288 cycles 16 seconds 4. Clearing the WDTIF flag after it has been set. 0110 1,048,576 cycles 32 seconds 0111 2,097,152 cycles 64 seconds 1xxx Reserved Note 1: Nominal period assumes FOSC is 32.768kHz. 5.5.1 WATCHDOG TIMER INTERRUPT OUTPUT When the WDT times out, the WDTIF interrupt flag gets set and the WDO pin is asserted low for a short pulse. The width of the pulse is determined by the WDTPWS bit according to Table5-9.  2011-2018 Microchip Technology Inc. DS20002280E-page 28

MCP795W1X/MCP795W2X FIGURE 5-8: WATCHDOG TIMER BLOCK DIAGRAM MCP795WXX WDTPS<3:0> 2,097,152 Oscillator FOSC WDT 0111 Block 1,048,576 Counter 0110 524,288 0101 Reset er 32,768 al 0100 X WDT Time Out 0 sc 4,096 U st 0011 M WDTIF 64-sec Start-up Po 2,048 1 0010 WDTEN Delay 512 0001 32 Reset WDTDLYEN 0000 Set WDTIF Clear WDT Output CLRWDT Pulse Gen WDO EVHS EVHS Block WDTPWS  2011-2018 Microchip Technology Inc. DS20002280E-page 29

MCP795W1X/MCP795W2X REGISTER 5-16: WDTCON: WATCHDOG TIMER CONTROL REGISTER (ADDRESS 0x0A) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WDTEN WDTIF WDTDLYEN WDTPWS WDTPS3 WDTPS2 WDTPS1 WDTPS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown bit 7 WDTEN: Watchdog Timer Enable bit(1) 1 = Watchdog Timer enabled 0 = Watchdog Timer disabled bit 6 WDTIF: Watchdog Timer Interrupt Flag bit 1 = Watchdog Timer has timed out (must be cleared in software) 0 = Watchdog Timer has not timed out bit 5 WDTDLYEN: Watchdog Timer Delay Enable bit 1 = Enable 2,097,152 oscillator cycle (64-second nominal) start-up delay before time-out period begins after WDT is reset 0 = Disable start-up delay bit 4 WDTPWS: Watchdog Timer Output Pulse Width Select bit 1 = 4,096 oscillator cycles (125 ms nominal) 0 = 4 oscillator cycles (122 µs nominal) bit 3-0 WDTPS<3:0>: Watchdog Timer Time-out Period Select bits 0000 = 32 oscillator cycles (977 µs nominal) 0001 = 512 oscillator cycles (15.6 ms nominal) 0010 = 2,048 oscillator cycles (62.5 ms nominal) 0011 = 4,096 oscillator cycles (125 ms nominal) 0100 = 32,768 oscillator cycles (1 second nominal) 0101 = 524,288 oscillator cycles (16 second nominal) 0110 = 1,048,576 oscillator cycles (32 second nominal) 0111 = 2,097,152 oscillator cycles (64 second nominal) 1xxx = Reserved; do not use Note 1: The WDTEN bit is automatically cleared when operating from the backup power supply. TABLE 5-10: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page WDTCON WDTEN WDTIF WDTDLYEN WDTPWS WDTPS3 WDTPS2 WDTPS1 WDTPS0 30 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used in Watchdog Timer configuration.  2011-2018 Microchip Technology Inc. DS20002280E-page 30

MCP795W1X/MCP795W2X 5.6 Event Detection If the total number of transitions specified by the EVHCS<1:0> bits do not occur within the time-out The MCP795WXX features two separate event period, then the transition count will be reset and count- detection modules: a high-speed event detect and a ing will start over (Figure5-10). The time-out period is low-speed event detect. The high-speed event detect driven by the oscillator. If the oscillator is not running, can be used to detect signal preambles, while the then the time-out will not occur. low-speed event detect is meant for debouncing mechanical switches. TABLE 5-11: HIGH-SPEED EVENT COUNT The event detection modules are not available while SELECTION operating from the backup power supply. Required Transitions EVHCS<1:0> 5.6.1 HIGH-SPEED EVENT DETECT for Interrupt The high-speed event detect module is designed to 00 1 detect a series of digital transitions (both low-to-high 01 4 and high-to-low) on the EVHS input, and then generate 10 16 an interrupt. The number of transitions required to 11 32 occur is determined by the EVHCS<1:0> bits as shown in Table5-11. Once the specified number of transitions 5.6.1.1 Clearing the WDT Using EVHS have occurred, the EVHIF interrupt flag is set and the IRQ pin is asserted low. The EVHS input can also be used to clear the Watchdog Timer on both low-to-high and high-to-low The high-speed event detect has a time-out period of transitions by setting the EVWDTEN bit. Note that 8,192oscillator cycles (250ms nominal assuming a when this bit is set, the high-speed event detect module 32.768kHz clock frequency). is disabled and the EVHEN bit is ignored. FIGURE 5-9: HIGH-SPEED EVENT DETECT BLOCK DIAGRAM MCP795WXX EVHEN Oscillator FOSC Postscaler Time Out Block 1:8,192 Occurred S Q Reset R Reset Edge Prescaler Interrupt IRQ 0 Detected 1, 4, 16, 32 Set EVHIF Output Logic and EVHS Edge Detect 1 EVHCS<1:0> EVWDTEN Clear WDT FIGURE 5-10: HIGH-SPEED EVENT DETECT WAVEFORM EXAMPLE 1 2 3 4 n-1(1) 1 2 3 4 5 n(1) EVHS 8,192 osc. cycles < 8,192 osc. cycles EVHIF Bit Note 1: ‘n’ refers to the required number of transitions as determined by the EVHCS<1:0> bits.  2011-2018 Microchip Technology Inc. DS20002280E-page 31

MCP795W1X/MCP795W2X 5.6.1.2 Configuring High-Speed Event The low-speed event detect module is driven by the Detect oscillator. If the oscillator is not running, then the debounce period will not expire and the EVLIF flag will In order to configure the high-speed event detect not be set. module, the following steps need to be performed: 1. Enable the oscillator. TABLE 5-12: LOW-SPEED EVENT 2. Configure the EVHCS<1:0> bits to select the DEBOUNCE PERIOD desired number of transitions. SELECTION 3. Ensure the EVWDTEN bit is cleared. Debounce Period Nominal Debounce 4. Ensure the EVHIF flag is cleared. EVLPS (FOSC Cycles) Period(1) 5. Enable the high-speed event detect module by 0 1,024 cycles 31.25 ms setting the EVHEN bit. 1 16,384 cycles 500 ms 5.6.2 LOW-SPEED EVENT DETECT Note 1: Nominal period assumes FOSC is The low-speed event detect module is designed to 32.768kHz. interface directly with mechanical switches to provide a debounced signal. The debounce period is selectable 5.6.2.1 Configuring Low-Speed Event through the EVLPS bit as shown in Table5-12. Low Detect speed events occur when the EVLS input toggles and In order to configure the low-speed event detect remains stable for the selected debounce period. module, the following steps need to be performed: After a transition on the EVLS input, the MCP795WXX 1. Enable the oscillator. will begin counting the debounce period. Either a 2. Configure the EVLPS bit to select the desired high-to-low or a low-to-high transition will initiate debounce period. counting. Once the debounce period has expired, the 3. Ensure the EVLIF flag is cleared. EVLIF flag is set and the IRQ pin is asserted low (Figure5-12). If the EVLS input returns to its original 4. Enable the low-speed event detect module by level before the debounce period expires, then setting the EVLEN bit. counting is aborted and the EVLIF flag will not be set. FIGURE 5-11: LOW-SPEED EVENT DETECT BLOCK DIAGRAM MCP795WXX EVLPS 31.25 ms 0 Set EVLIF Oscillator FOSC Postscaler Postscaler 500 ms Block EVLEN 1:1,024 1:16 1 Reset EVLS Matches Interrupt IRQ EVLS D Q Latched State Output Logic Latch New CK EVLS State FIGURE 5-12: LOW-SPEED EVENT DETECT WAVEFORM EXAMPLE EVLS Debounce Period(1) EVLIF Bit Note 1: The debounce period is determined by the EVLPS bit.  2011-2018 Microchip Technology Inc. DS20002280E-page 32

MCP795W1X/MCP795W2X REGISTER 5-17: EVDTCON: EVENT DETECT CONTROL REGISTER (ADDRESS 0x0B) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EVHIF EVLIF EVHEN EVLEN EVWDTEN EVLPS EVHCS1 EVHCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown bit 7 EVHIF: High-Speed Event Detect Interrupt Flag bit 1 = High-speed event detection occurred (must be cleared in software) 0 = High-speed event detection did not occur bit 6 EVLIF: Low-Speed Event Detect Interrupt Flag bit 1 = Low-speed event detection occurred (must be cleared in software) 0 = Low-speed event detection did not occur bit 5 EVHEN: High-Speed Event Detect Module Enable bit If EVWDTEN = 0: 1 = High-Speed Event Detect enabled 0 = High-Speed Event Detect disabled If EVWDTEN = 1: Unused. bit 4 EVLEN: Low-Speed Event Detect Module Enable bit 1 = Low-Speed Event Detect enabled 0 = Low-Speed Event Detect disabled bit 3 EVWDTEN: EVHS Input WDT Clear Enable bit 1 = Enable Watchdog Timer clear on EVHS input transition. Disables high-speed event detect module. 0 = Disable EVHS input clearing Watchdog Timer. bit 2 EVLPS: Low-Speed Event Detect Debounce Period Select bit 1 = 16,384 oscillator cycles (500 ms nominal) 0 = 1,024 oscillator cycles (31.25 ms nominal) bit 1-0 EVHCS<1:0>: High-Speed Event Detect Transition Count Select bits Selects how many transitions must occur on the EVHS input before an interrupt is triggered 00 = 1 transition 01 = 4 transitions 10 = 16 transitions 11 = 32 transitions TABLE 5-13: SUMMARY OF REGISTERS ASSOCIATED WITH EVENT DETECTION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page EVDTCON EVHIF EVLIF EVHEN EVLEN EVWDTEN EVLPS EVHCS1 EVHCS0 33 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used in event detect configuration.  2011-2018 Microchip Technology Inc. DS20002280E-page 33

MCP795W1X/MCP795W2X 5.7 Clock Output TABLE 5-14: CLKOUT OUTPUT MODES The MCP795WXX features Square Wave Clock Output SQWEN OUT Mode and General Purpose Output modes through the 0 0 Logic Low Output CLKOUT pin. If the SQWEN bit is set, then CLKOUT 0 1 Logic High Output operates in Square Wave Clock Output mode. Otherwise, CLKOUT operates in General Purpose 1 x Square Wave Clock Output Output mode (Table5-14). The CLKOUT pin is disabled while operating from the backup power supply. FIGURE 5-13: CLKOUT OUTPUT BLOCK DIAGRAM MCP795WXX SQWFS<1:0> Oscillator X1 32.768 kHz 11 8.192 kHz X2 EXTOSC DTigriimtal stscaler 4.0961 k HHzz 1001MUX Po 00 0 ST 1 1 CRSTRIM CLKOUT OUT 0 SQWEN 5.7.1 SQUARE WAVE OUTPUT MODE 5.7.2 GENERAL PURPOSE OUTPUT MODE The MCP795WXX can be configured to generate a square wave clock signal on CLKOUT. The input clock If the square wave clock output is disabled, CLKOUT frequency, FOSC, is divided according to the acts as a general purpose output. The output logic level SQWFS<1:0> bits as shown in Table5-15. is controlled by the OUT bit. The square wave output is not available when The general purpose output is not available when operating from the backup power supply. operating from the backup power supply. Note: All of the clock output rates are affected by digital trimming except for the 1:1 postscaler value (SQWFS<1:0> = 11). TABLE 5-15: CLOCK OUTPUT RATES Nominal SQWFS<1:0> Postscaler Frequency 00 1:32,768 1 Hz 01 1:8 4.096 kHz 10 1:4 8.192 kHz 11 1:1 32.768 kHz Note 1: Nominal frequency assumes FOSC is 32.768kHz.  2011-2018 Microchip Technology Inc. DS20002280E-page 34

MCP795W1X/MCP795W2X REGISTER 5-18: CONTROL: RTCC CONTROL REGISTER (ADDRESS 0x08) R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OUT SQWEN ALM1EN ALM0EN EXTOSC CRSTRIM SQWFS1 SQWFS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown bit 7 OUT: Logic Level for General Purpose Output Square Wave Clock Output Mode (SQWEN = 1): Unused. General Purpose Output Mode (SQWEN = 0): 1 = CLKOUT signal level is logic high 0 = CLKOUT signal level is logic low bit 6 SQWEN: Square Wave Output Enable bit 1 = Enable Square Wave Clock Output mode 0 = Disable Square Wave Clock Output mode bit 5 ALM1EN: Alarm 1 Module Enable bit 1 = Alarm 1 enabled 0 = Alarm 1 disabled bit 4 ALM0EN: Alarm 0 Module Enable bit 1 = Alarm 0 enabled 0 = Alarm 0 disabled bit 3 EXTOSC: External Oscillator Input bit 1 = Enable X1 pin to be driven by external 32.768 kHz source 0 = Disable external 32.768 kHz input bit 2 CRSTRIM: Coarse Trim Mode Enable bit Coarse Trim mode results in the MCP795WXX applying digital trimming every second. 1 = Enable Coarse Trim mode. If SQWEN = 1, CLKOUT will output trimmed 1 Hz(1) nominal clock signal. 0 = Disable Coarse Trim mode See Section5.9 “Digital Trimming” for details bit 1-0 SQWFS<1:0>: Square Wave Clock Output Frequency Select bits If SQWEN = 1 and CRSTRIM = 0: Selects frequency of clock output on CLKOUT 00 = 1 Hz(1) 01 = 4.096 kHz(1) 10 = 8.192 kHz(1) 11 = 32.768 kHz If SQWEN = 0 or CRSTRIM = 1: Unused. Note 1: The 8.192 kHz, 4.096 kHz, and 1 Hz square wave clock output frequencies are affected by digital trimming. TABLE 5-16: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK OUTPUT CONFIGURATION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page CONTROL OUT SQWEN ALM1EN ALM0EN EXTOSC CRSTRIM SQWFS1 SQWFS0 35 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used in clock output configuration.  2011-2018 Microchip Technology Inc. DS20002280E-page 35

MCP795W1X/MCP795W2X 5.8 Interrupt Outputs 5.8.2 WDO INTERRUPT OUTPUT The MCP795WXX features interrupt outputs for the If an alarm module is enabled and assigned to the alarm and event detect modules. The alarm interrupt WDO pin, then when the alarm triggers and the output can be assigned to either the IRQ pin or the interrupt flag, ALMxIF, is set, the WDO pin will be WDO pin, based on the setting of the ALMxPIN bit for asserted low for 8 oscillator cycles (244µs nominal each alarm module. Setting ALMxPIN to a ‘1’ assigns assuming a 32.768kHz clock frequency) and then the associated alarm module to the WDO pin and clear- deasserted again. The ALMxIF flag must then be ing ALMxPIN to a ‘0’ assigns the module to the IRQ pin. cleared to rearm the WDO output and allow it to trigger The event detect modules are always assigned to the again upon the next alarm interrupt. IRQ pin. If both alarm modules are enabled and assigned to the Both the IRQ and the WDO pins are active-low. WDO pin, then either module can trigger the WDO output pulse. However, both ALMxIF flags must be 5.8.1 IRQ INTERRUPT OUTPUT cleared for the WDO output to trigger upon the next alarm interrupt. The interrupt outputs of modules that are enabled and assigned to the IRQ pin are OR’d together. If any of the The Watchdog Timer output on the WDO pin is interrupt flags are set, then the IRQ pin will assert low. independent of the alarm modules and will occur In order to deassert the IRQ pin, all of the assigned regardless of the state of the alarm modules and their interrupt flags must be cleared or the modules must be interrupt flags. disabled. The WDO interrupt output is available when operating The IRQ interrupt output is available when operating from the backup power supply. from the backup power supply. FIGURE 5-15: WDO OUTPUT BLOCK FIGURE 5-14: IRQ OUTPUT BLOCK DIAGRAM DIAGRAM ALM0IF ALM0EN ALM0IF ALM0PIN ALM0EN Pulse Gen ALM0PIN ALM1IF ALM1EN ALM1IF ALM1PIN ALM1EN IRQ ALM1PIN EVLIF WDO EVLEN WDT EVHIF Output EVHEN TABLE 5-17: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT OUTPUT CONFIGURATION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page EVDTCON EVHIF EVLIF EVHEN EVLEN EVWDTEN EVLPS EVHCS1 EVHCS0 TBD ALM0WKDAY ALM0PIN ALM0MSK2 ALM0MSK1 ALM0MSK0 ALM0IF WKDAY2 WKDAY1 WKDAY0 26 ALM1WKDAY ALM1PIN ALM1MSK2 ALM1MSK1 ALM1MSK0 ALM1IF WKDAY2 WKDAY1 WKDAY0 26 CONTROL OUT SQWEN ALM1EN ALM0EN EXTOSC CRSTRIM SQWFS1 SQWFS0 35 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used in interrupt output configuration.  2011-2018 Microchip Technology Inc. DS20002280E-page 36

MCP795W1X/MCP795W2X 5.9 Digital Trimming The adjustment occurs once per minute when CRSTRIM=0. The TRIMSIGN bit specifies whether to The MCP795WXX features digital trimming to correct add cycles or to subtract them. The TRIMVAL<7:0> bits for inaccuracies of the external crystal or clock source, are used to specify by how many clock cycles to adjust. up to roughly ±259ppm when CRSTRIM=0. In Each step in the TRIMVAL<7:0> value equates to addition to compensating for intrinsic inaccuracies in adding or subtracting two clock pulses to or from the the clock, this feature can also be used to correct for 32.768kHz clock signal. This results in a correction of error due to temperature variation. This can enable the roughly 1.017ppm per step when CRSTRIM=0. user to achieve high levels of accuracy across a wide Setting TRIMVAL<7:0> to 0x00 disables digital temperature operating range. trimming. Digital trimming consists of the MCP795WXX Digital trimming also occurs while operating off the periodically adding or subtracting clock cycles, backup supply. resulting in small adjustments in the internal timing. REGISTER 5-19: OSCTRIM: OSCILLATOR DIGITAL TRIM REGISTER (ADDRESS 0x09) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TRIMVAL7 TRIMVAL6 TRIMVAL5 TRIMVAL4 TRIMVAL3 TRIMVAL2 TRIMVAL1 TRIMVAL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown bit 7-0 TRIMVAL<7:0>: Oscillator Trim Value bits When CRSTRIM = 0: 11111111 = Add or subtract 510 clock cycles every minute 11111110 = Add or subtract 508 clock cycles every minute • • • 00000010 = Add or subtract 4 clock cycles every minute 00000001 = Add or subtract 2 clock cycles every minute 00000000 = Disable digital trimming When CRSTRIM = 1: 11111111 = Add or subtract 510 clock cycles every second 11111110 = Add or subtract 508 clock cycles every second • • • 00000010 = Add or subtract 4 clock cycles every second 00000001 = Add or subtract 2 clock cycles every second 00000000 = Disable digital trimming  2011-2018 Microchip Technology Inc. DS20002280E-page 37

MCP795W1X/MCP795W2X 5.9.1 CALIBRATION 5.9.1.2 Calibration by Observing Time Deviation In order to perform calibration, the number of error clock pulses per minute must be found and the To calibrate the MCP795WXX by observing the corresponding trim value must be loaded into deviation over time, perform the following steps: TRIMVAL<7:0>. 1. Ensure TRIMVAL<7:0> is reset to 0x00. There are two methods for determining the trim value. 2. Load the timekeeping registers to synchronize The first method involves measuring an output the MCP795WXX with a known-accurate frequency directly and calculating the deviation from reference time. ideal. The second method involves observing the 3. Enable the crystal oscillator or external clock number of seconds gained or lost over a period of time. input by setting the ST bit or EXTOSC bit, Once the OSCTRIM register has been loaded, digital respectively. trimming will automatically occur every minute 4. Observe how many seconds are gained or lost (CRSTRIM=0). over a period of time (larger time periods offer more accuracy). 5.9.1.1 Calibration by Measuring Frequency 5. Calculate the PPM deviation (see Equation5-4). To calibrate the MCP795WXX by measuring the output frequency, perform the following steps: EQUATION 5-4: CALCULATING ERROR 1. Enable the crystal oscillator or external clock PPM input by setting the ST bit or EXTOSC bit, respectively. PPM = S----e---c---D-----e---v---i--a---t--i--o---n--1000000 ExpectedSec 2. Ensure TRIMVAL<7:0> is reset to 0x00. 3. Select an output frequency by setting Where: SQWFS<1:0>. 4. Set SQWEN to enable the square wave output. ExpectedSec = Number of seconds in chosen period SecDeviation = Number of seconds gained or lost 5. Measure the resulting output frequency using a calibrated measurement tool, such as a frequency counter. • If the MCP795WXX has gained time relative to 6. Calculate the number of error clocks per minute the reference clock, then the oscillator is (see Equation5-3). faster than ideal and the TRIMSIGN bit must be cleared. EQUATION 5-3: CALCULATING TRIM • If the MCP795WXX has lost time relative to the VALUE FROM MEASURED reference clock, then the oscillator is slower FREQUENCY than ideal and the TRIMSIGN bit must be set. 6. Calculate the trim value (see Equation5-5). 32768 FIDEAL–FMEAS-------------------60 FIDEAL EQUATION 5-5: CALCULATING TRIM TRIMVAL<7:0> = --------------------------------------------------------------------------------- 2 VALUE FROM ERROR PPM Where: PPM3276860 FIDEAL = Ideal frequency based on SQWFS<1:0> TRIMVAL<7:0> = ------------------------------------------- 10000002 FMEAS = Measured frequency 7. Load the correct value into TRIMVAL<7:0>. • If the number of error clocks per minute is negative, then the oscillator is faster than Note1: Choosing a longer time period for ideal and the TRIMSIGN bit must be cleared. observing deviation will improve • If the number of error clocks per minute is accuracy. positive, then the oscillator is slower than 2: Large temperature variations during the ideal and the TRIMSIGN bit must be set. observation period can skew results. 7. Load the correct value into TRIMVAL<7:0>. Note: Using a lower output frequency and/or averaging the measured frequency over a number of clock pulses will reduce the effects of jitter and improve accuracy.  2011-2018 Microchip Technology Inc. DS20002280E-page 38

MCP795W1X/MCP795W2X 5.9.2 COARSE TRIM MODE By monitoring the CLKOUT output frequency while in this mode, the user can easily observe the When CRSTRIM = 1, Coarse Trim mode is enabled. TRIMVAL<7:0> value affecting the clock timing. While in this mode, the MCP795WXX will apply trimming every second. If SQWEN is set, the CLKOUT pin will output a trimmed 1Hz nominal clock signal. Note1: The 1Hz Coarse Trim mode square wave output is not available while Because trimming is applied every second rather than operating from the backup power supply. every minute, each step of the TRIMVAL<7:0> value has a larger effect on the resulting time deviation and 2: With Coarse Trim mode enabled, the output clock frequency. TRIMVAL<7:0> value has a larger effect on timing. Leaving the mode enabled during normal operation will likely result in inaccurate time. TABLE 5-18: SUMMARY OF REGISTERS ASSOCIATED WITH DIGITAL TRIMMING Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page RTCHOUR TRIMSIGN 12/24 AM/PM HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 19 HRTEN1 CONTROL OUT SQWEN ALM1EN ALM0EN EXTOSC CRSTRIM SQWFS1 SQWFS0 35 OSCTRIM TRIMVAL7 TRIMVAL6 TRIMVAL5 TRIMVAL4 TRIMVAL3 TRIMVAL2 TRIMVAL1 TRIMVAL0 37 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by digital trimming.l  2011-2018 Microchip Technology Inc. DS20002280E-page 39

MCP795W1X/MCP795W2X 5.10 Battery Backup 5.10.1 POWER-FAIL TIMESTAMP The MCP795WXX features a backup power supply The MCP795WXX includes a power-fail timestamp input (VBAT) that can be used to provide power to the module that stores the minutes, hours, date, and month timekeeping circuitry, RTCC registers, and SRAM while when primary power is lost and when it is restored primary power is unavailable. The MCP795WXX will (Figure5-16). The PWRFAIL bit is also set to indicate automatically switch to backup power when VCC falls that a power failure occurred. below VTRIP, and back to VCC when it is above VTRIP. Note: Throughout this section, references to the The VBATEN bit must be set to enable the VBAT input. register and bit names for the Power-Fail Timestamp module are referred to The following functionality is maintained while generically by the use of ‘x’ in place of the operating on backup power: specific module name. Thus, • Timekeeping “PWRxxMIN” might refer to the minutes • Alarms register for power-down or power-up. • Alarm Outputs To utilize the power-fail timestamp feature, a backup • Digital Trimming power supply must be available with the VBAT input • RTCC Register and SRAM Contents enabled, and the oscillator should also be running to ensure accurate functionality. The following features are not available while operating on backup power: Note1: The PWRFAIL bit must be cleared to log • SPI Communication new timestamp data. This is to ensure • Watchdog Timer previous timestamp data is not lost. • Event Detect 2: Clearing the PWRFAIL bit will clear all • Square Wave Clock Output timestamp registers. • General Purpose Output 5.10.1.1 Configuring Battery Backup Note: The Watchdog Timer is automatically In order to configure the battery backup feature, the disabled when primary power is lost and is following steps need to be performed: not automatically re-enabled when power is restored. 1. Enable the oscillator. 2. Wait for the OSCRUN bit to be set, indicating the oscillator has started. 3. Enable battery backup by setting the VBATEN bit. FIGURE 5-16: POWER-FAIL TIMESTAMP TIMING VCC VTRIP Power-Down Power-Up Timestamp Timestamp  2011-2018 Microchip Technology Inc. DS20002280E-page 40

MCP795W1X/MCP795W2X REGISTER 5-20: PWRxxMIN: POWER-DOWN/POWER-UP TIMESTAMP MINUTES VALUE REGISTER (ADDRESSES 0x18/0x1C) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-4 MINTEN<2:0>: Binary-Coded Decimal Value of Minute’s Tens Digit Contains a value from 0 to 5 bit 3-0 MINONE<3:0>: Binary-Coded Decimal Value of Minute’s Ones Digit Contains a value from 0 to 9 REGISTER 5-21: PWRxxHOUR: POWER-DOWN/POWER-UP TIMESTAMP HOURS VALUE REGISTER (ADDRESSES 0x19/0x1D) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — 12/24 AM/PM HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 HRTEN1 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown If 12/24 = 1 (12-hour format): bit 7 Unimplemented: Read as ‘0’ bit 6 12/24: 12 or 24 Hour Time Format bit 1 = 12-hour format 0 = 24-hour format bit 5 AM/PM: AM/PM Indicator bit 1 = PM 0 = AM bit 4 HRTEN0: Binary-Coded Decimal Value of Hour’s Tens Digit Contains a value from 0 to 1 bit 3-0 HRONE<3:0>: Binary-Coded Decimal Value of Hour’s Ones Digit Contains a value from 0 to 9 If 12/24 = 0 (24-hour format): bit 7 Unimplemented: Read as ‘0’ bit 6 12/24: 12 or 24 Hour Time Format bit 1 = 12-hour format 0 = 24-hour format bit 5-4 HRTEN<1:0>: Binary-Coded Decimal Value of Hour’s Tens Digit Contains a value from 0 to 2. bit 3-0 HRONE<3:0>: Binary-Coded Decimal Value of Hour’s Ones Digit Contains a value from 0 to 9  2011-2018 Microchip Technology Inc. DS20002280E-page 41

MCP795W1X/MCP795W2X REGISTER 5-22: PWRxxDATE: POWER-DOWN/POWER-UP TIMESTAMP DATE VALUE REGISTER (ADDRESSES 0x1A/0x1E) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — DATETEN1 DATETEN0 DATEONE3 DATEONE2 DATEONE1 DATEONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DATETEN<1:0>: Binary-Coded Decimal Value of Date’s Tens Digit Contains a value from 0 to 3 bit 3-0 DATEONE<3:0>: Binary-Coded Decimal Value of Date’s Ones Digit Contains a value from 0 to 9 REGISTER 5-23: PWRxxMTH: POWER-DOWN/POWER-UP TIMESTAMP MONTH VALUE REGISTER (ADDRESSES 0x1B/0x1F) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WKDAY2 WKDAY1 WKDAY0 MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown bit 7-5 WKDAY<2:0>: Binary-Coded Decimal Value of Day bits Contains a value from 1 to 7. The representation is user-defined. bit 4 MTHTEN0: Binary-Coded Decimal Value of Month’s Ones Digit Contains a value of 0 or 1 bit 3-0 MTHONE<3:0>: Binary-Coded Decimal Value of Month’s Ones Digit Contains a value from 0 to 9 TABLE 5-19: SUMMARY OF REGISTERS ASSOCIATED WITH BATTERY BACKUP Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page RTCWKDAY — — OSCRUN PWRFAIL VBATEN WKDAY2 WKDAY1 WKDAY0 20 PWRDNMIN — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 41 PWRDNHOUR — 12/24 AM/PM HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 41 HRTEN1 PWRDNDATE — — DATETEN1 DATETEN0 DATEONE3 DATEONE2 DATEONE1 DATEONE0 42 PWRDNMTH WKDAY2 WKDAY1 WKDAY0 MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 42 PWRUPMIN — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 41 PWRUPHOUR — 12/24 AM/PM HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 41 HRTEN1 PWRUPDATE — — DATETEN1 DATETEN0 DATEONE3 DATEONE2 DATEONE1 DATEONE0 42 PWRUPMTH WKDAY2 WKDAY1 WKDAY0 MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 42 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used with battery backup.  2011-2018 Microchip Technology Inc. DS20002280E-page 42

MCP795W1X/MCP795W2X 6.0 ON-BOARD MEMORY There is no limit to the number of bytes that can be written in a single command. However, because the The MCP795W2X has 2Kbits (256 bytes) of RTCC registers and SRAM are separate blocks, writing EEPROM, while the MCP795W1X has 1Kbit past the end of each block will cause the internal (128bytes) of EEPROM. In addition, the devices have Address Pointer to roll over to the beginning of the 16bytes of protected EEPROM for storing crucial same block. Specifically, the Address Pointer will roll information, and 64 bytes of SRAM for general purpose over from 0x1F to 0x00, and from 0x5F to 0x20. usage. The SRAM is retained when the primary power Each data byte is latched into memory as it is received. supply is removed if a backup supply is present and Once all data bytes have been transmitted, CS is enabled. Since the EEPROM is nonvolatile, it does not driven high to end the operation (Figure6-1). require a supply for data retention. Although the SRAM is a separate block from the RTCC 6.1.2 SRAM/RTCC REGISTER READ registers, they are accessed using the same SEQUENCE instructions, READ and WRITE. The EEPROM is The device is selected by pulling CS low. The 8-bit accessed using the EEREAD and EEWRITE READ instruction is transmitted to the MCP795WXX instructions, and the protected EEPROM is accessed followed by an 8-bit address. using the IDREAD and IDWRITE instructions. RTCC and SRAM can be accessed for reads or writes After the READ instruction and address are sent, the immediately after starting an EEPROM write cycle. data stored in the memory at the selected address is shifted out on the SO pin. Data stored in the memory at 6.1 SRAM/RTCC Registers the next address can be read sequentially by continuing to provide clock pulses to the slave. The The RTCC registers are located at addresses 0x00 to internal Address Pointer automatically increments to 0x1F, and the SRAM is located at addresses 0x20 to the next higher address after each byte of data is 0x5F. The SRAM can be accessed while the RTCC shifted out. The Address Pointer allows the entire registers are being internally updated. The SRAM is not memory block to be serially read during one operation. initialized by a Power-on Reset (POR). The read operation is terminated by driving CS high (Figure6-2). Neither the RTCC registers nor the SRAM can be accessed when the device is operating off the backup Because the RTCC registers and SRAM are separate power supply. blocks, reading past the end of each block will cause the Address Pointer to roll over to the beginning of the 6.1.1 SRAM/RTCC REGISTER WRITE same block. Specifically, the Address Pointer will roll SEQUENCE over from 0x1F to 0x00, and from 0x5F to 0x20. The device is selected by pulling CS low. The 8-bit WRITE instruction is transmitted to the MCP795WXX followed by an 8-bit address. Next, the data to be written is transmitted. FIGURE 6-1: SRAM/RTCC WRITE SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCK Instruction Address Byte Data Byte 1 SI 0 0 0 1 0 0 1 0 A7 A6 A5 A4 A3 A2 A1 A0 7 6 5 4 3 2 1 0 CS 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 SCK Data Byte 2 Data Byte 3 Data Byte n SI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0  2011-2018 Microchip Technology Inc. DS20002280E-page 43

MCP795W1X/MCP795W2X FIGURE 6-2: SRAM/RTCC READ SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCK Instruction Address Byte SI 0 0 0 1 0 0 1 1 A7 A6 A5 A4 A3 A2 A1 A0 Data Out High-Impedance SO 7 6 5 4 3 2 1 0 6.1.3 CLEAR SRAM INSTRUCTION The CLRRAM instruction can be used to quickly clear the contents of SRAM to 0x00. The RTCC registers are not affected. The device is selected by pulling CS low. The 8-bit CLRRAM instruction is transmitted to the MCP795WXX followed by an 8-bit dummy data byte. CS is driven high to end the operation (Figure6-3). The value of the data byte is ignored. FIGURE 6-3: CLEAR SRAM SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK Instruction Dummy Data Byte SI 0 1 0 1 0 1 0 0 7 6 5 4 3 2 1 0 High-Impedance SO  2011-2018 Microchip Technology Inc. DS20002280E-page 44

MCP795W1X/MCP795W2X 6.2 STATUS Register The WIP bit indicates whether the MCP795WXX is busy with a nonvolatile memory write operation. When The STATUS register contains the BP<1:0>, WEL and set to a ‘1’, a write is in progress. When set to a ‘0’, no WIP bits. The STATUS register is accessed using the write is in progress. This bit is read-only. SRREAD and SRWRITE instructions. The Block Protection (BP<1:0>) bits are used to set the TABLE 6-1: BLOCK PROTECTION block write protection for the EEPROM array according Array Addresses to Table6-1. These bits are set by the user issuing the BP1 BP0 Write-Protected SRWRITE instruction. These bits are nonvolatile. 0 0 None The Write Enable Latch (WEL) bit indicates the status of the write enable latch. When set to a ‘1’, the latch Upper 1/4 allows writes to the nonvolatile memory, when set to a 0 1 60h-7Fh (MCP795W1X) ‘0’, the latch prohibits writes to the nonvolatile memory. C0h-FFh (MCP795W2X) The state of this bit can be updated via the EEWREN or Upper 1/2 EEWRDI instructions. This bit is read-only. 1 0 40h-7Fh (MCP795W1X) 80h-FFh (MCP795W2X) 1 1 All REGISTER 6-1: STATUS: EEPROM WRITE PROTECTION REGISTER U-0 U-0 U-0 U-0 R/W R/W R-0 R-0 — — — — BP1 BP0 WEL WIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown bit 7-4 Unimplemented: Read as ‘0’ bit 3-2 BP<1:0>: EEPROM Array Block Protection bits Selects which EEPROM region is write-protected 00 = None 01 = Upper 1/4 10 = Upper 1/2 11 = All bit 1 WEL: Write Enable Latch bit Indicates whether or not nonvolatile memory writes are enabled. It is automatically cleared at the end of a nonvolatile memory write cycle. 0 = Writes to nonvolatile memory are not enabled 1 = Writes to nonvolatile memory are enabled bit 0 WIP: Write-In-Process bit Indicates whether or not a nonvolatile memory write cycle is in process 0 = Nonvolatile write cycle is not in process 1 = Nonvolatile write cycle is in process 6.2.1 STATUS REGISTER WRITE After all eight bits of the instruction are transmitted, CS SEQUENCE must be driven high to set the write enable latch. If the write operation is initiated immediately after the The Write Status Register instruction (SRWRITE) EEWREN instruction without CS driven high, data will not allows the user to write to the nonvolatile bits in the be written to the array since the write enable latch was STATUS register. not properly set. The device is selected by pulling CS Prior to any attempt to write data to the STATUS low. The 8-bit SRWRITE instruction is transmitted to the register, the write enable latch must be set by issuing MCP795WXX followed by the 8-bit data byte. CS is the EEWREN instruction. This is done by setting CS low driven high to end the operation and initiate the and then clocking out the proper instruction into the nonvolatile write cycle (Figure6-4). MCP795WXX.  2011-2018 Microchip Technology Inc. DS20002280E-page 45

MCP795W1X/MCP795W2X FIGURE 6-4: WRITE STATUS REGISTER SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK Instruction Data to STATUS Register SI 0 0 0 0 0 0 0 1 7 6 5 4 3 2 1 0 High-Impedance SO 6.2.2 STATUS REGISTER READ The device is selected by pulling CS low. The 8-bit SEQUENCE SRREAD instruction is transmitted to the MCP795WXX. The STATUS register value is then shifted out on the The Read Status Register instruction (SRREAD) SO pin. The read operation is terminated by driving CS provides access to the STATUS register. The STATUS high (Figure6-5). register may be read at any time, even during a write cycle. This allows the user to poll the WIP bit to determine when a write cycle is complete. FIGURE 6-5: READ STATUS REGISTER SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK Instruction SI 0 0 0 0 0 1 0 1 Data from STATUS Register High-Impedance SO 7 6 5 4 3 2 1 0  2011-2018 Microchip Technology Inc. DS20002280E-page 46

MCP795W1X/MCP795W2X 6.3 EEPROM The following is a list of conditions under which the write enable latch will be reset: The MCP795W2X features 2 Kbits of EEPROM, and • Power-up the MCP795W1X features 1Kbit of EEPROM. It is organized in 8-byte pages with software write • WRDI instruction successfully executed protection configurable through the STATUS register. • EEWRITE instruction successfully executed • SRWRITE instruction successfully executed 6.3.1 WRITE ENABLE AND WRITE • IDWRITE instruction successfully executed DISABLE • Unlock sequence for protected EEPROM not The MCP795WXX contains a write enable latch. This followed correctly latch must be set before any write operation will be completed internally. The EEWREN instruction will set the latch, and the EEWRDI instruction will reset the latch. FIGURE 6-6: WRITE ENABLE SEQUENCE CS 0 1 2 3 4 5 6 7 SCK SI 0 0 0 0 0 1 1 0 High-Impedance SO FIGURE 6-7: WRITE DISABLE SEQUENCE CS 0 1 2 3 4 5 6 7 SCK SI 0 0 0 0 0 1 0 0 High-Impedance SO  2011-2018 Microchip Technology Inc. DS20002280E-page 47

MCP795W1X/MCP795W2X 6.3.2 EEPROM READ SEQUENCE Additionally, a page address begins with XXXX x000 and ends with XXXX x111. If the internal address The device is selected by pulling CS low. The 8-bit counter reaches XXXX x111 and clock signals EEREAD instruction is transmitted to the MCP795WXX continue to be applied to the chip, the address counter followed by an 8-bit address. See Figure6-8 for more will roll back to the first address of the page and details. over-write any data that previously existed in those After the correct EEREAD instruction and address are locations. sent, the data stored in the EEPROM at the selected Note: EEPROM write operations are limited to address is shifted out on the SO pin. Data stored in the writing bytes within a single physical page, memory at the next address can be read sequentially regardless of the number of bytes by continuing to provide clock pulses to the slave. The actually being written. Physical page internal Address Pointer automatically increments to boundaries start at addresses that are the next higher address after each byte of data is integer multiples of the page buffer size shifted out. When the highest address is reached, the (or ‘page size’) and, end at addresses that address counter rolls over to address 00h allowing the are integer multiples of page size – 1. If an read cycle to be continued indefinitely. The read operation is terminated by raising the CS pin EEWRITE command attempts to write (Figure6-8). across a physical page boundary, the result is that the data wraps around to the 6.3.3 EEPROM WRITE SEQUENCE beginning of the current page (overwriting data previously stored there), instead of Prior to any attempt to write data to the MCP795WXX being written to the next page as might be EEPROM, the write enable latch must be set by issuing expected. It is therefore necessary for the the EEWREN instruction. This is done by setting CS low application software to prevent EEPROM and then clocking out the proper instruction into the write operations that would attempt to MCP795WXX. After all eight bits of the instruction are cross a page boundary. transmitted, CS must be driven high to set the write enable latch. If the write operation is initiated For the data to be actually written to the array, the CS immediately after the EEWREN instruction without CS must be brought high after the Least Significant bit (D0) driven high, data will not be written to the array since of the nth data byte has been clocked in. If CS is driven the write enable latch was not properly set. high at any other time, the write operation will not be completed. Refer to Figure6-9 and Figure6-10 for After setting the write enable latch, the user may more detailed illustrations on the byte write sequence proceed by driving CS low, issuing an EEWRITE and the page write sequence, respectively. While the instruction, followed by the address, and then the data write is in progress, the STATUS register may be read to be written. Up to eight bytes of data can be sent to to check the status of the WIP, WEL, BP1 and BP0 bits. the device before a write cycle is necessary. The only Attempting to read a memory array location will not be restriction is that all of the bytes must reside in the possible during a write cycle. Polling the WIP bit in the same page. STATUS register is recommended in order to determine if a write cycle is in progress. When the write cycle is completed, the write enable latch is reset. FIGURE 6-8: EEPROM READ SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCK Instruction Address Byte SI 0 0 0 0 0 0 1 1 A7 A6 A5 A4 A3 A2 A1 A0 Data Out High-Impedance SO 7 6 5 4 3 2 1 0  2011-2018 Microchip Technology Inc. DS20002280E-page 48

MCP795W1X/MCP795W2X FIGURE 6-9: EEPROM BYTE WRITE SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Twc SCK Instruction Address Byte Data Byte SI 0 0 0 0 0 0 1 0 A7 A6 A5 A4 A3 A2 A1 A0 7 6 5 4 3 2 1 0 High-Impedance SO FIGURE 6-10: EEPROM PAGE WRITE SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCK Instruction Address Byte Data Byte 1 SI 0 0 0 0 0 0 1 0 A7 A6 A5 A4 A3 A2 A1 A0 7 6 5 4 3 2 1 0 CS 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 SCK Data Byte 2 Data Byte 3 Data Byte n (8 max) SI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 6.4 Protected EEPROM 6.4.1 PROTECTED EEPROM READ SEQUENCE The MCP795WXX features a 128-bit protected EEPROM block, organized as two 8-byte pages, that The device is selected by pulling CS low. The 8-bit requires a special unlock sequence to be followed in IDREAD instruction is transmitted to the MCP795WXX order to write to the memory. The protected EEPROM followed by an 8-bit address. See Figure6-11 for more can be used for storing crucial information such as a details. unique serial number. The MCP795WX1 and After the correct IDREAD instruction and address are MCP795WX2 include an EUI-48 and EUI-64 node sent, the data stored in the protected EEPROM at the address, respectively, preprogrammed into the selected address is shifted out on the SO pin. Data protected EEPROM block. Custom programming is stored in the memory at the next address can be read also available. sequentially by continuing to provide clock pulses to The protected EEPROM block is located at addresses the slave. The internal Address Pointer automatically 0x00 to 0x0F and is accessed using the IDREAD and increments to the next higher address after each byte IDWRITE instructions. of data is shifted out. When the highest address is reached, the address counter rolls over to address 00h Note: Attempts to access addresses outside of allowing the read cycle to be continued indefinitely. The 0x00 to 0x0F will result in the read operation is terminated by raising the CS pin. MCP795WXX ignoring the instruction.  2011-2018 Microchip Technology Inc. DS20002280E-page 49

MCP795W1X/MCP795W2X 6.4.2 PROTECTED EEPROM UNLOCK Note: Protected EEPROM write operations are SEQUENCE limited to writing bytes within a single The protected EEPROM block requires a special physical page, regardless of the number unlock sequence to prevent unintended writes, utilizing of bytes actually being written. Physical the UNLOCK instruction. page boundaries start at addresses that Before performing the unlock sequence, the WEL bit are integer multiples of the page buffer must first be set by executing an EEWREN instruction size (or ‘page size’) and, end at addresses (see Section6.3.1 “Write Enable and Write Disable” that are integer multiples of page size – 1. for details). If an IDWRITE command attempts to write across a physical page boundary, the To unlock the block, the following sequence must be result is that the data wraps around to the followed after setting the WEL bit: beginning of the current page (overwriting 1. Execute an UNLOCK instruction with a data byte data previously stored there), instead of of 0x55 being written to the next page as might be 2. Execute an UNLOCK instruction with a data byte expected. It is therefore necessary for the of 0xAA application software to prevent protected EEPROM write operations that would 3. Write the desired data bytes to the protected attempt to cross a page boundary. EEPROM using the IDWRITE instruction Figure6-12 illustrates the sequence. For the data to be actually written to the array, the CS must be brought high after the Least Significant bit (D0) Note1: Diverging from any step of the unlock of the nth data byte has been clocked in. If CS is driven sequence may result in the EEPROM high at any other time, the write operation will not be remaining locked, the write operation completed. Refer to Figure6-12 for more detailed being ignored, and the WEL bit being illustrations on the page write sequence. While the reset. write is in progress, the STATUS register may be read 2: Unlocking the EEPROM is not required in to check the status of the WIP, WEL, BP1 and BP0 bits. order to read from the memory. Attempting to read a memory array location will not be possible during a write cycle. Polling the WIP bit in the An entire protected EEPROM page does not have to be STATUS register is recommended in order to written in a single operation. However, the block is determine if a write cycle is in progress. When the write locked after each write operation and must be unlocked cycle is completed, the write enable latch is reset. again to start a new Write command. If an attempt is made to write to an address outside of 6.4.3 PROTECTED EEPROM WRITE the 0x00 to 0x0F range, the MCP795WXX will not SEQUENCE execute the WRITE instruction, no data will be written, Prior to any attempt to write data to the MCP795WXX and the device will immediately accept a new protected EEPROM block, the write enable latch must command. be set by issuing the EEWREN instruction, and then the protected EEPROM unlock sequence must be performed. The EEWREN instruction is issued by setting CS low and then clocking out the proper instruction into the MCP795WXX. After all eight bits of the instruction are transmitted, CS must be driven high to set the write enable latch. After setting the write enable latch and performing the unlock sequence, the user may proceed by driving CS low, issuing an IDWRITE instruction, followed by the address, and then the data to be written. Up to 8 bytes of data can be sent to the device before a write cycle is necessary. The only restriction is that all of the bytes must reside in the same page. Additionally, a page address begins with XXXX x000 and ends with XXXX x111. If the internal address counter reaches XXXX x111 and clock signals continue to be applied to the chip, the address counter will roll back to the first address of the page and over-write any data that previously existed in those locations.  2011-2018 Microchip Technology Inc. DS20002280E-page 50

MCP795W1X/MCP795W2X FIGURE 6-11: PROTECTED EEPROM READ SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCK Instruction Address Byte SI 0 0 1 1 0 0 1 1 0 0 0 0 A3 A2 A1 A0 Data Out High-Impedance SO 7 6 5 4 3 2 1 0 FIGURE 6-12: PROTECTED EEPROM UNLOCK AND PAGE WRITE SEQUENCE 1.UNLOCK CS Instruction with 0x55 Data Byte 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK Instruction Data Byte SI 0 0 0 1 0 1 0 0 0 1 0 1 0 1 0 1 2.UNLOCK CS Instruction with 0xAA Data Byte 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK Instruction Data Byte SI 0 0 0 1 0 1 0 0 1 0 1 0 1 0 1 0 3.IDWRITE Instruction CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCK Instruction Address Byte Data Byte 1 SI 0 0 1 1 0 0 1 0 0 0 0 0 A3 A2 A1 A0 7 6 5 4 3 2 1 0 CS 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 SCK Data Byte 2 Data Byte 3 Data Byte n (8 max) SI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0  2011-2018 Microchip Technology Inc. DS20002280E-page 51

MCP795W1X/MCP795W2X 6.5 Preprogrammed EUI-48 or EUI-64 6.5.1.2 EUI-64 Support Using the Node Address MCP795WX1 The preprogrammed EUI-48 node address of the The MCP795WX1 and MCP795WX2 are programmed MCP795WX1 can easily be encapsulated at the at the factory with a globally unique node address application level to form a globally unique, 64-bit node stored in the protected EEPROM block. address for systems utilizing the EUI-64 standard. This 6.5.1 EUI-48 NODE ADDRESS is done by adding 0xFFFE between the OUI and the (MCP795WX1) Extension Identifier, as shown below. The 6-byte EUI-48™ node address value of the Note: As an alternative, the MCP795WX2 MCP795WX1 is stored in protected EEPROM features an EUI-64 node address that can locations 0x02 through 0x07, as shown in Figure6-13. be used in EUI-64 applications directly The first three bytes are the Organizationally Unique without the need for encapsulation, Identifier (OUI) assigned to Microchip by the IEEE thereby simplifying system software. See Registration Authority. The remaining three bytes are Section6.5.2 “EUI-64 Node Address the Extension Identifier, and are generated by (MCP795WX2)” for details. Microchip to ensure a globally-unique, 48-bit value. 6.5.2 EUI-64 NODE ADDRESS 6.5.1.1 Organizationally Unique Identifiers (MCP795WX2) (OUIs) The 8-byte EUI-64™ node address value of the Each OUI provides roughly 16M (224) addresses. Once MCP795WX2 is stored in array locations 0x00 through the address pool for an OUI is exhausted, Microchip 0x07, as shown in Figure6-14. The first three bytes are will acquire a new OUI from IEEE to use for the Organizationally Unique Identifier (OUI) assigned programming this model. For more information on past to Microchip by the IEEE Registration Authority. and current OUIs see “Organizationally Unique The remaining five bytes are the Extension Identifier, Identifiers For Preprogrammed EUI-48 and EUI-64 and are generated by Microchip to ensure a Address Devices” Technical Brief (DS90003187). globally-unique, 64-bit value. Note: The OUI will change as addresses are Note: In conformance with IEEE guidelines, exhausted. Customers are not guaran- Microchip will not use the values 0xFFFE teed to receive a specific OUI and should and 0xFFFF for the first two bytes of the design their application to accept new EUI-64 Extension Identifier. These two OUIs as they are introduced. values are specifically reserved to allow applications to encapsulate EUI-48 addresses into EUI-64 addresses. FIGURE 6-13: EUI-48 NODE ADDRESS PHYSICAL MEMORY MAP EXAMPLE (MCP795WX1) 24-bit Organizationally 24-bit Extension Description Unique Identifier Identifier Data 00h 04h A3h 12h 34h 56h Array 02h 07h Address Corresponding EUI-48™ Node Address: 00-04-A3-12-34-56 Corresponding EUI-64™ Node Address After Encapsulation: 00-04-A3-FF-FE-12-34-56  2011-2018 Microchip Technology Inc. DS20002280E-page 52

MCP795W1X/MCP795W2X FIGURE 6-14: EUI-64 NODE ADDRESS PHYSICAL MEMORY MAP EXAMPLE (MCP795WX2) 24-bit Organizationally 40-bit Extension Description Unique Identifier Identifier Data 00h 04h A3h 12h 34h 56h 78h 90h Array 00h 07h Address Corresponding EUI-64™ Node Address: 00-04-A3-12-34-56-78-90  2011-2018 Microchip Technology Inc. DS20002280E-page 53

MCP795W1X/MCP795W2X 7.0 PACKAGING INFORMATION 7.1 Package Marking Information 14-Lead SOIC (3.90 mm) Example MCP795W20 I/SL e 3 1621256 14-Lead TSSOP Example 795W20I 1621 256 1st Line Marking Codes Part Number SOIC TSSOP MCP795W20 MCP795W20 795W20T MCP795W10 MCP795W10 795W10T MCP795W21 MCP795W21 795W21T MCP795W11 MCP795W11 795W11T MCP795W22 MCP795W22 795W22T MCP795W12 MCP795W12 795W12T Note: T = Temperature grade Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 JEDEC® designator for Matte Tin (Sn) * This package is RoHS compliant. The JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2011-2018 Microchip Technology Inc. DS20002280E-page 54

MCP795W1X/MCP795W2X Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011-2018 Microchip Technology Inc. DS20002280E-page 55

MCP795W1X/MCP795W2X Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011-2018 Microchip Technology Inc. DS20002280E-page 56

MCP795W1X/MCP795W2X (cid:2)(cid:3)(cid:4)(cid:5)(cid:6) (cid:29)(cid:10)(cid:9)(cid:2)(cid:30)(cid:11)(cid:14)(cid:2)(cid:31)(cid:10) (cid:30)(cid:2)(cid:8)!(cid:9)(cid:9)(cid:14)(cid:15)(cid:30)(cid:2)(cid:12)(cid:27)(cid:8)"(cid:27)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:27)$(cid:7)(cid:15)(cid:17) %(cid:2)(cid:12)(cid:16)(cid:14)(cid:27) (cid:14)(cid:2) (cid:14)(cid:14)(cid:2)(cid:30)(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)&(cid:27)(cid:8)"(cid:27)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)’(cid:7)(cid:8)(cid:27)(cid:30)(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:27)(cid:30)(cid:14)#(cid:2)(cid:27)(cid:30)(cid:2) (cid:11)(cid:30)(cid:30)(cid:12)())$$$(cid:20)(cid:31)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)(cid:31))(cid:12)(cid:27)(cid:8)"(cid:27)(cid:17)(cid:7)(cid:15)(cid:17)  2011-2018 Microchip Technology Inc. DS20002280E-page 57

MCP795W1X/MCP795W2X Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011-2018 Microchip Technology Inc. DS20002280E-page 58

MCP795W1X/MCP795W2X Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011-2018 Microchip Technology Inc. DS20002280E-page 59

MCP795W1X/MCP795W2X Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011-2018 Microchip Technology Inc. DS20002280E-page 60

MCP795W1X/MCP795W2X APPENDIX A: REVISION HISTORY TABLE -1: BIT NAME CHANGES Old Bit Name New Bit Name Revision A (11/2011) CALSGN TRIMSIGN Initial release of this document. OSCON OSCRUN VBAT PWRFAIL Revision B (03/2012) LP LPYR Added detailed descriptions for Registers. SQWE SQWEN ALM0 ALM0EN Revision C (06/2012) ALM1 ALM1EN Revised data sheet for 3V operation. RS0 SQWFS0 RS1 SQWFS1 Revision D (06/2016) RS2 CRSTRIM Removed preliminary status; Updated overall content CALIBRATION TRIMVAL<7:0> for improved clarity; Added detailed descriptions of WDDEL WDTDLYEN registers; Expanded descriptions of peripheral features; Updated block diagram and application WDTPLS WDTPWS schematic; Defined names for all bits and registers, WD<3:0> WDTPS<3:0> and renamed the bits shown in Table1 for clarification; EVEN0 EVLEN Renamed the DC characteristics shown in Table2 for EVEN1 EVHEN clarification. EVWDT EVWDTEN EVLDB EVLPS EVHS<1:0> EVHCS<1:0> ALM0C<2:0> ALM0MSK<2:0> ALM1C<2:0> ALM1MSK<2:0> TABLE -2: DC CHARACTERISTIC NAME CHANGES Old Name Old Symbol New Name New Symbol Operating Current ICC Read EEPROM Operating Current ICCEERD IDD Write ICCEEWR VBAT Current IBAT Timekeeping Backup Current IBATT Standby Current ICCS VCC Data Retention Current (oscillator off) ICCDAT Revision E (02/2018) Added detailed description of OUIs.  2011-2018 Microchip Technology Inc. DS20002280E-page 61

MCP795W1X/MCP795W2X NOTES:  2011-2018 Microchip Technology Inc. DS20002280E-page 62

MCP795W1X/MCP795W2X THE MICROCHIP WEBSITE CUSTOMER SUPPORT Microchip provides online support via our website at Users of Microchip products can receive assistance www.microchip.com. This website is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the website contains the following information: • Field Application Engineer (FAE) • Product Support – Data sheets and errata, • Technical Support application notes and sample programs, design resources, user’s guides and hardware support Customers should contact their distributor, documents, latest software releases and archived representative or Field Application Engineer (FAE) for software support. Local sales offices are also available to help customers. A listing of sales offices and locations is • General Technical Support – Frequently Asked included in the back of this document. Questions (FAQ), technical support requests, online discussion groups, Microchip consultant Technical support is available through the website program member listing at: http://microchip.com/support • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip website at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  2011-2018 Microchip Technology Inc. DS20002280E-page 63

MCP795W1X/MCP795W2X NOTES:  2011-2018 Microchip Technology Inc. DS20002280E-page 64

MCP795W1X/MCP795W2X PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Not every possible ordering combination is listed below. PART NO. X X [X](1) – X /XX Examples: a) MCP795W20-I/SL: 2Kbit EEPROM, Device EEPROM Protected Tape & Reel Temp. Package Industrial Density EEPROM Option Range Temperature, SOIC Package. Device: MCP795W 1.8V - 3.6V SPI Serial RTCC with b) MCP795W10-I/ST: 1Kbit EEPROM, Watchdog Timer and Event Detection Industrial Tempera- ture, TSSOP Pack- age. EEPROM 1 = 1 Kbit EEPROM Density: 2 = 2 Kbit EEPROM c) MCP795W21-I/SL: 2Kbit EEPROM, Preprogrammed EUI-48™ address, Protected 0 = Blank Industrial EEPROM: 1 = Preprogrammed EUI-48™ address Temperature, 2 = Preprogrammed EUI-64™ address SOIC Package. d) MCP795W22-I/ST: 2Kbit EEPROM, Preprogrammed EUI-64™ address, Tape & Reel Blank = Tube Industrial Temperature, TSSOP Package. Option: T = Tape & Reel Note 1: Tape and Reel identifier only Temperature I = -40C to +85C appears in the catalog part number Range: description. This identifier is used for ordering purposes and is not Package: SL = 14-Lead Plastic Small Outline (3.90mm body) printed on the device package. ST = 14-Lead Plastic Thin Shrink Small Outline Check with your Microchip Sales (4.4mm body) Office for package availability with the Tape and Reel option.  2011-2018 Microchip Technology Inc. DS20002280E-page 65

MCP795W1X/MCP795W2X NOTES:  2011-2018 Microchip Technology Inc. DS20002280E-page 66

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, AnyRate, AVR, and may be superseded by updates. It is your responsibility to AVR logo, AVR Freaks, BeaconThings, BitCloud, chipKIT, chipKIT ensure that your application meets with your specifications. logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, MICROCHIP MAKES NO REPRESENTATIONS OR Heldo, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, LINK WARRANTIES OF ANY KIND WHETHER EXPRESS OR MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST IMPLIED, WRITTEN OR ORAL, STATUTORY OR logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 OTHERWISE, RELATED TO THE INFORMATION, logo, Prochip Designer, QTouch, RightTouch, SAM-BA, SpyNIC, INCLUDING BUT NOT LIMITED TO ITS CONDITION, SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are QUALITY, PERFORMANCE, MERCHANTABILITY OR registered trademarks of Microchip Technology Incorporated in FITNESS FOR PURPOSE. Microchip disclaims all liability the U.S.A. and other countries. arising from this information and its use. Use of Microchip ClockWorks, The Embedded Control Solutions Company, devices in life support and/or safety applications is entirely at EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, the buyer’s risk, and the buyer agrees to defend, indemnify and mTouch, Precision Edge, and Quiet-Wire are registered hold harmless Microchip from any and all damages, claims, trademarks of Microchip Technology Incorporated in the U.S.A. suits, or expenses resulting from such use. No licenses are Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any conveyed, implicitly or otherwise, under any Microchip Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard, intellectual property rights unless otherwise stated. CryptoAuthentication, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter- Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Silicon Storage Technology is a registered trademark of Microchip Tempe, Arizona; Gresham, Oregon and design centers in California Technology Inc. in other countries. and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping GestIC is a registered trademark of Microchip Technology devices, Serial EEPROMs, microperipherals, nonvolatile memory and Germany II GmbH & Co. KG, a subsidiary of Microchip Technology analog products. In addition, Microchip’s quality system for the design Inc., in other countries. and manufacture of development systems is ISO 9001:2000 certified. All other trademarks mentioned herein are property of their respective companies. QUALITY MANAGEMENT SYSTEM © 2011-2018, Microchip Technology Incorporated, All Rights Reserved. CERTIFIED BY DNV ISBN: 978-1-5224-2726-1 == ISO/TS 16949 ==  2011-2018 Microchip Technology Inc. DS20002280E-page 67

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