MCP79410/MCP79411/MCP79412 2 I C™ Real-Time Clock/Calendar with EEPROM, SRAM, Unique ID and Battery Switchover Device Selection Table Description: Part EEPROM SRAM The MCP7941X series of low-power Real-Time Clocks Unique ID Number (Kbits) (Bytes) (RTC) uses digital timing compensation for an accurate clock/calendar, a programmable output control for MCP79410 1K 64 Blank versatility, a power sense circuit that automatically MCP79411 1K 64 EUI-48™ switches to the backup supply, and nonvolatile memory MCP79412 1K 64 EUI-64™ for data storage. Using a low-cost 32.768 kHz crystal, it tracks time using several internal registers. For Features: communication, the MCP7941X uses the I2C™ bus. • Real-Time Clock/Calendar (RTCC), Battery The clock/calendar automatically adjusts for months Backed: with fewer than 31 days, including corrections for - Hours, Minutes, Seconds, Day of Week, Day, leap years. The clock operates in either the 24-hour Month and Year or 12-hour format with an AM/PM indicator and - Dual alarm with single output settable alarm(s) to the second, minute, hour, day of • On-Chip Digital Trimming/Calibration: the week, date or month. Using the programmable CLKOUT, frequencies of 32.768, 8.192 and 4.096 - Range -127 to +127 ppm kHz and 1 Hz can be generated from the external - Resolution 1 ppm crystal. • Programmable Open-Drain Output Control: Along with the on-board Serial EEPROM and battery- - CLKOUT with 4 selectable frequencies backed SRAM memory, a 64-bit protected space is - Alarm output available for a unique ID or MAC address to be • 64 Bytes SRAM, Battery Backed programmed at the factory or by the end user. • 1 Kbits EEPROM (128x8): The device is fully accessible through the serial - 8 bytes/page interface while VCC is between 1.8V and 5.5V, but can - Block/sector write protection operate down to 1.3V for timekeeping and SRAM retention only. - Protect none, 1/4, 1/2 or all of array • Separate 64-Bit Unique ID: The RTC series of devices are available in the standard 8-lead SOIC, TSSOP, MSOP and 2x3 TDFN packages. - User or factory programmable - Protected area Package Types - EUI-48™ or EUI-64™ MAC address MSOP - Custom ID programming • Automatic VCC Switchover to VBAT Backup X1 1 8 VCC Supply X2 2 7 MFP TDFN • Power-Fail Time-Stamp for Battery Switchover VBAT 3 6 SCL • Low-Power CMOS Technology: X1 1 8 VCC VSS 4 5 SDA - Dynamic Current: 400 A max read X2 2 7 MFP - Dynamic Current: 3mA max EEPROM write SOIC, TSSOP VBAT 3 6 SCL VSS 4 5 SDA - Battery Backup Current: <700nA @ 1.8V X1 1 8 VCC • 100kHz and 400kHz Compatibility X2 2 7 MFP • ESD Protection >4,000V • More than 1 Million Erase/Write Cycles VBAT 3 6 SCL • Packages include 8-Lead SOIC, TSSOP, 2x3 VSS 4 5 SDA TDFN, MSOP • Pb-Free and RoHS Compliant • Temperature Ranges: - Industrial (I): -40°C to +85°C. Preliminary  2010 Microchip Technology Inc. DS22266A-page 1

MCP7941X FIGURE 1-1: TYPICAL OPERATING CIRCUIT X1 RTCC VDD or at cill s Time-Stamp/ O SRAM Alarms X2 MFP VBAT VBAT Switch I2C™ SCL VSS EEPROM ID SDA Preliminary DS22266A-page 2  2010 Microchip Technology Inc.

MCP7941X 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) VCC.............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS..........................................................................................................-0.6V to VCC +1.0V Storage temperature...............................................................................................................................-65°C to +150°C Ambient temperature with power applied................................................................................................-40°C to +125°C ESD protection on all pins 4 kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-1: DC CHARACTERISTICS Electrical Characteristics: DC CHARACTERISTICS Industrial (I): VCC = +1.8V to 5.5V TA = -40°C to +85°C Param. Sym. Characteristic Min. Typ. Max. Units Conditions No. — SCL, SDA pins — — — — D1 VIH High-level input voltage 0.7 VCC — V — D2 VIL Low-level input voltage — 0.3 VCC V VCC = 2.5V to 5.5V 0.2 VCC D3 VHYS Hysteresis of Schmitt 0.05 — V (Note1) Trigger inputs VCC (SDA, SCL pins) D4 VOL Low-level output voltage — 0.40 V IOL = 3.0ma @ VCC = 4.5V (MFP, SDA) IOL = 2.1ma @ VCC = 2.5V D5 ILI Input leakage current — ±1 A VIN = VSS or VCC D6 ILO Output leakage current — ±1 A VOUT = VSS or VCC D7 CIN, Pin capacitance — 10 pF VCC = 5.0V (Note1) COUT (SDA, SCL and MFP) TA = 25°C, f = 400kHz D8 ICC Read Operating current — 400 A VCC = 5.5V, SCL = 400kHz ICC Write EEPROM — 3 mA VCC = 5.5V D9 ICC Read Operating current — 300 A VCC = 5.5V, SCL = 400kHz SRAM ICC Write — 400 A VCC = 5.5V, SCL = 400kHz D10 ICCS Standby current (Note2) — 5 A VCC = 5.5V, SCL = SDA = VCC D11 IBAT VBAT Standby Current — 700 — nA VBAT = 1.8V @ 25°C (Note2) D12 VTRIP VBAT Change Over 1.3 1.7 V 1.5V typical at TAMB = 25°C D13 VCCFT VCC Fall Time (Note1) 300 s From VTRIP (max) to VTRIP (min) D14 VCCRT VCC Rise Time (Note1) 0 s From VTRIP (min) to VTRIP (max) D15 VBAT VBAT Voltage Range 1.3 5.5 V — (Note1) Note 1: This parameter is periodically sampled and not 100% tested. 2: Standby with oscillator running Preliminary  2010 Microchip Technology Inc. DS22266A-page 3

MCP7941X TABLE 1-2: AC CHARACTERISTICS Electrical Characteristics: AC CHARACTERISTICS Industrial (I): VCC = +1.8V to 5.5V TA = -40°C to +85°C Param. Symbol Characteristic Min. Max. Units Conditions No. 1 FCLK Clock frequency — 100 kHz 1.8V  VCC < 2.5V — 400 2.5V  VCC  5.5V 2 THIGH Clock high time 4000 — ns 1.8V  VCC < 2.5V 600 — 2.5V  VCC  5.5V 3 TLOW Clock low time 4700 — ns 1.8V  VCC < 2.5V 1300 — 2.5V  VCC  5.5V 4 TR SDA and SCL rise time — 1000 ns 1.8V  VCC < 2.5V (Note1) — 300 2.5V  VCC  5.5V 5 TF SDA and SCL fall time — 1000 ns 1.8V  VCC < 2.5V (Note1) — 300 2.5V  VCC  5.5V 6 THD:STA Start condition hold time 4000 — ns 1.8V  VCC < 2.5V 600 — 2.5V  VCC  5.5V 7 TSU:STA Start condition setup time 4700 — ns 1.8V  VCC < 2.5V 600 — 2.5V  VCC  5.5V 8 THD:DAT Data input hold time 0 — ns 9 TSU:DAT Data input setup time 250 — ns 1.8V  VCC < 2.5V 100 — 2.5V  VCC  5.5V 10 TSU:STO Stop condition setup time 4000 — ns 1.8V  VCC < 2.5V 600 — 2.5V  VCC  5.5V 11 TAA Output valid from clock — 3500 ns 1.8V  VCC < 2.5V — 900 2.5V  VCC  5.5V 12 TBUF Bus free time: Time the bus 4700 — ns 1.8V  VCC < 2.5V must be free before a new 1300 — 2.5V  VCC  5.5V transmission can start 13 TSP Input filter spike suppression — 50 ns (Note1 and Note2) (SDA and SCL pins) 14 TWC Write cycle time (byte or — 5 ms — page) 15 — Endurance 1M — cycles 25°C, VCC = 5.5V Page mode (Note3) Note 1: Not 100% tested. 2: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 3: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com. Preliminary DS22266A-page 4  2010 Microchip Technology Inc.

MCP7941X FIGURE 1-2: BUS TIMING DATA 5 4 2 D4 SCL 7 3 8 9 10 SDA 6 In 13 11 12 SDA Out Preliminary  2010 Microchip Technology Inc. DS22266A-page 5

MCP7941X 2.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table2-1. FIGURE 2-1: DEVICE PINOUTS SOIC/DFN/MSOP/TSSOP X1 1 8 Vcc X2 2 7 MFP VBAT 3 6 SCL Vss 4 5 SDA 2.1 Serial Data (SDA) This is a bidirectional pin used to transfer addresses and data into and out of the device. It is an open-drain terminal, therefore, the SDA bus requires a pull-up resistor to VCC (typically 10k for 100kHz, 2kfor 400kHz). For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the Start and Stop conditions. 2.2 Serial Clock (SCL) This input is used to synchronize the data transfer from and to the device. TABLE 2-1: PIN DESCRIPTIONS Pin Name Pin Function Vss Ground SDA Bidirectional Serial Data SCL Serial Clock X1 Xtal Input, External Oscillator Input X2 Xtal Output VBAT Battery Backup Input (3V Typ) MFP Multi Function Pin Vcc +1.8V to +5.5V Power Supply Preliminary DS22266A-page 6  2010 Microchip Technology Inc.

MCP7941X 3.0 I2C™ BUS CHARACTERISTICS 3.1.1.4 Data Valid (D) The state of the data line represents valid data when, 3.1 I2C Interface after a Start condition, the data line is stable for the duration of the high period of the clock signal. The MCP7941X supports a bidirectional 2-wire bus and data transmission protocol. A device that sends data The data on the line must be changed during the low onto the bus is defined as transmitter, and a device period of the clock signal. There is one bit of data per receiving data as receiver. The bus has to be controlled clock pulse. by a master device which generates the Start and Stop Each data transfer is initiated with a Start condition and conditions, while the MCP7941X works as slave. Both terminated with a Stop condition. The number of the master and slave can operate as transmitter or receiver data bytes transferred between the Start and Stop but the master device determines which mode is conditions is determined by the master device. activated. 3.1.1.5 Acknowledge 3.1.1 BUS CHARACTERISTICS Each receiving device, when addressed, is obliged to The following bus protocol has been defined: generate an Acknowledge signal after the reception of • Data transfer may be initiated only when the bus each byte. The master device must generate an extra is not busy. clock pulse which is associated with this Acknowledge • During data transfer, the data line must remain bit. stable whenever the clock line is high. Changes in Note: The MCP7941X does not generate any the data line while the clock line is high will be EEPROM Acknowledge bits if an internal interpreted as a Start or Stop condition. programming cycle is in progress. The Accordingly, the following bus conditions have been user may still access the SRAM and RTCC defined (Figure3-1). registers during an EEPORM write. 3.1.1.1 Bus not Busy (A) A device that acknowledges must pull down the SDA line during the Acknowledge clock pulse in such a way Both data and clock lines remain high. that the SDA line is stable-low during the high period of the Acknowledge-related clock pulse. Of course, setup 3.1.1.2 Start Data Transfer (B) and hold times must be taken into account. During A high-to-low transition of the SDA line while the clock reads, a master must signal an end of data to the slave (SCL) is high determines a Start condition. All by NOT generating an Acknowledge bit on the last byte commands must be preceded by a Start condition. that has been clocked out of the slave. In this case, the slave (MCP7941X) will leave the data line high to 3.1.1.3 Stop Data Transfer (C) enable the master to generate the Stop condition. A low-to-high transition of the SDA line while the clock (SCL) is high determines a Stop condition. All operations must end with a Stop condition. FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS (A) (B) (D) (D) (C) (A) SCL SDA Start Address or Data Stop Condition Acknowledge Allowed Condition Valid to Change Preliminary  2010 Microchip Technology Inc. DS22266A-page 7

MCP7941X FIGURE 3-2: ACKNOWLEDGE TIMING Acknowledge Bit SCL 1 2 3 4 5 6 7 8 9 1 2 3 SDA Data from transmitter Data from transmitter Transmitter must release the SDA line at this point Receiver must release the SDA line at this point allowing the Receiver to pull the SDA line low to so the Transmitter can continue sending data. acknowledge the previous eight bits of data. 3.1.2 DEVICE ADDRESSING AND OPERATION selected. The next byte received defines the address of the data byte (Figure3-3). The upper address bits are A control byte is the first byte received following the transferred first, followed by the Least Significant bits Start condition from the master device (Figure3-2). (LSb). The control byte consists of a control code; for the MCP7941X this is set as ‘1010111’ for read and write Following the Start condition, the MCP7941X monitors operations for the EEPROM. the SDA bus, checking the device type identifier being transmitted. Upon receiving an ‘1010111’ or The control byte for accessing the SRAM and RTCC ‘1101111’ code, the slave device outputs an registers are set to ‘1101111’. The RTCC registers and Acknowledge signal on the SDA line. Depending on the the SRAM share the same address space. state of the R/W bit, the MCP7941X will select a read The last bit of the control byte defines the operation to or write operation. be performed. When set to a ‘1’ a read operation is selected, and when set to a ‘0’ a write operation is FIGURE 3-3: ADDRESS SEQUENCE BIT ASSIGNMENTS EEPROM CONTROL BYTE ADDRESS BYTE 1 0 1 0 1 1 1 R/W X • • • • • • A 0 CONTROL {“A7” is “Don’t Care” for normal EEPROM CODE operations, but is used to access unique ID location and STATUS register.) X = Don’t Care SRAM RTCC CONTROL BYTE ADDRESS BYTE A 1 1 0 1 1 1 1 R/W X • • • • • • 0 CONTROL CODE X = Don’t Care Preliminary DS22266A-page 8  2010 Microchip Technology Inc.

MCP7941X 3.1.3 ACKNOWLEDGE POLLING Since the device will not acknowledge an EEPROM command during an EEPROM write cycle, this can be used to determine when the cycle is complete. This feature can be used to maximize bus throughput. Once the Stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a Start condition, followed by the control byte for a write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If no ACK is returned, then the Start bit and control byte must be resent. If the cycle is complete, then the device will return the ACK, and the master can then proceed with the next read or write command. See Figure3-4 for the flow diagram. FIGURE 3-4: ACKNOWLEDGE POLLING FLOW Send EE Write Command Send Stop Condition to Initiate EE Write Cycle Send Start Send Control Byte with R/W = 0 Did Device NO Acknowledge (ACK = 0)? YES Next Operation Preliminary  2010 Microchip Technology Inc. DS22266A-page 9

MCP7941X 4.0 RTCC FUNCTIONALITY The shaded areas are not implemented and read as ‘0’. No error checking is provided when loading time The MCP7941x family is a highly integrated RTCC. On- and date registers. board time and date counters are driven from a low- • Addresses 0x00h-0x06h are the RTCC Time and power oscillator to maintain the time and date. An Date registers. These are read/write registers. integrated VCC switch enables the device to maintain Care must be taken when accessing these regis- the time and date and also the contents of the SRAM ters while the oscillator is running. during a VCC power failure. • Addresses 0x07h-0x09h are the device Configu- 4.1 RTCC MEMORY MAP ration, Calibration and ID Unlock registers. The RTCC registers are contained in addresses • Addresses 0x0Ah-0x10h are the Alarm 0 regis- 0x00h-0x1fh. 64 bytes of user-accessable SRAM are ters. These are used to set up the Alarm 0, the located in the address range 0x20-0x5f. The SRAM Interrupt polarity and the Alarm 0 Compare. memory is a separate block from the RTCC control • Addresses 0x11h-0x17h are the same as 0x0Bh- and Configuration registers. All SRAM locations are 0x11h but are used for Alarm 1. battery-backed-up during a VCC power fail. Unused • Addresses 0x18h-0x1Fh are used for the time- locations are not accessible, MCP7941X will noACK stamp feature. after the address byte if the address is out of range. The Memory Map is shown in Table4-1. TABLE 4-1: RTCC MEMORY MAP Reset Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Function Range State 00h ST 10 Seconds Seconds Seconds 00-59 00h 01h 10 Minutes Minutes Minutes 00-59 00h 02h 10 Hour 10 Hour Hour Hours 1-12 + AM/PM 00h 12/24 AM/PM 00 - 23 03h OSCON VBAT VBATEN Day Day 1-7 01h 04h 10 Date Date Date 01-31 01h 05h LP 10 Month Month Month 01-12 01h 06h 10 Year Year Year 00-99 01h 07h OUT SQWE ALM1 ALM0 EXTOSC RS2 RS1 RS0 Control Reg. 80h 08h CALIBRATION Calibration 00h 09h UNIQUE UNLOCK ID SEQUENCE Unlock ID 00h 0Ah 10 Seconds Seconds Seconds 00-59 00h 0Bh 10 Minutes Minutes Minutes 00 - 59 00h 0Ch 10 Hour 10 Hours Hour Hours 1-12 + AM/PM 00h 12/24 AM/PM 00-23 0Dh ALM0POL ALM0C2 ALM0C1 ALM0C0 ALM0IF Day Day 1-7 01h 0Eh 10 Date Date Date 01-31 01h 0Fh 10 Month Month Month 01-12 01h 10h Reserved – Do not use Reserved 01h 11h 10 Seconds Seconds Seconds 00-59 00h 12h 10 Minutes Minutes Minutes 00-59 00h 13h 10 Hour 10 Hours Hour Hours 1-12 + AM/PM 00h 12/24 AM/PM 00-23 14h ALM1POL ALM1C2 ALM1C1 ALM1C0 ALM1IF Day Day 1-7 01h 15h 10 Date Date Date 01-31 01h 16h 10 Month Month Month 01-12 01h 17h Reserved - Do not use Reserved 01h 18h 10 Minutes Minutes 00h 19h 10 Hour 10 Hours Hour 00h 12/24 AM/PM 1Ah 10 Date Date 00h 1Bh Day 10 Month Month 00h 1Ch 10 Minutes Minutes 00h 1Dh 10 Hour 10 Hours Hour 00h 12/24 AM/PM 1Eh 10 Date Date 00h 1Fh Day 10 Month Month 00h Preliminary DS22266A-page 10  2010 Microchip Technology Inc.

MCP7941X 4.1.1 RTCC REGISTER ADDRESSES • Bit 7 is the OUT bit. This sets the logic level on the MFP when not using this as a square wave out- 0x00h – Contains the BCD seconds and 10 seconds. put. The range is 00 to 59. Bit 7 in this register is used to start or stop the on-board crystal oscillator. Setting this • Bit 6 is the SQWE bit. Setting this bit enables the bit to a ‘1’ starts the oscillator and clearing this bit to a divided output from the crystal oscillator. ‘0’ stops the on-board oscillator. • Bits 5:4 determine which alarms are active. 0x01h – Contains the BCD minutes and 10 minutes. - 00 – No Alarms are active The range is 00 to 59. - 01 – Alarm 0 is active 0x02h – Contains the BCD hour in bits 3:0. Bits 5:4 - 10 – Alarm 1 is active contain either the 10 hour in BCD for 24-hour format or - 11 – Both Alarms are active the AM/PM indicator and the 10-hour bit for 12-hour • Bit 3 is the EXTOSC enable bit. Setting this bit will format. Bit 5 determines the hour format. Setting this allow an external 32.768 kHz signal to drive the bit to ‘0’ enables 24-hour format, setting this bit to ‘1’ RTCC registers eliminating the need for an enables 12-hour format. external crystal. 0x03h – Contains the BCD day. The range is 1-7. • Bit 2:0 sets the internal divider for the 32.768 kHz Additional bits are also used for configuration and oscillator to be driven to the MFP. The duty cycle is status. 50%. The output is responsive to the Calibration register. The following frequencies are available: • Bit 3 is the VBATEN bit. If this bit is set, the internal circuitry is connected to the VBAT pin - 000 – 1 Hz when VCC fails. If this bit is ‘0’ then the VBAT pin is - 001 – 4.096 kHz disconnected and the only current drain on the - 010 – 8.192 kHz external battery is the VBAT pin leakage. - 011 – 32.768 kHz • Bit 4 is the VBAT bit. This bit is set by hardware - 1xx enables the Cal output function. Cal when the VCC fails and the VBAT is used to power output appears on MFP if SQWE is set (64 the Oscillator and the RTCC registers. This bit is Hz Nominal). cleared by software. Clearing this bit will also clear all the time-stamp registers. Note: The RTCC counters will continue to increment during the calibration. • Bit 5 is the OSCON bit. This is set and cleared by hardware. If this bit is set, the oscillator is running, 0x08h is the Calibration register. This is an 8-bit if cleared, the oscillator is not running. This bit register that is used to add or subtract clocks from the does not indicate that the oscillator is running at RTCC counter every minute. The MSB is the sign bit the correct frequency. The RTCC will wait 32 and indicates if the count should be added or oscillator cycles before the bit is set. The RTCC subtracted. The remaining 7 bits, with each bit adding will wait roughly 32 clock cycles to clear this bit. or subtracting 2 clocks, give the user the ability to add or subtract up to 254 clocks per minute. 0x04h – Contains the BCD date and 10 date. The range is 01-31. 0x09h is the unlock sequence address. To unlock write 0x05h – Contains the BCD month. Bit 4 contains the access to the unique ID area in the EEPROM, a 10 month. Bit 5 is the Leap Year bit, which is set during sequence must be written to this address in separate a leap year and is read-only. commands. The process is fully detailed in Section4.2.2 “Unlock Sequence”. 0x06h – Contains the BCD year and 10 year. The 0x0Ah-0x0fh and 0x11-0x16h are the Alarm 0 and Range is 00-99. Alarm 1 registers. The bits are the same as the RTCC 0x07h – Is the Control register. bits with the following differences: Locations 0x10h and 0x17h are reserved and should not be used to allow for future device compatibility. 0x0Dh/0x14h has additional bits for alarm configu- ration. • ALMxPOL: This bit specifies the level that the MFP will drive when the alarm is triggered. ALM2POL is a copy of ALM1POL. The default state of the MFP when used for alarms is the inverse of ALM1POL. • ALMxIF: This is the Alarm Interrupt Fag. This bit is set in hardware if the alarm was triggered. The bit is cleared in software. Preliminary  2010 Microchip Technology Inc. DS22266A-page 11

MCP7941X • ALMxC2:0: These Configuration bits determine 4.2 FEATURES the alarm match. The logic will trigger the alarm based on one of the following match conditions: 4.2.1 STATUS REGISTER 000 – Seconds match The STATUS register is in the nonvolatile EEPROM 001 – Minutes match array. To access the STATUS register, the address of 0xFFh is written to and read from. ACK polling may be 010 – Hours match (takes into account 12/24 used to determine if the write is complete. The bits in hour) this register are defined as: 011 – Matches the current day, interrupt at • Bit 3:2 are the EEPROM array block protection 12.00.00 a.m. Example: 12 midnight on bits. These bits are in the nonvolatile EEPROM 100 – Date array. This allows protection of the following 101 – RESERVED areas: 110 – RESERVED - 00 – None of the array is protected. 111 – Seconds, Minutes, Hour, Day, Date, - 01 – The upper 1/4 of the array 0x60h-0x7fh Month is protected. • The 12/24-hour bits 0xCh.6 and 0x13h.6 are cop- - 10 – The upper 1/2 of the array 0x40h-0x7fh ies of the bit in 0x02h.6. The bits are read-only. is protected. - 11 – All of the array 0x00-0x7fh is protected. 0x18h-0x1Bh are used for the timesaver function. These registers are loaded at the time when VCC fails • The unused bits are reserved at this time and and the RTCC operates on the VBAT. The VBAT bit is read as ‘0’. also set at this time. These registers are cleared when • With the current address read operation, the the VBAT bit is cleared in software. address is not incremented. Consequently, the subsequent reads are done from the same 0x1Ch-0x1Fh are used for the timesaver function. location. These registers are loaded at the time when VCC is restored and the RTCC switches to VDD. These If multiple bytes are loaded to the STATUS register, registers are cleared when the VBAT bit is cleared in only the last byte is written. software. 4.2.2 UNLOCK SEQUENCE Note: It is strongly recommended that the timesaver function only be used when the The unique ID location is user accessible by using the oscillator is running. This will ensure unlock ID sequence. accurate functionality. The unique ID location is 64-bits (8 bytes) and is stored in EEPROM locations 0xF0 to 0xF7. This location can be read at any time, however, a write is inhibited until unlocked. To unlock the write access to this location the following sequence must be completed: • A single write of 0x55h to address 0x09. Stop • A single write of 0xAAh to address 0x09. Stop This will allow the unique EEPROM locations to be written. After the byte or page write to these locations, the write sequence is initiated by the Stop condition. At this time, the ID locations are locked and no further writes are possible to this location unless a complete unlock sequence is repeated. Preliminary DS22266A-page 12  2010 Microchip Technology Inc.

MCP7941X 4.2.3 CALIBRATION RS2 RS1 RS0 Output Signal The MCP7941X utilizes digital calibration to correct for inaccuracies of the input clock source (either external 0 0 0 32768 or crystal). Calibration is enabled by setting the value 0 0 1 8 of the Calibration register at address 08H. Calibration 0 1 0 4 is achieved by adding or subtracting a number of input 0 1 1 1 clock cycles per minute in order to achieve ppm level With regards to the calibration function, the Calibration adjustments in the internal timing function of the register setting has no impact upon the MFP output MCP7941X. clock signal when bits RS1 and RS0 are set to ‘11’. The MSB of the Calibration register is the sign bit, with The setting of the Calibration register to a non-zero a ‘1’ indicating subtraction and a ‘0’ indicating addition. value (i.e., values other than 00H or 80H) enables the The remaining seven bits in the register indicate the calibration function which can be observed on the number of input clock cycles (multiplied by two) that MFP output pin. The calibration function can be are subtracted or added per minute to the internal expressed in terms of the number of input clock cycles timing function. added/subtracted from the internal timing function. The internal timing function can be monitored using With bits RS1 and RS0 set to ‘00’, the calibration the MFP open-drain output pin by setting bit [6] function can be expressed as: (SQWE) and bits [2:0] (RS2, RS1, RS0) of the control register at address 07H. Note that the MFP output T = (32768 +/- (2 * CALREG)) T output input waveform is disabled when the MCP7941X is running where: in VBAT mode. With the SQWE bit set to ‘1’, there are two methods that can be used to observe the internal Toutput = clock period of MFP output signal timing function of the MCP7941X: T = clock period of input signal input CALREG = decimal value of Calibration A. RS2 BIT SET TO ‘0’ register setting and the sign is With the RS2 bit set to ‘0’, the RS1 and RS0 bits determined by the MSB of enable the following internal timing signals to be Calibration register. output on the MFP pin: Since the calibration is done once per minute (i.e., RS2 RS1 RS0 Output Signal when the internal minute counter is incremented), only one cycle in sixty of the MFP output waveform is 0 0 0 1 Hz affected by the calibration setting. Also note that the 0 0 1 4.096 kHz duty cycle of the MFP output waveform will not 0 1 0 8.192 kHz necessarily be at 50% when the calibration setting is 0 1 1 32.768 kHz applied. The frequencies listed in the table presume an input With bits RS1 and RS0 set to ‘01’ or ‘10’, the clock source of exactly 32.768 kHz. In terms of the calibration function can not be expressed in terms of equivalent number of input clock cycles, the table the input clock period. In the case where the MSB of becomes: the Calibration register is set to ‘0’, the waveform appearing at the MFP output pin will be “delayed”, once per minute, by twice the number of input clock cycles defined in the Calibration register. The MFP waveform will appear as: FIGURE 4-1: RS1 AND RS0 WITH AND WITHOUT CALIBRATION Delay Preliminary  2010 Microchip Technology Inc. DS22266A-page 13

MCP7941X In the case where the MSB of the Calibration register 4.2.4 MFP is set to ‘1’, the MFP output waveforms that appear Pin 7 is a multi-function pin and supports the following when bits RS1 and RS0 are set to ‘01’ or ‘10’ are not functions: as responsive to the setting of the Calibration register. For example, when outputting the 4.096 kHz • Use of the OUT bit in the Control register for waveform (RS1, RS0 set to ‘01’), the output waveform single bit I/O is generated using only eight input clock cycles. • Alarm Outputs – Available in VBAT mode Consequently, attempting to subtract more than eight • FOUT mode – driven from a FOSC divider – Not input clock cycles from this output does not have a available in VBAT mode meaningful effect on the resulting waveform. Any The internal control logic for the MFP is connected to effect on the output will appear as a modification in the switched internal supply bus, this allows operation both the frequency and duty cycle of the waveform in VBAT mode. The Alarm Output is the only mode that appearing on the MFP output pin. operates in VBAT mode, other modes are suspended. B.RS2 BIT SET TO ‘1’ 4.2.5 VBAT With the RS2 bit set to ‘1’, the following internal timing If the VBAT feature is not being used, the VBAT pin signal is output on the MFP pin: should be connected to GND. A low-value series resistor is recommended between the external battery RS2 RS1 RS0 Output Signal and the VBAT pin. 1 x x 64.0 Hz The VBAT point is defined as 1.5V typical. When VDD The frequency listed in the table presumes an input falls below 1.5V the system will continue to operate clock source of exactly 32.768 kHz. In terms of the the RTCC and SRAM using the VBAT supply. The equivalent number of input clock cycles, the table following conditions apply: becomes: TABLE 4-2: RS2 RS1 RS0 Output Signal Supply Read/Write Powered 1 x x 512 Condition Access By Unlike the method previously described, the VCC < VTRIP, VCC < VBAT No VBAT calibration setting is continuously applied and affects every cycle of the output waveform. This results in the VCC > VTRIP, VCC < VBAT Yes VCC modulation of the frequency of the output waveform VCC > VTRIP, VCC > VBAT Yes VCC based upon the setting of the Calibration register. Using this setting, the calibration function can be 4.2.6 CRYSTAL SPECS expressed as: The MCP7941X has been designed to operate with a standard 32 kHz crystal. Devices with a specified load Toutput = (2 * (256 +/- (2 * CALREG))) Tinput capacitance of either 12pF or 6pF can be used. The where: end user should fully validate the chosen crystal across all the expected design parameters of the system to T = clock period of MFP output signal output ensure correct operation. T = clock period of input signal input The following crystals have been tested and shown to CALREG = decimal value of the Calibration work with the MCP7941X: register setting, and the sign is determined by the MSB of the • CM200S 12pF surface mount crystals from Calibration register. Citizen • ECS-.327 12pF surface mount crystals from ECS Since the calibration is done every cycle, the frequency INC of the output MFP waveform is constant. • CFS206 12pF leaded crystals from Citizen This is not a definitive list and all crystals should be tested in the target application across all temperature, voltage and other significant environmental conditions. Preliminary DS22266A-page 14  2010 Microchip Technology Inc.

MCP7941X 4.2.7 POWER-FAIL TIME-STAMP The MCP7941X family of RTCC devices feature a power-fail time-stamp feature. This feature will save the time at which VCC crosses the VTRIP voltage. To use this feature, a VBAT supply must be present and the oscillator must also be running. There are two separate sets of registers that are used to record this information: • The first set located at 0x18h through 0x1Bh are loaded at the time when VCC fails and the RTCC operates on the VBAT. The VBAT (register 0x03h bit 4) bit is also set at this time. • The second set of registers, located at 0x1Ch through 0x1Fh, are loaded at the time when VCC is restored and the RTCC switches to VCC. The power-fail time-stamp registers are cleared when the VBAT bit is cleared in software. Preliminary  2010 Microchip Technology Inc. DS22266A-page 15

MCP7941X 5.0 ON BOARD MEMORY removed, provided the VBAT supply is present and enabled. The EEPROM is organized as 128 x 8 bytes. The MCP7941X has both on-board EEPROM memory The EEPROM is nonvolatile memory and does not and Battery-Backed SRAM. The SRAM is arranged as require the VBAT supply for retention. 64 x 8 bytes and is retained when the VCC supply is 5.1 SRAM FIGURE 5-1: SRAM/RTCC BYTE WRITE S BUS ACTIVITY T S CONTROL ADDRESS MASTER A T R BYTE BYTE DATA O T P SDA LINE S1 1 0 11 11 0 x P A A A BUS ACTIVITY C C C K K K FIGURE 5-2: SRAM/RTCC MULTIPLE BYTE WRITE S T S BUS ACTIVITY A CONTROL ADDRESS T MASTER R BYTE BYTE DATA BYTE 0 DATA BYTE N O T P SDA LINE S11 0 11 1 1 0 x P A A A A BUS ACTIVITY C C C C K K K K The 64 bytes of user SRAM are at location 0x20h and can be accessed during an RTCC update. Upon POR Note: Entering an address past 5F for an SRAM the SRAM will be in an undefined state. operation will result in the MCP7941X not acknowledging the address. Writing to the SRAM and RTCC is accomplished in a similar way to writing to the EEPROM (as described later in this document) with the following consider- ations: • There is no page. The entire 64 bytes of SRAM or 32 bytes of RTCC register can be written in one command. • The SRAM allows an unlimited number of read/ write cycles with no cell wear out. • The RTCC and SRAM are not accessible when the device is running on the external VBAT. • The RTCC and SRAM are separate blocks. The SRAM array may be accessed during an RTCC update. • Read and write access is limited to either the RTCC register block or the SRAM array. The Address Pointer will rollover to the start of the addressed block. • Data written to the RTCC and SRAM are on a per byte basis. Preliminary DS22266A-page 16  2010 Microchip Technology Inc.

MCP7941X 5.2 EEPROM 5.2.1 EEPROM BYTE WRITE Note: Page write operations are limited to writing bytes within a single physical page, Following the Start condition from the master, the regardless of the number of bytes actually control code and the R/W bit (which is a logic low) are being transmitted. Physical page clocked onto the bus by the master transmitter. This boundaries start at addresses that are indicates to the addressed slave receiver that a byte integer multiples of the page buffer size (or with a word address will follow after it has generated an ‘page size’) and end at addresses that are Acknowledge bit during the ninth clock cycle. integer multiples of [page size - 1]. If a Therefore, the next byte transmitted by the master is page write command attempts to write the word address and will be written into the Address across a physical page boundary, the Pointer of the MCP7941X. After receiving another result is that the data wraps around to the Acknowledge signal from the MCP7941X, the master beginning of the current page (overwriting device transmits the data word to be written into the data previously stored there), instead of addressed memory location. The MCP7941X being written to the next page as might be acknowledges again and the master generates a Stop expected. It is therefore necessary for the condition. This initiates the internal write cycle, and, application software to prevent page write during this time, the MCP7941X does not generate operations that would attempt to cross a Acknowledge signals for EEPROM write commands. If page boundary. an attempt is made to write to an address and the protection is set then the device will acknowledge the command but no write cycle will occur, no data will be written, and the device will immediately accept a new Note: Addressing undefined EEPROM locations command. After a byte write command, the internal will result in the MCP7941X not address counter will point to the address location acknowledging the address. following the one that was just written. 5.2.2 EEPROM PAGE WRITE The write control byte, word address, and the first data byte are transmitted to the MCP7941X in the same way as in a byte write. But instead of generating a Stop condition, the master transmits up to 7 additional bytes, which are temporarily stored in the on-chip page buffer and will be written into memory after the master has transmitted a Stop condition. After receipt of each word, the three lower Address Pointer bits are internally incremented by one. If the master should transmit more than 8 bytes prior to generating the Stop condition, the address counter will roll over and the data received previously will be overwritten. As with the byte write operation, once the Stop condition is received, an internal write cycle will begin (Figure5-4). Preliminary  2010 Microchip Technology Inc. DS22266A-page 17

MCP7941X FIGURE 5-3: EE BYTE WRITE S BUS ACTIVITY T S CONTROL ADDRESS MASTER A T R BYTE BYTE DATA O T P SDA LINE S1 0 1 01 11 0 x P A A A BUS ACTIVITY C C C K K K x = don’t care for 1K devices FIGURE 5-4: EE PAGE WRITE S T S BUS ACTIVITY A CONTROL ADDRESS T MASTER R BYTE BYTE DATA BYTE 0 DATA BYTE 7 O T P SDA LINE S10 1 01 1 10 x P A A A A BUS ACTIVITY C C C C K K K K x = don’t care for 1K devices 5.2.3 BLOCK PROTECTION FIGURE 5-1: CURRENT ADDRESS READ (EEPROM SHOWN) The EEPROM does not support a hardware write protection pin, however, software block protection is S T S available to the use and is configured using the BUS ACTIVITY A CONTROL DATA T STATUS register. MASTER R BYTE BYTE O T P 5.2.4 READ OPERATION SDA LINE S 1 0 1 0 1 1 1 1 P Read operations are initiated in the same way as write A N BUS ACTIVITY C O operations with the exception that the R/W bit of the K A control byte is set to one. There are three basic types C of read operations: current address read, random read, K and sequential read. The SRAM array can be read in 5.2.4.2 Random Read the same way as the EEPROM using the control byte for the SRAM ‘1101111’ with a valid address. Random read operations allow the master to access any memory location in a random manner. To perform 5.2.4.1 Current Address Read this type of read operation, first the word address must The MCP7941X contains an address counter that be set. This is done by sending the word address to the maintains the address of the last word accessed, MCP7941X as part of a write operation (R/W bit set to internally incremented by one. Therefore, if the ‘0’). After the word address is sent, the master previous read access was to address n (n is any legal generates a Start condition following the Acknowledge. address), the next current address read operation This terminates the write operation, but not before the would access data from address n + 1. internal Address Pointer is set. Then, the master issues the control byte again but with the R/W bit set to a one. Upon receipt of the control byte with R/W bit set to one, The MCP7941X will then issue an Acknowledge and the MCP7941X issues an Acknowledge and transmits transmit the 8-bit data word. The master will not the 8-bit data word. The master will not acknowledge acknowledge the transfer but it does generate a Stop the transfer but does generate a Stop condition and the condition which causes the MCP7941X to discontinue MCP7941X discontinues transmission (Figure5-1). transmission (Figure5-2). After a random read command, the internal address counter will point to the address location following the one that was just read. Preliminary DS22266A-page 18  2010 Microchip Technology Inc.

MCP7941X 5.2.4.3 Sequential Read master, the master will NOT generate an Acknowledge but will generate a Stop condition. To provide Sequential reads are initiated in the same way as a sequential reads, the MCP7941X contains an internal random read except that after the MCP7941X transmits Address Pointer which is incremented by one at the the first data byte, the master issues an Acknowledge completion of each operation. This Address Pointer as opposed to the Stop condition used in a random allows the entire memory contents to be serially read read. This Acknowledge directs the MCP7941X to during one operation. The internal Address Pointer will transmit the next sequentially addressed 8-bit word automatically roll over to the start of the Block. (Figure5-3). Following the final byte transmitted to the FIGURE 5-2: RANDOM READ (EEPROM SHOWN) S S BUS ACTIVITY T T S CONTROL ADDRESS CONTROL DATA MASTER A A T R BYTE BYTE R BYTE BYTE O T T P SDA LINE S1 0 1 0 1 1 1 0 S1 0 1 0 1 P A A A N BUS ACTIVITY C C C O K K K A C K FIGURE 5-3: SEQUENTIAL READ (EEPROM SHOWN) CONTROL S BUS ACTIVITY T MASTER BYTE DATA n DATA n + 1 DATA n + 2 DATA n + X O P SDA LINE P A A A A N C C C C O BUS ACTIVITY K K K K A C K 5.3 Unique ID The MCP7941X features an additional 64-bit unique ID area. This is separate and in addition to the 1K of on- board EEPROM. The unique ID is located at addresses 0xF0 through 0xF7. Reading the unique ID requires the user to simply address these bytes. The unique ID area is protected to prevent unintended writes to these locations. The unlock sequence is detailed in 4.2.2 “Unlock Sequence”. The unique ID can be factory programmed on some devices to provide a unique IEEE EUI-48 or EUI-64 value. In addition, customer-provided codes can also be programmed. Preliminary  2010 Microchip Technology Inc. DS22266A-page 19

MCP7941X 6.0 PACKAGING INFORMATION 6.1 Package Marking Information 8-Lead SOIC (3.90 mm) Example: XXXXXT 79410I XXYYWW SN e 3 0527 NNN 13F 8-Lead TSSOP Example: XXXX 7941 TYWW I527 NNN 13F 8-Lead MSOP Example: XXXXX 79401I YWWNNN 52713F 8-Lead 2x3 TDFN Example: XXX AC4 YWW 527 NN 13 1st Line Marking Codes Part Number TSSOP MSOP TDFN MCP79410 7941 79410T AAP MCP79411 9411 79411T AAQ MCP79412 9412 79412T AAR Note: T = Temperature grade NN = Alphanumeric traceability code Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. Preliminary DS22266A-page 20  2010 Microchip Technology Inc.

MCP7941X (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:10)(cid:8)(cid:17)(cid:18)(cid:12)(cid:10)(cid:13)(cid:19)(cid:5)(cid:8)(cid:20)(cid:15)(cid:21)(cid:22)(cid:8)(cid:23)(cid:8)(cid:21)(cid:6)(cid:24)(cid:24)(cid:25)(cid:26)(cid:27)(cid:8)(cid:28)(cid:29)(cid:30)(cid:31)(cid:8)(cid:16)(cid:16)(cid:8) (cid:25)(cid:7)!(cid:8)"(cid:15)(cid:17)#$% (cid:21)(cid:25)(cid:12)(cid:5)& 2(cid:21)(cid:20)(cid:14)%(cid:22)(cid:13)(cid:14)&(cid:21) %(cid:14)(cid:19)!(cid:20)(cid:20)(cid:13)(cid:24)%(cid:14)(cid:10)(cid:11)(cid:19)3(cid:11)(cid:12)(cid:13)(cid:14)"(cid:20)(cid:11))(cid:18)(cid:24)(cid:12) ’(cid:14)(cid:10)(cid:25)(cid:13)(cid:11) (cid:13)(cid:14) (cid:13)(cid:13)(cid:14)%(cid:22)(cid:13)(cid:14)(cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:14)(cid:30)(cid:11)(cid:19)3(cid:11)(cid:12)(cid:18)(cid:24)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:19)(cid:18)$(cid:18)(cid:19)(cid:11)%(cid:18)(cid:21)(cid:24)(cid:14)(cid:25)(cid:21)(cid:19)(cid:11)%(cid:13)"(cid:14)(cid:11)%(cid:14) (cid:22)%%(cid:10)144)))(cid:28)&(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:28)(cid:19)(cid:21)&4(cid:10)(cid:11)(cid:19)3(cid:11)(cid:12)(cid:18)(cid:24)(cid:12) D e N E E1 NOTE1 1 2 3 b h α h c A A2 φ A1 L L1 β 5(cid:24)(cid:18)% (cid:17)(cid:27)66(cid:27)(cid:17)-(cid:23)-(cid:8)(cid:3) (cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)(cid:14)6(cid:18)&(cid:18)% (cid:17)(cid:27)7 78(cid:17) (cid:17)(cid:7)9 7!&((cid:13)(cid:20)(cid:14)(cid:21)$(cid:14)(cid:30)(cid:18)(cid:24) 7 : (cid:30)(cid:18)%(cid:19)(cid:22) (cid:13) (cid:29)(cid:28)(cid:16)(cid:15)(cid:14)0(cid:3)+ 8(cid:31)(cid:13)(cid:20)(cid:11)(cid:25)(cid:25)(cid:14);(cid:13)(cid:18)(cid:12)(cid:22)% (cid:7) < < (cid:29)(cid:28)(cid:15). (cid:17)(cid:21)(cid:25)"(cid:13)"(cid:14)(cid:30)(cid:11)(cid:19)3(cid:11)(cid:12)(cid:13)(cid:14)(cid:23)(cid:22)(cid:18)(cid:19)3(cid:24)(cid:13) (cid:7)(cid:16) (cid:29)(cid:28)(cid:16). < < (cid:3)%(cid:11)(cid:24)"(cid:21)$$(cid:14)(cid:14)* (cid:7)(cid:29) (cid:4)(cid:28)(cid:29)(cid:4) < (cid:4)(cid:28)(cid:16). 8(cid:31)(cid:13)(cid:20)(cid:11)(cid:25)(cid:25)(cid:14)=(cid:18)"%(cid:22) - >(cid:28)(cid:4)(cid:4)(cid:14)0(cid:3)+ (cid:17)(cid:21)(cid:25)"(cid:13)"(cid:14)(cid:30)(cid:11)(cid:19)3(cid:11)(cid:12)(cid:13)(cid:14)=(cid:18)"%(cid:22) -(cid:29) ,(cid:28)(cid:6)(cid:4)(cid:14)0(cid:3)+ 8(cid:31)(cid:13)(cid:20)(cid:11)(cid:25)(cid:25)(cid:14)6(cid:13)(cid:24)(cid:12)%(cid:22) (cid:2) (cid:5)(cid:28)(cid:6)(cid:4)(cid:14)0(cid:3)+ +(cid:22)(cid:11)&$(cid:13)(cid:20)(cid:14)?(cid:21)(cid:10)%(cid:18)(cid:21)(cid:24)(cid:11)(cid:25)@ (cid:22) (cid:4)(cid:28)(cid:16). < (cid:4)(cid:28).(cid:4) 2(cid:21)(cid:21)%(cid:14)6(cid:13)(cid:24)(cid:12)%(cid:22) 6 (cid:4)(cid:28)(cid:5)(cid:4) < (cid:29)(cid:28)(cid:16)(cid:15) 2(cid:21)(cid:21)%(cid:10)(cid:20)(cid:18)(cid:24)% 6(cid:29) (cid:29)(cid:28)(cid:4)(cid:5)(cid:14)(cid:8)-2 2(cid:21)(cid:21)%(cid:14)(cid:7)(cid:24)(cid:12)(cid:25)(cid:13) (cid:3) (cid:4)A < :A 6(cid:13)(cid:11)"(cid:14)(cid:23)(cid:22)(cid:18)(cid:19)3(cid:24)(cid:13) (cid:19) (cid:4)(cid:28)(cid:29)(cid:15) < (cid:4)(cid:28)(cid:16). 6(cid:13)(cid:11)"(cid:14)=(cid:18)"%(cid:22) ( (cid:4)(cid:28),(cid:29) < (cid:4)(cid:28).(cid:29) (cid:17)(cid:21)(cid:25)"(cid:14)(cid:2)(cid:20)(cid:11)$%(cid:14)(cid:7)(cid:24)(cid:12)(cid:25)(cid:13)(cid:14)(cid:23)(cid:21)(cid:10) (cid:4) .A < (cid:29).A (cid:17)(cid:21)(cid:25)"(cid:14)(cid:2)(cid:20)(cid:11)$%(cid:14)(cid:7)(cid:24)(cid:12)(cid:25)(cid:13)(cid:14)0(cid:21)%%(cid:21)& (cid:5) .A < (cid:29).A (cid:21)(cid:25)(cid:12)(cid:5)(cid:11)& (cid:29)(cid:28) (cid:30)(cid:18)(cid:24)(cid:14)(cid:29)(cid:14)(cid:31)(cid:18) !(cid:11)(cid:25)(cid:14)(cid:18)(cid:24)"(cid:13)#(cid:14)$(cid:13)(cid:11)%!(cid:20)(cid:13)(cid:14)&(cid:11)(cid:26)(cid:14)(cid:31)(cid:11)(cid:20)(cid:26)’(cid:14)(!%(cid:14)&! %(cid:14)((cid:13)(cid:14)(cid:25)(cid:21)(cid:19)(cid:11)%(cid:13)"(cid:14))(cid:18)%(cid:22)(cid:18)(cid:24)(cid:14)%(cid:22)(cid:13)(cid:14)(cid:22)(cid:11)%(cid:19)(cid:22)(cid:13)"(cid:14)(cid:11)(cid:20)(cid:13)(cid:11)(cid:28) (cid:16)(cid:28) *(cid:14)(cid:3)(cid:18)(cid:12)(cid:24)(cid:18)$(cid:18)(cid:19)(cid:11)(cid:24)%(cid:14)+(cid:22)(cid:11)(cid:20)(cid:11)(cid:19)%(cid:13)(cid:20)(cid:18) %(cid:18)(cid:19)(cid:28) ,(cid:28) (cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24) (cid:14)(cid:2)(cid:14)(cid:11)(cid:24)"(cid:14)-(cid:29)(cid:14)"(cid:21)(cid:14)(cid:24)(cid:21)%(cid:14)(cid:18)(cid:24)(cid:19)(cid:25)!"(cid:13)(cid:14)&(cid:21)(cid:25)"(cid:14)$(cid:25)(cid:11) (cid:22)(cid:14)(cid:21)(cid:20)(cid:14)(cid:10)(cid:20)(cid:21)%(cid:20)! (cid:18)(cid:21)(cid:24) (cid:28)(cid:14)(cid:17)(cid:21)(cid:25)"(cid:14)$(cid:25)(cid:11) (cid:22)(cid:14)(cid:21)(cid:20)(cid:14)(cid:10)(cid:20)(cid:21)%(cid:20)! (cid:18)(cid:21)(cid:24) (cid:14) (cid:22)(cid:11)(cid:25)(cid:25)(cid:14)(cid:24)(cid:21)%(cid:14)(cid:13)#(cid:19)(cid:13)(cid:13)"(cid:14)(cid:4)(cid:28)(cid:29).(cid:14)&&(cid:14)(cid:10)(cid:13)(cid:20)(cid:14) (cid:18)"(cid:13)(cid:28) (cid:5)(cid:28) (cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)(cid:18)(cid:24)(cid:12)(cid:14)(cid:11)(cid:24)"(cid:14)%(cid:21)(cid:25)(cid:13)(cid:20)(cid:11)(cid:24)(cid:19)(cid:18)(cid:24)(cid:12)(cid:14)(cid:10)(cid:13)(cid:20)(cid:14)(cid:7)(cid:3)(cid:17)-(cid:14)/(cid:29)(cid:5)(cid:28).(cid:17)(cid:28) 0(cid:3)+1 0(cid:11) (cid:18)(cid:19)(cid:14)(cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)(cid:28)(cid:14)(cid:23)(cid:22)(cid:13)(cid:21)(cid:20)(cid:13)%(cid:18)(cid:19)(cid:11)(cid:25)(cid:25)(cid:26)(cid:14)(cid:13)#(cid:11)(cid:19)%(cid:14)(cid:31)(cid:11)(cid:25)!(cid:13)(cid:14) (cid:22)(cid:21))(cid:24)(cid:14))(cid:18)%(cid:22)(cid:21)!%(cid:14)%(cid:21)(cid:25)(cid:13)(cid:20)(cid:11)(cid:24)(cid:19)(cid:13) (cid:28) (cid:8)-21 (cid:8)(cid:13)$(cid:13)(cid:20)(cid:13)(cid:24)(cid:19)(cid:13)(cid:14)(cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)’(cid:14)! !(cid:11)(cid:25)(cid:25)(cid:26)(cid:14))(cid:18)%(cid:22)(cid:21)!%(cid:14)%(cid:21)(cid:25)(cid:13)(cid:20)(cid:11)(cid:24)(cid:19)(cid:13)’(cid:14)$(cid:21)(cid:20)(cid:14)(cid:18)(cid:24)$(cid:21)(cid:20)&(cid:11)%(cid:18)(cid:21)(cid:24)(cid:14)(cid:10)!(cid:20)(cid:10)(cid:21) (cid:13) (cid:14)(cid:21)(cid:24)(cid:25)(cid:26)(cid:28) (cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:23)(cid:13)(cid:19)(cid:22)(cid:24)(cid:21)(cid:25)(cid:21)(cid:12)(cid:26)(cid:2)(cid:20)(cid:11))(cid:18)(cid:24)(cid:12)+(cid:4)(cid:5)(cid:9)(cid:4).(cid:15)0 Preliminary  2010 Microchip Technology Inc. DS22266A-page 21

MCP7941X (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:10)(cid:8)(cid:17)(cid:18)(cid:12)(cid:10)(cid:13)(cid:19)(cid:5)(cid:8)(cid:20)(cid:15)(cid:21)(cid:22)(cid:8)(cid:23)(cid:8)(cid:21)(cid:6)(cid:24)(cid:24)(cid:25)(cid:26)(cid:27)(cid:8)(cid:28)(cid:29)(cid:30)(cid:31)(cid:8)(cid:16)(cid:16)(cid:8) (cid:25)(cid:7)!(cid:8)"(cid:15)(cid:17)#$% (cid:21)(cid:25)(cid:12)(cid:5)& 2(cid:21)(cid:20)(cid:14)%(cid:22)(cid:13)(cid:14)&(cid:21) %(cid:14)(cid:19)!(cid:20)(cid:20)(cid:13)(cid:24)%(cid:14)(cid:10)(cid:11)(cid:19)3(cid:11)(cid:12)(cid:13)(cid:14)"(cid:20)(cid:11))(cid:18)(cid:24)(cid:12) ’(cid:14)(cid:10)(cid:25)(cid:13)(cid:11) (cid:13)(cid:14) (cid:13)(cid:13)(cid:14)%(cid:22)(cid:13)(cid:14)(cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:14)(cid:30)(cid:11)(cid:19)3(cid:11)(cid:12)(cid:18)(cid:24)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:19)(cid:18)$(cid:18)(cid:19)(cid:11)%(cid:18)(cid:21)(cid:24)(cid:14)(cid:25)(cid:21)(cid:19)(cid:11)%(cid:13)"(cid:14)(cid:11)%(cid:14) (cid:22)%%(cid:10)144)))(cid:28)&(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:28)(cid:19)(cid:21)&4(cid:10)(cid:11)(cid:19)3(cid:11)(cid:12)(cid:18)(cid:24)(cid:12) Preliminary DS22266A-page 22  2010 Microchip Technology Inc.

MCP7941X (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)’((cid:13)(cid:19)(cid:8)(cid:15)((cid:24)(cid:13)(cid:19))(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:10)(cid:8)(cid:17)(cid:18)(cid:12)(cid:10)(cid:13)(cid:19)(cid:5)(cid:8)(cid:20)(cid:15)’(cid:22)(cid:8)(cid:23)(cid:8)*(cid:29)*(cid:8)(cid:16)(cid:16)(cid:8) (cid:25)(cid:7)!(cid:8)"’(cid:15)(cid:15)(cid:17)(cid:9)% (cid:21)(cid:25)(cid:12)(cid:5)& 2(cid:21)(cid:20)(cid:14)%(cid:22)(cid:13)(cid:14)&(cid:21) %(cid:14)(cid:19)!(cid:20)(cid:20)(cid:13)(cid:24)%(cid:14)(cid:10)(cid:11)(cid:19)3(cid:11)(cid:12)(cid:13)(cid:14)"(cid:20)(cid:11))(cid:18)(cid:24)(cid:12) ’(cid:14)(cid:10)(cid:25)(cid:13)(cid:11) (cid:13)(cid:14) (cid:13)(cid:13)(cid:14)%(cid:22)(cid:13)(cid:14)(cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:14)(cid:30)(cid:11)(cid:19)3(cid:11)(cid:12)(cid:18)(cid:24)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:19)(cid:18)$(cid:18)(cid:19)(cid:11)%(cid:18)(cid:21)(cid:24)(cid:14)(cid:25)(cid:21)(cid:19)(cid:11)%(cid:13)"(cid:14)(cid:11)%(cid:14) (cid:22)%%(cid:10)144)))(cid:28)&(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:28)(cid:19)(cid:21)&4(cid:10)(cid:11)(cid:19)3(cid:11)(cid:12)(cid:18)(cid:24)(cid:12) D N E E1 NOTE1 1 2 b e c φ A A2 A1 L1 L 5(cid:24)(cid:18)% (cid:17)(cid:27)66(cid:27)(cid:17)-(cid:23)-(cid:8)(cid:3) (cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)(cid:14)6(cid:18)&(cid:18)% (cid:17)(cid:27)7 78(cid:17) (cid:17)(cid:7)9 7!&((cid:13)(cid:20)(cid:14)(cid:21)$(cid:14)(cid:30)(cid:18)(cid:24) 7 : (cid:30)(cid:18)%(cid:19)(cid:22) (cid:13) (cid:4)(cid:28)>.(cid:14)0(cid:3)+ 8(cid:31)(cid:13)(cid:20)(cid:11)(cid:25)(cid:25)(cid:14);(cid:13)(cid:18)(cid:12)(cid:22)% (cid:7) < < (cid:29)(cid:28)(cid:16)(cid:4) (cid:17)(cid:21)(cid:25)"(cid:13)"(cid:14)(cid:30)(cid:11)(cid:19)3(cid:11)(cid:12)(cid:13)(cid:14)(cid:23)(cid:22)(cid:18)(cid:19)3(cid:24)(cid:13) (cid:7)(cid:16) (cid:4)(cid:28):(cid:4) (cid:29)(cid:28)(cid:4)(cid:4) (cid:29)(cid:28)(cid:4). (cid:3)%(cid:11)(cid:24)"(cid:21)$$(cid:14) (cid:7)(cid:29) (cid:4)(cid:28)(cid:4). < (cid:4)(cid:28)(cid:29). 8(cid:31)(cid:13)(cid:20)(cid:11)(cid:25)(cid:25)(cid:14)=(cid:18)"%(cid:22) - >(cid:28)(cid:5)(cid:4)(cid:14)0(cid:3)+ (cid:17)(cid:21)(cid:25)"(cid:13)"(cid:14)(cid:30)(cid:11)(cid:19)3(cid:11)(cid:12)(cid:13)(cid:14)=(cid:18)"%(cid:22) -(cid:29) (cid:5)(cid:28),(cid:4) (cid:5)(cid:28)(cid:5)(cid:4) (cid:5)(cid:28).(cid:4) (cid:17)(cid:21)(cid:25)"(cid:13)"(cid:14)(cid:30)(cid:11)(cid:19)3(cid:11)(cid:12)(cid:13)(cid:14)6(cid:13)(cid:24)(cid:12)%(cid:22) (cid:2) (cid:16)(cid:28)(cid:6)(cid:4) ,(cid:28)(cid:4)(cid:4) ,(cid:28)(cid:29)(cid:4) 2(cid:21)(cid:21)%(cid:14)6(cid:13)(cid:24)(cid:12)%(cid:22) 6 (cid:4)(cid:28)(cid:5). (cid:4)(cid:28)>(cid:4) (cid:4)(cid:28)(cid:15). 2(cid:21)(cid:21)%(cid:10)(cid:20)(cid:18)(cid:24)% 6(cid:29) (cid:29)(cid:28)(cid:4)(cid:4)(cid:14)(cid:8)-2 2(cid:21)(cid:21)%(cid:14)(cid:7)(cid:24)(cid:12)(cid:25)(cid:13) (cid:3) (cid:4)A < :A 6(cid:13)(cid:11)"(cid:14)(cid:23)(cid:22)(cid:18)(cid:19)3(cid:24)(cid:13) (cid:19) (cid:4)(cid:28)(cid:4)(cid:6) < (cid:4)(cid:28)(cid:16)(cid:4) 6(cid:13)(cid:11)"(cid:14)=(cid:18)"%(cid:22) ( (cid:4)(cid:28)(cid:29)(cid:6) < (cid:4)(cid:28),(cid:4) (cid:21)(cid:25)(cid:12)(cid:5)(cid:11)& (cid:29)(cid:28) (cid:30)(cid:18)(cid:24)(cid:14)(cid:29)(cid:14)(cid:31)(cid:18) !(cid:11)(cid:25)(cid:14)(cid:18)(cid:24)"(cid:13)#(cid:14)$(cid:13)(cid:11)%!(cid:20)(cid:13)(cid:14)&(cid:11)(cid:26)(cid:14)(cid:31)(cid:11)(cid:20)(cid:26)’(cid:14)(!%(cid:14)&! %(cid:14)((cid:13)(cid:14)(cid:25)(cid:21)(cid:19)(cid:11)%(cid:13)"(cid:14))(cid:18)%(cid:22)(cid:18)(cid:24)(cid:14)%(cid:22)(cid:13)(cid:14)(cid:22)(cid:11)%(cid:19)(cid:22)(cid:13)"(cid:14)(cid:11)(cid:20)(cid:13)(cid:11)(cid:28) (cid:16)(cid:28) (cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24) (cid:14)(cid:2)(cid:14)(cid:11)(cid:24)"(cid:14)-(cid:29)(cid:14)"(cid:21)(cid:14)(cid:24)(cid:21)%(cid:14)(cid:18)(cid:24)(cid:19)(cid:25)!"(cid:13)(cid:14)&(cid:21)(cid:25)"(cid:14)$(cid:25)(cid:11) (cid:22)(cid:14)(cid:21)(cid:20)(cid:14)(cid:10)(cid:20)(cid:21)%(cid:20)! (cid:18)(cid:21)(cid:24) (cid:28)(cid:14)(cid:17)(cid:21)(cid:25)"(cid:14)$(cid:25)(cid:11) (cid:22)(cid:14)(cid:21)(cid:20)(cid:14)(cid:10)(cid:20)(cid:21)%(cid:20)! (cid:18)(cid:21)(cid:24) (cid:14) (cid:22)(cid:11)(cid:25)(cid:25)(cid:14)(cid:24)(cid:21)%(cid:14)(cid:13)#(cid:19)(cid:13)(cid:13)"(cid:14)(cid:4)(cid:28)(cid:29).(cid:14)&&(cid:14)(cid:10)(cid:13)(cid:20)(cid:14) (cid:18)"(cid:13)(cid:28) ,(cid:28) (cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)(cid:18)(cid:24)(cid:12)(cid:14)(cid:11)(cid:24)"(cid:14)%(cid:21)(cid:25)(cid:13)(cid:20)(cid:11)(cid:24)(cid:19)(cid:18)(cid:24)(cid:12)(cid:14)(cid:10)(cid:13)(cid:20)(cid:14)(cid:7)(cid:3)(cid:17)-(cid:14)/(cid:29)(cid:5)(cid:28).(cid:17)(cid:28) 0(cid:3)+1 0(cid:11) (cid:18)(cid:19)(cid:14)(cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)(cid:28)(cid:14)(cid:23)(cid:22)(cid:13)(cid:21)(cid:20)(cid:13)%(cid:18)(cid:19)(cid:11)(cid:25)(cid:25)(cid:26)(cid:14)(cid:13)#(cid:11)(cid:19)%(cid:14)(cid:31)(cid:11)(cid:25)!(cid:13)(cid:14) (cid:22)(cid:21))(cid:24)(cid:14))(cid:18)%(cid:22)(cid:21)!%(cid:14)%(cid:21)(cid:25)(cid:13)(cid:20)(cid:11)(cid:24)(cid:19)(cid:13) (cid:28) (cid:8)-21 (cid:8)(cid:13)$(cid:13)(cid:20)(cid:13)(cid:24)(cid:19)(cid:13)(cid:14)(cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)’(cid:14)! !(cid:11)(cid:25)(cid:25)(cid:26)(cid:14))(cid:18)%(cid:22)(cid:21)!%(cid:14)%(cid:21)(cid:25)(cid:13)(cid:20)(cid:11)(cid:24)(cid:19)(cid:13)’(cid:14)$(cid:21)(cid:20)(cid:14)(cid:18)(cid:24)$(cid:21)(cid:20)&(cid:11)%(cid:18)(cid:21)(cid:24)(cid:14)(cid:10)!(cid:20)(cid:10)(cid:21) (cid:13) (cid:14)(cid:21)(cid:24)(cid:25)(cid:26)(cid:28) (cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:23)(cid:13)(cid:19)(cid:22)(cid:24)(cid:21)(cid:25)(cid:21)(cid:12)(cid:26)(cid:2)(cid:20)(cid:11))(cid:18)(cid:24)(cid:12)+(cid:4)(cid:5)(cid:9)(cid:4):>0 Preliminary  2010 Microchip Technology Inc. DS22266A-page 23

MCP7941X (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)+(cid:13)(cid:14)(cid:24)(cid:25)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:10)(cid:8)(cid:17)(cid:18)(cid:12)(cid:10)(cid:13)(cid:19)(cid:5)(cid:8)(cid:9)(cid:6)(cid:14))(cid:6),(cid:5)(cid:8)(cid:20)+(cid:15)(cid:22)(cid:8)"+(cid:15)(cid:17)(cid:9)% (cid:21)(cid:25)(cid:12)(cid:5)& 2(cid:21)(cid:20)(cid:14)%(cid:22)(cid:13)(cid:14)&(cid:21) %(cid:14)(cid:19)!(cid:20)(cid:20)(cid:13)(cid:24)%(cid:14)(cid:10)(cid:11)(cid:19)3(cid:11)(cid:12)(cid:13)(cid:14)"(cid:20)(cid:11))(cid:18)(cid:24)(cid:12) ’(cid:14)(cid:10)(cid:25)(cid:13)(cid:11) (cid:13)(cid:14) (cid:13)(cid:13)(cid:14)%(cid:22)(cid:13)(cid:14)(cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:14)(cid:30)(cid:11)(cid:19)3(cid:11)(cid:12)(cid:18)(cid:24)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:19)(cid:18)$(cid:18)(cid:19)(cid:11)%(cid:18)(cid:21)(cid:24)(cid:14)(cid:25)(cid:21)(cid:19)(cid:11)%(cid:13)"(cid:14)(cid:11)%(cid:14) (cid:22)%%(cid:10)144)))(cid:28)&(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:28)(cid:19)(cid:21)&4(cid:10)(cid:11)(cid:19)3(cid:11)(cid:12)(cid:18)(cid:24)(cid:12) D N E E1 NOTE1 1 2 e b c A A2 φ A1 L1 L 5(cid:24)(cid:18)% (cid:17)(cid:27)66(cid:27)(cid:17)-(cid:23)-(cid:8)(cid:3) (cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)(cid:14)6(cid:18)&(cid:18)% (cid:17)(cid:27)7 78(cid:17) (cid:17)(cid:7)9 7!&((cid:13)(cid:20)(cid:14)(cid:21)$(cid:14)(cid:30)(cid:18)(cid:24) 7 : (cid:30)(cid:18)%(cid:19)(cid:22) (cid:13) (cid:4)(cid:28)>.(cid:14)0(cid:3)+ 8(cid:31)(cid:13)(cid:20)(cid:11)(cid:25)(cid:25)(cid:14);(cid:13)(cid:18)(cid:12)(cid:22)% (cid:7) < < (cid:29)(cid:28)(cid:29)(cid:4) (cid:17)(cid:21)(cid:25)"(cid:13)"(cid:14)(cid:30)(cid:11)(cid:19)3(cid:11)(cid:12)(cid:13)(cid:14)(cid:23)(cid:22)(cid:18)(cid:19)3(cid:24)(cid:13) (cid:7)(cid:16) (cid:4)(cid:28)(cid:15). (cid:4)(cid:28):. (cid:4)(cid:28)(cid:6). (cid:3)%(cid:11)(cid:24)"(cid:21)$$(cid:14) (cid:7)(cid:29) (cid:4)(cid:28)(cid:4)(cid:4) < (cid:4)(cid:28)(cid:29). 8(cid:31)(cid:13)(cid:20)(cid:11)(cid:25)(cid:25)(cid:14)=(cid:18)"%(cid:22) - (cid:5)(cid:28)(cid:6)(cid:4)(cid:14)0(cid:3)+ (cid:17)(cid:21)(cid:25)"(cid:13)"(cid:14)(cid:30)(cid:11)(cid:19)3(cid:11)(cid:12)(cid:13)(cid:14)=(cid:18)"%(cid:22) -(cid:29) ,(cid:28)(cid:4)(cid:4)(cid:14)0(cid:3)+ 8(cid:31)(cid:13)(cid:20)(cid:11)(cid:25)(cid:25)(cid:14)6(cid:13)(cid:24)(cid:12)%(cid:22) (cid:2) ,(cid:28)(cid:4)(cid:4)(cid:14)0(cid:3)+ 2(cid:21)(cid:21)%(cid:14)6(cid:13)(cid:24)(cid:12)%(cid:22) 6 (cid:4)(cid:28)(cid:5)(cid:4) (cid:4)(cid:28)>(cid:4) (cid:4)(cid:28):(cid:4) 2(cid:21)(cid:21)%(cid:10)(cid:20)(cid:18)(cid:24)% 6(cid:29) (cid:4)(cid:28)(cid:6).(cid:14)(cid:8)-2 2(cid:21)(cid:21)%(cid:14)(cid:7)(cid:24)(cid:12)(cid:25)(cid:13) (cid:3) (cid:4)A < :A 6(cid:13)(cid:11)"(cid:14)(cid:23)(cid:22)(cid:18)(cid:19)3(cid:24)(cid:13) (cid:19) (cid:4)(cid:28)(cid:4): < (cid:4)(cid:28)(cid:16), 6(cid:13)(cid:11)"(cid:14)=(cid:18)"%(cid:22) ( (cid:4)(cid:28)(cid:16)(cid:16) < (cid:4)(cid:28)(cid:5)(cid:4) (cid:21)(cid:25)(cid:12)(cid:5)(cid:11)& (cid:29)(cid:28) (cid:30)(cid:18)(cid:24)(cid:14)(cid:29)(cid:14)(cid:31)(cid:18) !(cid:11)(cid:25)(cid:14)(cid:18)(cid:24)"(cid:13)#(cid:14)$(cid:13)(cid:11)%!(cid:20)(cid:13)(cid:14)&(cid:11)(cid:26)(cid:14)(cid:31)(cid:11)(cid:20)(cid:26)’(cid:14)(!%(cid:14)&! %(cid:14)((cid:13)(cid:14)(cid:25)(cid:21)(cid:19)(cid:11)%(cid:13)"(cid:14))(cid:18)%(cid:22)(cid:18)(cid:24)(cid:14)%(cid:22)(cid:13)(cid:14)(cid:22)(cid:11)%(cid:19)(cid:22)(cid:13)"(cid:14)(cid:11)(cid:20)(cid:13)(cid:11)(cid:28) (cid:16)(cid:28) (cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24) (cid:14)(cid:2)(cid:14)(cid:11)(cid:24)"(cid:14)-(cid:29)(cid:14)"(cid:21)(cid:14)(cid:24)(cid:21)%(cid:14)(cid:18)(cid:24)(cid:19)(cid:25)!"(cid:13)(cid:14)&(cid:21)(cid:25)"(cid:14)$(cid:25)(cid:11) (cid:22)(cid:14)(cid:21)(cid:20)(cid:14)(cid:10)(cid:20)(cid:21)%(cid:20)! (cid:18)(cid:21)(cid:24) (cid:28)(cid:14)(cid:17)(cid:21)(cid:25)"(cid:14)$(cid:25)(cid:11) (cid:22)(cid:14)(cid:21)(cid:20)(cid:14)(cid:10)(cid:20)(cid:21)%(cid:20)! (cid:18)(cid:21)(cid:24) (cid:14) (cid:22)(cid:11)(cid:25)(cid:25)(cid:14)(cid:24)(cid:21)%(cid:14)(cid:13)#(cid:19)(cid:13)(cid:13)"(cid:14)(cid:4)(cid:28)(cid:29).(cid:14)&&(cid:14)(cid:10)(cid:13)(cid:20)(cid:14) (cid:18)"(cid:13)(cid:28) ,(cid:28) (cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)(cid:18)(cid:24)(cid:12)(cid:14)(cid:11)(cid:24)"(cid:14)%(cid:21)(cid:25)(cid:13)(cid:20)(cid:11)(cid:24)(cid:19)(cid:18)(cid:24)(cid:12)(cid:14)(cid:10)(cid:13)(cid:20)(cid:14)(cid:7)(cid:3)(cid:17)-(cid:14)/(cid:29)(cid:5)(cid:28).(cid:17)(cid:28) 0(cid:3)+1 0(cid:11) (cid:18)(cid:19)(cid:14)(cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)(cid:28)(cid:14)(cid:23)(cid:22)(cid:13)(cid:21)(cid:20)(cid:13)%(cid:18)(cid:19)(cid:11)(cid:25)(cid:25)(cid:26)(cid:14)(cid:13)#(cid:11)(cid:19)%(cid:14)(cid:31)(cid:11)(cid:25)!(cid:13)(cid:14) (cid:22)(cid:21))(cid:24)(cid:14))(cid:18)%(cid:22)(cid:21)!%(cid:14)%(cid:21)(cid:25)(cid:13)(cid:20)(cid:11)(cid:24)(cid:19)(cid:13) (cid:28) (cid:8)-21 (cid:8)(cid:13)$(cid:13)(cid:20)(cid:13)(cid:24)(cid:19)(cid:13)(cid:14)(cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)’(cid:14)! !(cid:11)(cid:25)(cid:25)(cid:26)(cid:14))(cid:18)%(cid:22)(cid:21)!%(cid:14)%(cid:21)(cid:25)(cid:13)(cid:20)(cid:11)(cid:24)(cid:19)(cid:13)’(cid:14)$(cid:21)(cid:20)(cid:14)(cid:18)(cid:24)$(cid:21)(cid:20)&(cid:11)%(cid:18)(cid:21)(cid:24)(cid:14)(cid:10)!(cid:20)(cid:10)(cid:21) (cid:13) (cid:14)(cid:21)(cid:24)(cid:25)(cid:26)(cid:28) (cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:23)(cid:13)(cid:19)(cid:22)(cid:24)(cid:21)(cid:25)(cid:21)(cid:12)(cid:26)(cid:2)(cid:20)(cid:11))(cid:18)(cid:24)(cid:12)+(cid:4)(cid:5)(cid:9)(cid:29)(cid:29)(cid:29)0 Preliminary DS22266A-page 24  2010 Microchip Technology Inc.

MCP7941X (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)-(cid:18)(cid:6)(cid:10)(cid:8).(cid:10)(cid:6)(cid:12)(cid:27)(cid:8)(cid:21)(cid:25)(cid:8)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:14))(cid:6),(cid:5)(cid:8)(cid:20)+(cid:21)(cid:22)(cid:8)(cid:23)(cid:8)/0(cid:28)0(cid:31)(cid:29)12(cid:8)(cid:16)(cid:16)(cid:8) (cid:25)(cid:7)!(cid:8)"’-.(cid:21)% (cid:21)(cid:25)(cid:12)(cid:5)& 2(cid:21)(cid:20)(cid:14)%(cid:22)(cid:13)(cid:14)&(cid:21) %(cid:14)(cid:19)!(cid:20)(cid:20)(cid:13)(cid:24)%(cid:14)(cid:10)(cid:11)(cid:19)3(cid:11)(cid:12)(cid:13)(cid:14)"(cid:20)(cid:11))(cid:18)(cid:24)(cid:12) ’(cid:14)(cid:10)(cid:25)(cid:13)(cid:11) (cid:13)(cid:14) (cid:13)(cid:13)(cid:14)%(cid:22)(cid:13)(cid:14)(cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:14)(cid:30)(cid:11)(cid:19)3(cid:11)(cid:12)(cid:18)(cid:24)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:19)(cid:18)$(cid:18)(cid:19)(cid:11)%(cid:18)(cid:21)(cid:24)(cid:14)(cid:25)(cid:21)(cid:19)(cid:11)%(cid:13)"(cid:14)(cid:11)%(cid:14) (cid:22)%%(cid:10)144)))(cid:28)&(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:28)(cid:19)(cid:21)&4(cid:10)(cid:11)(cid:19)3(cid:11)(cid:12)(cid:18)(cid:24)(cid:12) Preliminary  2010 Microchip Technology Inc. DS22266A-page 25

MCP7941X (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)-(cid:18)(cid:6)(cid:10)(cid:8).(cid:10)(cid:6)(cid:12)(cid:27)(cid:8)(cid:21)(cid:25)(cid:8)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:14))(cid:6),(cid:5)(cid:8)(cid:20)+(cid:21)(cid:22)(cid:8)(cid:23)(cid:8)/0(cid:28)0(cid:31)(cid:29)12(cid:8)(cid:16)(cid:16)(cid:8) (cid:25)(cid:7)!(cid:8)"’-.(cid:21)% (cid:21)(cid:25)(cid:12)(cid:5)& 2(cid:21)(cid:20)(cid:14)%(cid:22)(cid:13)(cid:14)&(cid:21) %(cid:14)(cid:19)!(cid:20)(cid:20)(cid:13)(cid:24)%(cid:14)(cid:10)(cid:11)(cid:19)3(cid:11)(cid:12)(cid:13)(cid:14)"(cid:20)(cid:11))(cid:18)(cid:24)(cid:12) ’(cid:14)(cid:10)(cid:25)(cid:13)(cid:11) (cid:13)(cid:14) (cid:13)(cid:13)(cid:14)%(cid:22)(cid:13)(cid:14)(cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:14)(cid:30)(cid:11)(cid:19)3(cid:11)(cid:12)(cid:18)(cid:24)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:19)(cid:18)$(cid:18)(cid:19)(cid:11)%(cid:18)(cid:21)(cid:24)(cid:14)(cid:25)(cid:21)(cid:19)(cid:11)%(cid:13)"(cid:14)(cid:11)%(cid:14) (cid:22)%%(cid:10)144)))(cid:28)&(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:28)(cid:19)(cid:21)&4(cid:10)(cid:11)(cid:19)3(cid:11)(cid:12)(cid:18)(cid:24)(cid:12) Preliminary DS22266A-page 26  2010 Microchip Technology Inc.

MCP7941X APPENDIX A: REVISION HISTORY Revision A (10/2010) Original release of this document. Preliminary  2010 Microchip Technology Inc. DS22266A-page 27

MCP7941X NOTES: Preliminary DS22266A-page 28  2010 Microchip Technology Inc.

MCP7941X THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following • Field Application Engineer (FAE) information: • Technical Support • Product Support – Data sheets and errata, • Development Systems Information Line application notes and sample programs, design resources, user’s guides and hardware support Customers should contact their distributor, documents, latest software releases and archived representative or field application engineer (FAE) for software support. Local sales offices are also available to help • General Technical Support – Frequently Asked customers. A listing of sales offices and locations is Questions (FAQ), technical support requests, included in the back of this document. online discussion groups, Microchip consultant Technical support is available through the web site program member listing at: http://support.microchip.com • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions. Preliminary  2010 Microchip Technology Inc. DS22266A-page 29

MCP7941X READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480)792-4150. Please list the following information, and use this outline to provide us with your comments about this document. TO: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: MCP7941X Literature Number: DS22266A Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? Preliminary DS22266A-page 30  2010 Microchip Technology Inc.

MCP7941X PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Not every possible ordering combination is listed below. PART NO. X /XX Examples: Device Temperature Package a) MCP79410-I/SN: Industrial Tempera- Range ture, SOIC package. b) MCP79410T-I/SN: Industrial Tempera- Device: MCP79410 = 1.8V - 5.5V I2C™ Serial RTCC ture, SOIC package, Tape and Reel. MCP79410T= 1.8V - 5.5V I2C Serial RTCC c) MCP79410-I/MNY001: Industrial Tem- MCP79411 = 1.8V - 5.5V I2C Serial RTCC, EUI-48TM perature, TDFN package, Custom ID. MCP79411T= 1.8V - 5.5V I2C Serial RTCC, EUI-48TM d) MCP79411-I/SN: Industrial Temperature, (Tape and Reel) SOIC package, EUI-48TM. MCP79412 = 1.8V - 5.5V I2C Serial RTCC, EUI-64TM e) MCP79411-I/MS: Industrial Temperature MCP79412T= 1.8V - 5.5V I2C Serial RTCC, EUI-64TM MSOP package, EUI-48TM. (Tape and Reel) f) MCP79412-I/SN: Industrial Tempera- ture, SOIC package, EUI-64TM. Temperature I = -40°C to +85°C g) MCP79412-I/ST: Industrial Temperature, Range: TSSOP package, EUI-64TM. h) MCP79412T-I/ST: Industrial Temperature, Package: SN = 8-Lead Plastic Small Outline (3.90 mm body) TSSOP package, Tape and Reel, EUI-64TM. ST = 8-Lead Plastic Thin Shrink Small Outline (4.4 mm) MS = 8-Lead Plastic Micro Small Outline MNY(1)= 8-Lead Plastic Dual Flat, No Lead Note 1: ’Y’ indicates a Nickel Palladium Gold (NiPdAu) finish. Preliminary  2010 Microchip Technology Inc. DS22266A-page 31

MCP7941X NOTES: Preliminary DS22266A-page 32  2010 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. PIC32 logo, rfPIC and UNI/O are registered trademarks of MICROCHIP MAKES NO REPRESENTATIONS OR Microchip Technology Incorporated in the U.S.A. and other WARRANTIES OF ANY KIND WHETHER EXPRESS OR countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MXDEV, MXLAB, SEEVAL and The Embedded Control QUALITY, PERFORMANCE, MERCHANTABILITY OR Solutions Company are registered trademarks of Microchip FITNESS FOR PURPOSE. Microchip disclaims all liability Technology Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, CodeGuard, devices in life support and/or safety applications is entirely at dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, the buyer’s risk, and the buyer agrees to defend, indemnify and ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial hold harmless Microchip from any and all damages, claims, Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified suits, or expenses resulting from such use. No licenses are logo, MPLIB, MPLINK, mTouch, Omniscient Code conveyed, implicitly or otherwise, under any Microchip Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, intellectual property rights. PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2010, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-60932-607-4 Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. Preliminary  2010 Microchip Technology Inc. DS22266A-page 33

Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office Asia Pacific Office India - Bangalore Austria - Wels 2355 West Chandler Blvd. Suites 3707-14, 37th Floor Tel: 91-80-3090-4444 Tel: 43-7242-2244-39 Chandler, AZ 85224-6199 Tower 6, The Gateway Fax: 91-80-3090-4123 Fax: 43-7242-2244-393 Tel: 480-792-7200 Harbour City, Kowloon India - New Delhi Denmark - Copenhagen Fax: 480-792-7277 Hong Kong Tel: 91-11-4160-8631 Tel: 45-4450-2828 Technical Support: Tel: 852-2401-1200 Fax: 91-11-4160-8632 Fax: 45-4485-2829 http://support.microchip.com Web Address: Fax: 852-2401-3431 India - Pune France - Paris www.microchip.com Australia - Sydney Tel: 91-20-2566-1512 Tel: 33-1-69-53-63-20 Tel: 61-2-9868-6733 Fax: 91-20-2566-1513 Fax: 33-1-69-30-90-79 ADtullaunthta, GA Fax: 61-2-9868-6755 Japan - Yokohama Germany - Munich Tel: 678-957-9614 China - Beijing Tel: 81-45-471- 6166 Tel: 49-89-627-144-0 Tel: 86-10-8528-2100 Fax: 49-89-627-144-44 Fax: 678-957-1455 Fax: 81-45-471-6122 Fax: 86-10-8528-2104 Italy - Milan Boston Korea - Daegu Westborough, MA China - Chengdu Tel: 82-53-744-4301 Tel: 39-0331-742611 Tel: 774-760-0087 Tel: 86-28-8665-5511 Fax: 82-53-744-4302 Fax: 39-0331-466781 Fax: 774-760-0088 Fax: 86-28-8665-7889 Korea - Seoul Netherlands - Drunen Chicago China - Chongqing Tel: 82-2-554-7200 Tel: 31-416-690399 Itasca, IL Tel: 86-23-8980-9588 Fax: 82-2-558-5932 or Fax: 31-416-690340 Tel: 630-285-0071 Fax: 86-23-8980-9500 82-2-558-5934 Spain - Madrid Fax: 630-285-0075 China - Hong Kong SAR Malaysia - Kuala Lumpur Tel: 34-91-708-08-90 Cleveland Tel: 852-2401-1200 Tel: 60-3-6201-9857 Fax: 34-91-708-08-91 Independence, OH Fax: 852-2401-3431 Fax: 60-3-6201-9859 UK - Wokingham Tel: 216-447-0464 China - Nanjing Malaysia - Penang Tel: 44-118-921-5869 Fax: 216-447-0643 Tel: 86-25-8473-2460 Tel: 60-4-227-8870 Fax: 44-118-921-5820 Dallas Fax: 86-25-8473-2470 Fax: 60-4-227-4068 Addison, TX China - Qingdao Philippines - Manila Tel: 972-818-7423 Tel: 86-532-8502-7355 Tel: 63-2-634-9065 Fax: 972-818-2924 Fax: 86-532-8502-7205 Fax: 63-2-634-9069 Detroit China - Shanghai Singapore Farmington Hills, MI Tel: 86-21-5407-5533 Tel: 65-6334-8870 Tel: 248-538-2250 Fax: 86-21-5407-5066 Fax: 65-6334-8850 Fax: 248-538-2260 China - Shenyang Taiwan - Hsin Chu Kokomo Tel: 86-24-2334-2829 Tel: 886-3-6578-300 Kokomo, IN Fax: 86-24-2334-2393 Fax: 886-3-6578-370 Tel: 765-864-8360 Fax: 765-864-8387 China - Shenzhen Taiwan - Kaohsiung Tel: 86-755-8203-2660 Tel: 886-7-213-7830 Los Angeles Fax: 86-755-8203-1760 Fax: 886-7-330-9305 Mission Viejo, CA Tel: 949-462-9523 China - Wuhan Taiwan - Taipei Tel: 86-27-5980-5300 Tel: 886-2-2500-6610 Fax: 949-462-9608 Fax: 86-27-5980-5118 Fax: 886-2-2508-0102 Santa Clara China - Xian Thailand - Bangkok Santa Clara, CA Tel: 408-961-6444 Tel: 86-29-8833-7252 Tel: 66-2-694-1351 Fax: 408-961-6445 Fax: 86-29-8833-7256 Fax: 66-2-694-1350 China - Xiamen Toronto Mississauga, Ontario, Tel: 86-592-2388138 Canada Fax: 86-592-2388130 Tel: 905-673-0699 China - Zhuhai Fax: 905-673-6509 Tel: 86-756-3210040 Fax: 86-756-3210049 08/04/10 Preliminary DS22266A-page 34  2010 Microchip Technology Inc.

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: MCP79410-I/MS MCP79410-I/SN MCP79410-I/ST MCP79410T-I/MNY MCP79410T-I/MS MCP79410T-I/SN MCP79410T-I/ST MCP79411-I/MS MCP79411-I/SN MCP79411-I/ST MCP79411T-I/MNY MCP79411T-I/MS MCP79411T-I/SN MCP79411T-I/ST MCP79412-I/MS MCP79412-I/SN MCP79412-I/ST MCP79412T-I/MNY MCP79412T-I/MS MCP79412T-I/SN MCP79412T-I/ST