MCP7940N 2 Battery-Backed I C Real-Time Clock/Calendar with SRAM Timekeeping Features Operating Ranges • Real-Time Clock/Calendar (RTCC): • 2-Wire Serial Interface, I2C Compatible - Hours, Minutes, Seconds, Day of Week, Day, - I2C clock rate up to 400 kHz Month, Year • Temperature Range: - Leap year compensated to 2399 - Industrial (I): -40°C to +85°C - 12/24 hour modes - Extended (E): -40°C to +125°C • Oscillator for 32.768 kHz Crystals: • Automotive AEC-Q100 Qualified - Optimized for 6-9 pF crystals Packages • On-Chip Digital Trimming/Calibration: • 8-Lead SOIC, MSOP, TSSOP, PDIP and 2x3 - ±1 PPM resolution TDFN - ±129 PPM range General Description • Dual Programmable Alarms The MCP7940N Real-Time Clock/Calendar (RTCC) • Versatile Output Pin: tracks time using internal counters for hours, minutes, - Clock output with selectable frequency seconds, days, months, years, and day of week. - Alarm output Alarms can be configured on all counters up to and - General purpose output including months. For usage and configuration, the • Power-Fail Time-Stamp: MCP7940N supports I2C communications up to 400 kHz. - Time logged on switchover to and from Battery mode The open-drain, multi-functional output can be Low-Power Features configured to assert on an alarm match, to output a selectable frequency square wave, or as a general • Wide Voltage Range: purpose output. - Operating voltage range of 1.8V to 5.5V The MCP7940N is designed to operate using a 32.768 - Backup voltage range of 1.3V to 5.5V kHz tuning fork crystal with external crystal load • Low Typical Timekeeping Current: capacitors. On-chip digital trimming can be used to - Operating from VCC: 1.2 μA at 3.3V adjust for frequency variance caused by crystal tolerance and temperature. - Operating from battery backup: 925 nA at 3.0V SRAM and timekeeping circuitry are powered from the • Automatic Switchover to Battery Backup back-up supply when main power is lost, allowing the device to maintain accurate time and the SRAM User Memory contents. The times when the device switches over to • 64-byte Battery-Backed SRAM the back-up supply and when primary power returns are both logged by the power-fail time-stamp. Package Types SOIC, MSOP, TSSOP(1), PDIP(1) TDFN(1) X1 1 8 VCC X1 1 8 VCC X2 2 7 MFP X2 2 7 MFP VBAT 3 6 SCL VBAT 3 6 SCL VSS 4 5 SDA VSS 4 5 SDA Note1: Available in I-temp only.  2011-2019 Microchip Technology Inc. DS20005010H-page 1

MCP7940N FIGURE 1-1: TYPICAL APPLICATION SCHEMATIC VCC VCC VCC 8 VCC 1 CX1 X1 Z H 6 K SCL 8 6 7 PIC® MCU 5 MCP7940N 2 32. CX2 SDA X2 7 3 MFP VBAT VBAT VSS 4 FIGURE 1-2: BLOCK DIAGRAM VCC Power Control Power-Fail VSS and Switchover Time-Stamp VBAT SCL I2C Interface Control Logic Configuration and Addressing SDA Seconds SRAM Minutes X1 32.768 kHz Hours Clock Divider Oscillator X2 Day of Week Digital Trimming Date Square Wave Month Alarms Output Year MFP Output Logic  2011-2019 Microchip Technology Inc. DS20005010H-page 2

MCP7940N 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) VCC.............................................................................................................................................................................6.5V All inputs and outputs (except SDA and SCL) w.r.t. VSS.....................................................................-0.6V to VCC +1.0V SDA and SCL w.r.t. VSS...............................................................................................................................-0.6V to 6.5V Storage temperature...............................................................................................................................-65°C to +150°C Ambient temperature with power applied................................................................................................-40°C to +125°C ESD protection on all pins......................................................................................................................................................≥ 4 kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-1: DC CHARACTERISTICS Electrical Characteristics: DC CHARACTERISTICS Industrial (I): VCC = +1.8V to 5.5V TA = -40°C to +85°C Extended (E): VCC = +1.8V to 5.5V TA = -40°C to +125°C Param. Sym. Characteristic Min. Typ.(2) Max. Units Conditions No. D1 VIH High-level input voltage 0.7 VCC — — V — D2 VIL Low-level input voltage — — 0.3 VCC V VCC ≥ 2.5V 0.2 VCC V VCC < 2.5V D3 VHYS Hysteresis of Schmitt 0.05 — — V (Note1) Trigger inputs VCC (SDA, SCL pins) D4 VOL Low-level output voltage — — 0.40 V IOL = 3.0mA @ VCC = 4.5V (MFP, SDA pins) IOL = 2.1mA @ VCC = 2.5V D5 ILI Input leakage current — — ±1 μA VIN = VSS or VCC D6 ILO Output leakage current — — ±1 μA VOUT = VSS or VCC D7 CIN, Pin capacitance — — 10 pF VCC = 5.0V (Note1) COUT (SDA, SCL, MFP pins) TA = 25°C, f = 1 MHz D8 COSC Oscillator pin — 3 — pF (Note1) capacitance (X1, X2 pins) D9 ICCREAD SRAM/RTCC register — — 300 μA VCC = 5.5V, SCL = 400kHz ICCWRITE operating current — — 400 μA VCC = 5.5V, SCL = 400kHz D10 ICCDAT VCC data-retention — — 1 μA SCL, SDA, VCC = 5.5V (I-Temp) current (oscillator off) — — 5 μA SCL, SDA, VCC = 5.5V (E-temp) D11 ICCT Timekeeping current — 1.2 — μA VCC = 3.3V (Note1) D12 VTRIP Power-fail switchover 1.3 1.5 1.7 V — voltage D13 VBAT Backup supply voltage 1.3 — 5.5 V (Note1) range D14 IBATT Timekeeping backup — — 850 nA VBAT = 1.3V, VCC = VSS (Note1) current 925 1200 nA VBAT = 3.0V, VCC = VSS (Note1) 9000 nA VBAT = 5.5V, VCC = VSS (Note1) Note 1: This parameter is not tested but ensured by characterization. 2: Typical measurements taken at room temperature.  2011-2019 Microchip Technology Inc. DS20005010H-page 3

MCP7940N Electrical Characteristics: DC CHARACTERISTICS (Continued) Industrial (I): VCC = +1.8V to 5.5V TA = -40°C to +85°C Extended (E): VCC = +1.8V to 5.5V TA = -40°C to +125°C Param. Sym. Characteristic Min. Typ.(2) Max. Units Conditions No. D15 IBATDAT VBAT data retention — — 750 nA VBAT = 3.6V, VCC = VSS current (oscillator off) Note 1: This parameter is not tested but ensured by characterization. 2: Typical measurements taken at room temperature.  2011-2019 Microchip Technology Inc. DS20005010H-page 4

MCP7940N TABLE 1-2: AC CHARACTERISTICS Electrical Characteristics: AC CHARACTERISTICS Industrial (I): VCC = +1.8V to 5.5V TA = -40°C to +85°C Extended (E): VCC = +1.8V to 5.5V TA = -40°C to +125°C Param. Symbol Characteristic Min. Typ. Max. Units Conditions No. 1 FCLK Clock frequency — — 100 kHz 1.8V ≤ VCC < 2.5V — — 400 2.5V ≤ VCC ≤ 5.5V 2 THIGH Clock high time 4000 — — ns 1.8V ≤ VCC < 2.5V 600 — — 2.5V ≤ VCC ≤ 5.5V 3 TLOW Clock low time 4700 — — ns 1.8V ≤ VCC < 2.5V 1300 — — 2.5V ≤ VCC ≤ 5.5V 4 TR SDA and SCL rise time — — 1000 ns 1.8V ≤ VCC < 2.5V (Note1) — — 300 2.5V ≤ VCC ≤ 5.5V 5 TF SDA and SCL fall time — — 1000 ns 1.8V ≤ VCC < 2.5V (Note1) — — 300 2.5V ≤ VCC ≤ 5.5V 6 THD:STA Start condition hold time 4000 — — ns 1.8V ≤ VCC < 2.5V 600 — — 2.5V ≤ VCC ≤ 5.5V 7 TSU:STA Start condition setup time 4700 — — ns 1.8V ≤ VCC < 2.5V 600 — — 2.5V ≤ VCC ≤ 5.5V 8 THD:DAT Data input hold time 0 — — ns (Note2) 9 TSU:DAT Data input setup time 250 — — ns 1.8V ≤ VCC < 2.5V 100 — — 2.5V ≤ VCC ≤ 5.5V 10 TSU:STO Stop condition setup time 4000 — — ns 1.8V ≤ VCC < 2.5V 600 — — 2.5V ≤ VCC ≤ 5.5V 11 TAA Output valid from clock — — 3500 ns 1.8V ≤ VCC < 2.5V — — 900 2.5V ≤ VCC ≤ 5.5V 12 TBUF Bus free time: Time the bus 4700 — — ns 1.8V ≤ VCC < 2.5V must be free before a new 1300 — — 2.5V ≤ VCC ≤ 5.5V transmission can start 13 TSP Input filter spike suppression — — 50 ns (Note1) (SDA and SCL pins) 14 TFVCC VCC fall time 300 — — μs (Note1) 15 TRVCC VCC rise time 0 — — μs (Note1) 16 FOSC Oscillator frequency — 32.768 — kHz — 17 TOSF Oscillator timeout period 1 — — ms (Note1) Note 1: Not 100% tested. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.  2011-2019 Microchip Technology Inc. DS20005010H-page 5

MCP7940N FIGURE 1-3: I2C BUS TIMING DATA 5 4 2 D3 SCL 7 3 8 9 10 SDA 6 In 13 11 12 SDA Out FIGURE 1-4: POWER SUPPLY TRANSITION TIMING VCC VTRIP(MAX) VTRIP(MIN) 14 15  2011-2019 Microchip Technology Inc. DS20005010H-page 6

MCP7940N 2.0 TYPICAL PERFORMANCE CURVE Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data represented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. FIGURE 2-1: TIMEKEEPING BACKUP CURRENT VS. BACKUP SUPPLY VOLTAGE 5.5 5.0 A) 44..05 -284550 TTT AAA === -284550°°°CCC nt (µ33..05 e urr2.5 C2.0 T AT 1.5 IB 1.0 0.5 0.0 1.30 1.90 2.50 3.10 3.70 4.30 4.90 5.50 VBAT Voltage (V)  2011-2019 Microchip Technology Inc. DS20005010H-page 7

MCP7940N 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table3-1. TABLE 3-1: PIN FUNCTION TABLE 8-pin 8-pin 8-pin 8-pin 8-pin Name Function SOIC MSOP TSSOP TDFN PDIP X1 1 1 1 1 1 Quartz Crystal Input, External Oscillator Input X2 2 2 2 2 2 Quartz Crystal Output VBAT 3 3 3 3 3 Battery Backup Supply Input Vss 4 4 4 4 4 Ground SDA 5 5 5 5 5 Bidirectional Serial Data (I2C) SCL 6 6 6 6 6 Serial Clock (I2C) MFP 7 7 7 7 7 Multifunction Pin Vcc 8 8 8 8 8 Primary Power Supply Note: Exposed pad on TFDN can be connected to Vss or left floating. 3.1 Serial Data (SDA) 3.5 Backup Supply (VBAT) This is a bidirectional pin used to transfer addresses This is the input for a backup supply to maintain the and data into and out of the device. It is an open-drain RTCC and SRAM registers during the time when VCC terminal. Therefore, the SDA bus requires a pull-up is unavailable. resistor to VCC (typically 10kΩ for 100kHz, 2kΩ for If the battery backup feature is not being used, the 400kHz). For normal data transfer, SDA is allowed to VBAT pin should be connected to VSS. change only during SCL low. Changes during SCL high are reserved for indicating the Start and Stop conditions. 3.2 Serial Clock (SCL) This input is used to synchronize the data transfer to and from the device. 3.3 Oscillator Input/Output (X1, X2) These pins are used as the connections for an external 32.768 kHz quartz crystal and load capacitors. X1 is the crystal oscillator input and X2 is the output. The MCP7940N is designed to allow for the use of external load capacitors in order to provide additional flexibility when choosing external crystals. The MCP7940N is optimized for crystals with a specified load capacitance of 6-9 pF. X1 also serves as the external clock input when the MCP7940N is configured to use an external oscillator. 3.4 Multifunction Pin (MFP) This is an output pin used for the alarm and square wave output functions. It can also serve as a general purpose output pin by controlling the OUT bit in the CONTROL register. The MFP is an open-drain output and requires a pull-up resistor to Vcc (typically 10 kΩ). This pin may be left floating if not used.  2011-2019 Microchip Technology Inc. DS20005010H-page 8

MCP7940N 4.0 I2C BUS CHARACTERISTICS 4.1.1.3 Stop Data Transfer (C) A low-to-high transition of the SDA line while the clock 4.1 I2C Interface (SCL) is high determines a Stop condition. All operations must end with a Stop condition. The MCP7940N supports a bidirectional 2-wire bus and data transmission protocol. A device that sends 4.1.1.4 Data Valid (D) data onto the bus is defined as transmitter, and a device receiving data as receiver. The bus has to be The state of the data line represents valid data when, controlled by a master device which generates the Start after a Start condition, the data line is stable for the and Stop conditions, while the MCP7940N works as duration of the high period of the clock signal. slave. Both master and slave can operate as The data on the line must be changed during the low transmitter or receiver but the master device period of the clock signal. There is one bit of data per determines which mode is activated. clock pulse. 4.1.1 BUS CHARACTERISTICS Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of the The following bus protocol has been defined: data bytes transferred between the Start and Stop • Data transfer may be initiated only when the bus conditions is determined by the master device. is not busy. 4.1.1.5 Acknowledge • During data transfer, the data line must remain stable whenever the clock line is high. Changes in Each receiving device, when addressed, is obliged to the data line while the clock line is high will be generate an Acknowledge signal after the reception of interpreted as a Start or Stop condition. each byte. The master device must generate an extra clock pulse which is associated with this Acknowledge Accordingly, the following bus conditions have been bit. defined (Figure4-1). Note: The I2C interface is disabled while operat- 4.1.1.1 Bus Not Busy (A) ing from the backup power supply. Both data and clock lines remain high. A device that acknowledges must pull down the SDA 4.1.1.2 Start Data Transfer (B) line during the Acknowledge clock pulse in such a way that the SDA line is stable-low during the high period of A high-to-low transition of the SDA line while the clock the Acknowledge-related clock pulse. Of course, setup (SCL) is high determines a Start condition. All and hold times must be taken into account. During commands must be preceded by a Start condition. reads, a master must signal an end of data to the slave by NOT generating an Acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave (MCP7940N) will leave the data line high to enable the master to generate the Stop condition. FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS (A) (B) (D) (D) (C) (A) SCL SDA Start Address or Data Stop Condition Acknowledge Allowed Condition Valid to Change  2011-2019 Microchip Technology Inc. DS20005010H-page 9

MCP7940N FIGURE 4-2: ACKNOWLEDGE TIMING Acknowledge Bit SCL 1 2 3 4 5 6 7 8 9 1 2 3 SDA Data from transmitter Data from transmitter Transmitter must release the SDA line at this point Receiver must release the SDA line at this point allowing the Receiver to pull the SDA line low to so the Transmitter can continue sending data. acknowledge the previous eight bits of data. 4.1.2 DEVICE ADDRESSING FIGURE 4-3: CONTROL BYTE FORMAT The control byte is the first byte received following the Acknowledge Bit Start condition from the master device (Figure4-3). The control byte begins with a 4-bit control code. For Read/Write Bit the MCP7940N, this is set ‘1101’ for register read and Start Bit write operations. The next three bits are non-config- Chip Select urable Chip Select bits that must always be set to ‘1’. Control Code Bits The last bit of the control byte defines the operation to be performed. When set to a ‘1’ a read operation is S 1 1 0 1 1 1 1 R/W ACK selected, and when set to a ‘0’ a write operation is selected. RTCC Register/SRAM Control Byte The combination of the 4-bit control code and the three Chip Select bits is called the slave address. Upon receiving a valid slave address, the slave device out- puts an acknowledge signal on the SDA line. Depend- ing on the state of the R/W bit, the MCP7940N will select a read or a write operation.  2011-2019 Microchip Technology Inc. DS20005010H-page 10

MCP7940N 5.0 FUNCTIONAL DESCRIPTION 5.1 Memory Organization The MCP7940N is a highly-integrated Real-Time The MCP7940N features two different blocks of mem- Clock/Calendar (RTCC). Using an on-board, low- ory: the RTCC registers and general purpose SRAM power oscillator, the current time is maintained in sec- (Figure5-1). They share the same address space, onds, minutes, hours, day of week, date, month, and accessed through the ‘1101111X’ control byte. year. The MCP7940N also features 64 bytes of general Unused locations are not accessible. The MCP7940N purpose SRAM. Two alarm modules allow interrupts to will not acknowledge if the address is out of range, as be generated at specific times with flexible comparison shown in the shaded region of the memory map in options. Digital trimming can be used to compensate Figure5-1. for inaccuracies inherent with crystals. Using the The RTCC registers are contained in addresses 0x00- backup supply input and an integrated power switch, 0x1F. Table5-1 shows the detailed RTCC register map. the MCP7940N will automatically switch to backup There are 64 bytes of user-accessible SRAM, located power when primary power is unavailable, allowing the in the address range 0x20-0x5F. The SRAM is a sepa- current time and the SRAM contents to be maintained. rate block from the RTCC registers. All RTCC registers The time-stamp module captures the time when pri- and SRAM locations are maintained while operating mary power is lost and when it is restored. from backup power. The RTCC configuration and Status registers are used to access all of the modules featured on the MCP7940N. FIGURE 5-1: MEMORY MAP RTCC Registers/SRAM 0x00 Time and Date 0x06 0x07 Configuration and Trimming 0x09 0x0A Alarm 0 0x10 0x11 Alarm 1 0x17 0x18 Power-Fail/Power-Up Time-Stamps 0x1F 0x20 SRAM (64 Bytes) 0x5F 0x60 Unimplemented; device does not ACK 0xFF I2C Address: 1101111x  2011-2019 Microchip Technology Inc. DS20005010H-page 11

MCP7940N TABLE 5-1: DETAILED RTCC REGISTER MAP Addr. Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Section5.3 “Timekeeping” 00h RTCSEC ST SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 01h RTCMIN — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 02h RTCHOUR — 12/24 AM/PM HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 HRTEN1 03h RTCWKDAY — — OSCRUN PWRFAIL VBATEN WKDAY2 WKDAY1 WKDAY0 04h RTCDATE — — DATETEN1 DATETEN0 DATEONE3 DATEONE2 DATEONE1 DATEONE0 05h RTCMTH — — LPYR MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 06h RTCYEAR YRTEN3 YRTEN2 YRTEN1 YRTEN0 YRONE3 YRONE2 YRONE1 YRONE0 07h CONTROL OUT SQWEN ALM1EN ALM0EN EXTOSC CRSTRIM SQWFS1 SQWFS0 08h OSCTRIM SIGN TRIMVAL6 TRIMVAL5 TRIMVAL4 TRIMVAL3 TRIMVAL2 TRIMVAL1 TRIMVAL0 09h Reserved Reserved – Do not use Section5.4 “Alarms” 0Ah ALM0SEC — SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 0Bh ALM0MIN — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 0Ch ALM0HOUR — 12/24(2) AM/PM HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 HRTEN1 0Dh ALM0WKDAY ALMPOL ALM0MSK2 ALM0MSK1 ALM0MSK0 ALM0IF WKDAY2 WKDAY1 WKDAY0 0Eh ALM0DATE — — DATETEN1 DATETEN0 DATEONE3 DATEONE2 DATEONE1 DATEONE0 0Fh ALM0MTH — — — MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 10h Reserved Reserved – Do not use Section5.4 “Alarms” 11h ALM1SEC — SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 12h ALM1MIN — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 13h ALM1HOUR — 12/24(2) AM/PM HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 HRTEN1 14h ALM1WKDAY ALMPOL(3) ALM1MSK2 ALM1MSK1 ALM1MSK0 ALM1IF WKDAY2 WKDAY1 WKDAY0 15h ALM1DATE — — DATETEN1 DATETEN0 DATEONE3 DATEONE2 DATEONE1 DATEONE0 16h ALM1MTH — — — MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 17h Reserved Reserved – Do not use Section5.7.1 “Power-Fail Time-Stamp” 18h PWRDNMIN — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 19h PWRDNHOUR — 12/24 AM/PM HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 HRTEN1 1Ah PWRDNDATE — — DATETEN1 DATETEN0 DATEONE3 DATEONE2 DATEONE1 DATEONE0 1Bh PWRDNMTH WKDAY2 WKDAY1 WKDAY0 MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 Section5.7.1 “Power-Fail Time-Stamp” 1Ch PWRUPMIN — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 1Dh PWRUPHOUR — 12/24 AM/PM HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 HRTEN1 1Eh PWRUPDATE — — DATETEN1 DATETEN0 DATEONE3 DATEONE2 DATEONE1 DATEONE0 1Fh PWRUPMTH WKDAY2 WKDAY1 WKDAY0 MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 Note 1: Grey areas are unimplemented. 2: The 12/24 bits in the ALMxHOUR registers are read-only and reflect the value of the 12/24 bit in the RTCHOUR register. 3: The ALMPOL bit in the ALM1WKDAY register is read-only and reflects the value of the ALMPOL bit in the ALM0WKDAY register.  2011-2019 Microchip Technology Inc. DS20005010H-page 12

MCP7940N 5.2 Oscillator Configuration EQUATION 5-1: LOAD CAPACITANCE CALCULATION The MCP7940N can be operated in two different oscil- lator configurations: using an external crystal or using C ×C an external clock input. CL = -----X---1-------------X---2--+CSTRAY C +C X1 X2 5.2.1 EXTERNAL CRYSTAL The crystal oscillator circuit on the MCP7940N is Where: designed to operate with a standard 32.768 kHz tuning CL = Effective load capacitance fork crystal and matching external load capacitors. By C = Capacitor value on X1+COSC using external load capacitors, the MCP7940N allows X1 C = Capacitor value on X2+COSC for a wide selection of crystals. Suitable crystals have a X2 CSTRAY = PCB stray capacitance load capacitance (CL) of 6-9 pF. Crystals with a load capacitance of 12.5 pF are not recommended. Figure5-2 shows the pin connections when using an 5.2.1.2 Layout Considerations external crystal. The oscillator circuit should be placed on the same FIGURE 5-2: CRYSTAL OPERATION side of the board as the device. Place the oscillator circuit close to the respective oscillator pins. The load capacitors should be placed next to the oscillator MCP7940N itself, on the same side of the board. X1 Use a grounded copper pour around the oscillator cir- cuit to isolate it from surrounding circuits. The CX1 To Internal Logic grounded copper pour should be routed directly to VSS. Do not run any signal traces or power traces inside the Quartz Crystal ST ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. CX2 X2 Layout suggestions are shown in Figure5-3. In-line packages may be handled with a single-sided layout that completely encompasses the oscillator pins. With fine-pitch packages, it is not always possible to com- Note1: The ST bit must be set to enable the pletely surround the pins and components. A suitable crystal oscillator circuit. solution is to tie the broken guard sections to a mirrored 2: Always verify oscillator performance over ground layer. In all cases, the guard trace(s) must be the voltage and temperature range that is returned to ground. expected for the application. For additional information and design guidance on oscillator circuits, refer to these Microchip Application 5.2.1.1 Choosing Load Capacitors Notes, available at the corporate website CL is the effective load capacitance as seen by the (www.microchip.com): crystal, and includes the physical load capacitors, pin • AN1365, “Recommended Usage of Microchip capacitance, and stray board capacitance. Equation5-1 Serial RTCC Devices” can be used to calculate CL. • AN1519, “Recommended Crystals for Microchip C and C are the external load capacitors. They X1 X2 Stand-Alone Real-Time Clock Calendar Devices” must be chosen to match the selected crystal’s speci- fied load capacitance. Note: If the load capacitance is not correctly matched to the chosen crystal’s specified value, the crystal may give a frequency outside of the crystal manufacturer’s specifications.  2011-2019 Microchip Technology Inc. DS20005010H-page 13

MCP7940N FIGURE 5-3: SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT Single-Sided and In-line Layouts: Fine-Pitch (Dual-Sided) Layouts: Copper Pour Oscillator Top Layer Copper Pour (tied to ground) Crystal (tied to ground) Bottom Layer Copper Pour (tied to ground) X1 X1 CX1 CX1 X2 Oscillator GND Crystal CX2 GND CX2 ` X2 DEVICE PINS DEVICE PINS 5.2.2 EXTERNAL CLOCK INPUT 5.2.3 OSCILLATOR FAILURE STATUS A 32.768 kHz external clock source can be connected The MCP7940N features an oscillator failure flag, to the X1 pin (Figure5-4). When using this configura- OSCRUN, that indicates whether or not the oscillator is tion, the X2 pin should be left floating. running. The OSCRUN bit is automatically set after 32 oscillator cycles are detected. If no oscillator cycles are Note: The EXTOSC bit must be set to enable an detected for more than TOSF, then the OSCRUN bit is external clock source. automatically cleared (Figure5-5). This can occur if the oscillator is stopped by clearing the ST bit or due to FIGURE 5-4: EXTERNAL CLOCK INPUT oscillator failure. OPERATION MCP7940N Clock from X1 Ext. Source FIGURE 5-5: OSCILLATOR FAILURE STATUS TIMING DIAGRAM X1 32 Clock Cycles < TOSF TOSF OSCRUN Bit TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH OSCILLATOR CONFIGURATION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page RTCSEC ST SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 16 RTCWKDAY — — OSCRUN PWRFAIL VBATEN WKDAY2 WKDAY1 WKDAY0 18 CONTROL OUT SQWEN ALM1EN ALM0EN EXTOSC CRSTRIM SQWFS1 SQWFS0 26 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by oscillator configuration.  2011-2019 Microchip Technology Inc. DS20005010H-page 14

MCP7940N 5.3 Timekeeping 5.3.1 DIGIT CARRY RULES The MCP7940N maintains the current time and date The following list explains which timer values cause a using an external 32.768 kHz crystal or clock source. digit carry when there is a rollover: Separate registers are used for tracking seconds, min- • Time of day: from 11:59:59 PM to 12:00:00 AM utes, hours, day of week, date, month, and year. The (12-hour mode) or 23:59:59 to 00:00:00 (24-hour MCP7940N automatically adjusts for months with less mode), with a carry to the Date and Weekday than 31 days and compensates for leap years from fields 2001 to 2399. The year is stored as a two-digit value. • Date: carries to the Month field according to Table Both 12-hour and 24-hour time formats are supported 5-3 and are selected using the 12/24 bit. • Weekday: from 7 to 1 with no carry The day of week value counts from 1 to 7, increments • Month: from 12/31 to 01/01 with a carry to the at midnight, and the representation is user-defined (i.e., Year field the MCP7940N does not require 1 to equal Sunday, • Year: from 99 to 00 with no carry etc.). All time and date values are stored in the registers as TABLE 5-3: DAY TO MONTH ROLLOVER binary-coded decimal (BCD) values. The MCP7940N SCHEDULE will continue to maintain the time and date while oper- Month Name Maximum Date ating off the backup supply. 01 January 31 When reading from the timekeeping registers, the reg- 02 February 28 or 29(1) isters are buffered to prevent errors due to rollover of 03 March 31 counters. The following events cause the buffers to be updated: 04 April 30 • When a read is initiated from the RTCC registers 05 May 31 (addresses 0x00 to 0x1F) 06 June 30 • During an RTCC register read operation, when 07 July 31 the register address rolls over from 0x1F to 0x00 08 August 31 The timekeeping registers should be read in a single 09 September 30 operation to utilize the on-board buffers and avoid 10 October 31 rollover issues. 11 November 30 Note1: Loading invalid values into the time and date registers will result in undefined 12 December 31 operation. Note 1: 29 during leap years, otherwise 28. 2: To avoid rollover issues when loading new time and date values, the oscillator/ clock input should be disabled by clearing the ST bit for External Crystal mode and the EXTOSC bit for External Clock Input mode. After waiting for the OSCRUN bit to clear, the new values can be loaded and the ST or EXTOSC bit can then be re-enabled.  2011-2019 Microchip Technology Inc. DS20005010H-page 15

MCP7940N REGISTER 5-1: RTCSEC: TIMEKEEPING SECONDS VALUE REGISTER (ADDRESS 0x00) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ST SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown bit 7 ST: Start Oscillator bit 1 = Oscillator enabled 0 = Oscillator disabled bit 6-4 SECTEN<2:0>: Binary-Coded Decimal Value of Second’s Tens Digit Contains a value from 0 to 5 bit 3-0 SECONE<3:0>: Binary-Coded Decimal Value of Second’s Ones Digit Contains a value from 0 to 9  2011-2019 Microchip Technology Inc. DS20005010H-page 16

MCP7940N REGISTER 5-2: RTCMIN: TIMEKEEPING MINUTES VALUE REGISTER (ADDRESS 0x01) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-4 MINTEN<2:0>: Binary-Coded Decimal Value of Minute’s Tens Digit Contains a value from 0 to 5 bit 3-0 MINONE<3:0>: Binary-Coded Decimal Value of Minute’s Ones Digit Contains a value from 0 to 9 REGISTER 5-3: RTCHOUR: TIMEKEEPING HOURS VALUE REGISTER (ADDRESS 0x02) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — 12/24 AM/PM HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 HRTEN1 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown If 12/24 = 1 (12-hour format): bit 7 Unimplemented: Read as ‘0’ bit 6 12/24: 12 or 24 Hour Time Format bit 1 = 12-hour format 0 = 24-hour format bit 5 AM/PM: AM/PM Indicator bit 1 = PM 0 = AM bit 4 HRTEN0: Binary-Coded Decimal Value of Hour’s Tens Digit Contains a value from 0 to 1 bit 3-0 HRONE<3:0>: Binary-Coded Decimal Value of Hour’s Ones Digit Contains a value from 0 to 9 If 12/24 = 0 (24-hour format): bit 7 Unimplemented: Read as ‘0’ bit 6 12/24: 12 or 24 Hour Time Format bit 1 = 12-hour format 0 = 24-hour format bit 5-4 HRTEN<1:0>: Binary-Coded Decimal Value of Hour’s Tens Digit Contains a value from 0 to 2. bit 3-0 HRONE<3:0>: Binary-Coded Decimal Value of Hour’s Ones Digit Contains a value from 0 to 9  2011-2019 Microchip Technology Inc. DS20005010H-page 17

MCP7940N REGISTER 5-4: RTCWKDAY: TIMEKEEPING WEEKDAY VALUE REGISTER (ADDRESS 0x03) U-0 U-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 — — OSCRUN PWRFAIL VBATEN WKDAY2 WKDAY1 WKDAY0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5 OSCRUN: Oscillator Status bit 1 = Oscillator is enabled and running 0 = Oscillator has stopped or has been disabled bit 4 PWRFAIL: Power Failure Status bit(1,2) 1 = Primary power was lost and the power-fail time-stamp registers have been loaded (must be cleared in software). Clearing this bit resets the power-fail time-stamp registers to ‘0’. 0 = Primary power has not been lost bit 3 VBATEN: External Battery Backup Supply (VBAT) Enable bit 1 = VBAT input is enabled 0 = VBAT input is disabled bit 2-0 WKDAY<2:0>: Binary-Coded Decimal Value of Day of Week Contains a value from 1 to 7. The representation is user-defined. Note 1: The PWRFAIL bit must be cleared to log new time-stamp data. This is to ensure previous time-stamp data is not lost. 2: The PWRFAIL bit cannot be written to a ‘1’ in software. Writing to the RTCWKDAY register will always clear the PWRFAIL bit. REGISTER 5-5: RTCDATE: TIMEKEEPING DATE VALUE REGISTER (ADDRESS 0x04) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 — — DATETEN1 DATETEN0 DATEONE3 DATEONE2 DATEONE1 DATEONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DATETEN<1:0>: Binary-Coded Decimal Value of Date’s Tens Digit Contains a value from 0 to 3 bit 3-0 DATEONE<3:0>: Binary-Coded Decimal Value of Date’s Ones Digit Contains a value from 0 to 9  2011-2019 Microchip Technology Inc. DS20005010H-page 18

MCP7940N REGISTER 5-6: RTCMTH: TIMEKEEPING MONTH VALUE REGISTER (ADDRESS 0x05) U-0 U-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 — — LPYR MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5 LPYR: Leap Year bit 1 = Year is a leap year 0 = Year is not a leap year bit 4 MTHTEN0: Binary-Coded Decimal Value of Month’s Tens Digit Contains a value of 0 or 1 bit 3-0 MTHONE<3:0>: Binary-Coded Decimal Value of Month’s Ones Digit Contains a value from 0 to 9 REGISTER 5-7: RTCYEAR: TIMEKEEPING YEAR VALUE REGISTER (ADDRESS 0x06) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 YRTEN3 YRTEN2 YRTEN1 YRTEN0 YRONE3 YRONE2 YRONE1 YRONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown bit 7-4 YRTEN<3:0>: Binary-Coded Decimal Value of Year’s Tens Digit Contains a value from 0 to 9 bit 3-0 YRONE<3:0>: Binary-Coded Decimal Value of Year’s Ones Digit Contains a value from 0 to 9 TABLE 5-4: SUMMARY OF REGISTERS ASSOCIATED WITH TIMEKEEPING Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page RTCSEC ST SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 16 RTCMIN — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 17 RTCHOUR — 12/24 AM/PM HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 17 HRTEN1 RTCWKDAY — — OSCRUN PWRFAIL VBATEN WKDAY2 WKDAY1 WKDAY0 18 RTCDATE — — DATETEN1 DATETEN0 DATEONE3 DATEONE2 DATEONE1 DATEONE0 18 RTCMTH — — LPYR MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 19 RTCYEAR YRTEN3 YRTEN2 YRTEN1 YRTEN0 YRONE3 YRONE2 YRONE1 YRONE0 19 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used in timekeeping.  2011-2019 Microchip Technology Inc. DS20005010H-page 19

MCP7940N 5.4 Alarms TABLE 5-5: ALARM MASKS The MCP7940N features two independent alarms. ALMxMSK<2:0> Alarm Asserts on Match of Each alarm can be used to either generate an interrupt 000 Seconds at a specific time in the future, or to generate a periodic 001 Minutes interrupt every minute, hour, day, day of week, or month. 010 Hours 011 Day of Week There is a separate interrupt flag, ALMxIF, for each alarm. The interrupt flags are set by hardware when the 100 Date chosen alarm mask condition matches (Table5-5). The 101 Reserved interrupt flags must be cleared in software. 110 Reserved If either alarm module is enabled by setting the corre- 111 Seconds, Minutes, Hours, Day of sponding ALMxEN bit in the CONTROL register, and if Week, Date, and Month the square wave clock output is disabled (SQWEN = 0), then the MFP will operate in Alarm Interrupt Output mode. Refer to Section5.5 “Output Configurations” Note1: The alarm interrupt flags must be cleared for details. The alarm interrupt output is available while by the user. If a flag is cleared while the operating from the backup power supply. corresponding alarm condition still Both Alarm0 and Alarm1 offer identical operation. All matches, the flag will be set again, gener- time and date values are stored in the registers as ating another interrupt. binary-coded decimal (BCD) values. 2: Loading invalid values into the alarm reg- Note: Throughout this section, references to the isters will result in undefined operation. register and bit names for the alarm mod- ules are referred to generically by the use of ‘x’ in place of the specific module num- ber. Thus, “ALMxSEC” might refer to the seconds register for Alarm0 or Alarm1. FIGURE 5-6: ALARM BLOCK DIAGRAM Alarm0 Timekeeping Alarm1 Registers Registers Registers ALM0SEC RTCSEC ALM1SEC ALM0MIN RTCMIN ALM1MIN ALM0HOUR RTCHOUR ALM1HOUR ALM0WKDAY RTCWKDAY ALM1WKDAY ALM0DATE RTCDATE ALM1DATE ALM0MTH RTCMTH ALM1MTH Alarm0 Mask Comparator Comparator Alarm1 Mask Set Set ALM0IF ALM1IF ALM0MSK<2:0> MFP Output Logic MFP ALM1MSK<2:0>  2011-2019 Microchip Technology Inc. DS20005010H-page 20

MCP7940N 5.4.1 CONFIGURING THE ALARM In order to configure the alarm modules, the following steps need to be performed: 1. Load the timekeeping registers and enable the oscillator 2. Configure the ALMxMSK<2:0> bits to select the desired alarm mask 3. Set or clear the ALMPOL bit according to the desired output polarity 4. Ensure the ALMxIF flag is cleared 5. Based on the selected alarm mask, load the alarm match value into the appropriate regis- ter(s) 6. Enable the alarm module by setting the ALMxEN bit REGISTER 5-8: ALMxSEC: ALARM0/1 SECONDS VALUE REGISTER (ADDRESSES 0x0A/0x11) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-4 SECTEN<2:0>: Binary-Coded Decimal Value of Second’s Tens Digit Contains a value from 0 to 5 bit 3-0 SECONE<3:0>: Binary-Coded Decimal Value of Second’s Ones Digit Contains a value from 0 to 9 REGISTER 5-9: ALMxMIN: ALARM0/1 MINUTES VALUE REGISTER (ADDRESSES 0x0B/0x12) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-4 MINTEN<2:0>: Binary-Coded Decimal Value of Minute’s Tens Digit Contains a value from 0 to 5 bit 3-0 MINONE<3:0>: Binary-Coded Decimal Value of Minute’s Ones Digit Contains a value from 0 to 9  2011-2019 Microchip Technology Inc. DS20005010H-page 21

MCP7940N REGISTER 5-10: ALMxHOUR: ALARM0/1 HOURS VALUE REGISTER (ADDRESSES 0x0C/0x13) U-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — 12/24 AM/PM HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 HRTEN1 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown If 12/24 = 1 (12-hour format): bit 7 Unimplemented: Read as ‘0’ bit 6 12/24: 12 or 24 Hour Time Format bit(1) 1 = 12-hour format 0 = 24-hour format bit 5 AM/PM: AM/PM Indicator bit 1 = PM 0 = AM bit 4 HRTEN0: Binary-Coded Decimal Value of Hour’s Tens Digit Contains a value from 0 to 1 bit 3-0 HRONE<3:0>: Binary-Coded Decimal Value of Hour’s Ones Digit Contains a value from 0 to 9 If 12/24 = 0 (24-hour format): bit 7 Unimplemented: Read as ‘0’ bit 6 12/24: 12 or 24 Hour Time Format bit(1) 1 = 12-hour format 0 = 24-hour format bit 5-4 HRTEN<1:0>: Binary-Coded Decimal Value of Hour’s Tens Digit Contains a value from 0 to 2. bit 3-0 HRONE<3:0>: Binary-Coded Decimal Value of Hour’s Ones Digit Contains a value from 0 to 9 Note 1: This bit is read-only and reflects the value of the 12/24 bit in the RTCHOUR register.  2011-2019 Microchip Technology Inc. DS20005010H-page 22

MCP7940N REGISTER 5-11: ALMxWKDAY: ALARM0/1 WEEKDAY VALUE REGISTER (ADDRESSES 0x0D/ 0x14) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 ALMPOL ALMxMSK2 ALMxMSK1 ALMxMSK0 ALMxIF WKDAY2 WKDAY1 WKDAY0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown bit 7 ALMPOL: Alarm Interrupt Output Polarity bit 1 = Asserted output state of MFP is a logic high level 0 = Asserted output state of MFP is a logic low level bit 6-4 ALMxMSK<2:0>: Alarm Mask bits 000 = Seconds match 001 = Minutes match 010 = Hours match (logic takes into account 12-/24-hour operation) 011 = Day of week match 100 = Date match 101 = Reserved; do not use 110 = Reserved; do not use 111 = Seconds, Minutes, Hour, Day of Week, Date and Month bit 3 ALMxIF: Alarm Interrupt Flag bit(1,2) 1 = Alarm match occurred (must be cleared in software) 0 = Alarm match did not occur bit 2-0 WKDAY<2:0>: Binary-Coded Decimal Value of Day bits Contains a value from 1 to 7. The representation is user-defined. Note 1: If a match condition still exists when this bit is cleared, it will be set again automatically. 2: The ALMxIF bit cannot be written to a 1 in software. Writing to the ALMxWKDAY register will always clear the ALMxIF bit. REGISTER 5-12: ALMxDATE: ALARM0/1 DATE VALUE REGISTER (ADDRESSES 0x0E/0x15) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 — — DATETEN1 DATETEN0 DATEONE3 DATEONE2 DATEONE1 DATEONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DATETEN<1:0>: Binary-Coded Decimal Value of Date’s Tens Digit Contains a value from 0 to 3 bit 3-0 DATEONE<3:0>: Binary-Coded Decimal Value of Date’s Ones Digit Contains a value from 0 to 9  2011-2019 Microchip Technology Inc. DS20005010H-page 23

MCP7940N REGISTER 5-13: ALMxMTH: ALARM0/1 MONTH VALUE REGISTER (ADDRESSES 0x0F/0x16) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 — — — MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 MTHTEN0: Binary-Coded Decimal Value of Month’s Tens Digit Contains a value of 0 or 1 bit 3-0 MTHONE<3:0>: Binary-Coded Decimal Value of Month’s Ones Digit Contains a value from 0 to 9 TABLE 5-6: SUMMARY OF REGISTERS ASSOCIATED WITH ALARMS Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ALM0SEC — SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 21 ALM0MIN — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 21 ALM0HOUR — 12/24 AM/PM HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 22 HRTEN1 ALM0WKDAY ALMPOL ALM0MSK2 ALM0MSK1 ALM0MSK0 ALM0IF WKDAY2 WKDAY1 WKDAY0 23 ALM0DATE — — DATETEN1 DATETEN0 DATEONE3 DATEONE2 DATEONE1 DATEONE0 23 ALM0MTH — — — MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 24 ALM1SEC — SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 21 ALM1MIN — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 21 ALM1HOUR — 12/24 AM/PM HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 22 HRTEN1 ALM1WKDAY ALMPOL ALM1MSK2 ALM1MSK1 ALM1MSK0 ALM1IF WKDAY2 WKDAY1 WKDAY0 23 ALM1DATE — — DATETEN1 DATETEN0 DATEONE3 DATEONE2 DATEONE1 DATEONE0 23 ALM1MTH — — — MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 24 CONTROL OUT SQWEN ALM1EN ALM0EN EXTOSC CRSTRIM SQWFS1 SQWFS0 26 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by alarms.  2011-2019 Microchip Technology Inc. DS20005010H-page 24

MCP7940N 5.5 Output Configurations TABLE 5-7: MFP OUTPUT MODES The MCP7940N features Square Wave Clock Output, SQWEN ALM0EN ALM1EN Mode Alarm Interrupt Output, and General Purpose Output General Purpose 0 0 0 modes. All of the output functions are multiplexed onto Output MFP according to Table5-7. 0 1 0 Only the alarm interrupt outputs are available while Alarm Interrupt 0 0 1 operating from the backup power supply. If none of the Output 0 1 1 output functions are being used, the MFP can safely be left floating. Square Wave Clock 1 x x Output Note: The MFP is an open-drain output and requires a pull-up resistor to VCC (typically 10 kΩ). FIGURE 5-7: MFP OUTPUT BLOCK DIAGRAM MCP7940N SQWFS<1:0> Oscillator X1 32.768 kHz 11 8.192 kHz 10X X2 EXTOSC Digital caler 4.0961 k HHzz 01MU Trim sts 00 0 ST o P 64 Hz 1 CRSTRIM ALM1EN,ALM0EN ALMPOL 11 1 MFP ALM1IF 1 10X 0 01MU 0 OUT 00 SQWEN ALM0IF 1 0  2011-2019 Microchip Technology Inc. DS20005010H-page 25

MCP7940N REGISTER 5-14: CONTROL: RTCC CONTROL REGISTER (ADDRESS 0x07) R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OUT SQWEN ALM1EN ALM0EN EXTOSC CRSTRIM SQWFS1 SQWFS0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown bit 7 OUT: Logic Level for General Purpose Output bit Square Wave Clock Output Mode (SQWEN = 1): Unused. Alarm Interrupt Output mode (ALM0EN = 1 or ALM1EN = 1): Unused. General Purpose Output mode (SQWEN = 0, ALM0EN = 0, and ALM1EN = 0): 1 = MFP signal level is logic high 0 = MFP signal level is logic low bit 6 SQWEN: Square Wave Output Enable bit 1 = Enable Square Wave Clock Output mode 0 = Disable Square Wave Clock Output mode bit 5 ALM1EN: Alarm 1 Module Enable bit 1 = Alarm 1 enabled 0 = Alarm 1 disabled bit 4 ALM0EN: Alarm 0 Module Enable bit 1 = Alarm 0 enabled 0 = Alarm 0 disabled bit 3 EXTOSC: External Oscillator Input bit 1 = Enable X1 pin to be driven by external 32.768 kHz source 0 = Disable external 32.768 kHz input bit 2 CRSTRIM: Coarse Trim Mode Enable bit Coarse Trim mode results in the MCP7940N applying digital trimming every 64 Hz clock cycle. 1 = Enable Coarse Trim mode. If SQWEN = 1, MFP will output trimmed 64 Hz(1) nominal clock signal. 0 = Disable Coarse Trim mode See Section5.6 “Digital Trimming” for details bit 1-0 SQWFS<1:0>: Square Wave Clock Output Frequency Select bits If SQWEN = 1 and CRSTRIM = 0: Selects frequency of clock output on MFP 00 = 1 Hz(1) 01 = 4.096 kHz(1) 10 = 8.192 kHz(1) 11 = 32.768 kHz If SQWEN = 0 or CRSTRIM = 1: Unused. Note 1: The 8.192 kHz, 4.096 kHz, 64 Hz, and 1 Hz square wave clock output frequencies are affected by digital trimming.  2011-2019 Microchip Technology Inc. DS20005010H-page 26

MCP7940N 5.5.1 SQUARE WAVE OUTPUT MODE 5.5.2.2 Dual Alarm Operation The MCP7940N can be configured to generate a When both alarm modules are enabled, the MFP out- square wave clock signal on MFP. The input clock put is determined by a combination of the ALM0IF, frequency, FOSC, is divided according to the ALM1IF, and ALMPOL flags. SQWFS<1:0> bits as shown in Table5-8. If ALMPOL = 1, the ALM0IF and ALM1IF flags are The square wave output is not available when operat- OR’d together and the result is output on MFP. If ing from the backup power supply. ALMPOL = 0, the ALM0IF and ALM1IF flags are AND’d together, and the result is inverted and output on MFP Note: All of the clock output rates are affected by (Table5-10). This provides the user with flexible digital trimming except for the 1:1 options for combining alarms. postscaler value (SQWFS<1:0> = 11). Note: If ALMPOL = 0 and both alarms are TABLE 5-8: CLOCK OUTPUT RATES enabled, the MFP will only assert when both ALM0IF and ALM1IF are set. Nominal SQWFS<1:0> Postscaler Frequency TABLE 5-10: DUAL ALARM OUTPUT 00 1:32,768 1 Hz TRUTH TABLE 01 1:8 4.096 kHz ALMPOL ALM0IF ALM1IF MFP 10 1:4 8.192 kHz 0 0 0 1 11 1:1 32.768 kHz 0 0 1 1 Note 1: Nominal frequency assumes FOSC is 0 1 0 1 32.768 kHz. 0 1 1 0 5.5.2 ALARM INTERRUPT OUTPUT 1 0 0 0 MODE 1 0 1 1 The MFP will provide an interrupt output when enabled 1 1 0 1 alarms match and the square wave clock output is dis- 1 1 1 1 abled. This prevents the user from having to poll the alarm interrupt flag to check for a match. 5.5.3 GENERAL PURPOSE OUTPUT The alarm interrupt output is available when operating MODE from the backup power supply. If the square wave clock output and both alarm mod- The ALMxIF flags control when the MFP is asserted, as ules are disabled, the MFP acts as a general purpose described in the following sections. output. The output logic level is controlled by the OUT bit. 5.5.2.1 Single Alarm Operation The general purpose output is not available when When only one alarm module is enabled, the MFP output operating from the backup power supply. is based on the corresponding ALMxIF flag and the ALMPOL flag. If ALMPOL = 1, the MFP output reflects the value of the ALMxIF flag. If ALMPOL = 0, the MFP output reflects the inverse of the ALMxIF flag (Table5-9). TABLE 5-9: SINGLE ALARM OUTPUT TRUTH TABLE ALMPOL ALMxIF(1) MFP 0 0 1 0 1 0 1 0 0 1 1 1 Note1: ALMxIF refers to the interrupt flag corre- sponding to the alarm module that is enabled.  2011-2019 Microchip Technology Inc. DS20005010H-page 27

MCP7940N TABLE 5-11: SUMMARY OF REGISTERS ASSOCIATED WITH OUTPUT CONFIGURATION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ALM0WKDAY ALMPOL ALM0MSK2 ALM0MSK1 ALM0MSK0 ALM0IF WKDAY2 WKDAY1 WKDAY0 23 ALM1WKDAY ALMPOL ALM1MSK2 ALM1MSK1 ALM1MSK0 ALM1IF WKDAY2 WKDAY1 WKDAY0 23 CONTROL OUT SQWEN ALM1EN ALM0EN EXTOSC CRSTRIM SQWFS1 SQWFS0 26 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used in output configuration.  2011-2019 Microchip Technology Inc. DS20005010H-page 28

MCP7940N 5.6 Digital Trimming occurs once per minute when CRSTRIM = 0. The SIGN bit specifies whether to add cycles or to subtract them. The MCP7940N features digital trimming to correct for The TRIMVAL<6:0> bits are used to specify by how inaccuracies of the external crystal or clock source, up many clock cycles to adjust. Each step in the to roughly ±129 PPM when CRSTRIM = 0. In addition TRIMVAL<6:0> value equates to adding or subtracting to compensating for intrinsic inaccuracies in the clock, two clock pulses to or from the 32.768 kHz clock signal. this feature can also be used to correct for error due to This results in a correction of roughly 1.017 PPM per temperature variation. This can enable the user to step when CRSTRIM = 0. Setting TRIMVAL<6:0> to achieve high levels of accuracy across a wide tempera- 0x00 disables digital trimming. ture operating range. Digital trimming also occurs while operating off the Digital trimming consists of the MCP7940N periodically backup supply. adding or subtracting clock cycles, resulting in small adjustments in the internal timing. The adjustment REGISTER 5-15: OSCTRIM: OSCILLATOR DIGITAL TRIM REGISTER (ADDRESS 0x08) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SIGN TRIMVAL6 TRIMVAL5 TRIMVAL4 TRIMVAL3 TRIMVAL2 TRIMVAL1 TRIMVAL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown bit 7 SIGN: Trim Sign bit 1 = Add clocks to correct for slow time 0 = Subtract clocks to correct for fast time bit 6-0 TRIMVAL<6:0>: Oscillator Trim Value bits When CRSTRIM = 0: 1111111 = Add or subtract 254 clock cycles every minute 1111110 = Add or subtract 252 clock cycles every minute • • • 0000010 = Add or subtract 4 clock cycles every minute 0000001 = Add or subtract 2 clock cycles every minute 0000000 = Disable digital trimming When CRSTRIM = 1: 1111111 = Add or subtract 254 clock cycles 128 times per second 1111110 = Add or subtract 252 clock cycles 128 times per second • • • 0000010 = Add or subtract 4 clock cycles 128 times per second 0000001 = Add or subtract 2 clock cycles 128 times per second 0000000 = Disable digital trimming  2011-2019 Microchip Technology Inc. DS20005010H-page 29

MCP7940N 5.6.1 CALIBRATION 5.6.1.2 Calibration by Observing Time Deviation In order to perform calibration, the number of error clock pulses per minute must be found and the corre- To calibrate the MCP7940N by observing the deviation sponding trim value must be loaded into over time, perform the following steps: TRIMVAL<6:0>. 1. Ensure TRIMVAL<6:0> is reset to 0x00. There are two methods for determining the trim value. 2. Load the timekeeping registers to synchronize The first method involves measuring an output fre- the MCP7940N with a known-accurate refer- quency directly and calculating the deviation from ideal. ence time. The second method involves observing the number of 3. Enable the crystal oscillator or external clock seconds gained or lost over a period of time. input by setting the ST bit or EXTOSC bit, Once the OSCTRIM register has been loaded, digital respectively. trimming will automatically occur every minute. 4. Observe how many seconds are gained or lost over a period of time (larger time periods offer 5.6.1.1 Calibration by Measuring Frequency more accuracy). To calibrate the MCP7940N by measuring the output 5. Calculate the PPM deviation (see Equation5-3). frequency, perform the following steps: 1. Enable the crystal oscillator or external clock EQUATION 5-3: CALCULATING ERROR input by setting the ST bit or EXTOSC bit, PPM respectively. SecDeviation 2. Ensure TRIMVAL<6:0> is reset to 0x00. PPM = -----------------------------------⋅1000000 ExpectedSec 3. Select an output frequency by setting SQWFS<1:0>. Where: 4. Set SQWEN to enable the square wave output. ExpectedSec = Number of seconds in chosen period 5. Measure the resulting output frequency using a SecDeviation = Number of seconds gained or lost calibrated measurement tool, such as a frequency counter. 6. Calculate the number of error clocks per minute • If the MCP7940N has gained time relative to (see Equation5-2). the reference clock, then the oscillator is faster than ideal and the SIGN bit must be EQUATION 5-2: CALCULATING TRIM cleared. VALUE FROM MEASURED • If the MCP7940N has lost time relative to the FREQUENCY reference clock, then the oscillator is slower than ideal and the SIGN bit must be set. (FIDEAL–FMEAS)⋅---3---2---7---6---8----⋅60 6. Calculate the trim value (see Equation5-4). FIDEAL TRIMVAL<6:0> = --------------------------------------------------------------------------------- 2 EQUATION 5-4: CALCULATING TRIM VALUE FROM ERROR Where: PPM FIDEAL = Ideal frequency based on SQWFS<1:0> PPM⋅32768⋅60 FMEAS = Measured frequency TRIMVAL<6:0> = --------1---0---0---0---0---0---0----⋅---2---------- • If the number of error clocks per minute is 7. Load the correct value into TRIMVAL<6:0>. negative, then the oscillator is faster than ideal and the SIGN bit must be cleared. • If the number of error clocks per minute is Note1: Choosing a longer time period for observ- positive, then the oscillator is slower than ing deviation will improve accuracy. ideal and the SIGN bit must be set. 2: Large temperature variations during the 7. Load the correct value into TRIMVAL<6:0>. observation period can skew results. Note: Using a lower output frequency and/or averaging the measured frequency over a number of clock pulses will reduce the effects of jitter and improve accuracy.  2011-2019 Microchip Technology Inc. DS20005010H-page 30

MCP7940N 5.6.2 COARSE TRIM MODE By monitoring the MFP output frequency while in this mode, the user can easily observe the TRIMVAL<6:0> When CRSTRIM = 1, Coarse Trim mode is enabled. value affecting the clock timing. While in this mode, the MCP7940N will apply trimming at a rate of 128 Hz. If SQWEN is set, the MFP will out- Note1: The 64 Hz Coarse Trim mode square put a trimmed 64 Hz nominal clock signal. wave output is not available while operat- ing from the backup power supply. Because trimming is applied at a rate of 128 Hz rather than once every minute, each step of the 2: With Coarse Trim mode enabled, the TRIMVAL<6:0> value has a significantly larger effect TRIMVAL<6:0> value has a drastic effect on the resulting time deviation and output clock on timing. Leaving the mode enabled frequency. during normal operation will likely result in inaccurate time. TABLE 5-12: SUMMARY OF REGISTERS ASSOCIATED WITH DIGITAL TRIMMING Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page CONTROL OUT SQWEN ALM1EN ALM0EN EXTOSC CRSTRIM SQWFS1 SQWFS0 26 OSCTRIM SIGN TRIMVAL6 TRIMVAL5 TRIMVAL4 TRIMVAL3 TRIMVAL2 TRIMVAL1 TRIMVAL0 29 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by digital trimming.  2011-2019 Microchip Technology Inc. DS20005010H-page 31

MCP7940N 5.7 Battery Backup 5.7.1 POWER-FAIL TIME-STAMP The MCP7940N features a backup power supply input The MCP7940N includes a power-fail time-stamp mod- (VBAT) that can be used to provide power to the time- ule that stores the minutes, hours, date, and month keeping circuitry, RTCC registers, and SRAM while pri- when primary power is lost and when it is restored mary power is unavailable. The MCP7940N will (Figure5-8). The PWRFAIL bit is also set to indicate automatically switch to backup power when VCC falls that a power failure occurred. below VTRIP, and back to VCC when it is above VTRIP. Note: Throughout this section, references to the The VBATEN bit must be set to enable the VBAT input. register and bit names for the Power-Fail Time-Stamp module are referred to gener- The following functionality is maintained while operat- ically by the use of ‘x’ in place of the spe- ing on backup power: cific module name. Thus, “PWRxxMIN” • Timekeeping might refer to the minutes register for • Alarms Power-Down or Power-Up. • Alarm Output To utilize the power-fail time-stamp feature, a backup • Digital Trimming power supply must be available with the VBAT input • RTCC Register and SRAM Contents enabled, and the oscillator should also be running to ensure accurate functionality. The following features are not available while operating on backup power: Note1: The PWRFAIL bit must be cleared to log • I2C Communication new time-stamp data. This is to ensure previous time-stamp data is not lost. • Square Wave Clock Output • General Purpose Output 2: Clearing the PWRFAIL bit will clear all time-stamp registers. FIGURE 5-8: POWER-FAIL TIME-STAMP TIMING VCC VTRIP Power-Down Power-Up Time-Stamp Time-Stamp  2011-2019 Microchip Technology Inc. DS20005010H-page 32

MCP7940N REGISTER 5-16: PWRxxMIN: POWER-DOWN/POWER-UP TIME-STAMP MINUTES VALUE REGISTER (ADDRESSES 0x18/0x1C) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-4 MINTEN<2:0>: Binary-Coded Decimal Value of Minute’s Tens Digit Contains a value from 0 to 5 bit 3-0 MINONE<3:0>: Binary-Coded Decimal Value of Minute’s Ones Digit Contains a value from 0 to 9 REGISTER 5-17: PWRxxHOUR: POWER-DOWN/POWER-UP TIME-STAMP HOURS VALUE REGISTER (ADDRESSES 0x19/0x1D) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — 12/24 AM/PM HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 HRTEN1 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown If 12/24 = 1 (12-hour format): bit 7 Unimplemented: Read as ‘0’ bit 6 12/24: 12 or 24 Hour Time Format bit 1 = 12-hour format 0 = 24-hour format bit 5 AM/PM: AM/PM Indicator bit 1 = PM 0 = AM bit 4 HRTEN0: Binary-Coded Decimal Value of Hour’s Tens Digit Contains a value from 0 to 1 bit 3-0 HRONE<3:0>: Binary-Coded Decimal Value of Hour’s Ones Digit Contains a value from 0 to 9 If 12/24 = 0 (24-hour format): bit 7 Unimplemented: Read as ‘0’ bit 6 12/24: 12 or 24 Hour Time Format bit 1 = 12-hour format 0 = 24-hour format bit 5-4 HRTEN<1:0>: Binary-Coded Decimal Value of Hour’s Tens Digit Contains a value from 0 to 2. bit 3-0 HRONE<3:0>: Binary-Coded Decimal Value of Hour’s Ones Digit Contains a value from 0 to 9  2011-2019 Microchip Technology Inc. DS20005010H-page 33

MCP7940N REGISTER 5-18: PWRxxDATE: POWER-DOWN/POWER-UP TIME-STAMP DATE VALUE REGISTER (ADDRESSES 0x1A/0x1E) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — DATETEN1 DATETEN0 DATEONE3 DATEONE2 DATEONE1 DATEONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DATETEN<1:0>: Binary-Coded Decimal Value of Date’s Tens Digit Contains a value from 0 to 3 bit 3-0 DATEONE<3:0>: Binary-Coded Decimal Value of Date’s Ones Digit Contains a value from 0 to 9 REGISTER 5-19: PWRxxMTH: POWER-DOWN/POWER-UP TIME-STAMP MONTH VALUE REGISTER (ADDRESSES 0x1B/0x1F) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WKDAY2 WKDAY1 WKDAY0 MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown bit 7-5 WKDAY<2:0>: Binary-Coded Decimal Value of Day bits Contains a value from 1 to 7. The representation is user-defined. bit 4 MTHTEN0: Binary-Coded Decimal Value of Month’s Ones Digit Contains a value of 0 or 1 bit 3-0 MTHONE<3:0>: Binary-Coded Decimal Value of Month’s Ones Digit Contains a value from 0 to 9 TABLE 5-13: SUMMARY OF REGISTERS ASSOCIATED WITH BATTERY BACKUP Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page RTCWKDAY — — OSCRUN PWRFAIL VBATEN WKDAY2 WKDAY1 WKDAY0 18 PWRDNMIN — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 33 PWRDNHOUR — 12/24 AM/PM HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 33 HRTEN1 PWRDNDATE — — DATETEN1 DATETEN0 DATEONE3 DATEONE2 DATEONE1 DATEONE0 34 PWRDNMTH WKDAY2 WKDAY1 WKDAY0 MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 34 PWRUPMIN — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 33 PWRUPHOUR — 12/24 AM/PM HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 33 HRTEN1 PWRUPDATE — — DATETEN1 DATETEN0 DATEONE3 DATEONE2 DATEONE1 DATEONE0 34 PWRUPMTH WKDAY2 WKDAY1 WKDAY0 MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 34 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used with battery backup.  2011-2019 Microchip Technology Inc. DS20005010H-page 34

MCP7940N 6.0 ON-BOARD MEMORY bit from the MCP7940N, the master device transmits the data byte to be written into the addressed memory The MCP7940N has 64 bytes of SRAM for general pur- location. The MCP7940N stores the data byte into pose usage. It is retained when the primary power memory and acknowledges again, and the master gen- supply is removed if a backup supply is present and erates a Stop condition (Figure6-1). enabled. If an attempt is made to write to an address past 0x5F, Although the SRAM is a separate block from the RTCC the MCP7940N will not acknowledge the address or registers, they are accessed using the same control data bytes, and no data will be written. After a byte byte, ‘1101111X’. Write command, the internal Address Pointer will point to the address location following the one that was just 6.1 SRAM/RTCC Registers written. The RTCC registers are located at addresses 0x00 to 6.1.2 SRAM/RTCC REGISTER 0x1F, and the SRAM is located at addresses 0x20 to SEQUENTIAL WRITE 0x5F. The SRAM can be accessed while the RTCC reg- isters are being internally updated. The SRAM is not The write control byte, address, and the first data byte initialized by a Power-On Reset (POR). are transmitted to the MCP7940N in the same way as in a byte write. But instead of generating a Stop condi- Neither the RTCC registers nor the SRAM can be tion, the master transmits additional data bytes. Upon accessed when the device is operating off the backup receipt of each byte, the MCP7940N responds with an power supply. Acknowledge, during which the data is latched into memory and the Address Pointer is internally incre- 6.1.1 SRAM/RTCC REGISTER BYTE mented by one. As with the byte write operation, the WRITE master ends the command by generating a Stop condi- Following the Start condition from the master, the con- tion (Figure6-2). trol code and the R/W bit (which is a logic low) are There is no limit to the number of bytes that can be writ- clocked onto the bus by the master transmitter. This ten in a single command. However, because the RTCC indicates to the addressed slave receiver that the registers and SRAM are separate blocks, writing past address byte will follow after it has generated an the end of each block will cause the Address Pointer to Acknowledge bit during the ninth clock cycle. There- roll over to the beginning of the same block. Specifi- fore, the next byte transmitted by the master is the cally, the Address Pointer will roll over from 0x1F to address and will be written into the Address Pointer of 0x00, and from 0x5F to 0x20. the MCP7940N. After receiving another Acknowledge FIGURE 6-1: SRAM/RTCC BYTE WRITE S BUS ACTIVITY T S CONTROL ADDRESS MASTER A T R BYTE BYTE DATA O T P SDA LINE S1 1 0 11 11 0 0 P A A A BUS ACTIVITY C C C K K K FIGURE 6-2: SRAM/RTCC SEQUENTIAL WRITE S T S BUS ACTIVITY A CONTROL ADDRESS T MASTER R BYTE BYTE DATA BYTE 0 DATA BYTE N O T P SDA LINE S11 0 11 1 1 0 0 P A A A A BUS ACTIVITY C C C C K K K K  2011-2019 Microchip Technology Inc. DS20005010H-page 35

MCP7940N 6.1.3 SRAM/RTCC REGISTER CURRENT ‘0’). After the address is sent, the master generates a ADDRESS READ Start condition following the Acknowledge. This termi- nates the write operation, but not before the internal The MCP7940N contains an address counter that Address Pointer is set. Then, the master issues the maintains the address of the last byte accessed, inter- control byte again but with the R/W bit set to a ‘1’. The nally incremented by one. Therefore, if the previous MCP7940N will then issue an Acknowledge and trans- read access was to address n (n is any legal address), mit the 8-bit data word. The master will not acknowl- the next current address read operation would access edge the transfer but it does generate a Stop condition data from address n + 1. which causes the MCP7940N to discontinue transmis- Upon receipt of the control byte with R/W bit set to ‘1’, sion (Figure6-4). After a random Read command, the the MCP7940N issues an Acknowledge and transmits internal address counter will point to the address loca- the 8-bit data word. The master will not acknowledge tion following the one that was just read. the transfer but does generate a Stop condition and the MCP7940N discontinues transmission (Figure6-3). 6.1.5 SRAM/RTCC REGISTER SEQUENTIAL READ FIGURE 6-3: SRAM/RTCC CURRENT Sequential reads are initiated in the same way as a ADDRESS READ random read except that after the MCP7940N trans- S mits the first data byte, the master issues an Acknowl- T S BUS ACTIVITY A CONTROL DATA T edge as opposed to the Stop condition used in a MASTER R BYTE BYTE O random read. This Acknowledge directs the T P MCP7940N to transmit the next sequentially SDA LINE S 1 1 0 1 1 1 1 1 P addressed 8-bit word (Figure6-5). Following the final A N byte transmitted to the master, the master will NOT BUS ACTIVITY C O generate an Acknowledge but will generate a Stop con- K A dition. To provide sequential reads, the MCP7940N C contains an internal Address Pointer which is incre- K mented by one at the completion of each operation. 6.1.4 SRAM/RTCC REGISTER RANDOM This Address Pointer allows the entire memory block to READ be serially read during one operation. Because the RTCC registers and SRAM are separate Random read operations allow the master to access blocks, reading past the end of each block will cause any memory location in a random manner. To perform the Address Pointer to roll over to the beginning of the this type of read operation, first the address must be same block. Specifically, the Address Pointer will roll set. This is done by sending the address to the over from 0x1F to 0x00, and from 0x5F to 0x20. MCP7940N as part of a write operation (R/W bit set to FIGURE 6-4: SRAM/RTCC RANDOM READ S S BUS ACTIVITY T T S CONTROL ADDRESS CONTROL DATA MASTER A A T R BYTE BYTE R BYTE BYTE O T T P SDA LINE S 1 1 0 1 1 1 1 0 S 1 1 0 1 1 1 1 1 P A A A N BUS ACTIVITY C C C O K K K A C K FIGURE 6-5: SRAM/RTCC SEQUENTIAL READ CONTROL S BUS ACTIVITY T MASTER BYTE DATA n DATA n + 1 DATA n + 2 DATA n + X O P SDA LINE P A A A A N C C C C O BUS ACTIVITY K K K K A C K  2011-2019 Microchip Technology Inc. DS20005010H-page 36

MCP7940N 7.0 PACKAGING INFORMATION 7.1 Package Marking Information 8-Lead SOIC (3.90 mm) Example: XXXXXXXT 7940NI XXXXYYWW SN e 3 1406 NNN 13F 8-Lead TSSOP Example: XXXX 940N TYWW I406 NNN 13F 8-Lead MSOP Example XXXXXT 7940NI YWWNNN 40613F 8-Lead PDIP (300 mil) Example: XXXXXXXX MCP7940N T/XXXNNN I/P e 3 13F YYWW 1406 8-Lead 2x3 TDFN Example: XXX AAV YWW 303 NN 13  2011-2019 Microchip Technology Inc. DS20005010H-page 37

MCP7940N 1st Line Marking Codes Part Number SOIC TSSOP MSOP TDFN PDIP MCP7940N 7940NT 940N 7940NT AAV MCP7940N T = Temperature grade Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 JEDEC® designator for Matte Tin (Sn) * This package is RoHs compliant. The JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2011-2019 Microchip Technology Inc. DS20005010H-page 38

MCP7940N 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2X 0.10 C A–B D A D NOTE 5 N E 2 E1 2 E1 E NOTE 1 1 2 e NX b B 0.25 C A–B D NOTE 5 TOP VIEW 0.10 C C A A2 SEATING PLANE 8X 0.10 C A1 SIDE VIEW h R0.13 h R0.13 H 0.23 L SEE VIEW C (L1) VIEW A–A VIEW C Microchip Technology Drawing No. C04-057-SN Rev D Sheet 1 of 2  2011-2019 Microchip Technology Inc. DS20005010H-page 39

MCP7940N 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e 1.27 BSC Overall Height A - - 1.75 Molded Package Thickness A2 1.25 - - Standoff § A1 0.10 - 0.25 Overall Width E 6.00 BSC Molded Package Width E1 3.90 BSC Overall Length D 4.90 BSC Chamfer (Optional) h 0.25 - 0.50 Foot Length L 0.40 - 1.27 Footprint L1 1.04 REF Foot Angle 0° - 8° Lead Thickness c 0.17 - 0.25 Lead Width b 0.31 - 0.51 Mold Draft Angle Top 5° - 15° Mold Draft Angle Bottom 5° - 15° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. 5. Datums A & B to be determined at Datum H. Microchip Technology Drawing No. C04-057-SN Rev D Sheet 2 of 2  2011-2019 Microchip Technology Inc. DS20005010H-page 40

MCP7940N 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging SILK SCREEN C Y1 X1 E RECOMMENDED LAND PATTERN Units MILLIMETERS Dimension Limits MIN NOM MAX Contact Pitch E 1.27 BSC Contact Pad Spacing C 5.40 Contact Pad Width (X8) X1 0.60 Contact Pad Length (X8) Y1 1.55 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-2057-SN Rev B  2011-2019 Microchip Technology Inc. DS20005010H-page 41

MCP7940N (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:13)(cid:17)(cid:8)(cid:18)(cid:16)(cid:19)(cid:13)(cid:17)(cid:20)(cid:8)(cid:18)(cid:21)(cid:6)(cid:10)(cid:10)(cid:8)(cid:22)(cid:23)(cid:12)(cid:10)(cid:13)(cid:17)(cid:5)(cid:8)(cid:24)(cid:18)(cid:15)(cid:25)(cid:8)(cid:26)(cid:8)(cid:27)(cid:28)(cid:27)(cid:8)(cid:21)(cid:21)(cid:8)(cid:29)(cid:30)(cid:7)(cid:31)(cid:8) (cid:15)(cid:18)(cid:18)(cid:22)(cid:9)! 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DS20005010H-page 42

MCP7940N Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011-2019 Microchip Technology Inc. DS20005010H-page 43

MCP7940N Note: For the mostcurrent package drawings,please seetheMicrochip Packaging Specification located at http://www.microchip.com/packaging  2011-2019 Microchip Technology Inc. DS20005010H-page 44

MCP7940N Note: For the mostcurrent package drawings,please seetheMicrochip Packaging Specification located at http://www.microchip.com/packaging  2011-2019 Microchip Technology Inc. DS20005010H-page 45

MCP7940N Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011-2019 Microchip Technology Inc. DS20005010H-page 46

MCP7940N Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011-2019 Microchip Technology Inc. DS20005010H-page 47

MCP7940N Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011-2019 Microchip Technology Inc. DS20005010H-page 48

MCP7940N (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)$(cid:23)(cid:6)(cid:10)(cid:8)%(cid:10)(cid:6)(cid:12)&(cid:8)"(cid:30)(cid:8)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:14)(cid:20)(cid:6)’(cid:5)(cid:8)(cid:24)("(cid:25)(cid:8)(cid:26)(cid:8))*+*,(cid:28)-.(cid:8)(cid:21)(cid:21)(cid:8)(cid:29)(cid:30)(cid:7)(cid:31)(cid:8) (cid:15)$%"! "(cid:30)(cid:12)(cid:5)# 1(cid:10)(cid:9)(cid:2)%(cid:11)(cid:14)(cid:2)&(cid:10) %(cid:2)(cid:8)!(cid:9)(cid:9)(cid:14)(cid:15)%(cid:2)(cid:12)(cid:28)(cid:8)2(cid:28)(cid:17)(cid:14)(cid:2)"(cid:9)(cid:28))(cid:7)(cid:15)(cid:17) ’(cid:2)(cid:12)(cid:16)(cid:14)(cid:28) (cid:14)(cid:2) (cid:14)(cid:14)(cid:2)%(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:30)(cid:28)(cid:8)2(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)$(cid:7)(cid:8)(cid:28)%(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)%(cid:14)"(cid:2)(cid:28)%(cid:2) (cid:11)%%(cid:12)033)))(cid:20)&(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)&3(cid:12)(cid:28)(cid:8)2(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)  2011-2019 Microchip Technology Inc. DS20005010H-page 49

MCP7940N 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A N B E1 NOTE 1 1 2 TOP VIEW E C A A2 PLANE L c A1 e eB 8X b1 8X b .010 C SIDE VIEW END VIEW Microchip Technology Drawing No. C04-018-P Rev E Sheet 1 of 2  2011-2019 Microchip Technology Inc. DS20005010H-page 50

MCP7940N 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging ALTERNATE LEAD DESIGN (NOTE 5) DATUM A DATUM A b b e e 2 2 e e Units INCHES Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e .100 BSC Top to Seating Plane A - - .210 Molded Package Thickness A2 .115 .130 .195 Base to Seating Plane A1 .015 - - Shoulder to Shoulder Width E .290 .310 .325 Molded Package Width E1 .240 .250 .280 Overall Length D .348 .365 .400 Tip to Seating Plane L .115 .130 .150 Lead Thickness c .008 .010 .015 Upper Lead Width b1 .040 .060 .070 Lower Lead Width b .014 .018 .022 Overall Row Spacing § eB - - .430 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. 5. Lead design above seating plane may vary, based on assembly vendor. Microchip Technology Drawing No. C04-018-P Rev E Sheet 2 of 2  2011-2019 Microchip Technology Inc. DS20005010H-page 51

MCP7940N APPENDIX A: REVISION HISTORY Revision E (01/2013) Revised Table 1-2: AC Characteristics; temperature Revision H (10/2019) range Added notes regarding automotive grade availability; Revision D (11/2012) Corrected MSOP marking rotation; Updated package drawings SOIC and PDIP. Added Extended Temp. Revision G (07/2018) Revision C (12/2011) Updated Section 5.5.1 “Square Wave Output Mode”. Added DC/AC Char. Charts. Revision F (03/2014) Revision B (09/2011) Updated overall content for improved clarity. Added • Added Figure1-2 detailed descriptions of registers. Updated block • Added Parameter D15 to Table1-1 diagram and application schematic. • Added Section3.3 “Oscillator Input/Output Defined names for all bits and registers, and renamed (X1, X2)”, Section3.4 “Multifunction Pin the bits shown in Table7-1 for clarification. (MFP)”, Section3.5 “Backup Supply (VBAT)” Renamed the DC characteristics shown in Table7-2 for • Added Figure5-1 clarification. • Updated Section5.2.3 “Oscillator Failure Status”, Section5.2.4 “Crystal Specs”, TABLE 7-1: BIT NAME CHANGES Section5.2.5 “Power-fail Time-stamp”. Old Bit Name New Bit Name Revision A (04/2011) OSCON OSCRUN VBAT PWRFAIL Original release of this document. LP LPYR SQWE SQWEN ALM0 ALM0EN ALM1 ALM1EN RS0 SQWFS0 RS1 SQWFS1 RS2 CRSTRIM CALIBRATION TRIMVAL<6:0> ALM0POL ALMPOL ALM1POL ALMPOL ALM0C<2:0> ALM0MSK<2:0> ALM1C<2:0> ALM1MSK<2:0> TABLE 7-2: DC CHARACTERISTIC NAME CHANGES Old Name Old Symbol New Name New Symbol Operating current SRAM ICC Read SRAM/RTCC register operating current ICCREAD ICC Write ICCWRITE Operating current IVCC Timekeeping current ICCT IBAT Timekeeping backup current IBATT Standby current ICCS VCC data retention current (oscillator off) ICCDAT  2011-2019 Microchip Technology Inc. DS20005010H-page 52

MCP7940N THE MICROCHIP WEBSITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This website is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the website contains the following information: • Field Application Engineer (FAE) • Technical Support • Product Support – Data sheets and errata, application notes and sample programs, design Customers should contact their distributor, resources, user’s guides and hardware support representative or Field Application Engineer (FAE) for documents, latest software releases and archived support. Local sales offices are also available to help software customers. A listing of sales offices and locations is • General Technical Support – Frequently Asked included in the back of this document. Questions (FAQ), technical support requests, Technical support is available through the website online discussion groups, Microchip consultant at: http://microchip.com/support program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip website at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  2011-2019 Microchip Technology Inc. DS20005010H-page 53

MCP7940N PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Not every possible ordering combination is listed below. PART NO. X /XX Examples: Device Temperature Package a) MCP7940N-I/SN: Industrial Temperature, Range SOIC package. b) MCP7940NT-I/SN: Industrial Temperature, Device: MCP7940N = 1.8V - 5.5V I2C Serial RTCC SOIC package, Tape and Reel. MCP7940NT= 1.8V - 5.5V I2C Serial RTCC c) MCP7940NT-I/MNY: Industrial Temperature, (Tape and Reel) TDFN package, Tape and Reel. d) MCP7940N-I/P: Industrial Temperature, PDIP package. Temperature I = -40°C to +85°C (Industrial) Range: E = -40°C to +125°C (Extended) e) MCP7940N-E/MS: Extended Temperature, MSOP package. f) MCP7940NT-E/MS: Extended Temperature, Package: SN = 8-Lead Plastic Small Outline (3.90 mm body) MSOP package, Tape and Reel. ST = 8-Lead Plastic Thin Shrink Small Outline g) MCP7940NT-I/ST: Industrial Temperature, (4.4 mm body, I-temp only) TSSOP package, Tape and Reel. MS = 8-Lead Plastic Micro Small Outline MNY(1)= 8-Lead Plastic Dual Flat, No Lead (I-temp only) h) MCP7940NT-E/SN: Extended Temperature, P = 8-Lead Plastic PDIP (300 mil body, I-temp only) SOIC package, Tape and Reel. Note: Contact Microchip for Automotive grade ordering part numbers. Note 1: "Y" indicates a Nickel Palladium Gold (NiPdAu) finish.  2011-2019 Microchip Technology Inc. DS20005010H-page 54

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, Adaptec, and may be superseded by updates. It is your responsibility to AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT, ensure that your application meets with your specifications. chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, MICROCHIP MAKES NO REPRESENTATIONS OR LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, WARRANTIES OF ANY KIND WHETHER EXPRESS OR Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, IMPLIED, WRITTEN OR ORAL, STATUTORY OR PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, OTHERWISE, RELATED TO THE INFORMATION, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, INCLUDING BUT NOT LIMITED TO ITS CONDITION, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA QUALITY, PERFORMANCE, MERCHANTABILITY OR are registered trademarks of Microchip Technology Incorporated in FITNESS FOR PURPOSE. Microchip disclaims all liability the U.S.A. and other countries. arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at APT, ClockWorks, The Embedded Control Solutions Company, the buyer’s risk, and the buyer agrees to defend, indemnify and EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision hold harmless Microchip from any and all damages, claims, Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, suits, or expenses resulting from such use. No licenses are SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, conveyed, implicitly or otherwise, under any Microchip TimePictra, TimeProvider, Vite, WinPath, and ZL are registered intellectual property rights unless otherwise stated. trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2011-2019, Microchip Technology Incorporated, All Rights Reserved. For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality. ISBN: 978-1-5224-5209-6  2011-2019 Microchip Technology Inc. DS20005010H-page 55

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