MCP79400/MCP79401/MCP79402 2 I C™ Real-Time Clock/Calendar with SRAM, Unique ID and Battery Switchover Device Selection Table Description: SRAM The MCP7940X series of low-power Real-Time Clocks Part Number Unique ID (Bytes) (RTC) uses digital timing compensation for an accurate clock/calendar, a programmable output control for MCP79400 64 Blank versatility, a power sense circuit that automatically MCP79401 64 EUI-48™ switches to the backup supply, and nonvolatile memory MCP79402 64 EUI-64™ for data storage. Using a low-cost 32.768 kHz crystal, it tracks time using several internal registers. For Features: communication, the MCP7940X uses the I2C™ bus. • Real-Time Clock/Calendar (RTCC), Battery The clock/calendar automatically adjusts for months Backed: with fewer than 31 days, including corrections for - Hours, Minutes, Seconds, Day of Week, Day, leap years. The clock operates in either the 24-hour Month and Year or 12-hour format with an AM/PM indicator and - Dual alarm with single output settable alarm(s) to the second, minute, hour, day of • On-Chip Digital Trimming/Calibration: the week, date or month. Using the programmable CLKOUT, frequencies of 32.768, 8.192 and 4.096 - Range -127 to +127 ppm kHz and 1 Hz can be generated from the external - Resolution 1 ppm crystal. • Programmable Open-Drain Output Control: Along with the battery-backed SRAM memory, a 64-bit - CLKOUT with 4 selectable frequencies protected EEPROM space is available for a unique ID - Alarm output or MAC address to be programmed at the factory or by • 64 Bytes SRAM, Battery Backed the end user. • 64-Bit Unique ID: The device is fully accessible through the serial - User or factory programmable interface while VCC is between 1.8V and 5.5V, but can - Protected EEPROM operate down to 1.3V for timekeeping and SRAM - EUI-48™ or EUI-64™ MAC address retention only. - Custom ID programming The RTC series of devices are available in the standard 8-lead SOIC, TSSOP, MSOP and 2x3 TDFN packages. • Automatic VCC Switchover to VBAT Backup Supply Package Types • Power-Fail Time-Stamp for Battery Switchover MSOP • Low-Power CMOS Technology: - Dynamic Current: 400 A max read X1 1 8 VCC - Dynamic Current: 400 A max SRAM X2 2 7 MFP TDFN - Battery Backup Current: <700nA @ 1.8V VBAT 3 6 SCL • 100kHz and 400kHz Compatibility X1 1 8 VCC VSS 4 5 SDA • ESD Protection >4,000V X2 2 7 MFP • 1 Million Erase/Write Cycles for Unique ID SOIC, TSSOP VBAT 3 6 SCL VSS 4 5 SDA • Packages include 8-Lead SOIC, TSSOP, 2x3 TDFN, MSOP X1 1 8 VCC • Pb-Free and RoHS Compliant X2 2 7 MFP • Temperature Ranges: VBAT 3 6 SCL - Industrial (I): -40°C to +85°C VSS 4 5 SDA  2011 Microchip Technology Inc. DS25009C-page 1

MCP7940X FIGURE 1-1: TYPICAL OPERATING CIRCUIT X1 RTCC VCC or at cill s Time-Stamp/ O SRAM Alarms X2 MFP VBAT VBAT Switch I2C™ SCL VSS ID SDA FIGURE 1-2: SCHEMATIC SYSTEM VCC C1 Note 1 R1 R2 R3 X1 VCC CX1 X1 X2 X MFP MFP CX2 41 9 7 P C VBAT M SCL SCL D1 R4 VSS SDA SDA C2 BAT Suggested Values: C1 100nF CX1, CX2 See Text C2 100pF R1 10K R2,3 2.2K R4 1K D1 Schottky Note 1: A 100nF Capacitor should be placed as close to the Vcc pin on the device BAT Backup Supply as possible. X1 32.768 kHz Crystal (See Text) DS25009C-page 2  2011 Microchip Technology Inc.

MCP7940X 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) VCC.............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS..........................................................................................................-0.6V to VCC +1.0V Storage temperature...............................................................................................................................-65°C to +150°C Ambient temperature with power applied................................................................................................-40°C to +125°C ESD protection on all pins 4 kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-1: DC CHARACTERISTICS Electrical Characteristics: DC CHARACTERISTICS Industrial (I): VCC = +1.8V to 5.5V TA = -40°C to +85°C Param. Sym. Characteristic Min. Typ. Max. Units Conditions No. — SCL, SDA pins — — — — D1 VIH High-level input voltage 0.7 VCC — V — D2 VIL Low-level input voltage — 0.3 VCC V VCC = 2.5V to 5.5V 0.2 VCC D3 VHYS Hysteresis of Schmitt 0.05 — V (Note1) Trigger inputs VCC (SDA, SCL pins) D4 VOL Low-level output voltage — 0.40 V IOL = 3.0ma @ VCC = 4.5V (MFP, SDA) IOL = 2.1ma @ VCC = 2.5V D5 ILI Input leakage current — ±1 A VIN = VSS or VCC D6 ILO Output leakage current — ±1 A VOUT = VSS or VCC D7 CIN, Pin capacitance — 10 pF VCC = 5.0V (Note1) COUT (SDA, SCL and MFP) TA = 25°C, f = 400kHz D8 ICC Read Operating current — 400 A VCC = 5.5V, SCL = 400kHz ICC Write ID — 3 mA VCC = 5.5V D9 ICC Read Operating current — 300 A VCC = 5.5V, SCL = 400kHz SRAM ICC Write — 400 A VCC = 5.5V, SCL = 400kHz D10 ICCS Standby current — 1 A VCC = 5.5V, SCL = SDA = VCC D11 IBAT Operating Current — 700 — nA VBAT = 1.8V @ 25°C, Figure2-1 IVCC — 5 — A VCC = 3.6V @ 25°C, Figure2-2 (Note2) D12 VTRIP VBAT Change Over 1.3 1.7 V 1.5V typical at TAMB = 25°C D13 VCCFT VCC Fall Time (Note1) 300 — s From VTRIP (max) to VTRIP (min) D14 VCCRT VCC Rise Time (Note1) 0 — s From VTRIP (min) to VTRIP (max) D15 VBAT VBAT Voltage Range 1.3 5.5 V — (Note1) D16 COSC Oscillator Pin — 3 — pF (Note1) Capacitance Note 1: This parameter is periodically sampled and not 100% tested. 2: Standby with oscillator running.  2011 Microchip Technology Inc. DS25009C-page 3

MCP7940X TABLE 1-2: AC CHARACTERISTICS Electrical Characteristics: AC CHARACTERISTICS Industrial (I): VCC = +1.8V to 5.5V TA = -40°C to +85°C Param. Symbol Characteristic Min. Max. Units Conditions No. 1 FCLK Clock frequency — 100 kHz 1.8V  VCC < 2.5V — 400 2.5V  VCC  5.5V 2 THIGH Clock high time 4000 — ns 1.8V  VCC < 2.5V 600 — 2.5V  VCC  5.5V 3 TLOW Clock low time 4700 — ns 1.8V  VCC < 2.5V 1300 — 2.5V  VCC  5.5V 4 TR SDA and SCL rise time — 1000 ns 1.8V  VCC < 2.5V (Note1) — 300 2.5V  VCC  5.5V 5 TF SDA and SCL fall time — 1000 ns 1.8V  VCC < 2.5V (Note1) — 300 2.5V  VCC  5.5V 6 THD:STA Start condition hold time 4000 — ns 1.8V  VCC < 2.5V 600 — 2.5V  VCC  5.5V 7 TSU:STA Start condition setup time 4700 — ns 1.8V  VCC < 2.5V 600 — 2.5V  VCC  5.5V 8 THD:DAT Data input hold time 0 — ns 9 TSU:DAT Data input setup time 250 — ns 1.8V  VCC < 2.5V 100 — 2.5V  VCC  5.5V 10 TSU:STO Stop condition setup time 4000 — ns 1.8V  VCC < 2.5V 600 — 2.5V  VCC  5.5V 11 TAA Output valid from clock — 3500 ns 1.8V  VCC < 2.5V — 900 2.5V  VCC  5.5V 12 TBUF Bus free time: Time the bus 4700 — ns 1.8V  VCC < 2.5V must be free before a new 1300 — 2.5V  VCC  5.5V transmission can start 13 TSP Input filter spike suppression — 50 ns (Note1 and Note2) (SDA and SCL pins) 14 TWC Write cycle time (byte or — 5 ms — page) 15 — Endurance 1M — cycles 25°C, VCC = 5.5V Page mode (Note3) Note 1: Not 100% tested. 2: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 3: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com. DS25009C-page 4  2011 Microchip Technology Inc.

MCP7940X FIGURE 1-2: BUS TIMING DATA 5 4 2 D4 SCL 7 3 8 9 10 SDA 6 In 13 11 12 SDA Out  2011 Microchip Technology Inc. DS25009C-page 5

MCP7940X 2.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS FIGURE 2-1: IBAT VS. VBAT 1400 1300 1200 1100 -40 A) 1000 n 900 0 (BAT 800 25 I 700 600 65 500 85 400 1 1.5 2 2.5 3 3.5 4 VBAT (V) FIGURE 2-2: IVCC ACTIVE VS. VCC @ 25°C 16 14 12 10 A) U 8 (C VC 6 I 4 2 0 1.5 2.5 3.5 4.5 5.5 VCC (V) DS25009C-page 6  2011 Microchip Technology Inc.

MCP7940X 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table3-1. TABLE 3-1: PIN DESCRIPTIONS Pin Name Pin Function Vss Ground SDA Bidirectional Serial Data SCL Serial Clock X1 Xtal Input, External Oscillator Input X2 Xtal Output VBAT Battery Backup Input (3V Typ) MFP Multi Function Pin Vcc +1.8V to +5.5V Power Supply FIGURE 3-1: DEVICE PINOUTS SOIC/DFN/MSOP/TSSOP X1 1 8 Vcc X2 2 7 MFP VBAT 3 6 SCL Vss 4 5 SDA 3.1 Serial Data (SDA) This is a bidirectional pin used to transfer addresses and data into and out of the device. It is an open-drain terminal, therefore, the SDA bus requires a pull-up resistor to VCC (typically 10k for 100kHz, 2kfor 400kHz). For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the Start and Stop conditions. 3.2 Serial Clock (SCL) This input is used to synchronize the data transfer from and to the device. 3.3 X1, X2 External Crystal Pins. 3.4 MFP Open drain pin used for alarm and clock-out. 3.5 VBAT Input for backup supply to maintain RTCC and SRAM during the time when VCC is below VTRIP.  2011 Microchip Technology Inc. DS25009C-page 7

MCP7940X 4.0 I2C BUS CHARACTERISTICS 4.1.1.4 Data Valid (D) The state of the data line represents valid data when, 4.1 I2C Interface after a Start condition, the data line is stable for the duration of the high period of the clock signal. The MCP7940X supports a bidirectional 2-wire bus and data transmission protocol. A device that sends data The data on the line must be changed during the low onto the bus is defined as transmitter, and a device period of the clock signal. There is one bit of data per receiving data as receiver. The bus has to be controlled clock pulse. by a master device which generates the Start and Stop Each data transfer is initiated with a Start condition and conditions, while the MCP7940X works as slave. Both terminated with a Stop condition. The number of the master and slave can operate as transmitter or receiver data bytes transferred between the Start and Stop but the master device determines which mode is conditions is determined by the master device. activated. 4.1.1.5 Acknowledge 4.1.1 BUS CHARACTERISTICS Each receiving device, when addressed, is obliged to The following bus protocol has been defined: generate an Acknowledge signal after the reception of • Data transfer may be initiated only when the bus each byte. The master device must generate an extra is not busy. clock pulse which is associated with this Acknowledge • During data transfer, the data line must remain bit. stable whenever the clock line is high. Changes in Note: The MCP7940X does not generate any the data line while the clock line is high will be Acknowledge bits while an internal Unique interpreted as a Start or Stop condition. ID programming cycle is in progress, but Accordingly, the following bus conditions have been the user may still access the SRAM and defined (Figure4-1). RTCC registers. 4.1.1.1 Bus not Busy (A) A device that acknowledges must pull down the SDA line during the Acknowledge clock pulse in such a way Both data and clock lines remain high. that the SDA line is stable-low during the high period of the Acknowledge-related clock pulse. Of course, setup 4.1.1.2 Start Data Transfer (B) and hold times must be taken into account. During A high-to-low transition of the SDA line while the clock reads, a master must signal an end of data to the slave (SCL) is high determines a Start condition. All by NOT generating an Acknowledge bit on the last byte commands must be preceded by a Start condition. that has been clocked out of the slave. In this case, the slave (MCP7940X) will leave the data line high to 4.1.1.3 Stop Data Transfer (C) enable the master to generate the Stop condition. A low-to-high transition of the SDA line while the clock (SCL) is high determines a Stop condition. All operations must end with a Stop condition. FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS (A) (B) (D) (D) (C) (A) SCL SDA Start Address or Data Stop Condition Acknowledge Allowed Condition Valid to Change DS25009C-page 8  2011 Microchip Technology Inc.

MCP7940X FIGURE 4-2: ACKNOWLEDGE TIMING Acknowledge Bit SCL 1 2 3 4 5 6 7 8 9 1 2 3 SDA Data from transmitter Data from transmitter Transmitter must release the SDA line at this point Receiver must release the SDA line at this point allowing the Receiver to pull the SDA line low to so the Transmitter can continue sending data. acknowledge the previous eight bits of data. 4.1.2 DEVICE ADDRESSING AND OPERATION selected. The next byte received defines the address of the data byte (Figure4-3). The upper address bits are A control byte is the first byte received following the transferred first, followed by the Least Significant bits Start condition from the master device (Figure4-2). (LSb). The control byte consists of a control code; for the MCP7940X this is set as ‘1010111’ for read and write Following the Start condition, the MCP7940X monitors operations for the Unique ID after the correct unlock the SDA bus, checking the device type identifier being sequence. transmitted. Upon receiving an ‘1010111’ or ‘1101111’ code, the slave device outputs an The control byte for accessing the SRAM and RTCC Acknowledge signal on the SDA line. Depending on the registers are set to ‘1101111’. The RTCC registers and state of the R/W bit, the MCP7940X will select a read the SRAM share the same address space. or write operation. The last bit of the control byte defines the operation to be performed. When set to a ‘1’ a read operation is selected, and when set to a ‘0’ a write operation is FIGURE 4-3: ADDRESS SEQUENCE BIT ASSIGNMENTS Unique ID CONTROL BYTE ADDRESS BYTE 1 0 1 0 1 1 1 R/W 1 1 1 1 0 A2 A1 A0 CONTROL CODE X = Don’t Care SRAM RTCC CONTROL BYTE ADDRESS BYTE A 1 1 0 1 1 1 1 R/W X • • • • • • 0 CONTROL CODE X = Don’t Care  2011 Microchip Technology Inc. DS25009C-page 9

MCP7940X 4.1.3 ACKNOWLEDGE POLLING Since the device will not acknowledge a Unique ID command during an ID write cycle, this can be used to determine when the cycle is complete. This feature can be used to maximize bus throughput. Once the Stop condition for a Write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a Start condition, followed by the control byte for a Write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If no ACK is returned, then the Start bit and control byte must be resent. If the cycle is complete, then the device will return the ACK, and the master can then proceed with the next Read or Write command. See Figure4-4 for the flow diagram. FIGURE 4-4: ACKNOWLEDGE POLLING FLOW Send ID Write Command Send Stop Condition to Initiate ID Write Cycle Send Start Send Control Byte with R/W = 0 Did Device NO Acknowledge (ACK = 0)? YES Next Operation DS25009C-page 10  2011 Microchip Technology Inc.

MCP7940X 5.0 RTCC FUNCTIONALITY FIGURE 5-1: MEMORY MAP The MCP7940X family is a highly integrated RTCC. 0x00 On-board time and date counters are driven from a low- Time and Date power oscillator to maintain the time and date. An 0x06 integrated VCC switch enables the device to maintain 0x07 Configuration and Calibration the time and date and also the contents of the SRAM 0x09 0x0A during a VCC power failure. Alarm 0 5.1 RTCC MEMORY MAP 0x10 0x11 The RTCC registers are contained in addresses 0x00h-0x1fh. 64 bytes of user-accessable SRAM are Alarm 1 located in the address range 0x20-0x5f. The SRAM 0x17 0x18 memory is a separate block from the RTCC control Time-Stamp 0x1F and Configuration registers. All SRAM locations are 0x20 battery-backed-up during a VCC power fail. Unused locations are not accessible, MCP7940X will noACK after the address byte if the address is out of range, as shown in the shaded region of the memory map in Figure5-1. The shaded areas are not implemented and read as ‘0’. No error checking is provided when SRAM (64 Bytes) loading time and date registers. • Addresses 0x00h-0x06h are the RTCC Time and Date registers. These are read/write registers. Care must be taken when writing to these regis- ters while the oscillator is running. 0x5F 0x60 • Incorrect data can appear in the Time and Date registers if a write is attempted during the time- frame where these internal registers are being incremented. The user can minimize the likeli- hood of data corruption by insuring that any writes to the Time and Date registers occur before the contents of the second register reach a value of 0x59H. • Addresses 0x07h-0x09h are the device Configu- ration, Calibration and ID Unlock registers. • Addresses 0x0Ah-0x10h are the Alarm 0 regis- ters. These are used to set up the Alarm 0, the Interrupt polarity and the Alarm 0 compare. 0xFF • Addresses 0x11h-0x17h are the same as 0x0Bh- 0x11h but are used for Alarm 1. • Addresses 0x18h-0x1Fh are used for the time- stamp feature. The detailed memory map is shown in Table5-1.  2011 Microchip Technology Inc. DS25009C-page 11

MCP7940X TABLE 5-1: DETAILED RTCC MEMORY MAP Reset Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Function Range State 00h ST 10 Seconds Seconds Seconds 00-59 00h 01h 10 Minutes Minutes Minutes 00-59 00h 02h 10 Hour 10 Hour Hour Hours 1-12 + AM/PM 00h 12/24 AM/PM 00 - 23 03h OSCON VBAT VBATEN Day Day 1-7 01h 04h 10 Date Date Date 01-31 01h 05h LP 10 Month Month Month 01-12 01h 06h 10 Year Year Year 00-99 01h 07h OUT SQWE ALM1 ALM0 EXTOSC RS2 RS1 RS0 Control Reg. 80h 08h CALIBRATION Calibration 00h 09h UNIQUE UNLOCK ID SEQUENCE Unlock ID 00h 0Ah 10 Seconds Seconds Seconds 00-59 00h 0Bh 10 Minutes Minutes Minutes 00 - 59 00h 0Ch 10 Hour 10 Hours Hour Hours 1-12 + AM/PM 00h 12/24 AM/PM 00-23 0Dh ALM0POL ALM0C2 ALM0C1 ALM0C0 ALM0IF Day Day 1-7 01h 0Eh 10 Date Date Date 01-31 01h 0Fh 10 Month Month Month 01-12 01h 10h Reserved – Do not use Reserved 01h 11h 10 Seconds Seconds Seconds 00-59 00h 12h 10 Minutes Minutes Minutes 00-59 00h 13h 10 Hour 10 Hours Hour Hours 1-12 + AM/PM 00h 12/24 AM/PM 00-23 14h ALM1POL ALM1C2 ALM1C1 ALM1C0 ALM1IF Day Day 1-7 01h 15h 10 Date Date Date 01-31 01h 16h 10 Month Month Month 01-12 01h 17h Reserved – Do not use Reserved 01h 18h 10 Minutes Minutes 00h 19h 10 Hour 10 Hours Hour 00h 12/24 AM/PM 1Ah 10 Date Date 00h 1Bh Day 10 Month Month 00h 1Ch 10 Minutes Minutes 00h 1Dh 10 Hour 10 Hours Hour 00h 12/24 AM/PM 1Eh 10 Date Date 00h 1Fh Day 10 Month Month 00h DS25009C-page 12  2011 Microchip Technology Inc.

MCP7940X 5.1.1 RTCC REGISTER ADDRESSES • Bit 7 is the OUT bit. This sets the logic level on the MFP when not using this as a square wave out- 0x00h – Contains the BCD seconds and 10 seconds. put. The range is 00 to 59. Bit 7 in this register is used to start or stop the on-board crystal oscillator. Setting this • Bit 6 is the SQWE bit. Setting this bit enables the bit to a ‘1’ starts the oscillator and clearing this bit to a divided output from the crystal oscillator. ‘0’ stops the on-board oscillator. • Bits 5:4 determine which alarms are active. 0x01h – Contains the BCD minutes and 10 minutes. - 00 – No Alarms are active The range is 00 to 59. - 01 – Alarm 0 is active 0x02h – Contains the BCD hour in bits 3:0. Bits 5:4 - 10 – Alarm 1 is active contain either the 10 hour in BCD for 24-hour format or - 11 – Both Alarms are active the AM/PM indicator and the 10-hour bit for 12-hour • Bit 3 is the EXTOSC enable bit. Setting this bit will format. Bit 6 determines the hour format. Setting this allow an external 32.768 kHz signal to drive the bit to ‘0’ enables 24-hour format, setting this bit to ‘1’ RTCC registers, eliminating the need for an enables 12-hour format. external crystal. 0x03h – Contains the BCD day. The range is 1-7. • Bit 2:0 sets the internal divider for the 32.768 kHz Additional bits are also used for configuration and oscillator to be driven to the MFP. The duty cycle is status. 50%. The output is responsive to the Calibration register. The following frequencies are available: • Bit 3 is the VBATEN bit. If this bit is set, the internal circuitry is connected to the VBAT pin - 000 – 1 Hz when VCC fails. If this bit is ‘0’ then the VBAT pin is - 001 – 4.096 kHz disconnected and the only current drain on the - 010 – 8.192 kHz external battery is the VBAT pin leakage. - 011 – 32.768 kHz • Bit 4 is the VBAT bit. This bit is set by hardware - 1xx enables the Cal output function. Cal when the VCC fails and the VBAT is used to power output appears on MFP if SQWE is set (64 the Oscillator and the RTCC registers. This bit is Hz Nominal). See Section5.2.2 “Calibra- cleared by software. Clearing this bit will also tion” for more details. clear all the time-stamp registers. Note: The RTCC counters will continue to • Bit 5 is the OSCON bit. This is set and cleared by increment during the calibration. hardware. If this bit is set, the oscillator is running, if cleared, the oscillator is not running. This bit 0x08h is the Calibration register. This is an 8-bit does not indicate that the oscillator is running at register that is used to add or subtract clocks from the the correct frequency. The RTCC will wait 32 RTCC counter every minute. The MSB is the sign bit oscillator cycles before the bit is set. The RTCC and indicates if the count should be added or will wait roughly 32 clock cycles to clear this bit. subtracted. The remaining 7 bits, with each bit adding or subtracting 2 clocks, give the user the ability to add 0x04h – Contains the BCD date and 10 date. The range is 01-31. Bits 5:4 contain 10’s date and bits 4:0 or subtract up to 254 clocks per minute. contain the date. 0x09h is the unlock sequence address. To unlock write 0x05h – Contains the BCD month. Bit 4 contains the access to the unique ID area in the EEPROM, a 10 month. Bit 5 is the Leap Year bit, which is set during sequence must be written to this address in separate commands. The process is fully detailed in a leap year and is read-only. Section5.2.1 “Unlock Sequence”. 0x06h – Contains the BCD year and 10 year. The 0x0Ah-0x0fh and 0x11-0x16h are the Alarm 0 and Range is 00-99. Alarm 1 registers. The bits are the same as the RTCC 0x07h – Is the Control register. bits with the following differences: Locations 0x10h and 0x17h are reserved and should not be used to allow for future device compatibility. 0x0Dh/0x14h has additional bits for alarm configu- ration. • ALMxPOL: This bit specifies the level that the MFP will drive when the alarm is triggered. ALM2POL is a copy of ALM1POL. The default state of the MFP when used for alarms is the inverse of ALM1POL. • ALMxIF: This is the Alarm Interrupt Fag. This bit is set in hardware if the alarm was triggered. The bit  2011 Microchip Technology Inc. DS25009C-page 13

MCP7940X is cleared in software. 5.2 FEATURES • ALMxC2:0: These Configuration bits determine the alarm match. The logic will trigger the alarm 5.2.1 UNLOCK SEQUENCE based on one of the following match conditions: The unique ID location is user accessible by using the 000 – Seconds match unlock ID sequence. 001 – Minutes match The unique ID location is 64-bits (8 bytes) and is stored in EEPROM locations 0xF0 to 0xF7. This 010 – Hours match (takes into account 12/24 location can be read at any time, however, a write is hour) inhibited until unlocked. 011 – Matches the current day, interrupt at 12.00.00 a.m. Example: 12 midnight on To unlock the write access to this location the following sequence must be completed: 100 – Date • A single write of 0x55h to address 0x09. Stop 101 – RESERVED • A single write of 0xAAh to address 0x09. Stop 110 – RESERVED This will allow the unique EEPROM locations to be 111 – Seconds, Minutes, Hour, Day, Date, written. Month • The 12/24-hour bits 0xCh.6 and 0x13h.6 are cop- After the byte or page write to these locations, the ies of the bit in 0x02h.6. The bits are read-only. write sequence is initiated by the Stop condition. At this time, the ID locations are locked and no further 0x18h-0x1Bh are used for the timesaver function. writes are possible to this location unless a complete These registers are loaded at the time when VCC fails unlock sequence is repeated. and the RTCC operates on the VBAT. The VBAT bit is also set at this time. These registers are cleared when the VBAT bit is cleared in software. 0x1Ch-0x1Fh are used for the timesaver function. These registers are loaded at the time when VCC is restored and the RTCC switches to VDD. These registers are cleared when the VBAT bit is cleared in software. Note: It is strongly recommended that the timesaver function only be used when the oscillator is running. This will ensure accurate functionality. DS25009C-page 14  2011 Microchip Technology Inc.

MCP7940X 5.2.2 CALIBRATION RS2 RS1 RS0 Output Signal The MCP7940X utilizes digital calibration to correct for inaccuracies of the input clock source (either external 0 0 0 32768 or crystal). Calibration is enabled by setting the value 0 0 1 8 of the Calibration register at address 08H. Calibration 0 1 0 4 is achieved by adding or subtracting a number of input 0 1 1 1 clock cycles per minute in order to achieve ppm level With regards to the calibration function, the Calibration adjustments in the internal timing function of the register setting has no impact upon the MFP output MCP7940X. clock signal when bits RS1 and RS0 are set to ‘11’. The MSB of the Calibration register is the sign bit, with The setting of the Calibration register to a non-zero a ‘1’ indicating subtraction and a ‘0’ indicating addition. value (i.e., values other than 00H or 80H) enables the The remaining seven bits in the register indicate the calibration function which can be observed on the number of input clock cycles (multiplied by two) that MFP output pin. The calibration function can be are subtracted or added per minute to the internal expressed in terms of the number of input clock cycles timing function. added/subtracted from the internal timing function. The internal timing function can be monitored using With bits RS1 and RS0 set to ‘00’, the calibration the MFP open-drain output pin by setting bit [6] function can be expressed as: (SQWE) and bits [2:0] (RS2, RS1, RS0) of the control register at address 07H. Note that the MFP output T = (32768 +/- (2 * CALREG)) T output input waveform is disabled when the MCP7940X is running where: in VBAT mode. With the SQWE bit set to ‘1’, there are two methods that can be used to observe the internal Toutput = clock period of MFP output signal timing function of the MCP7940X: T = clock period of input signal input CALREG = decimal value of Calibration A. RS2 BIT SET TO ‘0’ register setting and the sign is With the RS2 bit set to ‘0’, the RS1 and RS0 bits determined by the MSB of enable the following internal timing signals to be Calibration register. output on the MFP pin: Since the calibration is done once per minute (i.e., RS2 RS1 RS0 Output Signal when the internal minute counter is incremented), only one cycle in sixty of the MFP output waveform is 0 0 0 1 Hz affected by the calibration setting. Also note that the 0 0 1 4.096 kHz duty cycle of the MFP output waveform will not 0 1 0 8.192 kHz necessarily be at 50% when the calibration setting is 0 1 1 32.768 kHz applied. The frequencies listed in the table presume an input With bits RS1 and RS0 set to ‘01’ or ‘10’, the clock source of exactly 32.768 kHz. In terms of the calibration function can not be expressed in terms of equivalent number of input clock cycles, the table the input clock period. In the case where the MSB of becomes: the Calibration register is set to ‘0’, the waveform appearing at the MFP output pin will be “delayed”, once per minute, by twice the number of input clock cycles defined in the Calibration register. The MFP waveform will appear as: FIGURE 5-2: RS1 AND RS0 WITH AND WITHOUT CALIBRATION Delay  2011 Microchip Technology Inc. DS25009C-page 15

MCP7940X In the case where the MSB of the Calibration register 5.2.3 MFP is set to ‘1’, the MFP output waveforms that appear Pin 7 is a multi-function pin and supports the following when bits RS1 and RS0 are set to ‘01’ or ‘10’ are not functions: as responsive to the setting of the Calibration register. For example, when outputting the 4.096 kHz • Use of the OUT bit in the Control register for waveform (RS1, RS0 set to ‘01’), the output waveform single bit I/O is generated using only eight input clock cycles. • Alarm Outputs – Available in VBAT mode Consequently, attempting to subtract more than eight • FOUT mode – driven from a FOSC divider – Not input clock cycles from this output does not have a available in VBAT mode meaningful effect on the resulting waveform. Any The internal control logic for the MFP is connected to effect on the output will appear as a modification in the switched internal supply bus, this allows operation both the frequency and duty cycle of the waveform in VBAT mode. The Alarm Output is the only mode that appearing on the MFP output pin. operates in VBAT mode, other modes are suspended. B.RS2 BIT SET TO ‘1’ 5.2.4 VBAT With the RS2 bit set to ‘1’, the following internal timing The MCP7940X features an internal switch that will signal is output on the MFP pin: power the clock and the SRAM. In the event that the VCC supply is not available, the voltage applied to the RS2 RS1 RS0 Output Signal VBAT pin serves as the backup supply. A low-value 1 x x 64.0 Hz series resistor is recommended between the external The frequency listed in the table presumes an input battery and the VBAT pin to limit the current to the clock source of exactly 32.768 kHz. In terms of the internal switch circuit. equivalent number of input clock cycles, the table The VBAT trip point is the point at which the internal becomes: switch operates the device from the VBAT supply and is typically 1.5V (VTRIP specification D12) typical. RS2 RS1 RS0 Output Signal When VDD falls below 1.5V the system will continue to operate the RTCC and SRAM using the VBAT supply. 1 x x 512 The following conditions apply: Unlike the method previously described, the calibration setting is continuously applied and affects TABLE 5-2: every cycle of the output waveform. This results in the Supply Read/Write Powered modulation of the frequency of the output waveform Condition Access By based upon the setting of the Calibration register. VCC < VTRIP, VCC < VBAT No VBAT Using this setting, the calibration function can be VCC > VTRIP, VCC < VBAT Yes VCC expressed as: VCC > VTRIP, VCC > VBAT Yes VCC T = (2 * (256 +/- (2 * CALREG))) T output input If the VBAT feature is not being used, the VBAT pin must where: be connected to GND. For more information on VBAT Toutput = clock period of MFP output signal conditions see AN1365, “RTCC Best Practices Appli- T = clock period of input signal cation Note” (DS01365). input CALREG = decimal value of the Calibration register setting, and the sign is determined by the MSB of the Calibration register. Since the calibration is done every cycle, the frequency of the output MFP waveform is constant. DS25009C-page 16  2011 Microchip Technology Inc.

MCP7940X 5.2.5 CRYSTAL SPECS The MCP7940X has been designed to operate with a standard 32.768 kHz tuning fork crystal. The on-board oscillator has been characterized to operate with a crystal of maximum ESR of 70K Ohms. Crystals with a comparable specification are also suit- able for use with the MCP7940X. The table below is given as design guidance and a starting point for crystal and capacitor selection. Crystal Manufacturer Part Number CX1 Value CX2 Value Capacitance Micro Crystal CM7V-T1A 7pF 10pF 12pF Citizen CM200S-32.768KDZB-UT 6pF 10pF 8 pF Please work with your crystal vendor. EQUATION 5-1: The following must also be taken into consideration: • Pin capacitance (to be included in Cx2 and Cx1) CX2CX1 C = -----------------------------+C • Stray Board Capacitance load CX2+CX1 stray The recommended board layout for the oscillator area is shown in Figure5-3. This actual board shows the crystal and the load capacitors. In this example, C2 is CX1, C3 is CX2 and the crystal is designated as Y1. FIGURE 5-3: BOARD LAYOUT Gerber files are available from www/microchip.com/ rtcc. It is required that the final application should be tested with the chosen crystal and capacitor combinations across all operating and environmental conditions. Please also consult with the crystal specification to observe correct handling and reflow conditions and for information on ideal capacitor values. For more information please see AN1365, “RTCC Best Practices Application Note” (DS01365).  2011 Microchip Technology Inc. DS25009C-page 17

MCP7940X 5.2.6 POWER-FAIL TIME-STAMP • The first set, located at 0x18h through 0x1Bh, is loaded at the time when VCC falls below VTRIP The MCP7941X family of RTCC devices feature a and the RTCC operates on the VBAT. The VBAT power-fail time-stamp feature. This feature will store (register 0x03h bit 4) bit is also set at this time. the time at which VCC crosses the VTRIP voltage and is • The second set of registers, located at 0x1Ch shown in Figure5-4. To use this feature, a VBAT through 0x1Fh, is loaded at the time when VCC is supply must be present and the oscillator must also be restored and the RTCC switches to VCC. running. The power-fail time-stamp registers are cleared when There are two separate sets of registers that are used the VBAT bit is cleared in software. to record this information: FIGURE 5-4: POWER-FAIL GRAPH VCC V TRIP(max) V TRIP(min) Power-Down Power-Up Time-Stamp Time-Stamp V V C C C C F R T T DS25009C-page 18  2011 Microchip Technology Inc.

MCP7940X 6.0 ON BOARD MEMORY removed, provided the VBAT supply is present and enabled. The Unique ID is nonvolatile memory and The MCP7940X has both on-board Unique ID memory does not require the VBAT supply for retention. and battery-backed SRAM. The SRAM is arranged as 64 x 8 bytes and is retained when the VCC supply is 6.1 SRAM FIGURE 6-1: SRAM/RTCC BYTE WRITE S BUS ACTIVITY T S CONTROL ADDRESS MASTER A T R BYTE BYTE DATA O T P SDA LINE S1 1 0 11 11 0 x P A A A BUS ACTIVITY C C C K K K FIGURE 6-2: SRAM/RTCC MULTIPLE BYTE WRITE S T S BUS ACTIVITY A CONTROL ADDRESS T MASTER R BYTE BYTE DATA BYTE 0 DATA BYTE N O T P SDA LINE S11 0 11 1 1 0 x P A A A A BUS ACTIVITY C C C C K K K K The 64 bytes of user SRAM are at location 0x20h and can be accessed during an RTCC update. Upon POR Note: Entering an address past 5F for an SRAM operation will result in the MCP7940X not the SRAM will be in an undefined state. acknowledging the address. Writing to the SRAM and RTCC is accomplished in a similar way to writing to the EEPROM (as described later in this document) with the following consider- ations: • There is no page. The entire 64 bytes of SRAM or 32 bytes of RTCC register can be written in one command. • The SRAM allows an unlimited number of read/ write cycles with no cell wear out. • The RTCC and SRAM are not accessible when the device is running on the external VBAT. • The RTCC and SRAM are separate blocks. The SRAM array may be accessed during an RTCC update. • Read and write access is limited to either the RTCC register block or the SRAM array. The Address Pointer will rollover to the start of the addressed block. • Data written to the RTCC and SRAM are on a per byte basis.  2011 Microchip Technology Inc. DS25009C-page 19

MCP7940X 6.2 ID 6.2.1 ID BYTE WRITE Following the Start condition from the master, the control code and the R/W bit (which is a logic low) are clocked onto the bus by the master transmitter. This indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an Acknowledge bit during the ninth clock cycle. Therefore, the next byte transmitted by the master is the word address and will be written into the Address Pointer of the MCP7940X. After receiving another Acknowledge signal from the MCP7940X, the master device transmits the data word to be written into the addressed memory location. The MCP7940X acknowledges again and the master generates a Stop condition. This initiates the internal write cycle, and, during this time, the MCP7940X does not generate Acknowledge signals for Unique ID Write commands. If an attempt is made to write to an address and the protection is set then the device will acknowledge the command but no write cycle will occur, no data will be written, and the device will immediately accept a new command. After a Byte Write command, the internal address counter will point to the address location following the one that was just written. Note: Addressing undefined ID locations will result in the MCP7940X not acknowledg- ing the address. DS25009C-page 20  2011 Microchip Technology Inc.

MCP7940X FIGURE 6-3: ID BYTE WRITE S BUS ACTIVITY T S CONTROL ADDRESS MASTER A T R BYTE BYTE DATA O T P SDA LINE S1 0 1 01 11 0 11110 • • • P A A A BUS ACTIVITY C C C K K K 6.2.2 READ OPERATION the control byte again but with the R/W bit set to a one. The MCP7940X will then issue an Acknowledge and Read operations are initiated in the same way as write transmit the 8-bit data word. The master will not operations with the exception that the R/W bit of the acknowledge the transfer but it does generate a Stop control byte is set to one. There are three basic types condition which causes the MCP7940X to discontinue of read operations: current address read, random read, transmission (Figure6-5). After a random read and sequential read. The SRAM array can be read in command, the internal address counter will point to the the same way as the ID using the control byte for the address location following the one that was just read. SRAM ‘1101111’ with a valid address. 6.2.2.3 Sequential Read 6.2.2.1 Current Address Read Sequential reads are initiated in the same way as a The MCP7940X contains an address counter that random read except that after the MCP7940X transmits maintains the address of the last word accessed, the first data byte, the master issues an Acknowledge internally incremented by one. Therefore, if the as opposed to the Stop condition used in a random previous read access was to address n (n is any legal read. This Acknowledge directs the MCP7940X to address), the next current address read operation transmit the next sequentially addressed 8-bit word would access data from address n + 1. (Figure6-6). Following the final byte transmitted to the Upon receipt of the control byte with R/W bit set to one, master, the master will NOT generate an Acknowledge the MCP7940X issues an Acknowledge and transmits but will generate a Stop condition. To provide the 8-bit data word. The master will not acknowledge sequential reads, the MCP7940X contains an internal the transfer but does generate a Stop condition and the Address Pointer which is incremented by one at the MCP7940X discontinues transmission (Figure6-4). completion of each operation. This Address Pointer allows the entire memory contents to be serially read FIGURE 6-4: CURRENT ADDRESS during one operation. The internal Address Pointer will READ (ID SHOWN) automatically roll over to the start of the block. S T S BUS ACTIVITY A CONTROL DATA T MASTER R BYTE BYTE O T P SDA LINE S 1 0 1 0 1 1 1 1 1 1 1 1 0 • • • P A N BUS ACTIVITY C O K A C K 6.2.2.2 Random Read Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, first the word address must be set. This is done by sending the word address to the MCP7940X as part of a write operation (R/W bit set to ‘0’). After the word address is sent, the master generates a Start condition following the Acknowledge. This terminates the write operation, but not before the internal Address Pointer is set. Then, the master issues  2011 Microchip Technology Inc. DS25009C-page 21

MCP7940X FIGURE 6-5: RANDOM READ (UNIQUE ID SHOWN) S S BUS ACTIVITY T T S CONTROL ADDRESS CONTROL DATA MASTER A A T R BYTE BYTE R BYTE BYTE O T T P SDA LINE S1 0 1 0 1 1 1 0 S1 0 1 0 1 P A A A N BUS ACTIVITY C C C O K K K A C K FIGURE 6-6: SEQUENTIAL READ (UNIQUE ID SHOWN) CONTROL S BUS ACTIVITY T MASTER BYTE DATA n DATA n + 1 DATA n + 2 DATA n + X O P SDA LINE P A A A A N C C C C O BUS ACTIVITY K K K K A C K 6.3 Unique ID The MCP7940X features an additional 64-bit unique ID area. The unique ID is located at addresses 0xF0 through 0xF7. Reading the unique ID requires the user to simply address these bytes. The unique ID area is protected to prevent unintended writes to these locations. The unlock sequence is detailed in Section 5.2.1 “Unlock Sequence”. The unique ID can be factory programmed on some devices to provide a unique IEEE EUI-48 or EUI-64 value. In addition, customer-provided codes can also be programmed. DS25009C-page 22  2011 Microchip Technology Inc.

MCP7940X 7.0 PACKAGING INFORMATION 7.1 Package Marking Information 8-Lead SOIC (3.90 mm) Example: XXXXXT 79400I XXYYWW SN e 3 1133 NNN 13F 8-Lead TSSOP Example: XXXX 9400 TYWW I133 NNN 13F 8-Lead MSOP Example: XXXXX 79401I YWWNNN 13313F 8-Lead 2x3 TDFN Example: XXX AAS YWW 133 NN 13 1st Line Marking Codes Part Number TSSOP MSOP TDFN MCP79400 9400 79400T AAS MCP79401 9401 79401T AAT MCP79402 9402 79402T AAU Note: T = Temperature grade NN = Alphanumeric traceability code Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2011 Microchip Technology Inc. DS25009C-page 23

MCP7940X Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS25009C-page 24  2011 Microchip Technology Inc.

MCP7940X Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011 Microchip Technology Inc. DS25009C-page 25

MCP7940X (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:10)(cid:8)(cid:17)(cid:18)(cid:12)(cid:10)(cid:13)(cid:19)(cid:5)(cid:8)(cid:20)(cid:15)(cid:21)(cid:22)(cid:8)(cid:23)(cid:8)(cid:21)(cid:6)(cid:24)(cid:24)(cid:25)(cid:26)(cid:27)(cid:8)(cid:28)(cid:29)(cid:30)(cid:31)(cid:8)(cid:16)(cid:16)(cid:8) (cid:25)(cid:7)!(cid:8)"(cid:15)(cid:17)#$% (cid:21)(cid:25)(cid:12)(cid:5)& (cid:30)(cid:10)(cid:9)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2)!(cid:10)"(cid:31)(cid:2)(cid:8)#(cid:9)(cid:9)(cid:14)(cid:15)(cid:31)(cid:2)(cid:12)(cid:28)(cid:8)$(cid:28)(cid:17)(cid:14)(cid:2)%(cid:9)(cid:28)&(cid:7)(cid:15)(cid:17)"’(cid:2)(cid:12)(cid:16)(cid:14)(cid:28)"(cid:14)(cid:2)"(cid:14)(cid:14)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)((cid:28)(cid:8)$(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7))(cid:7)(cid:8)(cid:28)(cid:31)(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)(cid:31)(cid:14)%(cid:2)(cid:28)(cid:31)(cid:2) (cid:11)(cid:31)(cid:31)(cid:12)*++&&&(cid:20)!(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)!+(cid:12)(cid:28)(cid:8)$(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) DS25009C-page 26  2011 Microchip Technology Inc.

MCP7940X (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)’((cid:13)(cid:19)(cid:8)(cid:15)((cid:24)(cid:13)(cid:19))(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:10)(cid:8)(cid:17)(cid:18)(cid:12)(cid:10)(cid:13)(cid:19)(cid:5)(cid:8)(cid:20)(cid:15)’(cid:22)(cid:8)(cid:23)(cid:8)*(cid:29)*(cid:8)(cid:16)(cid:16)(cid:8) (cid:25)(cid:7)!(cid:8)"’(cid:15)(cid:15)(cid:17)(cid:9)% (cid:21)(cid:25)(cid:12)(cid:5)& (cid:30)(cid:10)(cid:9)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2)!(cid:10)"(cid:31)(cid:2)(cid:8)#(cid:9)(cid:9)(cid:14)(cid:15)(cid:31)(cid:2)(cid:12)(cid:28)(cid:8)$(cid:28)(cid:17)(cid:14)(cid:2)%(cid:9)(cid:28)&(cid:7)(cid:15)(cid:17)"’(cid:2)(cid:12)(cid:16)(cid:14)(cid:28)"(cid:14)(cid:2)"(cid:14)(cid:14)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)((cid:28)(cid:8)$(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7))(cid:7)(cid:8)(cid:28)(cid:31)(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)(cid:31)(cid:14)%(cid:2)(cid:28)(cid:31)(cid:2) (cid:11)(cid:31)(cid:31)(cid:12)*++&&&(cid:20)!(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)!+(cid:12)(cid:28)(cid:8)$(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D N E E1 NOTE1 1 2 b e c φ A A2 A1 L1 L @(cid:15)(cid:7)(cid:31)" (cid:6)(cid:19)AA(cid:19)(cid:6)8(cid:13)8(cid:26)(cid:22) (cid:21)(cid:7)!(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:2)A(cid:7)!(cid:7)(cid:31)" (cid:6)(cid:19)E EG(cid:6) (cid:6)(cid:25)H E#!7(cid:14)(cid:9)(cid:2)(cid:10))(cid:2)((cid:7)(cid:15)" E (cid:29) ((cid:7)(cid:31)(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)J;(cid:2)>(cid:22)? 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(cid:6)(cid:10)(cid:16)%(cid:14)%(cid:2)((cid:28)(cid:8)$(cid:28)(cid:17)(cid:14)(cid:2)N(cid:7)%(cid:31)(cid:11) 81 (cid:23)(cid:20)<(cid:4) (cid:23)(cid:20)(cid:23)(cid:4) (cid:23)(cid:20);(cid:4) (cid:6)(cid:10)(cid:16)%(cid:14)%(cid:2)((cid:28)(cid:8)$(cid:28)(cid:17)(cid:14)(cid:2)A(cid:14)(cid:15)(cid:17)(cid:31)(cid:11) (cid:21) (cid:3)(cid:20)(cid:24)(cid:4) <(cid:20)(cid:4)(cid:4) <(cid:20)1(cid:4) (cid:30)(cid:10)(cid:10)(cid:31)(cid:2)A(cid:14)(cid:15)(cid:17)(cid:31)(cid:11) A (cid:4)(cid:20)(cid:23); (cid:4)(cid:20)J(cid:4) (cid:4)(cid:20)(cid:5); (cid:30)(cid:10)(cid:10)(cid:31)(cid:12)(cid:9)(cid:7)(cid:15)(cid:31) A1 1(cid:20)(cid:4)(cid:4)(cid:2)(cid:26)8(cid:30) (cid:30)(cid:10)(cid:10)(cid:31)(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)O L (cid:29)O A(cid:14)(cid:28)%(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)$(cid:15)(cid:14)"" (cid:8) (cid:4)(cid:20)(cid:4)(cid:24) L (cid:4)(cid:20)(cid:3)(cid:4) A(cid:14)(cid:28)%(cid:2)N(cid:7)%(cid:31)(cid:11) 7 (cid:4)(cid:20)1(cid:24) L (cid:4)(cid:20)<(cid:4) (cid:21)(cid:25)(cid:12)(cid:5)(cid:11)& 1(cid:20) ((cid:7)(cid:15)(cid:2)1(cid:2)3(cid:7)"#(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)%(cid:14)6(cid:2))(cid:14)(cid:28)(cid:31)#(cid:9)(cid:14)(cid:2)!(cid:28)(cid:18)(cid:2)3(cid:28)(cid:9)(cid:18)’(cid:2)7#(cid:31)(cid:2)!#"(cid:31)(cid:2)7(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)(cid:31)(cid:14)%(cid:2)&(cid:7)(cid:31)(cid:11)(cid:7)(cid:15)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)(cid:31)(cid:8)(cid:11)(cid:14)%(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7)!(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)"(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)%(cid:2)81(cid:2)%(cid:10)(cid:2)(cid:15)(cid:10)(cid:31)(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)#%(cid:14)(cid:2)!(cid:10)(cid:16)%(cid:2))(cid:16)(cid:28)"(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)(cid:31)(cid:9)#"(cid:7)(cid:10)(cid:15)"(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)%(cid:2))(cid:16)(cid:28)"(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)(cid:31)(cid:9)#"(cid:7)(cid:10)(cid:15)"(cid:2)"(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)(cid:31)(cid:2)(cid:14)6(cid:8)(cid:14)(cid:14)%(cid:2)(cid:4)(cid:20)1;(cid:2)!!(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)"(cid:7)%(cid:14)(cid:20) <(cid:20) (cid:21)(cid:7)!(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)%(cid:2)(cid:31)(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6)8(cid:2)=1(cid:23)(cid:20);(cid:6)(cid:20) >(cid:22)?* >(cid:28)"(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)!(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)(cid:31)(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)6(cid:28)(cid:8)(cid:31)(cid:2)3(cid:28)(cid:16)#(cid:14)(cid:2)"(cid:11)(cid:10)&(cid:15)(cid:2)&(cid:7)(cid:31)(cid:11)(cid:10)#(cid:31)(cid:2)(cid:31)(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)"(cid:20) (cid:26)8(cid:30)* (cid:26)(cid:14))(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)!(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)’(cid:2)#"#(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)&(cid:7)(cid:31)(cid:11)(cid:10)#(cid:31)(cid:2)(cid:31)(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)’(cid:2))(cid:10)(cid:9)(cid:2)(cid:7)(cid:15))(cid:10)(cid:9)!(cid:28)(cid:31)(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)#(cid:9)(cid:12)(cid:10)"(cid:14)"(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)&(cid:7)(cid:15)(cid:17)?(cid:4)(cid:23)(cid:27)(cid:4)(cid:29)J>  2011 Microchip Technology Inc. DS25009C-page 27

MCP7940X Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS25009C-page 28  2011 Microchip Technology Inc.

MCP7940X Note: For the mostcurrent package drawings,please seetheMicrochip Packaging Specification located at http://www.microchip.com/packaging  2011 Microchip Technology Inc. DS25009C-page 29

MCP7940X Note: For the mostcurrent package drawings,please seetheMicrochip Packaging Specification located at http://www.microchip.com/packaging DS25009C-page 30  2011 Microchip Technology Inc.

MCP7940X Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011 Microchip Technology Inc. DS25009C-page 31

MCP7940X Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS25009C-page 32  2011 Microchip Technology Inc.

MCP7940X Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011 Microchip Technology Inc. DS25009C-page 33

MCP7940X (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)+(cid:18)(cid:6)(cid:10)(cid:8),(cid:10)(cid:6)(cid:12)(cid:27)(cid:8)(cid:21)(cid:25)(cid:8)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:14))(cid:6)-(cid:5)(cid:8)(cid:20).(cid:21)(cid:22)(cid:8)(cid:23)(cid:8)/0(cid:28)0(cid:31)(cid:29)12(cid:8)(cid:16)(cid:16)(cid:8) (cid:25)(cid:7)!(cid:8)"’+,(cid:21)% (cid:21)(cid:25)(cid:12)(cid:5)& (cid:30)(cid:10)(cid:9)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2)!(cid:10)"(cid:31)(cid:2)(cid:8)#(cid:9)(cid:9)(cid:14)(cid:15)(cid:31)(cid:2)(cid:12)(cid:28)(cid:8)$(cid:28)(cid:17)(cid:14)(cid:2)%(cid:9)(cid:28)&(cid:7)(cid:15)(cid:17)"’(cid:2)(cid:12)(cid:16)(cid:14)(cid:28)"(cid:14)(cid:2)"(cid:14)(cid:14)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)((cid:28)(cid:8)$(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7))(cid:7)(cid:8)(cid:28)(cid:31)(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)(cid:31)(cid:14)%(cid:2)(cid:28)(cid:31)(cid:2) (cid:11)(cid:31)(cid:31)(cid:12)*++&&&(cid:20)!(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)!+(cid:12)(cid:28)(cid:8)$(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) DS25009C-page 34  2011 Microchip Technology Inc.

MCP7940X APPENDIX A: REVISION HISTORY Revision A (04/2011) Original release of this document. Revision B (08/2011) Added Figure 1-2; Added Parameter D16 to Table 1-1; Added Sections 2.3-2.5; Added Figure 4.1; Revised Section 4.1.1; Revised Sections 4.2.4-4.2.6. Revision C (12/2011) Added DC/AC Char. Charts.  2011 Microchip Technology Inc. DS25009C-page 35

MCP7940X NOTES: DS25009C-page 36  2011 Microchip Technology Inc.

MCP79400/MCP79401/MCP79402 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following • Field Application Engineer (FAE) information: • Technical Support • Product Support – Data sheets and errata, • Development Systems Information Line application notes and sample programs, design resources, user’s guides and hardware support Customers should contact their distributor, documents, latest software releases and archived representative or field application engineer (FAE) for software support. Local sales offices are also available to help • General Technical Support – Frequently Asked customers. A listing of sales offices and locations is Questions (FAQ), technical support requests, included in the back of this document. online discussion groups, Microchip consultant Technical support is available through the web site program member listing at: http://microchip.com/support • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  2011 Microchip Technology Inc. DS25009C-page 37

MCP79400/MCP79401/MCP79402 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480)792-4150. Please list the following information, and use this outline to provide us with your comments about this document. TO: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: MCP7940X Literature Number: DS25009C Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS25009C-page 38  2011 Microchip Technology Inc.

MCP7940X PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Not every possible ordering combination is listed below. PART NO. X /XX Examples: Device Temperature Package a) MCP79400-I/SN: Industrial Temperature, Range SOIC package. b) MCP79400T-I/SN: Industrial Tempera- Device: MCP79400 = 1.8V - 5.5V I2C™ Serial RTCC ture, SOIC package, Tape and Reel. MCP79400T= 1.8V - 5.5V I2C Serial RTCC c) MCP79400T-I/MNY: Industrial Tempera- (Tape and Reel) ture, TDFN package. MCP79401 = 1.8V - 5.5V I2C Serial RTCC, EUI-48TM d) MCP79401-I/SN: Industrial Temperature, MCP79401T= 1.8V - 5.5V I2C Serial RTCC, EUI-48TM SOIC package, EUI-48TM. (Tape and Reel) e) MCP79401-I/MS: Industrial Temperature MCP79402 = 1.8V - 5.5V I2C Serial RTCC, EUI-64TM MSOP package, EUI-48TM. MCP79402T= 1.8V - 5.5V I2C Serial RTCC, EUI-64TM f) MCP79402-I/SN: Industrial Temperature, (Tape and Reel) SOIC package, EUI-64TM. g) MCP79402-I/ST: Industrial Temperature, Temperature I = -40°C to +85°C TSSOP package, EUI-64TM. Range: h) MCP79402-I/ST: Industrial Temperature, TSSOP package, Tape and Reel, EUI-64TM. Package: SN = 8-Lead Plastic Small Outline (3.90 mm body) ST = 8-Lead Plastic Thin Shrink Small Outline (4.4 mm) MS = 8-Lead Plastic Micro Small Outline MNY(1)= 8-Lead Plastic Dual Flat, No Lead Note 1: ’Y’ indicates a Nickel Palladium Gold (NiPdAu) finish.  2011 Microchip Technology Inc. DS25009C-page 39

MCP7940X NOTES: DS25009C-page 40  2011 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. PIC32 logo, rfPIC and UNI/O are registered trademarks of MICROCHIP MAKES NO REPRESENTATIONS OR Microchip Technology Incorporated in the U.S.A. and other WARRANTIES OF ANY KIND WHETHER EXPRESS OR countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MXDEV, MXLAB, SEEVAL and The Embedded Control QUALITY, PERFORMANCE, MERCHANTABILITY OR Solutions Company are registered trademarks of Microchip FITNESS FOR PURPOSE. Microchip disclaims all liability Technology Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, chipKIT, devices in life support and/or safety applications is entirely at chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, the buyer’s risk, and the buyer agrees to defend, indemnify and dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, hold harmless Microchip from any and all damages, claims, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, suits, or expenses resulting from such use. No licenses are Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, conveyed, implicitly or otherwise, under any Microchip MPLINK, mTouch, Omniscient Code Generation, PICC, intellectual property rights. PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2011, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-61341-912-0 Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2011 Microchip Technology Inc. DS25009C-page 41

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: MCP79400-I/SN MCP79402-I/MS MCP79402-I/SN MCP79402T-I/MNY MCP79402T-I/MS