MCP73831/2 Miniature Single-Cell, Fully Integrated Li-Ion, Li-Polymer Charge Management Controllers Features: Description: • Linear Charge Management Controller: The MCP73831/2 devices are highly advanced linear - Integrated Pass Transistor charge management controllers for use in space- limited, cost-sensitive applications. The MCP73831/2 - Integrated Current Sense are available in an 8-Lead, 2mm x 3mm DFN package - Reverse Discharge Protection or a 5-Lead, SOT-23 package. Along with their small • High Accuracy Preset Voltage Regulation: + 0.75% physical size, the low number of external components • Four Voltage Regulation Options: required make the MCP73831/2 ideally suited for - 4.20V, 4.35V, 4.40V, 4.50V portable applications. For applications charging from a • Programmable Charge Current: 15mA to 500mA USB port, the MCP73831/2 adhere to all the specifications governing the USB power bus. • Selectable Preconditioning: - 10%, 20%, 40%, or Disable The MCP73831/2 employ a constant-current/constant- voltage charge algorithm with selectable • Selectable End-of-Charge Control: preconditioning and charge termination. The constant - 5%, 7.5%, 10%, or 20% voltage regulation is fixed with four available options: • Charge Status Output 4.20V, 4.35V, 4.40V or 4.50V, to accommodate new, - Tri-State Output - MCP73831 emerging battery charging requirements. The constant - Open-Drain Output - MCP73832 current value is set with one external resistor. The MCP73831/2 devices limit the charge current based on • Automatic Power-Down die temperature during high power or high ambient • Thermal Regulation conditions. This thermal regulation optimizes the • Temperature Range: -40°C to +85°C charge cycle time while maintaining device reliability. • Packaging: Several options are available for the preconditioning - 8-Lead, 2mm x 3mm DFN threshold, preconditioning current value, charge - 5-Lead, SOT-23 termination value and automatic recharge threshold. The preconditioning value and charge termination Applications: value are set as a ratio or percentage of the programmed constant current value. Preconditioning • Lithium-Ion/Lithium-Polymer Battery Chargers can be disabled. Refer to Section1.0 “Electrical • Personal Data Assistants Characteristics” for available options and the • Cellular Telephones Product Identification System for standard options. • Digital Cameras The MCP73831/2 devices are fully specified over the • MP3 Players ambient temperature range of -40°C to +85°C. • Bluetooth Headsets • USB Chargers Package Types Typical Application MCP73831/2 MCP73831/2 2×3DFN* SOT-23-5 500mA Li-Ion Battery Charger VIN 4 3 VDD 1 8 PROG STAT 1 5 PROG V V 4.7F DD BAT 4.7F +SLii-nIognle VDD 2 EP 7 NC VSS 2 - Cell 9 V 3 4 V V 3 6 V BAT DD 5 BAT SS PROG VBAT 4 5 STAT 470 2k * Includes Exposed Thermal Pad (EP); see Table3-1. 1 2 STAT VSS MCP73831  2005-2014 Microchip Technology Inc. DS20001984G-page 1

MCP73831/2 Functional Block Diagram VDD 6µA DIRECTION CONTROL VBAT 6µA G=0.001 PROG 0.5µA + CA MCP73831 REFERENCE - ONLY GENERATOR 43.6k VREF(1.22V) 361k 3.9k VDD + 89k - PRECONDITION 182.3k 111k + 15k STAT - TERMINATION + - 7k CHARGE + VA - 190k 111k + SHDN 0.5µA - + DIRECTION CONTROL VBAT - 477k + UVLO - 255k 100k VSS DS20001984G-page 2  2005-2014 Microchip Technology Inc.

MCP73831/2 1.0 ELECTRICAL † Notice: Stresses above those listed under “Maximum CHARACTERISTICS Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those Absolute Maximum Ratings† indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions V ...................................................................................7.0V DD for extended periods may affect device reliability. All Inputs and Outputs w.r.t. V ...............-0.3 to (V +0.3)V SS DD Maximum Junction Temperature, T ............Internally Limited J Storage temperature.....................................-65°C to +150°C ESD protection on all pins: Human Body Model (1.5k in Series with 100pF)4kV Machine Model (200pF, No Series Resistance).............400V DC CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, all limits apply for V = [V (typical) + 0.3V] to 6V, T = -40°C to +85°C. DD REG A Typical values are at +25°C, V = [V (typical) + 1.0V] DD REG Parameters Sym. Min. Typ. Max. Units Conditions Supply Input Supply Voltage V 3.75 — 6 V DD Supply Current I — 510 1500 µA Charging SS — 53 200 µA Charge Complete, No Battery — 25 50 µA PROG Floating — 1 5 µA V < (V - 50mV) DD BAT — 0.1 2 µA V < V DD STOP UVLO Start Threshold V 3.3 3.45 3.6 V V Low-to-High START DD UVLO Stop Threshold V 3.2 3.38 3.5 V V High-to-Low STOP DD UVLO Hysteresis V — 70 — mV HYS Voltage Regulation (Constant-Voltage Mode) Regulated Output Voltage V 4.168 4.20 4.232 V MCP7383X-2 REG 4.317 4.35 4.383 V MCP7383X-3 4.367 4.40 4.433 V MCP7383X-4 4.466 4.50 4.534 V MCP7383X-5 V = [V (typical)+1V] DD REG I = 10mA OUT T = -5°C to +55°C A Line Regulation V / — 0.09 0.30 %/V V = [V (typical)+1V] to BAT DD REG V )/V | 6V, I = 10mA BAT DD OUT Load Regulation V /V | — 0.05 0.30 % I = 10mA to 50mA BAT BAT OUT V = [V (typical)+1V] DD REG Supply Ripple Attenuation PSRR — 52 —- dB I =10mA, 10Hz to 1kHz OUT — 47 — dB I =10mA, 10Hz to 10kHz OUT — 22 — dB I =10mA, 10Hz to 1MHz OUT Current Regulation (Fast Charge Constant-Current Mode) Fast Charge Current I 90 100 110 mA PROG = 10k REG Regulation 450 505 550 mA PROG = 2.0kNote1 12.5 14.5 16.5 mA PROG = 67k T = -5°C to +55°C A Note 1: Not production tested. Ensured by design.  2005-2014 Microchip Technology Inc. DS20001984G-page 3

MCP73831/2 DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, all limits apply for V = [V (typical) + 0.3V] to 6V, T = -40°C to +85°C. DD REG A Typical values are at +25°C, V = [V (typical) + 1.0V] DD REG Parameters Sym. Min. Typ. Max. Units Conditions Preconditioning Current Regulation (Trickle Charge Constant-Current Mode) Precondition Current I / I 7.5 10 12.5 % PROG = 2.0kto 10k PREG REG Ratio 15 20 25 % PROG = 2.0kto 10k 30 40 50 % PROG = 2.0kto 10k — 100 — % No Preconditioning T = -5°C to +55°C A Precondition Voltage V / V 64 66.5 69 % V Low-to-High PTH REG BAT Threshold Ratio 69 71.5 74 % V Low-to-High BAT Precondition Hysteresis V — 110 — mV V High-to-Low PHYS BAT Charge Termination Charge Termination I / I 3.75 5 6.25 % PROG = 2.0kto 10k TERM REG Current Ratio 5.6 7.5 9.4 % PROG = 2.0kto 10k 8.5 10 11.5 % PROG = 2.0kto 10k 15 20 25 % PROG = 2.0kto 10k T = -5°C to +55°C A Automatic Recharge Recharge Voltage V / V 91.5 94.0 96.5 % V High-to-Low RTH REG BAT Threshold Ratio 94 96.5 99 % V High-to-Low BAT Pass Transistor ON-Resistance ON-Resistance R — 350 — m V = 3.75V, T = 105°C DSON DD J Battery Detection Battery Detection Current I — 6 — µA V Source Current BAT_DET BAT No-Battery-Present V — V + — V V Voltage ≥ V for NO_BAT REG BAT NO_BAT Threshold 100mV No Battery condition No-Battery-Present Z 2 — — M V Impedance ≥ Z NO_BAT BAT NO_BAT Impedance for No Battery condition, Note1 Battery Discharge Current Output Reverse Leakage I — 0.15 2 µA PROG Floating DISCHARGE Current — 0.25 2 µA V Floating DD — 0.15 2 µA V < V DD STOP — -5.5 -15 µA Charge Complete Status Indicator – STAT Sink Current I — — 25 mA SINK Low Output Voltage V — 0.4 1 V I = 4mA OL SINK Source Current I — — 35 mA SOURCE High Output Voltage V — V -0.4 V - 1 V I = 4mA (MCP73831) OH DD DD SOURCE Input Leakage Current I — 0.03 1 µA High-Impedance LK PROG Input Charge Impedance R 2 — 67 k PROG Range Minimum Shutdown R 70 — 200 k PROG Impedance Automatic Power Down Automatic Power Down V V <(V V <(V — 3.5V  V  V PDENTER DD BAT DD BAT BAT REG Entry Threshold +20mV) +50mV) V Falling DD Note 1: Not production tested. Ensured by design. DS20001984G-page 4  2005-2014 Microchip Technology Inc.

MCP73831/2 DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, all limits apply for V = [V (typical) + 0.3V] to 6V, T = -40°C to +85°C. DD REG A Typical values are at +25°C, V = [V (typical) + 1.0V] DD REG Parameters Sym. Min. Typ. Max. Units Conditions Automatic Power Down V — V <(V V <(V 3.5V  V  V PDEXIT DD BAT DD BAT BAT REG Exit Threshold +150mV) +200mV) V Rising DD Thermal Shutdown Die Temperature T — 150 — C SD Die Temperature T — 10 — C SDHYS Hysteresis Note 1: Not production tested. Ensured by design. AC CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, all limits apply for V = [V (typical) + 0.3V] to 12V, DD REG T = -40°C to +85°C. Typical values are at +25°C, V = [V (typical) + 1.0V] A DD REG Parameters Sym. Min. Typ. Max. Units Conditions UVLO Start Delay t — — 5 ms V Low-to-High START DD Constant-Current Regulation Transition Time Out of t — — 1 ms V < V to V > V DELAY BAT PTH BAT PTH Preconditioning Current Rise Time Out of t — — 1 ms I Rising to 90% of I RISE OUT REG Preconditioning Termination Comparator t 0.4 1.3 3.2 ms Average I Falling TERM OUT Filter Charge Comparator Filter t 0.4 1.3 3.2 ms Average V CHARGE BAT Status Indicator Status Output turn-off tOFF — — 200 µs ISINK = 1mA to 0mA Status Output turn-on tON — — 200 µs ISINK = 0mA to 1mA TEMPERATURE SPECIFICATIONS Electrical Specifications: Unless otherwise indicated, all limits apply for V = [V (typical) + 0.3V] to 12V. DD REG Typical values are at +25°C, V = [V (typical) + 1.0V] DD REG Parameters Sym. Min. Typ. Max. Units Conditions Temperature Ranges Specified Temperature Range T -40 — +85 °C A Operating Temperature Range T -40 — +125 °C J Storage Temperature Range T -65 — +150 °C A Thermal Package Resistances 5-Lead, SOT-23  — 230 — °C/W 4-Layer JC51-7 Standard JA Board, Natural Convection (Note2) 8-Lead, 2mm x 3mm, DFN  — 76 — °C/W 4-Layer JC51-7 Standard JA Board, Natural Convection (Note1) Note 1: This represents the minimum copper condition on the PCB (Printed Circuit Board). 2: With large copper area on the PCB, the SOT-23-5 thermal resistance ( ) can reach a typical value of JA 130°C/W or better.  2005-2014 Microchip Technology Inc. DS20001984G-page 5

MCP73831/2 NOTES: DS20001984G-page 6  2005-2014 Microchip Technology Inc.

MCP73831/2 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, V = [V (typical) + 1V], I = 10mA and T = +25°C, Constant-Voltage mode. DD REG OUT A 4.210 e MCP73831-2 500 ag 4.205 450 Volt 4.200 IOUT = 10 mA mA) 400 ulation (V)44..119905 IOUT = 100 mA urrent ( 233505000 ery Reg 44..118805 IOUT = 450 mA harge C 112050000 Batt 4.175 C 50 4.170 0 4.50 4.75 5.00 5.25 5.50 5.75 6.00 2 7 12 17 22 27 32 37 42 47 52 57 62 67 Supply Voltage (V) Programming Resistor (kΩ) FIGURE 2-1: Battery Regulation Voltage FIGURE 2-4: Charge Current (I ) vs. OUT (V ) vs. Supply Voltage (V ). Programming Resistor (R ). BAT DD PROG e (V) 44..220150 MCP73831-2 110034 RPROG = 10 kΩ ag A) olt 4.200 IOUT = 10 mA m 102 n V 4.195 nt ( 101 atio 4.190 urre 100 attery Regul 4444....111177880505 IIOOUUTT == 140500 mmAA Charge C 999789 B 96 0 0 0 0 0 0 0 0 0 0 0 0 0 -4 -3 -2 -1 1 2 3 4 5 6 7 8 4.50 4.75 5.00 5.25 5.50 5.75 6.00 Ambient Temperature (°C) Supply Voltage (V) FIGURE 2-2: Battery Regulation Voltage FIGURE 2-5: Charge Current (I ) vs. OUT (V ) vs. Ambient Temperature (T ). Supply Voltage (V ). BAT A DD 0.40 516 kage Current (µA) 00000.....1223350505 ++-428055°°°CCC e Current (mA) 555550011168024 RPROG = 2 kΩ Lea 0.10 arg 504 ut Ch 502 p 0.05 ut 500 O 0.00 4.50 4.75 5.00 5.25 5.50 5.75 6.00 3.00 3.20 3.40 3.60 3.80 4.00 4.20 Battery Regulation Voltage (V) Supply Voltage (V) FIGURE 2-3: Output Leakage Current FIGURE 2-6: Charge Current (I ) vs. OUT (I ) vs. Battery Regulation Voltage Supply Voltage (V ). DISCHARGE DD (V ). BAT  2005-2014 Microchip Technology Inc. DS20001984G-page 7

MCP73831/2 TYPICAL PERFORMANCE CURVES (CONTINUED) Note: Unless otherwise indicated, V = [V (typical) + 1V], I = 10mA and T = +25°C, Constant-Voltage mode. DD REG OUT A 104 525 A) 103 RPROG = 10 kΩ A) 450 RPROG = 2 kΩ nt (m 110012 nt (m 375 e e 300 Curr 100 Curr 225 e 99 e g g 150 ar 98 ar Ch 97 Ch 75 96 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 25 35 45 55 65 75 85 95 105 115 125 135 145 155 Ambient Temperature (°C) Junction Temperature (°C) FIGURE 2-7: Charge Current (I ) vs. FIGURE 2-10: Charge Current (I ) vs. OUT OUT Ambient Temperature (T ). Junction Temperature (T ). A J 516 0 RPROG = 2 kΩ VAC = 100 mVp-p mA) 551124 B) -10 ICOOUUT T= = 1 40. 7m µAF, X7R Ceramic ent ( 510 n (d -20 ge Curr 550068 enuatio --4300 Char 550024 Att -50 500 -60 40 30 20 10 0 10 20 30 40 50 60 70 80 0.01 0.1 1 10 100 1000 - - - - Ambient Temperature (°C) Frequency (kHz) FIGURE 2-8: Charge Current (I ) vs. FIGURE 2-11: Power Supply Ripple OUT Ambient Temperature (T ). Rejection (PSRR). A 120 0 ent (mA) 1790505 RPROG = 10 kΩ n (dB) --2100 VICOAOUCUT T== = 11 400.007 mmµFVA,p X-p7R Ceramic Curr 60 atio -30 harge 3405 Attenu -40 C 15 -50 0 -60 5 5 5 5 5 5 5 5 5 5 5 5 5 5 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0.01 0.1 1 10 100 1000 Junction Temperature (°C) Frequency (kHz) FIGURE 2-9: Charge Current (I ) vs. FIGURE 2-12: Power Supply Ripple OUT Junction Temperature (T ). Rejection (PSRR). J DS20001984G-page 8  2005-2014 Microchip Technology Inc.

MCP73831/2 TYPICAL PERFORMANCE CURVES (CONTINUED) Note: Unless otherwise indicated, V = [V (typical) + 1V], I = 10mA and T = +25°C, Constant-Voltage mode. DD REG OUT A 14 0.10 1.40 0.10 12 0.05 1.20 0.05 age (V) 108 -00.0.005 ple (V) ent (A) 01..8000 -00.0.005 ple (V) Source Volt 246 IOUT = 10 mA ---000...211050 Output Rip Output Curr 000...246000 ---000...211050 Output Rip -20 COUT = 4.7 µF, X7R Ceramic --00..3205 -00..0200 COUT = 4.7 µF, X7R Ceramic --00..3205 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 4 6 8 0 2 4 6 8 0 2 4 6 8 0 2 4 6 8 0 1 1 1 1 1 2 1 1 1 1 1 2 Time (µs) Time (µs) FIGURE 2-13: Line Transient Response. FIGURE 2-16: Load Transient Response. 14 0.10 6.0 120 12 0.05 Voltage (V) 1680 --000.0..10005 Ripple (V) Voltage (V) 345...000 6810000 urrent (mA) Source 024 ICOOUUT T= = 1 40.07 mµFA, X7R Ceramic ---000...221505 Output Battery 12..00 MVRDPCDRP O=G7 53=.8 213V01 -k2ΩAC/IOT 2400 Charge C -2 -0.30 0.0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 4 6 8 0 2 4 6 8 0 2 4 6 8 0 2 4 6 8 1 1 1 1 1 2 1 1 1 1 1 Time (µs) Time (minutes) FIGURE 2-14: Line Transient Response. FIGURE 2-17: Complete Charge Cycle (180mAh Li-Ion Battery). 0.35 0.04 6.0 600 0.30 0.02 Current (A) 000...122505 --000.0..00042 Ripple (V) Voltage (V) 345...000 345000000 urrent (mA) Output 000...001050 ---000...100086 Output Battery 12..00 MVDCDP =7 53.823V1-2AC/IOT 120000 Charge C COUT = 4.7 µF, X7R Ceramic RPROG = 2 kΩ -0.05 -0.12 0.0 0 0 20 40 60 80 100 120 140 160 180 200 0 30 60 90 120 150 180 210 240 Time (µs) Time (minutes) FIGURE 2-15: Load Transient Response. FIGURE 2-18: Complete Charge Cycle (1000mAh Li-Ion Battery).  2005-2014 Microchip Technology Inc. DS20001984G-page 9

MCP73831/2 NOTES: DS20001984G-page 10  2005-2014 Microchip Technology Inc.

MCP73831/2 3.0 PIN DESCRIPTION The descriptions of the pins are listed in Table3-1. TABLE 3-1: PIN FUNCTION TABLES Pin No. Symbol Function DFN SOT-23-5 1 4 V Battery Management Input Supply DD 2 — V Battery Management Input Supply DD 3 3 V Battery Charge Control Output BAT 4 — V Battery Charge Control Output BAT 5 1 STAT Charge Status Output 6 2 V Battery Management 0V Reference SS 7 — NC No Connection 8 5 PROG Current Regulation Set and Charge Control Enable 9 — EP Exposed Thermal Pad (EP); must be connected to V . SS 3.1 Battery Management Input Supply 3.4 Battery Management 0V Reference (V ) (V ) DD SS A supply voltage of [V (typical) + 0.3V] to 6V is Connect to negative terminal of battery and input REG recommended. Bypass to V with a minimum of supply. SS 4.7µF. 3.5 Current Regulation Set (PROG) 3.2 Battery Charge Control Output Preconditioning, fast charge and termination currents (V ) BAT are scaled by placing a resistor from PROG to V . SS Connect to positive terminal of battery. Drain terminal The charge management controller can be disabled by of internal P-channel MOSFET pass transistor. Bypass allowing the PROG input to float. to V with a minimum of 4.7µF to ensure loop stability SS when the battery is disconnected. 3.6 Exposed Thermal Pad (EP) 3.3 Charge Status Output (STAT) An internal electrical connection exists between the Exposed Thermal Pad (EP) and the V pin. They must SS STAT is an output for connection to an LED for charge be connected to the same potential on the Printed status indication. Alternatively, a pull-up resistor can be Circuit Board (PCB). applied for interfacing to a host microcontroller. For better thermal performance, it is recommended to STAT is a tri-state logic output on the MCP73831 and add vias from the land area of EP to a copper layer on an open-drain output on the MCP73832. the other side of the PCB.  2005-2014 Microchip Technology Inc. DS20001984G-page 11

MCP73831/2 NOTES: DS20001984G-page 12  2005-2014 Microchip Technology Inc.

MCP73831/2 4.0 DEVICE OVERVIEW The MCP73831/2 are highly advanced linear charge The UVLO circuit places the device in Shutdown mode management controllers. Figure4-1 depicts the if the input supply falls to within +50mV of the battery operational flow algorithm from charge initiation to voltage. Again, the input supply must rise to a level completion and automatic recharge. 150mV above the battery voltage before the MCP73831/2 become operational. The UVLO circuit is always active. Whenever the input SHUTDOWN MODE supply is below the UVLO threshold or within +50mV V < V DD UVLO of the voltage at the V pin, the MCP73831/2 are BAT V < V DD BAT placed in Shutdown mode. or PROG > 200k During any UVLO condition, the battery reverse STAT = High Z discharge current is less than 2µA. VBAT < VPTH 4.2 Battery Detection PRECONDITIONING A 6µA (typical) current is sourced by the VBAT pin to MODE determine if a battery is present or not. If the voltage at Charge Current = IPREG VBAT rises to VREG + 100mV (typical), the device STAT = LOW assumes that a battery is not present. If the voltage stays below V + 100 mV (typical), the device REG VBAT > VPTH assumes that a battery is detected. In order to correctly detect a battery insertion, the impedance seen by the V > V FAST CHARGE BAT PTH V pin before the battery is connected must be BAT MODE greater than 2MΩ. Charge Current = IREG VBAT < VRTH STAT = LOW 4.3 Charge Qualification VBAT = VREG For a charge cycle to begin, all UVLO conditions must be met and a battery or output load must be present. A CONSTANT VOLTAGE charge current programming resistor must be MODE connected from PROG to V . If the PROG pin is open Charge Voltage = V SS REG or floating, the MCP73831/2 are disabled and the STAT = LOW battery reverse discharge current is less than 2µA. In this manner, the PROG pin acts as a charge enable I < I BAT TERM and can be used as a manual shutdown. CHARGE COMPLETE 4.4 Preconditioning MODE No Charge Current If the voltage at the V pin is less than the STAT = HIGH (MCP73831) BAT STAT = High Z (MCP73832) preconditioning threshold, the MCP73831/2 enter a preconditioning or Trickle Charge mode. The preconditioning threshold is factory set. Refer to FIGURE 4-1: Flowchart. Section1.0 “Electrical Characteristics” for preconditioning threshold options and the Product 4.1 Undervoltage Lockout (UVLO) Identification System for standard options. In this mode, the MCP73831/2 supply a percentage of An internal UVLO circuit monitors the input voltage and the charge current (established with the value of the keeps the charger in Shutdown mode until the input resistor connected to the PROG pin) to the battery. The supply rises above the UVLO threshold. The UVLO percentage or ratio of the current is factory set. Refer to circuitry has a built in hysteresis of 100mV. Section1.0 “Electrical Characteristics” for In the event a battery is present when the input power preconditioning current options and the Product Iden- is applied, the input supply must rise to a level 150mV tification System for standard options. above the battery voltage before the MCP73831/2 When the voltage at the V pin rises above the become operational. BAT preconditioning threshold, the MCP73831/2 enter the Constant-Current or Fast Charge mode.  2005-2014 Microchip Technology Inc. DS20001984G-page 13

MCP73831/2 4.5 Fast Charge Constant-Current 4.9 Thermal Regulation Mode The MCP73831/2 limit the charge current based on the During the Constant-Current mode, the programmed die temperature. The thermal regulation optimizes the charge current is supplied to the battery or load. The charge cycle time while maintaining device reliability. charge current is established using a single resistor Figure4-2 depicts the thermal regulation for the from PROG to V . Constant-Current mode is MCP73831/2. SS maintained until the voltage at the V pin reaches the BAT regulation voltage, V . REG 525 RPROG = 2 k 4.6 Constant-Voltage Mode A) 450 m Wreghuelna tiothne vovlotaltgaeg,e Vat ,t hceo nVstBaAnTt vpoinlta gree arcehgeusla ttiohne urrent ( 330705 REG C 225 begins. The regulation voltage is factory set to 4.2V, e 4.35V, 4.40V or 4.50V with a tolerance of ±0.75%. harg 150 C 75 4.7 Charge Termination 0 5 5 5 5 5 5 5 5 5 5 5 5 5 5 2 3 4 5 6 7 8 9 0 1 2 3 4 5 1 1 1 1 1 1 The charge cycle is terminated when, during Constant- Junction Temperature (°C) Voltage mode, the average charge current diminishes below a percentage of the programmed charge current FIGURE 4-2: Thermal Regulation. (established with the value of the resistor connected to the PROG pin). A 1ms filter time on the termination 4.10 Thermal Shutdown comparator ensures that transient load conditions do not result in premature charge cycle termination. The The MCP73831/2 suspend charge if the die tempera- percentage or ratio of the current is factory set. Refer to ture exceeds 150°C. Charging will resume when the Section1.0 “Electrical Characteristics” for charge die temperature has cooled by approximately 10°C. termination current options and the Product Identification System for standard options. The charge current is latched off and the MCP73831/2 enter a Charge Complete mode. 4.8 Automatic Recharge The MCP73831/2 continuously monitor the voltage at the V pin in the Charge Complete mode. If the BAT voltage drops below the recharge threshold, another charge cycle begins and current is once again supplied to the battery or load. The recharge threshold is factory set. Refer to Section1.0 “Electrical Characteristics” for recharge threshold options and the Product Identification System for standard options. DS20001984G-page 14  2005-2014 Microchip Technology Inc.

MCP73831/2 5.0 DETAILED DESCRIPTION 5.2 Digital Circuitry 5.2.1 STATUS INDICATOR (STAT) 5.1 Analog Circuitry The charge status output of the MCP73831 has three 5.1.1 BATTERY MANAGEMENT INPUT different states: High (H), Low (L), and High- SUPPLY (V ) Impedance (High Z). The charge status output of the DD MCP73832 is open-drain. It has two different states: The V pin is the input supply pin for the MCP73831/ DD Low (L) and High-Impedance (High Z). The charge sta- 2 devices. The MCP73831/2 automatically enter a tus output can be used to illuminate one, two or tri-color Power-Down mode if the voltage on the V input falls DD LEDs. Optionally, the charge status output can be used below the UVLO voltage (V ). This feature prevents STOP as an interface to a host microcontroller. draining the battery pack when the V supply is not DD present. Table5-1 summarizes the state of the status output during a charge cycle. 5.1.2 CURRENT REGULATION SET TABLE 5-1: STATUS OUTPUT (PROG) Fast charge current regulation can be scaled by placing STAT1 Charge Cycle State a programming resistor (R ) from the PROG input PROG MCP73831 MCP73832 to V . The program resistor and the charge current SS are calculated using the following equation: Shutdown High Z High Z No Battery Present High Z High Z 1000V Preconditioning L L I = ----------------- REG R PROG Constant-Current Fast L L Charge Where: Constant Voltage L L R = kOhms PROG Charge Complete – H High Z IREG = milliampere Standby The preconditioning trickle charge current and the 5.2.2 DEVICE DISABLE (PROG) charge termination current are ratiometric to the fast The current regulation set input pin (PROG) can be charge current based on the selected device options. used to terminate a charge at any time during the 5.1.3 BATTERY CHARGE CONTROL charge cycle, as well as to initiate a charge cycle or initiate a recharge cycle. OUTPUT (V ) BAT Placing a programming resistor from the PROG input to The battery charge control output is the drain terminal V enables the device. Allowing the PROG input to of an internal P-channel MOSFET. The MCP73831/2 SS float or by applying a logic-high input signal, disables provide constant current and voltage regulation to the the device and terminates a charge cycle. When battery pack by controlling this MOSFET in the linear disabled, the device’s supply current is reduced to region. The battery charge control output should be 25µA, typically. connected to the positive terminal of the battery pack.  2005-2014 Microchip Technology Inc. DS20001984G-page 15

MCP73831/2 NOTES: DS20001984G-page 16  2005-2014 Microchip Technology Inc.

MCP73831/2 6.0 APPLICATIONS followed by a constant voltage charging method. Figure6-1 depicts a typical stand-alone application The MCP73831/2 are designed to operate in circuit, while Figure6-2 and Figure6-3 depict the conjunction with a host microcontroller or in a stand- accompanying charge profile. alone application. The MCP73831/2 provide the preferred charge algorithm for Lithium-Ion and Lithium- Polymer cells. The algorithm uses a constant current Li-Ion Battery Charger 4 3 V V DD BAT + Single CIN RLED COUT Li-Ion - Cell 5 STAT PROG REGULATED WALL CUBE LED R PROG 1 2 V SS MCP73831 FIGURE 6-1: Typical Application Circuit. 6.0 120 6.0 600 Voltage (V) 345...000 6810000 urrent (mA) Voltage (V) 345...000 345000000 urrent (mA) Battery 12..00 MVDCDP =7 53.823V1-2AC/IOT 2400 Charge C Battery 12..00 MVDCDP =7 35.823V1-2AC/IOT 120000 Charge C RPROG = 10 kΩ RPROG = 2 kΩ 0.0 0 0.0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 4 6 8 0 2 4 6 8 3 6 9 2 5 8 1 4 1 1 1 1 1 1 1 1 2 2 Time (minutes) Time (minutes) FIGURE 6-2: Typical Charge Profile FIGURE 6-3: Typical Charge Profile in (180mAh Battery). Thermal Regulation (1000mAh Battery). 6.1 Application Circuit Design Due to the low efficiency of linear charging, the most 6.1.1.1 Current Programming Resistor important factors are thermal design and cost, which (R ) PROG are a direct function of the input voltage, output current The preferred fast charge current for Lithium-Ion cells and thermal impedance between the battery charger is at the 1C rate, with an absolute maximum current at and the ambient cooling air. The worst-case situation is the 2C rate. For example, a 500mAh battery pack has when the device has transitioned from the a preferred fast charge current of 500mA. Charging at Preconditioning mode to the Constant-Current mode. this rate provides the shortest charge cycle times In this situation, the battery charger has to dissipate the without degradation to the battery pack performance or maximum power. A trade-off must be made between life. the charge current, cost and thermal requirements of the charger. 6.1.1 COMPONENT SELECTION Selection of the external components in Figure6-1 is crucial to the integrity and reliability of the charging system. The following discussion is intended as a guide for the component selection process.  2005-2014 Microchip Technology Inc. DS20001984G-page 17

MCP73831/2 6.1.1.2 Input Overvoltage Protection (IOVP) 6.1.1.5 Reverse-Blocking Protection Input overvoltage protection must be used when the The MCP73831/2 provide protection from a faulted or input power source is hot-pluggable. This includes USB shorted input. Without the protection, a faulted or cables and Wall-type power supplies. The cabling of shorted input would discharge the battery pack through these supplies acts as an inductor. When the supplies the body diode of the internal pass transistor. are connected/disconnected from the system, large 6.1.1.6 Charge Inhibit voltage transients are created which may damage the system circuitry. These transients should be snubbed The current regulation set input pin (PROG) can be out. A transzorb connected from the V+ input supply used to terminate a charge at any time during the connector to the 0V ground reference will snub the charge cycle, as well as to initiate a charge cycle or transients. initiate a recharge cycle. Placing a programming resistor from the PROG input to 6.1.1.3 Thermal Considerations V enables the device. Allowing the PROG input to SS The worst-case power dissipation in the battery float or by applying a logic-high input signal, disables charger occurs when the input voltage is at the the device and terminates a charge cycle. When maximum and the device has transitioned from the disabled, the device’s supply current is reduced to Preconditioning mode to the Constant-Current mode. 25µA, typically. In this case, the power dissipation is: 6.1.1.7 Charge Status Interface PowerDissipation = V –V I A status output provides information on the state of DDMAX PTHMIN REGMAX charge. The output can be used to illuminate external Where: LEDs or interface to a host microcontroller. Refer to V = the maximum input voltage Table5-1 for a summary of the state of the status DDMAX output during a charge cycle. I = the maximum fast charge current REGMAX V = the minimum transition threshold 6.2 PCB Layout Issues PTHMIN voltage For optimum voltage regulation, place the battery pack as close as possible to the device’s V and V pins. Power dissipation with a 5V, ±10% input voltage source BAT SS This is recommended to minimize voltage drops along is: the high current-carrying PCB traces. PowerDissipation = 5.5V–2.7V550mA = 1.54W If the PCB layout is used as a heat sink, adding many vias in the heat sink pad can help conduct more heat to the PCB backplane, thus reducing the maximum This power dissipation with the battery charger in the junction temperature. Figure6-4 and Figure6-5 depict SOT-23-5 package will cause thermal regulation to be a typical layout with PCB heatsinking. entered as depicted in Figure6-3. Alternatively, the 2mm x 3mm DFN package could be utilized to reduce charge cycle times. RLED LED 6.1.1.4 External Capacitors VSS RPROG The MCP73831/2 are stable with or without a battery load. In order to maintain good AC stability in the Constant-Voltage mode, a minimum capacitance of VBAT COUT MCP73831 CIN VDD 4.7µF is recommended to bypass the V pin to V . BAT SS This capacitance provides compensation when there is no battery load. In addition, the battery and FIGURE 6-4: Typical Layout (Top). interconnections appear inductive at high frequencies. These elements are in the control feedback loop during Constant-Voltage mode. Therefore, the bypass capacitance may be necessary to compensate for the inductive nature of the battery pack. VSS Virtually any good quality output filter capacitor can be used, independent of the capacitor’s minimum Effective Series Resistance (ESR) value. The actual VBAT VDD value of the capacitor (and its associated ESR) depends on the output load current. A 4.7µF ceramic, tantalum or aluminum electrolytic capacitor at the FIGURE 6-5: Typical Layout (Bottom). output is usually sufficient to ensure stability for output currents up to a 500mA. DS20001984G-page 18  2005-2014 Microchip Technology Inc.

MCP73831/2 7.0 PACKAGING INFORMATION 7.1 Package Marking Information 8-Lead DFN (2x3x0.9 mm) Example Device Code MCP73831T-2ACI/MC AAE MCP73831T-2ATI/MC AAF AAE MCP73831T-2DCI/MC AAG MCP73831T-3ACI/MC AAH 739 MCP73831T-4ADI/MC AAJ 25 MCP73831T-5ACI/MC AAK MCP73832T-2ACI/MC AAL MCP73832T-2ATI/MC AAM MCP73832T-2DCI/MC AAP MCP73832T-3ACI/MC AAQ MCP73832T-4ADI/MC AAR MCP73832T-5ACI/MC AAS Note: Applies to 8-Lead DFN 5-Lead SOT-23 Example Device Code MCP73831T-2ACI/OT KDNN MCP73831T-2ATI/OT KENN MCP73831T-2DCI/OT KFNN XXNN MCP73831T-3ACI/OT KGNN KD25 MCP73831T-4ADI/OT KHNN MCP73831T-5ACI/OT KJNN MCP73832T-2ACI/OT KKNN MCP73832T-2ATI/OT KLNN MCP73832T-2DCI/OT KMNN MCP73832T-3ACI/OT KPNN MCP73832T-4ADI/OT KQNN MCP73832T-5ACI/OT KRNN MCP73832T-2DFI/OT LUNN Note: Applies to 5-Lead SOT-23 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e 3 Pb-free Compliant JEDEC® designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2005-2014 Microchip Technology Inc. DS20001984G-page 19

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MCP73831/2 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2005-2014 Microchip Technology Inc. DS20001984G-page 21

MCP73831/2 ((cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8))"(cid:6)(cid:10)(cid:10)(cid:8)*(cid:16)(cid:12)(cid:10)(cid:13)+(cid:5)(cid:8),-(cid:6)+(cid:11)(cid:13)(cid:11)(cid:12)(cid:20)-(cid:8)(cid:23)*,(cid:26)(cid:8)%)*,(cid:3)(cid:28)(cid:30)& (cid:19)(cid:20)(cid:12)(cid:5)’ 4(cid:21)(cid:20)(cid:14)%(cid:22)(cid:13)(cid:14)&(cid:21) %(cid:14)(cid:19)!(cid:20)(cid:20)(cid:13)(cid:24)%(cid:14)(cid:10)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:13)(cid:14)"(cid:20)(cid:11))(cid:18)(cid:24)(cid:12) ’(cid:14)(cid:10)(cid:25)(cid:13)(cid:11) (cid:13)(cid:14) (cid:13)(cid:13)(cid:14)%(cid:22)(cid:13)(cid:14)(cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:14)(cid:30)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:18)(cid:24)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:19)(cid:18)$(cid:18)(cid:19)(cid:11)%(cid:18)(cid:21)(cid:24)(cid:14)(cid:25)(cid:21)(cid:19)(cid:11)%(cid:13)"(cid:14)(cid:11)%(cid:14) (cid:22)%%(cid:10)255)))(cid:28)&(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:28)(cid:19)(cid:21)&5(cid:10)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:18)(cid:24)(cid:12) b N E E1 1 2 3 e e1 D A A2 c φ A1 L L1 6(cid:24)(cid:18)% (cid:17)(cid:27)99(cid:27)(cid:17),(cid:23),(cid:8)(cid:3) (cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)(cid:14)9(cid:18)&(cid:18)% (cid:17)(cid:27): :;(cid:17) (cid:17)(cid:7)< :!&((cid:13)(cid:20)(cid:14)(cid:21)$(cid:14)(cid:30)(cid:18)(cid:24) : . 9(cid:13)(cid:11)"(cid:14)(cid:30)(cid:18)%(cid:19)(cid:22) (cid:13) (cid:4)(cid:28)(cid:6).(cid:14)/(cid:3)0 ;!% (cid:18)"(cid:13)(cid:14)9(cid:13)(cid:11)"(cid:14)(cid:30)(cid:18)%(cid:19)(cid:22) (cid:13)(cid:29) (cid:29)(cid:28)(cid:6)(cid:4)(cid:14)/(cid:3)0 ;(cid:31)(cid:13)(cid:20)(cid:11)(cid:25)(cid:25)(cid:14)>(cid:13)(cid:18)(cid:12)(cid:22)% (cid:7) (cid:4)(cid:28)(cid:6)(cid:4) @ (cid:29)(cid:28)(cid:5). (cid:17)(cid:21)(cid:25)"(cid:13)"(cid:14)(cid:30)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:13)(cid:14)(cid:23)(cid:22)(cid:18)(cid:19)*(cid:24)(cid:13) (cid:7)(cid:15) (cid:4)(cid:28)=(cid:6) @ (cid:29)(cid:28)+(cid:4) (cid:3)%(cid:11)(cid:24)"(cid:21)$$ (cid:7)(cid:29) (cid:4)(cid:28)(cid:4)(cid:4) @ (cid:4)(cid:28)(cid:29). ;(cid:31)(cid:13)(cid:20)(cid:11)(cid:25)(cid:25)(cid:14)?(cid:18)"%(cid:22) , (cid:15)(cid:28)(cid:15)(cid:4) @ +(cid:28)(cid:15)(cid:4) (cid:17)(cid:21)(cid:25)"(cid:13)"(cid:14)(cid:30)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:13)(cid:14)?(cid:18)"%(cid:22) ,(cid:29) (cid:29)(cid:28)+(cid:4) @ (cid:29)(cid:28)=(cid:4) ;(cid:31)(cid:13)(cid:20)(cid:11)(cid:25)(cid:25)(cid:14)9(cid:13)(cid:24)(cid:12)%(cid:22) (cid:2) (cid:15)(cid:28)(cid:16)(cid:4) @ +(cid:28)(cid:29)(cid:4) 4(cid:21)(cid:21)%(cid:14)9(cid:13)(cid:24)(cid:12)%(cid:22) 9 (cid:4)(cid:28)(cid:29)(cid:4) @ (cid:4)(cid:28)H(cid:4) 4(cid:21)(cid:21)%(cid:10)(cid:20)(cid:18)(cid:24)% 9(cid:29) (cid:4)(cid:28)+. @ (cid:4)(cid:28)=(cid:4) 4(cid:21)(cid:21)%(cid:14)(cid:7)(cid:24)(cid:12)(cid:25)(cid:13) (cid:3) (cid:4)J @ +(cid:4)J 9(cid:13)(cid:11)"(cid:14)(cid:23)(cid:22)(cid:18)(cid:19)*(cid:24)(cid:13) (cid:19) (cid:4)(cid:28)(cid:4)= @ (cid:4)(cid:28)(cid:15)H 9(cid:13)(cid:11)"(cid:14)?(cid:18)"%(cid:22) ( (cid:4)(cid:28)(cid:15)(cid:4) @ (cid:4)(cid:28).(cid:29) (cid:19)(cid:20)(cid:12)(cid:5)(cid:11)’ (cid:29)(cid:28) (cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24) (cid:14)(cid:2)(cid:14)(cid:11)(cid:24)"(cid:14),(cid:29)(cid:14)"(cid:21)(cid:14)(cid:24)(cid:21)%(cid:14)(cid:18)(cid:24)(cid:19)(cid:25)!"(cid:13)(cid:14)&(cid:21)(cid:25)"(cid:14)$(cid:25)(cid:11) (cid:22)(cid:14)(cid:21)(cid:20)(cid:14)(cid:10)(cid:20)(cid:21)%(cid:20)! (cid:18)(cid:21)(cid:24) (cid:28)(cid:14)(cid:17)(cid:21)(cid:25)"(cid:14)$(cid:25)(cid:11) (cid:22)(cid:14)(cid:21)(cid:20)(cid:14)(cid:10)(cid:20)(cid:21)%(cid:20)! (cid:18)(cid:21)(cid:24) (cid:14) (cid:22)(cid:11)(cid:25)(cid:25)(cid:14)(cid:24)(cid:21)%(cid:14)(cid:13)#(cid:19)(cid:13)(cid:13)"(cid:14)(cid:4)(cid:28)(cid:29)(cid:15)(cid:16)(cid:14)&&(cid:14)(cid:10)(cid:13)(cid:20)(cid:14) (cid:18)"(cid:13)(cid:28) (cid:15)(cid:28) (cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)(cid:18)(cid:24)(cid:12)(cid:14)(cid:11)(cid:24)"(cid:14)%(cid:21)(cid:25)(cid:13)(cid:20)(cid:11)(cid:24)(cid:19)(cid:18)(cid:24)(cid:12)(cid:14)(cid:10)(cid:13)(cid:20)(cid:14)(cid:7)(cid:3)(cid:17),(cid:14)-(cid:29)(cid:5)(cid:28).(cid:17)(cid:28) /(cid:3)02 /(cid:11) (cid:18)(cid:19)(cid:14)(cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)(cid:28)(cid:14)(cid:23)(cid:22)(cid:13)(cid:21)(cid:20)(cid:13)%(cid:18)(cid:19)(cid:11)(cid:25)(cid:25)(cid:26)(cid:14)(cid:13)#(cid:11)(cid:19)%(cid:14)(cid:31)(cid:11)(cid:25)!(cid:13)(cid:14) (cid:22)(cid:21))(cid:24)(cid:14))(cid:18)%(cid:22)(cid:21)!%(cid:14)%(cid:21)(cid:25)(cid:13)(cid:20)(cid:11)(cid:24)(cid:19)(cid:13) (cid:28) (cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:23)(cid:13)(cid:19)(cid:22)(cid:24)(cid:21)(cid:25)(cid:21)(cid:12)(cid:26)(cid:2)(cid:20)(cid:11))(cid:18)(cid:24)(cid:12)0(cid:4)(cid:5)(cid:9)(cid:4)(cid:6)(cid:29)/ DS20001984G-page 22  2005-2014 Microchip Technology Inc.

MCP73831/2 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2005-2014 Microchip Technology Inc. DS20001984G-page 23

MCP73831/2 APPENDIX A: REVISION HISTORY Revision B (March 2006) The following is the list of modifications: Revision G (July 2014) 1. Added MCP73832 through document. The following is the list of modifications: Revision A (November 2005) 1. Updated the“DC Characteristics” table. 2. Added Section6.1.1.2 “Input Overvoltage Original Release of this Document. Protection (IOVP)”. Revision F (June 2013) The following is the list of modifications: 3. Updated the Functional Block Diagram. 4. Added the Battery Detection parameter and related information in the“DC Characteristics” table. 5. Added new section Section4.2 “Battery Detection”. 6. Minor grammatical and spelling corrections. Revision E (September 2008) The following is the list of modifications: 1. Package Types: Changed DFN pinout diagram. 2. Section1.0 “Electrical Characteristics”: Changed “Charge Impedance Range from 20k to 67k 3. Section1.0 “Electrical Characteristics”: Misc. Formatting changes. 4. Section2.0 “Typical Performance Curves”: Updated Figure2-4. 5. Section3.0 “Pin Description”: Added Exposed Pad pin to table and added Section3.6 “Exposed Thermal Pad (EP)”. 6. Updated Appendix A: “Revision History” 7. Added Land Pattern Package Outline Drawing for 2x3 DFN package. Revision D (April 2008) The following is the list of modifications: 1. Changed Charge Termination Current Ratio to 8.5% minimum and 11.5% maximum. Revision C (October 2007) The following is the list of modifications: 1. Numerous edits throughout document. 2. Added note to the Temperature Specifications table. 3. Updated Figure2-4. DS20001984G-page 24  2005-2014 Microchip Technology Inc.

MCP73831/2 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X XX X /XX Examples: * a) MCP73831-2ACI/OT: 4.20V VREG, Options AC, 5LD SOT23 Pkg Device V Options Temperature Package REG b) MCP73831T-2ACI/OT: Tape and Reel, Range 4.20V VREG, Options AC, 5LD SOT23 Pkg c) MCP73832-2ACI/MC: 4.20V VREG, Options AC, 8LD DFN Package Device: MCP73831: Single-Cell Charge Controller d) MCP73832T-2ACI/MC:Tape and Reel, MCP73831T: Single-Cell Charge Controller (Tape and Reel) 4.20V VREG, Options AC, 8LD DFN Package MCP73832 Single-Cell Charge Controller a) MCP73831-2ATI/OT: 4.20V VREG, MCP73832T: Single-Cell Charge Controller Options AT, 5LD SOT23 Pkg (Tape and Reel) b) MCP73831T-2ATI/OT: Tape and Reel, 4.20V VREG, Options AT, 5LD SOT23 Pkg Regulation Code VREG c) MOCptPio7n3s8 3A2T-, 28ALTDI/ MDFCN: P4a.c2k0aVg eVREG, Voltage: d) MCP73832T-2ATI/MC:Tape and Reel, 2 = 4.20V 4.20V VREG, Options AT, 8LD DFN Package 3 = 4.35V 4 = 4.40V a) MCP73831-2DCI/OT: 4.20V VREG, 5 = 4.50V Options DC, 5LD SOT23 Pkg b) MCP73831T-2DCI/OT: Tape and Reel, 4.20V VREG, Options DC, 5LD SOT23 Pkg Options: * Code IPREG/IREG VPTH/VREG ITERM/IREG VRTH/VREG c) MCP73832-2DCI/MC: 4.20V VREG, AC 10 66.5 7.5 96.5 Options DC, 8LD DFN Package AD 10 66.5 7.5 94 d) MCP73832T-2DCI/MC:Tape and Reel, AT 10 71.5 20 94 4.20V VREG, Options DC, 8LD DFN Package DC 100 x 7.5 96.5 a) MCP73831-3ACI/OT: 4.35V VREG, * Consult Factory for Alternative Device Options Options AC, 5LD SOT23 Pkg b) MCP73831T-3ACI/OT: Tape and Reel, Temperature I = -40C to +85C (Industrial) 4.35V VREG, Options AC, 5LD SOT23 Pkg Range: c) MCP73832-3ACI/MC: 4.35V VREG, Options AC, 8LD DFN Package d) MCP73832T-3ACI/MC:Tape and Reel, Package: MC = Dual-Flat, No-Lead (2x3 mm body), 8-Lead 4.35V VREG, Options AC, 8LD DFN Package OT = Small Outline Transistor (SOT23), 5-Lead a) MCP73831-4ADI/OT: 4.40V VREG, Options AD, 5LD SOT23 Pkg b) MCP73831T-4ADI/OT: Tape and Reel, 4.40V VREG, Options AD, 5LD SOT23 Pkg c) MCP73832-4ADI/MC: 4.40V VREG, Options AD, 8LD DFN Package d) MCP73832T-4ADI/MC:Tape and Reel, 4.40V VREG, Options AD, 8LD DFN Package a) MCP73831-5ACI/OT: 4.50V VREG, Options AC, 5LD SOT23 Pkg b) MCP73831T-5ACI/OT: Tape and Reel, 4.50V VREG, Options AC, 5LD SOT23 Pkg c) MCP73832-5ACI/MC: 4.50V VREG, Options AC, 8LD DFN Package d) MCP73832T-5ACI/MC:Tape and Reel, 4.50V VREG, Options AC, 8LD DFN Package * Consult Factory for Alternate Device Options  2005-2014 Microchip Technology Inc. DS20001984G-page 25

MCP73831/2 NOTES: DS20001984G-page 26  2005-2014 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, ensure that your application meets with your specifications. LANCheck, MediaLB, MOST, MOST logo, MPLAB, MICROCHIP MAKES NO REPRESENTATIONS OR OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, WARRANTIES OF ANY KIND WHETHER EXPRESS OR SST, SST Logo, SuperFlash and UNI/O are registered IMPLIED, WRITTEN OR ORAL, STATUTORY OR trademarks of Microchip Technology Incorporated in the OTHERWISE, RELATED TO THE INFORMATION, U.S.A. and other countries. INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR The Embedded Control Solutions Company and mTouch are FITNESS FOR PURPOSE. Microchip disclaims all liability registered trademarks of Microchip Technology Incorporated arising from this information and its use. Use of Microchip in the U.S.A. devices in life support and/or safety applications is entirely at Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, the buyer’s risk, and the buyer agrees to defend, indemnify and CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit hold harmless Microchip from any and all damages, claims, Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, suits, or expenses resulting from such use. No licenses are KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo, conveyed, implicitly or otherwise, under any Microchip MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code intellectual property rights. Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2005-2014, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-63276-375-4 QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures == ISO/TS 16949 == are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2005-2014 Microchip Technology Inc. DS20001984G-page 27

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: MCP73832T-4ADI/OT MCP73831-2DCI/MC MCP73831-2ATI/MC MCP73832-2ATI/MC MCP73832-5ACI/MC MCP73831T-5ACI/MC MCP73832-2ACI/MC MCP73832T-5ACI/MC MCP73832T-4ADI/MC MCP73832-3ACI/MC MCP73831T-4ADI/OT MCP73831-4ADI/MC MCP73831T-4ADI/MC MCP73831-3ACI/MC MCP73831-2ACI/MC MCP73831T-5ACI/OT MCP73831-5ACI/MC MCP73832-2DCI/MC MCP73832-4ADI/MC MCP73832T-5ACI/OT MCP73832T-2DFI/OT MCP73831T-2ACI/MC MCP73831T-2ACI/OT MCP73831T-2ATI/MC MCP73831T-2ATI/OT MCP73831T-2DCI/MC MCP73831T-2DCI/OT MCP73831T-3ACI/MC MCP73832T-2ACI/OT MCP73832T-2ATI/MC MCP73832T-2ATI/OT MCP73832T-2DCI/MC MCP73832T-2DCI/OT MCP73832T-3ACI/MC MCP73832T-3ACI/OT PIC24FJ32GA102T-I/ML PIC24FJ32GB002-I/SP PIC24FJ64GA102T-I/ML PIC24FJ32GA102T-I/SO PIC24FJ32GB002T-I/ML PIC24FJ32GB002T-I/SO PIC24FJ64GA102-I/SP PIC24FJ64GA102T-I/SO