MCP6V11/1U/2/4 7.5 µA, 80 kHz Zero-Drift Op Amps Features: Description: • High DC Precision: The Microchip Technology Inc. MCP6V11/1U/2/4 family - V Drift: ±50nV/°C (maximum) of operational amplifiers provides input offset voltage OS correction for very low offset and offset drift. These are - V : ±8µV (maximum) OS low-power devices, with a gain bandwidth product of - A : 112dB (minimum, V =5.5V) OL DD 80kHz (typical). They are unity gain stable, have - PSRR: 118dB (minimum, V =5.5V) DD virtually no 1/f noise, and have good Power Supply - CMRR: 119dB (minimum, VDD=5.5V) Rejection Ratio (PSRR) and Common Mode Rejection - E : 2.1µV (typical), f=0.1Hz to 10Hz Ratio (CMRR). These products operate with a single ni P-P - E : 0.67µV (typical), f=0.01Hz to 1Hz supply voltage as low as 1.6V, while drawing ni P-P 7.5µA/amplifier (typical) of quiescent current. • Low Power and Supply Voltages: - I : 7.5µA/amplifier (typical) The Microchip Technology Inc. MCP6V11/1U/2/4 op Q amps are offered in single (MCP6V11 and - Wide Supply Voltage Range: 1.6V to 5.5V MCP6V11U), dual (MCP6V12) and quad (MCP6V14) • Small Packages: packages. They were designed using an advanced - Singles in SC70, SOT-23 CMOS process. - Duals in MSOP-8, 2×3TDFN - Quads in TSSOP-14 Package Types • Easy to Use: MCP6V11 MCP6V12 - Rail-to-Rail Input/Output SOT-23 MSOP - Gain Bandwidth Product: 80kHz (typical) - Unity Gain Stable VOUT 1 5 VDD VOUTA 1 8 VDD • Extended Temperature Range: -40°C to +125°C VSS 2 VINA– 2 7 VOUTB VIN+ 3 4 VIN– VINA+ 3 6 VINB– Typical Applications: VSS 4 5 VINB+ • Portable Instrumentation MCP6V11U MCP6V12 • Sensor Conditioning SC70, SOT-23 2×3TDFN* • Temperature Measurement VIN+ 1 5 VDD VOUTA 1 8 VDD • DC Offset Correction VSS 2 VINA– 2 EP 7 VOUTB • Medical Instrumentation VIN– 3 4 VOUT VINA+ 3 9 6 VINB– V 4 5 V + SS INB Design Aids: • SPICE Macro Models MCP6V14 • FilterLab® Software TSSOP • Microchip Advanced Part Selector (MAPS) VOUTA 1 14VOUTD • Analog Demonstration and Evaluation Boards VINA– 2 13VIND– • Application Notes VINA+ 3 12VIND+ VDD 4 11VSS Related Parts: VINB+ 5 10VINC+ V – 6 9 V – • MCP6V01/2/3: Auto-Zeroed, Spread Clock INB INC • MCP6V06/7/8: Auto-Zeroed VOUTB 7 8 VOUTC • MCP6V26/7/8: Auto-Zeroed, Low Noise * Includes Exposed Thermal Pad (EP); see Table3-1. • MCP6V31/1U/2/4: Zero-Drift, Low Power  2012-2014 Microchip Technology Inc. DS20005124B-page 1

MCP6V11/1U/2/4 Typical Application Circuit R R 1 3 V V IN OUT R 2 C R 2 4 U 1 R R5 MCP6XXX 2 VDD/2 U2 VDD/2 MCP6V11 OffsetVoltageCorrectionforPowerDriver DS20005124B-page 2  2012-2014 Microchip Technology Inc.

MCP6V11/1U/2/4 1.0 ELECTRICAL CHARACTERISTICS 1.1 Absolute Maximum Ratings † V –V .................................................................................................................................................................6.5V DD SS Current at Input Pins ..............................................................................................................................................±2mA Analog Inputs (V + and V –)(Note1) .....................................................................................V –1.0V to V +1.0V IN IN SS DD All other Inputs and Outputs .......................................................................................................V –0.3V to V +0.3V SS DD Difference Input voltage .................................................................................................................................|V –V | DD SS Output Short Circuit Current ...........................................................................................................................Continuous Current at Output and Supply Pins ......................................................................................................................±30mA Storage Temperature .............................................................................................................................-65°C to +150°C Maximum Junction Temperature ..........................................................................................................................+150°C ESD protection on all pins (HBM, CDM, MM) 2kV,1.5kV,400V Note 1: See Section4.2.1, Rail-to-Rail Inputs. †Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 1.2 Specifications TABLE 1-1: DC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, T = +25°C, V = +1.6V to +5.5V, V = GND, A DD SS V = V /3,V =V /2, V =V /2, R = 100kΩ to V and C = 20pF (refer to Figure1-4 and Figure1-5). CM DD OUT DD L DD L L L Parameters Sym. Min. Typ. Max. Units Conditions Input Offset Input Offset Voltage V -8 — +8 µV T = +25°C OS A Input Offset Voltage Drift with TC -50 — +50 nV/°C T = -40 to +125°C 1 A Temperature (Linear Temp. Co.) (Note1) Input Offset Voltage Quadratic TC — ±0.08 — nV/°C2 T = -40 to +125°C 2 A Temp. Co. Power Supply Rejection Ratio PSRR 118 135 — dB Input Bias Current and Impedance Input Bias Current I — +5 — pA B Input Bias Current across Temperature I — +17 — pA T = +85°C B A I 0 +2.9 +5 nA T = +125°C B A Input Offset Current I — ±50 — pA OS Input Offset Current across Temperature I — ±80 — pA T = +85°C OS A I -1 ±0.4 +1 nA T = +125°C OS A Common Mode Input Impedance Z — 1013||6 — Ω||pF CM Differential Input Impedance Z — 1013||6 — Ω||pF DIFF Note 1: For Design Guidance only; not tested. 2: Figure2-18 shows how V and V changed across temperature for the first production lot. CML CMH  2012-2014 Microchip Technology Inc. DS20005124B-page 3

MCP6V11/1U/2/4 TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise indicated, T = +25°C, V = +1.6V to +5.5V, V = GND, A DD SS V = V /3,V =V /2, V =V /2, R = 100kΩ to V and C = 20pF (refer to Figure1-4 and Figure1-5). CM DD OUT DD L DD L L L Parameters Sym. Min. Typ. Max. Units Conditions Common Mode Common Mode V — — V 0.15 V (Note2) CML SS Input Voltage Range Low Common Mode V V +0.2 — — V (Note2) CMH DD Input Voltage Range High Common Mode Rejection Ratio CMRR 108 125 — dB V = 1.6V, DD V = -0.15V to 1.8V CM (Note2) CMRR 119 135 — dB V = 5.5V, DD V = -0.15V to 5.7V CM (Note2) Open-Loop Gain DC Open-Loop Gain (large signal) A 100 120 — dB V =1.6V, OL DD V = 0.3V to 1.4V OUT A 112 135 — dB V =5.5V, OL DD V = 0.3V to 5.3V OUT Output Minimum Output Voltage Swing V V V +14 V +45 mV R =10kΩ, G = +2, OL SS SS SS L 0.5V input overdrive V — V +1.4 — mV R =100kΩ, G = +2, OL SS L 0.5V input overdrive Maximum Output Voltage Swing V V –45 V –14 V mV R =10kΩ, G = +2, OH DD DD DD L 0.5V input overdrive V — V –1.4 — mV R =100kΩ, G = +2, OH DD L 0.5V input overdrive Output Short Circuit Current I — ±5 — mA V =1.6V SC DD I — ±17 — mA V =5.5V SC DD Power Supply Supply Voltage V 1.6 — 5.5 V DD Quiescent Current per amplifier I 4 7.5 11 µA I = 0, MCP6V11/1U Q O 3 6.5 11 I = 0, MCP6V12/14 O POR Trip Voltage V 0.9 — 1.5 V POR Note 1: For Design Guidance only; not tested. 2: Figure2-18 shows how V and V changed across temperature for the first production lot. CML CMH DS20005124B-page 4  2012-2014 Microchip Technology Inc.

MCP6V11/1U/2/4 TABLE 1-2: AC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, T = +25°C, V = +1.6V to +5.5V, V = GND, A DD SS V = V /3, V =V /2, V =V /2, R =100kΩ to V and C =20pF (refer to Figure1-4 and Figure1-5). CM DD OUT DD L DD L L L Parameters Sym. Min. Typ. Max. Units Conditions Amplifier AC Response Gain Bandwidth Product GBWP — 80 — kHz Slew Rate SR — 0.03 — V/µs Phase Margin PM — 70 — ° G = +1 Amplifier Noise Response Input Noise Voltage E — 0.67 — µV f = 0.01Hz to 1Hz ni P-P E — 2.1 — µV f = 0.1Hz to 10Hz ni P-P Input Noise Voltage Density e — 102 — nV/√Hz f < 500Hz ni Input Noise Current Density i — 4 — fA/√Hz ni Amplifier Distortion (Note1) Intermodulation Distortion (AC) IMD — 50 — µV V tone = 50mV at 100Hz, G = 1 PK CM PK N Amplifier Step Response Start Up Time t — 2 — ms G=+1, 0.1% V settling (Note2) STR OUT Offset Correction Settling Time t — 300 — µs G = +1, V step of 2V, STL IN V within 100µV of its final value OS Output Overdrive Recovery Time t — 450 — µs G = -10, ±0.5V input overdrive to V /2, ODR DD V 50% point to V 90% point (Note3) IN OUT Note 1: These parameters were characterized using the circuit in Figure1-6. In Figure2-37 and Figure2-38, there is an IMD tone at DC, a residual tone at1kHz and other IMD tones and clock tones. 2: High gains behave differently; see Section4.3.3, Offset at Power Up. 3: t includes some uncertainty due to clock edge timing. ODR TABLE 1-3: TEMPERATURE SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, all limits are specified for: V = +1.6V to +5.5V, DD V = GND. SS Parameters Sym. Min. Typ. Max. Units Conditions Temperature Ranges Specified Temperature Range T -40 — +125 °C A Operating Temperature Range T -40 — +125 °C (Note1) A Storage Temperature Range T -65 — +150 °C A Thermal Package Resistances Thermal Resistance, 5L-SC-70  — 209 — °C/W JA Thermal Resistance, 5L-SOT-23  — 201 — °C/W JA Thermal Resistance, 8L-2×3TDFN θ — 53 — °C/W JA Thermal Resistance, 8L-MSOP θ — 211 — °C/W JA Thermal Resistance, 14L-TSSOP θ — 100 — °C/W JA Note 1: Operation must not cause T to exceed Maximum Junction Temperature specification (+150°C). J  2012-2014 Microchip Technology Inc. DS20005124B-page 5

MCP6V11/1U/2/4 1.3 Timing Diagrams 1.4 Test Circuits The circuits used for most DC and AC tests are shown 1.6Vto5.5V in Figure1-4 and Figure1-5. Lay the bypass capacitors 1.6V V 0V out as discussed in Section4.3.10, Supply Bypassing DD and Filtering. R is equal to the parallel combination of N tSTR 1.001(VDD/3) RF and RG to minimize bias current effects. VOUT 0.999(VDD/3) VDD 1µF FIGURE 1-1: Amplifier Start Up. VIN RN RISO VOUT MCP6V1X VIN 100nF CL RL V /3 t DD STL V +100µV OS V R R L V G F OS VOS–100µV FIGURE 1-4: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. FIGURE 1-2: Offset Correction Settling Time. V DD 1µF VIN VDD/3 RN RISO VOUT MCP6V1X t ODR C R 100nF L L V V IN DD V t R R L ODR G F V OUT V /2 FIGURE 1-5: AC and DC Test Circuit for DD Most Inverting Gain Conditions. V SS The circuit in Figure1-6 tests the input’s dynamic FIGURE 1-3: Output Overdrive Recovery. behavior (i.e., IMD, t , t and t ). The STR STL ODR potentiometer balances the resistor network (V OUT should equal V at DC). The op amp’s Common REF mode input voltage is V =V /2. The error at the CM IN input (V ) appears at V with a noise gain of ERR OUT 10V/V. 11.0kΩ 100kΩ 500Ω 0.1% 0.1% 25turn V =V /3 REF DD V DD R ISO 1µF 0Ω V OUT V IN 100nF C R L L MCP6V1X 20pF open V L 11.0kΩ 100kΩ 249Ω 0.1% 0.1% 1% FIGURE 1-6: Test Circuit for Dynamic Input Behavior. DS20005124B-page 6  2012-2014 Microchip Technology Inc.

MCP6V11/1U/2/4 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, T =+25°C, V =+1.6V to 5.5V, V =GND, V =V /3, V =V /2, A DD SS CM DD OUT DD V =V /2, R =100kΩ to V and C = 20pF. L DD L L L 2.1 DC Input Precision 30% 8 s 4T2A =Sa+m25p°lCes 66 VRRCeeMpprr=ee ssVeeCnnMLttaattiivveePPaarrtt ce25% VDD= 1.6V and 5.5V V) e of Occurren1250%% e (µVoltagesetV4020 +++1-2282455550°°°°CCCCC ag1100%% OffO-2 ent ut-4 c p Per 5% In-6 0% -8 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 Input Offset Voltage (µV) Power Supply Voltage (V) FIGURE 2-1: Input Offset Voltage. FIGURE 2-4: Input Offset Voltage vs. Power Supply Voltage with V =V . CM CML 30% 8 s 4V2D DS=a m1.p6lVe sand 5.5V 66 VRRCeeMpprr=ee ssVeeCnnMHttaattiivveePPaarrtt ce25% V) 125°C Occurren20% e (µoltage42 +++-22845550°°°°CCCC e of 15% VsetV00 ag1100%% OffO-2 ent ut-4 c p Per 5% In-6 0% -8 -50 -40 -30 -20 -10 0 10 20 30 40 50 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 Input Offset Voltage Drift; TC (nV/°C) Power Supply Voltage (V) 1 FIGURE 2-2: Input Offset Voltage Drift. FIGURE 2-5: Input Offset Voltage vs. Power Supply Voltage with V =V . CM CMH 35% 8 42 Samples Representative Part es30% VDD= 1.6V and 5.5V 66 nc V) urre25% e (µe 4 ntage of Occn11210500%%%% VoltagOffsetVO-0202 VDD= 1.6V VDD= 5.5V ce ut-4 Per 5% InpI-6 0% -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 -88 Input Offset Voltage's Quadratic Temp Co; 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 TC (nV/°C2) Output Voltage (V) 2 FIGURE 2-3: Input Offset Voltage FIGURE 2-6: Input Offset Voltage vs. Quadratic Temp. Co. Output Voltage.  2012-2014 Microchip Technology Inc. DS20005124B-page 7

MCP6V11/1U/2/4 Note: Unless otherwise indicated, T =+25°C, V =+1.6V to 5.5V, V =GND, V =V /3, V =V /2, A DD SS CM DD OUT DD V =V /2, R =100kΩ to V and C = 20pF. L DD L L L 8 45% 66 VRRDeeDpprr=ee 1ss.ee6nnVttaattiivveePPaarrtt ss40% 2T1A =S a+m25p°lCes e (µV)oltage 42 rrenceOccur33230550%%%% VsetV 00 e of 20% OffInputO---246 ++++11-222844550055°°°°°°CCCCCC agercentaPe1115055%%%% -8 0% -0.5 0.0 0.5 1.0 1.5 2.0 2.5 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 Input Common Mode Voltage (V) 1/PSRR (µV/V) FIGURE 2-7: Input Offset Voltage vs. FIGURE 2-10: PSRR. Common Mode Voltage with V =1.6V. DD 8 45% 66 VRRDeeDpprr=ee 5ss.ee5nnVttaattiivveePPaarrtt ss40% 2T1A =S a+m25p°lCes e (µV)ge 4 rrenceur333050%%% a 2 c olt Oc25% VsetV 00 e of 20% VVDD=11.66VV VVDD=55.55VV OffInputO---246 ++++11-222844550055°°°°CCCCCC agercentaPe1115055%%%% -8 0% 0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 - Input Common Mode Voltage (V) 1/A (µV/V) OL FIGURE 2-8: Input Offset Voltage vs. FIGURE 2-11: DC Open-Loop Gain. Common Mode Voltage with V =5.5V. DD 70% 160 21 Samples es60% TA= 25°C 155 nc 150 Occurre4500%% VDD= 5.5V B)RR (d111444505 PSRR ge of 30% SR, PS111333505 a R tn2200%% M125 erce10% VDD= 1.6V C120 P 0% 115 VVVDDDD== 551..655VVV CCMMRRRR 110 6 2 8 4 0 4 8 2 6 1. 1. 0. 0. 0. 0. 0. 1. 1. -50 -25 0 25 50 75 100 125 - - - - 1/CMRR (µV/V) Ambient Temperature (°C) FIGURE 2-9: CMRR. FIGURE 2-12: CMRR and PSRR vs. Ambient Temperature. DS20005124B-page 8  2012-2014 Microchip Technology Inc.

MCP6V11/1U/2/4 Note: Unless otherwise indicated, T =+25°C, V =+1.6V to 5.5V, V =GND, V =V /3, V =V /2, A DD SS CM DD OUT DD V =V /2, R =100kΩ to V and C = 20pF. L DD L L L 160 1001000n 155 A)A VDD= 5.5V B)150 s ( n (dGain111444505 VDD= 5.5V rentCurr10010n op en-Loope111133325055 VDD= 1.6V et s, Offseas 111100000000p IOS DC OD120 ut Bi 1100p IB p 115 n I 110 111pp -50 -25 0 25 50 75 100 125 25 35 45 55 65 75 85 95 105 115 125 Ambient Temperature (°C) Ambient Temperature (°C) FIGURE 2-13: DC Open-Loop Gain vs. FIGURE 2-16: Input Bias and Offset Ambient Temperature. Currents vs. Ambient Temperature with V =+5.5V. DD 200 1.E1-00m2 pA)p 115500 TVADDDD== + 58.55°VC A)A11..EE-1100mm33 nts ( 100 de (1.1E0-004µ e u et Curre 5000 IB MagnitM11..EE1--000165µµ s, Offss -50 urrentu111..1EEE011---000000788nnn +++1882555°°CCC ut Bianpu--110500 IOS put CIn11..1EE0--100190pn +-2450°°CC I -200 1.E1-101pp 0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 - Common Mode Input Voltage (V) Input Voltage (V) FIGURE 2-14: Input Bias and Offset FIGURE 2-17: Input Bias Current vs. Input Currents vs. Common Mode Input Voltage with Voltage (below V ). SS T =+85°C. A 5000 pA)p 44000000 TVVADDDD== +551..2555VV°C s ( ent 33000000 urr C 2000 et se IB Off 1000 s, as 0 ut Biu-11000000 IOS p n I -2000 5 0 5 0 5 0 5 0 5 0 5 0 5 0 0. 0. 0. 1. 1. 2. 2. 3. 3. 4. 4. 5. 5. 6. - Common Mode Input Voltage (V) FIGURE 2-15: Input Bias and Offset Currents vs. Common Mode Input Voltage with T =+125°C. A  2012-2014 Microchip Technology Inc. DS20005124B-page 9

MCP6V11/1U/2/4 Note: Unless otherwise indicated, T =+25°C, V =+1.6V to 5.5V, V =GND, V =V /3, V =V /2, A DD SS CM DD OUT DD V =V /2, R =100kΩ to V and C = 20pF. L DD L L L 2.2 Other DC Voltages and Currents 0.4 40 1 Wafer Lot A) geVoltagModemmonput ComInpom (V)HeadrooH---000000000.......302310123 ULpopweerr (( VVCCMMLH––VVSDSD)) ort Circuit Current (mutput Sho---1321230000000 ++++++11--4288242205505555°°°°°°°°CCCCCCCC O -0.4 -40 -50 -25 0 25 50 75 100 125 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 Ambient Temperature (°C) Power Supply Voltage (V) FIGURE 2-18: Input Common Mode FIGURE 2-21: Output Short Circuit Current Voltage Headroom (Range) vs. Ambient vs. Power Supply Voltage. Temperature. 1000 11 Representative Part mV)m er)10 oom (HeadrooltageHput Vo 1011000 VOL–VSSVVDDDD–VVOOHH VVDDDDDD== 51..56VV Current (µA/amplifipply C 45678923 +++1822555°°°CCC tOut Su 1 -40°C 1 0 0.1 1 10 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 Output Current Magnitude (mA) Power Supply Voltage (V) FIGURE 2-19: Output Voltage Headroom FIGURE 2-22: Supply Current vs. Power vs. Output Current. Supply Voltage. 12 40% 11 RL= 25 k(cid:525) 850 Samples m (mV)1089 esurrencecu33325055%%%% 11TAWW=aa +ffee2rr5LL°Coott Headroo 567 VDD= 5.5V f Ocge of212050%%% ut Outpu 41234 VDD= 1.6V VOL–VSS VDD–VOH taPercentP1055%%% 0% 0 44 66 88 00 22 44 66 88 00 22 44 1 1 1 2 2 2 2 2 3 3 3 -50 -25 0 25 50 75 100 125 1. 1. 1. 1. 1. 1. 1. 1. 1. 1. 1. Ambient Temperature (°C) POR Trip Voltage (V) FIGURE 2-20: Output Voltage Headroom FIGURE 2-23: Power-on Reset Trip vs. Ambient Temperature. Voltage. DS20005124B-page 10  2012-2014 Microchip Technology Inc.

MCP6V11/1U/2/4 Note: Unless otherwise indicated, T =+25°C, V =+1.6V to 5.5V, V =GND, V =V /3, V =V /2, A DD SS CM DD OUT DD V =V /2, R =100kΩ to V and C = 20pF. L DD L L L 1.6 1.4 V)1.2 e ( g1.0 a Volt0.8 p Tri0.6 R R O0.4 P 0.2 0.0 -50 -25 0 25 50 75 100 125 Ambient Temperature (°C) FIGURE 2-24: Power-on Reset Voltage vs. Ambient Temperature.  2012-2014 Microchip Technology Inc. DS20005124B-page 11

MCP6V11/1U/2/4 Note: Unless otherwise indicated, T =+25°C, V =+1.6V to 5.5V, V =GND, V =V /3, V =V /2, A DD SS CM DD OUT DD V =V /2, R =100kΩ to V and C = 20pF. L DD L L L 2.3 Frequency Response 100 140 100 90 z) PM H120 90 R, PSRR (dB) 4567800000 CMRR width Product (k1068000 VDD= 5.5V 678000 se Margin (°) RCMR 2300 PSRR dn Band 40 GBWP VDD= 1.6V 50 haPh ai 20 40 10 G 0 0 30 1.E1+001 1.E10+002 1.E1+k03 1.E10+k04 1.1E0+00k5 -50 -25 0 25 50 75 100 125 Frequency (Hz) Ambient Temperature (°C) FIGURE 2-25: CMRR and PSRR vs. FIGURE 2-28: Gain Bandwidth Product Frequency. and Phase Margin vs. Ambient Temperature. 70 0 140 100 60 VCDLD== 2 10. 6pVF -30 Hz)120 PM GBWP RF= 1 M(cid:159) 90 k n-Loop Gain (dB)Open 1234510000000 (cid:145)| AAOOLL| ------9611211005218800000 n-Loop Phase (°)Open dwidth Product (n Ban106840000 VDD= 1.6V VDD= 5.5V 67850000 hase Margin (°)hP -10 -240 Gai 20 40 -20 -270 0 30 1.E10+002 1.E1+k03 1.1E0+k04 1.1E0+00k5 1.E1+M06 0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Frequency (Hz) - Common Mode Input Voltage (V) FIGURE 2-26: Open-Loop Gain vs. FIGURE 2-29: Gain Bandwidth Product Frequency with V =1.6V. and Phase Margin vs. Common Mode Input DD Voltage. 70 0 140 100 60 VCDLD== 2 50. 5pVF -30 Hz)120 VDD= 5.5V 90 n-Loop Gain (dB)Open 1234510000000 (cid:145)| AAOOLL| ------9611211005218800000 n-Loop Phase (°)Open dwidth Product (kn Ban106840000 GBVWDDP= 1.P6MV 67850000 hase Margin (°)Ph -10 -240 Gai 20 40 -20 -270 0 30 1.E10+002 1.E1+k03 1.1E0+k04 1.1E0+00k5 1.E1+M06 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Frequency (Hz) Output Voltage (V) FIGURE 2-27: Open-Loop Gain vs. FIGURE 2-30: Gain Bandwidth Product Frequency with V =5.5V. and Phase Margin vs. Output Voltage. DD DS20005124B-page 12  2012-2014 Microchip Technology Inc.

MCP6V11/1U/2/4 Note: Unless otherwise indicated, T =+25°C, V =+1.6V to 5.5V, V =GND, V =V /3, V =V /2, A DD SS CM DD OUT DD V =V /2, R =100kΩ to V and C = 20pF. L DD L L L 1.E1+0005k 140 nce VDD= 1.6V 120 ut Impeda11..EE++1001034kk ChannelRTI (dB)10800 MCP6V12 op Outpsed-Loo11()(cid:159)..EE++100102100 G = 1 V/V nnel-to-Chanaration, Sepa 246000 MCP6V14 Clo GG == 1 1011 VV//VV 1.E+001 0 1.E10+002 1.E1+k03 1.E10+k04 1.1E0+00k5 1.E1+M06 1.E1+k03 1.1E0+k04 1.1E0+00k5 1.E1M+06 Frequency (Hz) Frequency (Hz) FIGURE 2-31: Closed-Loop Output FIGURE 2-33: Channel-to-Channel Impedance vs. Frequency with V =1.6V. Separation vs. Frequency. DD 1.E1+0005k 10 ce VDD= 5.5V ng dan1.E+1004k iSwi VDD= 5.5V mpe ge ag op Output Io11()(cid:159)..EE++1001023k0 t VoltOutput)(V-PP- 111.E+02 V1DD.E=+ 10.63V 1.E+04 1.E+05 Lo m Closed-1.E+0110 GGG === 1 1 0 111 VVV///VVV ximuMax 1.E+001 00.11 1.E10+002 1.E1+k03 1.E10+k04 1.1E0+00k5 1.E1+M06 100 1k 10k 100k Frequency (Hz) Frequency (Hz) FIGURE 2-32: Closed-Loop Output FIGURE 2-34: Maximum Output Voltage Impedance vs. Frequency with V =5.5V. Swing vs. Frequency. DD  2012-2014 Microchip Technology Inc. DS20005124B-page 13

MCP6V11/1U/2/4 Note: Unless otherwise indicated, T =+25°C, V =+1.6V to 5.5V, V =GND, V =V /3, V =V /2, A DD SS CM DD OUT DD V =V /2, R =100kΩ to V and C = 20pF. L DD L L L 2.4 Input Noise and Distortion 1000 1000 1000 nsity; eni oltage; V)PK GVDDDDDMt=o n1e V =/V 50 mVPPKK,, f = 100 Hz e V µ ise Voltage DInput Noe(nV/Hz)(cid:165)ni1011000 VVDDDD== 51..56VV 1110000 d Input Noise ntegratedE(µV)niP-P (m, RTI (pectrumMD SpI1011000 IMD tone at DVVCDDDD== 51..56VV 100 Hz tone 1 Eni(0 Hz to f) 1 I 11 1.E1+001.E1+0011.E10+0021.E1+k031.E10+k041.1E0+00k5 1.E1+000 1.E+01 1010.E+02 1.E+031k 1.E+04 1.1E0+k05 Frequency (Hz) Frequency (Hz) FIGURE 2-35: Input Noise Voltage Density FIGURE 2-38: Inter-Modulation Distortion and Integrated Input Noise Voltage vs. vs. Frequency with V Disturbance DD Frequency. (see Figure1-6). 160 f < 500 Hz VDD= 1.6V yy 114400 ensit 120 VDD= 1.6V e(t)ni DoltageDoise VoNoHz)(nV/(cid:165)(cid:165)108680000 VDD= 5.5V Noise Voltage; N(0.5 µV/div) NNPPBBWW==1100HHzz nput In 242000 Input 0 NPBW = 1 Hz 5 0 5 0 5 0 5 0 5 0 5 0 5 0 0. 0. 0. 1. 1. 2. 2. 3. 3. 4. 4. 5. 5. 6. 0 10 20 30 40 50 60 70 80 90 100 - Common Mode Input Voltage (V) Time (s) FIGURE 2-36: Input Noise Voltage Density FIGURE 2-39: Input Noise vs. Time with vs. Input Common Mode Voltage. 1Hz and 10Hz Filters and V =1.6V. DD 1000 3.0 GVCCDMMMt=o n1 eV =/V 50 mVPPKK, f = 100 Hz 2.5 VDD= 5.5V (µV)m, RTI (mPK100 IMD tone at DrCesidual 100 Hz tone Voltage; e(t)0112ni....V/div)5050 pectruMD Sp 1100 VVDDDD== 15..65VV Noise nputN--100...(0.5 µ050 NPBW = 100 Hz I I -1.5 NPBW = 1 Hz 11 -2.0 1.E1+00 1.E1+001 1.E10+002 1.E1+k03 1.1E0+k04 1.1E0+00k5 0 10 20 30 40 50 60 70 80 90 100 Frequency (Hz) Time (s) FIGURE 2-37: Inter-Modulation Distortion FIGURE 2-40: Input Noise vs. Time with vs. Frequency with V Disturbance (see 1Hz and 10Hz Filters and V =5.5V. CM DD Figure1-6). DS20005124B-page 14  2012-2014 Microchip Technology Inc.

MCP6V11/1U/2/4 Note: Unless otherwise indicated, T =+25°C, V =+1.6V to 5.5V, V =GND, V =V /3, V =V /2, A DD SS CM DD OUT DD V =V /2, R =100kΩ to V and C = 20pF. L DD L L L 2.5 Time Response 40 80 80 Offset Voltage (µV)nputO11223305050505 VVDDDD== 15..65VV TVVPOOCSSB ----024642860000000 Temperature (°C)PCBT Voltage (10 mV/div)utputV345672000000 VGD =D =1 5.5V I -5 Temperature increased by -100 O10 using heat gun for 5 seconds. -10 -120 0 0 10 20 30 40 50 60 70 80 90 100 0 20 40 60 80 100 120 140 160 180 200 Time (s) Time (µs) FIGURE 2-41: Input Offset Voltage vs. FIGURE 2-44: Non-inverting Small Signal Time with Temperature Change. Step Response. 8 6 5.5 7 G = 1 5 5.0 VGD =D =1 5.5V V) 6 VDD 4 V) 4.5 utOffset Voltage (mO 23451 POR Trip Point 0123-1Supply Voltage (wer tput Voltage (V)Out223341......050505 Inp-01 VOS --32Po 01..50 -2 -4 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Time (ms) Time (ms) FIGURE 2-42: Input Offset Voltage vs. FIGURE 2-45: Non-inverting Large Signal Time at Power Up. Step Response. 7 80 e (V) 56 VIN VGD =D =1 5.5V V/div)6700 VGD =D =-1 5.5V oltag 4 VOUT 10 m50 ut V 3 ge (40 p a OutO 2 VoltV30 nput, 1 utput20 I 0 O10 -1 0 0 2 4 6 8 10 12 14 16 18 20 0 20 40 60 80 100 120 140 160 180 200 Time (ms) Time (µs) FIGURE 2-43: The MCP6V11/1U/2/4 FIGURE 2-46: Inverting Small Signal Step Family Shows No Input Phase Reversal with Response. Overdrive.  2012-2014 Microchip Technology Inc. DS20005124B-page 15

MCP6V11/1U/2/4 Note: Unless otherwise indicated, T =+25°C, V =+1.6V to 5.5V, V =GND, V =V /3, V =V /2, A DD SS CM DD OUT DD V =V /2, R =100kΩ to V and C = 20pF. L DD L L L 5.5 7 7 5.0 VGD =D =-1 5.5V 6 6 4.5 v) tput Voltage (V)Out223341......050505 Output Voltage (V)p 234512 VOUT VVG0.D 5=DV ==- 1O550v. 55VeVVr/Vdrive G VIN 234512ltage ×G (1 V/diut Vo 1.0 p 0.5 0 G VIN VOUT 0In 0.0 -1 -1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Time (ms) 0 1 1 2 Ti2me (3500 3µs/di4v) 4 5 5 6 FIGURE 2-47: Inverting Large Signal Step FIGURE 2-49: Output Overdrive Recovery Response. vs. Time with G=-10V/V. 0.08 1.E1-00m2 0.5V Input Overdrive 0.07 VDD= 5.5V s) Falling Edge e ( V/µs)00..0056 ery Tim VDD= 1.6V Rate (0.04 Recov1.E-10m3 tODR, low ew e0.03 ve v VVDDDD==55.55VV Sl0.02 dri 0.01 VDD= 1.6V Over tODR, high Rising Edge 0.00 1.E1-0004µ -50 -25 0 25 50 75 100 125 1 10 100 1000 Ambient Temperature (°C) Inverting Gain Magnitude (V/V) FIGURE 2-48: Slew Rate vs. Ambient FIGURE 2-50: Output Overdrive Recovery Temperature. Time vs. Inverting Gain. DS20005124B-page 16  2012-2014 Microchip Technology Inc.

MCP6V11/1U/2/4 3.0 PIN DESCRIPTIONS Descriptions of the pins are listed in Table3-1. TABLE 3-1: PIN FUNCTION TABLE MCP6V11 MCP6V11U MCP6V12 MCP6V14 Symbol Description SOT-23, SOT-23 2×3TDFN MSOP TSSOP SC-70 1 4 1 1 1 V , V Output (Op Amp A) OUT OUTA 4 3 2 2 2 V –, V – Inverting Input (Op Amp A) IN INA 3 1 3 3 3 V +, V + Non-inverting Input (Op Amp A) IN INA 5 5 8 8 4 V Positive Power Supply DD — — 5 5 5 V + Non-inverting Input (Op Amp B) INB — — 6 6 6 V – Inverting Input (Op Amp B) INB — — 7 7 7 V Output (Op Amp B) OUTB — — — — 8 V Output (Op Amp C) OUTC — — — — 9 V – Inverting Input (Op Amp C) INC — — — — 10 V + Non-inverting Input (Op Amp C) INC 2 2 4 4 11 V Negative Power Supply SS — — — — 12 V + Non-inverting Input (Op Amp D) IND — — — — 13 V – Inverting Input (Op Amp D) IND — — — — 14 V Output (Op Amp D) OUTD — — 9 — — EP Exposed Thermal Pad (EP); must be connected to V SS 3.1 Analog Outputs 3.4 Exposed Thermal Pad (EP) The analog output pins (V ) are low-impedance There is an internal connection between the exposed OUT voltage sources. thermal pad (EP) and the V pin; they must be SS connected to the same potential on the printed circuit 3.2 Analog Inputs board (PCB). This pad can be connected to a PCB ground plane to The non-inverting and inverting inputs (V +, V –, …) IN IN provide a larger heat sink. This improves the package are high-impedance CMOS inputs with low bias thermal resistance (θ ). currents. JA 3.3 Power Supply Pins The positive power supply (V ) is 1.6V to 5.5V higher DD than the negative power supply (V ). For normal SS operation, the other pins are between V and V . SS DD Typically, these parts are used in a single (positive) supply configuration. In this case, V is connected to SS ground and V is connected to the supply. V will DD DD need bypass capacitors.  2012-2014 Microchip Technology Inc. DS20005124B-page 17

MCP6V11/1U/2/4 NOTES: DS20005124B-page 18  2012-2014 Microchip Technology Inc.

MCP6V11/1U/2/4 4.0 APPLICATIONS The Low-Pass Filter reduces high-frequency content, including harmonics of the Chopping Clock. The MCP6V11/1U/2/4 family of zero-drift op amps is The Output Buffer drives external loads at the V pin manufactured using Microchip’s state of the art CMOS OUT (V is an internal reference voltage). process. It is designed for precision applications with REF requirements for small packages and low power. Its low The Oscillator runs at fOSC1=50kHz. Its output is supply voltage and low quiescent current make the divided by two, to produce the Chopping Clock rate of MCP6V11/1U/2/4 devices ideal for battery-powered fCHOP=25kHz. applications. The internal POR part starts the part in a known good state, protecting against power supply brown-outs. 4.1 Overview of Zero-Drift Operation The Digital Control block controls switching and POR Figure4-1 shows a simplified diagram of the events. MCP6V11/1U/2/4 zero-drift op amps. This diagram will 4.1.2 CHOPPING ACTION be used to explain how slow voltage errors are reduced in this architecture (much better VOS, ΔVOS/ΔTA (TC1), Figure4-2 shows the amplifier connections for the first CMRR, PSRR, AOL and 1/f noise). phase of the Chopping Clock and Figure4-3 shows them for the second phase. Its slow voltage errors alternate in polarity, making the average error small. V REF Output V + V IN OUT Buffer VIN+ VIN– Main Amp. NC V – Main IN Amp. NC Low-Pass Filter Low-Pass Filter Aux. Amp. Chopper Chopper Aux. Input Output Amp. Switches Switches FIGURE 4-2: First Chopping Clock Phase; Equivalent Amplifier Diagram. V + Oscillator DigitalControl POR IN FIGURE 4-1: Simplified Zero-Drift Op V – Main IN Amp Functional Diagram. Amp. NC 4.1.1 BUILDING BLOCKS Low-Pass The Main Amplifier is designed for high gain and Filter bandwidth, with a differential topology. Its main input pair (+ and - pins at the top left) is used for the higher frequency portion of the input signal. Its auxiliary input pair (+ and - pins at the bottom left) is used for the low- Aux. frequency portion of the input signal and corrects the Amp. op amp’s input offset voltage. Both inputs are added together internally. The Auxiliary Amplifier, Chopper Input Switches and FIGURE 4-3: Second Chopping Clock Chopper Output Switches provide a high DC gain to the Phase; Equivalent Amplifier Diagram. input signal. DC errors are modulated to higher frequencies, while white noise is modulated to low frequency.  2012-2014 Microchip Technology Inc. DS20005124B-page 19

MCP6V11/1U/2/4 4.1.3 INTERMODULATION DISTORTION (IMD) Bond V These op amps will show intermodulation distortion DD Pad (IMD) products when an AC signal is present. The signal and clock can be decomposed into sine wave tones (Fourier series components). These tones Bond Input Bond V + V – interact with the zero-drift circuitry’s nonlinear response IN Pad Stage Pad IN to produce IMD tones at sum and difference frequen- cies. Each of the square wave clock’s harmonics has a series of IMD tones centered on it. See Figure2-37 and Bond Figure2-38. VSS Pad 4.2 Other Functional Blocks FIGURE 4-4: Simplified Analog Input ESD Structures. 4.2.1 RAIL-TO-RAIL INPUTS The input ESD diodes clamp the inputs when they try The input stage of the MCP6V11/1U/2/4 op amps uses to go more than one diode drop below V . They also two differential CMOS input stages in parallel. One SS clamp any voltages well above V ; their breakdown operates at low Common mode input voltage (V , DD CM voltage is high enough to allow normal operation, but which is approximately equal to V + and V – in IN IN not low enough to protect against slow overvoltage normal operation) and the other at high V . With this CM (beyond V ) events. Very fast ESD events (that meet topology, the input operates with V up to V +0.2V, DD CM DD the spec) are limited so that damage does not occur. and down to V –0.15V, at +25°C (see Figure2-18). SS The input offset voltage (V ) is measured at In some applications, it may be necessary to prevent OS V =V –0.15V and V +0.2V to ensure proper excessive voltages from reaching the op amp inputs; CM SS DD operation. Figure4-5 shows one approach to protecting these inputs. D and D may be small signal silicon diodes, The transition between the input stages occurs when 1 2 Schottky diodes for lower clamping voltages or diode V ≈V –0.9V (see Figure2-7 and Figure2-8). For CM DD connected FETs for low leakage. the best distortion and gain linearity, with non-inverting gains, avoid this region of operation. V DD 4.2.1.1 Phase Reversal The input devices are designed to not exhibit phase U1 D inversion when the input pins exceed the supply 1 MCP6V1X voltages. Figure2-43 shows an input voltage V 1 exceeding both supplies with no phase inversion. D V 2 OUT V 4.2.1.2 Input Voltage Limits 2 In order to prevent damage and/or improper operation of these amplifiers, the circuit must limit the voltages at FIGURE 4-5: Protecting the Analog Inputs the input pins (see Section1.1 “Absolute Maximum Against High Voltages. Ratings†”). This requirement is independent of the current limits discussed later on. The ESD protection on the inputs can be depicted as shown in Figure4-4. This structure was chosen to protect the input transistors against many (but not all) overvoltage conditions, and to minimize input bias current (I ). B DS20005124B-page 20  2012-2014 Microchip Technology Inc.

MCP6V11/1U/2/4 4.2.1.3 Input Current Limits 4.3 Application Tips In order to prevent damage and/or improper operation 4.3.1 INPUT OFFSET VOLTAGE OVER of these amplifiers, the circuit must limit the currents TEMPERATURE into the input pins (see Section1.1 “Absolute Maxi- mum Ratings†”). This requirement is independent of Table1-1 gives both the linear and quadratic the voltage limits discussed previously. temperature coefficients (TC and TC ) of input offset 1 2 voltage. The input offset voltage, at any temperature in Figure4-6 shows one approach to protecting these inputs. The resistors R and R limit the possible the specified range, can be calculated as follows: 1 2 current in or out of the input pins (and into D and D ). 1 2 The diode currents will dump onto V . EQUATION 4-1: DD 2 V T  = V +TC T+TC T OS A OS 1 2 V DD Where: ΔT = T –25°C U A 1 D 1 V (T ) = input offset voltage at T MCP6V1X OS A A V1 VOS = input offset voltage at +25°C R1 D2 VOUT TC1 = linear temperature coefficient V 2 TC = quadratic temperature coefficient 2 R 2 4.3.2 DC GAIN PLOTS V –min(V ,V ) SS 1 2 min(R ,R )> 1 2 2mA Figures2-9 to 2-11 are histograms of the reciprocals max(V1,V2)–VDD (in units of µV/V) of CMRR, PSRR and AOL, min(R1,R2)> 2mA respectively. They represent the change in input offset voltage (V ) with a change in Common mode input OS FIGURE 4-6: Protecting the Analog Inputs voltage (V ), power supply voltage (V ) and output CM DD Against High Currents. voltage (V ). OUT It is also possible to connect the diodes to the left of The 1/AOL histogram is centered near 0µV/V because resistors R and R . In this case, the currents through the measurements are dominated by the op amp’s 1 2 the diodes D and D need to be limited by some other input noise. The negative values shown represent 1 2 mechanism. The resistors then serve as in-rush current noise and tester limitations, not unstable behavior. Pro- limiters; the DC current into the input pins (VIN+ and duction tests make multiple VOS measurements, which V –) should be very small. validates an op amp's stability; an unstable part would IN show greater V variability, or the output would stick A significant amount of current can flow out of the OS at one of the supply rails. inputs (through the ESD diodes) when the Common mode voltage (V ) is below ground (V ); see CM SS 4.3.3 OFFSET AT POWER UP Figure2-17. When these parts power up, the input offset (V ) OS 4.2.2 RAIL-TO-RAIL OUTPUT starts at its uncorrected value (usually less than ±5mV). Circuits with high DC gain can cause the The output voltage range of the MCP6V11/1U/2/4 output to reach one of the two rails. In this case, the zero-drift op amps is V –20mV (minimum) and DD time to a valid output is delayed by an output overdrive V +20mV (maximum) when R =10kΩ is SS L time (like t ), in addition to the start-up time (like connected to V /2 and V =5.5V. Refer to ODR DD DD t ). Figure2-19 and Figure2-20 for more information. STR It can be simple to avoid this extra start-up time. This op amp is designed to drive light loads; use Reducing the gain is one method. Adding a capacitor another amplifier to buffer the output from heavy loads. across the feedback resistor (R ) is another method. F  2012-2014 Microchip Technology Inc. DS20005124B-page 21

MCP6V11/1U/2/4 4.3.4 SOURCE RESISTANCES G is the circuit’s noise gain. For non-inverting gains, N G and the Signal Gain are equal. For inverting gains, The input bias currents have two significant N G is 1+|Signal Gain| (e.g., -1V/V gives G =+2 V/V). components; switching glitches that dominate at room N N temperature and below, and input ESD diode leakage currents that dominate at +85°C and above. 1.E1+0005k RL||(RF+ RG) (cid:149) 100 k(cid:159) Make the resistances seen by the inputs small and )(cid:159) equal. This minimizes the output offset caused by the ( O input bias currents. R1IS.E+1004k d The inputs should see a resistance on the order of 10Ω de n to 1kΩ at high frequencies (i.e., above 1MHz). This me helps minimize the impact of switching glitches, which mm11.EE++001133kk o c are very fast, on overall performance. In some cases, it e R may be necessary to add resistors in series with the inputs to achieve this improvement in performance. 1.E+10020 GN= 1 GN= 10 GN= 100 Small input resistances may be needed for high gains. 1.1E0-p11 11.E0-01p0 1.E1-n09 1.1E0-n08 11.E0-00n7 1.E1-µ06 Capacitive Load (F) Without them, parasitic capacitances might cause FIGURE 4-8: Recommended R Values positive feedback and instability. ISO for Capacitive Loads. 4.3.5 SOURCE CAPACITANCE After selecting R for your circuit, double check the ISO The capacitances seen by the two inputs should be resulting frequency response peaking and step small. Large input capacitances and source resis- response overshoot. Modify RISO's value until the tances, together with high gain, can lead to positive response is reasonable. Bench evaluation is helpful. feedback and instability. 4.3.7 STABILIZING OUTPUT LOADS 4.3.6 CAPACITIVE LOADS This family of zero-drift op amps has an output Driving large capacitive loads can cause stability impedance (Figure2-31 and Figure2-32) that has a problems for voltage feedback op amps. As the load double zero when the gain is low. This can cause a capacitance increases, the feedback loop’s phase large phase shift in feedback networks that have low- margin decreases and the closed-loop bandwidth is impedance near the part’s bandwidth. This large phase reduced. This produces gain peaking in the frequency shift can cause stability problems. response, with overshoot and ringing in the step Figure4-9 shows that the load on the output is response. These zero-drift op amps have a different (R +R )||(R +R ), where R is before the load L ISO F G ISO output impedance than most op amps, due to their (like Figure4-7). This load needs to be large enough to unique topology. maintain stability; it should be at least 10kΩ. When driving a capacitive load with these op amps, a series resistor at the output (R in Figure4-7) ISO R R G F improves the feedback loop’s phase margin (stability) V by making the output load resistive at higher OUT frequencies. The bandwidth will be generally lower R C L L than the bandwidth with no capacitive load. U 1 R MCP6V1X ISO V OUT FIGURE 4-9: Output Load. C L U 1 MCP6V1X FIGURE 4-7: Output Resistor, R , ISO Stabilizes Capacitive Loads. Figure4-8 gives recommended R values for ISO different capacitive loads and gains. The x-axis is the load capacitance (C ). The y-axis is the resistance L (R ). ISO DS20005124B-page 22  2012-2014 Microchip Technology Inc.

MCP6V11/1U/2/4 4.3.8 GAIN PEAKING 4.3.9 REDUCING UNDESIRED NOISE AND SIGNALS Figure4-10 shows an op amp circuit that represents non-inverting amplifiers (VM is a DC voltage and VP is Reduce undesired noise and signals with: the input) or inverting amplifiers (V is a DC voltage P • Low bandwidth signal filters: and V is the input). The capacitances C and C M N G - Minimizes random analog noise represent the total capacitance at the input pins; they include the op amp’s Common mode input capacitance - Reduces interfering signals (C ), board parasitic capacitance and any capacitor • Good PCB layout techniques: CM placed in parallel. The capacitance CFP represents the - Minimizes crosstalk parasitic capacitance coupling the output and non- - Minimizes parasitic capacitances and inverting input pins. inductances that interact with fast switching edges • Good power supply design: - Isolation from other parts C N RN CFP - Filtering of interference on supply line(s) V P U 4.3.10 SUPPLY BYPASSING AND 1 FILTERING MCP6V1X With this family of operational amplifiers, the power V V M OUT supply pin (V for single supply) should have a local R R DD G C F bypass capacitor (i.e., 0.01µF to 0.1µF) within 2mm G of the pin for good high-frequency performance. These parts also need a bulk capacitor (i.e., 1µF or FIGURE 4-10: Amplifier with Parasitic larger) within 100mm to provide large, slow currents. Capacitance. This bulk capacitor can be shared with other low noise, analog parts. C acts in parallel with R (except for a gain of +1V/V), G G In some cases, high-frequency power supply noise which causes an increase in gain at high frequencies. (e.g., switched mode power supplies) may cause C also reduces the phase margin of the feedback G undue intermodulation distortion, with a DC offset shift; loop, which becomes less stable. This effect can be this noise needs to be filtered. Adding a resistor into the reduced by either reducing C or R ||R . G F G supply connection can be helpful. C and R form a low-pass filter that affects the signal N N at VP. This filter has a single real pole at 1/(2πRNCN). 4.3.11 PCB DESIGN FOR DC PRECISION The largest value of RF that should be used depends In order to achieve DC precision on the order of ±1µV, on noise gain (see GN in Section4.3.6, Capacitive many physical errors need to be minimized. The design Loads), CG and the open-loop gain’s phase shift. An of the Printed Circuit Board (PCB), the wiring, and the approximate limit for RF is: thermal environment have a strong impact on the precision achieved. A poor PCB design can easily be EQUATION 4-2: more than 100times worse than the MCP6V11/1U/2/4 op amps’ minimum and maximum specifications. 12 pF 2 R 40 k--------------G F CG N 4.3.11.1 PCB Layout Any time two dissimilar metals are joined together, a Some applications may modify these values to reduce temperature dependent voltage appears across the either output loading or gain peaking (step response junction (the Seebeck or thermojunction effect). This overshoot). effect is used in thermocouples to measure At high gains, R needs to be small, in order to prevent temperature. The following are examples of N positive feedback and oscillations. Large C values thermojunctions on a PCB: N can also help. • Components (resistors, op amps, …) soldered to a copper pad • Wires mechanically attached to the PCB • Jumpers • Solder joints • PCB vias  2012-2014 Microchip Technology Inc. DS20005124B-page 23

MCP6V11/1U/2/4 Typical thermojunctions have temperature to voltage 4.4 Typical Applications conversion coefficients of 1 to 100µV/°C (sometimes higher). 4.4.1 WHEATSTONE BRIDGE Microchip’s AN1258 (“Op Amp Precision Design: PCB Many sensors are configured as Wheatstone bridges. Layout Techniques”) contains in-depth information on Strain gauges and pressure sensors are two common PCB layout techniques that minimize thermojunction examples. These signals can be small and the effects. It also discusses other effects, such as Common mode noise large. Amplifier designs with high crosstalk, impedances, mechanical stresses and differential gain are desirable. humidity. Figure4-11 shows how to interface to a Wheatstone bridge with a minimum of components. Because the 4.3.11.2 Crosstalk circuit is not symmetric, the ADC input is single ended, DC crosstalk causes offsets that appear as a larger and there is a minimum of filtering; the CMRR is good input offset voltage. Common causes include: enough for moderate Common mode noise. • Common mode noise (remote sensors) • Ground loops (current return paths) V 0.01C 1kΩ V DD DD • Power supply coupling R R 100R Interference from the mains (usually 50Hz or 60Hz), 0.2R ADC and other AC sources, can also affect the DC performance. Nonlinear distortion can convert these signals to multiple tones, including a DC shift in voltage. R R 0.2R U1 When the signal is sampled by an ADC, these AC MCP6V11 signals can also be aliased to DC, causing an apparent FIGURE 4-11: Simple Design. shift in offset. To reduce interference: 4.4.2 RTD SENSOR - Keep traces and wires as short as possible The ratiometric circuit in Figure4-12 conditions a two- - Use shielding wire RTD, for applications with a limited temperature range. U acts a difference amplifier, with a low - Use ground plane (at least a star ground) 1 frequency pole. The sensor’s wiring resistance (R ) is - Place the input signal source near to the DUT W corrected in firmware. Failure (open) of the RTD is - Use good PCB layout techniques detected by an out-of-range voltage. - Use a separate power supply filter (bypass capacitors) for these zero-drift op amps V DD 4.3.11.3 Miscellaneous Effects Keep the resistances seen by the input pins as small RT RN and as near to equal as possible, to minimize bias- 34.8kΩ 10.0kΩ 10nF current-related offsets. RW RF Make the (trace) capacitances seen by the input pins 2.00MΩ small and equal. This is helpful in minimizing switching U glitch-induced offset voltages. R 1 RTD 100Ω MCP6V11 Bending a coax cable with a radius that is too small R R 1.00kΩ causes a small voltage drop to appear on the center R G F W 10.0kΩ 2.00MΩ conductor (the triboelectric effect). Make sure the 100nF bending radius is large enough to keep the conductors and insulation in full contact. RB 1.0µF 10nF VDD 4.99kΩ Mechanical stresses can make some capacitor types (such as some ceramics) output small voltages. Use ADC more appropriate capacitor types in the signal path and minimize mechanical stresses and vibration. FIGURE 4-12: RTD Sensor. Humidity can cause electrochemical potential voltages to appear in a circuit. Proper PCB cleaning helps, as does the use of encapsulants. DS20005124B-page 24  2012-2014 Microchip Technology Inc.

MCP6V11/1U/2/4 4.4.3 OFFSET VOLTAGE CORRECTION Figure4-13 shows MCP6V11 (U ) correcting the input 2 offset voltage of another op amp (U ). R and C 1 2 2 integrate the offset error seen at U ’s input; the 1 integration needs to be slow enough to be stable (with the feedback provided by R and R ). R and R 1 3 4 5 attenuate the integrator’s output; this shifts the integrator pole down in frequency. R R 1 3 V V IN OUT R 2 C R 2 4 U 1 R R5 MCP6XXX 2 V /2 U DD 2 V /2 DD MCP6V11 FIGURE 4-13: Offset Correction. 4.4.4 PRECISION COMPARATOR Use high gain before a comparator to improve the latter’s performance. Do not use MCP6V11/1U/2/4 as a comparator by itself; the V correction circuitry does OS not operate properly without a feedback loop. U 1 VIN MCP6V11 R 1 R2 R3 R4 R 5 V OUT V /2 DD U 2 MCP6541 FIGURE 4-14: Precision Comparator.  2012-2014 Microchip Technology Inc. DS20005124B-page 25

MCP6V11/1U/2/4 NOTES: DS20005124B-page 26  2012-2014 Microchip Technology Inc.

MCP6V11/1U/2/4 5.0 DESIGN AIDS 5.4 Analog Demonstration and Evaluation Boards Microchip provides the basic design aids needed for the MCP6V11/1U/2/4 family of op amps. Microchip offers a broad spectrum of Analog Demonstration and Evaluation Boards that are 5.1 SPICE Macro Model designed to help customers achieve faster time to market. For a complete listing of these boards and their The latest SPICE macro model for the corresponding user’s guides and technical information, MCP6V11/1U/2/4 op amps is available on the visit the Microchip web site at www.microchip.com/ana- Microchip web site at www.microchip.com. This model log tools. is intended to be an initial design tool that works well in Some boards that are especially useful are: the op amp’s linear region of operation over the tem- perature range. See the model file for information on its • MCP6V01 Thermocouple Auto-Zeroed Reference capabilities. Design (P/N MCP6V01RD-TCPL) Bench testing is a very important part of any design and • MCP6XXX Amplifier Evaluation Board 1 (P/N cannot be replaced with simulations. Also, simulation DS51667) results using this macro model need to be validated by • MCP6XXX Amplifier Evaluation Board 2 (P/N comparing them to the data sheet specifications and DS51668) characteristic curves. • MCP6XXX Amplifier Evaluation Board 3 (P/N DS51673) 5.2 FilterLab® Software • MCP6XXX Amplifier Evaluation Board 4 (P/N Microchip’s FilterLab® software is an innovative DS51681) • Active Filter Demo Board Kit (P/N DS51614) software tool that simplifies analog active filter (using op amps) design. Available at no cost from the • 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board Microchip web site at www.microchip.com/filterlab, the (P/N SOIC8EV) FilterLab design tool provides full schematic diagrams • 14-Pin SOIC/TSSOP/DIP Evaluation Board (P/N of the filter circuit with component values. It also SOIC14EV) outputs the filter circuit in SPICE format, which can be used with the macro model to simulate actual filter 5.5 Application Notes performance. The following Microchip Application Notes are 5.3 Microchip Advanced Part Selector available on the Microchip web site at www.microchip. com/appnotes and are recommended as supplemental (MAPS) reference resources. MAPS is a software tool that helps efficiently identify ADN003: “Select the Right Operational Amplifier for Microchip devices that fit a particular design require- your Filtering Circuits”, DS21821 ment. Available at no cost from the Microchip web site AN722: “Operational Amplifier Topologies and DC at www.microchip.com/maps, MAPS is an overall Specifications”, DS00722 selection tool for Microchip’s product portfolio that includes Analog, Memory, MCUs and DSCs. Using this AN723: “Operational Amplifier AC Specifications and tool, a customer can define a filter to sort features for a Applications”, DS00723 parametric search of devices and export side-by-side AN884: “Driving Capacitive Loads With Op Amps”, technical comparison reports. Helpful links are also DS00884 provided for Data Sheets, Purchase and Sampling of Microchip parts. AN990: “Analog Sensor Conditioning Circuits – An Overview”, DS00990 AN1177: “Op Amp Precision Design: DC Errors”, DS01177 AN1228: “Op Amp Precision Design: Random Noise”, DS01228 AN1258: “Op Amp Precision Design: PCB Layout Techniques”, DS01258 These Application Notes and others are listed in the design guide: “Signal Chain Design Guide”, DS21825  2012-2014 Microchip Technology Inc. DS20005124B-page 27

MCP6V11/1U/2/4 NOTES: DS20005124B-page 28  2012-2014 Microchip Technology Inc.

MCP6V11/1U/2/4 6.0 PACKAGING INFORMATION 6.1 Package Marking Information 5-Lead SC70 (MCP6V11U) Example: Device Code DJ25 MCP6V11UT-E/LT DJNN Note: Applies to 5-Lead SC-70. 5-Lead SOT-23 (MCP6V11/1U) Example: Device Code MCP6V11T-E/OT 2CNN 2C25 MCP6V11UT-E/OT 2DNN Note: Applies to 5-Lead SOT-23. 8-Lead MSOP (3x3 mm)(MCP6V12) Example 6V12E 410256 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC® designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2012-2014 Microchip Technology Inc. DS20005124B-page 29

MCP6V11/1U/2/4 8-Lead TDFN (2x3x0.75 mm)(MCP6V12) Example Device Code MCP6V12-E/MNY ABV ABV MCP6V12T-E/MNY ABV 410 25 Note: Applies to 8-Lead 2x3 TDFN. 14-Lead TSSOP (4.4 mm)(MCP6V14) Example XXXXXXXX 6V14E/ST YYWW 1410 256 NNN DS20005124B-page 30  2012-2014 Microchip Technology Inc.

MCP6V11/1U/2/4 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:10)(cid:8)(cid:17)(cid:18)(cid:12)(cid:10)(cid:13)(cid:19)(cid:5)(cid:8)(cid:20)(cid:21)(cid:6)(cid:19)(cid:11)(cid:13)(cid:11)(cid:12)(cid:22)(cid:21)(cid:8)(cid:23)(cid:4)(cid:20)(cid:24)(cid:8)(cid:25)(cid:15)(cid:26)(cid:27)(cid:28)(cid:29) (cid:30)(cid:22)(cid:12)(cid:5)(cid:31) .(cid:10)(cid:9)(cid:2)#(cid:11)(cid:14)(cid:2)(cid:31)(cid:10) #(cid:2)(cid:8)$(cid:9)(cid:9)(cid:14)(cid:15)#(cid:2)(cid:12)(cid:28)(cid:8)/(cid:28)(cid:17)(cid:14)(cid:2)!(cid:9)(cid:28)-(cid:7)(cid:15)(cid:17) 0(cid:2)(cid:12)(cid:16)(cid:14)(cid:28) (cid:14)(cid:2) (cid:14)(cid:14)(cid:2)#(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)1(cid:28)(cid:8)/(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)#(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)#(cid:14)!(cid:2)(cid:28)#(cid:2) (cid:11)##(cid:12)+22---(cid:20)(cid:31)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)(cid:31)2(cid:12)(cid:28)(cid:8)/(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D b 3 2 1 E1 E 4 5 e e A A2 c A1 L 3(cid:15)(cid:7)# (cid:6)(cid:19)44(cid:19)(cid:6)"(cid:13)"(cid:26)(cid:22) (cid:21)(cid:7)(cid:31)(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:2)4(cid:7)(cid:31)(cid:7)# (cid:6)(cid:19)5 56(cid:6) (cid:6)(cid:25)7 5$(cid:31)8(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)1(cid:7)(cid:15) 5 ( 1(cid:7)#(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)9((cid:2))(cid:22)* 6,(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2):(cid:14)(cid:7)(cid:17)(cid:11)# (cid:25) (cid:4)(cid:20);(cid:4) < (cid:30)(cid:20)(cid:30)(cid:4) (cid:6)(cid:10)(cid:16)!(cid:14)!(cid:2)1(cid:28)(cid:8)/(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)/(cid:15)(cid:14) (cid:25)(cid:3) (cid:4)(cid:20);(cid:4) < (cid:30)(cid:20)(cid:4)(cid:4) (cid:22)#(cid:28)(cid:15)!(cid:10)%% (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:4) < (cid:4)(cid:20)(cid:30)(cid:4) 6,(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)=(cid:7)!#(cid:11) " (cid:30)(cid:20);(cid:4) (cid:3)(cid:20)(cid:30)(cid:4) (cid:3)(cid:20)(cid:23)(cid:4) (cid:6)(cid:10)(cid:16)!(cid:14)!(cid:2)1(cid:28)(cid:8)/(cid:28)(cid:17)(cid:14)(cid:2)=(cid:7)!#(cid:11) "(cid:30) (cid:30)(cid:20)(cid:30)( (cid:30)(cid:20)(cid:3)( (cid:30)(cid:20)(cid:29)( 6,(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)4(cid:14)(cid:15)(cid:17)#(cid:11) (cid:21) (cid:30)(cid:20);(cid:4) (cid:3)(cid:20)(cid:4)(cid:4) (cid:3)(cid:20)(cid:3)( .(cid:10)(cid:10)#(cid:2)4(cid:14)(cid:15)(cid:17)#(cid:11) 4 (cid:4)(cid:20)(cid:30)(cid:4) (cid:4)(cid:20)(cid:3)(cid:4) (cid:4)(cid:20)(cid:23)9 4(cid:14)(cid:28)!(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)/(cid:15)(cid:14) (cid:8) (cid:4)(cid:20)(cid:4); < (cid:4)(cid:20)(cid:3)9 4(cid:14)(cid:28)!(cid:2)=(cid:7)!#(cid:11) 8 (cid:4)(cid:20)(cid:30)( < (cid:4)(cid:20)(cid:23)(cid:4) (cid:30)(cid:22)(cid:12)(cid:5)(cid:11)(cid:31) (cid:30)(cid:20) (cid:21)(cid:7)(cid:31)(cid:14)(cid:15) (cid:7)(cid:10)(cid:15) (cid:2)(cid:21)(cid:2)(cid:28)(cid:15)!(cid:2)"(cid:30)(cid:2)!(cid:10)(cid:2)(cid:15)(cid:10)#(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)$!(cid:14)(cid:2)(cid:31)(cid:10)(cid:16)!(cid:2)%(cid:16)(cid:28) (cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)#(cid:9)$ (cid:7)(cid:10)(cid:15) (cid:20)(cid:2)(cid:6)(cid:10)(cid:16)!(cid:2)%(cid:16)(cid:28) (cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)#(cid:9)$ (cid:7)(cid:10)(cid:15) (cid:2) (cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)#(cid:2)(cid:14)&(cid:8)(cid:14)(cid:14)!(cid:2)(cid:4)(cid:20)(cid:30)(cid:3)(cid:5)(cid:2)(cid:31)(cid:31)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2) (cid:7)!(cid:14)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7)(cid:31)(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)!(cid:2)#(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6)"(cid:2)’(cid:30)(cid:23)(cid:20)((cid:6)(cid:20) )(cid:22)*+ )(cid:28) (cid:7)(cid:8)(cid:2)(cid:21)(cid:7)(cid:31)(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)#(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)&(cid:28)(cid:8)#(cid:2),(cid:28)(cid:16)$(cid:14)(cid:2) (cid:11)(cid:10)-(cid:15)(cid:2)-(cid:7)#(cid:11)(cid:10)$#(cid:2)#(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14) (cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)-(cid:7)(cid:15)(cid:17)*(cid:4)(cid:23)(cid:27)(cid:4)9(cid:30))  2012-2014 Microchip Technology Inc. DS20005124B-page 31

MCP6V11/1U/2/4 (cid:30)(cid:22)(cid:12)(cid:5)(cid:31) .(cid:10)(cid:9)(cid:2)#(cid:11)(cid:14)(cid:2)(cid:31)(cid:10) #(cid:2)(cid:8)$(cid:9)(cid:9)(cid:14)(cid:15)#(cid:2)(cid:12)(cid:28)(cid:8)/(cid:28)(cid:17)(cid:14)(cid:2)!(cid:9)(cid:28)-(cid:7)(cid:15)(cid:17) 0(cid:2)(cid:12)(cid:16)(cid:14)(cid:28) (cid:14)(cid:2) (cid:14)(cid:14)(cid:2)#(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)1(cid:28)(cid:8)/(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)#(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)#(cid:14)!(cid:2)(cid:28)#(cid:2) (cid:11)##(cid:12)+22---(cid:20)(cid:31)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)(cid:31)2(cid:12)(cid:28)(cid:8)/(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) DS20005124B-page 32  2012-2014 Microchip Technology Inc.

MCP6V11/1U/2/4 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:10)(cid:8)(cid:17)(cid:18)(cid:12)(cid:10)(cid:13)(cid:19)(cid:5)(cid:8)(cid:20)(cid:21)(cid:6)(cid:19)(cid:11)(cid:13)(cid:11)(cid:12)(cid:22)(cid:21)(cid:8)(cid:23)(cid:17)(cid:20)(cid:24)(cid:8)(cid:25)(cid:15)(cid:17)(cid:20)(cid:3) !(cid:29) (cid:30)(cid:22)(cid:12)(cid:5)(cid:31) .(cid:10)(cid:9)(cid:2)#(cid:11)(cid:14)(cid:2)(cid:31)(cid:10) #(cid:2)(cid:8)$(cid:9)(cid:9)(cid:14)(cid:15)#(cid:2)(cid:12)(cid:28)(cid:8)/(cid:28)(cid:17)(cid:14)(cid:2)!(cid:9)(cid:28)-(cid:7)(cid:15)(cid:17) 0(cid:2)(cid:12)(cid:16)(cid:14)(cid:28) (cid:14)(cid:2) (cid:14)(cid:14)(cid:2)#(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)1(cid:28)(cid:8)/(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)#(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)#(cid:14)!(cid:2)(cid:28)#(cid:2) (cid:11)##(cid:12)+22---(cid:20)(cid:31)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)(cid:31)2(cid:12)(cid:28)(cid:8)/(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) b N E E1 1 2 3 e e1 D A A2 c φ A1 L L1 3(cid:15)(cid:7)# (cid:6)(cid:19)44(cid:19)(cid:6)"(cid:13)"(cid:26)(cid:22) (cid:21)(cid:7)(cid:31)(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:2)4(cid:7)(cid:31)(cid:7)# (cid:6)(cid:19)5 56(cid:6) (cid:6)(cid:25)7 5$(cid:31)8(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)1(cid:7)(cid:15) 5 ( 4(cid:14)(cid:28)!(cid:2)1(cid:7)#(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)(cid:24)((cid:2))(cid:22)* 6$# (cid:7)!(cid:14)(cid:2)4(cid:14)(cid:28)!(cid:2)1(cid:7)#(cid:8)(cid:11) (cid:14)(cid:30) (cid:30)(cid:20)(cid:24)(cid:4)(cid:2))(cid:22)* 6,(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2):(cid:14)(cid:7)(cid:17)(cid:11)# (cid:25) (cid:4)(cid:20)(cid:24)(cid:4) < (cid:30)(cid:20)(cid:23)( (cid:6)(cid:10)(cid:16)!(cid:14)!(cid:2)1(cid:28)(cid:8)/(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)/(cid:15)(cid:14) (cid:25)(cid:3) (cid:4)(cid:20);(cid:24) < (cid:30)(cid:20)(cid:29)(cid:4) (cid:22)#(cid:28)(cid:15)!(cid:10)%% (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:4) < (cid:4)(cid:20)(cid:30)( 6,(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)=(cid:7)!#(cid:11) " (cid:3)(cid:20)(cid:3)(cid:4) < (cid:29)(cid:20)(cid:3)(cid:4) (cid:6)(cid:10)(cid:16)!(cid:14)!(cid:2)1(cid:28)(cid:8)/(cid:28)(cid:17)(cid:14)(cid:2)=(cid:7)!#(cid:11) "(cid:30) (cid:30)(cid:20)(cid:29)(cid:4) < (cid:30)(cid:20);(cid:4) 6,(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)4(cid:14)(cid:15)(cid:17)#(cid:11) (cid:21) (cid:3)(cid:20)(cid:5)(cid:4) < (cid:29)(cid:20)(cid:30)(cid:4) .(cid:10)(cid:10)#(cid:2)4(cid:14)(cid:15)(cid:17)#(cid:11) 4 (cid:4)(cid:20)(cid:30)(cid:4) < (cid:4)(cid:20)9(cid:4) .(cid:10)(cid:10)#(cid:12)(cid:9)(cid:7)(cid:15)# 4(cid:30) (cid:4)(cid:20)(cid:29)( < (cid:4)(cid:20);(cid:4) .(cid:10)(cid:10)#(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)> < (cid:29)(cid:4)> 4(cid:14)(cid:28)!(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)/(cid:15)(cid:14) (cid:8) (cid:4)(cid:20)(cid:4); < (cid:4)(cid:20)(cid:3)9 4(cid:14)(cid:28)!(cid:2)=(cid:7)!#(cid:11) 8 (cid:4)(cid:20)(cid:3)(cid:4) < (cid:4)(cid:20)((cid:30) (cid:30)(cid:22)(cid:12)(cid:5)(cid:11)(cid:31) (cid:30)(cid:20) (cid:21)(cid:7)(cid:31)(cid:14)(cid:15) (cid:7)(cid:10)(cid:15) (cid:2)(cid:21)(cid:2)(cid:28)(cid:15)!(cid:2)"(cid:30)(cid:2)!(cid:10)(cid:2)(cid:15)(cid:10)#(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)$!(cid:14)(cid:2)(cid:31)(cid:10)(cid:16)!(cid:2)%(cid:16)(cid:28) (cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)#(cid:9)$ (cid:7)(cid:10)(cid:15) (cid:20)(cid:2)(cid:6)(cid:10)(cid:16)!(cid:2)%(cid:16)(cid:28) (cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)#(cid:9)$ (cid:7)(cid:10)(cid:15) (cid:2) (cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)#(cid:2)(cid:14)&(cid:8)(cid:14)(cid:14)!(cid:2)(cid:4)(cid:20)(cid:30)(cid:3)(cid:5)(cid:2)(cid:31)(cid:31)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2) (cid:7)!(cid:14)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7)(cid:31)(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)!(cid:2)#(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6)"(cid:2)’(cid:30)(cid:23)(cid:20)((cid:6)(cid:20) )(cid:22)*+ )(cid:28) (cid:7)(cid:8)(cid:2)(cid:21)(cid:7)(cid:31)(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)#(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)&(cid:28)(cid:8)#(cid:2),(cid:28)(cid:16)$(cid:14)(cid:2) (cid:11)(cid:10)-(cid:15)(cid:2)-(cid:7)#(cid:11)(cid:10)$#(cid:2)#(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14) (cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)-(cid:7)(cid:15)(cid:17)*(cid:4)(cid:23)(cid:27)(cid:4)(cid:24)(cid:30))  2012-2014 Microchip Technology Inc. DS20005124B-page 33

MCP6V11/1U/2/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20005124B-page 34  2012-2014 Microchip Technology Inc.

MCP6V11/1U/2/4 Note: For the mostcurrent package drawings,please seetheMicrochip Packaging Specification located at http://www.microchip.com/packaging  2012-2014 Microchip Technology Inc. DS20005124B-page 35

MCP6V11/1U/2/4 Note: For the mostcurrent package drawings,please seetheMicrochip Packaging Specification located at http://www.microchip.com/packaging DS20005124B-page 36  2012-2014 Microchip Technology Inc.

MCP6V11/1U/2/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2012-2014 Microchip Technology Inc. DS20005124B-page 37

MCP6V11/1U/2/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20005124B-page 38  2012-2014 Microchip Technology Inc.

MCP6V11/1U/2/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2012-2014 Microchip Technology Inc. DS20005124B-page 39

MCP6V11/1U/2/4 "(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)#(cid:18)(cid:6)(cid:10)(cid:8)$(cid:10)(cid:6)(cid:12)%(cid:8)(cid:30)(cid:22)(cid:8)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:14)&(cid:6)’(cid:5)(cid:8)(cid:23)((cid:30)(cid:24)(cid:8))(cid:8) *!*(cid:28)+(cid:27)(cid:2)(cid:8)(cid:16)(cid:16)(cid:8),(cid:22)(cid:7)-(cid:8)(cid:25)(cid:20)#$(cid:30)(cid:29) (cid:30)(cid:22)(cid:12)(cid:5)(cid:31) .(cid:10)(cid:9)(cid:2)#(cid:11)(cid:14)(cid:2)(cid:31)(cid:10) #(cid:2)(cid:8)$(cid:9)(cid:9)(cid:14)(cid:15)#(cid:2)(cid:12)(cid:28)(cid:8)/(cid:28)(cid:17)(cid:14)(cid:2)!(cid:9)(cid:28)-(cid:7)(cid:15)(cid:17) 0(cid:2)(cid:12)(cid:16)(cid:14)(cid:28) (cid:14)(cid:2) (cid:14)(cid:14)(cid:2)#(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)1(cid:28)(cid:8)/(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)#(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)#(cid:14)!(cid:2)(cid:28)#(cid:2) (cid:11)##(cid:12)+22---(cid:20)(cid:31)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)(cid:31)2(cid:12)(cid:28)(cid:8)/(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) DS20005124B-page 40  2012-2014 Microchip Technology Inc.

MCP6V11/1U/2/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2012-2014 Microchip Technology Inc. DS20005124B-page 41

MCP6V11/1U/2/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20005124B-page 42  2012-2014 Microchip Technology Inc.

MCP6V11/1U/2/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2012-2014 Microchip Technology Inc. DS20005124B-page 43

MCP6V11/1U/2/4 NOTES: DS20005124B-page 44  2012-2014 Microchip Technology Inc.

MCP6V11/1U/2/4 APPENDIX A: REVISION HISTORY Revision B (March 2014) The following is the list of modifications: 1. Added new devices to the family: MCP6V12 and MCP6V14, and the related information throughout the document. 2. Updated Table1-3 with new packages’ thermal resistances. 3. Updated Figures1-6,2-19 and2-22 in Section2.0 “Typical Performance Curves”. Added new Figure2-33. 4. Updated Table3-1 in Section3.0 “Pin Descriptions” for the new devices. 5. Updated markings and specification drawings in Section6.0 “Packaging Information”. 6. Updated Product Identification System. Revision A (March 2012) • Original Release of this Document.  2012-2014 Microchip Technology Inc. DS20005124B-page 45

MCP6V11/1U/2/4 NOTES: DS20005124B-page 46  2012-2014 Microchip Technology Inc.

MCP6V11/1U/2/4 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. [X](1) –X /XX Examples: a) MCP6V11T-E/OT: Tape and Reel, Device Tape and ReelTemperature Package Extended temperature, Range 5LD SOT-23 package Device: MCP6V11T: Single Op Amp (Tape and Reel) (SOT-23) a) MCP6V11UT-E/LT: Tape and Reel MCP6V11UT: Single Op Amp (Tape and Reel) Extended temperature, (SC-70, SOT-23) 5LD SC70 package MCP6V12: Dual Op Amp (MSOP, 2x3TDFN) b) MCP6V11UT-E/OT: Tape and Reel, MCP6V12T: Dual Op Amp (Tape and Reel) (MSOP, Extended temperature, 2x3TDFN) 5LD SOT-23 package MCP6V14: Quad Op Amp (TSSOP) MCP6V14T: Quad Op Amp (Tape and Reel) (TSSOP) a) MCP6V12-E/MS: Extended temperature, 8LD MSOP package Temperature Range: E = -40°C to +125°C (Extended) b) MCP6V12T-E/MS: Tape and Reel, Extended temperature, 8LD MSOP package Package: LT = Plastic Small Outline Transistor, 5-lead c) MCP6V12T-E/MNY: Tape and Reel, OT = Plastic Small Outline Transistor, 5-lead Extended temperature, MNY* = Plastic Dual Flat, No-Lead - 2×3×0.75 mm 8LD 2x3 TDFN package Body, 8-lead MS = Plastic Micro Small Outline, 8-lead a) MCP6V14-E/ST: Extended temperature, ST = Plastic Thin Shrink Small Outline - 4.4mm 14LD TSSOP package Body, 14-lead b) MCP6V14T-E/ST: Tape and Reel Extended temperature, * Y = Nickel palladium gold manufacturing designator. Only 14LD TSSOP package available on the TDFN package. Note1: Tape and Reel identifier only appears in the catalog part number description. This identi- fier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option.  2012-2014 Microchip Technology Inc. DS20005124B-page 47

MCP6V11/1U/2/4 NOTES: DS20005124B-page 48  2012-2014 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, ensure that your application meets with your specifications. PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash MICROCHIP MAKES NO REPRESENTATIONS OR and UNI/O are registered trademarks of Microchip Technology WARRANTIES OF ANY KIND WHETHER EXPRESS OR Incorporated in the U.S.A. and other countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MTP, SEEVAL and The Embedded Control Solutions QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Silicon Storage Technology is a registered trademark of devices in life support and/or safety applications is entirely at Microchip Technology Inc. in other countries. the buyer’s risk, and the buyer agrees to defend, indemnify and Analog-for-the-Digital Age, Application Maestro, BodyCom, hold harmless Microchip from any and all damages, claims, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, suits, or expenses resulting from such use. No licenses are dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, conveyed, implicitly or otherwise, under any Microchip ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial intellectual property rights. Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2012-2014, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-63276-007-4 QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures == ISO/TS 16949 == are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2012-2014 Microchip Technology Inc. DS20005124B-page 49

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