MCP6H01/2 1.2 MHz, 16V Op Amps Features Description • Input Offset Voltage: ±0.7mV (typical) Microchip’s MCP6H01/2 family of operational amplifi- • Quiescent Current: 135µA (typical) ers (op amps) has a wide supply voltage range of 3.5V to 16V and rail-to-rail output operation. This family is • Common Mode Rejection Ratio: 100dB (typical) unity gain stable and has a gain bandwidth product of • Power Supply Rejection Ratio: 102dB (typical) 1.2MHz (typical). These devices operate with a • Rail-to-Rail Output single-supply voltage as high as 16V, while only • Supply Voltage Range: drawing 135µA/amplifier (typical) of quiescent current. - Single-Supply Operation: 3.5V to 16V The MCP6H01/2 family is offered in single - Dual-Supply Operation: ±1.75V to ±8V (MCP6H01) and dual (MCP6H02) configurations. All • Gain Bandwidth Product: 1.2MHz (typical) devices are fully specified in extended temperature • Slew Rate: 0.8V/µs (typical) range from -40°C to +125°C. • Unity Gain Stable Package Types • Extended Temperature Range: -40°C to +125°C • No Phase Reversal MCP6H01 MCP6H02 SOIC SOIC Applications NC 1 8 NC VOUTA 1 8 VDD • Automotive Power Electronics VIN– 2 7 VDD VINA– 2 7 VOUTB • Industrial Control Equipment VIN+ 3 6 VOUT VINA+ 3 6 VINB– • Battery Powered Systems VSS 4 5 NC VSS 4 5 VINB+ • Medical Diagnostic Instruments Design Aids MCP6H01 MCP6H02 2x3 TDFN 2x3 TDFN • SPICE Macro Models • FilterLab® Software NC 1 8 NC VOUTA 1 8 VDD • Mindi™ Circuit Designer and Simulator VIN– 2 EP 7 VDD VINA– 2 EP 7 VOUTB • MAPS (Microchip Advanced Part Selector) VIN+ 3 9 6 VOUT VINA+ 3 9 6 VINB– V 4 5 NC V 4 5 V + • Analog Demonstration and Evaluation Boards SS SS INB • Application Notes * Includes Exposed Thermal Pad (EP); see Table3-1. Typical Application R R 1 2 V V 1 REF V DD V OUT MCP6H01 V 2 R1 R2 Difference Amplifier © 2010 Microchip Technology Inc. DS22243B-page 1

MCP6H01/2 NOTES: DS22243B-page 2 © 2010 Microchip Technology Inc.

MCP6H01/2 1.0 ELECTRICAL CHARACTERISTICS 1.1 Absolute Maximum Ratings † V – V ..........................................................................17V † Notice: Stresses above those listed under “Absolute DD SS Current at Input Pins......................................................±2mA Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of Analog Inputs (V +, V -)††.............V –1.0V to V +1.0V IN IN SS DD the device at those or any other conditions above those All Other Inputs and Outputs ............V –0.3V to V +0.3V SS DD indicated in the operational listings of this specification is not Difference Input Voltage|..........................................VDD – VSS implied. Exposure to maximum rating conditions for extended Output Short-Circuit Current...................................continuous periods may affect device reliability. Current at Output and Supply Pins ..............................±65mA †† See 4.1.2 “Input Voltage Limits”. Storage Temperature.....................................-65°C to +150°C Maximum Junction Temperature (T )...........................+150°C J ESD protection on all pins (HBM; MM)...................≥ 2kV; 200V DC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, V =+3.5V to +16V, V =GND, T =+25°C, DD SS A V =V /2 -1.4V, V ≈V /2, V =V /2 and R =10kΩ to V . (Refer to Figure1-1). CM DD OUT DD L DD L L Parameters Sym Min Typ Max Units Conditions Input Offset Input Offset Voltage V -3.5 ±0.7 +3.5 mV OS Input Offset Drift with Temperature ΔV /ΔT — ±2.5 — µV/°C T =-40°C to +125°C OS A A Power Supply Rejection Ratio PSRR 87 102 — dB Input Bias Current and Impedance Input Bias Current I — 10 — pA B I — 600 — pA T =+85°C B A I — 10 25 nA T =+125°C B A Input Offset Current I — ±1 — pA OS Common Mode Input Impedance Z — 1013||6 — Ω||pF CM Differential Input Impedance Z — 1013||6 — Ω||pF DIFF Common Mode Common Mode Input Voltage Range V V −0.3 — V −2.3 V CMR SS DD Common Mode Rejection Ratio CMRR 78 93 — dB V =-0.3V to 1.2V, CM V =3.5V DD 82 98 — dB V =-0.3V to 2.7V, CM V =5V DD 84 100 — dB V =-0.3V to 12.7V, CM V =15V DD Open-Loop Gain DC Open-Loop Gain (Large Signal) A 95 115 — dB 0.2V < V <(V -0.2V) OL OUT DD © 2010 Microchip Technology Inc. DS22243B-page 3

MCP6H01/2 DC ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise indicated, V =+3.5V to +16V, V =GND, T =+25°C, DD SS A V =V /2 -1.4V, V ≈V /2, V =V /2 and R =10kΩ to V . (Refer to Figure1-1). CM DD OUT DD L DD L L Parameters Sym Min Typ Max Units Conditions Output High-Level Output Voltage V 3.490 3.495 — V V =3.5V OH DD 0.5V input overdrive 4.985 4.993 — V V =5V DD 0.5V input overdrive 14.970 14.980 — V V =15V DD 0.5V input overdrive Low-Level Output Voltage V — 0.005 0.010 V V =3.5V OL DD 0.5V input overdrive — 0.007 0.015 V V =5V DD 0.5V input overdrive — 0.020 0.030 V V =15V DD 0.5V input overdrive Output Short-Circuit Current I — ±27 — mA V =3.5V SC DD — ±45 — mA V =5V DD — ±50 — mA V =15V DD Power Supply Supply Voltage V 3.5 — 16 V Single-supply operation DD ±1.75 — ±8 V Dual-supply operation Quiescent Current per Amplifier I — 125 175 µA I =0, V =3.5V Q O DD V =V /4 CM DD — 130 180 µA I =0, V =5V O DD V =V /4 CM DD — 135 185 µA I =0, V =15V O DD V =V /4 CM DD AC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, T =+25°C, V =+3.5V to +16V, V =GND, A DD SS V =V /2 -1.4V, V ≈V /2, V =V /2, R =10kΩ to V and C = 60pF. (Refer to Figure1-1). CM DD OUT DD L DD L L L Parameters Sym Min Typ Max Units Conditions AC Response Gain Bandwidth Product GBWP — 1.2 — MHz Phase Margin PM — 57 — ° G=+1V/V Slew Rate SR — 0.8 — V/µs Noise Input Noise Voltage E — 12 — µVp-p f=0.1Hz to 10Hz ni Input Noise Voltage Density e — 35 — nV/√Hz f=1kHz ni — 30 — nV/√Hz f=10kHz Input Noise Current Density i — 1.9 — fA/√Hz f=1kHz ni DS22243B-page 4 © 2010 Microchip Technology Inc.

MCP6H01/2 TEMPERATURE SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, V =+3.5V to +16V and V =GND. DD SS Parameters Sym Min Typ Max Units Conditions Temperature Ranges Operating Temperature Range T -40 — +125 °C Note1 A Storage Temperature Range T -65 — +150 °C A Thermal Package Resistances Thermal Resistance, 8L-2x3 TDFN θ — 41 — °C/W JA Thermal Resistance, 8L-SOIC θ — 149.5 — °C/W JA Note1: The internal junction temperature (T ) must not exceed the absolute maximum specification of +150°C. J 1.2 Test Circuits C The circuit used for most DC and AC tests is shown in F 6.8pF Figure1-1. This circuit can independently set V and CM V (refer to Equation1-1). Note that V is not the OUT CM circuit’s common mode voltage ((VP+VM)/2), and that RG RF V includes V plus the effects (on the input offset 100kΩ 100kΩ OST OS error, VOST) of temperature, CMRR, PSRR and AOL. VP VDD/2 V DD V EQUATION 1-1: IN+ C C B1 B2 G = R ⁄R DM F G MCP6H0X 100nF 1µF V = (V +V ⁄2)⁄2 CM P DD VOST = VIN––VIN+ VIN– VOUT = (VDD⁄2)+(VP–VM)+VOST⋅(1+GDM) VM VOUT Where: RG RF RL CL 100kΩ 100kΩ 10kΩ 60pF G = Differential Mode Gain (V/V) DM V = Op Amp’s Common Mode (V) CM C Input Voltage F V 6.8pF L V = Op Amp’s Total Input Offset (mV) OST Voltage FIGURE 1-1: AC and DC Test Circuit for Most Specifications. © 2010 Microchip Technology Inc. DS22243B-page 5

MCP6H01/2 NOTES: DS22243B-page 6 © 2010 Microchip Technology Inc.

MCP6H01/2 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, T =+25°C, V =+3.5V to +16V, V =GND, V =V /2 -1.4V, V ≈V /2, A DD SS CM DD OUT DD V =V /2, R =10kΩ to V and C =60pF. L DD L L L 21% 1000 e of Occurences 1112589%%%% 2550 Samples et Voltage (µV) 2468000000000 TTTTAAAA ==== +++-41820255°5°°CCC°C g s -200 nta 6% Off -400 Perce 3% Input --860000 VRDeDp r=e 5sVentative Part 0% -1000 0 5 0 5 0 5 0 5 0 5 0 5 0 3. 2. 2. 1. 1. 0. 0. 0. 1. 1. 2. 2. 3. -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 - - - - - - Input Offset Voltage (mV) Common Mode Input Voltage (V) FIGURE 2-1: Input Offset Voltage. FIGURE 2-4: Input Offset Voltage vs. Common Mode Input Voltage. 35% 1000 ge of Occurences 12235050%%%% 2T5A 5=0 - S 4a0m°Cp lteos +125°C set Voltage (µV) -2246800000000000 TTTTAAAA ==== +++-41820255°5°°CCC°C nta 10% Off -400 Perce 5% Input --860000 VRDeDp r=e 1s5eVntative Part 0% -1000 64208642024680246 1111---- 1111 -0.5 1.5 3.5 5.5 7.5 9.5 11.5 13.5 15.5 ---- Input Offset Voltage Drift (µV/°C) Common Mode Input Voltage (V) FIGURE 2-2: Input Offset Voltage Drift. FIGURE 2-5: Input Offset Voltage vs. Common Mode Input Voltage. 1000 1000 Input Offset Voltage (µV) ----8642246800000000000000000 VRDeDp r=e 3s.e5nVtativeTTTT PAAAA a====r t+++-41820255°5°°CCC°C Input Offset Voltage (µV) ----8642246800000000000000000 Representative PVaDrVtD D=D 3=. 55VV VDD = 15V -1000 -1000 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 0 2 4 6 8 10 12 14 16 Common Mode Input Voltage (V) Output Voltage (V) FIGURE 2-3: Input Offset Voltage vs. FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage. Output Voltage. © 2010 Microchip Technology Inc. DS22243B-page 7

MCP6H01/2 Note: Unless otherwise indicated, T =+25°C, V =+3.5V to +16V, V =GND, V =V /2 -1.4V, V ≈V /2, A DD SS CM DD OUT DD V =V /2, R =10kΩ to V and C =60pF. L DD L L L 1000 120 PSRR+ V) 800 110 Representative Part µ 600 100 ge ( 400 dB) 90 CMRR put Offset Volta ---6422000000000 TTTTAAAA ==== +++-41820255°5°°CCC°C CMRR, PSRR ( 4567800000 PSRR- In -800 Representative Part 30 -1000 20 0 2 4 6 8 10 12 14 16 18 1100 110000 1 010k0 1 01000k0 1 0 100000k0 1 0 0 10M000 Power Supply Voltage (V) Frequency (Hz) FIGURE 2-7: Input Offset Voltage vs. FIGURE 2-10: CMRR, PSRR vs. Power Supply Voltage. Frequency. 1,000 130 y sit 120 PSRR en B)110 D d Noise Voltage (nV/Hz)√ 100 CMRR, PSRR (107890000 C M R R @@@ VVVDDDDDD === 1535V.5VV ut 60 p n I 50 10 11 1100 110000 1 010k0 1 01000k0 110000k0 0 0 -50 -25 0 25 50 75 100 125 Frequency (Hz) Ambient Temperature (°C) FIGURE 2-8: Input Noise Voltage Density FIGURE 2-11: CMRR, PSRR vs. Ambient vs. Frequency. Temperature. se Voltage Density (nV/ Hz)√233445505050 and Offset Currents 1(A)0111001010000110000000nnpn0000 VDD = 15V Input Bias Current Noi 20 f = 1 kHz as put 15 VDD = 16V ut Bi 101p0 n p Input Offset Current I 10 In 1p1 -1 1 3 5 7 9 11 13 15 25 35 45 55 65 75 85 95 05 15 25 1 1 1 Common Mode Input Voltage (V) Ambient Temperature (°C) FIGURE 2-9: Input Noise Voltage Density FIGURE 2-12: Input Bias, Offset Currents vs. Common Mode Input Voltage. vs. Ambient Temperature. DS22243B-page 8 © 2010 Microchip Technology Inc.

MCP6H01/2 Note: Unless otherwise indicated, T =+25°C, V =+3.5V to +16V, V =GND, V =V /2 -1.4V, V ≈V /2, A DD SS CM DD OUT DD V =V /2, R =10kΩ to V and C =60pF. L DD L L L 100100000n 120 0 TA = +125°C 100 Open-Loop Gain -30 urrent (A)1010011000n00n Gain (dB) 6800 Open-Loop Phase --9600 Phase (°) Input Bias C 1011010000pp TA = +85°C VDD = 15V Open-Loop 24000 ---111852000 Open-Loop 11p -20 -210 0 2 4 6 8 10 12 14 16 1 .00E.-011 1 .01E+ 0 0 11.00E+ 0 1 11.00E0+0 2 11.0Ek+ 0 3 110.0Ek+0 4 110.00E+k05 11.0ME+ 0 6101.0ME+07 Common Mode Input Voltage (V) Frequency (Hz) FIGURE 2-13: Input Bias Current vs. FIGURE 2-16: Open-Loop Gain, Phase vs. Common Mode Input Voltage. Frequency. 200 160 190 nt Current mplifier) 111114567800000 VVVDDDDDD === 1535V.5VV oop Gain (dB)111123450000 Quiesce(µA/A 111101230000 C-Open L110100 VSS + 0.2V < VOUT < VDD - 0.2V D 90 90 80 80 -50 -25 0 25 50 75 100 125 3 5 7 9 11 13 15 17 Ambient Temperature (°C) Power Supply Voltage (V) FIGURE 2-14: Quiescent Current vs. FIGURE 2-17: DC Open-Loop Gain vs. Ambient Temperature. Power Supply Voltage. 200 150 180 dB)140 nt Current mplifier) 111102460000 Loop Gain (111123000 VVDDDD == 155VV Quiesce(µA/A 468000 TTTAAA === +++1822555°°CC°C DC-Open 10900 VDD = 3.5V T = -40°C 20 A 80 0 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0 2 4 6 8 10 12 14 16 Output Voltage Headroom (V) Power Supply Voltage (V) VDD - VOH or VOL - VSS FIGURE 2-15: Quiescent Current vs. FIGURE 2-18: DC Open-Loop Gain vs. Power Supply Voltage. Output Voltage Headroom. © 2010 Microchip Technology Inc. DS22243B-page 9

MCP6H01/2 Note: Unless otherwise indicated, T =+25°C, V =+3.5V to +16V, V =GND, V =V /2 -1.4V, V ≈V /2, A DD SS CM DD OUT DD V =V /2, R =10kΩ to V and C =60pF. L DD L L L 160 nt 70 e annel dB) 112400 uit Curr 5600 Channel to ChSeparation ( 1068000 Input Referred utput Short Circ(mA)12340000 TTTTAAAA ==== +++-41820255°5°°CCC°C O 0 40 0 2 4 6 8 10 12 14 16 110000 1 01k0 0 1 01000k0 1 0100000k0 Frequency (Hz) Power Supply Voltage (V) FIGURE 2-19: Channel-to-Channel FIGURE 2-22: Output Short Circuit Current Separation vs. Frequency (MCP6H02 only). vs. Power Supply Voltage. 1.8 180 100 n Bandwidth Product (MHz)0001111.......4680246 Gain BandwidthP hParsoed uMcatrgin 468111100002460000Phase Margin (°) ut Voltage Swing (V)P-P 101 VDD = V15DDV = 5VVDD = 3.5V Gai 0.2 VDD = 3.5V 20 Outp 0.0 0 0.1 -50 -25 0 25 50 75 100 125 1 10000 1 10k0 0 1 1000k0 0 1 0100000k0 1 0 10M0000 Ambient Temperature (°C) Frequency (Hz) FIGURE 2-20: Gain Bandwidth Product, FIGURE 2-23: Output Voltage Swing vs. Phase Margin vs. Ambient Temperature. Frequency. 1.8 180 V)10000 dwidth Product (MHz)01111.....80246 Gain BandwidthP hParosed uMcatrgin 81111002460000e Margin (°) ge Headroom (m 1010000 VDD = 15V VDD - VOH n s a Ba 0.6 60 ha olt Gain 00..24 VDD = 15V 2400 P put V 10 VOL - VSS ut 0.0 0 O 1 -50 -25 0 25 50 75 100 125 0.01 0.1 1 10 100 Ambient Temperature (°C) Output Current (mA) FIGURE 2-21: Gain Bandwidth Product, FIGURE 2-24: Output Voltage Headroom Phase Margin vs. Ambient Temperature. vs. Output Current. DS22243B-page 10 © 2010 Microchip Technology Inc.

MCP6H01/2 Note: Unless otherwise indicated, T =+25°C, V =+3.5V to +16V, V =GND, V =V /2 -1.4V, V ≈V /2, A DD SS CM DD OUT DD V =V /2, R =10kΩ to V and C =60pF. L DD L L L mV) 1000 mV) 8 m ( VDD = 5V m ( 7 VDD - VOH Voltage Headroo 101001 VDD - VOHVOL - VSS Voltage Headroo 456 VOL - VSS VDD = 5V Output 0.1 Output 23 0.01 0.1 1 10 100 -50 -25 0 25 50 75 100 125 Output Current (mA) Ambient Temperature (°C) FIGURE 2-25: Output Voltage Headroom FIGURE 2-28: Output Voltage Headroom vs. Output Current. vs. Ambient Temperature. V) 1000 V) 8 m m m ( VDD = 3.5V m ( 7 o 100 o o o utput Voltage Headr 101 VOL - VS S V DD - VOH utput Voltage Headr 3456 VDD - VVOOHL - VSS VDD = 3.5V O 0.1 O 2 0.0 0.1 1.0 10.0 -50 -25 0 25 50 75 100 125 Output Current (mA) Ambient Temperature (°C) FIGURE 2-26: Output Voltage Headroom FIGURE 2-29: Output Voltage Headroom vs. Output Current. vs. Ambient Temperature. V) 22 1.0 m m ( 21 0.9 oo 20 s) 0.8 Voltage Headr 111789 VDD - VOH VOL - VSS Slew Rate (V/µ 0000....4567 R i s i nFga lElindgg eE, dVgDeD, =V D1D5 V= 15V put 16 VDD = 15V 0.3 ut O 15 0.2 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 Ambient Temperature (°C) Ambient Temperature (°C) FIGURE 2-27: Output Voltage Headroom FIGURE 2-30: Slew Rate vs. Ambient vs. Ambient Temperature. Temperature. © 2010 Microchip Technology Inc. DS22243B-page 11

MCP6H01/2 Note: Unless otherwise indicated, T =+25°C, V =+3.5V to +16V, V =GND, V =V /2 -1.4V, V ≈V /2, A DD SS CM DD OUT DD V =V /2, R =10kΩ to V and C =60pF. L DD L L L 1.6 16 1.4 Falling Edge, VDD = 5V 14 Rising Edge, VDD = 5V e (V/µs) 11..02 age (V)1102 Rat 0.8 Volt 8 Slew 00..46 R i s iFnagl lEindgg Ee,d VgDeD, V=D 3D. 5=V 3.5V Output 46 VGD =D =+ 11V5/VV 0.2 2 0.0 -50 -25 0 25 50 75 100 125 0 Ambient Temperature (°C) Time (20 µs/div) FIGURE 2-31: Slew Rate vs. Ambient FIGURE 2-34: Large Signal Non-Inverting Temperature. Pulse Response. 16 v) 14 di mv/ V) 12 VGD =D =-1 1V5/VV put Voltage (20 VGD =D =+ 11V5/VV Output Voltage ( 10468 ut O 2 0 Time (2 µs/div) Time (20 µs/div) FIGURE 2-32: Small Signal Non-Inverting FIGURE 2-35: Large Signal Inverting Pulse Pulse Response. Response. 17 v) V = 15V 15 20 mv/di GD =D -1V/V ge (V) 1113 VIN VOUT ge ( olta 9 olta ut V 7 V p 5 utput Out 3 VGD =D =+ 21V5/VV O 1 -1 Time (2 µs/div) Time (0.1 ms/div) FIGURE 2-33: Small Signal Inverting Pulse FIGURE 2-36: The MCP6H01/2 Shows No Response. Phase Reversal. DS22243B-page 12 © 2010 Microchip Technology Inc.

MCP6H01/2 Note: Unless otherwise indicated, T =+25°C, V =+3.5V to +16V, V =GND, V =V /2 -1.4V, V ≈V /2, A DD SS CM DD OUT DD V =V /2, R =10kΩ to V and C =60pF. L DD L L L 1000 11.00mE-03 101.000E-µ04 ut 11.000Eµ-05 sed Loop Outpmpedance (Ω)11000 GN: -I (A)IN 10111110....10100000000EEEEnnnµ----00009876 TTTTAAAA ==== +++-41820255°5°°CCC°C oI 101V/V 100p Cl 11V/V 1.00E-10 10p 1V/V 1.00E-11 1p 1 1.00E-12 1 .10E0+0 1 11.00E0+0 2 1 .01Ek+0 3 1 . 01E+00k4 11.00E+005k 1 . 01EM+06 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 Frequency (Hz) VIN (V) FIGURE 2-37: Closed Loop Output FIGURE 2-38: Measured Input Current vs. Impedance vs. Frequency. Input Voltage (below V ). SS © 2010 Microchip Technology Inc. DS22243B-page 13

MCP6H01/2 NOTES: DS22243B-page 14 © 2010 Microchip Technology Inc.

MCP6H01/2 3.0 PIN DESCRIPTIONS Descriptions of the pins are listed in Table3-1. TABLE 3-1: PIN FUNCTION TABLE MCP6H01 MCP6H02 Symbol Description SOIC 2x3 TDFN SOIC 2x3 TDFN 6 6 1 1 V , V Analog Output (op amp A) OUT OUTA 2 2 2 2 V –, V – Inverting Input (op amp A) IN INA 3 3 3 3 V +, V + Non-inverting Input (op amp A) IN INA 7 7 8 8 V Positive Power Supply DD — — 5 5 V + Non-inverting Input (op amp B) INB — — 6 6 V – Inverting Input (op amp B) INB — — 7 7 V Analog Output (op amp B) OUTB 4 4 4 4 V Negative Power Supply SS 1, 5, 8 1, 5, 8 — — NC No Internal Connection — 9 — 9 EP Exposed Thermal Pad (EP); must be connected to V SS 3.1 Analog Outputs 3.3 Power Supply Pins The output pins are low-impedance voltage sources. The positive power supply (V ) is 3.5V to 16V higher DD than the negative power supply (V ). For normal SS 3.2 Analog Inputs operation, the other pins are at voltages between VSS and V . DD The non-inverting and inverting inputs are Typically, these parts can be used in single-supply high-impedance CMOS inputs with low bias currents. operation or dual-supply operation. Also, V will need DD bypass capacitors. 3.4 Exposed Thermal Pad (EP) There is an internal electrical connection between the Exposed Thermal Pad (EP) and the V pin; they must SS be connected to the same potential on the Printed Circuit Board (PCB). © 2010 Microchip Technology Inc. DS22243B-page 15

MCP6H01/2 NOTES: DS22243B-page 16 © 2010 Microchip Technology Inc.

MCP6H01/2 4.0 APPLICATION INFORMATION 4.1 V The MCP6H01/2 family of op amps is manufactured DD using Microchip’s state-of-the-art CMOS process and is specifically designed for low-power, high-precision D D 1 2 applications. V 1 V OUT 4.1 Inputs MCP6H0x V 4.1.1 PHASE REVERSAL 2 The MCP6H01/2 op amps are designed to prevent phase reversal when the input pins exceed the supply FIGURE 4-2: Protecting the Analog voltages. Figure2-36 shows the input voltage Inputs. exceeding the supply voltage without any phase A significant amount of current can flow out of the reversal. inputs when the Common Mode voltage (V ) is below CM 4.1.2 INPUT VOLTAGE LIMITS ground (VSS); See Figure2-38. In order to prevent damage and/or improper operation 4.1.3 INPUT CURRENT LIMITS of these amplifiers, the circuit must limit the voltages at In order to prevent damage and/or improper operation the input pins (see Section1.1 “Absolute Maximum of these amplifiers, the circuit must limit the currents Ratings †”). into the input pins (see Section1.1 “Absolute The ESD protection on the inputs can be depicted as Maximum Ratings †”). shown in Figure4-1. This structure was chosen to Figure4-3 shows one approach to protecting these protect the input transistors against many (but not all) inputs. The resistors R and R limit the possible 1 2 over-voltage conditions, and to minimize the input bias currents in or out of the input pins (and the ESD diodes, current (IB). D1 and D2). The diode currents will go through either V or V . DD SS Bond V V DD Pad DD D D 1 2 VIN+ BPoandd SIntapguet BPoandd VIN– V1 R 1 MCP6H0X V OUT V 2 V Bond R2 SS Pad R 3 FIGURE 4-1: Simplified Analog Input ESD V –(minimum expected V ) Structures. R > SS 1 1 2mA The input ESD diodes clamp the inputs when they try V –(minimum expected V ) SS 2 to go more than one diode drop below VSS. They also R2> 2mA clamp any voltages that go well above V ; their DD breakdown voltage is high enough to allow normal FIGURE 4-3: Protecting the Analog operation, but not low enough to protect against slow Inputs. over-voltage (beyond V ) events. Very fast ESD DD events (that meet the specification) are limited so that 4.1.4 NORMAL OPERATION damage does not occur. The inputs of the MCP6H01/2 op amps connect to a In some applications, it may be necessary to prevent differential PMOS input stage. It operates at a low excessive voltages from reaching the op amp inputs; common mode input voltage (V ), including ground. CM Figure4-2 shows one approach to protecting these With this topology, the device operates with a V up CM inputs. to V –2.3V and 0.3V below V (refer to Figure2-3 DD SS through 2-5). The input offset voltage is measured at V =V –0.3V and V –2.3V to ensure proper CM SS DD operation. © 2010 Microchip Technology Inc. DS22243B-page 17

MCP6H01/2 For a unity gain buffer, V must be maintained below IN V –2.3V for correct operation. 1 0 10k0 DD V = 16V Ω) RDLD = 10 kΩ 4.2 Rail-to-Rail Output (O The output voltage range of the MCP6H01/2 op amps d R IS 100 GN: e 1 V/V is 0.020V (typical) and 14.980V (typical) when nd 2 V/V R =10kΩ is connected to V /2 and V =15V. me ≥ 5 V/V L DD DD m 10 Refer to Figures2-24 through 2-29 for more o c information. Re 1 4.3 Capacitive Loads 1 .1E0-p1 1 1 1.0E0-1p0 1 . E1-n0 9 1 . E10-0n8 1 .E 0-.017µ 1 . E 1-µ0 6 Normalized Load Capacitance; C/G (F) Driving large capacitive loads can cause stability L N problems for voltage feedback op amps. As the load FIGURE 4-5: Recommended R Values ISO capacitance increases, the feedback loop’s phase for Capacitive Loads. margin decreases and the closed-loop bandwidth is reduced. This produces gain peaking in the frequency 4.4 Supply Bypass response, with overshoot and ringing in the step response. While a unity-gain buffer (G=+1V/V) is the With this family of operational amplifiers, the power most sensitive to capacitive loads, all gains show the supply pin (V for single supply) should have a local DD same general behavior. bypass capacitor (i.e., 0.01µF to 0.1µF) within 2mm When driving large capacitive loads with these op for good high-frequency performance. It can use a bulk amps (e.g., >100pF when G=+1V/V), a small series capacitor (i.e., 1µF or larger) within 100mm to provide resistor at the output (R in Figure4-4) improves the large, slow currents. This bulk capacitor can be shared ISO feedback loop’s phase margin (stability) by making the with other analog parts. output load resistive at higher frequencies. The bandwidth will generally be lower than the bandwidth 4.5 Unused Op Amps with no capacitance load. An unused op amp in a dual package (MCP6H02) should be configured as shown in Figure4-6. These circuits prevent the output from toggling and causing – R crosstalk. Circuit A sets the op amp at its minimum ISO noise gain. The resistor divider produces any desired MCP6H0X VOUT reference voltage within the output voltage range of the V + IN C op amp; the op amp buffers that reference voltage. L Circuit B uses the minimum number of components and operates as a comparator, but it may draw more FIGURE 4-4: Output Resistor, R current. ISO Stabilizes Large Capacitive Loads. Figure4-5 gives the recommended RISO values for 1/2 MCP6H02 (A) 1/2 MCP6H02 (B) different capacitive loads and gains. The x-axis is the V V normalized load capacitance (C /G ), where G is the DD DD L N N circuit’s noise gain. For non-inverting gains, G and the N V Signal Gain are equal. For inverting gains, GN is R1 DD 1+|Signal Gain| (e.g., -1V/V gives G = +2V/V). N V After selecting RISO for your circuit, double check the R2 REF resulting frequency response peaking and step response overshoot. Modify R ’s value until the ISO response is reasonable. Bench evaluation and R 2 simulations with the MCP6H01/2 SPICE macro model V = V ×-------------------- REF DD R +R are very helpful. 1 2 FIGURE 4-6: Unused Op Amps. DS22243B-page 18 © 2010 Microchip Technology Inc.

MCP6H01/2 4.6 PCB Surface Leakage (CMRR). Moreover, R should be much smaller than SEN R and R in order to minimize the resistive loading of 1 2 In applications where low input bias current is critical, the source. PCB surface leakage effects need to be considered. To ensure proper operation, the op amp common mode Surface leakage is caused by humidity, dust or other input voltage must be kept within the allowed range. contamination on the board. Under low-humidity condi- The reference voltage (V ) is supplied by a tions, a typical resistance between nearby traces is REF 1012Ω. A 15V difference would cause 15pA of current low-impedance source. In single-supply applications, V is typically V /2. to flow; which is greater than the MCP6H01/2 family’s REF DD bias current at +25°C (10pA, typical). . The easiest way to reduce surface leakage is to use a R R 1 2 guard ring around sensitive pins (or traces). The guard V ring is biased at the same voltage as the sensitive pin. REF V An example of this type of layout is shown in DD Figure4-7. V OUT RSEN ISEN MCP6H01 Guard Ring V – V + V IN IN SS R1 R2 R << R , R SEN 1 2 R ⎛ 2⎞ FIGURE 4-7: Example Guard Ring Layout VOUT = (V1–V2)⎝R------⎠ +VREF 1 for Inverting Gain. 1. Non-inverting Gain and Unity-Gain Buffer: FIGURE 4-8: High Side Current Sensing a. Connect the non-inverting pin (VIN+) to the Using Difference Amplifier. input with a wire that does not touch the PCB surface. 4.7.2 TWO OP AMP INSTRUMENTATION b. Connect the guard ring to the inverting input AMPLIFIER pin (V –). This biases the guard ring to the IN The MCP6H01/2 op amps are well suited for common mode input voltage. conditioning sensor signals in battery-powered 2. Inverting Gain and Transimpedance Gain applications. Figure4-9 shows a two op amp Amplifiers (convert current to voltage, such as instrumentation amplifier using the MCP6H02, which photo detectors): works well for applications requiring rejection of a. Connect the guard ring to the non-inverting common mode noise at higher gains. input pin (V +). This biases the guard ring IN To ensure proper operation, the op amp common mode to the same reference voltage as the op input voltage must be kept within the allowed range. amp (e.g., V /2 or ground). DD The reference voltage (V ) is supplied by a low REF b. Connect the inverting pin (VIN–) to the input impedance source. In single-supply applications, VREF with a wire that does not touch the PCB is typically V /2. DD surface. 4.7 Application Circuits 4.7.1 DIFFERENCE AMPLIFIER The MCP6H01/2 op amps can be used in current sensing applications. Figure4-8 shows a resistor (R ) that converts the sensor current (I ) to SEN SEN voltage, as well as a difference amplifier that amplifies the voltage across the resistor while rejecting common mode noise. R and R must be well matched to obtain 1 2 an acceptable Common Mode Rejection Ratio © 2010 Microchip Technology Inc. DS22243B-page 19

MCP6H01/2 A photodiode configured in Photovoltaic mode has a R zero voltage potential placed across it. In this mode, G the light sensitivity and linearity is maximized, making it best suited for precision applications. The key amplifier VREF R1 R2 R2 R1 specifications for this application are: low input bias current, common mode input voltage range (including V ground), and rail-to-rail output. V OUT 2 ½ ½ MCP6H02 MCP6H02 C2 V 1 R 2 R 2R V V = (V –V )⎛1+----1--+--------1-⎞ +V OUT OUT 1 2 ⎝ R2 RG⎠ REF ID1 VDD – FIGURE 4-9: Two Op Amp Light D1 MCP6H01 Instrumentation Amplifier. + To obtain the best CMRR possible, and not limit the performance by the resistor tolerances, set a high gain VOUT = ID1*R2 with the R resistor. G 4.7.3 PHOTODETECTOR AMPLIFIER FIGURE 4-10: Photodetector Amplifier. The MCP6H01/2 op amps can be used to easily convert the signal from a sensor that produces an output current (such as a photo diode) into voltage (a transimpedance amplifier). This is implemented with a single resistor (R ) in the feedback loop of the 2 amplifiers shown in Figure4-10. The optional capacitor (C ) sometimes provides stability for these circuits. 2 DS22243B-page 20 © 2010 Microchip Technology Inc.

MCP6H01/2 5.0 DESIGN AIDS 5.4 MAPS (Microchip Advanced Part Selector) Microchip provides the basic design tools needed for the MCP6H01/2 family of op amps. MAPS is a software tool that helps semiconductor professionals efficiently identify Microchip devices that fit a particular design requirement. Available at no cost from 5.1 SPICE Macro Model the Microchip website at www.microchip.com/ maps, The latest SPICE macro model for the MCP6H01/2 op MAPS is an overall selection tool for Microchip’s product amp is available on the Microchip web site at portfolio that includes analog, memory, MCUs and www.microchip.com. The model was written and tested DSCs. Using this tool, you can define a filter to sort in PSPICE owned by Orcad (Cadence). For other features for a parametric search of devices and export simulators, it may require translation. side-by-side technical comparison reports. Helpful links are also provided for data sheets, purchases and The model covers a wide aspect of the op amp’s sampling of Microchip parts. electrical specifications. Not only does the model cover voltage, current and resistance of the op amp, but it 5.5 Analog Demonstration and also covers the temperature and noise effects on the Evaluation Boards behavior of the op amp. The model has not been Microchip offers a broad spectrum of Analog verified outside the specification range listed in the op Demonstration and Evaluation Boards that are designed amp data sheet. The model behaviors under these con- to help you achieve faster time to market. For a com- ditions cannot be guaranteed to match the actual op plete listing of these boards and their corresponding amp performance. user’s guides and technical information, visit the Moreover, the model is intended to be an initial design Microchip web site: www.microchip.com/analogtools. tool. Bench testing is a very important part of any Some boards that are especially useful include: design and cannot be replaced with simulations. Also, • MCP6XXX Amplifier Evaluation Board 1 simulation results using this macro model need to be • MCP6XXX Amplifier Evaluation Board 2 validated by comparing them to the data sheet • MCP6XXX Amplifier Evaluation Board 3 specifications and characteristic curves. • MCP6XXX Amplifier Evaluation Board 4 5.2 FilterLab® Software • Active Filter Demo Board Kit • 5/6-Pin SOT-23 Evaluation Board, P/N VSUPEV2 Microchip’s FilterLab software is an innovative software • 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board, tool that simplifies analog active filter (using op amps) P/N SOIC8EV design. Available at no cost from the Microchip web site 5.6 Application Notes at www.microchip.com/filterlab, the FilterLab design tool provides full schematic diagrams of the filter circuit The following Microchip analog design note and appli- with component values. It also outputs the filter circuit cation notes are available on the Microchip web site at in SPICE format, which can be used with the macro www.microchip.com/appnotes, and are recommended model to simulate actual filter performance. as supplemental reference resources. • ADN003: “Select the Right Operational Amplifier 5.3 Mindi™ Circuit Designer and for your Filtering Circuits”, DS21821 Simulator • AN722: “Operational Amplifier Topologies and DC Specifications”, DS00722 Microchip’s Mindi circuit designer and simulator aids in • AN723: “Operational Amplifier AC Specifications the design of various circuits useful for active filter, and Applications”, DS00723 amplifier and power management applications. It is a • AN884: “Driving Capacitive Loads With Op free online circuit designer and simulator available from Amps”, DS00884 the Microchip web site at www.microchip.com/mindi. • AN990: “Analog Sensor Conditioning Circuits– This interactive circuit designer and simulator enables An Overview”, DS00990 designers to quickly generate circuit diagrams and • AN1177: “Op Amp Precision Design: DC Errors”, simulate circuits. Circuits developed using the Mindi DS01177 circuit designer and simulator can be downloaded to a • AN1228: “Op Amp Precision Design: Random personal computer or workstation. Noise”, DS01228 • AN1297: “Microchip’s Op Amp SPICE Macro Models”’ DS01297 • AN1332: “Current Sensing Circuit Concepts and Fundamentals”’ DS01332 These application notes and others are listed in: • “Signal Chain Design Guide”, DS21825 © 2010 Microchip Technology Inc. DS22243B-page 21

MCP6H01/2 NOTES: DS22243B-page 22 © 2010 Microchip Technology Inc.

MCP6H01/2 6.0 PACKAGING INFORMATION 6.1 Package Marking Information 8-Lead SOIC (150 mil) (MCP6H01, MCP6H02) Example: XXXXXXXX MCP6H01E XXXXYYWW SN^e^31010 NNN 256 8-Lead 2x3 TDFN (MCP6H01, MCP6H02) Example: XXX AAL YWW 010 NN 25 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2010 Microchip Technology Inc. DS22243B-page 23

MCP6H01/2 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22243B-page 24 © 2010 Microchip Technology Inc.

MCP6H01/2 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2010 Microchip Technology Inc. DS22243B-page 25

MCP6H01/2 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:10)(cid:8)(cid:17)(cid:18)(cid:12)(cid:10)(cid:13)(cid:19)(cid:5)(cid:8)(cid:20)(cid:15)(cid:21)(cid:22)(cid:8)(cid:23)(cid:8)(cid:21)(cid:6)(cid:24)(cid:24)(cid:25)(cid:26)(cid:27)(cid:8)(cid:28)(cid:29)(cid:30)(cid:31)(cid:8)(cid:16)(cid:16)(cid:8) (cid:25)(cid:7)!(cid:8)"(cid:15)(cid:17)#$% (cid:21)(cid:25)(cid:12)(cid:5)& (cid:30)(cid:10)(cid:9)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2)!(cid:10)"(cid:31)(cid:2)(cid:8)#(cid:9)(cid:9)(cid:14)(cid:15)(cid:31)(cid:2)(cid:12)(cid:28)(cid:8)$(cid:28)(cid:17)(cid:14)(cid:2)%(cid:9)(cid:28)&(cid:7)(cid:15)(cid:17)"’(cid:2)(cid:12)(cid:16)(cid:14)(cid:28)"(cid:14)(cid:2)"(cid:14)(cid:14)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)((cid:28)(cid:8)$(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7))(cid:7)(cid:8)(cid:28)(cid:31)(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)(cid:31)(cid:14)%(cid:2)(cid:28)(cid:31)(cid:2) (cid:11)(cid:31)(cid:31)(cid:12)*++&&&(cid:20)!(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)!+(cid:12)(cid:28)(cid:8)$(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) DS22243B-page 26 © 2010 Microchip Technology Inc.

MCP6H01/2 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2010 Microchip Technology Inc. DS22243B-page 27

MCP6H01/2 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22243B-page 28 © 2010 Microchip Technology Inc.

MCP6H01/2 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)’(cid:18)(cid:6)(cid:10)(cid:8)((cid:10)(cid:6)(cid:12)(cid:27)(cid:8)(cid:21)(cid:25)(cid:8)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:14))(cid:6)*(cid:5)(cid:8)(cid:20)+(cid:21)(cid:22)(cid:8)(cid:23)(cid:8),-(cid:28)-(cid:31)(cid:29)./(cid:8)(cid:16)(cid:16)(cid:8) (cid:25)(cid:7)!(cid:8)"0’((cid:21)% (cid:21)(cid:25)(cid:12)(cid:5)& (cid:30)(cid:10)(cid:9)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2)!(cid:10)"(cid:31)(cid:2)(cid:8)#(cid:9)(cid:9)(cid:14)(cid:15)(cid:31)(cid:2)(cid:12)(cid:28)(cid:8)$(cid:28)(cid:17)(cid:14)(cid:2)%(cid:9)(cid:28)&(cid:7)(cid:15)(cid:17)"’(cid:2)(cid:12)(cid:16)(cid:14)(cid:28)"(cid:14)(cid:2)"(cid:14)(cid:14)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)((cid:28)(cid:8)$(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7))(cid:7)(cid:8)(cid:28)(cid:31)(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)(cid:31)(cid:14)%(cid:2)(cid:28)(cid:31)(cid:2) (cid:11)(cid:31)(cid:31)(cid:12)*++&&&(cid:20)!(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)!+(cid:12)(cid:28)(cid:8)$(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) © 2010 Microchip Technology Inc. DS22243B-page 29

MCP6H01/2 APPENDIX A: REVISION HISTORY Revision B (October 2010) The following is the list of modifications: • Updated Section 4.1 “Inputs”. • Updated Section 6.0 “Packaging Information”. - Package drawings were replaced for Drawing C04-057C, 8-Lead Plastic Small Outline (SN) - Narrow, 3.90mm Body [SOIC] - Package drawings were replaced for Drawing C04-129C, 8-Lead Plastic Dual Flat, No Lead Package (MN) - 2x3x0.75mm Body [TDFN] Revision A (March 2010) • Original Release of this Document. DS22243A-page 30 © 2010 Microchip Technology Inc.

MCP6H01/2 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. -X /XX Examples: a) MCP6H01-E/SN: 8LD SOIC pkg Device Temperature Package b) MCP6H01T-E/SN: Tape and Reel, Range 8LD SOIC pkg c) MCP6H01T-E/MNY: Tape and Reel, 8LD 2x3 TDFN pkg Device: MCP6H01: Single Op Amp MCP6H01T: Single Op Amp (Tape and Reel) d) MCP6H02-E/SN: 8LD SOIC pkg (SOIC and 2x3 TDFN) e) MCP6H02T-E/SN: Tape and Reel, MCP6H02: Dual Op Amp 8LD SOIC pkg MCP6H02T: Dual Op Amp (Tape and Reel) f) MCP6H02T-E/MNY: Tape and Reel (SOIC and 2x3 TDFN) 8LD 2x3 TDFN pkg Temperature Range: E = -40°C to +125°C Package: MNY * = Plastic Dual Flat, No Lead, (2x3 TDFN ) 8-lead SN = Plastic SOIC, (150 mil Body), 8-lead * Y = Nickel palladium gold manufacturing designator. Only available on the TDFN package. © 2010 Microchip Technology Inc. DS22243B-page 31

MCP6H01/2 NOTES: DS22243B-page 32 © 2010 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. PIC32 logo, rfPIC and UNI/O are registered trademarks of MICROCHIP MAKES NO REPRESENTATIONS OR Microchip Technology Incorporated in the U.S.A. and other WARRANTIES OF ANY KIND WHETHER EXPRESS OR countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MXDEV, MXLAB, SEEVAL and The Embedded Control QUALITY, PERFORMANCE, MERCHANTABILITY OR Solutions Company are registered trademarks of Microchip FITNESS FOR PURPOSE. Microchip disclaims all liability Technology Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, CodeGuard, devices in life support and/or safety applications is entirely at dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, the buyer’s risk, and the buyer agrees to defend, indemnify and ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial hold harmless Microchip from any and all damages, claims, Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified suits, or expenses resulting from such use. No licenses are logo, MPLIB, MPLINK, mTouch, Omniscient Code conveyed, implicitly or otherwise, under any Microchip Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, intellectual property rights. PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2010, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-60932-640-1 Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2010 Microchip Technology Inc. DS22243B-page 33

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