MCP65R41/6 3 µA Comparator with Integrated Reference Voltage Features Description • Factory Set Reference Voltage The Microchip Technology Inc. MCP65R41/6 family of - Available Voltage: 1.21V and 2.4V push-pull and open-drain output comparators are offered with integrated Reference Voltages of 1.21V - Tolerance: ±1% (typical) and 2.4V. This family provides ±1% (typical) tolerance • Low Quiescent Current: 2.5µA (typical) while consuming 2.5µA (typical) current. These • Propagation Delay: 4µs with 100mV overdrive comparators operate with a single-supply voltage as • Input Offset Voltage: ±3mV (typical) low as 1.8V to 5.5V, which makes them ideal for low • Rail-to-Rail Input: V - 0.3V to V + 0.3V cost and/or battery powered applications. SS DD • Output Options: These comparators are optimized for low power, - MCP65R41  Push-Pull single-supply applications with greater than rail-to-rail - MCP65R46 Open-Drain input operation. The output limits supply current surges and dynamic power consumption while switching. The • Wide Supply Voltage Range: 1.8V to 5.5V internal input hysteresis eliminates output switching • Packages: SOT23-6 due to internal noise voltage, reducing current draw. The MCP65R41 output interfaces to CMOS/TTL logic. Typical Applications The open-drain output device MCP65R46 can be used as a level-shifter from 1.6V to 10V using a pull-up • Laptop computers resistor. It can also be used as a wired-OR logic. • Mobile Phones This family of devices is available with 6 lead SOT-23 • Hand-held Metering Systems package. • Hand-held Electronics • RC Timers Package Types • Alarm and Monitoring Circuits • Window Comparators MCP65R41/6 SOT23-6 Design Aids OUT 1 6 V DD • Microchip Advanced Part Selector (MAPS) • Analog Demonstration and Evaluation Boards VSS 2 + - 5 VREF +IN 3 4 -IN Typical Application Over Temperature Alert V REF R VDD VPU 4 R * PU Thermistor VREF VOUT R 2 R R F 3 * Pull-up resistor required for the MCP65R46 only.  2010 Microchip Technology Inc. DS22269A-page 1

MCP65R41/6 NOTES: DS22269A-page 2  2010 Microchip Technology Inc.

MCP65R41/6 1.0 ELECTRICAL †Notice: Stresses above those listed under “Maximum CHARACTERISTICS Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those 1.1 Absolute Maximum Ratings† indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions V - V .......................................................................7.0V DD SS for extended periods may affect device reliability. All other inputs and outputs...........V – 0.3V to V + 0.3V SS DD Difference Input voltage ......................................|V - V | DD SS Output Short Circuit Current ....................................±25mA Current at Input Pins ..................................................±2mA Current at Output and Supply Pins ..........................±50mA Storage temperature...................................-65°C to +150°C Ambient temperature with power applied....-40°C to +125°C Junction temperature................................................+150°C ESD protection on all pins (HBM/MM)4kV/200V ESD protection on MCP65R46 OUT pin (HBM/MM)............. 4kV/175V DC CHARACTERISTICS Unless otherwise indicated, all limits are specified for: V = +1.8V to +5.5V, V = GND, T = +25°C, V = DD SS A IN+ V /2, V = V , R =100 k to V /2 (MCP65R41 only), and R = 2.74 k to V (MCP65R46 only), DD IN- SS L DD Pull-Up DD and T = -40°C to 125°C. A Parameters Sym Min Typ Max Units Conditions Power Supply Supply Voltage V 1.8 — 5.5 V DD Quiescent Current per Comparator I — 2.5 4 µA I = 0 Q OUT Input Input Voltage Range V V 0.3 — V +0.3 V CMR SS DD Common-Mode Rejection Ratio CMRR 55 70 — dB V = -0.3V to 5.3V CM VDD = 5V 50 65 — dB VCM = 2.5V to 5.3V 55 70 — dB MCP65R41, V = -0.3V to 2.5V CM 50 70 — dB MCP65R46, V = -0.3V to 2.5V CM Power Supply Rejection Ratio PSRR 63 80 — dB V = V CM SS Input Offset Voltage V -10 ±3 +10 mV V = V (Note1) OS CM SS Drift with Temperature V /T — ±10 — µV/°C V = V OS CM SS Input Hysteresis Voltage V 1 3.3 5 mV V = V (Note1) HYST CM SS Drift with Temperature V /T — 6 — µV/°C V = V HYST CM SS Drift with Temperature V /T2 — 5 — µV/°C2 V = V HYST CM SS Input Bias Current I — 1 — pA V =V B CM SS T = +85°C I — 50 — pA V = V A B CM SS T = +125°C I — — 5000 pA V = V A B CM SS Input Offset Current I — ±1 — pA V =V OS CM SS Note 1: The input offset voltage is the center (average) of the input-referred trip points. The input hysteresis is the difference between the input-referred trip points. 2: Limit the output current to Absolute Maximum Rating of 30mA. 3: Do not short the output of the MCP65R46 comparators above V + 10V. SS 4: The low power reference voltage pin is designed to drive small capacitive loads. See Section4.5.2.  2010 Microchip Technology Inc. DS22269A-page 3

MCP65R41/6 DC CHARACTERISTICS (CONTINUED) Unless otherwise indicated, all limits are specified for: V = +1.8V to +5.5V, V = GND, T = +25°C, V = DD SS A IN+ V /2, V = V , R =100 k to V /2 (MCP65R41 only), and R = 2.74 k to V (MCP65R46 only), DD IN- SS L DD Pull-Up DD and T = -40°C to 125°C. A Parameters Sym Min Typ Max Units Conditions Common Mode/ Z /Z — 1013||4 — ||pF CM DIFF Differential Input Impedance Push Pull Output High Level Output Voltage V V 0.2 — — V I = -2 mA, V = 5V OH DD OUT DD Low Level Output Voltage V — — V +0.2 V I = 2 mA, V = 5V OL SS OUT DD Short Circuit Current I — ±50 — mA (Note2) MCP65R41 SC I — ±1.5 — mA (Note2) MCP65R46 SC Open Drain Output (MCP65R46) Low Level Output Voltage V — — V +0.2 V I = 2 mA OL SS OUT Short Circuit Current I — ±50 — mA SC High-Level Output Current I -100 — — nA V = 10V OH PU Pull-up Voltage V 1.6 — 10 V Note3 PU Output Pin Capacitance C — 8 — pF OUT Reference Voltage Output Initial Reference Tolerance V -2 ±1 +2 % I = 0A, TOL REF V = 1.21V and 2.4V REF V 1.185 1.21 1.234 V I = 0A REF REF 2.352 2.4 2.448 V Reference Output Current I — ±500 — µA V = ±2% (maximum) REF TOL Drift with Temperature (character- V /T — 27 100 ppm V = 1.21V, V = 1.8V REF REF DD ized but not production tested) — 22 100 ppm V = 1.21V, V = 5.5V REF DD — 23 100 ppm V = 2.4V, V = 5.5V REF DD Capacitive Load C — 200 — pF Note4 L Note 1: The input offset voltage is the center (average) of the input-referred trip points. The input hysteresis is the difference between the input-referred trip points. 2: Limit the output current to Absolute Maximum Rating of 30mA. 3: Do not short the output of the MCP65R46 comparators above V + 10V. SS 4: The low power reference voltage pin is designed to drive small capacitive loads. See Section4.5.2. DS22269A-page 4  2010 Microchip Technology Inc.

MCP65R41/6 AC CHARACTERISTICS Unless otherwise indicated, all limits are specified for: V = +1.8V to +5.5V, V = GND, T = +25°C, DD SS A V = V /2, Step = 200 mV, Overdrive = 100 mV, R =100 k to V /2 (MCP65R41 only), IN+ DD L DD R = 2.74 k to V (MCP65R46 only), and C = 50 pF. Pull-Up DD L Parameters Sym Min Typ Max Units Conditions Rise Time t — 0.85 — µs R Fall Time t — 0.85 — µs F Propagation Delay (High to Low) t — 4 8.0 µs PHL Propagation Delay (Low to High) t — 4 8.0 µs PLH Propagation Delay Skew t — ±0.2 — µs Note1 PDS Maximum Toggle Frequency f — 160 — kHz V = 1.8V MAX DD f — 120 — kHz V = 5.5V MAX DD Input Noise Voltage E — 200 — µV 10Hz to 100kHz N P-P Note 1: Propagation Delay Skew is defined as: t = t - t . PDS PLH PHL TEMPERATURE SPECIFICATIONS Unless otherwise indicated, all limits are specified for: V = +1.8V to +5.5V and V = GND. DD SS Symbo Parameters Min Typ Max Units Conditions l Temperature Ranges Specified Temperature Range T -40 — +125 °C A Operating Temperature Range T -40 — +125 °C A Storage Temperature Range T -65 — +150 °C A Thermal Package Resistances Thermal Resistance, SOT23-6  — 190.5 — °C/W JA 1.2 Test Circuit Configuration V DD V 200k MCP65R46 DD 2.74k 200k MCP65R41 200k VOUT 200k 100k 50p 200k VOUT V = 0V SS 200k 50p VIN=VSS V = 0V SS V =V IN SS FIGURE 1-2: Test Circuit for the Open Drain Comparators. FIGURE 1-1: Test Circuit for the Push-pull Output Comparators.  2010 Microchip Technology Inc. DS22269A-page 5

MCP65R41/6 NOTES: DS22269A-page 6  2010 Microchip Technology Inc.

MCP65R41/6 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = GND, R = 100k to V /2 (MCP65R41 only), R = 2.74k to V /2 (MCP65R46 only) and C = 50pF. L DD Pull-Up DD L 50% 60% VDD = 1.8V VDD = 5.5V VCM = VSS 40% VCM = VSS VCM = VSS 50% Avg. = 9.86 µV/°C %) Avg. = 1.09 mV Avg. = 0.61 mV %) StDev = 4.97 µV/°C es ( 30% S85tD0 euvn =it s1.59 mV S85tD0 euvn =it s1.48 mV es ( 40% 8T5A0 = U -4n0it°sC to +125°C c c n n 30% e e curr 20% curr 20% c c O O 10% 10% 0% 0% -10 -8 -6 -4 -2 0 2 4 6 8 10 -60 -48 -36 -24 -12 0 12 24 36 48 60 V (mV) V Drift (µV/°C) OS OS FIGURE 2-1: Input Offset Voltage. FIGURE 2-4: Input Offset Voltage Drift. 10.0 3.0 8.0 VCM = VSS 6.0 2.0 4.0 mV) 2.0 VDD= 1.8V V) 1.0 V (OS --420...000 VDD= 5.5V V (mOS -10..00 -6.0 -2.0 -8.0 TA= -40°C to +125°C -10.0 -3.0 -50 -25 0 25 50 75 100 125 1.5 2.5 3.5 4.5 5.5 Temperature(°C) V (V) DD FIGURE 2-2: Input Offset Voltage FIGURE 2-5: Input Offset Voltage vs. vs. Temperature. Supply Voltage vs. Temperature. 10.0 10.0 68..00 TA= -40°C VDD = 1.8V 7.5 TVAD D= =-4 50.°5CV to +125°C 4.0 TA= +25°C 5.0 mV) 2.0 V) 2.5 V (OS -20..00 TA= +85°C (mOS -02..50 -4.0 TA= +125°C V -5.0 -6.0 -7.5 -8.0 -10.0 -10.0 -0.3 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 -1.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 V (V) V (V) CM CM FIGURE 2-3: Input Offset Voltage FIGURE 2-6: Input Offset Voltage vs. vs. Common-Mode Input Voltage. Common-Mode Input Voltage.  2010 Microchip Technology Inc. DS22269A-page 7

MCP65R41/6 Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = GND, R = 100k to V /2 (MCP65R41 only), R = 2.74k to V /2 (MCP65R46 only) and C = 50pF. L DD Pull-Up DD L 30% 80% 25% VASDtvDDg e=. v =5 =.25 .0V3. 1m7V mV VASDtvDDg e=. v =1 =.28 .0V4. 1m7V mV 70% VADvDg .= = 5 5.5.V7 µV/°C %) 850 units 850 units %) 60% StDev = 0.50 µV/°C Occurrences ( 112050%%% Occurrences ( 23450000%%%% 85VAS0DtvD DgU e.=n v= i1 t =6.s8 .01V. 5µ5V /µ°VC/°C 5% TA = -40°C 10% TVAC M= =- 4V0S°SC to +125°C 0% 0% 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 2 4 6 8 10 12 14 16 18 20 V (mV) V Drift, TC1 (µV/°C) HYST HYST FIGURE 2-7: Input Hysteresis Voltage FIGURE 2-10: Input Hysteresis Voltage at -40°C. Drift - Linear Temperature Compensation (TC1). 30% 30% %) 25% VAS85DtvD0Dg e=.u v =n5 =i.2t5 s.0V8. 1m7V mV VAS85DtvD0Dg e=.u v =n1 =i.3t8 s.0V0. 1m7V mV %) VADvDg .= = 5 0.5.V25 µV/°C2 VASDtvDDg e.= v= 1 =.08 .03V. 2µ VµV/°/C°C22 Occurrences ( 112050%%% Occurrences ( 1200%% 1TVS3ACt8 MD=0 e= -Uv 4V 0n=S°iS Ct0s. 1to µ +V1/°2C52°C VVASDCtvDDMg e .== v= 5 V =1.S5 0S0V..46 µµVV//°°CC 5% TA = +25°C 0% 0% 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 -0.50 -0.25 0.00 0.25 0.50 0.75 1.00 VHYST (mV) VHYST Drift, TC2 (µV/°C2) FIGURE 2-8: Input Hysteresis Voltage FIGURE 2-11: Input Hysteresis Voltage at +25°C. Drift - Quadratic Temperature Compensation (TC2). 5.0 30% VDD = 5.5V VDD = 1.8V VCM = VSS 25% Avg. = 3.2 mV Avg. = 3.4 mV %) S85tD0 euvn =it s0.13 mV S85tD0 euvn =it s0.14 mV 4.0 es ( 20% mV) VDD = 1.8V currenc 1105%% V (HYST3.0 Oc 2.0 5% VDD= 5.5V TA = +125°C 0% 1.0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 -50 -25 0 25 50 75 100 125 V (mV) Temperature(°C) HYST FIGURE 2-9: Input Hysteresis Voltage FIGURE 2-12: Input Hysteresis Voltage at +125°C. vs. Temperature. DS22269A-page 8  2010 Microchip Technology Inc.

MCP65R41/6 Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = GND, R = 100k to V /2 (MCP65R41 only), R = 2.74k to V /2 (MCP65R46 only) and C = 50pF. L DD Pull-Up DD L 100% 5.0 Temp -40°C Temp +125°C VDD = 1.8V 90% Avg. = 1.93 µA Avg. = 3.51 µA 80% StDev= 0.08 µA StDev= 0.07 µA 4.0 %) 70% mV) ces ( 60% TAevmg.p = + 38 5µ°AC (HYST 3.0 urren 4500%% StDev= 0.07 µA V 2.0 TTTTAAAA ==== +++-41820255°5°°CCC°C Occ 123000%%% V85D0D =u n1i.t8sV TASetvDmge.p v= =+ 2 20.55.0°2C8 µ µAA 1.0 0% -0.3 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 0.0 1.0 2.0 3.0 4.0 5.0 V (V) I (µV/V) CM Q FIGURE 2-13: Input Hysteresis Voltage vs. FIGURE 2-16: Quiescent Current. Common-Mode Input Voltage. 5.0 3.0 VDD = 5.5V 2.9 VDD = 1.8V 2.8 4.0 2.7 Sweep VIN+ ,VIN- = VDD/2 mV) A)2.6 (HYST 3.0 I (µQ22..45 V 2.0 TTAA == -+4205°°CC 22..23 SSwweeeepp VVIINN-- ,,VVIINN++ == VDD/2 TA = +85°C 2.1 1.0 TA = +125°C 2.0 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 V (V) V (V) CM CM FIGURE 2-14: Input Hysteresis Voltage vs. FIGURE 2-17: Quiescent Current vs. Common-Mode Input Voltage. Common-Mode Input Voltage. 5.0 3.0 TTAA == -+4205°°CC 2.9 VDD = 5.5V 4.0 TA = +85°C 2.8 mV) TA = +125°C A) 22..67 V (HYST 3.0 I (µQ222...345 Sweep VIN- ,VIN+ = VDD/2 2.0 2.2 Sweep VIN+ ,VIN- = VDD/2 2.1 1.0 2.0 1.5 2.5 3.5 4.5 5.5 -1.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 V (V) V (V) DD CM FIGURE 2-15: Input Hysteresis Voltage vs. FIGURE 2-18: Quiescent Current vs. Supply Voltage vs. Temperature. Common-Mode Input Voltage.  2010 Microchip Technology Inc. DS22269A-page 9

MCP65R41/6 Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = GND, R = 100k to V /2 (MCP65R41 only), R = 2.74k to V /2 (MCP65R46 only) and C = 50pF. L DD Pull-Up DD L 4.5 4.0 4.0 3.5 VDD = 5.5V MCP65R46 3.5 3.0 3.0 2.5 A) 2.5 A) µ m 2.0 I (Q 12..50 TA = -40°C I (Q 1.5 Sweep VIN- ,VIN+ = VDD/2 Sweep VIN+ ,VIN- = VDD/2 1.0 TA = +25°C 1.0 TA = +85°C 0.5 0.5 TA = +125°C 0.0 0.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 -1.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 V (V) V (V) DD CM FIGURE 2-19: Quiescent Current vs. FIGURE 2-22: Quiescent Current vs. Supply Voltage vs. Temperature. Common-Mode Input Voltage. 18 10.0 16 100 mV Over-Drive 0 dB Output Attenuation 9.0 MCP65R46 VCM = VDD/2 14 RL = Open 8.0 12 7.0 A) 10 µA) 6.0 (µQ 8 I (Q 5.0 VDD = 5.5V I VDD = 5.5V 4.0 VDD = 4.5V 6 VDD = 1.8V 3.0 VDD = 3.5V 4 2.0 VDD = 2.5V 2 1.0 VDD = 1.8V 0 0 1 2 3 4 5 6 7 8 9 10 1100 110000 1010k0 101000k0 10100000k0 Toggle Frequency (Hz) VPU (V) FIGURE 2-20: Quiescent Current vs. FIGURE 2-23: Quiescent Current vs. Pull Toggle Frequency. Up Voltage. 120 7.0 TA = -40°C VDD = 5.5V VIN+ = VDD/2 80 TA = +25°C 6.0 TA = +85°C 5.0 40 A) 4.0 I (mSC -400 TA = +125°C V (V)OUT 23..00 TA = -40°C VIN- VOUT -80 TA = +25°C 1.0 -120 TA = +85°C 0.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 -1.0 VDD (V) Time (3 µs/div) FIGURE 2-21: Short Circuit Current vs. FIGURE 2-24: No Phase Reversal. Supply Voltage vs. Temperature. DS22269A-page 10  2010 Microchip Technology Inc.

MCP65R41/6 Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = GND, R = 100k to V /2 (MCP65R41 only), R = 2.74k to V /2 (MCP65R46 only) and C = 50pF. L DD Pull-Up DD L 3.0 2.0 2.5 VDD = 1.8V 1.8 VDD = 5.5V VDD - VOH V) V) 1.6 TA = +125°C V, V - V (OLDDOH 112...050 VTTVAAOD L=D= -+- 41V02O°5HC°C V, V - V (OLDDOH00111.....68024 VTTAAO L== T +-A41 02=°5 C-°4C0°C 0.5 TA = +125°C 0.4 TA = -40°C 0.2 0.0 0.0 0.0 2.0 4.0 6.0 8.0 10.0 0 5 10 15 20 25 I (mA) I (mA) OUT OUT FIGURE 2-25: Output Headroom vs. FIGURE 2-28: Output Headroom vs. Output Current. Output Current. 100% 80% es (%) 67890000%%%% tAS8P5tvHD0gL e.u v=n= i3 t0s.5.237 µ µss V1V0DC0DM =mt=P 1LVVH. D8ODV/v2er-Drive es (%)567000%%% tAS8P5tvLD0Hg e.u v=n= i2 t0s.5.1 µ5s µs tAS8P5tvHD0Lg e.u v=n= i3 t0s.6.1 µ9s µs MCP65R46 nc 50% Avg. = 3.92 µs nc40% e StDev= 0.45 µs e urr 40% 850 units urr30% c 30% c Oc 20% Oc20% VDD= 1.8V 100 mV Over-Drive 10% MCP65R41 10% VCM = VDD/2 0% 0% 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10 Prop. Delay (µs) Prop. Delay (µs) FIGURE 2-26: Low-to-High and FIGURE 2-29: Low-to-High and High-to-Low Propagation Delays. High-to-Low Propagation Delays. 100% 80% 90% VDD = 5.5V MCP65R46 100 mV Over-Drive 70% %) 7800%% VCM = VDD/2 %)60% tAPvLHg. = 3.1 µs tAPvHLg. = 4.9 µs nces ( 5600%% tPHL tPLH nces (4500%% S85tD0 euvn =it s0.16 µs S85tD0 euvn =it s0.26 µs e Avg. = 4.76 µs Avg. = 4.97 µs e urr 40% StDev = 0.38 µs StDev = 0.41 µs urr30% Occ 30% 850 units 850 units Occ20% VDD = 5.5V 20% 100 mV Over-Drive 10% MCP65R41 10% VCM = VDD/2 0% 0% 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10 Prop. Delay (µs) Prop. Delay (µs) FIGURE 2-27: Low-to-High and FIGURE 2-30: Low-to-High and High-to-Low Propagation Delays. High-to-Low Propagation Delays .  2010 Microchip Technology Inc. DS22269A-page 11

MCP65R41/6 Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = GND, R = 100k to V /2 (MCP65R41 only), R = 2.74k to V /2 (MCP65R46 only) and C = 50pF. L DD Pull-Up DD L 8 8 7 V10D0D =m 1V. 8OVver- MCP65R41 7 V10D0D =m 1V. 8OVver-Drive MCP65R46 y (µs)ay (ns)56 Di ttPPLHHL y (µs)ay (ns)56 elaDel4 elaDel4 tPLH p. Dop. 3 p. Dop. 3 tPHL ProPr2 ProPr2 1 1 0 0 0.00 0.50 1.00 1.50 2.00 0.0 0.5 1.0 1.5 2.0 V (V) V (V) CM CM FIGURE 2-31: Propagation Delay vs. FIGURE 2-34: Propagation Delay vs. Common-Mode Input Voltage. Common-Mode Input Voltage. 8 8 7 tPLH MCP65R41 7 V10D0D =m 5V. 5OVver-Drive MCP65R46 Prop. Delay (µs)Prop. Delay (ns)23456 tPHL Prop. Delay (µs)Prop. Delay (ns)23456 ttPPLHHL 1 VDD = 5.5V 1 100 mV Over-Drive 0 0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 V (V) V (V) CM CM FIGURE 2-32: Propagation Delay vs. FIGURE 2-35: Propagation Delay vs. Common-Mode Input Voltage. Common-Mode Input Voltage. 20 25 MCP65R41 VCM = VDD/2 VCM = VDD/2 MCP65R46 16 tPHL, 10 mV Over-Drive 20 Prop. Delay (ns)Prop. Delay (µs) 1248 ttPPHLHLt,,P 11LH00,00 1 mm0 VVm OOV vvOeevrr--eDDr-rrDiivvreeive Prop. Delay (ns)Prop. Delay (µs) 11055 ttttPPPPHLHLHHLL,,,, 11110000 00mm mmVVVV OO OOvveevvrree--rrDD--DDrriirrvviieevvee 0 0 1.5 2.5 3.5 4.5 5.5 1.5 2.5 3.5 4.5 5.5 V (V) V (V) DD DD FIGURE 2-33: Propagation Delay vs. FIGURE 2-36: Propagation Delay vs. Supply Voltage. Supply Voltage. DS22269A-page 12  2010 Microchip Technology Inc.

MCP65R41/6 Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = GND, R = 100k to V /2 (MCP65R41 only), R = 2.74k to V /2 (MCP65R46 only) and C = 50pF. L DD Pull-Up DD L 10 10 100 mV Over-Drive MCP65R41 100mV Over-Drive MCP65R46 VCM = VDD/2 VCM= VDD/2 8 8 Prop. Delay (µs)Prop. Delay (ns) 246 tttPPPHHLLLH,,, VVVDDDDDD === 515...585VVV Prop. Delay (ns)Prop. Delay (µs) 246 tPttLPPHHH,LL V,, VDVDDDDD= ==5 .515..V58VV tPLH, VDD = 1.8V tPLH , VDD= 1.8V 0 0 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 Temperature (°C) Temperature(°C) FIGURE 2-37: Propagation Delay vs. FIGURE 2-40: Propagation Delay vs. Temperature. Temperature. 100 1000 100 mV Over-Drive MCP65R41 100 mV Over-Drive MCP65R46 VCM = VDD/2 VCM = VDD/2 Delay (µs) 10 VVDDDD == 55..55VV,, ttPPLHHL Delay (µs) 100 Prop. Prop. 10 VVDDDD == 15..85VV,, ttPPLLHH VVDDDD == 11..88VV,, ttPPLHHL 1 VVDDDD == 15..85VV,, ttPPHHLL 1 00..0011 00..11 11 1100 110000 0.01 0.1 1 10 100 Capacitive Load (nf) Capacitive Load (nf) FIGURE 2-38: Propagation Delay vs. FIGURE 2-41: Propagation Delay vs. Capacitive Load. Capacitive Load. 50 50 45 MCP65R41 VCM = VDD/2 45 MCP65R46 VCM = VDD/2 40 40 Prop. Delay (µs)Prop. Delay (ns)112233050505 ttPPHHLL,, VVDDDD == 51..58ttVVPPLLHH,, VVDDDD == 51..58VV Prop. Delay (µs)Prop. Delay (ns)112233050505 ttPPHHLL,, VVDDDD == 51..58ttPPVVLLHH,, VVDDDD == 51..58VV 5 5 0 0 0.001 0.01 0.1 1 0.001 0.01 0.1 1 Over-Drive (mV) Over-Drive (mV) FIGURE 2-39: Propagation Delay vs. FIGURE 2-42: Propagation Delay vs. Input Over-Drive. Input Over-Drive.  2010 Microchip Technology Inc. DS22269A-page 13

MCP65R41/6 Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = GND, R = 100k to V /2 (MCP65R41 only), R = 2.74k to V /2 (MCP65R46 only) and C = 50pF. L DD Pull-Up DD L 60% 80% MCP65R41 100 mV Over-Drive MCP65R46 50% 70% VCM = VDD/2 %) VADvDg=. =1 .-80V.36 µs VADvDg=. =5 .5-0V.21 µs %) 60% VDD = 1.8V nces ( 3400%% S85tD0 euvn =it s0.07 µs S85tD0 euvn =it s0.07 µs nces ( 4500%% AS85tvD0g e.u v=n =i1t s.01. 1µ1s µs e e Occurr 20% Occurr 2300%% VASDtvDDg e=. v =5 =.15 .0V8.11 4µ sµs 10% 1V0C0M m= VV DOD/v2er-Drive 10% 850 units 0% 0% -1.0 -0.5 0.0 0.5 1.0 -3 -1.5 0 1.5 3 Prop. Delay Skew (µs) Prop. Delay Skew (ns) FIGURE 2-43: Propagation Delay Skew. FIGURE 2-46: Propagation Delay Skew. 90 90 VCM = VSS MCP65R41 VCM = VSS MCP65R46 85 VDD = 1.8V to 5.5V 85 VDD = 1.8V to 5.5V B)80 B)80 d d RR (75 CPMSRRRR RR (75 PCSMRRRR S70 S70 P P R/65 R/65 R R CM5650 VVCDMD == -50.5.3VV to VDD + 0.3V CM5650 VIVnCDpMDu ==t -R50.e5.3fVeVr rteod VDD + 0.3V Input Referred 50 50 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 Temperature(°C) Temperature(°C) FIGURE 2-44: Common-Mode Rejection FIGURE 2-47: Common-Mode Rejection Ratio and Power Supply Rejection Ratio vs. Ratio and Power Supply Rejection Ratio vs. Temperature. Temperature. 40% 40% %) 30% V85D0D =u n1i.t8sV VASCtvDMg e.= v= - =00 ..032.V36 8tmo mV VV/VD/DV + 0.2V %) 30% VACvMg .= = - 00..30V5 tmoV V/VDD/2 VASCtvDMg e.= v= - =00 ..030.V33 tmmoV VV//VDVD + 0.3V ences ( 20% VAStCvDMg e.= v= V =-D0 0D./0.252 4t m om VVV/DV/DV+ 0.3V VASCtvDMg e.= v= - =00 ..135.V 1m 4toV m /VVVD/DV/2 ences ( 20% VACvMg .=S = tVD 0De.D0v/22 = mt o0V .V4/V6D Dm+ V0/.V3V urr urr StDev = 0.25 mV/V c c Oc 10% Oc 10% VDD = 5.5V 850 units 0% 0% -5 -4 -3 -2 -1 0 1 2 3 4 5 -2.5 -2.0 -1.5 -1.0-0.5 0.0 0.5 1.0 1.5 2.0 2.5 CMRR (mV/V) CMRR (mV/V) FIGURE 2-45: Common-Mode Rejection FIGURE 2-48: Common-Mode Rejection Ratio. Ratio. DS22269A-page 14  2010 Microchip Technology Inc.

MCP65R41/6 Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = GND, R = 100k to V /2 (MCP65R41 only), R = 2.74k to V /2 (MCP65R46 only) and C = 50pF. L DD Pull-Up DD L 1000 30% VCM = VSS 25% Avg. = -127.9 µV/V 100 %) StDev = 99.88 µV/V pA) 10 IB ces ( 20% 3588 units (B en 15% & I 1 |IOS| urr OS cc 10% I 0.1 O 5% 0.01 0% 25 50 75 100 125 -500 -250 0 250 500 Temperature (°C) PSRR (µV/V) FIGURE 2-49: Input Offset Current and FIGURE 2-52: Power Supply Rejection Input Bias Current vs. Temperature. Ratio. 1000 1.235 100 IB @ TA = +125°C VDD = 5.5V 1.230 IREF = 0A 1.225 A) IB @ TA = +85°C 1.220 TA = +85°C & I (pSB 101 |IOS| @ TA = +125°C V (V)REF111...222011505 TA = +25°C IO 1.200 TA = -40°C 0.1 1.195 TA = +125°C 1.190 |IOS| @ TA = +85°C 0.01 1.185 0.0 1.0 2.0 3.0 4.0 5.0 6.0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCM (V) VDD (V) FIGURE 2-50: Input Offset Current and FIGURE 2-53: V vs. V . REF DD Input Bias Current vs. Common-Mode Input Voltage vs. Temperature. 1E1+01m0 2.45 1E+10m9 A)1E1+000µ8 2.43 IREF = 0A ut Current (1111EEEE1++++01100000010n4567nµµ TA= -40°C V (V)REF 22..3491 TTAA == ++8255°°CC Inp111EEE1+++01001000ppn123 TTTAAA=== +++1282555°°CC°C 2.37 TTAA == +-4102°5C°C 1E+10p0 2.35 -0.8 -0.6 -0.4 -0.2 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Input Voltage (V) VDD (V) FIGURE 2-51: Input Bias Current vs. FIGURE 2-54: V vs. V . REF DD Input Voltage vs. Temperature.  2010 Microchip Technology Inc. DS22269A-page 15

MCP65R41/6 Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = GND, R = 100k to V /2 (MCP65R41 only), R = 2.74k to V /2 (MCP65R46 only) and C = 50pF. L DD Pull-Up DD L 1.235 1.235 1.230 VDD = 1.8V 1.230 V = 1.8V 1.225 1.225 DD 1.220 TA = +85°C 1.220 Temp. Co. = 27ppm V (V)REF111...222011505 TA = +25°C (V)REF 111...222011505 11..129050 TTAA == -+4102°5C°C V 11..129050 VTeDDm=p .5 C.5oV. = 22ppm 1.190 1.190 1.185 1.185 -0.5 -0.3 -0.1 0.1 0.3 0.5 -50 -25 0 25 50 75 100 125 Temperature (°C) I (µA) REF FIGURE 2-55: V vs. I over FIGURE 2-58: V vs. Temperature. REF REF REF Temperature. 2.45 1.235 V = 5.5V 1.230 VDD = 5.5V 2.43 TeDDmp. Co. = 23ppm 1.225 1.220 TA = +85°C V) 1.215 TA = +25°C V) 2.41 V (REF 111...222001050 TA = -40°C V (REF 2.39 1.195 TA = +125°C 2.37 1.190 1.185 2.35 -0.5 -0.3 -0.1 0.1 0.3 0.5 -50 -25 0 25 50 75 100 125 I (µA) Temperature (°C) REF FIGURE 2-56: V vs. I over FIGURE 2-59: V vs. Temperature. REF REF REF Temperature. 20.0 2.45 VREF = 1.21V VDD = 5.5V 15.0 2.43 10.0 V (V)REF 22..3491 TTAA == ++8255°°CC I (mA)SC -055...000 SSoinukricnigng TA = -40°C -10.0 2.37 TA = +125°C -15.0 2.35 -20.0 -0.5 -0.3 -0.1 0.1 0.3 0.5 1.5 2.5 3.5 4.5 5.5 I (µA) V (V) REF DD FIGURE 2-57: V vs. I over FIGURE 2-60: Short Circuit Current vs. REF REF Temperature. V . DD DS22269A-page 16  2010 Microchip Technology Inc.

MCP65R41/6 Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = GND, R = 100k to V /2 (MCP65R41 only), R = 2.74k to V /2 (MCP65R46 only) and C = 50pF. L DD Pull-Up DD L 50% %)40% VVADRvDEgF .= == 1 1.08..20V16V% VVADRvDEgF .= == 5 10.5..20V12V% es (30% 850 units 850 units c n e urr20% c c O10% 0% 2.0% 1.2% 0.4% -0.4% -1.2% -2.0% V (mV) TOL FIGURE 2-61: Reference Voltage Tolerance. 50% VDD = 5.5V 40% VREF = 2.4V %) Avg. = -0.22% es (30% 850 units c n e urr20% c c O10% 0% 2.0% 1.2% 0.4% -0.4% -1.2% -2.0% V (mV) TOL FIGURE 2-62: Reference Voltage Tolerance.  2010 Microchip Technology Inc. DS22269A-page 17

MCP65R41/6 NOTES: DS22269A-page 18  2010 Microchip Technology Inc.

MCP65R41/6 3.0 PIN DESCRIPTIONS Descriptions of the pins are listed in Table3-1. TABLE 3-1: PIN FUNCTION TABLE MCP65R41/6 Symbol Description SOT23-6 1 OUT Digital Output 2 V Ground SS 3 V + Non-inverting Input IN 4 V – Inverting Input IN 5 V Reference Voltage Output REF 6 V Positive Power Supply DD 3.1 Analog Inputs 3.4 Power Supply (V and V ) SS DD The comparator non-inverting and inverting inputs are The positive power supply pin (V ) is 1.8V to 5.5V DD high-impedance CMOS inputs with low bias currents. higher than the negative power supply pin (V ). For SS normal operation, the other pins are at voltages 3.2 Digital Outputs between VSS and VDD. Typically, these parts are used in a single (positive) The comparator outputs are CMOS/TTL compatible supply configuration. In this case, V is connected to push-pull and open-drain digital outputs. The push-pull SS ground and V is connected to the supply. V will is designed to directly interface to a CMOS/TTL com- DD DD need a local bypass capacitor (typically 0.01µF to patible pin while the open-drain output is designed for 0.1µF) within 2mm of the V pin. These can share a level shifting and wired-OR interfaces. DD bulk capacitor with the nearby analog parts (within 100mm), but it is not required. 3.3 Analog Outputs The V Output pin outputs a reference voltage of REF 1.21V or 2.4V.  2010 Microchip Technology Inc. DS22269A-page 19

MCP65R41/6 NOTES: DS22269A-page 20  2010 Microchip Technology Inc.

MCP65R41/6 4.0 APPLICATIONS INFORMATION 4.1.2 INPUT VOLTAGE AND CURRENT LIMITS The MCP65R41/6 family of Push-Pull and Open-Drain output comparators are fabricated on Microchip’s state- The ESD protection on the inputs can be depicted as of-the-art CMOS process. They are suitable for a wide shown in Figure4-2. This structure was chosen to range of high-speed applications requiring low power protect the input transistors, and to minimize the input consumption. bias current (IB). The input ESD diodes clamp the inputs when trying to go more than one diode drop below V . They also clamp any voltages that go too 4.1 Comparator Inputs SS far above V ; their breakdown voltage is high enough DD to allow a normal operation, and low enough to bypass 4.1.1 NORMAL OPERATION the ESD events within the specified limits. The input stage of this family of devices uses three differential input stages in parallel: one operates at low input voltages, one at high input voltages, and one at V Bond DD mid input voltages. With this topology, the input voltage Pad range is 0.3V above V and 0.3V below V , while DD SS providing low offset voltage throughout the Common mode range. The input offset voltage is measured at Bond Input Bond V + V – both VSS - 0.3V and VDD + 0.3V to ensure proper IN Pad Stage Pad IN operation. The MCP65R41/6 family has internally-set hysteresis VHYST that is small enough to maintain input offset V Bond accuracy, and large enough to eliminate the output SS Pad chattering caused by the comparator’s own input noise voltage E . Figure4-1 depicts this behavior. Input FIGURE 4-2: Simplified Analog Input ESD NI offset voltage (V ) is the center (average) of the Structures. OS (input-referred) low-high and high-low trip points. Input In order to prevent damage and/or improper operation hysteresis voltage (V ) is the difference between HYST of these comparators, the circuit they are connected to the same trip points. limit the currents (and voltages) at the V + and V – IN IN pins (see Absolute Maximum Ratings†). Figure4-3 9 30 shows the recommended approach to protect these 8 VDD = 5.0V 25 inputs. The internal ESD diodes prevent the input pins Output Voltage (V) 01234567 VOUT HysVteINr-esis ---0511211505050put Voltage (10 mV/div) (topWlihVmiunehItNi tero +(etnVfh s taIiehiNmsn e+ctdpo ui lnreVarsrpmnI eNRudne–t 1 tn)p Va ttihfenInrNrod.do –m D au)R isg o2fg hrsd ool hieDmimnos1giw tD gatnt1hono, e odiarn e npgDfsdao i2 rsstD. otsbo2oieb r psllofer aRew rcv 1 ueg aarnrbrnoeto duntvh ntRe edd 2 ,riV naaaDpwlnsDunodt. -1 -20In V -2 -25 DD VPU -3 0 100 200 300 Tim400e (105000 ms600/div)700 800 900 1000-30 D 1 R * FIGURE 4-1: The MCP65R41/6 PU V1 + Comparators’ Internal Hysteresis Eliminates R1 VOUT Output Chatter Caused by Input Noise Voltage. – D 2 V 2 R R 2 3 V –(minimum expected V ) SS 1 R  1 2mA V –(minimum expected V ) SS 2 R  2 2mA * Pull-up resistor required for the MCP65R46 only. FIGURE 4-3: Protecting the Analog Inputs.  2010 Microchip Technology Inc. DS22269A-page 21

MCP65R41/6 It is also possible to connect the diodes to the left of the 4.3.1 NON-INVERTING CIRCUIT resistors R and R . In this case, the currents through 1 2 Figure4-4 shows a non-inverting circuit for single- the diodes D and D need to be limited by some other 1 2 supply applications using just two resistors. The mechanism. The resistor then serves as an in-rush cur- resulting hysteresis diagram is shown in Figure4-5. rent limiter; the DC current into the input pins (V + and IN V –) should be very small. IN V A significant amount of current can flow out of the REF inputs when the Common mode voltage (VCM) is below V VPU DD ground (V ); see Figure4-3. The applications that are SS high impedance may need to limit the usable voltage R * V - PU range. REF V OUT 4.1.3 PHASE REVERSAL + The MCP65R41/6 comparator family uses CMOS tran- sistors at the input. They are designed to prevent V phase inversion when the input pins exceed the supply IN voltages. Figure2-3 shows an input voltage exceeding R1 RF both supplies with no resulting phase inversion. * Pull-up resistor required for the MCP65R46 only. 4.2 Push-Pull Output FIGURE 4-4: Non-inverting Circuit with Hysteresis for Single-Supply. The push-pull output is designed to be compatible with CMOS and TTL logic, while the output transistors are configured to give a rail-to-rail output performance. V OUT They are driven with circuitry that minimizes any V switching current (shoot-through current from supply- DD V to-supply) when the output is transitioned from high-to- OH low, or from low-to-high (see Figures2-18 and 2-19 for High-to-Low Low-to-High more information). 4.3 Externally Set Hysteresis VOL VIN V SS V V V V A greater flexibility in selecting the hysteresis (or the SS THL TLH DD input trip points) is achieved by using external resistors. FIGURE 4-5: Hysteresis Diagram for the Hysteresis reduces output chattering when one input is Non-Inverting Circuit. slowly moving past the other. It also helps in systems where it is best not to cycle between high and low The trip points for Figures4-4 and4-5 are: states too frequently (e.g., air conditioner thermostatic control). Output chatter also increases the dynamic EXAMPLE 4-1: supply current.  R1 R1 V = V 1+------- –V ------- TLH REF RF OLRF  R1 R1 V = V 1+------- –V ------- THL REF RF OHRF Where: V = trip voltage from low to high TLH V = trip voltage from high to low THL DS22269A-page 22  2010 Microchip Technology Inc.

MCP65R41/6 4.3.2 INVERTING CIRCUIT By using this simplified circuit, the trip voltage can be calculated using the following equation: Figure4-6 shows an inverting circuit for single-supply using three resistors. The resulting hysteresis diagram EQUATION 4-1: is shown in Figure4-7.  R  R 23  F  VDD VPU VTHL = VOHR----2---3----+-----R----F--- +V23R----2---3----+-----R----F-- VIN RPU* V = V --------R----2--3--------- +V --------R----F---------- VREF V TLH OLR23+RF 23R23+RF OUT Where: R 2 V = trip voltage from low to high TLH V = trip voltage from high to low THL R R F 3 Figures2-23 and 2-26 can be used to determine the typical values for V and V . OH OL * Pull-up resistor required for the MCP65R46 only. 4.4 Bypass Capacitors FIGURE 4-6: Inverting Circuit with With this family of comparators, the power supply pin Hysteresis. (V for single supply) should have a local bypass DD capacitor (i.e., 0.01µF to 0.1µF) within 2mm for good edge rate performance. V OUT V DD 4.5 Capacitive Loads V OH Low-to-High High-to-Low 4.5.1 OUT PIN Reasonable capacitive loads (e.g., logic gates) have VOL VIN little impact on the propagation delay (see Figure2-34). V The supply current increases with the increasing toggle SS V V V V frequency (Figure2-22), especially with higher SS TLH THL DD capacitive loads. The output slew rate and propagation FIGURE 4-7: Hysteresis Diagram for the delay performance will be reduced with higher capaci- Inverting Circuit. tive loads. In order to determine the trip voltages (V and V ) THL TLH 4.5.2 V PIN for the circuit shown in Figure4-6, R and R can be REF 2 3 simplified to the Thevenin equivalent circuit with The reference output is designed to interface to the respect to V , as shown in Figure4-8: comparator input pins, either directly or with some REF resistive network, such as voltage divider network, with V minimal capacitive load. The recommended capacitive PU VDD load is 200pF (typical). Capacitive loads greater than 2000pF may cause the V output to oscillate at R * REF - PU power up. V OUT + V SS V 23 R R 23 F Where: R R R = --------2------3----- 23 R +R 2 3 R 3 V = -------------------V 23 R +R REF 2 3 * Pull-up resistor required for the MCP65R46 only. FIGURE 4-8: Thevenin Equivalent Circuit.  2010 Microchip Technology Inc. DS22269A-page 23

MCP65R41/6 4.6 PCB Surface Leakage V DD In applications where the low input bias current is V REF critical, the Printed Circuit Board (PCB) surface MCP6041 V leakage effects need to be considered. Surface PU leakage is caused by humidity, dust or other type of VREF V DD contamination on the board. Under low humidity R PU conditions, a typical resistance between nearby traces V is 1012. A 5V difference would cause 5pA of current IN to flow. This is greater than the MCP65R41/6 family’s R1 R2 VOUT bias current at +25°C (1pA, typical). VREF MCP65R46 The easiest way to reduce the surface leakage is to use a guard ring around the sensitive pins (or traces). The FIGURE 4-10: Precise Inverting guard ring is biased at the same voltage as the Comparator. sensitive pin. An example of this type of layout is shown in Figure4-9. 4.7.2 BISTABLE MULTI-VIBRATOR A simple bistable multi-vibrator design is shown in IN- IN+ Figure4-11. V needs to be between ground and the V REF SS maximum comparator internal V of 2.4V to achieve REF oscillation. The output duty cycle changes with V . REF R R 1 2 V REF V DD V OUT Guard Ring MCP65R41 FIGURE 4-9: Example Guard Ring Layout for Inverting Circuit. 1. Inverting Configuration (Figures4-6 and4-9): C R 1 3 a) Connect the guard ring to the non-inverting FIGURE 4-11: Bistable Multi-Vibrator. input pin (V +). This biases the guard ring IN to the same reference voltage as the 4.7.3 OVER TEMPERATURE comparator (e.g., V /2 or ground). DD PROTECTION CIRCUIT b) Connect the inverting pin (V –) to the input IN pad without touching the guard ring. The MCP65R41 device can be used as an over temperature protection circuit using a thermistor. The 2. Non-inverting Configuration (Figure4-4): 2.4VV can be used as stable reference to the a) Connect the non-inverting pin (V +) to the REF IN thermistor, the alert threshold and hysteresis threshold. input pad without touching the guard ring. This is ideal for battery powered applications, where b) Connect the guard ring to the inverting input the change in temperature and output toggle pin (VIN–). thresholds would remain fixed as battery voltage decays over time. 4.7 Typical Applications VREF 4.7.1 PRECISE COMPARATOR Some applications require a higher DC precision. An R4 VREFVDD VPU easy way to solve this problem is to use an amplifier RPU* (such as the MCP6041, a 600nA low power and VREF VOUT 14kHz bandwidth op amp) to gain-up the input signal Thermistor before it reaches the comparator. Figure4-10 shows R2 an example of this approach, which also level shifts to V using the Open-Drain option, MCP65R46. PU R3 RF * Pull-up resistor required for the MCP65R46 only. FIGURE 4-12: Over Temperature Alert Circuit. DS22269A-page 24  2010 Microchip Technology Inc.

MCP65R41/6 5.0 PACKAGING INFORMATION 5.1 Package Marking Information 6-Lead SOT-23 Example Part Number Code XXNN MCP65R41T-1202E/CHY HVNN HV25 MCP65R41T-2402E/CHY HWNN MCP65R46T-1202E/CHY HXNN MCP65R46T-2402E/CHY HYNN Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2010 Microchip Technology Inc. DS22269A-page 25

MCP65R41/6 6-Lead Plastic Small Outline Transistor (CHY) [SOT-23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging b N 4 E E1 PIN1IDBY LASERMARK 1 2 3 e e1 D A A2 c φ L A1 L1 Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 6 Pitch e 0.95 BSC Outside Lead Pitch e1 1.90 BSC Overall Height A 0.90 – 1.45 Molded Package Thickness A2 0.89 – 1.30 Standoff A1 0.00 – 0.15 Overall Width E 2.20 – 3.20 Molded Package Width E1 1.30 – 1.80 Overall Length D 2.70 – 3.10 Foot Length L 0.10 – 0.60 Footprint L1 0.35 – 0.80 Foot Angle (cid:3) 0° – 30° Lead Thickness c 0.08 – 0.26 Lead Width b 0.20 – 0.51 Notes: 1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.127 mm per side. 2. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. MicrochipTechnologyDrawingC04-028B DS22269A-page 26  2010 Microchip Technology Inc.

MCP65R41/6 6-Lead Plastic Small Outline Transistor (CHY) [SOT-23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2010 Microchip Technology Inc. DS22269A-page 27

MCP65R41/6 NOTES: DS22269A-page 28  2010 Microchip Technology Inc.

MCP65R41/6 APPENDIX A: REVISION HISTORY Revision A (December 2010) • Original Release of this Document.  2010 Microchip Technology Inc. DS22269A-page 29

MCP65R41/6 NOTES: DS22269A-page 30  2010 Microchip Technology Inc.

MCP65R41/6 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Examples: PART NO. X -XX XX X /XX a)MCP65R41T-1202E/CHY: Push-Pull Output, Device Tape an d Reference Reference Temperature Package 1.2VREF, Voltage Tolerance Range Tape and Reel, 6LD SOT-23 Pkg. b)MCP65R41T-2402E/CHY: Push-Pull Output, 2.4VREF, Device MCP65R41T: Push-pull Output Comparator Tape and Reel, MCP65R46T: Open-drain Output Comparator 6LD SOT-23 Pkg. Reference Voltage 12 = 1.21V (typical) Initial Reference Voltage a)MCP65R46T-1202E/CHY: Open-Drain Output, 24 = 2.4V (typical) Initial Reference Voltage 1.2VREF, Tape and Reel, 6LD SOT-23 Pkg. Reference Tolerance 02 = 2% Reference Voltage Tolerance b)MCP65R46T-2402E/CHY: Open-Drain Output, 2.4VREF, Tape and Reel, Temperature Range E = -40C to +125C (Extended) 6LD SOT-23 Pkg. Package CHY = Plastic Small OutlineTransistor, 6-Lead  2010 Microchip Technology Inc. DS22269A-page 31

MCP65R41/6 NOTES: DS22269A-page 32  2010 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. PIC32 logo, rfPIC and UNI/O are registered trademarks of MICROCHIP MAKES NO REPRESENTATIONS OR Microchip Technology Incorporated in the U.S.A. and other WARRANTIES OF ANY KIND WHETHER EXPRESS OR countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MXDEV, MXLAB, SEEVAL and The Embedded Control QUALITY, PERFORMANCE, MERCHANTABILITY OR Solutions Company are registered trademarks of Microchip FITNESS FOR PURPOSE. Microchip disclaims all liability Technology Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, CodeGuard, devices in life support and/or safety applications is entirely at dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, the buyer’s risk, and the buyer agrees to defend, indemnify and ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial hold harmless Microchip from any and all damages, claims, Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified suits, or expenses resulting from such use. No licenses are logo, MPLIB, MPLINK, mTouch, Omniscient Code conveyed, implicitly or otherwise, under any Microchip Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, intellectual property rights. PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2010, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-60932-781-1 Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2010 Microchip Technology Inc. DS22269A-page 33

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: MCP65R41T-1202E/CHY MCP65R41T-2402E/CHY MCP65R46T-2402E/CHY