M MCP6546/7/8/9 Open-Drain Output Sub-Microamp Comparators Features Description • Low Quiescent Current: 600nA/comparator (typ.) The Microchip Technology Inc. MCP6546/7/8/9 family • Rail-to-Rail Input: V - 0.3V to V + 0.3V of comparators is offered in single (MCP6546), single SS DD • Open-Drain Output: V ≤10V with chip select (MCP6548), dual (MCP6547) and quad OUT (MCP6549) configurations. The outputs are open-drain • Propagation Delay 4µs (typ.) and are capable of driving heavy DC or capacitive • Wide Supply Voltage Range: 1.6V to 5.5V loads. • Single available in SOT-23-5, SC-70-5 packages These comparators are optimized for low power, • Available in Single, Dual and Quad single-supply application with greater than rail-to-rail • Chip Select (CS) with MCP6548 input operation. The output limits supply current surges • Low Switching Current and dynamic power consumption while switching. The open-drain output of the MCP6546/7/8/9 family can be • Internal Hysteresis: 3.3mV (typ.) used as a level-shifter for up to 10V using a pull-up • Industrial Temperature: -40°C to +85°C resistor. It can also be used as a wired-OR logic. The Typical Applications internal Input hysteresis eliminates output switching due to internal noise voltage, reducing current draw. • Laptop Computers These comparators operate with a single-supply • Mobile Phones voltage as low as 1.6V and draw less than 1µA/ comparator of quiescent current. • Metering Systems • Hand-held Electronics The related MCP6541/2/3/4 family of comparators from Microchip has a push-pull output that supports rail-to- • RC Timers rail output swing and interfaces with CMOS/TTL logic. • Alarm and Monitoring Circuits • Windowed Comparators • Multi-vibrators Related Devices • CMOS/TTL-Compatible Output: MCP6541/2/3/4 Package Types MCP6549 MCP6546 MCP6546-R MCP6547 PDIP, SOIC, TSSOP PDIP, SOIC, MSOP SOT-23-5 PDIP, SOIC, MSOP NC 1 8 NC OUT 1 5 VSS OUTA 1 8 VDD OUTA 1 14 OUTD VIN– 2 - 7 VDD VDD 2 + - VINA– 2 - + 7 OUTB VINA– 2 - + + - 13 VIND– VIN+ 3 + 6 OUT VIN+ 3 4 VIN– VINA+ 3 + - 6 VINB– VINA+ 3 12 VIND+ VSS 4 5 NC VSS 4 5 VINB+ VDD 4 11 VSS MCP6546 MCP6548 VINB+ 5 10 VINC+ SOT-23-5, SC-70-5 PDIP, SOIC, MSOP VINB– 6 - + + - 9 VINC– OUTB 7 8 OUTC OUT 1 5 VDD NC 1 8 CS VSS 2 VIN– 2 - 7 VDD + - VIN+ 3 4 VIN– VIN+ 3 + 6 OUT VSS 4 5 NC  2003 Microchip Technology Inc. DS21714C-page 1

MCP6546/7/8/9 1.0 ELECTRICAL † Notice: Stresses above those listed under “Maximum Rat- ings” may cause permanent damage to the device. This is a CHARACTERISTICS stress rating only and functional operation of the device at those or any other conditions above those indicated in the 1.1 Absolute Maximum Ratings † operational listings of this specification is not implied. Expo- sure to maximum rating conditions for extended periods may V - V ..............................................................7.0V DD SS affect device reliability. Open-Drain output.....................................V +10.5V SS PIN FUNCTION TABLE All inputs and outputs ...........V –0.3V to V +0.3V SS DD Difference Input voltage ............................|V - V | NAME FUNCTION DD SS V +, V +, V +, V +, V + Non-Inverting Inputs Output Short-Circuit Current .......................continuous IN INA INB INC IND V –, V –, V –, V –, V – Inverting Inputs Current at Input Pins .........................................±2mA IN INA INB INC IND V Positive Power Supply Current at Output and Supply Pins ..................±30mA DD V Negative Power Supply Storage temperature..........................-65°C to +150°C SS OUT, OUTA, OUTB, OUTC, Outputs Maximum Junction Temperature (T )...............+150°C J OUTD ESD protection on all pins (HBM;MM)..........4kV;200V CS Chip Select NC Not Connected DC CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, V = +1.6V to +5.5V, V = GND, T = 25°C, V + = V /2, V – = V , DD SS A IN DD IN SS R =2.74kΩ to V = V (Refer to Figure1-3). PU PU DD Parameters Sym Min Typ Max Units Conditions Power Supply Supply Voltage V 1.6 — 5.5 V DD Quiescent Current per comparator I 0.3 0.6 1 µA I = 0 Q OUT Input Input Voltage Range V V − 0.3 — V + 0.3 V CMR SS DD Common Mode Rejection Ratio CMRR 55 70 — dB V = 5V, V = -0.3V to 5.3V DD CM Common Mode Rejection Ratio CMRR 50 65 — dB V = 5V, V = 2.5V to 5.3V DD CM Common Mode Rejection Ratio CMRR 55 70 — dB V = 5V, V = -0.3V to 2.5V DD CM Power Supply Rejection Ratio PSRR 63 80 — dB V = V CM SS Input Offset Voltage V -7.0 ±1.5 +7.0 mV V = V (Note1) OS CM SS Drift with Temperature ∆V /∆T — ±3 — µV/°C T = -40°C to +85°C, V = V OS A A CM SS Input Hysteresis Voltage V 1.5 3.3 6.5 mV V = V (Note1) HYST CM SS Drift with Temperature ∆V /∆T — 10 — µV/°C T = -40°C to +25°C, V = V HYST A A CM SS Drift with Temperature ∆V /∆T — 5 — µV/°C T = +25°C to +85°C, V = V HYST A A CM SS Input Bias Current I — 1 — pA V =V B CM SS Over Temperature I — — 100 pA T = -40°C to +85°C, V = V (Note3) B A CM SS Input Offset Current I — ±1 — pA V =V OS CM SS Common Mode Input Impedance Z — 1013||4 — Ω||pF CM Differential Input Impedance Z — 1013||2 — Ω||pF DIFF Open-Drain Output Output Pull-Up Voltage V V — 10 V (Note2) PU DD High-Level Output Current I -100 — — nA V = 1.6V to 5.5V, V = 10V (Note2) OH DD PU Low-Level Output Voltage V V — V + 0.2 V I = 2mA, V = V = 5V OL SS SS OUT PU DD Short-Circuit Current I — ±50 — mA V = V = 5.0V (Note2) SC PU DD Output Pin Capacitance C — 8 — pF OUT Note 1: The input offset voltage is the center of the input-referred trip points. The input hysteresis is the difference between the input-referred trip points. 2: Do not short the output above V + 10V. Limit the output current to Absolute Maximum Rating of 30mA. The SS comparator does not function properly when V < V . PU DD 3: Input bias current overtemperature is not tested for the SC-70-5 package. DS21714C-page 2  2003 Microchip Technology Inc.

MCP6546/7/8/9 AC CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, V = +1.6V to +5.5V, V = GND, T = 25°C, V + = V /2, DD SS A IN DD Step = 200mV, Overdrive = 100mV, R =2.74kΩ to V = V , and C = 36pF (Refer to Figure1-2 and Figure1-3). PU PU DD L Parameters Sym Min Typ Max Units Conditions Fall Time t — 0.7 — µs (Note1) F Propagation Delay (High-to-Low) t — 4.0 8.0 µs PHL Propagation Delay (Low-to-High) t — 3.0 8.0 µs (Note1) PLH Propagation Delay Skew t — -1.0 — µs (Notes1 and2) PDS Maximum Toggle Frequency f — 225 — kHz V = 1.6V MAX DD f — 165 — kHz V = 5.5V MAX DD Input Noise Voltage E — 200 — µV 10Hz to 100kHz N P-P Note 1: t and t depend on the load (R and C ); these specifications are valid for the indicated load only. R PLH L L 2: Propagation Delay Skew is defined as: t = t - t . PDS PLH PHL SPECIFICATIONS FOR MCP6548 CHIP SELECT Electrical Specifications: Unless otherwise indicated, V = +1.6V to +5.5V, V = GND, T = 25°C, V + = V /2, V – = V , DD SS A IN DD IN SS R =2.74kΩ to V = V , and C = 36pF (Refer to Figures1-1 and1-3). PU PU DD L Parameters Sym Min Typ Max Units Conditions CS Low Specifications CS Logic Threshold, Low V V — 0.2V V IL SS DD CS Input Current, Low I — 5 — pA CS = V CSL SS CS High Specifications CS Logic Threshold, High V 0.8V — V V IH DD DD CS Input Current, High I — 1 — pA CS = V CSH DD CS Input High, V Current I — 18 — pA CS = V DD DD DD CS Input High, GND Current I — -20 — pA CS = V SS DD Comparator Output Leakage I — 1 — pA V = V +10V O(LEAK) OUT SS CS Dynamic Specifications CS Low to Comparator Output Low t — 2 50 ms CS = 0.2V to V = V /2, ON DD OUT DD Turn-on Time V – = V IN DD CS High to Comparator Output t — 10 — µs CS = 0.8V to V = V /2, OFF DD OUT DD High Z Turn-off Time V – = V IN DD CS Hysteresis V — 0.6 — V V = 5V CS_HYST DD CS VIL VIH VIN– 100mV t t ON OFF VIN+ = VDD/2 100mV tPHL VOUT Hi-Z Hi-Z t PLH V OH I -20pA, typ. -0.6µA, typ. -20pA, typ. SS V OUT 1pA, typ. 1pA, typ. VOL VOL I CS FIGURE 1-1: Timing Diagram for the CS FIGURE 1-2: Propagation Delay Timing pin on the MCP6548. Diagram.  2003 Microchip Technology Inc. DS21714C-page 3

MCP6546/7/8/9 TEMPERATURE SPECIFICATIONS Electrical Specifications: Unless otherwise indicated, V = +1.6V to +5.5V and V = GND. DD SS Parameters Sym Min Typ Max Units Conditions Temperature Ranges Specified Temperature Range T -40 — +85 °C A Operating Temperature Range T -40 — +125 °C Note A Storage Temperature Range T -65 — +150 °C A Thermal Package Resistances Thermal Resistance, 5L-SC-70 θ — 331 — °C/W JA Thermal Resistance, 5L-SOT-23 θ — 256 — °C/W JA Thermal Resistance, 8L-PDIP θ — 85 — °C/W JA Thermal Resistance, 8L-SOIC θ — 163 — °C/W JA Thermal Resistance, 8L-MSOP θ — 206 — °C/W JA Thermal Resistance, 14L-PDIP θ — 70 — °C/W JA Thermal Resistance, 14L-SOIC θ — 120 — °C/W JA Thermal Resistance, 14L-TSSOP θ — 100 — °C/W JA Note: The MCP6546/7/8/9 operates over this extended temperature range, but with reduced performance. In any case, the Junction Temperature (T ) must not exceed the absolute maximum specification of +150°C. J 1.2 Test Circuit Configuration This test circuit configuration is used to determine the AC and DC specifications. V DD V = V PU DD 200kΩ R MCP654X PU 2.74kΩ 200kΩ VOUT 100kΩ 36pF V = 0V V = V SS IN SS FIGURE 1-3: AC and DC Test circuit for the open- drain output comparators. DS21714C-page 4  2003 Microchip Technology Inc.

MCP6546/7/8/9 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, V = +1.6V to +5.0V, V = GND, T = +25°C, V + = V /2, V – = GND, DD SS A IN DD IN R = 2.74kΩ to V =V , and C = 36pF. PU PU DD L 14% 18% ences 12% 1V2C0M0 = S VaSmSples ences1146%% 1V2C0M0 = S VaSmSples urr 10% urr12% c c Oc 8% Oc10% e of 6% e of 8% entag 4% entag 46%% erc 2% erc 2% P P 0% 0% -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2 5.6 6.0 Input Offset Voltage (mV) Input Hysteresis Voltage (mV) FIGURE 2-1: Input Offset Voltage FIGURE 2-4: Input Hysteresis Voltage Histogram at V =V . Histogram at V =V . CM SS CM SS 16% 26% s 1200 Samples s24% 1200 Samples nce 14% VCM = VSS nce22% TA = 25°C to 85°C VCM = VSS urre 12% urre1280%% Occ 10% Occ1146%% TA = -40°C to 25°C of 8% of 12% ge 6% ge 10% enta 4% enta 68%% erc 2% erc 4% P P 2% 0% 0% -14-12-10 -8 -6 -4 -2 0 2 4 6 8 10 12 14 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Input Offset Voltage Drift (µV/°C) Input Hysteresis Voltage Drift (µV/°C) FIGURE 2-2: Input Offset Voltage Drift FIGURE 2-5: Input Hysteresis Voltage Histogram at V =V . Drift Histogram. CM SS 500 6.0 V) 400 VCM = VSS mV) 5.5 VCM = VSS Input Offset Voltage (µ ----4321123000000000000000 VVDDDD == 15..65VV put Hysteresis Voltage ( 2233445.......0505050 VVDDDD == 15..65VV n -500 I 1.5 -40 -20 0 20 40 60 80 -40 -20 0 20 40 60 80 Ambient Temperature (°C) Ambient Temperature (°C) FIGURE 2-3: Input Offset Voltage vs. FIGURE 2-6: Input Hysteresis Voltage vs. Ambient Temperature at V =V . Ambient Temperature at V =V . CM SS CM SS  2003 Microchip Technology Inc. DS21714C-page 5

MCP6546/7/8/9 Note: Unless otherwise indicated, V = +1.6V to +5.0V, V = GND, T = +25°C, V + = V /2, V – = GND, DD SS A IN DD IN R = 2.74kΩ to V =V , and C = 36pF. PU PU DD L 2.0 6.0 Voltage (mV) 0011....0505 VDD = 1.6V TA = 85°C s Voltage (mV) 4455....0505 VDD = 1.6V TTAA == 8255°°CC et esi 3.5 ut Offs --10..05 TTAA == -2450°°CC Hyster 23..50 Inp --21..05 Input 12..50 TA = -40°C 4 2 0 2 4 6 8 0 2 4 6 8 0 4 2 0 2 4 6 8 0 2 4 6 8 0 0. 0. 0. 0. 0. 0. 0. 1. 1. 1. 1. 1. 2. 0. 0. 0. 0. 0. 0. 0. 1. 1. 1. 1. 1. 2. - - - - Common Mode Input Voltage (V) Common Mode Input Voltage (V) FIGURE 2-7: Input Offset Voltage vs. FIGURE 2-10: Input Hysteresis Voltage vs. Common Mode Input Voltage at V = 1.6V. Common Mode Input Voltage at V =1.6V. DD DD 2.0 6.0 V) 1.5 VDD = 5.5V mV) 5.5 VDD = 5.5V Voltage (m 001...050 TA = 85°C s Voltage ( 445...050 TA = 85°C et esi 3.5 Input Offs ----2110....0505 TTAA = = - 4205°°CC Input Hyster 1223....5050 TTAA == -2450°°CC 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 0. 0. 0. 1. 1. 2. 2. 3. 3. 4. 4. 5. 5. 6. 0. 0. 0. 1. 1. 2. 2. 3. 3. 4. 4. 5. 5. 6. - - Common Mode Input Voltage (V) Common Mode Input Voltage (V) FIGURE 2-8: Input Offset Voltage vs. FIGURE 2-11: Input Hysteresis Voltage vs. Common Mode Input Voltage at V =5.5V. Common Mode Input Voltage at V =5.5V. DD DD 90 24 ed 22 TA = 85°C err 85 20 VDD = 5.5V RR; Input Ref(dB) 778050 PSRR, VIN+ = VSS, VDD = 1.6V to 5.5V Current (pA) 1111102468 Input Bias Current CMRR, PS 6605 CCMMRRCRRM,,R VVRIINN, ++V ==IN +--00 =..33 2VV. 5 ttVoo 5t2o..35 5VV.,,3 VVVDD, DDV =D=D 55 =..00 5VV.0V Input 2468 Input Offset Current 55 0 -40 -20 0 20 40 60 80 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Ambient Temperature (°C) Common Mode Input Voltage (V) FIGURE 2-9: CMRR, PSRR vs. Ambient FIGURE 2-12: Input Bias Current, Input Temperature at V = V . Offset Current vs. Common Mode Input Voltage CM SS at +85°C. DS21714C-page 6  2003 Microchip Technology Inc.

MCP6546/7/8/9 Note: Unless otherwise indicated, V = +1.6V to +5.0V, V = GND, T = +25°C, V + = V /2, V – = GND, DD SS A IN DD IN R = 2.74kΩ to V =V , and C = 36pF. PU PU DD L ut Current (pA) 1111122024680268 VVDCDM == 5V.D5DV Input Bias Current escent Current A/comparator) 00000.....34567 TTTAAA === +-+428055°°C°CC np 4 Qui(µ 0.2 I 2 Input Offset Current 0.1 0 -2 0.0 25 35 45 55 65 75 85 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Ambient Temperature (°C) Power Supply Voltage (V) FIGURE 2-13: Input Bias Current, Input FIGURE 2-16: Quiescent Current vs. Offset Current vs. Ambient Temperature. Power Supply Voltage. 0.7 0.7 V = 5.5 V VDD = 5.5V uiescent Current µA/comparator) 00000.....23456 VDDDD = 1.6 V uiescent Current µA/comparator)00000.....23456 SIQw deoeeps V nINo+t, iVnIcNl–u d=e V pDDu/l2l-uSpw reeespis tVoINr –c,u VrrINe+n =t VDD/2 Q( Q( 0.1 0.1 0.0 0.0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 -40 -20 0 20 40 60 80 0. 0. 0. 1. 1. 2. 2. 3. 3. 4. 4. 5. 5. 6. - Ambient Temperature (°C) Common Mode Input Voltage (V) FIGURE 2-14: Quiescent Current vs. FIGURE 2-17: Quiescent Current vs. Ambient Temperature vs. Power Supply Voltage. Common Mode Input Voltage at V = 5V. DD 0.7 50 VDD = 1.6V nt 45 Quiescent Current (µA/comparator)00000.....23456 SIQw deoeeps V nINo+t, iVnIcNl–u =d eV pDDu/l2l-uSpw reeespis tVoINr –c,u VrIrNe+n =t VDD/2 ut Short Circuit Curre(mA)122334505050 -IO-ISOC-SI,CO T,S ATC ,A= T = A+ =8+ 52-°45C0°C°C 0.1 utp 10 O 5 0.0 0 4 2 0 2 4 6 8 0 2 4 6 8 0 0. 0. 0. 0. 0. 0. 0. 1. 1. 1. 1. 1. 2. 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 - - Common Mode Input Voltage (V) Power Supply Voltage (V) FIGURE 2-15: Quiescent Current vs. FIGURE 2-18: Output Short-Circuit Current Common Mode Input Voltage at V = 1.6V. vs. Power Supply Voltage. DD  2003 Microchip Technology Inc. DS21714C-page 7

MCP6546/7/8/9 Note: Unless otherwise indicated, V = +1.6V to +5.0V, V = GND, T = +25°C, V + = V /2, V – = GND, DD SS A IN DD IN R = 2.74kΩ to V =V , and C = 36pF. PU PU DD L 0.8 1.0 droom (V) 00..67 VDD = 1.6V droom (V) 000...789 VDD = 5V.O5LVV-OVLS-SV, STSA, T=A 2 =5 °-C40°C Hea 0.5 VOL-VSS, TA = -40°C Hea 0.6 VOL-VSS, TA = 85°C ge 0.4 VOL-VSS, TA = +25°C ge 0.5 Output Volta 0000....0123 VOL-VSS, TA = +85°C Output Volta 00000.....01234 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0 2 4 6 8 10 12 14 16 18 20 22 Output Current (mA) Output Current (mA) FIGURE 2-19: Output Voltage Headroom FIGURE 2-22: Output Voltage Headroom vs. Output Current at V =1.6V. vs. Output Current at V =5.5V. DD DD 50% 65% ces 45% 410080 SmaVm Opvleesrdrive ces 5650%% 410080 SmaVm Opvleesrdrive ccurren 334050%%% VVDDC M= = 5 .V5DVD/2 ccurren 445050%%% VCM = VDD/2 O O 35% ge of 2205%% VDD = 1.6V ge of 2350%% VDD = 1.6V VDD = 5.5V Percenta 11055%%% Percenta 1120505%%%% 0% 0% 0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8 High-to-Low Propagation Delay (µs) Low-to-High Propagation Delay (µs) FIGURE 2-20: High-to-Low Propagation FIGURE 2-23: Low-to-High Propagation Delay Histogram. Delay Histogram. 50% 8 of Occurrences2334450505%%%%% VDD = 5.5V VDD = 1.6V41V00C80M Sm=a VVm DODp/vl2eesrdrive on Delay (µs) 4567 1V0C0M m= VV DOD/v2erdrive tPHL @ VDD = 5.5VtPHL @ VDD = 1.6V ntage 1250%% pagati 23 e10% o Perc 5% Pr 1 tPLH @ VDD = 5.5V t @ V = 1.6V 0% 0 PLH DD -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 -40 -20 0 20 40 60 80 Propagation Delay Skew (µs) Ambient Temperature (°C) FIGURE 2-21: Propagation Delay Skew FIGURE 2-24: Propagation Delay vs. Histogram. Ambient Temperature. DS21714C-page 8  2003 Microchip Technology Inc.

MCP6546/7/8/9 Note: Unless otherwise indicated, V = +1.6V to +5.0V, V = GND, T = +25°C, V + = V /2, V – = GND, DD SS A IN DD IN R = 2.74kΩ to V =V , and C = 36pF. PU PU DD L 14 100 13 VCM = VDD/2 VCM = VDD/2 µs) 1112 tPHL @ 10 mV Overdrive µs) y ( 10 y ( tPHL @ VDD = 5.5V ela 9 ela gation D 5678 tPLH @tPL 1H 0@ m 1V0 0O mveVrd Orivveerdrive gation D 10 tPLH @ VDD = 1.6V a 4 a p p Pro 23 t @ 100 mV Overdrive Pro tPLH @ VDD = 5.5V 1 PLH tPHL @ VDD = 1.6V 0 1 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1 10 100 1000 Power Supply Voltage (V) Input Overdrive (mV) FIGURE 2-25: Propagation Delay vs. FIGURE 2-28: Propagation Delay vs. Input Power Supply Voltage. Overdrive. 8 8 VDD = 1.6V VDD = 5.5V s) 7 100 mV Overdrive s) 7 100 mV Overdrive µ µ y ( 6 y ( 6 a a Del 5 Del 5 tPHL n 4 n 4 atio 3 tPHL atio 3 g g Propa 12 tPLH Propa 12 tPLH 0 0 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Common Mode Input Voltage (V) Common Mode Input Voltage (V) FIGURE 2-26: Propagation Delay vs. FIGURE 2-29: Propagation Delay vs. Common Mode Input Voltage at V = 1.6V. Common Mode Input Voltage at V = 5.5V. DD DD y (µs) 111246800000 1V0C0M m= VV DOD/v2erdrive tPLH @ VDD = 5.5V mparator) 10 1VID0CD0M d m=o eVVs DO Dn/v2oetr idnrcivluede pull-up resistor current Dela 120 tPLH @ VDD = 1.6V A/co VDD = 5.5 V Propagation 10246800000 tPHL @ VDD = 1.6VtPHL @ VDD = 5.5V ply Current (µ 1 VDD = 1.6 V p 0 Su 0.1 0 10 20 30 40 50 60 70 80 90 0.1 1 10 100 Load Capacitance (nF) Toggle Frequency (kHz) FIGURE 2-27: Propagation Delay vs. Load FIGURE 2-30: Supply Current vs. Toggle Capacitance. Frequency.  2003 Microchip Technology Inc. DS21714C-page 9

MCP6546/7/8/9 Note: Unless otherwise indicated, V = +1.6V to +5.0V, V = GND, T = +25°C, V + = V /2, V – = GND, DD SS A IN DD IN R = 2.74kΩ to V =V , and C = 36pF. PU PU DD L onDelay(µs) 45678 VVVICINNM–+===V1VD0CD0M/2mVOverdtPrLivHe@VDD=1.6VtPLH@VDD=5.5V utput Voltage (V) 23344556........50505050 VDD = V5.O5UVT opagati 23 elect, O 112...050 Pr 1 tPHL@VDD=1.6V tPHL@VDD=5.5V hip S 00..05 CS 0 C -0.5 0 10 20 30 40 50 60 70 80 90 100 0 1 2 3 4 5 6 7 8 9 10 Pull-upResistor,R (k ) Time (ms) PU FIGURE 2-31: Propagation Delay vs. Pull- FIGURE 2-34: Chip Select (CS) Step up Resistor. Response (MCP6548 only). or) 1001.µE-04 or)100µ1.E-04 Comparator Comparator arat 101µ.E-05 TuCronms pOanra Htoerre SChuotms pOafrfa Htoerre arat 10µ1.E-05 Turns-On Shuts-Off p p m 11µ.E-06 m 1µ1.E-06 co Co CS High-to-Low Supply Current (A/ 1110010001111n....npEEEEn----10000987 VDD = 1.6CVS High-to-Low CSC HSy sLtoewre-stois-High Supply Current (A/111001000nnpn1111....EEEE----10000987 CVSDD L =o w5.-5toV-High CS Hysteresis 101p.E-11 10p1.E-11 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Chip Select (CS) Voltage (V) Chip Select (CS) Voltage (V) FIGURE 2-32: Supply Current (shoot FIGURE 2-35: Supply Current (shoot through current) vs. Chip Select (CS) Voltage at through current) vs. Chip Select (CS) Voltage at V = 1.6V (MCP6548 only). V = 5.5V (MCP6548 only). DD DD A/comparator)22330505 CS VOUT --0131..06..36Output Voltage,CS Voltage (V) µA/comparator)223305050000 CS VOUT VDD = 5.5V --0515..05.15.0Output Voltage,CS Voltage (V) nt (µ15 Start-up IDD VDD = 1.6V -4.9 ent (150 Start-up IDD -16.5 urre10 -6.6 Curr100 Charging output -22.0 ply C 5 -8.2 pply 50 capacitance -27.5 Sup 0 IDD -9.8 Su 0 IDD -33.0 0 1 2 3 4 5 6 7 8 9 10 11 12 0 1 2 3 4 5 6 7 8 9 10 11 12 Time (1 ms/div) Time (1 ms/div) FIGURE 2-33: Supply Current (charging FIGURE 2-36: Supply Current (charging current) vs. Chip Select (CS) pulse at V = 1.6V current) vs. Chip Select (CS) pulse at V = 5.5V DD DD (MCP6548 only). (MCP6548 only). DS21714C-page 10  2003 Microchip Technology Inc.

MCP6546/7/8/9 Note: Unless otherwise indicated, V = +1.6V to +5.0V, V = GND, T = +25°C, V + = V /2, V – = GND, DD SS A IN DD IN R = 2.74kΩ to V =V , and C = 36pF. PU PU DD L 7 500 put Voltage 456 VDD = 5.5V VOUT Current (pA) 334405050000 TCVVAIISNN +–= = ==+ V 8VVD5DSD°SDC/2 VDD = 1.6V verting Input, Out(V) 0123 VIN– Output Leakage 11220505500000 VDD = 5.5V n 0 I -1 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10 Time (1 ms/div) Output Voltage (V) FIGURE 2-37: The MCP6546/7/8/9 FIGURE 2-38: Output Leakage Current comparators show no phase reversal. (CS =V ) vs. Output Voltage (MCP6548 only) DD  2003 Microchip Technology Inc. DS21714C-page 11

MCP6546/7/8/9 3.0 APPLICATIONS INFORMATION 3.3 MCP6548 Chip Select (CS) The MCP6546/7/8/9 family of push-pull output The MCP6548 is a single comparator with a chip select comparators are fabricated on Microchip’s state-of-the- (CS) option. When CS is pulled high, the total current art CMOS process. They are suitable for a wide range consumption drops to 20pA (typ). 1pA (typ) flows of applications requiring very low power consumption. through the CS pin, 1pA (typ) flows through the output pin and 18pA (typ) flows through the V pin, as DD 3.1 Comparator Inputs shown in Figure1-1. When this happens, the comparator output is put into a high-impedance state. The MCP6546/7/8/9 comparator family uses CMOS By pulling CS low, the comparator is enabled. If the CS transistors at the input. They are designed to prevent pin is left floating, the comparator will not operate phase inversion when the input pins exceed the supply properly. Figure1-1 shows the output voltage and voltages. Figure2-37 shows an input voltage supply current response to a CS pulse. exceeding both supplies with no resulting phase inversion. The internal CS circuitry is designed to minimize glitches when cycling the CS pin. This helps conserve The input stage of this family of devices uses two power, which is especially important in battery-powered differential input stages in parallel: one operates at low applications. input voltages and the other at high input voltages. With this topology, the input voltage is 0.3V above V DD 3.4 Externally Set Hysteresis and 0.3V below V . Therefore, the input offset SS voltage is measured at both VSS - 0.3V and VDD + 0.3V Greater flexibility in selecting hysteresis, or input trip to ensure proper operation. points, is achieved by using external resistors. The maximum operating input voltages that can be Input offset voltage (V ) is the center (average) of the OS applied are VSS - 0.3V and VDD + 0.3V. Voltages on the (input-referred) low-high and high-low trip points. Input inputs that exceed this absolute maximum rating can hysteresis voltage (V ) is the difference between HYST cause excessive current to flow and permanently the same trip points. Hysteresis reduces output damage the device. In applications where the input pin chattering when one input is slowly moving past the exceeds the specified range, external resistors can be other, thus reducing dynamic supply current. It also used to limit the current below ±2mA, as shown in helps in systems where it is best not to cycle between Figure3-1. states too frequently (e.g., air conditioner thermostatic control). The MCP6546/7/8/9 family has internally-set hysteresis that is small enough to maintain input offset accuracy (<7mV), and large enough to eliminate RIN MCP654X VOUT output chattering caused by the comparator’s own input noise voltage (200µVp-p). V IN 9 30 V = 5.0V (Maximum expected V )–V 8 DD 25 R ≥-------------------------------------------------------I--N-----------------D----D---- 7 VIN+ = 2.75V 20 v) IN 2 mA V) 6 VOUT 15 V/di RIN≥-V---S----S----–-----(--M-----i--n---i--m--2--u-- -mm---- -A-e--x---p---e---c--t--e---d--- --V----I--N-----) Voltage ( 345 Hysteresis 0510 ge (10 m FshIGouUlRd Eb e3 -u1s:ed to limAint einxpceust sreivseis itnopru (tR cINu)r rent if Output 012 ---11550 put Volta either of the inputs exceeds the absolute -1 VIN– -20 In maximum specification. -2 -25 -3 0 100 200 300 400 500 600 700 800 900 1000-30 Time (100 ms/div) 3.2 Open-Drain Output FIGURE 3-2: The MCP6546/7/8/9 The open-drain output is designed to make level- comparators’ internal hysteresis eliminates shifting and wired-OR logic easy to implement. The output chatter caused by input noise voltage. output can go as high as 10V for 9V battery-powered applications. The output stage minimizes switching current (shoot-through current from supply-to-supply) when the output changes state. See Figures2-15,2-17 and 2-32 through2-36, for more information. DS21714C-page 12  2003 Microchip Technology Inc.

MCP6546/7/8/9 3.4.1 INVERTING CIRCUIT Where: Figure3-3 shows an inverting circuit for a single-supply R R R = -------2-------3---- application using three resistors, besides the pull-up 23 R +R 2 3 resistor. The resulting hysteresis diagram is shown in Figure3-4. R V = -----------3-------×V 23 R +R DD 2 3 VDD VPU Using this simplified circuit, the trip voltage can be VIN IPU RPU calculated using the following equation: V MCP654X VOUT EQUATION DD I OL R2 IRF VTHL = VPUR----------+------RR----2---3--+------R--------- +V23R---------R--+-F----R-+-----R--+--P---U-R--------- 23 F PU 23 F PU R3 RF VTLH = VOLR--------R--+--2--3--R------- +V23R--------R--+--F----R------ 23 F 23 F V = trip voltage from low to high TLH FIGURE 3-3: Inverting circuit with VTHL = trip voltage from high to low hysteresis. Figure2-19 and Figure2-22 can be used to determine typical values for V . This voltage is dependent on the OL V OUT output current I as shown in Figure3-3. This current OL V can be determined using the equation below: PU V OH EQUATION Low-to-High High-to-Low I = I +I OL PU RF VVOSSL VIN IOL = V----P---U--R---–-----V----O----L- +V--R--2--3----–--+---V--R--O---L-- V V V V PU 23 F SS TLH THL DD V = trip voltage from low to high V can be calculated using the equation below: TLH OH V = trip voltage from high to low THL EQUATION FIGURE 3-4: Hysteresis diagram for the inverting circuit. VOH = (VPU–V23)×R---------R-+---2--3R----+-----+R----F-R--------- 23 F PU In order to determine the trip voltages (V and V ) THL TLH for the circuit shown in Figure3-3, R and R can be 2 3 As explained in Section3.1, “Comparator Inputs”, it is simplified to the Thevenin equivalent circuit with important to keep the non-inverting input below respect to V , as shown in Figure3-5. DD V +0.3V when V > V . DD PU DD V 3.5 Supply Bypass PU With this family of comparators, the power supply pin R - PU (V for single supply) should have a local bypass DD MCP654X VOUT capacitor (i.e., 0.01µF to 0.1µF) within 2mm for good edge rate performance. + 3.6 Capacitive Loads V 23 Reasonable capacitive loads (e.g., logic gates) have R23 RF little impact on propagation delay (see Figure2-27). The supply current increases with increasing toggle FIGURE 3-5: Thevenin Equivalent Circuit. frequency (Figure2-30), especially with higher capacitive loads.  2003 Microchip Technology Inc. DS21714C-page 13

MCP6546/7/8/9 3.7 Battery Life 3.9 Typical Applications In order to maximize battery life in portable 3.9.1 PRECISE COMPARATOR applications, use large resistors and small capacitive loads. Also, avoid toggling the output more than Some applications require higher DC precision. An necessary and do not use chip select (CS) to conserve easy way to solve this problem is to use an amplifier power for short periods of time. Capacitive loads will (such as the MCP6041) to gain-up the input signal draw additional power at start-up. before it reaches the comparator. Figure3-7 shows an example of this approach. 3.8 PCB Surface Leakage V In applications where low input bias current is critical, DD PCB (Printed Circuit Board) surface leakage effects need to be considered. Surface leakage is caused by V REF humidity, dust or other contamination on the board. MCP6041 Under low-humidity conditions, a typical resistance between nearby traces is 1012Ω. A 5V difference VDD VPU would cause 5pA. If current-to-flow, this is greater R than the MCP6546/7/8/9 family’s bias current at 25°C V PU IN (1pA, typ). R1 R2 MCP6546 VOUT V The easiest way to reduce surface leakage is to use a REF guard ring around sensitive pins (or traces). The guard ring is biased at the same voltage as the sensitive pin. An example of this type of layout is shown in FIGURE 3-7: Precise Inverting Figure3-6. Comparator. V - V + 3.9.2 WINDOWED COMPARATOR IN IN V SS Figure3-8 shows one approach to designing a windowed comparator. The wired-OR connection produces a high output (logic 1) when the input voltage is between V and V (where V > V ). RB RT RT RB V PU 1/2 Guard Ring VRT MCP6547 RPU FIGURE 3-6: Example Guard Ring Layout V OUT for Inverting Circuit. 1. Inverting Configuration (Figures3-3 and 3-6): VIN a. Connect the guard ring to the non-inverting input pin (V +). This biases the guard ring IN to the same reference voltage as the VRB 1/2 comparator (e.g., V /2 or ground). DD MCP6547 b. Connect the inverting pin (V –) to the input IN pad without touching the guard ring. FIGURE 3-8: Windowed comparator. DS21714C-page 14  2003 Microchip Technology Inc.

MCP6546/7/8/9 4.0 PACKAGING INFORMATION 4.1 Package Marking Information 5-Lead SC-70 (MCP6546) Example: XNN A25 YWW 307 5-Lead SOT-23 (MCP6546) Example: XXNN AB37 8-Lead PDIP (300 mil) Example: XXXXXXXX MCP6546 XXXXXNNN I/P256 YYWW 0307 8-Lead SOIC (150 mil) Example: XXXXXXXX MCP6546 XXXXYYWW I/SN0307 NNN 256 8-Lead MSOP Example: XXXXXX 6546I YWWNNN 307256 Legend: XX...X Customer specific information* YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard marking consists of Microchip part number, year code, week code, traceability code (facility code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please check with your Microchip Sales Office.  2003 Microchip Technology Inc. DS21714C-page 15

MCP6546/7/8/9 Package Marking Information (Continued) 14-Lead PDIP (300 mil) (MCP6549) Example: XXXXXXXXXXXXXX MCP6549-I/P XXXXXXXXXXXXXX YYWWNNN 0307256 14-Lead SOIC (150 mil) (MCP6549) Example: XXXXXXXXXX MCP6549ISL XXXXXXXXXX YYWWNNN 0307256 14-Lead TSSOP (MCP6549) Example: XXXXXXXX MCP6549I YYWW 0307 NNN 256 DS21714C-page 16  2003 Microchip Technology Inc.

MCP6546/7/8/9 5-Lead Plastic Package (LT) (SC-70) E E1 D p B n 1 Q1 A2 A c A1 L Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 5 5 Pitch p .026 (BSC) 0.65 (BSC) Overall Height A .031 .043 0.80 1.10 Molded Package Thickness A2 .031 .039 0.80 1.00 Standoff A1 .000 .004 0.00 0.10 Overall Width E .071 .094 1.80 2.40 Molded Package Width E1 .045 .053 1.15 1.35 Overall Length D .071 .087 1.80 2.20 Foot Length L .004 .012 0.10 0.30 Top of Molded Pkg to Lead Shoulder Q1 .004 .016 0.10 0.40 Lead Thickness c .004 .007 0.10 0.18 Lead Width B .006 .012 0.15 0.30 *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. JEITA (EIAJ) Standard: SC-70 Drawing No. C04-061  2003 Microchip Technology Inc. DS21714C-page 17

MCP6546/7/8/9 5-Lead Plastic Small Outline Transistor (OT) (SOT23) E E1 p B p1 D n 1 α c A A2 φ A1 β L Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 5 5 Pitch p .038 0.95 Outside lead pitch (basic) p1 .075 1.90 Overall Height A .035 .046 .057 0.90 1.18 1.45 Molded Package Thickness A2 .035 .043 .051 0.90 1.10 1.30 Standoff § A1 .000 .003 .006 0.00 0.08 0.15 Overall Width E .102 .110 .118 2.60 2.80 3.00 Molded Package Width E1 .059 .064 .069 1.50 1.63 1.75 Overall Length D .110 .116 .122 2.80 2.95 3.10 Foot Length L .014 .018 .022 0.35 0.45 0.55 Foot Angle φ 0 5 10 0 5 10 Lead Thickness c .004 .006 .008 0.09 0.15 0.20 Lead Width B .014 .017 .020 0.35 0.43 0.50 Mold Draft Angle Top α 0 5 10 0 5 10 Mold Draft Angle Bottom β 0 5 10 0 5 10 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-178 Drawing No. C04-091 DS21714C-page 18  2003 Microchip Technology Inc.

MCP6546/7/8/9 8-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n 1 α E A A2 L c A1 β B1 p eB B Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch p .100 2.54 Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32 Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26 Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60 Overall Length D .360 .373 .385 9.14 9.46 9.78 Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43 Lead Thickness c .008 .012 .015 0.20 0.29 0.38 Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78 Lower Lead Width B .014 .018 .022 0.36 0.46 0.56 Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92 Mold Draft Angle Top a 5 10 15 5 10 15 Mold Draft Angle Bottom b 5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018  2003 Microchip Technology Inc. DS21714C-page 19

MCP6546/7/8/9 8-Lead Plastic Small Outline (SN) –Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 h α 45° c A A2 φ β L A1 Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch p .050 1.27 Overall Height A .053 .061 .069 1.35 1.55 1.75 Molded Package Thickness A2 .052 .056 .061 1.32 1.42 1.55 Standoff § A1 .004 .007 .010 0.10 0.18 0.25 Overall Width E .228 .237 .244 5.79 6.02 6.20 Molded Package Width E1 .146 .154 .157 3.71 3.91 3.99 Overall Length D .189 .193 .197 4.80 4.90 5.00 Chamfer Distance h .010 .015 .020 0.25 0.38 0.51 Foot Length L .019 .025 .030 0.48 0.62 0.76 Foot Angle φ 0 4 8 0 4 8 Lead Thickness c .008 .009 .010 0.20 0.23 0.25 Lead Width B .013 .017 .020 0.33 0.42 0.51 Mold Draft Angle Top α 0 12 15 0 12 15 Mold Draft Angle Bottom β 0 12 15 0 12 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057 DS21714C-page 20  2003 Microchip Technology Inc.

MCP6546/7/8/9 8-Lead Plastic Micro Small Outline Package (MS) (MSOP) E E1 p D 2 B n 1 α A A2 c φ A1 (F) L β Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch p .026 BSC 0.65 BSC Overall Height A - - .043 - - 1.10 Molded Package Thickness A2 .030 .033 .037 0.75 0.85 0.95 Standoff A1 .000 - .006 0.00 - 0.15 Overall Width E .193 TYP. 4.90 BSC Molded Package Width E1 .118 BSC 3.00 BSC Overall Length D .118 BSC 3.00 BSC Foot Length L .016 .024 .031 0.40 0.60 0.80 Footprint (Reference) F .037 REF 0.95 REF Foot Angle φ 0° - 8° 0° - 8° Lead Thickness c .003 .006 .009 0.08 - 0.23 Lead Width B .009 .012 .016 0.22 - 0.40 Mold Draft Angle Top α 5° - 15° 5° - 15° Mold Draft Angle Bottom β 5° - 15° 5° - 15° *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MO-187 Drawing No. C04-111  2003 Microchip Technology Inc. DS21714C-page 21

MCP6546/7/8/9 14-Lead Plastic Dual In-line (P) –300 mil (PDIP) E1 D 2 n 1 α E A A2 c L A1 β B1 eB B p Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 14 14 Pitch p .100 2.54 Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32 Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26 Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60 Overall Length D .740 .750 .760 18.80 19.05 19.30 Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43 Lead Thickness c .008 .012 .015 0.20 0.29 0.38 Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78 Lower Lead Width B .014 .018 .022 0.36 0.46 0.56 Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92 Mold Draft Angle Top α 5 10 15 5 10 15 Mold Draft Angle Bottom β 5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-005 DS21714C-page 22  2003 Microchip Technology Inc.

MCP6546/7/8/9 14-Lead Plastic Small Outline (SL) –Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 α h 45× c A A2 φ A1 L β Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 14 14 Pitch p .050 1.27 Overall Height A .053 .061 .069 1.35 1.55 1.75 Molded Package Thickness A2 .052 .056 .061 1.32 1.42 1.55 Standoff § A1 .004 .007 .010 0.10 0.18 0.25 Overall Width E .228 .236 .244 5.79 5.99 6.20 Molded Package Width E1 .150 .154 .157 3.81 3.90 3.99 Overall Length D .337 .342 .347 8.56 8.69 8.81 Chamfer Distance h .010 .015 .020 0.25 0.38 0.51 Foot Length L .016 .033 .050 0.41 0.84 1.27 Foot Angle φ 0 4 8 0 4 8 Lead Thickness c .008 .009 .010 0.20 0.23 0.25 Lead Width B .014 .017 .020 0.36 0.42 0.51 Mold Draft Angle Top α 0 12 15 0 12 15 Mold Draft Angle Bottom β 0 12 15 0 12 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-065  2003 Microchip Technology Inc. DS21714C-page 23

MCP6546/7/8/9 14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP) E E1 p D 2 n 1 B α A c φ β A1 A2 L Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 14 14 Pitch p .026 0.65 Overall Height A .043 1.10 Molded Package Thickness A2 .033 .035 .037 0.85 0.90 0.95 Standoff § A1 .002 .004 .006 0.05 0.10 0.15 Overall Width E .246 .251 .256 6.25 6.38 6.50 Molded Package Width E1 .169 .173 .177 4.30 4.40 4.50 Molded Package Length D .193 .197 .201 4.90 5.00 5.10 Foot Length L .020 .024 .028 0.50 0.60 0.70 Foot Angle φ 0 4 8 0 4 8 Lead Thickness c .004 .006 .008 0.09 0.15 0.20 Lead Width B1 .007 .010 .012 0.19 0.25 0.30 Mold Draft Angle Top α 0 5 10 0 5 10 Mold Draft Angle Bottom β 0 5 10 0 5 10 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005” (0.127mm) per side. JEDEC Equivalent: MO-153 Drawing No. C04-087 DS21714C-page 24  2003 Microchip Technology Inc.

MCP6546/7/8/9 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. -X /XX Examples: a) MCP6546T-I/LT: Tape and Reel, Device Temperature Package Industrial Temperature, Range 5LD SC-70. b) MCP6546T-I/OT: Tape and Reel, Industrial Temperature, Device: MCP6546: Single Comparator MCP6546T: Single Comparator (Tape and Reel) 5LD SOT-23. (SC-70, SOT-23, SOIC, MSOP) c) MCP6546-I/P: Industrial Temperature, MCP6546RT:Single Comparator (Rotated - Tape and 8LD PDIP. Reel) (SOT-23 only) d) MCP6546RT-I/OT:Tape and Reel, MCP6547: Dual Comparator MCP6547T: Dual Comparator Industrial Temperature, (Tape and Reel for SOIC and MSOP) 5LD SOT23. MCP6548: Single Comparator with CS MCP6548T: Single Comparator with CS a) MCP6547-I/MS: Industrial Temperature, (Tape and Reel for SOIC and MSOP) 8LD MSOP. MCP6549: Quad Comparator b) MCP6547T-I/MS: Tape and Reel, MCP6549T: Quad Comparator Industrial Temperature, (Tape and Reel for SOIC and TSSOP) 8LD MSOP. c) MCP6547-I/P: Industrial Temperature, Temperature Range: I = -40°C to +85°C 8LD PDIP. a) MCP6548-I/SN: Industrial Temperature, Package: LT = Plastic Package (SC-70), 5-lead 8LD SOIC. OT = Plastic Small Outline Transistor (SOT-23), 5-lead b) MCP6548T-I/SN: Tape and Reel, MS = Plastic MSOP, 8-lead P = Plastic DIP (300 mil Body), 8-lead, 14-lead Industrial Temperature, SN = Plastic SOIC (150 mil Body), 8-lead 8LD SOIC. SL = Plastic SOIC (150 mil Body), 14-lead (MCP6549) c) MCP6548-I/P: Industrial Temperature, ST = Plastic TSSOP (4.4mm Body), 14-lead (MCP6549) 8LD PDIP. a) MCP6549T-I/SL: Tape and Reel, Industrial Temperature, 14LD SOIC. b) MCP6549T-I/SL: Tape and Reel, Industrial Temperature, 14LD SOIC. c) MCP6549-I/P: Industrial Temperature, 14LD PDIP. Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office 2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 3. The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.  2003 Microchip Technology Inc. DS21714C-page 25

MCP6546/7/8/9 NOTES: DS21714C-page 26  2003 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is intended through suggestion only The Microchip name and logo, the Microchip logo, Accuron, and may be superseded by updates. It is your responsibility to dsPIC, KEELOQ, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. PRO MATE and PowerSmart are registered trademarks of No representation or warranty is given and no liability is Microchip Technology Incorporated in the U.S.A. and other assumed by Microchip Technology Incorporated with respect countries. to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such AmpLab, FilterLab, microID, MXDEV, MXLAB, PICMASTER, use or otherwise. Use of Microchip’s products as critical SEEVAL and The Embedded Control Solutions Company are components in life support systems is not authorized except registered trademarks of Microchip Technology Incorporated with express written approval by Microchip. No licenses are in the U.S.A. conveyed, implicitly or otherwise, under any intellectual Application Maestro, dsPICDEM, dsPICDEM.net, ECAN, property rights. ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPIC, Select Mode, SmartSensor, SmartShunt, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2003, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified.  2003 Microchip Technology Inc. Preliminary DS21714C-page 27

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: MCP6548-I/P MCP6549T-I/SL MCP6549T-I/ST MCP6548T-I/SN MCP6547-I/P MCP6548T-I/MS MCP6547-I/MS MCP6547-I/SN MCP6549-I/P MCP6546RT-I/OT MCP6549-I/ST MCP6546-I/P MCP6546-I/MS MCP6546-I/SN MCP6546T-I/LT MCP6546T-I/SN MCP6547T-I/SN MCP6546T-I/OT MCP6546T-I/MS MCP6547T-I/MS MCP6548- I/MS MCP6548-I/SN