MCP6541/1R/1U/2/3/4 Push-Pull Output Sub-Microamp Comparators Features Description • Low Quiescent Current: 600nA/comparator (typ.) The Microchip Technology Inc. MCP6541/2/3/4 family • Rail-to-Rail Input: V - 0.3V to V + 0.3V of comparators is offered in single (MCP6541, SS DD MCP6541R, MCP6541U), single with Chip Select (CS) • CMOS/TTL-Compatible Output (MCP6543), dual (MCP6542) and quad (MCP6544) • Propagation Delay: 4µs (typ., 100mV Overdrive) configurations. The outputs are push-pull (CMOS/TTL- • Wide Supply Voltage Range: 1.6V to 5.5V compatible) and are capable of driving heavy DC or • Available in Single, Dual and Quad capacitive loads. • Single available in SOT-23-5, SC-70-5 * packages These comparators are optimized for low power, single- • Chip Select (CS) with MCP6543 supply operation with greater than rail-to-rail input • Low Switching Current operation. The push-pull output of the • Internal Hysteresis: 3.3mV (typ.) MCP6541/1R/1U/2/3/4 family supports rail-to-rail output swing and interfaces with TTL/CMOS logic. The internal • Temperature Ranges: input hysteresis eliminates output switching due to inter- - Industrial: -40°C to +85°C nal input noise voltage, reducing current draw. The out- - Extended: -40°C to +125°C put limits supply current surges and dynamic power consumption while switching. This product family oper- Typical Applications ates with a single-supply voltage as low as 1.6V and draws less than 1µA/comparator of quiescent current. • Laptop Computers • Mobile Phones The related MCP6546/7/8/9 family of comparators from Microchip has an open-drain output. Used with a pull-up • Metering Systems resistor, these devices can be used as level-shifters for • Hand-held Electronics any desired voltage up to 10V and in wired-OR logic. • RC Timers * SC-70-5 E-Temp parts not available at this release of • Alarm and Monitoring Circuits the data sheet. • Windowed Comparators MCP6541U SOT-23-5 is E-Temp only. • Multi-vibrators Related Devices • Open-Drain Output: MCP6546/7/8/9 Package Types MCP6541 MCP6541R MCP6542 MCP6544 PDIP, SOIC, MSOP SOT-23-5 PDIP, SOIC, MSOP PDIP, SOIC, TSSOP NC 1 8 NC OUT 1 5 VSS OUTA 1 8 VDD OUTA 1 14OUTD VIN– 2 -- 7 VDD VDD 2 + - VINA– 2 -+ 7 OUTB VINA– 2 -+ +- 13VIND– VIN+ 3 ++ 6 OUT VIN+ 3 4 VIN– VINA+ 3 + - 6 VINB– VINA+ 3 12VIND+ VSS 4 5 NC VSS 4 5 VINB+ VDD 4 11VSS V + 5 10V + INB INC MCP6541 MCP6541U MCP6543 V – 6 - + +- 9 V – INB INC SOT-23-5, SC-70-5 SOT-23-5 PDIP, SOIC, MSOP OUTB 7 8 OUTC OUT 1 5 VDD VIN– 1 5 VDD NC 1 8 CS VVINS+S 23 + - 4 VIN– VVINS+S 23 +- 4 OUT VVIINN+– 23 +- 76 VODUDT VSS 4 5 NC © 2006 Microchip Technology Inc. DS21696E-page 1

MCP6541/1R/1U/2/3/4 1.0 ELECTRICAL † Notice: Stresses above those listed under “Absolute Maxi- mum Ratings” may cause permanent damage to the device. CHARACTERISTICS This is a stress rating only and functional operation of the device at those or any other conditions above those indicated Absolute Maximum Ratings † in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods VDD - VSS.........................................................................7.0V may affect device reliability. Current at Analog Input Pin (VIN+, VIN-.........................±2mA †† See Section4.1.2 “Input Voltage and Current Analog Input (V ) ††......................V - 1.0V to V + 1.0V Limits” IN SS DD All other Inputs and Outputs...........V - 0.3V to V + 0.3V SS DD Difference Input voltage .......................................|V - V | DD SS Output Short-Circuit Current .................................continuous Current at Input Pins ....................................................±2mA Current at Output and Supply Pins ............................±30mA Storage temperature.....................................-65°C to +150°C Maximum Junction Temperature (T )..........................+150°C J ESD protection on all pins (HBM;MM)...................4kV; 400V DC CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, V = +1.6V to +5.5V, V = GND, T = +25°C,V + = V /2, DD SS A IN DD VIN– = VSS, and RL=100kΩ to VDD/2 (Refer to Figure1-3). Parameters Sym Min Typ Max Units Conditions Power Supply Supply Voltage V 1.6 — 5.5 V DD Quiescent Current per comparator I 0.3 0.6 1.0 µA I = 0 Q OUT Input Input Voltage Range V V −0.3 — V +0.3 V CMR SS DD Common Mode Rejection Ratio CMRR 55 70 — dB V = 5V, V = -0.3V to 5.3V DD CM Common Mode Rejection Ratio CMRR 50 65 — dB V = 5V, V = 2.5V to 5.3V DD CM Common Mode Rejection Ratio CMRR 55 70 — dB V = 5V, V = -0.3V to 2.5V DD CM Power Supply Rejection Ratio PSRR 63 80 — dB V = V CM SS Input Offset Voltage V -7.0 ±1.5 +7.0 mV V = V (Note1) OS CM SS Drift with Temperature ΔV /ΔT — ±3 — µV/°C T = -40°C to +125°C, V = V OS A A CM SS Input Hysteresis Voltage V 1.5 3.3 6.5 mV V = V (Note1) HYST CM SS Linear Temp. Co. (Note2) TC — 6.7 — µV/°C T = -40°C to +125°C, V = V 1 A CM SS Quadratic Temp. Co. (Note2) TC — -0.035 — µV/°C2 T = -40°C to +125°C, V = V 2 A CM SS Input Bias Current I — 1 — pA V =V B CM SS At Temperature (I-Temp parts) I — 25 100 pA T = +85°C, V = V (Note3) B A CM SS At Temperature (E-Temp parts) I — 1200 5000 pA T = +125°C, V = V (Note3) B A CM SS Input Offset Current I — ±1 — pA V =V OS CM SS Common Mode Input Impedance Z — 1013||4 — Ω||pF CM Differential Input Impedance Z — 1013||2 — Ω||pF DIFF Note 1: The input offset voltage is the center (average) of the input-referred trip points. The input hysteresis is the difference between the input-referred trip points. 2: V at different temperatures is estimated using V (T ) = V + (T - 25°C) TC + (T - 25°C)2 TC . HYST HYST A HYST A 1 A 2 3: Input bias current at temperature is not tested for SC-70-5 package. 4: Limit the output current to Absolute Maximum Rating of 30mA. DS21696E-page 2 © 2006 Microchip Technology Inc.

MCP6541/1R/1U/2/3/4 DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, V = +1.6V to +5.5V, V = GND, T = +25°C,V + = V /2, DD SS A IN DD VIN– = VSS, and RL=100kΩ to VDD/2 (Refer to Figure1-3). Parameters Sym Min Typ Max Units Conditions Push-Pull Output High-Level Output Voltage V V −0.2 — — V I = -2mA, V = 5V OH DD OUT DD Low-Level Output Voltage V — — V +0.2 V I = 2mA, V = 5V OL SS OUT DD Short-Circuit Current I — -2.5, +1.5 — mA V = 1.6V (Note4) SC DD I — ±30 — mA V = 5.5V (Note4) SC DD Note 1: The input offset voltage is the center (average) of the input-referred trip points. The input hysteresis is the difference between the input-referred trip points. 2: V at different temperatures is estimated using V (T ) = V + (T - 25°C) TC + (T - 25°C)2 TC . HYST HYST A HYST A 1 A 2 3: Input bias current at temperature is not tested for SC-70-5 package. 4: Limit the output current to Absolute Maximum Rating of 30mA. AC CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, V = +1.6V to +5.5V, V = GND, T = +25°C, V + = V /2, DD SS A IN DD Step = 200mV, Overdrive = 100mV, and C = 36pF (Refer to Figure1-2 and Figure1-3). L Parameters Sym Min Typ Max Units Conditions Rise Time t — 0.85 — µs R Fall Time t — 0.85 — µs F Propagation Delay (High-to-Low) t — 4 8 µs PHL Propagation Delay (Low-to-High) t — 4 8 µs PLH Propagation Delay Skew t — ±0.2 — µs (Note1) PDS Maximum Toggle Frequency f — 160 — kHz V = 1.6V MAX DD f — 120 — kHz V = 5.5V MAX DD Input Noise Voltage E — 200 — µV 10Hz to 100kHz ni P-P Note 1: Propagation Delay Skew is defined as: t = t - t . PDS PLH PHL MCP6543 CHIP SELECT (CS) CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = VSS, and C = 36pF (Refer to Figures1-1 and 1-3). L Parameters Sym Min Typ Max Units Conditions CS Low Specifications CS Logic Threshold, Low V V — 0.2V V IL SS DD CS Input Current, Low I — 5.0 — pA CS = V CSL SS CS High Specifications CS Logic Threshold, High V 0.8V — V V IH DD DD CS Input Current, High I — 1 — pA CS = V CSH DD CS Input High, V Current I — 18 — pA CS = V DD DD DD CS Input High, GND Current I — –20 — pA CS = V SS DD Comparator Output Leakage I — 1 — pA V = V ,CS = V O(LEAK) OUT DD DD CS Dynamic Specifications CS Low to Comparator Output Low t — 2 50 ms CS = 0.2V to V = V /2, ON DD OUT DD Turn-on Time V – = V IN DD CS High to Comparator Output t — 10 — µs CS = 0.8V to V = V /2, OFF DD OUT DD High Z Turn-off Time V – = V IN DD CS Hysteresis V — 0.6 — V V = 5V CS_HYST DD © 2006 Microchip Technology Inc. DS21696E-page 3

MCP6541/1R/1U/2/3/4 CS V V IL IH V – IN 100mV t t ON OFF VIN+ = VDD/2 100mV tPHL VOUT Hi-Z Hi-Z t PLH V OH -20pA (typ.) -0.6µA (typ.) -20pA (typ.) I SS V OUT 1pA (typ.) 1pA (typ.) V V I OL OL CS FIGURE 1-1: Timing Diagram for the CS FIGURE 1-2: Propagation Delay Timing Pin on the MCP6543. Diagram. DS21696E-page 4 © 2006 Microchip Technology Inc.

MCP6541/1R/1U/2/3/4 TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, V = +1.6V to +5.5V and V = GND. DD SS Parameters Sym Min Typ Max Units Conditions Temperature Ranges Specified Temperature Range T -40 — +85 °C A Operating Temperature Range T -40 — +125 °C Note A Storage Temperature Range T -65 — +150 °C A Thermal Package Resistances Thermal Resistance, 5L-SC-70 θ — 331 — °C/W JA Thermal Resistance, 5L-SOT-23 θ — 256 — °C/W JA Thermal Resistance, 8L-PDIP θ — 85 — °C/W JA Thermal Resistance, 8L-SOIC θ — 163 — °C/W JA Thermal Resistance, 8L-MSOP θ — 206 — °C/W JA Thermal Resistance, 14L-PDIP θ — 70 — °C/W JA Thermal Resistance, 14L-SOIC θ — 120 — °C/W JA Thermal Resistance, 14L-TSSOP θ — 100 — °C/W JA Note: The MCP6541/2/3/4 I-Temp parts operate over this extended temperature range, but with reduced perfor- mance. In any case, the Junction Temperature (T ) must not exceed the Absolute Maximum specification J of +150°C. 1.1 Test Circuit Configuration This test circuit configuration is used to determine the AC and DC specifications. V DD 200kΩ MCP654X 200kΩ 200kΩ VOUT 200kΩ 36pF V = 0V V = V SS IN SS FIGURE 1-3: AC and DC Test Circuit for the Push-Pull Output Comparators. © 2006 Microchip Technology Inc. DS21696E-page 5

MCP6541/1R/1U/2/3/4 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = GND, R = 100kΩ to V /2, and C = 36pF. L DD L 14% 18% nces 12% 1V2C0M0 = S VaSmSples nces 16% 1V2C0M0 = S VaSmSples Occurre 108%% Occurre 111024%%% Percentage of 246%%% Percentage of 2468%%%% 0% 0% -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2 5.6 6.0 Input Offset Voltage (mV) Input Hysteresis Voltage (mV) FIGURE 2-1: Input Offset Voltage at FIGURE 2-4: Input Hysteresis Voltage at V =V . V =V . CM SS CM SS s25% 16% e 596 Samples s 1200 Samples c urrence1124%% VTAC=M -=4 0V°SCS to +125°C ccurren1250%% VTAC M= =-4 V0S°SC to +125°C c10% O e of Oc 68%% age of 10% VDD = 5.5V VDD = 1.6V ntag 4% cent 5% erce 2% Per 0% P 0% 6 0 4 8 2 6 0 4 8 2 6 0 4 4 2 0 8 6 4 2 0 2 4 6 8 0 2 4 4. 5. 5. 5. 6. 6. 7. 7. 7. 8. 8. 9. 9. -1 -1 -1 - - - - 1 1 1 Input Hysteresis Voltage – Input Offset Voltage Drift (µV/°C) Linear Temp. Co.; TC (µV/°C) 1 FIGURE 2-2: Input Offset Voltage Drift at FIGURE 2-5: Input Hysteresis Voltage V =V . Linear Temp. Co. (TC ) at V =V . CM SS 1 CM SS ut, Output Voltage (V) 34567 VDD = 5.5V VOUT age of Occurrences11111202468068%%%%%%%% 5VTV9ACD 6MD= S==-4 a V10mS.°6SpCVl etos +125°C VDD = 5.5V ng Inp 12 ercent 024%%% erti 0 VIN– P 60 56 52 48 44 40 36 32 28 24 20 16 v 0 0 0 0 0 0 0 0 0 0 0 0 In -1 -0. -0. -0. -0. -0. -0. -0. -0. -0. -0. -0. -0. 0 1 2 3 4 5 6 7 8 9 10 Input Hysteresis Voltage – Time (1 ms/div) Quadratic Temp. Co.; TC2 (µV/°C2) FIGURE 2-3: The MCP6541/1R/1U/2/3/4 FIGURE 2-6: Input Hysteresis Voltage comparators show no phase reversal. Quadratic Temp. Co. (TC ) at V =V . 2 CM SS DS21696E-page 6 © 2006 Microchip Technology Inc.

MCP6541/1R/1U/2/3/4 Note: Unless otherwise indicated, V =+1.6V to +5.5V, V =GND, T =25°C, V +=V /2, V –=GND, DD SS A IN DD IN R =100kΩ to V /2, and C =36pF. L DD L 1.0 6.5 mV) 00..68 VCM = VSS e (mV) 56..50 VCM = VSS Offset Voltage ( --00000.....02442 VVDDDD == 15..65VV steresis Voltag 33445.....05050 VDD = 1.6V Input --00..86 put Hy 22..05 VDD = 5.5V -1.0 In 1.5 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 Ambient Temperature (°C) Ambient Temperature (°C) FIGURE 2-7: Input Offset Voltage vs. FIGURE 2-10: Input Hysteresis Voltage vs. Ambient Temperature at V =V . Ambient Temperature at V =V . CM SS CM SS 2.0 V) 6.0 Input Offset Voltage (mV) ----00112110........05050505 VDD T=A 1 =.6 +V125°C TTTTAAAA ==== +-++41820255°5°°CCC°C Input Hysteresis Voltage (m 122334455.........505050505 VDD = 1.6V TTTTAAAA === = +++ -82145520°°5°CC°CC 4 2 0 2 4 6 8 0 2 4 6 8 0 4 2 0 2 4 6 8 0 2 4 6 8 0 0. 0. 0. 0. 0. 0. 0. 1. 1. 1. 1. 1. 2. 0. 0. 0. 0. 0. 0. 0. 1. 1. 1. 1. 1. 2. - - - - Common Mode Input Voltage (V) Common Mode Input Voltage (V) FIGURE 2-8: Input Offset Voltage vs. FIGURE 2-11: Input Hysteresis Voltage vs. Common Mode Input Voltage at V =1.6V. Common Mode Input Voltage at V =1.6V. DD DD 2.0 V) 6.0 et Voltage (mV) 0011....0505 VDD = 5.5V TTAA == +-4205°°CC esis Voltage (m 34455.....50505 VDD = 5.5V TTTTAAAA ==== +-++41820255°5°°CCC°C Input Offs ----2110....0505 TTA A= = + +12855°°CC nput Hyster 1223....5050 I 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 0. 0. 0. 1. 1. 2. 2. 3. 3. 4. 4. 5. 5. 6. 0. 0. 0. 1. 1. 2. 2. 3. 3. 4. 4. 5. 5. 6. - - Common Mode Input Voltage (V) Common Mode Input Voltage (V) FIGURE 2-9: Input Offset Voltage vs. FIGURE 2-12: Input Hysteresis Voltage vs. Common Mode Input Voltage at V = 5.5V. Common Mode Input Voltage at V =5.5V. DD DD © 2006 Microchip Technology Inc. DS21696E-page 7

MCP6541/1R/1U/2/3/4 Note: Unless otherwise indicated, V =+1.6V to +5.5V, V =GND, T =25°C, V +=V /2, V –=GND, DD SS A IN DD IN R =100kΩ to V /2, and C =36pF. L DD L B) 8950 Input Referred ents (A)101001001000nn IB, TA = +125°C VDD = 5.5V R, PSRR (d 778050 PSRR, VIN+ = VSS, VDD = 1.6V to 5.5V Offset Curr1101010000pp IB, TA = +85°C MR 65 as, IOS, TA = +125°C C 60 CMRR, VIN+ = -0.3 to 5.3V, VDD = 5.0V ut Bi 11p IOS, TA = +85°C p 55 In 100.01f -50 -25 0 25 50 75 100 125 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Ambient Temperature (°C) Common Mode Input Voltage (V) FIGURE 2-13: CMRR,PSRR vs. Ambient FIGURE 2-16: Input Bias Current, Input Temperature. Offset Current vs. Common Mode Input Voltage. 1000 0.7 s V = 5.5V nput Bias, Offset Current(pA) 101010 VDCDM = VDD IB | IOS | Quiescent Currentper Comparator (µA) 000000......123456 TTTAT AA=A == =+ ++1-28245550°°°°CCCC I 0.1 0.0 55 65 75 85 95 105 115 125 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Ambient Temperature (°C) Power Supply Voltage (V) FIGURE 2-14: Input Bias Current, Input FIGURE 2-17: Quiescent Current vs. Offset Current vs. Ambient Temperature. Power Supply Voltage. 0.7 0.7 V = 1.6V V = 5.5V DD DD 0.6 0.6 urrentor (µA) 0.5 urrentor (µA) 0.5 Cat 0.4 Cat 0.4 cent mpar 0.3 cent mpar 0.3 Quieser co 0.2 Sweep VIN+, VIN– = VDD/2 Quieser Co 0.2 Sweep VIN+, VIN– = VDD/2 p 0.1 p 0.1 Sweep V –, V + = V /2 Sweep V –, V + = V /2 IN IN DD IN IN DD 0.0 0.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Common Mode Input Voltage (V) Common Mode Input Voltage (V) FIGURE 2-15: Quiescent Current vs. FIGURE 2-18: Quiescent Current vs. Common Mode Input Voltage at V =1.6V. Common Mode Input Voltage at V =5.5V. DD DD DS21696E-page 8 © 2006 Microchip Technology Inc.

MCP6541/1R/1U/2/3/4 Note: Unless otherwise indicated, V =+1.6V to +5.5V, V =GND, T =25°C, V +=V /2, V –=GND, DD SS A IN DD IN R =100kΩ to V /2, and C =36pF. L DD L 10 35 100 mV Overdrive nt TA = -40°C upply Current (µA) 1 VRCL M= = in VfiDnDi/t2y VVDDDD == 51..56VV ut Short Circuit CurreMagnitude (mA) 1122305050 TTTA AA= == + ++1228555°°°CCC S p ut 5 O 0.1 0 0.1 1 10 100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Toggle Frequency (kHz) Power Supply Voltage (V) FIGURE 2-19: Supply Current vs. Toggle FIGURE 2-22: Output Short Circuit Current Frequency. Magnitude vs. Power Supply Voltage. droom (V) 000...678 VTTAAO L==– V+ +1SS28:55°°CC VDD = 1.6V droom (V) 0001....7890 TTTAV A=O== L+ ++1–282 V555S°°°SCCC: Hea 0.5 TA = +25°C Hea 0.6 TAA = -40°C Voltage 00..34 TA = -40°C TTAA ==V D++D18–25V5°CO°HC: Voltage 000...345 TTAAV ==D D++ –18 25V5°OC°HC: ut 0.2 TA = +25°C ut 0.2 TA = +25°C utp 0.1 TA = -40°C utp 0.1 VDD = 5.5V TA = -40°C O O 0.0 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 5 10 15 20 25 Output Current (mA) Output Current (mA) FIGURE 2-20: Output Voltage Headroom FIGURE 2-23: Output Voltage Headroom vs. Output Current at V =1.6V. vs. Output Current at V =5.5V. DD DD 45% 45% s 600 Samples s 600 Samples e 40% e 40% nc 100 mV Overdrive nc 100 mV Overdrive urre 3305%% VCM = VDD/2 urre 3305%% VCM = VDD/2 c c c c O 25% O 25% e of 20% e of 20% entag 1105%% VDD = 1.6V VDD = 5.5V entag 1105%% VDD = 1.6V VDD = 5.5V c c er 5% er 5% P P 0% 0% 0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8 High-to-Low Propagation Delay (µs) Low-to-High Propagation Delay (µs) FIGURE 2-21: High-to-Low Propagation FIGURE 2-24: Low-to-High Propagation Delay. Delay. © 2006 Microchip Technology Inc. DS21696E-page 9

MCP6541/1R/1U/2/3/4 Note: Unless otherwise indicated, V =+1.6V to +5.5V, V =GND, T =25°C, V +=V /2, V –=GND, DD SS A IN DD IN R =100kΩ to V /2, and C =36pF. L DD L 45% 8 s 600 Samples 100 mV Overdrive Occurrence 23345050%%%% 1V0C0M m= VV DOD/v2erdrive Delay (µs) 567 VCM = tVPLDHD /@2 VDD = 5.5V tPHL @ VDD = 5.5V of 20% on 4 ercentage 11055%%% VDD = 5.5V VDD = 1.6V Propagati 123 tPLH @ VDD = 1.6V tPHL @ VDD = 1.6V P 0% 0 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 -50 -25 0 25 50 75 100 125 Propagation Delay Skew (µs) Ambient Temperature (°C) FIGURE 2-25: Propagation Delay Skew. FIGURE 2-28: Propagation Delay vs. Ambient Temperature. 14 100 Delay (µs) 1111012389 VtPCLMH @= V 1D0D /m2V Overdrive Delay (µs) tttPPPHLHHLL @@@ VVVDDDDDD === 511...V566CVVVM = VDD/2 gation 567 ttPPLHHL @@ 11000 m mVV O Ovveerrddrrivivee gation 10 opa 34 opa tPLH @ VDD = 5.5V Pr 2 tPHL @ 100 mV Overdrive Pr 1 0 1 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1 10 100 1000 Power Supply Voltage (V) Input Overdrive (mV) FIGURE 2-26: Propagation Delay vs. FIGURE 2-29: Propagation Delay vs. Input Power Supply Voltage. Overdrive. 8 8 µs) 7 V10D0D =m 1V. 6OVverdrive µs) 7 V10D0D =m 5V. 5OVverdrive Delay ( 56 Delay ( 56 tPHL gation 34 ttPLH gation 34 tPLH pa 2 PHL pa 2 o o Pr 1 Pr 1 0 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Common Mode Input Voltage (V) Common Mode Input Voltage (V) FIGURE 2-27: Propagation Delay vs. FIGURE 2-30: Propagation Delay vs. Common Mode Input Voltage at V =1.6V. Common Mode Input Voltage at V =5.5V. DD DD DS21696E-page 10 © 2006 Microchip Technology Inc.

MCP6541/1R/1U/2/3/4 Note: Unless otherwise indicated, V =+1.6V to +5.5V, V =GND, T =25°C, V +=V /2, V –=GND, DD SS A IN DD IN R =100kΩ to V /2, and C =36pF. L DD L Propagation Delay (µs) 1122334450505050505 1V0C0MttPP mHL=HL VV @@ DOD VV/v2DDeDDr d==r i11v..e66VV ttPPLHHL @@ VVDDDD == 55..55VV hip Select, Output Voltage (V) 0011223344556.............0505050505050 VDD =V 5OC.U5STV 0 C -0.5 0 10 20 30 40 50 60 70 80 90 0 1 2 3 4 5 6 7 8 9 10 Load Capacitance (nF) Time (ms) FIGURE 2-31: Propagation Delay vs. Load FIGURE 2-34: Chip Select (CS) Step Capacitance. Response (MCP6543 only). 1.E-10m3 1.E-10m3 Comparator Comparator Comparator Comparator Supply Currentper Comparator (A)111111......11EEEEEE0110------000000100010987654nnnµµµ TurnsH iOgnh-to-LoCwS CSCL oHSwSyhs-tutoet-rsHe Oisgifshf Supply Currentper Comparator (A)111111......EEEEEE110101------000000100100987654nnnµµµ TLuorwn-sCto SO-Hnigh HystCeSreHsiisgh-to-LoCSwShuts Off 1.1E0-100p V = 1.6V 1.E10-100p V = 5.5V DD DD 1.E1-101p 1.E1-101p 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Chip Select (CS) Voltage (V) Chip Select (CS) Voltage (V) FIGURE 2-32: Supply Current (shoot FIGURE 2-35: Supply Current (shoot through current) vs. Chip Select (CS) Voltage at through current) vs. Chip Select (CS) Voltage at V =1.6V (MCP6543 only). V =5.5V (MCP6543 only). DD DD upply Current (µA) 11223050505 VDD = 1C.6hcVaarpgaincgit aonucteput VOSICDUtSDTart-up ----016431..06....5926Output Voltage, Chip Select Voltage (V), Supply Currenter Comparator (µA)11111202468024680000000000 VVDODU T= 5C.5SV ChcaSarptgaairnctg-itu aopnu cItDepDut -------03621119631852Output Voltage, Chip Select Voltage (V) S 0 -8.1 p 0 -24 0 1 2 3 4 5 6 7 8 9 1011121314 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 Time (1 ms/div) Time (0.5 ms/div) FIGURE 2-33: Supply Current (charging FIGURE 2-36: Supply Current (charging current) vs. Chip Select (CS) pulse at V =1.6V current) vs. Chip Select (CS) pulse at V =5.5V DD DD (MCP6543 only). (MCP6543 only). © 2006 Microchip Technology Inc. DS21696E-page 11

MCP6541/1R/1U/2/3/4 Note: Unless otherwise indicated, V =+1.6V to +5.5V, V =GND, T =25°C, V +=V /2, V –=GND, DD SS A IN DD IN R =100kΩ to V /2, and C =36pF. L DD L 1.E1-00m2 A)1.E-10m3 de (1.E10-004µ nitu1.E1-005µ g1.E-016µ a M1.E10-007n nt 1.E1-008n urre1.E-019n ++12855°°CC put C11..EE110--110010pp +-4250°°CC n I1.E-112p -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 Input Voltage (V) FIGURE 2-37: Input Bias Current vs. Input Voltage DS21696E-page 12 © 2006 Microchip Technology Inc.

MCP6541/1R/1U/2/3/4 3.0 PIN DESCRIPTIONS Descriptions of the pins are listed in Table3-1. TABLE 3-1: PIN FUNCTION TABLE MM(CSPSOPDO6IIC5PP,4,)1 (MSSOCCTP-7-62053-45-51), MCP6541R MCP6541U MCP6542 MCP6543 MCP6544 Symbol Description 6 1 1 4 1 6 1 OUT, OUTA Digital Output (comparator A) 2 4 4 1 2 2 2 V –, V – Inverting Input (comparator A) IN INA 3 3 3 3 3 3 3 V +, V + Non-inverting Input (comparator A) IN INA 7 5 2 5 8 7 4 V Positive Power Supply DD — — — — 5 — 5 V + Non-inverting Input (comparator B) INB — — — — 6 — 6 V – Inverting Input (comparator B) INB — — — — 7 — 7 OUTB Digital Output (comparator B) — — — — — — 8 OUTC Digital Output (comparator C) — — — — — — 9 V – Inverting Input (comparator C) INC — — — — — — 10 V + Non-inverting Input (comparator C) INC 4 2 5 2 4 4 11 V Negative Power Supply SS — — — — — — 12 V + Non-inverting Input (comparator D) IND — — — — — — 13 V – Inverting Input (comparator D) IND — — — — — — 14 OUTD Digital Output (comparator D) — — — — — 8 — CS Chip Select 1, 5, 8 — — — — 1, 5 — NC No Internal Connection 3.1 Analog Inputs 3.4 Power Supply (V and V ) SS DD The comparator non-inverting and inverting inputs are The positive power supply pin (V ) is 1.6V to 5.5V DD high-impedance CMOS inputs with low bias currents. higher than the negative power supply pin (V ). For SS normal operation, the other pins are at voltages 3.2 CS Digital Input between VSS and VDD. Typically, these parts are used in a single (positive) This is a CMOS, Schmitt-triggered input that places the supply configuration. In this case, V is connected to part into a low power mode of operation. SS ground and V is connected to the supply. V will DD DD need a local bypass capacitor (typically 0.01µF to 3.3 Digital Outputs 0.1µF) within 2mm of the V pin. These can share a DD The comparator outputs are CMOS, push-pull digital bulk capacitor with nearby analog parts (within outputs. They are designed to be compatible with 100mm), but it is not required. CMOS and TTL logic and are capable of driving heavy DC or capacitive loads. © 2006 Microchip Technology Inc. DS21696E-page 13

MCP6541/1R/1U/2/3/4 4.0 APPLICATIONS INFORMATION the resistors R and R limit the possible current drawn 1 2 out of the input pin. Diodes D and D prevent the input 1 2 The MCP6541/2/3/4 family of push-pull output compar- pin (V + and V –) from going too far above V . IN IN DD ators are fabricated on Microchip’s state-of-the-art When implemented as shown, resistors R and R also 1 2 CMOS process. They are suitable for a wide range of limit the current through D and D . 1 2 applications requiring very low power consumption. 4.1 Comparator Inputs VDD 4.1.1 PHASE REVERSAL D 1 The MCP6541/1R/1U/2/3/4 comparator family uses V + 1 CMOS transistors at the input. They are designed to prevent phase inversion when the input pins exceed R1 M–CP6G0X VOUT the supply voltages. Figure2-3 shows an input voltage D 2 exceeding both supplies with no resulting phase V inversion. 2 R R 2 3 4.1.2 INPUT VOLTAGE AND CURRENT LIMITS V –(minimum expected V ) SS 1 R ≥ 1 2mA The ESD protection on the inputs can be depicted as shown in Figure4-1. This structure was chosen to pro- V –(minimum expected V ) SS 2 tect the input transistors, and to minimize input bias R ≥ 2 2mA current (IB). The input ESD diodes clamp the inputs when they try to go more than one diode drop below FIGURE 4-2: Protecting the Analog Inputs. V . They also clamp any voltages that go too far SS above V ; their breakdown voltage is high enough to It is also possible to connect the diodes to the left of the DD allow normal operation, and low enough to bypass ESD resistors R1 and R2. In this case, the currents through events within the specified limits. the diodes D1 and D2 need to be limited by some other mechanism. The resistor then serves as in-rush current limiter; the DC current into the input pins (V + and IN VDD Bond VIN–) should be very small. Pad A significant amount of current can flow out of the inputs when the common mode voltage (V ) is below CM ground (V ); see Figure2-37. Applications that are SS V + Bond Input Bond V – high impedance may need to limit the useable voltage IN Pad Stage Pad IN range. 4.1.3 NORMAL OPERATION Bond The input stage of this family of devices uses two V SS Pad differential input stages in parallel: one operates at low input voltages and the other at high input voltages. With FIGURE 4-1: Simplified Analog Input ESD this topology, the input voltage is 0.3V above VDD and Structures. 0.3V below VSS. Therefore, the input offset voltage is measured at both V - 0.3V and V + 0.3V to ensure SS DD In order to prevent damage and/or improper operation proper operation. of these amplifiers, the circuits they are in must limit the The MCP6541/1R/1U/2/3/4 family has internally-set currents (and voltages) at the V + and V – pins (see IN IN hysteresis that is small enough to maintain input offset Absolute Maximum Ratings † at the beginning of accuracy (<7mV) and large enough to eliminate output Section1.0 “Electrical Characteristics”). Figure4-3 chattering caused by the comparator’s own input noise shows the recommended approach to protecting these voltage (200µV ). Figure4-3 depicts this behavior. inputs. The internal ESD diodes prevent the input pins p-p (V + and V –) from going too far below ground, and IN IN DS21696E-page 14 © 2006 Microchip Technology Inc.

MCP6541/1R/1U/2/3/4 4.4 Externally Set Hysteresis 8 25 7 VDD = 5.0V 20 Greater flexibility in selecting hysteresis (or input trip ge (V) 456 VOUT VIN– 5110 mV/div)05 pI(ninoppinuutts to-)r feifssf eeartcr vehodiel)tv aleogdwe -b(hVyig OuhSs )ia ninsgd teh hxeitg echren-nlaotelw rr e t(rsaipivs etporoarsign.ets). oInf pthuet a 1 Volt 23 -0ge (5 hysteresis voltage (VHYST) is the difference between Output -101 Hysteresis ---nput Volta211050 tcohhteha ettres aarinmndge t hwuthrsiep nr e dopunoceine tsisn .dp uyHnt yaissm tesicrlo eswsuilspy p mlrye ocdvuuirncrgee snp t.a oIstut attplhsueot I helps in systems where it is best not to cycle between -2 -25 -3 -30 states too frequently (e.g., air conditioner thermostatic Time (100 ms/div) control). FIGURE 4-3: The MCP6541/2/3/4 4.4.1 NON-INVERTING CIRCUIT comparators’ internal hysteresis eliminates Figure4-4 shows a non-inverting circuit for single- output chatter caused by input noise voltage. supply applications using just two resistors. The resulting hysteresis diagram is shown in Figure4-5. 4.2 Push-Pull Output The push-pull output is designed to be compatible with V DD CMOS and TTL logic, while the output transistors are configured to give rail-to-rail output performance. They V - are driven with circuitry that minimizes any switching REF current (shoot-through current from supply-to-supply) MCP654X VOUT when the output is transitioned from high-to-low, or from + low-to-high (see Figures2-15,2-18,2-32 through2-36 for more information). V IN 4.3 MCP6543 Chip Select (CS) R R 1 F The MCP6543 is a single comparator with Chip Select FIGURE 4-4: Non-inverting circuit with (CS). When CS is pulled high, the total current hysteresis for single-supply. consumption drops to 20pA (typ.); 1pA (typ.) flows through the CS pin, 1pA (typ.) flows through the out- put pin and 18pA (typ.) flows through the VDD pin, as VOUT shown in Figure1-1. When this happens, the V comparator output is put into a high-impedance state. DD V By pulling CS low, the comparator is enabled. If the CS OH pin is left floating, the comparator will not operate High-to-Low Low-to-High properly. Figure1-1 shows the output voltage and supply current response to a CS pulse. VOL VIN The internal CS circuitry is designed to minimize V SS glitches when cycling the CS pin. This helps conserve V V V V SS THL TLH DD power, which is especially important in battery-powered applications. FIGURE 4-5: Hysteresis Diagram for the Non-Inverting Circuit. The trip points for Figures4-4 and4-5 are: EQUATION 4-1: ⎛ R1⎞ ⎛R1⎞ V = V ⎜1+-------⎟ –V ⎜-------⎟ TLH REF⎝ RF⎠ OL⎝RF⎠ ⎛ R1⎞ ⎛R1⎞ V = V ⎜1+-------⎟ –V ⎜-------⎟ THL REF⎝ RF⎠ OH⎝RF⎠ V = trip voltage from low to high TLH V = trip voltage from high to low THL © 2006 Microchip Technology Inc. DS21696E-page 15

MCP6541/1R/1U/2/3/4 4.4.2 INVERTING CIRCUIT Where: Figure4-6 shows an inverting circuit for single-supply R R using three resistors. The resulting hysteresis diagram R = -------2-------3---- 23 R +R is shown in Figure4-7. 2 3 R V V = -----------3-------×V DD 23 R +R DD 2 3 V IN Using this simplified circuit, the trip voltage can be V DD MCP654X VOUT calculated using the following equation: R2 EQUATION 4-2: ⎛ R ⎞ R R3 RF VTHL = VOH⎝⎜R----2---3----+-2--3--R----F---⎠⎟ +V23⎝⎛R----2---3----+-F----R----F--⎠⎞ ⎛ R ⎞ R V = V ⎜------------2--3---------⎟ +V ⎛------------F----------⎞ TLH OL⎝R23+RF⎠ 23⎝R23+RF⎠ FIGURE 4-6: Inverting Circuit With V = trip voltage from low to high Hysteresis. TLH V = trip voltage from high to low THL V OUT Figure2-20 and Figure2-23 can be used to determine V DD typical values for V and V . OH OL V OH Low-to-High High-to-Low 4.5 Bypass Capacitors V V With this family of comparators, the power supply pin OL IN VSS (VDD for single supply) should have a local bypass V V V V capacitor (i.e., 0.01µF to 0.1µF) within 2mm for good SS TLH THL DD edge rate performance. FIGURE 4-7: Hysteresis Diagram for the Inverting Circuit. 4.6 Capacitive Loads In order to determine the trip voltages (VTHL and VTLH) Reasonable capacitive loads (e.g., logic gates) have for the circuit shown in Figure4-6, R2 and R3 can be little impact on propagation delay (see Figure2-31). simplified to the Thevenin equivalent circuit with The supply current increases with increasing toggle respect to VDD, as shown in Figure4-8. frequency (Figure2-19), especially with higher capacitive loads. V DD 4.7 Battery Life - In order to maximize battery life in portable applications, use large resistors and small capacitive MCP654X VOUT loads. Avoid toggling the output more than necessary. + Do not use Chip Select (CS) frequently to conserve V SS start-up power. Capacitive loads will draw additional power at start-up. V 23 R R 23 F FIGURE 4-8: Thevenin Equivalent Circuit. DS21696E-page 16 © 2006 Microchip Technology Inc.

MCP6541/1R/1U/2/3/4 4.8 PCB Surface Leakage 4.9 Unused Comparators In applications where low input bias current is critical, An unused amplifier in a quad package (MCP6544) PCB (Printed Circuit Board) surface leakage effects should be configured as shown in Figure4-10. This need to be considered. Surface leakage is caused by circuit prevents the output from toggling and causing humidity, dust or other contamination on the board. crosstalk. It uses the minimum number of components Under low humidity conditions, a typical resistance and draws minimal current (see Figure2-15 and between nearby traces is 1012Ω. A 5V difference would Figure2-18). cause 5pA of current to flow. This is greater than the MCP6541/1R/1U/2/3/4 family’s bias current at 25°C ¼ MCP6544 (1pA, typ.). The easiest way to reduce surface leakage is to use a VDD guard ring around sensitive pins (or traces). The guard ring is biased at the same voltage as the sensitive pin. An example of this type of layout is shown in Figure4-9. – V - V + IN IN V SS + FIGURE 4-10: Unused Comparators. Guard Ring FIGURE 4-9: Example Guard Ring Layout for Inverting Circuit. 1. Inverting Configuration (Figures4-6 and4-9): a. Connect the guard ring to the non-inverting input pin (V +). This biases the guard ring IN to the same reference voltage as the comparator (e.g., V /2 or ground). DD b. Connect the inverting pin (V –) to the input IN pad without touching the guard ring. 2. Non-inverting Configuration (Figure4-4): a. Connect the non-inverting pin (V +) to the IN input pad without touching the guard ring. b. Connect the guard ring to the inverting input pin (V –). IN © 2006 Microchip Technology Inc. DS21696E-page 17

MCP6541/1R/1U/2/3/4 4.10 Typical Applications 4.10.3 BISTABLE MULTI-VIBRATOR A simple bistable multi-vibrator design is shown in 4.10.1 PRECISE COMPARATOR Figure4-13. V needs to be between the power REF Some applications require higher DC precision. An supplies (V =GND and V ) to achieve oscillation. SS DD easy way to solve this problem is to use an amplifier The output duty cycle changes with V . REF (such as the MCP6041) to gain-up the input signal before it reaches the comparator. Figure4-11 shows an example of this approach. R1 R2 V REF VDD VDD V REF MCP6041 MCP6541 VOUT V DD V IN C R R1 R2 MCP654X VOUT 1 3 V REF FIGURE 4-13: Bistable Multi-vibrator. FIGURE 4-11: Precise Inverting Comparator. 4.10.2 WINDOWED COMPARATOR Figure4-12 shows one approach to designing a win- dowed comparator. The AND gate produces a logic ‘1’ when the input voltage is between V and V (where RB RT V > V ). RT RB V RT 1/2 MCP6542 V IN V 1/2 RB MCP6542 FIGURE 4-12: Windowed Comparator. DS21696E-page 18 © 2006 Microchip Technology Inc.

MCP6541/1R/1U/2/3/4 5.0 PACKAGING INFORMATION 5.1 Package Marking Information 5-Lead SC-70 (MCP6541) Example: I-Temp E-Temp Device Code Code XXNN Front) AB25 Front) YWW (Back) MCP6541U ABNN Note2 636 (Back) Note 1: I-Temp parts prior to March 2005 are marked “ABN” 2: SC-70-5 E-Temp parts not available at this release of this data sheet. 5-Lead SOT-23 (MCP6541, MCP6541R, MCP6541U) Example: I-Temp E-Temp Device Code Code XXNN MCP6541 ABNN GTNN AB25 MCP6541R AGNN GUNN MCP6541U — ATNN Note: Applies to 5-Lead SOT-23 8-Lead PDIP (300 mil) Example: XXXXXXXX MCP6541 MCP6541 XXXXXNNN I/P256 OR E/P^e3^256 YYWW 0636 0636 8-Lead SOIC (150 mil) Example: XXXXXXXX MCP6542 MCP6541E XXXXYYWW I/SN0636 OR SN^e^30636 NNN 256 256 8-Lead MSOP Example: XXXXXX 6543I YWWNNN 636256 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2006 Microchip Technology Inc. DS21696E-page 19

MCP6541/1R/1U/2/3/4 Package Marking Information (Continued) 14-Lead PDIP (300 mil) (MCP6544) Example: XXXXXXXXXXXXXX MCP6544-I/P XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN 0636256 MCP6544E/Pe3 OR 0636256 MCP6544 OR I/P^e^3 0636256 14-Lead SOIC (150 mil) (MCP6544) Example: XXXXXXXXXX MCP6544ISL XXXXXXXXXX XXXXXXXXXX YYWWNNN 0636256 MCP6544 OR E/SL^e^3 0636256 14-Lead TSSOP (MCP6544) Example: XXXXXXXX MCP6544I YYWW 0636 NNN 256 DS21696E-page 20 © 2006 Microchip Technology Inc.

MCP6541/1R/1U/2/3/4 5-Lead Plastic Small Outline Transistor (LT) (SC-70) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 D p B n 1 Q1 A2 A c A1 L Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 5 5 Pitch p .026 (BSC) 0.65 (BSC) Overall Height A .031 .043 0.80 1.10 Molded Package Thickness A2 .031 .039 0.80 1.00 Standoff A1 .000 .004 0.00 0.10 Overall Width E .071 .094 1.80 2.40 Molded Package Width E1 .045 .053 1.15 1.35 Overall Length D .071 .087 1.80 2.20 Foot Length L .004 .012 0.10 0.30 Top of Molded Pkg to Q1 .004 .016 0.10 0.40 Lead Shoulder Lead Thickness c .004 .007 0.10 0.18 Lead Width B .006 .012 0.15 0.30 * Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. BSC: Basic Dimension. Theoretically exact value shown without tolerances. See ASME Y14.5M JEITA (EIAJ) Standard: SC-70 Revised 07-19-05 Drawing No. C04-061 © 2006 Microchip Technology Inc. DS21696E-page 21

MCP6541/1R/1U/2/3/4 5-Lead Plastic Small Outline Transistor (OT) (SOT23) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 p B p1 D n 1 α c A A2 φ A1 L β Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 5 5 Pitch p .038 0.95 Outside lead pitch (basic) p1 .075 1.90 Overall Height A .035 .046 .057 0.90 1.18 1.45 Molded Package Thickness A2 .035 .043 .051 0.90 1.10 1.30 Standoff A1 .000 .003 .006 0.00 0.08 0.15 Overall Width E .102 .110 .118 2.60 2.80 3.00 Molded Package Width E1 .059 .064 .069 1.50 1.63 1.75 Overall Length D .110 .116 .122 2.80 2.95 3.10 Foot Length L .014 .018 .022 0.35 0.45 0.55 Foot Angle f 0 5 10 0 5 10 Lead Thickness c .004 .006 .008 0.09 0.15 0.20 Lead Width B .014 .017 .020 0.35 0.43 0.50 Mold Draft Angle Top a 0 5 10 0 5 10 Mold Draft Angle Bottom b 0 5 10 0 5 10 *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. EIAJ Equivalent: SC-74A Drawing No. C04-091 Revised 09-12-05 DS21696E-page 22 © 2006 Microchip Technology Inc.

MCP6541/1R/1U/2/3/4 8-Lead Plastic Dual In-line (P) – 300 mil (PDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 D 2 n 1 α E A A2 L c A1 β B1 p eB B Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch p .100 2.54 Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32 Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26 Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60 Overall Length D .360 .373 .385 9.14 9.46 9.78 Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43 Lead Thickness c .008 .012 .015 0.20 0.29 0.38 Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78 Lower Lead Width B .014 .018 .022 0.36 0.46 0.56 Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92 Mold Draft Angle Top α 5 10 15 5 10 15 Mold Draft Angle Bottom β 5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018 © 2006 Microchip Technology Inc. DS21696E-page 23

MCP6541/1R/1U/2/3/4 8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 p D 2 B n 1 h α 45° c A A2 φ β L A1 Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch p .050 1.27 Overall Height A .053 .061 .069 1.35 1.55 1.75 Molded Package Thickness A2 .052 .056 .061 1.32 1.42 1.55 Standoff § A1 .004 .007 .010 0.10 0.18 0.25 Overall Width E .228 .237 .244 5.79 6.02 6.20 Molded Package Width E1 .146 .154 .157 3.71 3.91 3.99 Overall Length D .189 .193 .197 4.80 4.90 5.00 Chamfer Distance h .010 .015 .020 0.25 0.38 0.51 Foot Length L .019 .025 .030 0.48 0.62 0.76 Foot Angle φ 0 4 8 0 4 8 Lead Thickness c .008 .009 .010 0.20 0.23 0.25 Lead Width B .013 .017 .020 0.33 0.42 0.51 Mold Draft Angle Top α 0 12 15 0 12 15 Mold Draft Angle Bottom β 0 12 15 0 12 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057 DS21696E-page 24 © 2006 Microchip Technology Inc.

MCP6541/1R/1U/2/3/4 8-Lead Plastic Micro Small Outline Package (MS) (MSOP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 e b c ϕ A A2 A1 L1 L Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e 0.65 BSC Overall Height A — — 1.10 Molded Package Thickness A2 0.75 0.85 0.95 Standoff A1 0.00 — 0.15 Overall Width E 4.90 BSC Molded Package Width E1 3.00 BSC Overall Length D 3.00 BSC Foot Length L 0.40 0.60 0.80 Footprint L1 0.95 REF Foot Angle ϕ 0° — 8° Lead Thickness c 0.08 — 0.23 Lead Width b 0.22 — 0.40 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing No. C04–111, Sept. 8, 2006 © 2006 Microchip Technology Inc. DS21696E-page 25

MCP6541/1R/1U/2/3/4 14-Lead Plastic Dual In-line (P) – 300 mil (PDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 D 2 n 1 α E A A2 c L A1 β B1 eB B p Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 14 14 Pitch p .100 2.54 Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32 Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26 Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60 Overall Length D .740 .750 .760 18.80 19.05 19.30 Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43 Lead Thickness c .008 .012 .015 0.20 0.29 0.38 Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78 Lower Lead Width B .014 .018 .022 0.36 0.46 0.56 Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92 Mold Draft Angle Top α 5 10 15 5 10 15 Mold Draft Angle Bottom β 5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-005 DS21696E-page 26 © 2006 Microchip Technology Inc.

MCP6541/1R/1U/2/3/4 14-Lead Plastic Small Outline (SL) – Narrow, 150 mil (SOIC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 p D 2 B n 1 α h 45° c A A2 φ A1 L β Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 14 14 Pitch p .050 1.27 Overall Height A .053 .061 .069 1.35 1.55 1.75 Molded Package Thickness A2 .052 .056 .061 1.32 1.42 1.55 Standoff § A1 .004 .007 .010 0.10 0.18 0.25 Overall Width E .228 .236 .244 5.79 5.99 6.20 Molded Package Width E1 .150 .154 .157 3.81 3.90 3.99 Overall Length D .337 .342 .347 8.56 8.69 8.81 Chamfer Distance h .010 .015 .020 0.25 0.38 0.51 Foot Length L .016 .033 .050 0.41 0.84 1.27 Foot Angle φ 0 4 8 0 4 8 Lead Thickness c .008 .009 .010 0.20 0.23 0.25 Lead Width B .014 .017 .020 0.36 0.42 0.51 Mold Draft Angle Top α 0 12 15 0 12 15 Mold Draft Angle Bottom β 0 12 15 0 12 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-065 Revised 7-20-06 © 2006 Microchip Technology Inc. DS21696E-page 27

MCP6541/1R/1U/2/3/4 14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 p D 2 n 1 B α A c φ β L A1 A2 Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 14 14 Pitch p .026 BSC 0.65 BSC Overall Height A .039 .041 .043 1.00 1.05 1.10 Molded Package Thickness A2 .033 .035 .037 0.85 0.90 0.95 Standoff A1 .002 .004 .006 0.05 0.10 0.15 Overall Width E .246 .251 .256 6.25 6.38 6.50 Molded Package Width E1 .169 .173 .177 4.30 4.40 4.50 Molded Package Length D .193 .197 .201 4.90 5.00 5.10 Foot Length L .020 .024 .028 0.50 0.60 0.70 Foot Angle φ 0° 4° 8° 0° 4° 8° Lead Thickness c .004 .006 .008 0.09 0.15 0.20 Lead Width B .007 .010 .012 0.19 0.25 0.30 Mold Draft Angle Top α 12° REF 12° REF Mold Draft Angle Bottom β 12° REF 12° REF * Controlling Parameter Notes: Dimensions D and E1 do not include mold fla sh or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. BSC: Basic Dimension. Theoretically exact value shown without tolerances. See ASME Y14.5M REF: Reference Dimension, usually without tole rance, for information purposes only. See ASME Y14.5M JEDEC Equivalent: MO-153 AB-1 Drawing No. C04-087 Revised: 08-17-05 DS21696E-page 28 © 2006 Microchip Technology Inc.

MCP6541/1R/1U/2/3/4 APPENDIX A: REVISION HISTORY Revision E (September 2006) The following is the list of modifications: 1. Added MCP6541U pinout for the SOT-23-5 package. 2. Clarified Absolute Maximum Analog Input Voltage and Current Specifications. 3. Added applications writeups on unused comparators. 4. Added disclaimer to package outline drawings. Revision D (May 2006) The following is the list of modifications: 1. Added E-temp parts. 2. Changed V temperature specification to HYST linear and quadratic temperature coefficients. 3. Changed specifications and plots for E-Temp. 4. Added Section 3.0 Pin Descriptions 5. Corrected package marking (See Section5.1 “Package Marking Information”) 6. Added Appendix A: Revision History. Revision C (September 2003) Revision B (November 2002) Revision A (March 2002) • Original Release of this Document. © 2006 Microchip Technology Inc. DS21696E-page 29

MCP6541/1R/1U/2/3/4 NOTES: DS21696E-page 30 © 2006 Microchip Technology Inc.

MCP6541/1R/1U/2/3/4 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. -X /XX Examples: a) MCP6541T-I/LT: Tape and Reel, Device Temperature Package Industrial Temperature, Range 5LD SC-70. b) MCP6541T-I/OT: Tape and Reel, Industrial Temperature, Device: MCP6541: Single Comparator 5LD SOT-23. MCP6541T: Single Comparator (Tape and Reel) (SC-70, SOT-23, SOIC, MSOP) c) MCP6541-E/P: Extended Temperature, MCP6541RT: Single Comparator (Rotated - Tape and 8LD PDIP. Reel) (SOT-23 only) d) MCP6541RT-I/OT:Tape and Reel, MCP6541UT: Single Comparator (Tape and Reel) Industrial Temperature, (SOT-23-5 is E-Temp only) MCP6542: Dual Comparator 5LD SOT23. MCP6542T: Dual Comparator e) MCP6541-E/SN: Extended Temperature, (Tape and Reel for SOIC and MSOP) 8LD SOIC. MCP6543: Single Comparator with CS f) MCP6541UT-E/OT:Tape and Reel, MCP6543T: Single Comparator with CS (Tape and Reel for SOIC and MSOP) Extended Temperature, MCP6544: Quad Comparator 5LD SOT23. MCP6544T: Quad Comparator (Tape and Reel for SOIC and TSSOP) a) MCP6542-I/MS: Industrial Temperature, 8LD MSOP. Temperature Range: I = -40°C to +85°C b) MCP6542T-I/MS: Tape and Reel, E * = -40°C to +125°C Industrial Temperature, * SC-70-5 E-Temp parts not available at this release of the 8LD MSOP. data sheet. c) MCP6542-I/P: Industrial Temperature, Package: LT = Plastic Package (SC-70), 5-lead 8LD PDIP. OT = Plastic Small Outline Transistor (SOT-23), 5-lead d) MCP6542-E/SN: Extended Temperature, MS = Plastic MSOP, 8-lead 8LD SOIC. P = Plastic DIP (300 mil Body), 8-lead, 14-lead SN = Plastic SOIC (150 mil Body), 8-lead SL = Plastic SOIC (150 mil Body), 14-lead (MCP6544) a) MCP6543-I/SN: Industrial Temperature, ST = Plastic TSSOP (4.4mm Body), 14-lead (MCP6544) 8LD SOIC. b) MCP6543T-I/SN: Tape and Reel, Industrial Temperature, 8LD SOIC. c) MCP6543-I/P: Industrial Temperature, 8LD PDIP. d) MCP6543-E/SN: Extended Temperature, 8LD SOIC. a) MCP6544T-I/SL: Tape and Reel, Industrial Temperature, 14LD SOIC. b) MCP6544T-E/SL: Tape and Reel, Extended Temperature, 14LD SOIC. c) MCP6544-I/P: Industrial Temperature, 14LD PDIP. d) MCP6544T-E/ST: Tape and Reel, Extended Temperature, 14LD TSSOP. © 2006 Microchip Technology Inc. DS21696E-page 31

MCP6541/1R/1U/2/3/4 NOTES: DS21696E-page 32 © 2006 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, Accuron, and may be superseded by updates. It is your responsibility to dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. PROMATE, PowerSmart, rfPIC, and SmartShunt are MICROCHIP MAKES NO REPRESENTATIONS OR registered trademarks of Microchip Technology Incorporated WARRANTIES OF ANY KIND WHETHER EXPRESS OR in the U.S.A. and other countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, INCLUDING BUT NOT LIMITED TO ITS CONDITION, SEEVAL, SmartSensor and The Embedded Control Solutions QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, CodeGuard, devices in life support and/or safety applications is entirely at dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, the buyer’s risk, and the buyer agrees to defend, indemnify and ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, hold harmless Microchip from any and all damages, claims, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active suits, or expenses resulting from such use. No licenses are Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit, conveyed, implicitly or otherwise, under any Microchip PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, intellectual property rights. PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2006, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company’s quality system processes and procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2006 Microchip Technology Inc. DS21696E-page 33

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: MCP6541-E/MS MCP6541-E/P MCP6541-E/SN MCP6541RT-E/OT MCP6541T-E/MS MCP6541T-E/OT MCP6541T-E/SN MCP6541UT-I/LT MCP6542-E/MS MCP6542-E/P MCP6542-E/SN MCP6542T-E/MS MCP6542T- E/SN MCP6543-E/MS MCP6543-E/P MCP6543-E/SN MCP6543T-E/MS MCP6543T-E/SN MCP6544-E/P MCP6544-E/SL MCP6544T-E/SL MCP6544T-E/ST