M MCP6541/2/3/4 Push-Pull Output Sub-Microamp Comparators Features Description • Low Quiescent Current: 600nA/comparator (typ.) The Microchip Technology Inc. MCP6541/2/3/4 family • Rail-to-Rail Input: V - 0.3V to V + 0.3V of comparators is offered in single (MCP6541), single SS DD with chip select (MCP6543), dual (MCP6542) and quad • CMOS/TTL-Compatible Output (MCP6544) configurations. The outputs are push-pull • Propagation Delay 4 µs (typ.) (CMOS/TTL-compatible) and are capable of driving • Wide Supply Voltage Range: 1.6V to 5.5V heavy DC or capacitive loads. • Available in Single, Dual and Quad These comparators are optimized for low power, single- • Single available in SOT-23-5, SC-70-5 packages supply operation with greater than rail-to-rail input • Chip Select (CS) with MCP6543 operation. The push-pull output of the MCP6541/2/3/4 • Low Switching Current family supports rail-to-rail output swing and interfaces • Internal Hysteresis: 3.3 mV (typ.) with TTL/CMOS logic. The internal input hysteresis eliminates output switching due to internal input noise • Industrial Temperature: -40°C to +85°C voltage, reducing current draw. The output limits supply current surges and dynamic power consumption while Typical Applications switching. This product family operates with a single- • Laptop Computers supply voltage as low as 1.6V and draws less than 1µA/ comparator of quiescent current. • Mobile Phones • Metering Systems The related MCP6546/7/8/9 family of comparators from Microchip has an open-drain output. Used with a pull-up • Hand-held Electronics resistor, these devices can be used as level-shifters for • RC Timers any desired voltage up to 10V and in wired-OR logic. • Alarm and Monitoring Circuits • Windowed Comparators • Multi-vibrators Related Devices • Open-Drain Output: MCP6546/7/8/9 Package Types MCP6541 MCP6541-R MCP6542 MCP6544 PDIP, SOIC, MSOP SOT-23-5 PDIP, SOIC, MSOP PDIP, SOIC, TSSOP NC 1 8 NC OUT 1 5 VSS OUTA 1 8 VDD OUTA 1 14 OUTD VIN– 2 -- 7 VDD VDD 2 + - VINA– 2 - + 7 OUTB VINA– 2 - + + - 13 VIND– VIN+ 3 ++ 6 OUT VIN+ 3 4 VIN– VINA+ 3 + - 6 VINB– VINA+ 3 12 VIND+ VSS 4 5 NC VSS 4 5 VINB+ VDD 4 11 VSS VINB+ 5 10 VINC+ MCP6541 MCP6543 VINB– 6 - + + - 9 VINC– SOT-23-5, SC-70-5 PDIP, SOIC, MSOP OUTB 7 8 OUTC OUT 1 5 VDD NC 1 8 CS VSS 2 VIN– 2 - 7 VDD + - VIN+ 3 4 VIN– VIN+ 3 + 6 OUT VSS 4 5 NC  2003 Microchip Technology Inc. DS21696C-page 1

MCP6541/2/3/4 1.0 ELECTRICAL † Notice: Stresses above those listed under “Maximum Rat- ings” may cause permanent damage to the device. This is a CHARACTERISTICS stress rating only and functional operation of the device at those or any other conditions above those indicated in the 1.1 Absolute Maximum Ratings † operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods V - V .........................................................................7.0V DD SS may affect device reliability. All inputs and outputs ......................V –0.3V to V +0.3V SS DD PIN FUNCTION TABLE Difference Input voltage .......................................|V - V | DD SS Output Short-Circuit Current .................................continuous NAME FUNCTION Current at Input Pins ....................................................±2mA V +, V +, V +, V +, Non-Inverting Inputs Current at Output and Supply Pins ............................±30mA IN INA INB INC V + IND Storage temperature.....................................-65°C to +150°C V –, V –, V –, V –, V – Inverting Inputs IN INA INB INC IND Maximum Junction Temperature (T )..........................+150°C J V Positive Power Supply DD ESD protection on all pins (HBM;MM)...................4kV; 400V V Negative Power Supply SS OUT, OUTA, OUTB, OUTC, Outputs OUTD CS Chip Select NC Not Connected DC CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, V = +1.6V to +5.5V, V = GND, T = +25°C,V + = V /2, DD SS A IN DD VIN– = VSS, and RL=100kΩ to VDD/2 (Refer to Figure1-3). Parameters Sym Min Typ Max Units Conditions Power Supply Supply Voltage V 1.6 — 5.5 V DD Quiescent Current per comparator I 0.3 0.6 1.0 µA I = 0 Q OUT Input Input Voltage Range V V −0.3 — V +0.3 V CMR SS DD Common Mode Rejection Ratio CMRR 55 70 — dB V = 5V, V = -0.3V to 5.3V DD CM Common Mode Rejection Ratio CMRR 50 65 — dB V = 5V, V = 2.5V to 5.3V DD CM Common Mode Rejection Ratio CMRR 55 70 — dB V = 5V, V = -0.3V to 2.5V DD CM Power Supply Rejection Ratio PSRR 63 80 — dB V = V CM SS Input Offset Voltage V -7.0 ±1.5 +7.0 mV V = V (Note1) OS CM SS Drift with Temperature ∆V /∆T — ±3 — µV/°C T = -40°C to +85°C, V = V OS A A CM SS Input Hysteresis Voltage V 1.5 3.3 6.5 mV V = V (Note1) HYST CM SS Drift with Temperature ∆V /∆T — 10 — µV/°C T = -40°C to +25°C, V = V HYST A A CM SS Drift with Temperature ∆V /∆T — 5 — µV/°C T = +25°C to +85°C, V = V HYST A A CM SS Input Bias Current I — 1 — pA V =V B CM SS Over-Temperature I — — 100 pA T = -40°C to +85°C, V = V B A CM SS (Note3) Input Offset Current I — ±1 — pA V =V OS CM SS Common Mode Input Impedance Z — 1013||4 — Ω||pF CM Differential Input Impedance Z — 1013||2 — Ω||pF DIFF Push-Pull Output High-Level Output Voltage V V −0.2 — — V I = -2 mA, V = 5V OH DD OUT DD Low-Level Output Voltage V — — V +0.2 V I = 2 mA, V = 5V OL SS OUT DD Short-Circuit Current I — ±50 — mA (Note2) SC Note 1: The input offset voltage is the center (average) of the input-referred trip points. The input hysteresis is the difference between the input-referred trip points. 2: Limit the output current to Absolute Maximum Rating of 30mA. 3: Input bias current over temperature is not tested for SC-70-5 package. DS21696C-page 2  2003 Microchip Technology Inc.

MCP6541/2/3/4 AC CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, V = +1.6V to +5.5V, V = GND, T = +25°C, V + = V /2, DD SS A IN DD Step = 200mV, Overdrive = 100mV, and C = 36pF (Refer to Figure1-2 and Figure1-3). L Parameters Sym Min Typ Max Units Conditions Rise Time t — 0.85 — µs R Fall Time t — 0.85 — µs F Propagation Delay (High-to-Low) t — 4 8 µs PHL Propagation Delay (Low-to-High) t — 4 8 µs PLH Propagation Delay Skew t — ±0.2 — µs (Note1) PDS Maximum Toggle Frequency f — 160 — kHz V = 1.6V MAX DD f — 120 — kHz V = 5.5V MAX DD Input Noise Voltage E — 200 — µV 10Hz to 100kHz N P-P Note 1: Propagation Delay Skew is defined as: t = t - t . PDS PLH PHL SPECIFICATIONS FOR MCP6543 CHIP-SELECT Electrical Specifications: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = VSS, and C = 36pF (Refer to Figures1-1 and 1-3). L Parameters Sym Min Typ Max Units Conditions CS Low Specifications CS Logic Threshold, Low V V — 0.2V V IL SS DD CS Input Current, Low I — 5.0 — pA CS = V CSL SS CS High Specifications CS Logic Threshold, High V 0.8V — V V IH DD DD CS Input Current, High I — 1 — pA CS = V CSH DD CS Input High, V Current I — 18 — pA CS = V DD DD DD CS Input High, GND Current I — -20 — pA CS = V SS DD Comparator Output Leakage I — 1 — pA V = V O(LEAK) OUT DD CS Dynamic Specifications CS Low to Comparator Output Low t — 2 50 ms CS = 0.2V to V = V /2, ON DD OUT DD Turn-on Time V – = V IN DD CS High to Comparator Output t — 10 — µs CS = 0.8V to V = V /2, OFF DD OUT DD High Z Turn-off Time V – = V IN DD CS Hysteresis V — 0.6 — V V = 5V CS_HYST DD CS VIL VIH VIN– 100mV t t ON OFF VIN+ = VDD/2 100mV tPHL VOUT Hi-Z Hi-Z t PLH V OH I -20pA, typ. -0.6µA, typ. -20pA, typ. SS V OUT 1pA, typ. 1pA, typ. VOL VOL I CS FIGURE 1-1: Timing Diagram for the CS FIGURE 1-2: Propagation Delay Timing Pin on the MCP6543. Diagram.  2003 Microchip Technology Inc. DS21696C-page 3

MCP6541/2/3/4 TEMPERATURE SPECIFICATIONS Electrical Specifications: Unless otherwise indicated, V = +1.6V to +5.5V and V = GND. DD SS Parameters Sym Min Typ Max Units Conditions Temperature Ranges Specified Temperature Range T -40 — +85 °C A Operating Temperature Range T -40 — +125 °C Note A Storage Temperature Range T -65 — +150 °C A Thermal Package Resistances Thermal Resistance, 5L-SC-70 θ — 331 — °C/W JA Thermal Resistance, 5L-SOT-23 θ — 256 — °C/W JA Thermal Resistance, 8L-PDIP θ — 85 — °C/W JA Thermal Resistance, 8L-SOIC θ — 163 — °C/W JA Thermal Resistance, 8L-MSOP θ — 206 — °C/W JA Thermal Resistance, 14L-PDIP θ — 70 — °C/W JA Thermal Resistance, 14L-SOIC θ — 120 — °C/W JA Thermal Resistance, 14L-TSSOP θ — 100 — °C/W JA Note: The MCP6541/2/3/4 operates over this extended temperature range, but with reduced performance. In any case, the Junction Temperature (T ) must not exceed the Absolute Maximum specification of +150°C. J 1.2 Test Circuit Configuration This test circuit configuration is used to determine the AC and DC specifications. V DD 200kΩ MCP654X 200kΩ 200kΩ VOUT 200kΩ 36pF V = 0V V = V SS IN SS FIGURE 1-3: AC and DC Test Circuit for the Push-Pull Output Comparators. DS21696C-page 4  2003 Microchip Technology Inc.

MCP6541/2/3/4 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = GND, R = 100kΩ to V /2, and C = 36pF. L DD L 14% 18% s 1200 Samples s 1200 Samples ence 12% VCM = VSS ence1146%% VCM = VSS urr 10% urr12% c c Oc 8% Oc10% e of 6% e of 8% entag 4% entag 46%% erc 2% erc 2% P P 0% 0% -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2 5.6 6.0 Input Offset Voltage (mV) Input Hysteresis Voltage (mV) FIGURE 2-1: Input Offset Voltage FIGURE 2-4: Input Hysteresis Voltage Histogram at V =V . Histogram at V =V . CM SS CM SS 16% 26% s 1200 Samples s24% 1200 Samples ccurrence111024%%% VCM = VSS ccurrence11226802%%%% VCM = VSS TA = +25°C to T+A8 5=° -C40°C to +25°C O O14% of 8% of 12% ge 6% ge 10% enta 4% enta 68%% Perc 2% Perc 24%% 0% 0% -14-12-10 -8 -6 -4 -2 0 2 4 6 8 10 12 14 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Input Offset Voltage Drift (µV/°C) Input Hysteresis Voltage Drift (µV/°C) FIGURE 2-2: Input Offset Voltage Drift FIGURE 2-5: Input Hysteresis Voltage Histogram at V =V . Drift Histogram. CM SS 500 6.0 V) 400 VCM = VSS mV) 5.5 VCM = VSS e (µ 230000 VDD = 1.6V ge ( 5.0 set Voltag -1100000 esis Volta 344...505 VVDDDD == 11..66VV Input Off ---432000000 VDD = 5.5V put Hyster 223...050 VDD = 5.5V -500 In 1.5 -40 -20 0 20 40 60 80 -40 -20 0 20 40 60 80 Ambient Temperature (°C) Ambient Temperature (°C) FIGURE 2-3: Input Offset Voltage vs. FIGURE 2-6: Input Hysteresis Voltage vs. Ambient Temperature at V =V . Ambient Temperature at V =V . CM SS CM SS  2003 Microchip Technology Inc. DS21696C-page 5

MCP6541/2/3/4 Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = GND, R = 100kΩ to V /2, and C = 36pF. L DD L 2.0 6.0 Voltage (mV) 0011....0505 VDD = 1.6V TA = +85°C s Voltage (mV) 4455....0505 VDD = 1.6V TTAA == ++8255°°CC ut Offset --10..05 TTAA == +-4205°°CC Hysteresi 233...505 Inp -1.5 put 2.0 TA = -40°C -2.0 In 1.5 4 2 0 2 4 6 8 0 2 4 6 8 0 4 2 0 2 4 6 8 0 2 4 6 8 0 0. 0. 0. 0. 0. 0. 0. 1. 1. 1. 1. 1. 2. 0. 0. 0. 0. 0. 0. 0. 1. 1. 1. 1. 1. 2. - - - - Common Mode Input Voltage (V) Common Mode Input Voltage (V) FIGURE 2-7: Input Offset Voltage vs. FIGURE 2-10: Input Hysteresis Voltage vs. Common Mode Input Voltage at V = 1.6V. Common Mode Input Voltage at V =1.6V. DD DD V) 12..50 VDD = 5.5V mV) 56..50 VDD = 5.5V e (m 1.0 age ( 5.0 et Voltag 00..05 TA = +85°C esis Volt 344...505 TA = +85°C Input Offs ----2110....0505 TA = +25°C TA = -40°C Input Hyster 1223....5050 TTAA == +-4205°°CC 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 0. 0. 0. 1. 1. 2. 2. 3. 3. 4. 4. 5. 5. 6. 0. 0. 0. 1. 1. 2. 2. 3. 3. 4. 4. 5. 5. 6. - - Common Mode Input Voltage (V) Common Mode Input Voltage (V) FIGURE 2-8: Input Offset Voltage vs. FIGURE 2-11: Input Hysteresis Voltage vs. Common Mode Input Voltage at V = 5.5V. Common Mode Input Voltage at V = 5.5V. DD DD 90 d 24 MRR, PSRR; Input Referre(dB) 667788050505 CCCMMPMSRRRRRRRR,, ,VV ,V VIINNINI++N+ +== = =-- 200 V...533SVVVS, tttVoooD 525D ...=353V VV1,,,. 6VVVVDDD DDDt o=== 5555....5000VVVV Input Current (pA) 111112202468022468 TVAD D= = + 58.55°VC InpIuntp Outf fBseiat sC Cuurrrernentt C 0 55 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -40 -20 0 20 40 60 80 Ambient Temperature (°C) Common Mode Input Voltage (V) FIGURE 2-9: CMRR, PSRR vs. Ambient FIGURE 2-12: Input Bias Current, Input Temperature at V = V . Offset Current vs. Common Mode Voltage at CM SS +85°C. DS21696C-page 6  2003 Microchip Technology Inc.

MCP6541/2/3/4 Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = GND, R = 100kΩ to V /2, and C = 36pF. L DD L 22 0.7 20 VDD = 5.5V TA = +85°C ent (pA) 11112468 VCM = VDD Input Bias Current Current arator)000...456 TTAA == +-4205°°CC nput Curr 10468 Input Offset uiescent µA/comp00..23 I 2 Current Q( 0.1 0 -2 0.0 25 35 45 55 65 75 85 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Ambient Temperature (°C) Power Supply Voltage (V) FIGURE 2-13: Input Bias Current, Input FIGURE 2-16: Quiescent Current vs. Offset Current vs. Ambient Temperature. Power Supply Voltage. 0.7 0.7 V = 5.5 V VDD = 5.5V 0.6 DD 0.6 Quiescent Current (µA/comparator) 0000....2345 VDD = 1.6 V Quiescent Current (µA/comparator)0000....2345 Sweep VIN+, VIN– = VDD/2 Sweep VIN–, VIN+ = VDD/2 0.1 0.1 0.0 0.0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 -40 -20 0 20 40 60 80 0. 0. 0. 1. 1. 2. 2. 3. 3. 4. 4. 5. 5. 6. - Ambient Temperature (°C) Common Mode Input Voltage (V) FIGURE 2-14: Quiescent Current vs. FIGURE 2-17: Quiescent Current vs. Ambient Temperature. Common Mode Input Voltage at V = 5V. DD 0.7 50 VDD = 1.6V nt 45 0.6 e Quiescent Current (µA/comparator) 00000.....12345 Sweep VIN+, VIN- = VDD/2 Sweep VIN-, VIN+ = VDD/2 utput Short Circuit Curr(mA)11223340505050 -IOSC, TA- =IO S +C8, 5T°AC =- I O+S2C5, °TCA = -40°C|+IOSC|, T|+AI O=S C+|,2 T5°AC = -40°C 0.0 O 5 |+IOSC|, TA = +85°C 4 2 0 2 4 6 8 0 2 4 6 8 0 0 -0. -0. 0. 0. 0. 0. 0. 1. 1. 1. 1. 1. 2. 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Common Mode Input Voltage (V) Power Supply Voltage (V) FIGURE 2-15: Quiescent Current vs. FIGURE 2-18: Output Short-Circuit Current Common Mode Input Voltage at V = 1.6V. vs. Power Supply Voltage. DD  2003 Microchip Technology Inc. DS21696C-page 7

MCP6541/2/3/4 Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = GND, R = 100kΩ to V /2, and C = 36pF. L DD L 1.0 1.0 ge Headroom (V)00000.....56789 VDD = 1VVV.OO6OLLVL---VVVSSSSSS,,, TTTAAA === ++-284550°°°CCC ge Headroom (V) 00000.....56789 VVVVDOOODLLL ---=VVV SSS5SSS.5,,, VTTTAAA === -++428055°°°CCC olta0.4 olta 0.4 V0.3 V 0.3 Output 00..12 VVVDDDDDD---VVVOOOHHH,,, TTTAAA === -++482055°°°CCC Output 00..12 V D V D D-VVDD-OVDH-OV, HTO, AHT ,= AT =-A4 =+0 2°+C58°5C°C 0.0 0.0 0.0 0.5 1.0 1.5 2.0 2.5 0 5 10 15 20 25 Output Current (mA) Output Current (mA) FIGURE 2-19: Output Voltage Headroom FIGURE 2-22: Output Voltage Headroom vs. Output Current at V =1.6V. vs. Output Current at V =5.5V. DD DD 45% 45% s 600 Samples s 600 Samples e40% e40% c 100 mV Overdrive c 100 mV Overdrive n n urre3305%% VCM = VDD/2 urre3305%% VCM = VDD/2 c c c c O25% O25% of 20% of 20% e e ag15% ag15% ent10% VDD = 1.6V VDD = 5.5V ent10% VDD = 1.6V VDD = 5.5V c c er 5% er 5% P P 0% 0% 0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8 High-to-Low Propagation Delay (µs) Low-to-High Propagation Delay (µs) FIGURE 2-20: High-to-Low Propagation FIGURE 2-23: Low-to-High Propagation Delay Histogram. Delay Histogram. 45% 8 s 600 Samples 100 mV Overdrive ccurrence334050%%% 1V0C0M m= VV DOD/v2erdrive elay (µs) 567 VCM = VtPDLDH/ 2@ VDD = 5.5V tPHL @ VDD = 5.5V O25% D of 20% on 4 entage 1105%% VDD = 5.5V VDD = 1.6V opagati 23 erc 5% Pr 1 tPLH @ VDD = 1.6V tPHL @ VDD = 1.6V P 0% 0 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 -40 -20 0 20 40 60 80 Propagation Delay Skew (µs) Ambient Temperature (°C) FIGURE 2-21: Propagation Delay Skew FIGURE 2-24: Propagation Delay vs. Histogram. Ambient Temperature. DS21696C-page 8  2003 Microchip Technology Inc.

MCP6541/2/3/4 Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = GND, R = 100kΩ to V /2, and C = 36pF. L DD L 1134 VCM = VDD/2 100 VCM = VDD/2 Delay (µs) 11101289 tPLH @ 10 mV Overdrive Delay (µs) tPHL @ VDD = 5tt.5PPHLVHL @@ VVDDDD == 11..66VV gation 567 ttPPHLHL @@ 1100 0m mVV O Ovveerdrdrirvieve gation 10 tPLH @ VDD = 5.5V a 4 a op 3 op Pr 2 tPHL @ 100 mV Overdrive Pr 1 0 1 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1 10 100 1000 Power Supply Voltage (V) Input Overdrive (mV) FIGURE 2-25: Propagation Delay vs. FIGURE 2-28: Propagation Delay vs. Input Power Supply Voltage. Overdrive. 8 8 VDD = 1.6V VDD = 5.5V s) 7 100 mV Overdrive s) 7 100 mV Overdrive µ µ y ( 6 y ( 6 a a Del 5 Del 5 tPHL n 4 tPLH n 4 atio 3 atio 3 tPLH pag 2 tPHL pag 2 o o Pr 1 Pr 1 0 0 4 2 0 2 4 6 8 0 2 4 6 8 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 0. 0. 0. 0. 0. 0. 0. 1. 1. 1. 1. 1. 2. 0. 0. 0. 1. 1. 2. 2. 3. 3. 4. 4. 5. 5. 6. - - - Common Mode Input Voltage (V) Common Mode Input Voltage (V) FIGURE 2-26: Propagation Delay vs. FIGURE 2-29: Propagation Delay vs. Common Mode Input Voltage at V = 1.6V. Common Mode Input Voltage at V = 5.5V. DD DD 50 100 mV Overdrive 10 Delay (µs) 33440505 VCM = VDD/2 tPHL @ VDD = 1.6V ent (µA) 1VR0CL0 M= m= In VVfiD nODi/vt2yerdrive VDD = 5.5 V Propagation 11220505 ttPPLHHL @@ VVDDDD == 15..65VV Supply Curr 1 VDD = 1.6 V 5 tPLH @ VDD = 5.5V 0 0.1 0 10 20 30 40 50 60 70 80 90 0.1 1 10 100 Load Capacitance (nF) Toggle Frequency (kHz) FIGURE 2-27: Propagation Delay vs. Load FIGURE 2-30: Supply Current vs. Toggle Capacitance. Frequency.  2003 Microchip Technology Inc. DS21696C-page 9

MCP6541/2/3/4 Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = GND, R = 100kΩ to V /2, and C = 36pF. L DD L Output Voltage (V) 34567 VDD = 5.5V VOUT utput Voltage (V) 23344556........50505050 VDD = 5V.O5UVT nput, 2 VIN– ect, O 12..50 erting I 01 hip Sel 001...050 CS Inv -1 C-0.5 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10 Time (1 ms/div) Time (ms) FIGURE 2-31: The MCP6541/2/3/4 FIGURE 2-34: Chip-Select (CS) Step comparators show no phase reversal. Response (MCP6543 only). mparator)110100µµµ111...EEE---000654 TuCronms pOanra Htoerre SChuotms pOafrfa Htoerre mparator)110100µµµ111...EEE---000654 TuCronms pOanra Htoerre ShCuotms pOafrfa Htoerre A/co100n1.E-07 CS Hysteresis A/Co100n1.E-07 CS Low-to-High CS High-to-Low Supply Current (101100npn111...EEE---100098 VDD = 1.6VCS High-to-Low CS Low-to-High Supply Current (110100nnp111...EEE---100098 VDD = 5.5V CS Hysteresis 10p1.E-11 10p1.E-11 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Chip Select (CS) Voltage (V) Chip Select (CS) Voltage (V) FIGURE 2-32: Supply Current (shoot FIGURE 2-35: Supply Current (shoot through current) vs. Chip-Select (CS) Voltage at through current) vs. Chip-Select (CS) Voltage at V = 1.6V (MCP6543 only). V = 5.5V (MCP6543 only). DD DD upply Current A/Comparator)11223050505 VDD = 1.C6Vhcaarpgaincgit aonucteput SVOtaUrTt-upC ISDD ----016431..06....5926Output Voltage, Chip Select Voltage (V), Supply Current (µA/Comparator)11111224680246800000000000 VDD = 5.5V VOCCUShTcaarSpgtaiancrgitt- auonpuc tIepDDut -------03621119631852Output Voltage, Chip Select Voltage (V) Sµ 0 -24 ( 0 -8.1 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Time (1 ms/div) Time (0.5 ms/div) FIGURE 2-33: Supply Current (charging FIGURE 2-36: Supply Current (charging current) vs. Chip-Select (CS) pulse at current) vs. Chip-Select (CS) pulse at V =1.6V (MCP6543 only). V =5.5V (MCP6543 only). DD DD DS21696C-page 10  2003 Microchip Technology Inc.

MCP6541/2/3/4 3.0 APPLICATIONS INFORMATION 3.3 MCP6543 Chip Select (CS) The MCP6541/2/3/4 family of push-pull output compar- The MCP6543 is a single comparator with chip select ators are fabricated on Microchip’s state-of-the-art (CS). When CS is pulled high, the total current CMOS process. They are suitable for a wide range of consumption drops to 20pA (typ); 1pA (typ) flows applications requiring very low power consumption. through the CS pin, 1pA (typ) flows through the output pin and 18pA (typ) flows through the V pin, as DD 3.1 Comparator Inputs shown in Figure1-1. When this happens, the comparator output is put into a high-impedance state. The MCP6541/2/3/4 comparator family uses CMOS By pulling CS low, the comparator is enabled. If the CS transistors at the input. They are designed to prevent pin is left floating, the comparator will not operate phase inversion when the input pins exceed the supply properly. Figure1-1 shows the output voltage and voltages. Figure2-31 shows an input voltage supply current response to a CS pulse. exceeding both supplies with no resulting phase The internal CS circuitry is designed to minimize inversion. glitches when cycling the CS pin. This helps conserve The input stage of this family of devices uses two power, which is especially important in battery- differential input stages in parallel: one operates at low powered applications. input voltages and the other at high input voltages. With this topology, the input voltage is 0.3V above V and DD 3.4 Externally-Set Hysteresis 0.3V below V . Therefore, the input offset voltage is SS measured at both VSS - 0.3V and VDD + 0.3V to ensure Greater flexibility in selecting hysteresis (or input trip proper operation. points) is achieved by using external resistors. The maximum operating input voltages that can be Input offset voltage (V ) is the center (average) of the OS applied are VSS - 0.3V and VDD + 0.3V. Voltages on the (input-referred) low-high and high-low trip points. Input inputs that exceed this absolute maximum rating can hysteresis voltage (V ) is the difference between HYST cause excessive current to flow and permanently the same trip points. Hysteresis reduces output damage the device. In applications where the input pin chattering when one input is slowly moving past the exceeds the specified range, external resistors can be other and thus reduces dynamic supply current. It also used to limit the current below ±2mA, as shown in helps in systems where it is best not to cycle between Figure3-1. states too frequently (e.g., air conditioner thermostatic control). The MCP6541/2/3/4 family has internally-set hysteresis that is small enough to maintain input offset accuracy (<7mV) and large enough to eliminate output RIN MCP654X VOUT chattering caused by the comparator’s own input noise voltage (200µVp-p). V IN 9 30 RRIINN≥≥(--V--M------S----a----S--x------i–--m--------(--u--M----m------i-- --n-e-----ix---m---p--22----ue-- ---c-mmm----t----e --AA--e-d---x--- ---pV------e--I----c--N--t----e--)----d---–--- ---V---V----I----D--N--------D-)--- Voltage (V) 345678 VVDIND+ == 5 +.V02V.O7U5TV Hysteresis 0511220505 ge (10 mV/div) FshIGouUlRd Eb e3 -u1s:ed to limAitn e inxpceust sreivseis itnopr u(tR cINu)r rent if Output 012 ---11550 put Volta either of the inputs exceeds the Absolute -1 VIN– -20 In -2 -25 Maximum specification. -3 0 100 200 300 400 500 600 700 800 900 1000-30 Time (100 ms/div) 3.2 Push-Pull Output FIGURE 3-2: The MCP6541/2/3/4 The push-pull output is designed to be compatible with comparators’ internal hysteresis eliminates CMOS and TTL logic, while the output transistors are output chatter caused by input noise voltage. configured to give rail-to-rail output performance. They are driven with circuitry that minimizes any switching current (shoot-through current from supply-to-supply) when the output is transitioned from high-to-low, or from low-to-high (see Figures2-15,2-17,2-32 through2-36 for more information).  2003 Microchip Technology Inc. DS21696C-page 11

MCP6541/2/3/4 3.4.1 NON-INVERTING CIRCUIT 3.4.2 INVERTING CIRCUIT Figure3-3 shows a non-inverting circuit for single- Figure3-5 shows an inverting circuit for single-supply supply applications using just two resistors. The using three resistors. The resulting hysteresis diagram resulting hysteresis diagram is shown in Figure3-4. is shown in Figure3-6. V V DD DD V V - IN REF V MCP654X VOUT DD MCP654X VOUT + R 2 V IN R R R R F 1 F 3 FIGURE 3-3: Non-inverting circuit with hysteresis for single-supply. FIGURE 3-5: Inverting Circuit With Hysteresis. V OUT VDD VOUT V OH V DD High-to-Low Low-to-High V OH Low-to-High High-to-Low VOL VIN V SS VSS VTHL VTLH VDD VOL VIN V SS V V V V SS TLH THL DD FIGURE 3-4: Hysteresis Diagram for the Non-Inverting Circuit. FIGURE 3-6: Hysteresis Diagram for the Inverting Circuit. The trip points for Figures3-3 and3-4 are: In order to determine the trip voltages (V and V ) THL TLH EQUATION for the circuit shown in Figure3-5, R and R can be 2 3 simplified to the Thevenin equivalent circuit with  R  R  V = V 1+-----1-- –V -----1-- respect to VDD, as shown in Figure3-7. TLH REF R  OLR  F F  R  R  V 1 1 DD V = V 1+------- –V ------- THL REF R  OHR  F F - V = trip voltage from low to high TLH MCP654X VOUT V = trip voltage from high to low THL + V SS V 23 R R 23 F FIGURE 3-7: Thevenin Equivalent Circuit. DS21696C-page 12  2003 Microchip Technology Inc.

MCP6541/2/3/4 Where: 3.8 PCB Surface Leakage R R In applications where low input bias current is critical, R = -------2-------3---- 23 R +R PCB (Printed Circuit Board) surface leakage effects 2 3 need to be considered. Surface leakage is caused by R humidity, dust or other contamination on the board. V = -----------3-------×V 23 R +R DD Under low humidity conditions, a typical resistance 2 3 between nearby traces is 1012Ω. A 5V difference would cause 5pA, if current-to-flow. This is greater than the Using this simplified circuit, the trip voltage can be MCP6541/2/3/4 family’s bias current at 25°C (1pA, calculated using the following equation: typ). The easiest way to reduce surface leakage is to use a EQUATION guard ring around sensitive pins (or traces). The guard VTHL = VOHR--------R---+-2--3--R------- +V23R--------R---+-F----R------ rAinng iesx baimaspeled aot ft hteh issa mtyep veo ltoafg ela ayso utht e isse nsshitoivwen p inin. 23 F 23 F Figure3-8. VTLH = VOLR--------R---+-2--3--R------- +V23R--------R---+-F----R------ V - V + 23 F 23 F IN IN V SS V = trip voltage from low to high TLH V = trip voltage from high to low THL Figure2-19 and Figure2-22 can be used to determine typical values for V and V . OH OL Guard Ring 3.5 Bypass Capacitors FIGURE 3-8: Example Guard Ring Layout With this family of comparators, the power supply pin for Inverting Circuit. (V for single supply) should have a local bypass DD capacitor (i.e., 0.01µF to 0.1µF) within 2mm for good 1. Inverting Configuration (Figures3-5 and3-8): edge rate performance. a. Connect the guard ring to the non-inverting input pin (V +). This biases the guard ring 3.6 Capacitive Loads IN to the same reference voltage as the Reasonable capacitive loads (e.g., logic gates) have comparator (e.g., VDD/2 or ground). little impact on propagation delay (see Figure2-27). b. Connect the inverting pin (V –) to the input IN The supply current increases with increasing toggle pad without touching the guard ring. frequency (Figure2-30), especially with higher 2. Non-inverting Configuration (Figure3-3): capacitive loads. a. Connect the non-inverting pin (V +) to the IN input pad without touching the guard ring. 3.7 Battery Life b. Connect the guard ring to the inverting input In order to maximize battery life in portable pin (V –). IN applications, use large resistors and small capacitive loads. Also, avoid toggling the output more than necessary and do not use chip select (CS) to conserve power for short periods of time. Capacitive loads will draw additional power at start-up.  2003 Microchip Technology Inc. DS21696C-page 13

MCP6541/2/3/4 3.9 Typical Applications 3.9.3 BISTABLE MULTI-VIBRATOR A simple bistable multi-vibrator design is shown in 3.9.1 PRECISE COMPARATOR Figure3-11. V needs to be between the power REF Some applications require higher DC precision. An supplies (V =GND and V ) to achieve oscillation. SS DD easy way to solve this problem is to use an amplifier The output duty cycle changes with V . REF (such as the MCP6041) to gain-up the input signal before it reaches the comparator. Figure3-9 shows an example of this approach. R1 R2 V REF VDD VDD V REF MCP6041 MCP6541 VOUT V DD V IN C R R1 R2 MCP654X VOUT 1 3 V REF FIGURE 3-11: Bistable Multi-vibrator. FIGURE 3-9: Precise Inverting Comparator. 3.9.2 WINDOWED COMPARATOR Figure3-10 shows one approach to designing a win- dowed comparator. The AND gate produces a logic ‘1’ when the input voltage is between V and V (where RB RT V > V ). RT RB V RT 1/2 MCP6542 V IN V 1/2 RB MCP6542 FIGURE 3-10: Windowed Comparator. DS21696C-page 14  2003 Microchip Technology Inc.

MCP6541/2/3/4 4.0 PACKAGING INFORMATION 4.1 Package Marking Information 5-Lead SC-70 (MCP6541) Example: XNN A25 YWW 307 5-Lead SOT-23 (MCP6541) Example: XXNN AB37 8-Lead PDIP (300 mil) Example: XXXXXXXX MCP6541 XXXXXNNN I/P256 YYWW 0307 8-Lead SOIC (150 mil) Example: XXXXXXXX MCP6542 XXXXYYWW I/SN0307 NNN 256 8-Lead MSOP Example: XXXXXX 6543I YWWNNN 307256 Legend: XX...X Customer specific information* YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard marking consists of Microchip part number, year code, week code, traceability code (facility code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please check with your Microchip Sales Office.  2003 Microchip Technology Inc. DS21696C-page 15

MCP6541/2/3/4 Package Marking Information (Continued) 14-Lead PDIP (300 mil) (MCP6544) Example: XXXXXXXXXXXXXX MCP6544-I/P XXXXXXXXXXXXXX YYWWNNN 0307256 14-Lead SOIC (150 mil) (MCP6544) Example: XXXXXXXXXX MCP6544ISL XXXXXXXXXX YYWWNNN 0307256 14-Lead TSSOP (MCP6544) Example: XXXXXXXX MCP6544I YYWW 0307 NNN 256 DS21696C-page 16  2003 Microchip Technology Inc.

MCP6541/2/3/4 5-Lead Plastic Package (LT) (SC-70) E E1 D p B n 1 Q1 A2 A c A1 L Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 5 5 Pitch p .026 (BSC) 0.65 (BSC) Overall Height A .031 .043 0.80 1.10 Molded Package Thickness A2 .031 .039 0.80 1.00 Standoff A1 .000 .004 0.00 0.10 Overall Width E .071 .094 1.80 2.40 Molded Package Width E1 .045 .053 1.15 1.35 Overall Length D .071 .087 1.80 2.20 Foot Length L .004 .012 0.10 0.30 Top of Molded Pkg to Lead Shoulder Q1 .004 .016 0.10 0.40 Lead Thickness c .004 .007 0.10 0.18 Lead Width B .006 .012 0.15 0.30 *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. JEITA (EIAJ) Standard: SC-70 Drawing No. C04-061  2003 Microchip Technology Inc. DS21696C-page 17

MCP6541/2/3/4 5-Lead Plastic Small Outline Transistor (OT) (SOT23) E E1 p B p1 D n 1 α c A A2 φ A1 β L Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 5 5 Pitch p .038 0.95 Outside lead pitch (basic) p1 .075 1.90 Overall Height A .035 .046 .057 0.90 1.18 1.45 Molded Package Thickness A2 .035 .043 .051 0.90 1.10 1.30 Standoff § A1 .000 .003 .006 0.00 0.08 0.15 Overall Width E .102 .110 .118 2.60 2.80 3.00 Molded Package Width E1 .059 .064 .069 1.50 1.63 1.75 Overall Length D .110 .116 .122 2.80 2.95 3.10 Foot Length L .014 .018 .022 0.35 0.45 0.55 Foot Angle φ 0 5 10 0 5 10 Lead Thickness c .004 .006 .008 0.09 0.15 0.20 Lead Width B .014 .017 .020 0.35 0.43 0.50 Mold Draft Angle Top α 0 5 10 0 5 10 Mold Draft Angle Bottom β 0 5 10 0 5 10 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-178 Drawing No. C04-091 DS21696C-page 18  2003 Microchip Technology Inc.

MCP6541/2/3/4 8-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n 1 α E A A2 L c A1 β B1 p eB B Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch p .100 2.54 Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32 Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26 Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60 Overall Length D .360 .373 .385 9.14 9.46 9.78 Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43 Lead Thickness c .008 .012 .015 0.20 0.29 0.38 Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78 Lower Lead Width B .014 .018 .022 0.36 0.46 0.56 Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92 Mold Draft Angle Top α 5 10 15 5 10 15 Mold Draft Angle Bottom β 5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018  2003 Microchip Technology Inc. DS21696C-page 19

MCP6541/2/3/4 8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 h α 45° c A A2 φ β L A1 Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch p .050 1.27 Overall Height A .053 .061 .069 1.35 1.55 1.75 Molded Package Thickness A2 .052 .056 .061 1.32 1.42 1.55 Standoff § A1 .004 .007 .010 0.10 0.18 0.25 Overall Width E .228 .237 .244 5.79 6.02 6.20 Molded Package Width E1 .146 .154 .157 3.71 3.91 3.99 Overall Length D .189 .193 .197 4.80 4.90 5.00 Chamfer Distance h .010 .015 .020 0.25 0.38 0.51 Foot Length L .019 .025 .030 0.48 0.62 0.76 Foot Angle φ 0 4 8 0 4 8 Lead Thickness c .008 .009 .010 0.20 0.23 0.25 Lead Width B .013 .017 .020 0.33 0.42 0.51 Mold Draft Angle Top α 0 12 15 0 12 15 Mold Draft Angle Bottom β 0 12 15 0 12 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057 DS21696C-page 20  2003 Microchip Technology Inc.

MCP6541/2/3/4 8-Lead Plastic Micro Small Outline Package (MS) (MSOP) E E1 p D 2 B n 1 α A A2 c φ A1 (F) L β Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch p .026 BSC 0.65 BSC Overall Height A - - .043 - - 1.10 Molded Package Thickness A2 .030 .033 .037 0.75 0.85 0.95 Standoff A1 .000 - .006 0.00 - 0.15 Overall Width E .193 TYP. 4.90 BSC Molded Package Width E1 .118 BSC 3.00 BSC Overall Length D .118 BSC 3.00 BSC Foot Length L .016 .024 .031 0.40 0.60 0.80 Footprint (Reference) F .037 REF 0.95 REF Foot Angle φ 0° - 8° 0° - 8° Lead Thickness c .003 .006 .009 0.08 - 0.23 Lead Width B .009 .012 .016 0.22 - 0.40 Mold Draft Angle Top α 5° - 15° 5° - 15° Mold Draft Angle Bottom β 5° - 15° 5° - 15° *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MO-187 Drawing No. C04-111  2003 Microchip Technology Inc. DS21696C-page 21

MCP6541/2/3/4 14-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n 1 α E A A2 c L A1 β B1 eB B p Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 14 14 Pitch p .100 2.54 Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32 Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26 Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60 Overall Length D .740 .750 .760 18.80 19.05 19.30 Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43 Lead Thickness c .008 .012 .015 0.20 0.29 0.38 Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78 Lower Lead Width B .014 .018 .022 0.36 0.46 0.56 Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92 Mold Draft Angle Top α 5 10 15 5 10 15 Mold Draft Angle Bottom β 5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-005 DS21696C-page 22  2003 Microchip Technology Inc.

MCP6541/2/3/4 14-Lead Plastic Small Outline (SL) – Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 α h 45° c A A2 φ A1 L β Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 14 14 Pitch p .050 1.27 Overall Height A .053 .061 .069 1.35 1.55 1.75 Molded Package Thickness A2 .052 .056 .061 1.32 1.42 1.55 Standoff § A1 .004 .007 .010 0.10 0.18 0.25 Overall Width E .228 .236 .244 5.79 5.99 6.20 Molded Package Width E1 .150 .154 .157 3.81 3.90 3.99 Overall Length D .337 .342 .347 8.56 8.69 8.81 Chamfer Distance h .010 .015 .020 0.25 0.38 0.51 Foot Length L .016 .033 .050 0.41 0.84 1.27 Foot Angle φ 0 4 8 0 4 8 Lead Thickness c .008 .009 .010 0.20 0.23 0.25 Lead Width B .014 .017 .020 0.36 0.42 0.51 Mold Draft Angle Top α 0 12 15 0 12 15 Mold Draft Angle Bottom β 0 12 15 0 12 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-065  2003 Microchip Technology Inc. DS21696C-page 23

MCP6541/2/3/4 14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP) E E1 p D 2 n 1 B α A c φ β A1 A2 L Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 14 14 Pitch p .026 0.65 Overall Height A .043 1.10 Molded Package Thickness A2 .033 .035 .037 0.85 0.90 0.95 Standoff § A1 .002 .004 .006 0.05 0.10 0.15 Overall Width E .246 .251 .256 6.25 6.38 6.50 Molded Package Width E1 .169 .173 .177 4.30 4.40 4.50 Molded Package Length D .193 .197 .201 4.90 5.00 5.10 Foot Length L .020 .024 .028 0.50 0.60 0.70 Foot Angle φ 0 4 8 0 4 8 Lead Thickness c .004 .006 .008 0.09 0.15 0.20 Lead Width B1 .007 .010 .012 0.19 0.25 0.30 Mold Draft Angle Top α 0 5 10 0 5 10 Mold Draft Angle Bottom β 0 5 10 0 5 10 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005” (0.127mm) per side. JEDEC Equivalent: MO-153 Drawing No. C04-087 DS21696C-page 24  2003 Microchip Technology Inc.

MCP6541/2/3/4 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. -X /XX Examples: a) MCP6541T-I/LT: Tape and Reel, Device Temperature Package Industrial Temperature, Range 5LD SC-70. b) MCP6541T-I/OT: Tape and Reel, Industrial Temperature, Device: MCP6541: Single Comparator MCP6541T: Single Comparator (Tape and Reel) 5LD SOT-23. (SC-70, SOT-23, SOIC, MSOP) c) MCP6541-I/P: Industrial Temperature, MCP6541RT:Single Comparator (Rotated - Tape and 8LD PDIP. Reel) (SOT-23 only) d) MCP6541RT-I/OT:Tape and Reel, MCP6542: Dual Comparator MCP6542T: Dual Comparator Industrial Temperature, (Tape and Reel for SOIC and MSOP) 5LD SOT23. MCP6543: Single Comparator with CS MCP6543T: Single Comparator with CS a) MCP6542-I/MS: Industrial Temperature, (Tape and Reel for SOIC and MSOP) MCP6544: Quad Comparator 8LD MSOP. MCP6544T: Quad Comparator b) MCP6542T-I/MS: Tape and Reel, (Tape and Reel for SOIC and TSSOP) Industrial Temperature, 8LD MSOP. Temperature Range: I = -40°C to +85°C c) MCP6542-I/P: Industrial Temperature, 8LD PDIP. Package: LT = Plastic Package (SC-70), 5-lead OT = Plastic Small Outline Transistor (SOT-23), 5-lead MS = Plastic MSOP, 8-lead a) MCP6543-I/SN: Industrial Temperature, P = Plastic DIP (300 mil Body), 8-lead, 14-lead 8LD SOIC. SN = Plastic SOIC (150 mil Body), 8-lead b) MCP6543T-I/SN: Tape and Reel, SL = Plastic SOIC (150 mil Body), 14-lead (MCP6544) ST = Plastic TSSOP (4.4mm Body), 14-lead (MCP6544) Industrial Temperature, 8LD SOIC. c) MCP6543-I/P: Industrial Temperature, 8LD PDIP. a) MCP6544T-I/SL: Tape and Reel, Industrial Temperature, 14LD SOIC. b) MCP6544T-I/SL: Tape and Reel, Industrial Temperature, 14LD SOIC. c) MCP6544-I/P: Industrial Temperature, 14LD PDIP. Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office 2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 3. The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.  2003 Microchip Technology Inc. DS21696C-page 25

MCP6541/2/3/4 NOTES: DS21696C-page 26  2003 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to The Microchip name and logo, the Microchip logo, dsPIC, ensure that your application meets with your specifications. KEELOQ, MPLAB, PIC, PICmicro, PICSTART, PRO MATE and No representation or warranty is given and no liability is PowerSmart are registered trademarks of Microchip assumed by Microchip Technology Incorporated with respect Technology Incorporated in the U.S.A. and other countries. to the accuracy or use of such information, or infringement of FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL patents or other intellectual property rights arising from such and The Embedded Control Solutions Company are use or otherwise. Use of Microchip’s products as critical registered trademarks of Microchip Technology Incorporated components in life support systems is not authorized except in the U.S.A. with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual Accuron, Application Maestro, dsPICDEM, dsPICDEM.net, property rights. ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In- Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICC, PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPIC, Select Mode, SmartSensor, SmartShunt, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2003, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified. DS21696C-page 27  2003 Microchip Technology Inc.

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: MCP6543-I/SN MCP6543-I/MS MCP6544-I/SL MCP6544-I/ST MCP6541-I/SN MCP6541-I/MS MCP6542-I/P MCP6544-I/P MCP6541-I/P MCP6542-I/SN MCP6543-I/P MCP6541RT-I/OT MCP6542-I/MS MCP6544T-I/ST MCP6544T-I/SL MCP6543T-I/SN MCP6542T-I/SN MCP6541T-I/MS MCP6542T-I/MS MCP6541T-I/OT MCP6543T- I/MS MCP6541T-I/SN