MCP6491/2/4 7.5 MHz, Low-Input Bias Current Op Amps Features Description • Low-Input Bias Current The Microchip MCP6491/2/4 family of operational - 150pA (typical, T = +125°C) amplifiers (op amps) has low-input bias current A (150pA, typical at 125°C) and rail-to-rail input and • Low Quiescent Current output operation. This family is unity gain stable and - 530µA/amplifier (typical) has a gain bandwidth product of 7.5MHz (typical). • Low-Input Offset Voltage These devices operate with a single-supply voltage as - ±1.5mV (maximum) low as 2.4V, while only drawing 530µA/amplifier • Supply Voltage Range: 2.4V to 5.5V (typical) of quiescent current. These features make the • Rail-to-Rail Input/Output family of op amps well suited for photodiode amplifier, pH electrode amplifier, low leakage amplifier, and • Gain Bandwidth Product: 7.5MHz (typical) battery-powered signal conditioning applications, etc. • Slew Rate: 6V/µs (typical) The MCP6491/2/4 family is offered in single • Unity Gain Stable (MCP6491), dual (MCP6492), quad (MCP6494) • No Phase Reversal packages. All devices are designed using an advanced • Small Packages CMOS process and fully specified in extended - Singles in SC70-5, SOT-23-5 temperature range from -40°C to +125°C. • Extended Temperature Range Related Parts - -40°C to +125°C • MCP6471/2/4: 2MHz, Low-Input Bias Current Op Applications Amps • Photodiode Amplifier • MCP6481/2/4: 4MHz, Low-Input Bias Current Op Amps • pH Electrode Amplifier • Low Leakage Amplifier • Piezoelectric Transducer Amplifier • Active Analog Filter • Battery-Powered Signal Conditioning Design Aids • SPICE Macro Models • FilterLab® Software • MAPS (Microchip Advanced Part Selector) • Analog Demonstration and Evaluation Boards • Application Notes Package Types MCP6491 MCP6492 MCP6492 MCP6494 SC70, SOT-23 SOIC, MSOP 2x3TDFN* SOIC, TSSOP VOUT 11 55 VDD VOUTA 1 8 VDD VOUTA 1 8 VDD VOUTA 1 14VOUTD VSS 22 VINA– 2 7 VOUTB VINA– 2 EP 7 VOUTB VINA– 2 13VIND– VIN+ 33 44 VIN– VINA+ 3 6 VINB– VINA+ 3 9 6 VINB– VINA+ 3 12VIND+ VSS 4 5 VINB+ VSS 4 5 VINB+ VDD 4 11 VSS VINB+ 5 10 VINC+ VINB– 6 9 VINC– * Includes Exposed Thermal Pad (EP); see Table3-1. VOUTB 7 8 VOUTC  2012-2013 Microchip Technology Inc. DS20002321C-page 1

MCP6491/2/4 Typical Application C 2 R 2 V OUT I V D1 DD – Light D1 MCP649X + Photodiode Amplifier DS20002321C-page 2  2012-2013 Microchip Technology Inc.

MCP6491/2/4 1.0 ELECTRICAL CHARACTERISTICS 1.1 Absolute Maximum Ratings † V –V .........................................................................................................................................................................................6.5V DD SS Current at Input Pins......................................................................................................................................................................±2mA Analog Inputs (V +, V -) (Note1).................................................................................................................V –1.0V to V +1.0V IN IN SS DD All Other Inputs and Outputs ...........................................................................................................................V –0.3V to V +0.3V SS DD Difference Input Voltage...........................................................................................................................................................V –V DD SS Output Short-Circuit Current...................................................................................................................................................continuous Current at Output and Supply Pins .............................................................................................................................................±60mA Storage Temperature.....................................................................................................................................................-65°C to +150°C Maximum Junction Temperature (T )...........................................................................................................................................+150°C J ESD protection on all pins (HBM)4kV Note1: See Section4.1.2, Input Voltage Limits. † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 1.2 Specifications TABLE 1-1: DC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, V =+2.4V to +5.5V, V =GND, T =+25°C, DD SS A V =V /2, V V /2, V =V /2 and R =10kto V . (Refer to Figure1-1). CM DD OUT DD L DD L L Parameters Sym Min Typ Max Units Conditions Input Offset Input Offset Voltage V -1.5 — +1.5 mV V =3.0V, V =V /4 OS DD CM DD Input Offset Drift with Temperature V /T — ±2.5 — µV/°C T =-40°C to +125°C OS A A Power Supply Rejection Ratio PSRR 75 90 — dB V =V /4 CM DD Input Bias Current and Impedance Input Bias Current I — ±1 — pA B — 8 — pA T =+85°C A — 150 350 pA T =+125°C A Input Offset Current I — ±0.1 — pA OS Common Mode Input Impedance Z — 1013||6 — ||pF CM Differential Input Impedance Z — 1013||6 — ||pF DIFF Common Mode Common Mode Input Voltage V V -0.3 — V +0.3 V CMR SS DD Range Common Mode Rejection Ratio CMRR 65 84 — dB V =-0.3V to 2.7V, CM V =2.4V DD 70 88 — dB V =-0.3V to 5.8V, CM V =5.5V DD Open-Loop Gain DC Open-Loop Gain (Large Signal) A 95 115 — dB 0.2V<V <(V –0.2V) OL OUT DD V =5.5V, V =V DD CM SS  2012-2013 Microchip Technology Inc. DS20002321C-page 3

MCP6491/2/4 TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise indicated, V =+2.4V to +5.5V, V =GND, T =+25°C, DD SS A V =V /2, V V /2, V =V /2 and R =10kto V . (Refer to Figure1-1). CM DD OUT DD L DD L L Parameters Sym Min Typ Max Units Conditions Output High-Level Output Voltage V 2.380 2.396 — V V =2.4V OH DD 0.5V input overdrive 5.480 5.493 — V V =5.5V DD 0.5V input overdrive Low-Level Output Voltage V — 0.004 0.020 V V =2.4V OL DD 0.5V input overdrive — 0.007 0.020 V V =5.5V DD 0.5V input overdrive Output Short-Circuit Current I — ±15 — mA V =2.4V SC DD — ±40 — mA V =5.5V DD Power Supply Supply Voltage V 2.4 — 5.5 V DD Quiescent Current per Amplifier I 200 530 800 µA I =0, V =V /4 Q O CM DD TABLE 1-2: AC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, T =+25°C, V =+2.4V to +5.5V, V =GND, A DD SS V =V /2, V V /2, V =V /2, R =10kto V and C = 20pF. (Refer to Figure1-1). CM DD OUT DD L DD L L L Parameters Sym Min Typ Max Units Conditions AC Response Gain Bandwidth Product GBWP — 7.5 — MHz Phase Margin PM — 57 — ° G=+1V/V Slew Rate SR — 6 — V/µs Noise Input Noise Voltage E — 6 — µVp-p f=0.1Hz to 10Hz ni Input Noise Voltage Density e — 19 — nV/Hz f=1kHz ni — 14 — nV/Hz f=10kHz Input Noise Current Density i — 0.6 — fA/Hz f=1kHz ni TABLE 1-3: TEMPERATURE SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, V =+2.4V to +5.5V and V =GND. DD SS Parameters Sym Min Typ Max Units Conditions Temperature Ranges Operating Temperature Range T -40 — +125 °C Note1 A Storage Temperature Range T -65 — +150 °C A Thermal Package Resistances Thermal Resistance, 5L-SC-70  — 331 — °C/W JA Thermal Resistance, 5L-SOT-23  — 256 — °C/W JA Thermal Resistance, 8L-2x3 TDFN  — 52.5 — °C/W JA Thermal Resistance, 8L-MSOP  — 211 — °C/W JA Thermal Resistance, 8L-SOIC  — 149.5 — °C/W JA Thermal Resistance, 14L-SOIC  — 95.3 — °C/W JA Thermal Resistance, 14L-TSSOP  — 100 — °C/W JA Note1: The internal junction temperature (T ) must not exceed the absolute maximum specification of +150°C. J DS20002321C-page 4  2012-2013 Microchip Technology Inc.

MCP6491/2/4 1.3 Test Circuits C The circuit used for most DC and AC tests is shown in F 6.8pF Figure1-1. This circuit can independently set V and CM V (refer to Equation1-1). Note that V is not the OUT CM circuit’s common mode voltage ((VP+VM)/2), and that RG RF V includes V plus the effects (on the input offset 100k 100k OST OS error, VOST) of temperature, CMRR, PSRR and AOL. VP VDD/2 V DD V EQUATION 1-1: IN+ C C B1 B2 GDM = RFRG MCP649X 100nF 1µF V = V +V 22 CM P DD VOST = VIN+–VIN– VIN– VOUT = VDD2+VP–VM+VOST1+GDM VM VOUT Where: RG RF RL CL 100k 100k 10k 20pF G = Differential Mode Gain (V/V) DM V = Op Amp’s Common Mode (V) CM C Input Voltage F 6.8pF VL V = Op Amp’s Total Input Offset (mV) OST Voltage FIGURE 1-1: AC and DC Test Circuit for Most Specifications.  2012-2013 Microchip Technology Inc. DS20002321C-page 5

MCP6491/2/4 NOTES: DS20002321C-page 6  2012-2013 Microchip Technology Inc.

MCP6491/2/4 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, T =+25°C, V =+2.4V to +5.5V, V =GND, V =V /2, V V /2, A DD SS CM DD OUT DD V =V /2, R =10kto V and C =20pF. L DD L L L s 18% 1000 currence 1125%% 2VV7DC0DM =S= a3Vm.D0DpV/l4 e s age (µV) 468000000 +++-48210255°5°°CCC°C Oc olt 200 age of 69%% Offset V -2000 ent 3% ut pu --440000 Perc 0% In --860000 VRDeDpr=e 5s.e5nVtative Part 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1000 2 0 8 6 4 2 2 4 6 8 0 2 1 1 - - - - 1 1 5 0 5 0 5 0 5 0 5 0 5 0 5 0 - - 0. 0. 0. 1. 1. 2. 2. 3. 3. 4. 4. 5. 5. 6. Input Offset Voltage (µV) - Common Mode Input Voltage (V) FIGURE 2-1: Input Offset Voltage. FIGURE 2-4: Input Offset Voltage vs. Common Mode Input Voltage. 18% 1000 ntage of Occurrences 116925%%%% T2VV7ADC 0DM= =S =- 4a3V0m.D0°DpCV/l4 et os +125°C t Offset Voltage (µV)ut --2246844000000000000000 ReVprDeDs=e n2t.4aVtive Part VDD= 5.5V e p -600 erc 3% In -800 P -1000 0% 12 10 -8 -6 -4 -2 0 2 4 6 8 10 12 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 - - Input Offset Voltage Drift (µV/°C) Output Voltage (V) FIGURE 2-2: Input Offset Voltage Drift. FIGURE 2-5: Input Offset Voltage vs. Output Voltage. 1000 1000 Offset Voltage (µV) -2468200000000000 +++-48210255°5°°CCC°C Offset Voltage (µV) -2468200000000000 +++-41820255°°°5CCC°C ut Inpu ----864400000000 VRDeDpr=e 2s.e4nVtative Part t Input --644000000 Representative Part -800 -1000 -1000 531135791357913579 -0.-0.-0.0.0.0.0.0.1.1.1.1.1.2.2.2.2.2. 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 Common Mode Input Voltage (V) Power Supply Voltage (V) FIGURE 2-3: Input Offset Voltage vs. FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage. Power Supply Voltage.  2012-2013 Microchip Technology Inc. DS20002321C-page 7

MCP6491/2/4 Note: Unless otherwise indicated, T =+25°C, V =+2.4V to +5.5V, V =GND, V =V /2, V V /2, A DD SS CM DD OUT DD V =V /2, R =10kto V and C =20pF. L DD L L L 1,000 105 y Densit dB) 19050 PSRR oise Voltage (nV/Hz)(cid:165)100 MRR, PSRR (C 889050 CMRR @@ VVDD== 52..54VV NN 75 DD ut p 70 n I 10 65 10.E.1- 1 1 . E1+ 0 1 .1E0+ 1 11.0E0+ 2 1.1Ek+3 11.E0+k4 11.0E0+k5 1 1.EM+6 -50 -25 0 25 50 75 100 125 Frequency (Hz) Temperature (°C) FIGURE 2-7: Input Noise Voltage Density FIGURE 2-10: CMRR, PSRR vs. Ambient vs. Frequency. Temperature. y 30 110n00 nsit 25 nts 100p VDD= 5.5 V e e 100 oise DHz) 20 et Curr 10p10 Input Bias Current oltage N(nV/(cid:165) 1105 f = 10 kHz and Offsa(A) 1p1 Vput 5 VVDD== 55.55 VV Bias 0.10p.1 Input Offset Current In 0 put 0.010.p01 0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 In 25 35 45 55 65 75 85 95 05 15 25 - 1 1 1 Common Mode Input Voltage (V) Ambient Temperature (°C) FIGURE 2-8: Input Noise Voltage Density FIGURE 2-11: Input Bias, Offset Currents vs. Common Mode Input Voltage. vs. Ambient Temperature. 100 250 90 Representative Part A) 200 VDD= 5.5 V p dB) 80 PSRR+ ent ( 150 TA= +125°C R ( 70 urr PSR 60 CMRR as C 100 MRR, CM 5400 PSRR- ut Binpu 50 TTA==++8855°CC I 0 30 T = +25°C A -50 20 1.0100E+ 0 1 11.000E0+02 1 .010kE+03 1 .1000Ek+04 11.000E0+0k5 1 . 010EM+06 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Frequency (Hz) Common Mode Input Voltage (V) FIGURE 2-9: CMRR, PSRR vs. FIGURE 2-12: Input Bias Current vs. Frequency. Common Mode Input Voltage. DS20002321C-page 8  2012-2013 Microchip Technology Inc.

MCP6491/2/4 Note: Unless otherwise indicated, T =+25°C, V =+2.4V to +5.5V, V =GND, V =V /2, V V /2, A DD SS CM DD OUT DD V =V /2, R =10kto V and C =20pF. L DD L L L 700 600 600 Quiescent CurrentQ(µA/Amplifier) 555550257005050 VDDDD= 2.4VVDD= 5.5V Quiescent CurrentQ(µA/Amplifier) 234520000000000 +++-48210255°5°°CCC°C 475 VCM= VDD/4 100 VCM= VDD/4 0 450 0 5 0 5 0 5 0 5 0 5 0 5 0 5 -50 -25 0 25 50 75 100 125 0. 0. 1. 1. 2. 2. 3. 3. 4. 4. 5. 5. 6. 6. Ambient Temperature (°C) Power Supply Voltage (V) FIGURE 2-13: Quiescent Current vs. FIGURE 2-16: Quiescent Current vs. Ambient Temperature. Power Supply Voltage. 700 120 0 Quiescent Current(µA/Amplifier) 455663450505500000000 VDD= 2.4V en-Loop Gain (dB)Ope 10246820000000 Open-Loop GOapinen-Loop Phase ------119631128500050000en-Loop Phase (°)Ope 300 -20 -210 0.50.30.10.10.30.50.70.91.11.31.51.71.92.12.32.52.72.9 1.10E + 0 0 11.00E+ 0 1 11.00E0+0 2 11.0kE+ 0 3 11.00Ek+0 4 110.0E0+0k5 11.0ME+0 6 110.0ME+0 7 110.0E0+M08 ---Common Mode Input Voltage (V) Frequency (Hz) FIGURE 2-14: Quiescent Current vs. FIGURE 2-17: Open-Loop Gain, Phase vs. Common Mode Input Voltage. Frequency. 150 700 Quiescent Current(µA/Amplifier) 455665050500000 pen-Loop Gain (dB) 111112340000 VVDDDD== 25..45VV 400 VVDD= 5.5VV O C 350 D 100 300 90 5 0 5 0 5 0 5 0 5 0 5 0 5 0 0. 0. 0. 1. 1. 2. 2. 3. 3. 4. 4. 5. 5. 6. -50 -25 0 25 50 75 100 125 - Common Mode Input Voltage (V) Temperature (°C) FIGURE 2-15: Quiescent Current vs. FIGURE 2-18: DC Open-Loop Gain vs. Common Mode Input Voltage. Ambient Temperature.  2012-2013 Microchip Technology Inc. DS20002321C-page 9

MCP6491/2/4 Note: Unless otherwise indicated, T =+25°C, V =+2.4V to +5.5V, V =GND, V =V /2, V V /2, A DD SS CM DD OUT DD V =V /2, R =10kto V and C =20pF. L DD L L L 14 70 10 V = 5.5V uct 12 60 )P-P DD d V width ProMHz) 108 Phase Margin 4500 Margin (°) e Swing ( 1 VDD= 2.4V Band( 6 30 hase oltag n Gain 424 VDD= 2.4V GGaaiinnBBaannddwwiiddtthhPPrroodduucctt 212000 PP t Vutput O 0 0 0.1 -50 -25 0 25 50 75 100 125 101000 110k00 110000k0 11000000k0 1 0100M000 11000000M00 Ambient Temperature (°C) Frequency (Hz) FIGURE 2-19: Gain Bandwidth Product, FIGURE 2-22: Output Voltage Swing vs. Phase Margin vs. Ambient Temperature. Frequency. 14 70 V)1000 duct 12 60 m (m VVDDDD== 22..44VV n Bandwidth ProGain(MHz)10684 Gain BandwPidhtahs eP rMoadrugcint 34520000 Phase Margin (°)P oltage Headroout Vo 101001 VVDDDD--VVOOHH VVOOLL--VVSSSS 2 VDD= 5.5V 10 utp O 0 0 0.1 -50 -25 0 25 50 75 100 125 0.01 0.1 1 10 Ambient Temperature (°C) Output Current (mA) FIGURE 2-20: Gain Bandwidth Product, FIGURE 2-23: Output Voltage Headroom Phase Margin vs. Ambient Temperature. vs. Output Current. 60 V) 1000 ent 4500 +-2405°°CC m (m VDD= 5.5V Short Circuit CurrS(mA)--21123000000 +++11182225555°°°°CCCC Voltage HeadrooV 10100 VDD-VOH VOL-VSS ut -30 +85°C ut 1 Outp --5400 +-2405°°CC Outp -60 0.1 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0.01 0.1 1 10 100 Power Supply Voltage (V) Output Current (mA) FIGURE 2-21: Output Short Circuit Current FIGURE 2-24: Output Voltage Headroom vs. Power Supply Voltage. vs. Output Current. DS20002321C-page 10  2012-2013 Microchip Technology Inc.

MCP6491/2/4 Note: Unless otherwise indicated, T =+25°C, V =+2.4V to +5.5V, V =GND, V =V /2, V V /2, A DD SS CM DD OUT DD V =V /2, R =10kto V and C =20pF. L DD L L L V) 7 m m ( 6 v) droo 5 VDD-VOH mV/di ea 0 ge H 4 ge (1 Volta 3 VOL-VSS Volta ut 2 ut Outp 1 VDD= 2.4V Outp VGD =D =+ 15 VV/V 0 -50 -25 0 25 50 75 100 125 Temperature (°C) Time (0.2 µs/div) FIGURE 2-25: Output Voltage Headroom FIGURE 2-28: Small Signal Non-Inverting vs. Ambient Temperature. Pulse Response. V) 10 m droom ( 789 VDD-VOH V/div) VGD =D =-1 5 V V/V a m ge He 56 e (10 a g Volt 343 VOL-VSS Volta Output 12 VDD= 5.5V Output 0 -50 -25 0 25 50 75 100 125 Temperature (°C) Time (0.2 µs/div) FIGURE 2-26: Output Voltage Headroom FIGURE 2-29: Small Signal Inverting Pulse vs. Ambient Temperature. Response. 10.0 5.0 9.0 Falling Edge, VDD = 5.5V 4.5 e (V/µs) 678...000 Rising Edge, VDD = 5.5V e (V) 34..50 Slew Rat 345...000 put Voltag 223...050 2.0 R i s iFnagl lEindgg Ee,d VgDeD, V= D2D. 4=V 2 .4V tOut 1.5 VVGD =D =+155 VVV/V 1.0 1.0 0.0 0.5 -50 -25 0 25 50 75 100 125 0.0 Ambient Temperature (°C) Time (1 µs/div) FIGURE 2-27: Slew Rate vs. Ambient FIGURE 2-30: Large Signal Non-Inverting Temperature. Pulse Response.  2012-2013 Microchip Technology Inc. DS20002321C-page 11

MCP6491/2/4 Note: Unless otherwise indicated, T =+25°C, V =+2.4V to +5.5V, V =GND, V =V /2, V V /2, A DD SS CM DD OUT DD V =V /2, R =10kto V and C =20pF. L DD L L L 5.0 1.10Em+09 4.5 110.0E0+µ08 V = 5 V V) 4.0 GD =D -1 V/V 11.00E+µ07 age ( 33..05 A) 1.01E+µ06 put Volt 22..05 -I(pIN11110..000EE0++nn0045 +++8212555°°CC°C tut -4400°°CC O 1.5 1.01E+n03 1.0 110.00E+p02 0.5 11.00E+p01 0.0 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 Time (1 µs/div) V (V) IN FIGURE 2-31: Large Signal Inverting Pulse FIGURE 2-34: Measured Input Current vs. Response. Input Voltage (below V ). SS 6 100 utput Voltages (V)put, O 23451 VGVD =DIN =+ 25 VV/V VOUT annel to ChannelChaSeparation (dB)S 56789340000000 Input Referred n 0 I 20 -1 1.0E+02100 11.0E+03k 101.0E+04k 1001.0E+05k 1M1.0E+06 Frequency (Hz) Time (1 ms/div) FIGURE 2-32: The MCP6491/2/4 Shows FIGURE 2-35: Channel-to-Channel No Phase Reversal. Separation vs. Frequency (MCP6492/4 only). 1000 ut p Outpce ()(cid:58)100 on oa Ld sed mpe 10 GN: ooI 110011VV//VV Cl 11 V/V 1 V/V 1 11.0E0+002 1 .10Ek+03 11.0E0+k04 11.00E0+k05 1 .01EM+06 11.00EM+07 Frequency (Hz) FIGURE 2-33: Closed Loop Output Impedance vs. Frequency. DS20002321C-page 12  2012-2013 Microchip Technology Inc.

MCP6491/2/4 3.0 PIN DESCRIPTIONS Descriptions of the pins are listed in Table3-1. TABLE 3-1: PIN FUNCTION TABLE MCP6491 MCP6492 MCP6494 Symbol Description SC70, SOT-23 SOIC, MSOP 2x3TDFN SOIC, TSSOP 1 1 1 1 V , V Analog Output (op amp A) OUT OUTA 4 2 2 2 V –, V – Inverting Input (op amp A) IN INA 3 3 3 3 V +, V + Non-inverting Input (op amp A) IN INA 5 8 8 4 V Positive Power Supply DD — 5 5 5 V + Non-Inverting Input (op amp B) INB — 6 6 6 V – Inverting Input (op amp B) INB — 7 7 7 V Analog Output (op amp B) OUTB — — — 8 V Analog Output (op amp C) OUTC — — — 9 V – Inverting Input (op amp C) INC — — — 10 V + Non-Inverting Input (op amp C) INC 2 4 4 11 V Negative Power Supply SS — — — 12 V + Non-Inverting Input (op amp D) IND — — — 13 V – Inverting Input (op amp D) IND — — — 14 V Analog Output (op amp D) OUTD — — 9 — EP Exposed Thermal Pad (EP); must be connected to V . SS 3.1 Analog Outputs 3.4 Exposed Thermal Pad (EP) The output pins are low-impedance voltage sources. There is an internal electrical connection between the Exposed Thermal Pad (EP) and the V pin; they must SS 3.2 Analog Inputs be connected to the same potential on the Printed Circuit Board (PCB). The non-inverting and inverting inputs are This pad can be connected to a PCB ground plane to high-impedance CMOS inputs with low bias currents. provide a larger heat sink. This improves the package thermal resistance ( ). 3.3 Power Supply Pins JA The positive power supply (V ) is 2.4V to 5.5V higher DD than the negative power supply (V ). For normal SS operation, the other pins are at voltages between V SS and V . DD Typically, these parts are used in single-supply opera- tion. In this case, V is connected to ground and V SS DD is connected to the supply. V will need bypass DD capacitors.  2012-2013 Microchip Technology Inc. DS20002321C-page 13

MCP6491/2/4 NOTES: DS20002321C-page 14  2012-2013 Microchip Technology Inc.

MCP6491/2/4 4.0 APPLICATION INFORMATION V DD The MCP6491/2/4 family of op amps is manufactured using Microchip’s state-of-the-art CMOS process and is specifically designed for low-power, high-precision D D 1 2 applications. V 1 V OUT 4.1 Inputs MCP649X V 2 4.1.1 PHASE REVERSAL The MCP6491/2/4 op amps are designed to prevent FIGURE 4-2: Protecting the Analog phase reversal when the input pins exceed the supply Inputs. voltages. Figure2-32 shows the input voltage exceeding the supply voltage without any phase A significant amount of current can flow out of the reversal. inputs when the Common mode voltage (VCM) is below ground (V ), as shown in Figure2-34. SS 4.1.2 INPUT VOLTAGE LIMITS 4.1.3 INPUT CURRENT LIMITS In order to prevent damage and/or improper operation In order to prevent damage and/or improper operation of these amplifiers, the circuit must limit the voltages at of these amplifiers, the circuit must limit the currents the input pins (see Section1.1 “Absolute Maximum into the input pins (see Section1.1 “Absolute Ratings †”). Maximum Ratings †”). The ESD protection on the inputs can be depicted as Figure4-3 shows one approach to protect these inputs. shown in Figure4-1. This structure was chosen to The R and R resistors limit the possible currents in or protect the input transistors against many (but not all) 1 2 out of the input pins (and the ESD diodes, D and D ). overvoltage conditions, and to minimize the input bias 1 2 The diode currents will go through either V or V . current (I ). DD SS B V DD Bond V DD Pad D D 1 2 V 1 V + Bond Input Bond V – R1 MCP649X V IN Pad Stage Pad IN OUT V 2 R 2 Bond V SS R Pad 3 V –min(V ,V ) SS 1 2 FIGURE 4-1: Simplified Analog Input ESD min (R ,R ) > 1 2 2mA Structures. max(V ,V )–V 1 2 DD min (R ,R )> The input ESD diodes clamp the inputs when they try 1 2 2mA to go more than one diode drop below VSS. They also FIGURE 4-3: Protecting the Analog clamp any voltages that go well above V . Their DD Inputs. breakdown voltage is high enough to allow normal operation, but not low enough to protect against slow overvoltage (beyond V ) events. Very fast ESD DD events (that meet the specification) are limited so that damage does not occur. In some applications, it may be necessary to prevent excessive voltages from reaching the op amp inputs; Figure4-2 shows one approach to protect these inputs.  2012-2013 Microchip Technology Inc. DS20002321C-page 15

MCP6491/2/4 4.1.4 NORMAL OPERATION Figure4-5 gives the recommended R values for ISO different capacitive loads and gains. The x-axis is the The inputs of the MCP6491/2/4 op amps use two normalized load capacitance (C /G ), where G is the differential input stages in parallel. One operates at a L N N circuit’s noise gain. For non-inverting gains, G and the low Common mode input voltage (V ), while the other N CM Signal Gain are equal. For inverting gains, G is operates at a high V . With this topology, the device N CM 1+|Signal Gain| (e.g., -1V/V gives G = +2V/V). operates with a V up to 0.3V above V and 0.3V N CM DD below VSS (refer to Figures2-3 and 2-4). The input After selecting RISO for your circuit, double check the offset voltage is measured at V =V –0.3V and resulting frequency response peaking and step CM SS VDD+0.3V to ensure proper operation. response overshoot. Modify RISO’s value until the response is reasonable. Bench evaluation and The transition between the input stages occurs when simulations with the MCP6491/2/4 SPICE macro V is near V –1.4V (refer to Figures2-3 and 2-4). CM DD model are helpful. For the best distortion performance and gain linearity, with non-inverting gains, avoid this region of operation. 1000 4.2 Rail-to-Rail Output )(cid:58) VDD= 5.5 V (O RL= 10 k(cid:525) The output voltage range of the MCP6491/2/4 op amps S R I 100 is 0.007V (typical) and 5.493V (typical) when d RL=10k is connected to VDD/2 and VDD=5.5V. nde G : Refer to Figures2-23 and 2-24 for more information. e N m 1 V/V m 10 2 V/V 4.3 Capacitive Loads oco (cid:116)(cid:116)55 VV//VV e R Driving large capacitive loads can cause stability 1 problems for voltage feedback op amps. As the load 1.1E0-1p1 1 1.E0-01p0 1 . E 1-n0 9 1 . E1-00n8 1 . E 0-.017µ 1 . E 1-0µ6 capacitance increases, the feedback loop’s phase Normalized Load Capacitance; C /G (F) margin decreases and the closed-loop bandwidth is L N FIGURE 4-5: Recommended R Values reduced. This produces gain peaking in the frequency ISO response, with overshoot and ringing in the step for Capacitive Loads. response. While a unity-gain buffer (G=+1V/V) is the most sensitive to capacitive loads, all gains show the 4.4 Supply Bypass same general behavior. With this family of operational amplifiers, the power When driving large capacitive loads with these op supply pin (V for single supply) should have a local DD amps (e.g., >100pF when G=+1V/V), a small series bypass capacitor (i.e., 0.01µF to 0.1µF) within 2mm resistor at the output (R in Figure4-4) improves the ISO for good high-frequency performance. It can use a bulk feedback loop’s phase margin (stability) by making the capacitor (i.e., 1µF or larger) within 100mm to provide output load resistive at higher frequencies. The large, slow currents. This bulk capacitor can be shared bandwidth will generally be lower than the bandwidth with other analog parts. with no capacitance load. – R ISO MCP649X VOUT V + IN C L FIGURE 4-4: Output Resistor, R ISO Stabilizes Large Capacitive Loads. DS20002321C-page 16  2012-2013 Microchip Technology Inc.

MCP6491/2/4 4.5 Unused Op Amps 4.6 PCB Surface Leakage An unused op amp in a quad package (MCP6494) In applications where low-input bias current is critical, should be configured as shown in Figure4-6. These PCB surface leakage effects need to be considered. circuits prevent the output from toggling and causing Surface leakage is caused by humidity, dust or other crosstalk. CircuitA sets the op amp at its minimum contamination on the board. Under low-humidity noise gain. The resistor divider produces any desired conditions, a typical resistance between nearby traces reference voltage within the output voltage range of the is 1012. A 5V difference would cause 5pA of current op amp, and the op amp buffers that reference voltage. to flow, which is greater than the MCP6491/2/4 family’s CircuitB uses the minimum number of components bias current at +25°C (1pA, typical). and operates as a comparator, but it may draw more The easiest way to reduce surface leakage is to use a current. guard ring around sensitive pins (or traces). The guard ring is biased at the same voltage as the sensitive pin. ¼ MCP6494 (A) ¼ MCP6494 (B) An example of this type of layout is shown in V V Figure4-7. DD DD V R DD 1 Guard Ring V – V + V IN IN SS V R REF 2 R 2 V = V -------------------- REF DD R +R 1 2 FIGURE 4-6: Unused Op Amps. FIGURE 4-7: Example Guard Ring Layout for Inverting Gain. 1. Non-Inverting Gain and Unity-Gain Buffer: a.Connect the non-inverting pin (V +) to the IN input with a wire that does not touch the PCB surface. b.Connect the guard ring to the inverting input pin (V –). This biases the guard ring to the IN Common mode input voltage. 2. Inverting Gain and Transimpedance Gain Amplifiers (convert current to voltage, such as photo detectors): a.Connect the guard ring to the non-inverting input pin (V +). This biases the guard ring IN to the same reference voltage as the op amp (e.g., V /2 or ground). DD b.Connect the inverting pin (V –) to the input IN with a wire that does not touch the PCB surface.  2012-2013 Microchip Technology Inc. DS20002321C-page 17

MCP6491/2/4 4.7 Application Circuits 4.7.2 ACTIVE LOW PASS FILTER The MCP6491/2/4 op amps’ low-input bias current 4.7.1 PHOTO DETECTION makes it possible for the designer to use larger The MCP6491/2/4 op amps can be used to easily resistors and smaller capacitors for active low-pass convert the signal from a sensor that produces an filter applications. However, as the resistance output current (such as a photo diode) into a voltage (a increases, the noise generated also increases. transimpedance amplifier). This is implemented with a Parasitic capacitances and the large value resistors single resistor (R ) in the feedback loop of the could also modify the frequency response. These 2 amplifiers shown in Figure4-8 and Figure4-9. The trade-offs need to be considered when selecting circuit optional capacitor (C ) sometimes provides stability for elements. 2 these circuits. Usually, the op amp bandwidth is 100x the filter cutoff A photodiode configured in the Photovoltaic mode has frequency (or higher) for good performance. It is zero voltage potential placed across it (Figure4-8). In possible to have the op amp bandwidth 10x higher than this mode, the light sensitivity and linearity is the cutoff frequency, thus having a design that is more maximized, making it best suited for precision sensitive to component tolerances. applications. The key amplifier specifications for this Figure4-10 and Figure4-11 show low-pass, second- application are: low-input bias current, Common mode order, Butterworth filters with a cutoff frequency of input voltage range (including ground), and rail-to-rail 10Hz. The filter in Figure4-10 has a non-inverting gain output. of +1V/V, and the filter in Figure4-11 has an inverting gain of -1V/V. C 2 C 1 R 47nF 2 V I OUT D1 V – DD R1 R2 D 768k 1.27M 1 Light MCP6491 V + IN + C2 MCP6491 VOUT 22nF – V = I *R OUT D1 2 FIGURE 4-8: Photovoltaic Mode Detector. In contrast, a photodiode that is configured in the f = 10Hz, G = +1V/V Photoconductive mode has a reverse bias voltage P across the photo-sensing element (Figure4-9). This FIGURE 4-10: Second-Order, Low-Pass decreases the diode capacitance, which facilitates Butterworth Filter with Sallen-Key Topology. high-speed operation (e.g., high-speed digital communications). However, the reverse bias voltage also increased diode leakage current and caused R 2 linearity errors. 618k C 2 R1 R3 C1 618k 1.00M 8.2nF R2 VIN VOUT ID1 VDD VOUT C2 – 47nF – D MCP6491 1 Light MCP6491 V /2 + DD + V V = I *R BIAS OUT D1 2 VBIAS < 0V fP = 10Hz, G = -1V/V FIGURE 4-11: Second-Order, Low-Pass FIGURE 4-9: Photoconductive Mode Butterworth Filter with Multiple-Feedback Detector. Topology. DS20002321C-page 18  2012-2013 Microchip Technology Inc.

MCP6491/2/4 4.7.3 PH ELECTRODE AMPLIFIER The MCP6491/2/4 op amps can be used for sensing applications where the sensor has high output impedance, such as a pH electrode sensor; its output impedance is in the range of 1 M to 1G. The key op amp specifications for these kinds of applications are low-input bias current and high-input impedance. A typical sensing circuit is shown in Figure4-12, it is implemented with a non-inverting amplifier which has a gain of 1+R /R . The input voltage error due to input 2 1 bias current is equal to I *R , which is amplified by B OUT 1+R /R at the output. To minimize the voltage error 2 1 and get the V with better accuracy, the I must be OUT B small enough. R 2 R 1 – MCP6491 V OUT V IN + R OUT pH electrode + V SEN – V is the sensed voltage by pH electrode SEN R is the pH electrode’s output impedance OUT FIGURE 4-12: pH Electrode Amplifier.  2012-2013 Microchip Technology Inc. DS20002321C-page 19

MCP6491/2/4 NOTES: DS20002321C-page 20  2012-2013 Microchip Technology Inc.

MCP6491/2/4 5.0 DESIGN AIDS 5.4 Analog Demonstration and Evaluation Boards Microchip Technology Inc. provides the basic design tools needed for the MCP6491/2/4 family of op amps. Microchip offers a broad spectrum of Analog Demonstration and Evaluation Boards that are designed to help you achieve faster time to market. For 5.1 SPICE Macro Model a complete listing of these boards and their The latest SPICE macro model for the MCP6491/2/4 corresponding user’s guides and technical information, op amps is available on the Microchip web site at visit the Microchip web site: www.microchip.com. The model was written and tested www.microchip.com/analogtools. in PSpice, owned by Orcad (Cadence®). For other Some boards that are especially useful include: simulators, translation may be required. • MCP6XXX Amplifier Evaluation Board 1 The model covers a wide aspect of the op amp’s • MCP6XXX Amplifier Evaluation Board 2 electrical specifications. Not only does the model cover • MCP6XXX Amplifier Evaluation Board 3 voltage, current and resistance of the op amp, but it • MCP6XXX Amplifier Evaluation Board 4 also covers the temperature and noise effects on the • Active Filter Demo Board Kit behavior of the op amp. The model has not been • 5/6-Pin SOT-23 Evaluation Board, part number verified outside the specification range listed in the op VSUPEV2 amp data sheet. The model behaviors under these conditions cannot be guaranteed to match the actual • 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board, op amp performance. part number SOIC8EV Moreover, the model is intended to be an initial design 5.5 Application Notes tool. Bench testing is a very important part of any The following Microchip analog design note and design and cannot be replaced with simulations. Also, application notes are available on the Microchip web simulation results using this macro model need to be site at www.microchip.com/appnotes, and are validated by comparing them to the data sheet recommended as supplemental reference resources. specifications and characteristic curves. • ADN003: “Select the Right Operational Amplifier for your Filtering Circuits”, DS21821 5.2 FilterLab Software • AN722: “Operational Amplifier Topologies and DC Microchip’s FilterLab software is an innovative software Specifications”, DS00722 tool that simplifies analog active filter (using op amps) • AN723: “Operational Amplifier AC Specifications design. Available at no cost from the Microchip web site and Applications”, DS00723 at www.microchip.com/filterlab, the FilterLab design • AN884: “Driving Capacitive Loads With Op tool provides full schematic diagrams of the filter circuit Amps”, DS00884 with component values. It also outputs the filter circuit • AN990: “Analog Sensor Conditioning Circuits– in SPICE format, which can be used with the macro An Overview”, DS00990 model to simulate actual filter performance. • AN1177: “Op Amp Precision Design: DC Errors”, DS01177 5.3 MAPS (Microchip Advanced Part • AN1228: “Op Amp Precision Design: Random Selector) Noise”, DS01228 • AN1297: “Microchip’s Op Amp SPICE Macro MAPS is a software tool that helps semiconductor Models”’ DS01297 professionals efficiently identify Microchip devices that • AN1332: “Current Sensing Circuit Concepts and fit a particular design requirement. Available at no cost, Fundamentals”’ DS01332 MAPS is an overall selection tool for Microchip’s product portfolio that includes analog, memory, MCUs • AN1494: “Using MCP6491 Op Amps for Photode- and DSCs. Using this tool, you can define a filter to sort tection Applications” DS01494 features for a parametric search of devices and export These application notes and others are listed in: side-by-side technical comparison reports. Helpful links • “Signal Chain Design Guide”, DS21825 are also provided for data sheets, purchases and sampling of Microchip parts. The web site is available at www.microchip.com/maps.  2012-2013 Microchip Technology Inc. DS20002321C-page 21

MCP6491/2/4 NOTES: DS20002321C-page 22  2012-2013 Microchip Technology Inc.

MCP6491/2/4 6.0 PACKAGING INFORMATION 6.1 Package Marking Information 5-Lead SOT-23 (MCP6491 only) Example Part Number Code 3G25 MCP6491T-E/OT 3GNN 5-Lead SC-70 (MCP6491 only) Example Part Number Code DR25 MCP6491T-E/LTY DRNN 8-Lead MSOP (3x3 mm) (MCP6492 only) Example 6492E 320256 8-Lead SOIC (3.90 mm) (MCP6492 only) Example MCP6492 E/SN1320 256 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e 3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2012-2013 Microchip Technology Inc. DS20002321C-page 23

MCP6491/2/4 8-Lead TDFN (2x3x0.75 mm) (MCP6492 only) Example Part Number Code ABN MCP6492T-E/MNY ABN 320 25 14-Lead SOIC (3.90 mm) (MCP6494 only) Example MCP6494 E/SL 1320256 14-Lead TSSOP (4.4 mm) (MCP6494 only) Example XXXXXXXX 6494E/ST YYWW 1320 256 NNN DS20002321C-page 24  2012-2013 Microchip Technology Inc.

MCP6491/2/4 5-Lead Plastic Small Outine Transistor (LTY) [SC70] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D b 3 2 1 E1 E 4 5 e e A A2 c A1 L )(cid:8)(cid:5)(cid:15)(cid:9) (cid:23)*++*(cid:23)(cid:14)%(cid:14),(cid:30) (cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:5)(cid:10)(cid:8)(cid:11)+(cid:5)(cid:6)(cid:5)(cid:15)(cid:9) (cid:23)*- -.(cid:23) (cid:23)(cid:29)/ -(cid:18)(cid:6)0(cid:7)(cid:21)(cid:11)(cid:10)(cid:19)(cid:11)1(cid:5)(cid:8)(cid:9) - ! 1(cid:5)(cid:15)(cid:16)(cid:20) (cid:7) (cid:25)(cid:3)2!(cid:11)"(cid:30)# .’(cid:7)(cid:21)(cid:12)(cid:17)(cid:17)(cid:11)3(cid:7)(cid:5)(cid:28)(cid:20)(cid:15) (cid:29) (cid:25)(cid:3)4(cid:25) 5 (cid:2)(cid:3)(cid:2)(cid:25) (cid:23)(cid:10)(cid:17)(cid:13)(cid:7)(cid:13)(cid:11)1(cid:12)(cid:16)6(cid:12)(cid:28)(cid:7)(cid:11)%(cid:20)(cid:5)(cid:16)6(cid:8)(cid:7)(cid:9)(cid:9) (cid:29)(cid:26) (cid:25)(cid:3)4(cid:25) 5 (cid:2)(cid:3)(cid:25)(cid:25) (cid:30)(cid:15)(cid:12)(cid:8)(cid:13)(cid:10)(cid:19)(cid:19) (cid:29)(cid:2) (cid:25)(cid:3)(cid:25)(cid:25) 5 (cid:25)(cid:3)(cid:2)(cid:25) .’(cid:7)(cid:21)(cid:12)(cid:17)(cid:17)(cid:11)7(cid:5)(cid:13)(cid:15)(cid:20) (cid:14) (cid:2)(cid:3)4(cid:25) (cid:26)(cid:3)(cid:2)(cid:25) (cid:26)(cid:3) (cid:25) (cid:23)(cid:10)(cid:17)(cid:13)(cid:7)(cid:13)(cid:11)1(cid:12)(cid:16)6(cid:12)(cid:28)(cid:7)(cid:11)7(cid:5)(cid:13)(cid:15)(cid:20) (cid:14)(cid:2) (cid:2)(cid:3)(cid:2)! (cid:2)(cid:3)(cid:26)! (cid:2)(cid:3)8! .’(cid:7)(cid:21)(cid:12)(cid:17)(cid:17)(cid:11)+(cid:7)(cid:8)(cid:28)(cid:15)(cid:20) (cid:4) (cid:2)(cid:3)4(cid:25) (cid:26)(cid:3)(cid:25)(cid:25) (cid:26)(cid:3)(cid:26)! 9(cid:10)(cid:10)(cid:15)(cid:11)+(cid:7)(cid:8)(cid:28)(cid:15)(cid:20) + (cid:25)(cid:3)(cid:2)(cid:25) (cid:25)(cid:3)(cid:26)(cid:25) (cid:25)(cid:3) 2 +(cid:7)(cid:12)(cid:13)(cid:11)%(cid:20)(cid:5)(cid:16)6(cid:8)(cid:7)(cid:9)(cid:9) (cid:16) (cid:25)(cid:3)(cid:25)4 5 (cid:25)(cid:3)(cid:26)2 +(cid:7)(cid:12)(cid:13)(cid:11)7(cid:5)(cid:13)(cid:15)(cid:20) 0 (cid:25)(cid:3)(cid:2)! 5 (cid:25)(cid:3) (cid:25) (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:2)(cid:3) (cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:5)(cid:10)(cid:8)(cid:9)(cid:11)(cid:4)(cid:11)(cid:12)(cid:8)(cid:13)(cid:11)(cid:14)(cid:2)(cid:11)(cid:13)(cid:10)(cid:11)(cid:8)(cid:10)(cid:15)(cid:11)(cid:5)(cid:8)(cid:16)(cid:17)(cid:18)(cid:13)(cid:7)(cid:11)(cid:6)(cid:10)(cid:17)(cid:13)(cid:11)(cid:19)(cid:17)(cid:12)(cid:9)(cid:20)(cid:11)(cid:10)(cid:21)(cid:11)(cid:22)(cid:21)(cid:10)(cid:15)(cid:21)(cid:18)(cid:9)(cid:5)(cid:10)(cid:8)(cid:9)(cid:3)(cid:11)(cid:23)(cid:10)(cid:17)(cid:13)(cid:11)(cid:19)(cid:17)(cid:12)(cid:9)(cid:20)(cid:11)(cid:10)(cid:21)(cid:11)(cid:22)(cid:21)(cid:10)(cid:15)(cid:21)(cid:18)(cid:9)(cid:5)(cid:10)(cid:8)(cid:9)(cid:11)(cid:9)(cid:20)(cid:12)(cid:17)(cid:17)(cid:11)(cid:8)(cid:10)(cid:15)(cid:11)(cid:7)(cid:24)(cid:16)(cid:7)(cid:7)(cid:13)(cid:11)(cid:25)(cid:3)(cid:2)(cid:26)(cid:27)(cid:11)(cid:6)(cid:6)(cid:11)(cid:22)(cid:7)(cid:21)(cid:11)(cid:9)(cid:5)(cid:13)(cid:7)(cid:3) (cid:26)(cid:3) (cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:5)(cid:10)(cid:8)(cid:5)(cid:8)(cid:28)(cid:11)(cid:12)(cid:8)(cid:13)(cid:11)(cid:15)(cid:10)(cid:17)(cid:7)(cid:21)(cid:12)(cid:8)(cid:16)(cid:5)(cid:8)(cid:28)(cid:11)(cid:22)(cid:7)(cid:21)(cid:11)(cid:29)(cid:30)(cid:23)(cid:14)(cid:11)(cid:31)(cid:2) (cid:3)!(cid:23)(cid:3) "(cid:30)#$ "(cid:12)(cid:9)(cid:5)(cid:16)(cid:11)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:5)(cid:10)(cid:8)(cid:3)(cid:11)%(cid:20)(cid:7)(cid:10)(cid:21)(cid:7)(cid:15)(cid:5)(cid:16)(cid:12)(cid:17)(cid:17)&(cid:11)(cid:7)(cid:24)(cid:12)(cid:16)(cid:15)(cid:11)’(cid:12)(cid:17)(cid:18)(cid:7)(cid:11)(cid:9)(cid:20)(cid:10)((cid:8)(cid:11)((cid:5)(cid:15)(cid:20)(cid:10)(cid:18)(cid:15)(cid:11)(cid:15)(cid:10)(cid:17)(cid:7)(cid:21)(cid:12)(cid:8)(cid:16)(cid:7)(cid:9)(cid:3) MicrochipTechnologyDrawingC04-083B (cid:23)(cid:5)(cid:16)(cid:21)(cid:10)(cid:16)(cid:20)(cid:5)(cid:22)%(cid:7)(cid:16)(cid:20)(cid:8)(cid:10)(cid:17)(cid:10)(cid:28)&(cid:4)(cid:21)(cid:12)((cid:5)(cid:8)(cid:28)#(cid:25) :(cid:25)2(cid:2)"  2012-2013 Microchip Technology Inc. DS20002321C-page 25

MCP6491/2/4 5-Lead Plastic Small Outine Transistor (LTY) [SC70] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20002321C-page 26  2012-2013 Microchip Technology Inc.

MCP6491/2/4 (cid:8)(cid:9)(cid:10)(cid:5)(cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:11)(cid:6)(cid:4)(cid:16)(cid:17)(cid:13)(cid:18)(cid:19)(cid:11)(cid:15)(cid:15)(cid:13)(cid:20)(cid:21)(cid:4)(cid:15)(cid:16)(cid:22)(cid:5)(cid:13)(cid:23)(cid:24)(cid:11)(cid:22)(cid:6)(cid:16)(cid:6)(cid:4)(cid:3)(cid:24)(cid:13)(cid:25)(cid:20)(cid:23)(cid:26)(cid:13)(cid:27)(cid:18)(cid:20)(cid:23)(cid:9)(cid:28)(cid:29)(cid:30) (cid:2)(cid:3)(cid:4)(cid:5)(cid:7) 9(cid:10)(cid:21)(cid:11)(cid:15)(cid:20)(cid:7)(cid:11)(cid:6)(cid:10)(cid:9)(cid:15)(cid:11)(cid:16)(cid:18)(cid:21)(cid:21)(cid:7)(cid:8)(cid:15)(cid:11)(cid:22)(cid:12)(cid:16)6(cid:12)(cid:28)(cid:7)(cid:11)(cid:13)(cid:21)(cid:12)((cid:5)(cid:8)(cid:28)(cid:9)<(cid:11)(cid:22)(cid:17)(cid:7)(cid:12)(cid:9)(cid:7)(cid:11)(cid:9)(cid:7)(cid:7)(cid:11)(cid:15)(cid:20)(cid:7)(cid:11)(cid:23)(cid:5)(cid:16)(cid:21)(cid:10)(cid:16)(cid:20)(cid:5)(cid:22)(cid:11)1(cid:12)(cid:16)6(cid:12)(cid:28)(cid:5)(cid:8)(cid:28)(cid:11)(cid:30)(cid:22)(cid:7)(cid:16)(cid:5)(cid:19)(cid:5)(cid:16)(cid:12)(cid:15)(cid:5)(cid:10)(cid:8)(cid:11)(cid:17)(cid:10)(cid:16)(cid:12)(cid:15)(cid:7)(cid:13)(cid:11)(cid:12)(cid:15)(cid:11) (cid:20)(cid:15)(cid:15)(cid:22)$==((((cid:3)(cid:6)(cid:5)(cid:16)(cid:21)(cid:10)(cid:16)(cid:20)(cid:5)(cid:22)(cid:3)(cid:16)(cid:10)(cid:6)=(cid:22)(cid:12)(cid:16)6(cid:12)(cid:28)(cid:5)(cid:8)(cid:28) b N E E1 1 2 3 e e1 D A A2 c φ A1 L L1 )(cid:8)(cid:5)(cid:15)(cid:9) (cid:23)*++*(cid:23)(cid:14)%(cid:14),(cid:30) (cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:5)(cid:10)(cid:8)(cid:11)+(cid:5)(cid:6)(cid:5)(cid:15)(cid:9) (cid:23)*- -.(cid:23) (cid:23)(cid:29)/ -(cid:18)(cid:6)0(cid:7)(cid:21)(cid:11)(cid:10)(cid:19)(cid:11)1(cid:5)(cid:8)(cid:9) - ! +(cid:7)(cid:12)(cid:13)(cid:11)1(cid:5)(cid:15)(cid:16)(cid:20) (cid:7) (cid:25)(cid:3);!(cid:11)"(cid:30)# .(cid:18)(cid:15)(cid:9)(cid:5)(cid:13)(cid:7)(cid:11)+(cid:7)(cid:12)(cid:13)(cid:11)1(cid:5)(cid:15)(cid:16)(cid:20) (cid:7)(cid:2) (cid:2)(cid:3);(cid:25)(cid:11)"(cid:30)# .’(cid:7)(cid:21)(cid:12)(cid:17)(cid:17)(cid:11)3(cid:7)(cid:5)(cid:28)(cid:20)(cid:15) (cid:29) (cid:25)(cid:3);(cid:25) 5 (cid:2)(cid:3) ! (cid:23)(cid:10)(cid:17)(cid:13)(cid:7)(cid:13)(cid:11)1(cid:12)(cid:16)6(cid:12)(cid:28)(cid:7)(cid:11)%(cid:20)(cid:5)(cid:16)6(cid:8)(cid:7)(cid:9)(cid:9) (cid:29)(cid:26) (cid:25)(cid:3)4; 5 (cid:2)(cid:3)8(cid:25) (cid:30)(cid:15)(cid:12)(cid:8)(cid:13)(cid:10)(cid:19)(cid:19) (cid:29)(cid:2) (cid:25)(cid:3)(cid:25)(cid:25) 5 (cid:25)(cid:3)(cid:2)! .’(cid:7)(cid:21)(cid:12)(cid:17)(cid:17)(cid:11)7(cid:5)(cid:13)(cid:15)(cid:20) (cid:14) (cid:26)(cid:3)(cid:26)(cid:25) 5 8(cid:3)(cid:26)(cid:25) (cid:23)(cid:10)(cid:17)(cid:13)(cid:7)(cid:13)(cid:11)1(cid:12)(cid:16)6(cid:12)(cid:28)(cid:7)(cid:11)7(cid:5)(cid:13)(cid:15)(cid:20) (cid:14)(cid:2) (cid:2)(cid:3)8(cid:25) 5 (cid:2)(cid:3)4(cid:25) .’(cid:7)(cid:21)(cid:12)(cid:17)(cid:17)(cid:11)+(cid:7)(cid:8)(cid:28)(cid:15)(cid:20) (cid:4) (cid:26)(cid:3)(cid:27)(cid:25) 5 8(cid:3)(cid:2)(cid:25) 9(cid:10)(cid:10)(cid:15)(cid:11)+(cid:7)(cid:8)(cid:28)(cid:15)(cid:20) + (cid:25)(cid:3)(cid:2)(cid:25) 5 (cid:25)(cid:3)2(cid:25) 9(cid:10)(cid:10)(cid:15)(cid:22)(cid:21)(cid:5)(cid:8)(cid:15) +(cid:2) (cid:25)(cid:3)8! 5 (cid:25)(cid:3)4(cid:25) 9(cid:10)(cid:10)(cid:15)(cid:11)(cid:29)(cid:8)(cid:28)(cid:17)(cid:7) (cid:3) (cid:25)> 5 8(cid:25)> +(cid:7)(cid:12)(cid:13)(cid:11)%(cid:20)(cid:5)(cid:16)6(cid:8)(cid:7)(cid:9)(cid:9) (cid:16) (cid:25)(cid:3)(cid:25)4 5 (cid:25)(cid:3)(cid:26)2 +(cid:7)(cid:12)(cid:13)(cid:11)7(cid:5)(cid:13)(cid:15)(cid:20) 0 (cid:25)(cid:3)(cid:26)(cid:25) 5 (cid:25)(cid:3)!(cid:2) (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:2)(cid:3) (cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:5)(cid:10)(cid:8)(cid:9)(cid:11)(cid:4)(cid:11)(cid:12)(cid:8)(cid:13)(cid:11)(cid:14)(cid:2)(cid:11)(cid:13)(cid:10)(cid:11)(cid:8)(cid:10)(cid:15)(cid:11)(cid:5)(cid:8)(cid:16)(cid:17)(cid:18)(cid:13)(cid:7)(cid:11)(cid:6)(cid:10)(cid:17)(cid:13)(cid:11)(cid:19)(cid:17)(cid:12)(cid:9)(cid:20)(cid:11)(cid:10)(cid:21)(cid:11)(cid:22)(cid:21)(cid:10)(cid:15)(cid:21)(cid:18)(cid:9)(cid:5)(cid:10)(cid:8)(cid:9)(cid:3)(cid:11)(cid:23)(cid:10)(cid:17)(cid:13)(cid:11)(cid:19)(cid:17)(cid:12)(cid:9)(cid:20)(cid:11)(cid:10)(cid:21)(cid:11)(cid:22)(cid:21)(cid:10)(cid:15)(cid:21)(cid:18)(cid:9)(cid:5)(cid:10)(cid:8)(cid:9)(cid:11)(cid:9)(cid:20)(cid:12)(cid:17)(cid:17)(cid:11)(cid:8)(cid:10)(cid:15)(cid:11)(cid:7)(cid:24)(cid:16)(cid:7)(cid:7)(cid:13)(cid:11)(cid:25)(cid:3)(cid:2)(cid:26)(cid:27)(cid:11)(cid:6)(cid:6)(cid:11)(cid:22)(cid:7)(cid:21)(cid:11)(cid:9)(cid:5)(cid:13)(cid:7)(cid:3) (cid:26)(cid:3) (cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:5)(cid:10)(cid:8)(cid:5)(cid:8)(cid:28)(cid:11)(cid:12)(cid:8)(cid:13)(cid:11)(cid:15)(cid:10)(cid:17)(cid:7)(cid:21)(cid:12)(cid:8)(cid:16)(cid:5)(cid:8)(cid:28)(cid:11)(cid:22)(cid:7)(cid:21)(cid:11)(cid:29)(cid:30)(cid:23)(cid:14)(cid:11)(cid:31)(cid:2) (cid:3)!(cid:23)(cid:3) "(cid:30)#$ "(cid:12)(cid:9)(cid:5)(cid:16)(cid:11)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:5)(cid:10)(cid:8)(cid:3)(cid:11)%(cid:20)(cid:7)(cid:10)(cid:21)(cid:7)(cid:15)(cid:5)(cid:16)(cid:12)(cid:17)(cid:17)&(cid:11)(cid:7)(cid:24)(cid:12)(cid:16)(cid:15)(cid:11)’(cid:12)(cid:17)(cid:18)(cid:7)(cid:11)(cid:9)(cid:20)(cid:10)((cid:8)(cid:11)((cid:5)(cid:15)(cid:20)(cid:10)(cid:18)(cid:15)(cid:11)(cid:15)(cid:10)(cid:17)(cid:7)(cid:21)(cid:12)(cid:8)(cid:16)(cid:7)(cid:9)(cid:3) (cid:23)(cid:5)(cid:16)(cid:21)(cid:10)(cid:16)(cid:20)(cid:5)(cid:22)%(cid:7)(cid:16)(cid:20)(cid:8)(cid:10)(cid:17)(cid:10)(cid:28)&(cid:4)(cid:21)(cid:12)((cid:5)(cid:8)(cid:28)#(cid:25) :(cid:25);(cid:2)"  2012-2013 Microchip Technology Inc. DS20002321C-page 27

MCP6491/2/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20002321C-page 28  2012-2013 Microchip Technology Inc.

MCP6491/2/4 Note: For the mostcurrent package drawings,please seetheMicrochip Packaging Specification located at http://www.microchip.com/packaging  2012-2013 Microchip Technology Inc. DS20002321C-page 29

MCP6491/2/4 Note: For the mostcurrent package drawings,please seetheMicrochip Packaging Specification located at http://www.microchip.com/packaging DS20002321C-page 30  2012-2013 Microchip Technology Inc.

MCP6491/2/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2012-2013 Microchip Technology Inc. DS20002321C-page 31

MCP6491/2/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20002321C-page 32  2012-2013 Microchip Technology Inc.

MCP6491/2/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2012-2013 Microchip Technology Inc. DS20002321C-page 33

MCP6491/2/4 (cid:31)(cid:9)(cid:10)(cid:5)(cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:11)(cid:6)(cid:4)(cid:16)(cid:17)(cid:13)(cid:18)(cid:19)(cid:11)(cid:15)(cid:15)(cid:13)(cid:20)(cid:21)(cid:4)(cid:15)(cid:16)(cid:22)(cid:5)(cid:13)(cid:25)(cid:18)(cid:2)(cid:26)(cid:13) (cid:13)(cid:2)(cid:11)(cid:24)(cid:24)(cid:3)!"(cid:13)(cid:29)#$%(cid:13)(cid:19)(cid:19)(cid:13)&(cid:3)(cid:12)’(cid:13)(cid:27)(cid:18)(cid:20)()(cid:30) (cid:2)(cid:3)(cid:4)(cid:5)(cid:7) 9(cid:10)(cid:21)(cid:11)(cid:15)(cid:20)(cid:7)(cid:11)(cid:6)(cid:10)(cid:9)(cid:15)(cid:11)(cid:16)(cid:18)(cid:21)(cid:21)(cid:7)(cid:8)(cid:15)(cid:11)(cid:22)(cid:12)(cid:16)6(cid:12)(cid:28)(cid:7)(cid:11)(cid:13)(cid:21)(cid:12)((cid:5)(cid:8)(cid:28)(cid:9)<(cid:11)(cid:22)(cid:17)(cid:7)(cid:12)(cid:9)(cid:7)(cid:11)(cid:9)(cid:7)(cid:7)(cid:11)(cid:15)(cid:20)(cid:7)(cid:11)(cid:23)(cid:5)(cid:16)(cid:21)(cid:10)(cid:16)(cid:20)(cid:5)(cid:22)(cid:11)1(cid:12)(cid:16)6(cid:12)(cid:28)(cid:5)(cid:8)(cid:28)(cid:11)(cid:30)(cid:22)(cid:7)(cid:16)(cid:5)(cid:19)(cid:5)(cid:16)(cid:12)(cid:15)(cid:5)(cid:10)(cid:8)(cid:11)(cid:17)(cid:10)(cid:16)(cid:12)(cid:15)(cid:7)(cid:13)(cid:11)(cid:12)(cid:15)(cid:11) (cid:20)(cid:15)(cid:15)(cid:22)$==((((cid:3)(cid:6)(cid:5)(cid:16)(cid:21)(cid:10)(cid:16)(cid:20)(cid:5)(cid:22)(cid:3)(cid:16)(cid:10)(cid:6)=(cid:22)(cid:12)(cid:16)6(cid:12)(cid:28)(cid:5)(cid:8)(cid:28) DS20002321C-page 34  2012-2013 Microchip Technology Inc.

MCP6491/2/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2012-2013 Microchip Technology Inc. DS20002321C-page 35

MCP6491/2/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20002321C-page 36  2012-2013 Microchip Technology Inc.

MCP6491/2/4 (cid:31)(cid:9)(cid:10)(cid:5)(cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:11)(cid:6)(cid:4)(cid:16)(cid:17)(cid:13)*(cid:21)(cid:11)(cid:15)(cid:13)+(cid:15)(cid:11)(cid:4)"(cid:13)(cid:2)(cid:3)(cid:13)(cid:10)(cid:5)(cid:11)(cid:12)(cid:13)(cid:14)(cid:11)(cid:17),(cid:11)-(cid:5)(cid:13)(cid:25).(cid:2)(cid:26)(cid:13) (cid:13)(cid:28)/(cid:29)/%#0(cid:8)(cid:13)(cid:19)(cid:19)(cid:13)&(cid:3)(cid:12)’(cid:13)(cid:27)(cid:23)*+(cid:2)(cid:30) (cid:2)(cid:3)(cid:4)(cid:5)(cid:7) 9(cid:10)(cid:21)(cid:11)(cid:15)(cid:20)(cid:7)(cid:11)(cid:6)(cid:10)(cid:9)(cid:15)(cid:11)(cid:16)(cid:18)(cid:21)(cid:21)(cid:7)(cid:8)(cid:15)(cid:11)(cid:22)(cid:12)(cid:16)6(cid:12)(cid:28)(cid:7)(cid:11)(cid:13)(cid:21)(cid:12)((cid:5)(cid:8)(cid:28)(cid:9)<(cid:11)(cid:22)(cid:17)(cid:7)(cid:12)(cid:9)(cid:7)(cid:11)(cid:9)(cid:7)(cid:7)(cid:11)(cid:15)(cid:20)(cid:7)(cid:11)(cid:23)(cid:5)(cid:16)(cid:21)(cid:10)(cid:16)(cid:20)(cid:5)(cid:22)(cid:11)1(cid:12)(cid:16)6(cid:12)(cid:28)(cid:5)(cid:8)(cid:28)(cid:11)(cid:30)(cid:22)(cid:7)(cid:16)(cid:5)(cid:19)(cid:5)(cid:16)(cid:12)(cid:15)(cid:5)(cid:10)(cid:8)(cid:11)(cid:17)(cid:10)(cid:16)(cid:12)(cid:15)(cid:7)(cid:13)(cid:11)(cid:12)(cid:15)(cid:11) (cid:20)(cid:15)(cid:15)(cid:22)$==((((cid:3)(cid:6)(cid:5)(cid:16)(cid:21)(cid:10)(cid:16)(cid:20)(cid:5)(cid:22)(cid:3)(cid:16)(cid:10)(cid:6)=(cid:22)(cid:12)(cid:16)6(cid:12)(cid:28)(cid:5)(cid:8)(cid:28)  2012-2013 Microchip Technology Inc. DS20002321C-page 37

MCP6491/2/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20002321C-page 38  2012-2013 Microchip Technology Inc.

MCP6491/2/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2012-2013 Microchip Technology Inc. DS20002321C-page 39

MCP6491/2/4 (cid:2)(cid:3)(cid:4)(cid:5)(cid:7) 9(cid:10)(cid:21)(cid:11)(cid:15)(cid:20)(cid:7)(cid:11)(cid:6)(cid:10)(cid:9)(cid:15)(cid:11)(cid:16)(cid:18)(cid:21)(cid:21)(cid:7)(cid:8)(cid:15)(cid:11)(cid:22)(cid:12)(cid:16)6(cid:12)(cid:28)(cid:7)(cid:11)(cid:13)(cid:21)(cid:12)((cid:5)(cid:8)(cid:28)(cid:9)<(cid:11)(cid:22)(cid:17)(cid:7)(cid:12)(cid:9)(cid:7)(cid:11)(cid:9)(cid:7)(cid:7)(cid:11)(cid:15)(cid:20)(cid:7)(cid:11)(cid:23)(cid:5)(cid:16)(cid:21)(cid:10)(cid:16)(cid:20)(cid:5)(cid:22)(cid:11)1(cid:12)(cid:16)6(cid:12)(cid:28)(cid:5)(cid:8)(cid:28)(cid:11)(cid:30)(cid:22)(cid:7)(cid:16)(cid:5)(cid:19)(cid:5)(cid:16)(cid:12)(cid:15)(cid:5)(cid:10)(cid:8)(cid:11)(cid:17)(cid:10)(cid:16)(cid:12)(cid:15)(cid:7)(cid:13)(cid:11)(cid:12)(cid:15)(cid:11) (cid:20)(cid:15)(cid:15)(cid:22)$==((((cid:3)(cid:6)(cid:5)(cid:16)(cid:21)(cid:10)(cid:16)(cid:20)(cid:5)(cid:22)(cid:3)(cid:16)(cid:10)(cid:6)=(cid:22)(cid:12)(cid:16)6(cid:12)(cid:28)(cid:5)(cid:8)(cid:28) DS20002321C-page 40  2012-2013 Microchip Technology Inc.

MCP6491/2/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2012-2013 Microchip Technology Inc. DS20002321C-page 41

MCP6491/2/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20002321C-page 42  2012-2013 Microchip Technology Inc.

MCP6491/2/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2012-2013 Microchip Technology Inc. DS20002321C-page 43

MCP6491/2/4 NOTES: DS20002321C-page 44  2012-2013 Microchip Technology Inc.

MCP6491/2/4 APPENDIX A: REVISION HISTORY Revision C (June 2013) The following is the list of modifications: 1. Added new devices to the family (MCP6492 and MCP6494) and related information throughout the document. 2. Updated thermal package resistance information in Table1-3. 3. Added Figure2-35 in Section2.0, Typical Per- formance Curves. 4. Updated Section3.0, Pin Descriptions. 5. Added new Section4.5, Unused Op Amps. 6. Updated the list of reference documents in Section5.5, Application Notes. 7. Added package markings and drawings for the MCP6492 and MCP6494 devices. 8. Updated Product Identification System. Revision B (October 2012) The following is the list of modifications: 1. Updated the maximum low input offset voltage value in the Features section. 2. Updated the minimum and maximum input offset voltage in Table1-1 “DC Electrical Specifications”. Revision A (September 2012) • Original Release of this Document.  2012-2013 Microchip Technology Inc. DS20002321C-page 45

MCP6491/2/4 NOTES: DS20002321C-page 46  2012-2013 Microchip Technology Inc.

MCP6491/2/4 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. -X /XX Examples: a) MCP6491T-E/LTY: Tape and Reel, Device Temperature Package Extended Temp., Range 5LD SC70 package b) MCP6491T-E/OT: Tape and Reel, Extended Temp., 5LD SOT-23 package Device: MCP6491T: Single Op Amp (Tape and Reel) (SC70, SOT-23) MCP6492: Dual Op Amp (SOIC and MSOP only) c) MCP6492-E/MS: Extended Temp., MCP6492T: Dual Op Amp (Tape and Reel) 8LD MSOP package (SOIC, MSOP and 2x3 TDFN) d) MCP6492T-E/MS: Tape and Reel, MCP6494: Quad Op Amp Extended Temp., MCP6494T: Quad Op Amp (Tape and Reel) 8LD MSOP package (SOIC and TSSOP) e) MCP6492-E/SN: Extended Temp., 8LD SOIC package f) MCP6492T-E/SN: Tape and Reel, Temperature Range: E = -40°C to +125°C (Extended) Extended Temp., 8LD SOIC package g) MCP6492T-E/MNY: Tape and Reel, Package: LTY = Plastic Package (SC70), 5-lead Extended Temp., OT = Plastic Small Outline Transistor, (SOT-23), 8LD 2x3 TDFN package 5-lead MNY* = Plastic Dual Flat, No Lead, (2x3 TDFN), 8-lead (TDFN) h) MCP6494-E/SL: Extended Temp., 14LD SN = Lead Plastic Small Outline (150 mil body), SOIC package 8-lead (SOIC) i) MCP6494T-E/SL: Tape and Reel, MS = Plastic MSOP, 8-lead Extended Temp., 14LD SL = Plastic Small Outline, (150 mil body), SOIC package 14-lead (SOIC) j) MCP6494-E/ST: Extended Temp., ST = Plastic Thin Shrink Small Outline 14LD TSSOP package (150 mil body), 14-lead (TSSOP) k) MCP6494T-E/ST: Tape and Reel, * Y = Nickel palladium gold manufacturing designator. Only Extended Temp., available on the TDFN package. 14LD TSSOP package  2012-2013 Microchip Technology Inc. DS20002321C-page 47

MCP6491/2/4 NOTES: DS20002321C-page 48  2012-2013 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, ensure that your application meets with your specifications. PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash MICROCHIP MAKES NO REPRESENTATIONS OR and UNI/O are registered trademarks of Microchip Technology WARRANTIES OF ANY KIND WHETHER EXPRESS OR Incorporated in the U.S.A. and other countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MTP, SEEVAL and The Embedded Control Solutions QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Silicon Storage Technology is a registered trademark of devices in life support and/or safety applications is entirely at Microchip Technology Inc. in other countries. the buyer’s risk, and the buyer agrees to defend, indemnify and Analog-for-the-Digital Age, Application Maestro, BodyCom, hold harmless Microchip from any and all damages, claims, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, suits, or expenses resulting from such use. No licenses are dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, conveyed, implicitly or otherwise, under any Microchip ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial intellectual property rights. Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2012-2013, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-62077-247-8 QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures == ISO/TS 16949 == are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2012-2013 Microchip Technology Inc. DS20002321C-page 49

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