MCP6401/1R/1U/2/4/6/7/9 1 MHz, 45 µA Op Amps Features Description • Low Quiescent Current: 45µA (typical) The Microchip Technology Inc. • Gain Bandwidth Product: 1MHz (typical) MCP6401/1R/1U/2/4/6/7/9 family of operational amplifiers (op amps) has low quiescent current • Rail-to-Rail Input and Output (45µA,typical) and rail-to-rail input and output • Supply Voltage Range: 1.8V to 6.0V operation. This family is unity gain stable and has a • Unity Gain Stable gain bandwidth product of 1MHz (typical). These • Extended Temperature Ranges: devices operate with a power supply voltage of 1.8V to - -40°C to +125°C (E temp) 6.0V. These features make the family of op amps well - -40°C to +150°C (H temp) suited for single-supply, battery-powered applications. • No Phase Reversal The MCP6401/1R/1U/2/4/6/7/9 family is designed with Microchip’s advanced CMOS process and offered in Applications single, dual and quad packages. The devices are available in two extended temperature ranges (E temp • Portable Equipment and H temp) with different package types, which • Battery Powered System makes them well-suited for automotive and industrial • Medical Instrumentation applications. • Automotive Electronics • Data Acquisition Equipment • Sensor Conditioning • Analog Active Filters Design Aids • SPICE Macro Models • FilterLab® Software • Microchip Advanced Part Selector (MAPS) • Analog Demonstration and Evaluation Boards • Application Notes Typical Application R 2 D 2 V R IN 1 V OUT MCP6401 D 1 Precision Half-Wave Rectifier © 2009-2011 Microchip Technology Inc. DS22229D-page 1

MCP6401/1R/1U/2/4/6/7/9 E Temp Package Types H Temp Package Types MCP6401 MCP6401R MCP6401 MCP6402 SC70-5, SOT-23-5 SOT-23-5 SOT-23-5 SOIC VOUT 1 5 VDD VOUT 1 5 VSS VOUT 1 5 VDD VOUTA 1 8 VDD VSS 2 VDD 2 VSS 2 VINA– 2 7 VOUTB VIN+ 3 4 VIN– VIN+ 3 4 VIN– VIN+ 3 4 VIN– VINA+ 3 6 VINB– VSS 4 5 VINB+ MCP6402 MCP6401U MCP6404 MCP6406 SOIC SOT-23-5 SOIC SOT-23-5 VVVOIIVNNUAAST+–SA 1234 8765 VVVVDOIINNDUBBT–+B VVVIINNS+–S 123 54 VVDODUT VVVOIINNUAAT+–A 123 111432VVVOIINNUDDT–+D VVVOINUS+ST 123 54 VVDIND– VDD 4 11VSS VINB+ 5 10VINC+ MCP6402 MCP6404 VINB– 6 9 VINC– 2x3TDFN SOIC, TSSOP VOUTB 7 8 VOUTC VOUTA 1 8 VDD VOUTA 1 14VOUTD VINA– 2 EP 7 VOUTBVINA– 2 13VIND– MCP6407 MCP6409 VINA+ 3 9 6 VINB– VINA+ 3 12VIND+ SOIC SOIC V 4 5 V + VDD 4 11VSS SS INB VVVOIIUNNBTB+B– 567 1980VVVIIONNUCCT+–C VVVOIIVNNUAAST+–SA 1234 8756 VVVVDOIINNDUBBT–+BVVVOIIVNNUDAAT+D–A 2134 11111432VVVVSOIINNSUDDT–+D * Includes Exposed Thermal Pad (EP); see Table3-1. VINB+ 5 10VINC+ E temp: -40°C to +125°C VINB– 6 9 VINC– VOUTB 7 8 VOUTC H temp: -40°C to +150°C DS22229D-page 2 © 2009-2011 Microchip Technology Inc.

MCP6401/1R/1U/2/4/6/7/9 1.0 ELECTRICAL † Notice: Stresses above those listed under “Absolute CHARACTERISTICS Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions 1.1 Absolute Maximum Ratings † above those indicated in the operational listings of this specification is not implied. Exposure to maximum rat- V – V ........................................................................7.0V DD SS ing conditions for extended periods may affect device Current at Input Pins.....................................................±2mA reliability. Analog Inputs (VIN+, VIN-)††..........VSS –1.0V to VDD +1.0V †† See Section4.1.2 “Input Voltage Limits”. All Other Inputs and Outputs .........V –0.3V to V +0.3V SS DD Difference Input Voltage ......................................|V – V | DD SS Output Short-Circuit Current ................................Continuous Current at Output and Supply Pins ............................±30mA Storage Temperature....................................-65°C to +150°C Maximum Junction Temperature (T )..........................+155°C J ESD Protection on All Pins (HBM; MM; CDM)....≥ 4kV; 300V, 1500V 1.2 MCP6401/1R/1U/2/4 Electrical Specifications DC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, T =+25°C, V =+1.8v to +6.0v, V =GND, A DD SS V =V /2, V ≈V /2, V =V D/2 and R =100kΩ to V (Refer to Figure1-1). CM DD OUT DD L DD L L Parts Parameters Sym Min Typ Max Units Temp Conditions (Note1) Input Offset Input Offset Voltage V -4.5 ±0.8 +4.5 mV E, H V = V OS CM SS — ±1.0 — mV +125°C E — ±1.5 — mV +150°C H Input Offset Drift with ΔV /ΔT — ±2.0 — µV/°C -40°C E V = V OS A CM SS Temperature to +125°C — ±2.5 — µV/°C -40°C H to +150°C Power Supply PSRR 63 78 — dB E, H V = V CM SS Rejection Ratio — 75 — dB +125°C E — 73 — dB +150°C H Input Bias Current and Impedance Input Bias Current I — 1 100 pA E, H B — 30 — pA +85°C E, H — 800 — pA +125°C E — 7 — nA +150°C H Input Offset Current I — 1 — pA E, H OS — 5 — pA +85°C E, H — 20 — pA +125°C E — 45 — pA +150°C H Note 1: E part stands for the one whose operating temperature range is from -40°C to +125°C and H part stands for the one whose operating temperature range is from -40°C to +150°C. 2: Figure2-14 shows how V changes across temperature. CMR © 2009-2011 Microchip Technology Inc. DS22229D-page 3

MCP6401/1R/1U/2/4/6/7/9 DC ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise indicated, T =+25°C, V =+1.8v to +6.0v, V =GND, A DD SS V =V /2, V ≈V /2, V =V D/2 and R =100kΩ to V (Refer to Figure1-1). CM DD OUT DD L DD L L Parts Parameters Sym Min Typ Max Units Temp Conditions (Note1) Common Mode Input Z — 1013||6 — Ω||pF E, H CM Impedance Differential Input Z — 1013||6 — Ω||pF E, H DIFF Impedance Common Mode Common Mode Input V V -0.20 — V +0.20 V E, H V = 1.8V CMR SS DD DD Voltage Range V -0.05 — V +0.05 V +125°C E SS DD (Note2) V — V V +150°C H SS DD V -0.30 — V +0.30 V E, H V = 6.0V SS DD DD V -0.15 — V +0.15 V +125°C E SS DD V -0.10 — V +0.10 V +150°C H SS DD Common Mode CMRR 56 71 — dB E, H V = -0.2V to 2.0V, CM Rejection Ratio V = 1.8V DD — 68 — dB +125°C E V = -0.05V to 1.85V, CM V = 1.8V DD — 65 — dB +150°C H V = 0V to 1.8V, CM V = 1.8V DD 63 78 — dB E, H V = -0.3V to 6.3V, CM V = 6.0V DD — 76 — dB +125°C E V = -0.15V to 6.15V, CM V = 6.0V DD — 75 — dB +150°C H V = -0.1V to 6.1V, CM V = 6.0V DD Open-Loop Gain DC Open-Loop Gain A 90 110 — dB E, H V = 0.3V to V - OL OUT DD (Large Signal) 0.3V, — 105 — dB +125°C E V = V — 100 — dB +150°C H CM SS Output High-Level Output V 1.790 1.792 — V E, H V = 1.8V OH DD Voltage — 1.788 — V +125°C E RL = 10kΩ 0.5V input overdrive — 1.785 — V +150°C H 5.980 5.985 — V E, H V = 6.0V DD — 5.980 — V +125°C E RL = 10kΩ 0.5V input overdrive — 5.975 — V +150°C H Low-Level Output V — 0.008 0.010 V E, H V = 1.8V OL DD Voltage — 0.012 — V +125°C E RL = 10kΩ 0.5V input overdrive — 0.015 — V +150°C H — 0.015 0.020 V E, H V = 6.0V DD — 0.020 — V +125°C E RL = 10kΩ 0.5V input overdrive — 0.025 — V +150°C H Note 1: E part stands for the one whose operating temperature range is from -40°C to +125°C and H part stands for the one whose operating temperature range is from -40°C to +150°C. 2: Figure2-14 shows how V changes across temperature. CMR DS22229D-page 4 © 2009-2011 Microchip Technology Inc.

MCP6401/1R/1U/2/4/6/7/9 DC ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise indicated, T =+25°C, V =+1.8v to +6.0v, V =GND, A DD SS V =V /2, V ≈V /2, V =V D/2 and R =100kΩ to V (Refer to Figure1-1). CM DD OUT DD L DD L L Parts Parameters Sym Min Typ Max Units Temp Conditions (Note1) Output Short-Circuit I — ±5 — mA E, H V = 1.8V SC DD Current — ±15 — mA E, H V = 6.0V DD Power Supply Supply Voltage V 1.8 — 6.0 V E, H DD Quiescent Current I 20 45 70 µA E, H I = 0, V = 5.0V Q O DD per Amplifier — 55 — µA +125°C E VCM = 0.2VDD — 60 — µA +150°C H Note 1: E part stands for the one whose operating temperature range is from -40°C to +125°C and H part stands for the one whose operating temperature range is from -40°C to +150°C. 2: Figure2-14 shows how V changes across temperature. CMR AC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, T =+25°C, V = +1.8 to +6.0V, V =GND, V =V /2, A DD SS CM DD V ≈V /2, V =V /2, R =100kΩ to V and C =60pF (Refer to Figure1-1). OUT DD L DD L L L Parameters Sym Min Typ Max Units Parts Conditions AC Response Gain Bandwidth Product GBWP — 1 — MHz E, H Phase Margin PM — 65 — ° E, H G = +1V/V Slew Rate SR — 0.5 — V/µs E, H Noise Input Noise Voltage E — 3.6 — µVp-p E, H f = 0.1Hz to 10Hz ni Input Noise Voltage Density e — 28 — nV/√Hz E, H f = 1kHz ni Input Noise Current Density i — 0.6 — fA/√Hz E, H f = 1kHz ni TEMPERATURE SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, V =+1.8V to +6.0V and V =GND. DD SS Parameters Sym Min Typ Max Units Conditions Temperature Ranges Operating Temperature Range T -40 — +125 °C E temp parts (Note1) A T -40 — +150 °C H temp parts (Note1) A Storage Temperature Range T -65 — +155 °C A Thermal Package Resistances Thermal Resistance, 5L-SC70 θ — 331 — °C/W JA Thermal Resistance, 5L-SOT-23 θ — 220.7 — °C/W JA Thermal Resistance, 8L-SOIC θ — 149.5 — °C/W JA Thermal Resistance, 8L-2x3 TDFN θ — 52.5 — °C/W JA Thermal Resistance, 14L-SOIC θ — 95.3 — °C/W JA Thermal Resistance, 14L-TSSOP θ — 100 — °C/W JA Note 1: The internal junction temperature (T ) must not exceed the absolute maximum specification of +155°C. J © 2009-2011 Microchip Technology Inc. DS22229D-page 5

MCP6401/1R/1U/2/4/6/7/9 1.3 MCP6406/7/9 Electrical Specifications DC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, T =+25°C, V =+1.8V to +6.0V, V =GND, A DD SS V =V /2, V »V /2, V =V /2 and R =100kΩ to V (Refer to Figure1-1). CM DD OUT DD L DD L L Parts Parameters Sym Min Typ Max Units Temp Conditions (Note1) Input Offset Input Offset Voltage V -4.5 — +4.5 mV E, H V = V OS CM SS -5.0 ±1.0 +5.0 mV +125°C E -5.5 ±1.5 +5.5 mV +150°C H Input Offset Drift ΔV /DT — ±2.0 — µV/°C -40°C E V = V OS A CM SS with Temperature to +125°C — ±2.5 — µV/°C -40°C H to +150°C Power Supply PSRR 63 78 — dB E, H V = V CM SS Rejection Ratio 60 75 — dB +125°C E 58 73 — dB +150°C H Input Bias Current and Impedance Input Bias Current I — ±1 100 pA E, H B — 30 — pA +85°C E, H — 800 2000 pA +125°C E — 7 12 nA +150°C H Input Offset Current I — 1 — pA E, H OS — 5 — pA +85°C E, H — 20 — pA +125°C E — 45 — pA +150°C H Common Mode Z — 1013||6 — Ω||pF E, H CM Input Impedance Differential Input Z — 1013||6 — Ω||pF E, H DIFF Impedance Common Mode Common Mode V V -0.20 — V +0.20 V E, H V = 1.8V CMR SS DD DD Input Voltage Range V -0.05 — V +0.05 V +125°C E SS DD (Note2) V — V V +150°C H SS DD V -0.30 — V +0.30 V E, H V = 6.0V SS DD DD V -0.15 — V +0.15 V +125°C E SS DD V -0.10 — V +0.10 V +150°C H SS DD Note 1: E part stands for the one whose operating temperature range is from -40°C to +125°C and H part stands for the one whose operating temperature range is from -40°C to +150°C. 2: Figure2-14 shows how V changes across temperature. CMR DS22229D-page 6 © 2009-2011 Microchip Technology Inc.

MCP6401/1R/1U/2/4/6/7/9 DC ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise indicated, T =+25°C, V =+1.8V to +6.0V, V =GND, A DD SS V =V /2, V »V /2, V =V /2 and R =100kΩ to V (Refer to Figure1-1). CM DD OUT DD L DD L L Parts Parameters Sym Min Typ Max Units Temp Conditions (Note1) Common Mode CMRR 56 71 — dB E, H V = -0.2V to 2.0V, CM Rejection Ratio V = 1.8V DD 53 68 — dB +125°C E V = -0.05V to 1.85V, CM V = 1.8V DD 50 65 — dB +150°C H V = 0V to 1.8V, CM V = 1.8V DD 63 78 — dB E, H V = -0.3V to 6.3V, CM V = 6.0V DD 61 76 — dB +125°C E V = -0.15V to 6.15V, CM V = 6.0V DD 60 75 — dB +150°C H V = -0.1V to 6.1V, CM V = 6.0V DD Open-Loop Gain DC Open-Loop Gain A 90 110 — dB E, H V = 0.3V to OL OUT (Large Signal) 88 105 — dB +125°C E VDD-0.3V, VCM = VSS 85 100 — dB +150°C H Output High-Level Output V 1.790 1.792 — V E, H V = 1.8V OH DD Voltage 1.785 1.788 — V +125°C E RL = 10kΩ 0.5V input overdrive 1.782 1.785 — V +150°C H 5.980 5.985 — V E, H V = 6.0V DD 5.970 5.980 — V +125°C E RL = 10kΩ 0.5V input overdrive 5.965 5.975 — V +150°C H Low-Level Output V — 0.008 0.010 V E, H V = 1.8V OL DD Voltage — 0.012 0.015 V +125°C E RL = 10kΩ 0.5V input overdrive — 0.015 0.018 V +150°C H — 0.015 0.020 V E, H V = 6.0V DD — 0.020 0.030 V +125°C E RL = 10kΩ 0.5V input overdrive — 0.025 0.035 V +150°C H Output Short-Circuit I — ±5 — mA E, H V = 1.8V SC DD Current — ±15 — mA E, H V = 6.0V DD Power Supply Supply Voltage V 1.8 — 6.0 V E, H DD Quiescent Current I 20 45 70 µA E, H I = 0, V = 5.0V Q O DD per Amplifier 30 55 80 µA +125°C E VCM = 0.2VDD 35 60 90 µA +150°C H Note 1: E part stands for the one whose operating temperature range is from -40°C to +125°C and H part stands for the one whose operating temperature range is from -40°C to +150°C. 2: Figure2-14 shows how V changes across temperature. CMR © 2009-2011 Microchip Technology Inc. DS22229D-page 7

MCP6401/1R/1U/2/4/6/7/9 AC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, T = +25°C, V = +1.8 to +6.0V, V = GND, V = V /2, A DD SS CM DD V ≈V /2, V = V /2, R = 100kΩ to V and C = 60pF (Refer to Figure1-1). OUT DD L DD L L L Parameters Sym Min Typ Max Units Part Conditions AC Response Gain Bandwidth Product GBWP — 1 — MHz E, H Phase Margin PM — 65 — ° E, H G = +1V/V Slew Rate SR — 0.5 — V/µs E, H Noise Input Noise Voltage E — 3.6 — µVp-p E, H f = 0.1Hz to 10Hz ni Input Noise Voltage Density e — 28 — nV/√Hz E, H f = 1kHz ni Input Noise Current Density i — 0.6 — fA/√Hz E, H f = 1kHz ni TEMPERATURE SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, V = +1.8V to +6.0V and V = GND. DD SS Parameters Sym Min Typ Max Units Conditions Temperature Ranges Operating Temperature Range T -40 — +125 °C E temp parts (Note1) A T -40 — +150 °C H temp parts (Note1) A Storage Temperature Range T -65 — +155 °C A Thermal Package Resistances Thermal Resistance, 5L-SOT-23 θ — 220.7 — °C/W JA Thermal Resistance, 8L-SOIC θ — 149.5 — °C/W JA Thermal Resistance, 14L-SOIC θ — 95.3 — °C/W JA Note 1: The internal junction temperature (T ) must not exceed the absolute maximum specification of +155°C. J 1.4 Test Circuits C The circuit used for most DC and AC tests is shown in F 6.8pF Figure1-1. This circuit can independently set V and CM V ; see Equation1-1. Note that V is not the OUT CM circuit’s Common Mode voltage ((VP+VM)/2), and that RG RF V includes V plus the effects (on the input offset 100kΩ 100kΩ OST OS error, VOST) of temperature, CMRR, PSRR and AOL. VP VDD/2 V DD V EQUATION 1-1: IN+ C C B1 B2 GDM = RF⁄RG MCP640x 100nF 1µF V = (V +V ⁄2)⁄2 CM P DD V V = V –V IN– OST IN– IN+ V = (V ⁄2)+(V –V )+V (1+G ) V V OUT DD P M OST DM M OUT RG RF RL CL Where: 100kΩ 100kΩ 100kΩ 60pF G = Differential Mode Gain (V/V) DM V = Op Amp’s Common Mode (V) C CM F V Input Voltage 6.8pF L V = Op Amp’s Total Input Offset (mV) OST FIGURE 1-1: AC and DC Test Circuit for Voltage Most Specifications. DS22229D-page 8 © 2009-2011 Microchip Technology Inc.

MCP6401/1R/1U/2/4/6/7/9 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, T = +25°C, V = +1.8V to +6.0V, V = GND, V = V /2, V ≈V /2, A DD SS CM DD OUT DD V = V /2, R = 100kΩ to V and C = 60pF. L DD L L L 24% 45% ences 1281%% 1V7C6M0 = S VaSmSples ences 3450%% 1VT7AC6M=0=- S4 V0aS°mSCp tloe s+125°C ur ur 30% Occ15% Occ 25% of 12% of 20% e e ag 9% ag 15% Percent 36%% Percent 105%% 0% 0% -10 -8 -6 -4 -2 0 2 4 6 8 10 -5 -4 -3 -2 -1 0 1 2 3 4 5 Input Offset Voltage Drift (μV/°C) Input Offset Voltage (mV) FIGURE 2-1: Input Offset Voltage. FIGURE 2-4: Input Offset Voltage Drift. 24% 50% Occurences 112581%%% 1VT2AC0M=0 =+ S 1Va2Sm5SºpCles Occurences 33440505%%%% 1VT2AC0M=0=- S4 V0aS°mSCp tloe s+150°C Percentage of 12369%%%% Percentage of 112205055%%%%% 0% 0% -5 -4 -3 -2 -1 0 1 2 3 4 5 -10 -8 -6 -4 -2 0 2 4 6 8 10 Input Offset Voltage (mV) Input Offset Voltage Drift (μV/°C) FIGURE 2-2: Input Offset Voltage. FIGURE 2-5: Input Offset Voltage Drift. 24% 1000 of Occurences 11122581%%%% 1VT2AC0M=0 =+ S 1Va5Sm0SºpCles et Voltage (μV) 2468000000000 VRPDaeDrptr=e 6s.e0nVtative TTAA== +-4205°°CC ercentage 369%%% Input Offs ----864200000000 TTTAAA=== +++11852505°C°°CC P 0% -1000 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 -5 -4 -3 -2 -1 0 1 2 3 4 5 0. 0. 0. 1. 1. 2. 2. 3. 3. 4. 4. 5. 5. 6. 6. Input Offset Voltage (mV) - Common Mode Input Voltage (V) FIGURE 2-3: Input Offset Voltage. FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage with V = 6.0V. DD © 2009-2011 Microchip Technology Inc. DS22229D-page 9

MCP6401/1R/1U/2/4/6/7/9 Note: Unless otherwise indicated, T = +25°C, V = +1.8V to +6.0V, V = GND, V = V /2, V ≈V /2, A DD SS CM DD OUT DD V = V /2, R = 100kΩ to V and C = 60pF. L DD L L L 1400 1,000 μV)11020000 VRDeDpr=e 1s.e8nVtative sity e ( 800 Part en g D Input Offset Volta---6422460000000000000 TTTTTAAAAA===== ++++-4118205255°05°°CCC°°CC put Noise Voltage (nV/Hz)√100 -800 In 5 3 1 1 3 5 7 9 1 3 5 7 9 1 3 10 0. 0. 0. 0. 0. 0. 0. 0. 1. 1. 1. 1. 1. 2. 2. 00..11 1 1 101 0 10100 0 1k10 0 0 1010k0 0 0 101000k000 - - -Common Mode Input Voltage (V) Frequency (Hz) FIGURE 2-7: Input Offset Voltage vs. FIGURE 2-10: Input Noise Voltage Density Common Mode Input Voltage with V = 1.8V. vs. Frequency. DD 1000 y 40 V) 750 sit 35 µ n e ( 500 De 30 Input Offset Voltag ---7522505500000 VDD = 1.8VVDD =R 6e.0pVresentative Part nput Noise Voltage (nV/Hz)√112205055 fV =DD 1 = k 6H.z0 V -1000 I 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 Output Voltage (V) Common Mode Input Voltage (V) FIGURE 2-8: Input Offset Voltage vs. FIGURE 2-11: Input Noise Voltage Density Output Voltage. vs. Common Mode Input Voltage. 200 100 oltage (μV) -1100000 TTAA== ++115205°°CC Representative Part R (dB)789000 PSRR-PSRR+ RCepMrResRentative Part V R et -200 PS60 Input Offs --430000 TTTAAA=== ++-482055°°°CCC CMRR, 345000 -500 20 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 1 100 110000 110k0 0 1 1000k0 0 1 100000k0 0 1 010M0000 Power Supply Voltage (V) Frequency (Hz) FIGURE 2-9: Input Offset Voltage vs. FIGURE 2-12: CMRR, PSRR vs. Power Supply Voltage. Frequency. DS22229D-page 10 © 2009-2011 Microchip Technology Inc.

MCP6401/1R/1U/2/4/6/7/9 Note: Unless otherwise indicated, T = +25°C, V = +1.8V to +6.0V, V = GND, V = V /2, V ≈V /2, A DD SS CM DD OUT DD V = V /2, R = 100kΩ to V and C = 60pF. L DD L L L 90 10000 85 PSRR (VDD= 1.8V to 6.0V) A) TA= +150°C dB) 80 nt (p1000 SRR ( 7705 Curre 100 TA= +125°C RR,P 65 CMRR (VDD= 6.0V) Bias CM 60 CMRR (VDD= 1.8V) put 10 TA= +85°C 55 In VDD= 6.0V 1 50 0 5 0 5 0 5 0 5 0 5 0 5 0 -50 -25 0 25 50 75 100 125 150 0. 0. 1. 1. 2. 2. 3. 3. 4. 4. 5. 5. 6. Ambient Temperature (°C) Common Mode Input Voltage (V) FIGURE 2-13: CMRR, PSRR vs. Ambient FIGURE 2-16: Input Bias Current vs. Temperature. Common Mode Input Voltage. 0.4 65 e ag 0.3 60 mon Mode Input VoltRange Limits (V)--00000.....01221 VCMR_H-VOHV@@CMV RVVO_DDLLDD--==VV 1SS6SS..80@@VV VVDDDD== 16..80VV Quiescent Current (μA/Amplifier) 3445550505 VVVDDDDDD=== 651...008VVV om -0.3 30 VCM= 0.2VDD C -0.4 25 -50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150 Ambient Temperature (°C) Ambient Temperature (°C) FIGURE 2-14: Common Mode Input FIGURE 2-17: Quiescent Current vs. Voltage Range Limits vs. Ambient Temperature. Ambient Temperature. et 10000 80 Bias Current, Input OffsCurrent (pA) 101010000 VDDI=n p6.u0tV Bias Current Quiescent Current (μA/Amplifier) 12345670000000 VCM= 0.2VDD TTTTTAAAAA===== +++- 4+18201255°55°°CCC0°C°C ut Input Offset Current p 0 n 1 I 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 25 50 75 100 125 150 0. 0. 1. 1. 2. 2. 3. 3. 4. 4. 5. 5. 6. 6. 7. Ambient Temperature (°C) Power Supply Voltage (V) FIGURE 2-15: Input Bias, Offset Current FIGURE 2-18: Quiescent Current vs. vs. Ambient Temperature. Power Supply Voltage. © 2009-2011 Microchip Technology Inc. DS22229D-page 11

MCP6401/1R/1U/2/4/6/7/9 Note: Unless otherwise indicated, T = +25°C, V = +1.8V to +6.0V, V = GND, V = V /2, V ≈V /2, A DD SS CM DD OUT DD V = V /2, R = 100kΩ to V and C = 60pF. L DD L L L 120 0 1.6 90 Open-Loop Gain (dB)10246800000 Open-Loop GOapinen-Loop Phase -----119635200000 Open-Loop Phase (°) Bandwidth Product (MHz) 0111111.......9012345 GPaihna Bsea nMdawrgidinth Product 56677885050505 Phase Margin (°) 0 VDD = 6.0V -180 ain 0.8 VDD= 6.0V 50 -20 -210 G 0.7 45 1 0.0E.-101 1 . 01E+ 0 0 11.0E0+0 1 11.00E+002 1 .10Ek+0 3 11.0E0+k04 11.00E+005k 1 .10EM+06 110.0ME+07 -50 -25 0 25 50 75 100 125 150 Frequency (Hz) Temperature (°C) FIGURE 2-19: Open-Loop Gain, Phase vs. FIGURE 2-22: Gain Bandwidth Product, Frequency. Phase Margin vs. Ambient Temperature. 150 1.6 90 B)145 MHz) 1.5 85 ain (d113450 duct ( 11..34 Phase Margin 7850 n (°) DC Open-Loop G111111011223505050 RVSL S= + 1 00. 3kVΩ < VOUT < VDD - 0.3V ain Bandwidth Pro 00111.....89012 VDD= 1.8V Gain Bandwidth Product 5566705050 Phase Margi 100 G 0.7 45 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 -50 -25 0 25 50 75 100 125 150 Power Supply Voltage (V) Temperature (°C) FIGURE 2-20: DC Open-Loop Gain vs. FIGURE 2-23: Gain Bandwidth Product, Power Supply Voltage. Phase Margin vs. Ambient Temperature. B)114550 ent 25 n (d140 VDD = 6.0V Curr 20 TA=-40°C pen-Loop Gai111111223350505 VDD = 1.8V Short Circuit (mA) 1105 TTTTAAAA==== ++++1128255550°°CC°°CC DC O110150 Large Signal AOL utput 5 100 O 0 0.00 0.05 0.10 0.15 0.20 0.25 0 5 0 5 0 5 0 5 0 5 0 5 0 Output Voltage Headroom 0. 0. 1. 1. 2. 2. 3. 3. 4. 4. 5. 5. 6. Power Supply Voltage (°V) V - V or V -V (V) DD OH OL SS FIGURE 2-21: DC Open-Loop Gain vs. FIGURE 2-24: Output Short Circuit Current Output Voltage Headroom. vs. Power Supply Voltage. DS22229D-page 12 © 2009-2011 Microchip Technology Inc.

MCP6401/1R/1U/2/4/6/7/9 Note: Unless otherwise indicated, T = +25°C, V = +1.8V to +6.0V, V = GND, V = V /2, V ≈V /2, A DD SS CM DD OUT DD V = V /2, R = 100kΩ to V and C = 60pF. L DD L L L 10 0.9 )P-P VDD = 6.0V 0.8 Falling Edge, VDD= 6.0V wing (V VDD = 1.8V V/μs)00..67 Rising Edge, VDD= 6.0V Output Voltage S 1 Slew Rate (0000....2345 RisiFnagl lEindgg Ee,d VgDeD, V= D1D.8=V 1.8V 0.1 0.1 100 1k 10k 100k 1M -50 -25 0 25 50 75 100 125 150 100 1000 10000 100000 1000000 Frequency (Hz) Temperature (°C) FIGURE 2-25: Output Voltage Swing vs. FIGURE 2-28: Slew Rate vs. Ambient Frequency. Temperature. 1000 m droo 100 VDD - VOH @ VDD = 1.8V v/div) Hea VOL - VSS @ VDD = 1.8V 0 m age mV) 10 ge (2 Volt( olta Output 1 V VOLD D- -V VSSO H@ @ V DVDD D= =6 .60.V0V RL = 10 kΩ Output V VGD =D =+ 16 V.0/VV 0.1 01.001 100.10 1 10 0 0 1100000 Output Current (mA) Time (2 µs/div) FIGURE 2-26: Output Voltage Headroom FIGURE 2-29: Small Signal Non-Inverting vs. Output Current. Pulse Response. 24 Output Voltage Headroom V-Vor V-V(mV)DDOHOLSS 11122581369 VVDODL--VVSOVVSH@ DO@DL V --VDVVDDSODS=H= @@6 6. 0 .VV0VDVDDD== 11..88VV utput Voltage (20 mv/div) VGD =D -=1 6 V.0/VV O 0 -50 -25 0 25 50 75 100 125 150 Ambient Temperature (°C) Time (2 µs/div) FIGURE 2-27: Output Voltage Headroom FIGURE 2-30: Small Signal Inverting Pulse vs. Ambient Temperature. Response. © 2009-2011 Microchip Technology Inc. DS22229D-page 13

MCP6401/1R/1U/2/4/6/7/9 Note: Unless otherwise indicated, T = +25°C, V = +1.8V to +6.0V, V = GND, V = V /2, V ≈V /2, A DD SS CM DD OUT DD V = V /2, R = 100kΩ to V and C = 60pF. L DD L L L 6.0 10000 5.5 Output Voltage (V)12233445........50505050 VGD =D =+ 16 .V0/VV Closed Loop Output Impedance ((cid:2))110100000 11G01N1 :V V/V/V 1 V/V 1.0 0.5 1 0.0 1 .10E0+ 0 1 11.00E0+0 2 1 1.0Ek+ 0 3 11.00E+k04 11.00E0+0k5 11.0ME+06 Time (20 µs/div) Frequency (Hz) FIGURE 2-31: Large Signal Non-Inverting FIGURE 2-34: Closed Loop Output Pulse Response. Impedance vs. Frequency. 6.0 1.100Em-03 5.5 110.000E-μ04 5.0 11.000Eμ-05 utput Voltage (V)223344......050505 VGD =D =-1 6 V.0/VV -I(A)IN 1101011111.....000000110000000EEEEEnnμ-----np0000167890 TTTTTAAAAA===== ++++-4112802555°50°°CCC°°CC O1.5 11.000E-p11 1.0 0.5 1.010Ep-12 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.0 V (V) Time (20 µs/div) IN FIGURE 2-32: Large Signal Inverting Pulse FIGURE 2-35: Measured Input Current vs. Response. Input Voltage (below V ). SS 7.0 n 150 o put Voltages (V) 3456....0000 VIN VOUT Channel Separati(dB) 111112340000 nput, Out 012...000 VGD =D =+ 26 .V0/VV annel to 10900 Input Referred I h C -1.0 80 110000 1100k0 1 010000k 10010k0000 Time (0.1 ms/div) Frequency (Hz) FIGURE 2-33: The FIGURE 2-36: Channel-to-Channel MCP6401/1R/1U/2/4/6/7/9 Shows No Phase Separation vs. Frequency (MCP6402/4/7/9 only). Reversal. DS22229D-page 14 © 2009-2011 Microchip Technology Inc.

© 3.0 PIN DESCRIPTIONS 2 0 09 Descriptions of the pins are listed in Table3-1. -2 0 1 TABLE 3-1: PIN FUNCTION TABLE 1 1 M ic MCP6401 MCP6401R MCP6401U MCP6402 MCP6404 MCP6406 MCP6407 MCP6409 roc SC70-5, 2x3 SOIC, Symbol Description h SOT-23-5 SOT-23-5 SOIC SOT-23-5 SOIC SOIC ip SOT-23-5 TDFN TSSOP T ec 1 1 4 1 1 1 1 1 1 VOUT, VOUTA Analog Output (op amp A) h nolo 4 4 3 2 2 2 4 2 2 VIN–, VINA– Inverting Input (op amp A) gy 3 3 1 3 3 3 3 3 3 VIN+, VINA+ Non-inverting Input (op amp A) Inc. 5 2 5 8 8 4 5 8 4 VDD Positive Power Supply — — — 5 5 5 — 5 5 V + Non-inverting Input (op amp B) INB — — — 6 6 6 — 6 6 V – Inverting Input (op amp B) INB — — — 7 7 7 — 7 7 V Analog Output (op amp B) OUTB — — — — — 8 — — 8 V Analog Output (op amp C) OUTC — — — — — 9 — — 9 V – Inverting Input (op amp C) INC M — — — — — 10 — — 10 V + Non-inverting Input (op amp C) INC C 2 5 2 4 4 11 2 4 11 V Negative Power Supply SS P — — — — — 12 — — 12 V + Non-inverting Input (op amp D) IND — — — — — 13 — — 13 V – Inverting Input (op amp D) 6 IND 4 — — — — — 14 — — 14 V Analog Output (op amp D) OUTD 0 — — — — 9 — — — — EP Exposed Thermal Pad (EP); must be 1 connected to V . SS / 1 R / 1 U / 2 D / S 4 2 2 / 22 6 9 D / -p 7 a ge / 1 9 5

MCP6401/1R/1U/2/4/6/7/9 3.1 Analog Output (V ) OUT The output pin is low-impedance voltage source. 3.2 Analog Inputs (V +, V -) IN IN The non-inverting and inverting inputs are high- impedance CMOS inputs with low bias currents. 3.3 Power Supply Pin (V , V ) DD SS The positive power supply (V ) is 1.8V to 6.0V higher DD than the negative power supply (V ). For normal SS operation, the other pins are at voltages between V SS and V . DD Typically, these parts are used in a single (positive) supply configuration. In this case, V is connected to SS ground and V is connected to the supply. V will DD DD need bypass capacitors. DS22229D-page 16 © 2009-2011 Microchip Technology Inc.

MCP6401/1R/1U/2/4/6/7/9 4.0 APPLICATION INFORMATION V The MCP6401/1R/1U/2/4/6/7/9 family of op amps is DD manufactured using Microchip’s state-of-the-art CMOS process and is specifically designed for low-power, high-precision applications. D1 D2 U1 V 1 V OUT 4.1 Rail-to-Rail Input MCP640x V 2 4.1.1 PHASE REVERSAL The MCP6401/1R/1U/2/4/6/7/9 op amps are designed FIGURE 4-2: Protecting the Analog to prevent phase reversal when the input pins exceed Inputs. the supply voltages. Figure2-33 shows the input voltage exceeding the supply voltage with no phase A significant amount of current can flow out of the reversal. inputs when the Common Mode voltage (V ) is below CM ground (V ); See Figure2-35. SS 4.1.2 INPUT VOLTAGE LIMITS 4.1.3 INPUT CURRENT LIMITS In order to prevent damage and/or improper operation of these amplifiers, the circuit must limit the voltages at In order to prevent damage and/or improper operation the input pins (see Section1.1 “Absolute Maximum of these amplifiers, the circuit must limit the currents Ratings †”). into the input pins (see Section1.1 “Absolute Maximum Ratings †”). The ESD protection on the inputs can be depicted as Figure4-3 shows one approach to protecting these shown in Figure4-1. This structure was chosen to inputs. The resistors R and R limit the possible protect the input transistors against many (but not all) 1 2 currents in or out of the input pins (and the ESD diodes, over-voltage conditions, and to minimize the input bias D and D ). The diode currents will go through either current (I ). 1 2 B V or V . DD SS V Bond VDD DD Pad D D 1 2 U 1 V Bond Input Bond 1 V V + V – OUT IN Pad Stage Pad IN R1 MCP640x V 2 R 2 Bond V V –min(V , V ) SS Pad min(R ,R )> SS 1 2 1 2 2mA FIGURE 4-1: Simplified Analog Input ESD max(V ,V )–V 1 2 DD min(R ,R )> Structures. 1 2 2mA The input ESD diodes clamp the inputs when they try FIGURE 4-3: Protecting the Analog to go more than one diode drop below V . They also Inputs. SS clamp any voltages that go well above V ; their DD 4.1.4 NORMAL OPERATION breakdown voltage is high enough to allow normal The input stage of the MCP6401/1R/1U/2/4/6/7/9 op operation, but not low enough to protect against slow amps use two differential input stages in parallel. One over-voltage (beyond V ) events. Very fast ESD DD operates at a low Common Mode input voltage (V ), events (that meet the spec) are limited so that damage CM while the other operates at a high V . With this does not occur. CM topology, the device operates with a V up to 300mV CM In some applications, it may be necessary to prevent above V and 300mV below V (see Figure2-14). DD SS excessive voltages from reaching the op amp inputs; The input offset voltage is measured at V = V – CM SS Figure4-2 shows one approach to protecting these 0.3V and V +0.3V to ensure proper operation. DD inputs. The transition between the input stages occurs when V is near V –1.1V (see Figures2-6 and 2-7). For CM DD the best distortion performance and gain linearity, with non-inverting gains, avoid this region of operation. © 2009-2011 Microchip Technology Inc. DS22229D-page 17

MCP6401/1R/1U/2/4/6/7/9 4.2 Rail-to-Rail Output After selecting R for your circuit, double-check the ISO resulting frequency response peaking and step The output voltage range of the response overshoot. Modify R ’s value until the ISO MCP6401/1R/1U/2/4/6/7/9 op amps is VSS+20mV response is reasonable. Bench evaluation and (minimum) and VDD – 20mV (maximum) when simulations with the MCP6401/1R/1U/2/4/6/7/9 SPICE RL=10kΩ is connected to VDD/2 and VDD=6.0V. macro model are very helpful. Refer to Figures2-26 and 2-27 for more information. 4.4 Supply Bypass 4.3 Capacitive Loads With this family of operational amplifiers, the power Driving large capacitive loads can cause stability supply pin (V for single-supply) should have a local DD problems for voltage feedback op amps. As the load bypass capacitor (i.e., 0.01µF to 0.1µF) within 2mm capacitance increases, the feedback loop’s phase for good high frequency performance. It can use a bulk margin decreases and the closed-loop bandwidth is capacitor (i.e., 1µF or larger) within 100mm to provide reduced. This produces gain peaking in the frequency large, slow currents. This bulk capacitor can be shared response, with overshoot and ringing in the step with other analog parts. response. While a unity-gain buffer (G = +1V/V) is the most sensitive to capacitive loads, all gains show the 4.5 Unused Op Amps same general behavior. When driving large capacitive loads with these op An unused op amp in quad packages (MCP6404 or amps (e.g., > 100pF when G = +1V/V), a small series MCP6409) should be configured as shown in Figure4- resistor at the output (R in Figure4-4) improves the 6. These circuits prevent the output from toggling and ISO feedback loop’s phase margin (stability) by making the causing crosstalk. Circuit A sets the op amp at its output load resistive at higher frequencies. The minimum noise gain. The resistor divider produces any bandwidth will be generally lower than the bandwidth desired reference voltage within the output voltage with no capacitance load. range of the op amp, which buffers that reference voltage. Circuit B uses the minimum number of components and operates as a comparator, but it may draw more current. – R ISO MCP640x V OUT ¼ MCP6404 (A) ¼ MCP6404 (B) V + IN CL VDD V DD V R DD 1 FIGURE 4-4: Output Resistor, R ISO Stabilizes Large Capacitive Loads. V R REF 2 Figure4-5 gives recommended R values for ISO different capacitive loads and gains. The x-axis is the normalized load capacitance (C /G ), where G is the L N N R circuit's noise gain. For non-inverting gains, GN and the V = V ×-----------2-------- Signal Gain are equal. For inverting gains, GN is REF DD R1+R2 1+|Signal Gain| (e.g., -1V/V gives G = +2V/V). N FIGURE 4-6: Unused Op Amps. 10000 VDD = 6.0 V Ω) RL = 10 kΩ (O 1000 S R I d e nd 100 GN: e 1 V/V m 2 V/V m o 10 ≥ 5 V/V c e R 1 10p 100p 1n 10n 0.1µ 1µ 1.E-11 1.E-10 1.E-09 1.E-08 1.E-07 1.E-06 Normalized Load Capacitance; C /G (F) L N FIGURE 4-5: Recommended R Values ISO for Capacitive Loads. DS22229D-page 18 © 2009-2011 Microchip Technology Inc.

MCP6401/1R/1U/2/4/6/7/9 4.6 PCB Surface Leakage 4.7 Application Circuits In applications where low input bias current is critical, 4.7.1 PRECISION HALF-WAVE Printed Circuit Board (PCB) surface leakage effects RECTIFIER need to be considered. Surface leakage is caused by humidity, dust or other contamination on the board. The precision half-wave rectifier, which is also known Under low humidity conditions, a typical resistance as a super diode, is a configuration obtained with an between nearby traces is 1012Ω. A 5V difference would operational amplifier in order to have a circuit behave cause 5pA of current to flow; which is greater than the like an ideal diode and rectifier. It effectively cancels the MCP6401/1R/1U/2/4/6/7/9 family’s bias current at forward voltage drop of the diode so that very low level +25°C (±1.0pA, typical). signals can still be rectified with minimal error. This can be useful for high-precision signal processing. The The easiest way to reduce surface leakage is to use a MCP6401/1R/1U/2/4/6/7/9 op amps have high input guard ring around sensitive pins (or traces). The guard impedance, low input bias current and rail-to-rail ring is biased at the same voltage as the sensitive pin. input/output, which makes this device suitable for An example of this type of layout is shown in precision rectifier applications. Figure4-7. Figure4-8 shows a precision half-wave rectifier and its transfer characteristic. The rectifier’s input impedance is determined by the input resistor R . To avoid loading Guard Ring V – V + V 1 IN IN SS effect, it must be driven from a low-impedance source. When V is greater than zero, D is OFF, D is ON, and IN 1 2 V is zero. When V is less than zero, D is ON, D OUT IN 1 2 is OFF, and V is the V with an amplification of OUT IN -R /R . 2 1 The rectifier circuit shown in Figure4-8 has the benefit that the op amp never goes in saturation, so the only FIGURE 4-7: Example Guard Ring Layout thing affecting its frequency response is the amplification and the gain bandwidth product. for Inverting Gain. . 1. Non-inverting Gain and Unity-Gain Buffer: a) Connect the non-inverting pin (VIN+) to the R2 input with a wire that does not touch the PCB surface. D 2 b) Connect the guard ring to the inverting input pin (VIN–). This biases the guard ring to the VIN R1 Common Mode input voltage. V OUT 2. Inverting Gain and Transimpedance Gain MCP6401 Amplifiers (convert current to voltage, such as D photo detectors): 1 a) Connect the guard ring to the non-inverting input pin (V +). This biases the guard ring IN to the same reference voltage as the op Precision Half-Wave Rectifier amp (e.g., V /2 or ground). DD b) Connect the inverting pin (V –) to the input IN V with a wire that does not touch the PCB OUT surface. -R /R 2 1 V IN Transfer Characteristic FIGURE 4-8: Precision Half-Wave Rectifier. © 2009-2011 Microchip Technology Inc. DS22229D-page 19

MCP6401/1R/1U/2/4/6/7/9 4.7.2 BATTERY CURRENT SENSING 4.7.3 INSTRUMENTATION AMPLIFIER The MCP6401/1R/1U/2/4/6/7/9 op amps’ Common The MCP6401/1R/1U/2/4/6/7/9 op amps are well Mode Input Range, which goes 0.3V beyond both suited for conditioning sensor signals in battery- supply rails, supports their use in high-side and low- powered applications. Figure4-10 shows a two op amp side battery current sensing applications. The low instrumentation amplifier, using the MCP6402, that quiescent current (45µA, typical) helps prolong battery works well for applications requiring rejection of life, and the rail-to-rail output supports detection of low Common Mode noise at higher gains. The reference currents. voltage (V ) is supplied by a low impedance source. REF In single supply applications, V is typically V /2. Figure4-9 shows a high-side battery current sensor REF DD circuit. The 10Ω resistor is sized to minimize power losses. The battery current (IDD) through the 10Ω RG resistor causes its top terminal to be more negative than the bottom terminal. This keeps the Common VREF R1 R2 R2 R1 VOUT Mode input voltage of the op amp below V , which is DD within its allowed range. The output of the op amp will also be below V , which is within its Maximum Output DD V Voltage Swing specification. 2 ½ MCP6402 ½ MCP6402 IDD To load V1 1.8V to 10Ω VDD V V = (V –V )⎛1+R----1--+-2---R----1-⎞ +V 6.0V OUT OUT 1 2 ⎝ R R ⎠ REF MCP6401 2 G 100kΩ FIGURE 4-10: Two Op Amp Instrumentation Amplifier. 1MΩ V –V DD OUT I = ------------------------------------------ DD (10 V/V)⋅(10Ω) FIGURE 4-9: Supply Current Sensing. DS22229D-page 20 © 2009-2011 Microchip Technology Inc.

MCP6401/1R/1U/2/4/6/7/9 5.0 DESIGN AIDS 5.4 Analog Demonstration and Evaluation Boards Microchip provides the basic design tools needed for the MCP6401/1R/1U/2/4/6/7/9 family of op amps. Microchip offers a broad spectrum of Analog Demonstration and Evaluation Boards that are 5.1 SPICE Macro Model designed to help you achieve faster time to market. For a complete listing of these boards and their The latest SPICE macro model for the corresponding user’s guides and technical information, MCP6401/1R/1U/2/4/6/7/9 op amp is available on the visit www.microchip.com/analogtools, the Microchip Microchip web site at www.microchip.com. The model web site. was written and tested in official Orcad (Cadence) Some boards that are especially useful are: owned PSPICE. For other simulators, translation may be required. • MCP6XXX Amplifier Evaluation Board 1 The model covers a wide aspect of the op amp's • MCP6XXX Amplifier Evaluation Board 2 electrical specifications. Not only does the model cover • MCP6XXX Amplifier Evaluation Board 3 voltage, current, and resistance of the op amp, but it • MCP6XXX Amplifier Evaluation Board 4 also covers the temperature and noise effects on the • Active Filter Demo Board Kit behavior of the op amp. The model has not been • 5/6-Pin SOT-23 Evaluation Board, P/N VSUPEV2 verified outside of the specification range listed in the • 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board, op amp data sheet. The model behaviors under these P/N SOIC8EV conditions cannot be guaranteed to match the actual op amp performance. • 14-Pin SOIC/TSSOP/DIP Evaluation Board, P/N SOIC14EV Moreover, the model is intended to be an initial design tool. Bench testing is a very important part of any 5.5 Application Notes design and cannot be replaced with simulations. Also, simulation results using this macro model need to be The following Microchip Analog Design Note and validated by comparing them to the data sheet Application Notes are available on the Microchip web specifications and characteristic curves. site at www.microchip.com/appnotes and are recommended as supplemental reference resources. 5.2 FilterLab® Software • ADN003: “Select the Right Operational Amplifier Microchip’s FilterLab® software is an innovative for your Filtering Circuits”, DS21821 software tool that simplifies analog active filter (using • AN722: “Operational Amplifier Topologies and DC op amps) design. Available at no cost from the Specifications”, DS00722 Microchip web site at www.microchip.com/filterlab, the • AN723: “Operational Amplifier AC Specifications FilterLab design tool provides full schematic diagrams and Applications”, DS00723 of the filter circuit with component values. It also • AN884: “Driving Capacitive Loads With Op outputs the filter circuit in SPICE format, which can be Amps”, DS00884 used with the macro model to simulate actual filter • AN990: “Analog Sensor Conditioning Circuits– performance. An Overview”, DS00990 5.3 Microchip Advanced Part Selector • AN1177: “Op Amp Precision Design: DC Errors”, DS01177 (MAPS) • AN1228: “Op Amp Precision Design: Random MAPS is a software tool that helps semiconductor Noise”, DS01228 professionals efficiently identify Microchip devices that • AN1297: “Microchip’s Op Amp SPICE Macro fit a particular design requirement. Available at no cost Models”, DS01297 from the Microchip website at • AN1332: “Current Sensing Circuit Concepts and www.microchip.com/maps, the MAPS is an overall Fundamentals”, DS01332 selection tool for Microchip’s product portfolio that includes Analog, Memory, MCUs and DSCs. Using this These application notes and others are listed in the tool, you can define a filter to sort features for a design guide: parametric search of devices and export side-by-side • “Signal Chain Design Guide”, DS21825 technical comparison reports. Helpful links are also provided for Datasheets, Purchase, and Sampling of Microchip parts. © 2009-2011 Microchip Technology Inc. DS22229D-page 21

MCP6401/1R/1U/2/4/6/7/9 6.0 PACKAGING INFORMATION 6.1 Package Marking Information 5-Lead SC70 (MCP6401 only) Example: BL25 5-Lead SOT-23 Part Number Code (MCP6401/1R/1U, MCP6406) Example: MCP6401T-E/OT NLNN MCP6401T-H/OT U8NN MCP6401RT-E/OT NMNN MCP6401RT-H/OT U9NN NL25 MCP6401UT-E/OT NPNN MCP6401UT-H/OT V8NN MCP6406T-E/OT ZXNN MCP6406T-H/OT ZYNN 8-Lead TDFN (2x3) (MCP6402 only) Example: AAW Part Number Code 129 MCP6402T-E/MNY AAW 25 8-Lead SOIC (150 mil) (MCP6401, MCP6402, MCP6407) Example: MCP6402E SN^e3^1129 NNN 256 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. DS22229D-page 22 © 2009-2011 Microchip Technology Inc.

MCP6401/1R/1U/2/4/6/7/9 Package Marking Information (Continued) 14-Lead SOIC (150 mil) (MCP6404, MCP6409) Example: MCP6404 H/SLe^^3 1129256 and 14-Lead TSSOP (MCP6404 only) Example: XXXXXXXX 6404E/ST 1129 YYWW 256 NNN Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2009-2011 Microchip Technology Inc. DS22229D-page 23

MCP6401/1R/1U/2/4/6/7/9 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:10)(cid:8)(cid:17)(cid:18)(cid:12)(cid:10)(cid:13)(cid:19)(cid:5)(cid:8)(cid:20)(cid:21)(cid:6)(cid:19)(cid:11)(cid:13)(cid:11)(cid:12)(cid:22)(cid:21)(cid:8)(cid:23)(cid:4)(cid:20)(cid:24)(cid:8)(cid:25)(cid:15)(cid:26)(cid:27)(cid:28)(cid:29) (cid:30)(cid:22)(cid:12)(cid:5)(cid:31) .(cid:10)(cid:9)(cid:2)#(cid:11)(cid:14)(cid:2)(cid:31)(cid:10) #(cid:2)(cid:8)$(cid:9)(cid:9)(cid:14)(cid:15)#(cid:2)(cid:12)(cid:28)(cid:8)/(cid:28)(cid:17)(cid:14)(cid:2)!(cid:9)(cid:28)-(cid:7)(cid:15)(cid:17) 0(cid:2)(cid:12)(cid:16)(cid:14)(cid:28) (cid:14)(cid:2) (cid:14)(cid:14)(cid:2)#(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)1(cid:28)(cid:8)/(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)#(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)#(cid:14)!(cid:2)(cid:28)#(cid:2) (cid:11)##(cid:12)+22---(cid:20)(cid:31)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)(cid:31)2(cid:12)(cid:28)(cid:8)/(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D b 3 2 1 E1 E 4 5 e e A A2 c A1 L 3(cid:15)(cid:7)# (cid:6)(cid:19)44(cid:19)(cid:6)"(cid:13)"(cid:26)(cid:22) (cid:21)(cid:7)(cid:31)(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:2)4(cid:7)(cid:31)(cid:7)# (cid:6)(cid:19)5 56(cid:6) (cid:6)(cid:25)7 5$(cid:31)8(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)1(cid:7)(cid:15) 5 ( 1(cid:7)#(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)9((cid:2))(cid:22)* 6,(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2):(cid:14)(cid:7)(cid:17)(cid:11)# (cid:25) (cid:4)(cid:20);(cid:4) < (cid:30)(cid:20)(cid:30)(cid:4) (cid:6)(cid:10)(cid:16)!(cid:14)!(cid:2)1(cid:28)(cid:8)/(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)/(cid:15)(cid:14) (cid:25)(cid:3) (cid:4)(cid:20);(cid:4) < (cid:30)(cid:20)(cid:4)(cid:4) (cid:22)#(cid:28)(cid:15)!(cid:10)%% (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:4) < (cid:4)(cid:20)(cid:30)(cid:4) 6,(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)=(cid:7)!#(cid:11) " (cid:30)(cid:20);(cid:4) (cid:3)(cid:20)(cid:30)(cid:4) (cid:3)(cid:20)(cid:23)(cid:4) (cid:6)(cid:10)(cid:16)!(cid:14)!(cid:2)1(cid:28)(cid:8)/(cid:28)(cid:17)(cid:14)(cid:2)=(cid:7)!#(cid:11) "(cid:30) (cid:30)(cid:20)(cid:30)( (cid:30)(cid:20)(cid:3)( (cid:30)(cid:20)(cid:29)( 6,(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)4(cid:14)(cid:15)(cid:17)#(cid:11) (cid:21) (cid:30)(cid:20);(cid:4) (cid:3)(cid:20)(cid:4)(cid:4) (cid:3)(cid:20)(cid:3)( .(cid:10)(cid:10)#(cid:2)4(cid:14)(cid:15)(cid:17)#(cid:11) 4 (cid:4)(cid:20)(cid:30)(cid:4) (cid:4)(cid:20)(cid:3)(cid:4) (cid:4)(cid:20)(cid:23)9 4(cid:14)(cid:28)!(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)/(cid:15)(cid:14) (cid:8) (cid:4)(cid:20)(cid:4); < (cid:4)(cid:20)(cid:3)9 4(cid:14)(cid:28)!(cid:2)=(cid:7)!#(cid:11) 8 (cid:4)(cid:20)(cid:30)( < (cid:4)(cid:20)(cid:23)(cid:4) (cid:30)(cid:22)(cid:12)(cid:5)(cid:11)(cid:31) (cid:30)(cid:20) (cid:21)(cid:7)(cid:31)(cid:14)(cid:15) (cid:7)(cid:10)(cid:15) (cid:2)(cid:21)(cid:2)(cid:28)(cid:15)!(cid:2)"(cid:30)(cid:2)!(cid:10)(cid:2)(cid:15)(cid:10)#(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)$!(cid:14)(cid:2)(cid:31)(cid:10)(cid:16)!(cid:2)%(cid:16)(cid:28) (cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)#(cid:9)$ (cid:7)(cid:10)(cid:15) (cid:20)(cid:2)(cid:6)(cid:10)(cid:16)!(cid:2)%(cid:16)(cid:28) (cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)#(cid:9)$ (cid:7)(cid:10)(cid:15) (cid:2) (cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)#(cid:2)(cid:14)&(cid:8)(cid:14)(cid:14)!(cid:2)(cid:4)(cid:20)(cid:30)(cid:3)(cid:5)(cid:2)(cid:31)(cid:31)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2) (cid:7)!(cid:14)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7)(cid:31)(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)!(cid:2)#(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6)"(cid:2)’(cid:30)(cid:23)(cid:20)((cid:6)(cid:20) )(cid:22)*+ )(cid:28) (cid:7)(cid:8)(cid:2)(cid:21)(cid:7)(cid:31)(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)#(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)&(cid:28)(cid:8)#(cid:2),(cid:28)(cid:16)$(cid:14)(cid:2) (cid:11)(cid:10)-(cid:15)(cid:2)-(cid:7)#(cid:11)(cid:10)$#(cid:2)#(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14) (cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)-(cid:7)(cid:15)(cid:17)*(cid:4)(cid:23)(cid:27)(cid:4)9(cid:30)) DS22229D-page 24 © 2009-2011 Microchip Technology Inc.

MCP6401/1R/1U/2/4/6/7/9 (cid:30)(cid:22)(cid:12)(cid:5)(cid:31) .(cid:10)(cid:9)(cid:2)#(cid:11)(cid:14)(cid:2)(cid:31)(cid:10) #(cid:2)(cid:8)$(cid:9)(cid:9)(cid:14)(cid:15)#(cid:2)(cid:12)(cid:28)(cid:8)/(cid:28)(cid:17)(cid:14)(cid:2)!(cid:9)(cid:28)-(cid:7)(cid:15)(cid:17) 0(cid:2)(cid:12)(cid:16)(cid:14)(cid:28) (cid:14)(cid:2) (cid:14)(cid:14)(cid:2)#(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)1(cid:28)(cid:8)/(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)#(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)#(cid:14)!(cid:2)(cid:28)#(cid:2) (cid:11)##(cid:12)+22---(cid:20)(cid:31)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)(cid:31)2(cid:12)(cid:28)(cid:8)/(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) © 2009-2011 Microchip Technology Inc. DS22229D-page 25

MCP6401/1R/1U/2/4/6/7/9 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:10)(cid:8)(cid:17)(cid:18)(cid:12)(cid:10)(cid:13)(cid:19)(cid:5)(cid:8)(cid:20)(cid:21)(cid:6)(cid:19)(cid:11)(cid:13)(cid:11)(cid:12)(cid:22)(cid:21)(cid:8)(cid:23)(cid:17)(cid:20)(cid:24)(cid:8)(cid:25)(cid:15)(cid:17)(cid:20)(cid:3) !(cid:29) (cid:30)(cid:22)(cid:12)(cid:5)(cid:31) .(cid:10)(cid:9)(cid:2)#(cid:11)(cid:14)(cid:2)(cid:31)(cid:10) #(cid:2)(cid:8)$(cid:9)(cid:9)(cid:14)(cid:15)#(cid:2)(cid:12)(cid:28)(cid:8)/(cid:28)(cid:17)(cid:14)(cid:2)!(cid:9)(cid:28)-(cid:7)(cid:15)(cid:17) 0(cid:2)(cid:12)(cid:16)(cid:14)(cid:28) (cid:14)(cid:2) (cid:14)(cid:14)(cid:2)#(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)1(cid:28)(cid:8)/(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)#(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)#(cid:14)!(cid:2)(cid:28)#(cid:2) (cid:11)##(cid:12)+22---(cid:20)(cid:31)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)(cid:31)2(cid:12)(cid:28)(cid:8)/(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) b N E E1 1 2 3 e e1 D A A2 c φ A1 L L1 3(cid:15)(cid:7)# (cid:6)(cid:19)44(cid:19)(cid:6)"(cid:13)"(cid:26)(cid:22) (cid:21)(cid:7)(cid:31)(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:2)4(cid:7)(cid:31)(cid:7)# (cid:6)(cid:19)5 56(cid:6) (cid:6)(cid:25)7 5$(cid:31)8(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)1(cid:7)(cid:15) 5 ( 4(cid:14)(cid:28)!(cid:2)1(cid:7)#(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)(cid:24)((cid:2))(cid:22)* 6$# (cid:7)!(cid:14)(cid:2)4(cid:14)(cid:28)!(cid:2)1(cid:7)#(cid:8)(cid:11) (cid:14)(cid:30) (cid:30)(cid:20)(cid:24)(cid:4)(cid:2))(cid:22)* 6,(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2):(cid:14)(cid:7)(cid:17)(cid:11)# (cid:25) (cid:4)(cid:20)(cid:24)(cid:4) < (cid:30)(cid:20)(cid:23)( (cid:6)(cid:10)(cid:16)!(cid:14)!(cid:2)1(cid:28)(cid:8)/(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)/(cid:15)(cid:14) (cid:25)(cid:3) (cid:4)(cid:20);(cid:24) < (cid:30)(cid:20)(cid:29)(cid:4) (cid:22)#(cid:28)(cid:15)!(cid:10)%% (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:4) < (cid:4)(cid:20)(cid:30)( 6,(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)=(cid:7)!#(cid:11) " (cid:3)(cid:20)(cid:3)(cid:4) < (cid:29)(cid:20)(cid:3)(cid:4) (cid:6)(cid:10)(cid:16)!(cid:14)!(cid:2)1(cid:28)(cid:8)/(cid:28)(cid:17)(cid:14)(cid:2)=(cid:7)!#(cid:11) "(cid:30) (cid:30)(cid:20)(cid:29)(cid:4) < (cid:30)(cid:20);(cid:4) 6,(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)4(cid:14)(cid:15)(cid:17)#(cid:11) (cid:21) (cid:3)(cid:20)(cid:5)(cid:4) < (cid:29)(cid:20)(cid:30)(cid:4) .(cid:10)(cid:10)#(cid:2)4(cid:14)(cid:15)(cid:17)#(cid:11) 4 (cid:4)(cid:20)(cid:30)(cid:4) < (cid:4)(cid:20)9(cid:4) .(cid:10)(cid:10)#(cid:12)(cid:9)(cid:7)(cid:15)# 4(cid:30) (cid:4)(cid:20)(cid:29)( < (cid:4)(cid:20);(cid:4) .(cid:10)(cid:10)#(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)> < (cid:29)(cid:4)> 4(cid:14)(cid:28)!(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)/(cid:15)(cid:14) (cid:8) (cid:4)(cid:20)(cid:4); < (cid:4)(cid:20)(cid:3)9 4(cid:14)(cid:28)!(cid:2)=(cid:7)!#(cid:11) 8 (cid:4)(cid:20)(cid:3)(cid:4) < (cid:4)(cid:20)((cid:30) (cid:30)(cid:22)(cid:12)(cid:5)(cid:11)(cid:31) (cid:30)(cid:20) (cid:21)(cid:7)(cid:31)(cid:14)(cid:15) (cid:7)(cid:10)(cid:15) (cid:2)(cid:21)(cid:2)(cid:28)(cid:15)!(cid:2)"(cid:30)(cid:2)!(cid:10)(cid:2)(cid:15)(cid:10)#(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)$!(cid:14)(cid:2)(cid:31)(cid:10)(cid:16)!(cid:2)%(cid:16)(cid:28) (cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)#(cid:9)$ (cid:7)(cid:10)(cid:15) (cid:20)(cid:2)(cid:6)(cid:10)(cid:16)!(cid:2)%(cid:16)(cid:28) (cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)#(cid:9)$ (cid:7)(cid:10)(cid:15) (cid:2) (cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)#(cid:2)(cid:14)&(cid:8)(cid:14)(cid:14)!(cid:2)(cid:4)(cid:20)(cid:30)(cid:3)(cid:5)(cid:2)(cid:31)(cid:31)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2) (cid:7)!(cid:14)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7)(cid:31)(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)!(cid:2)#(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6)"(cid:2)’(cid:30)(cid:23)(cid:20)((cid:6)(cid:20) )(cid:22)*+ )(cid:28) (cid:7)(cid:8)(cid:2)(cid:21)(cid:7)(cid:31)(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)#(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)&(cid:28)(cid:8)#(cid:2),(cid:28)(cid:16)$(cid:14)(cid:2) (cid:11)(cid:10)-(cid:15)(cid:2)-(cid:7)#(cid:11)(cid:10)$#(cid:2)#(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14) (cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)-(cid:7)(cid:15)(cid:17)*(cid:4)(cid:23)(cid:27)(cid:4)(cid:24)(cid:30)) DS22229D-page 26 © 2009-2011 Microchip Technology Inc.

MCP6401/1R/1U/2/4/6/7/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2009-2011 Microchip Technology Inc. DS22229D-page 27

MCP6401/1R/1U/2/4/6/7/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22229D-page 28 © 2009-2011 Microchip Technology Inc.

MCP6401/1R/1U/2/4/6/7/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2009-2011 Microchip Technology Inc. DS22229D-page 29

MCP6401/1R/1U/2/4/6/7/9 "(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:10)(cid:8)(cid:17)(cid:18)(cid:12)(cid:10)(cid:13)(cid:19)(cid:5)(cid:8)(cid:23)(cid:15)(cid:30)(cid:24)(cid:8)#(cid:8)(cid:30)(cid:6)(cid:21)(cid:21)(cid:22)$%(cid:8)!&’(cid:28)(cid:8)(cid:16)(cid:16)(cid:8)((cid:22)(cid:7))(cid:8)(cid:25)(cid:15)(cid:17)*(cid:26)(cid:29) (cid:30)(cid:22)(cid:12)(cid:5)(cid:31) .(cid:10)(cid:9)(cid:2)#(cid:11)(cid:14)(cid:2)(cid:31)(cid:10) #(cid:2)(cid:8)$(cid:9)(cid:9)(cid:14)(cid:15)#(cid:2)(cid:12)(cid:28)(cid:8)/(cid:28)(cid:17)(cid:14)(cid:2)!(cid:9)(cid:28)-(cid:7)(cid:15)(cid:17) 0(cid:2)(cid:12)(cid:16)(cid:14)(cid:28) (cid:14)(cid:2) (cid:14)(cid:14)(cid:2)#(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)1(cid:28)(cid:8)/(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)#(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)#(cid:14)!(cid:2)(cid:28)#(cid:2) (cid:11)##(cid:12)+22---(cid:20)(cid:31)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)(cid:31)2(cid:12)(cid:28)(cid:8)/(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) DS22229D-page 30 © 2009-2011 Microchip Technology Inc.

MCP6401/1R/1U/2/4/6/7/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2009-2011 Microchip Technology Inc. DS22229D-page 31

MCP6401/1R/1U/2/4/6/7/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22229D-page 32 © 2009-2011 Microchip Technology Inc.

MCP6401/1R/1U/2/4/6/7/9 "(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)+(cid:18)(cid:6)(cid:10)(cid:8),(cid:10)(cid:6)(cid:12)%(cid:8)(cid:30)(cid:22)(cid:8)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:14)-(cid:6).(cid:5)(cid:8)(cid:23)/(cid:30)(cid:24)(cid:8)#(cid:8) 0!0(cid:28)&(cid:27)(cid:2)(cid:8)(cid:16)(cid:16)(cid:8)((cid:22)(cid:7))(cid:8)(cid:25)(cid:20)+,(cid:30)(cid:29) (cid:30)(cid:22)(cid:12)(cid:5)(cid:31) .(cid:10)(cid:9)(cid:2)#(cid:11)(cid:14)(cid:2)(cid:31)(cid:10) #(cid:2)(cid:8)$(cid:9)(cid:9)(cid:14)(cid:15)#(cid:2)(cid:12)(cid:28)(cid:8)/(cid:28)(cid:17)(cid:14)(cid:2)!(cid:9)(cid:28)-(cid:7)(cid:15)(cid:17) 0(cid:2)(cid:12)(cid:16)(cid:14)(cid:28) (cid:14)(cid:2) (cid:14)(cid:14)(cid:2)#(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)1(cid:28)(cid:8)/(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)#(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)#(cid:14)!(cid:2)(cid:28)#(cid:2) (cid:11)##(cid:12)+22---(cid:20)(cid:31)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)(cid:31)2(cid:12)(cid:28)(cid:8)/(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) © 2009-2011 Microchip Technology Inc. DS22229D-page 33

MCP6401/1R/1U/2/4/6/7/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22229D-page 34 © 2009-2011 Microchip Technology Inc.

MCP6401/1R/1U/2/4/6/7/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2009-2011 Microchip Technology Inc. DS22229D-page 35

MCP6401/1R/1U/2/4/6/7/9 (cid:30)(cid:22)(cid:12)(cid:5)(cid:31) .(cid:10)(cid:9)(cid:2)#(cid:11)(cid:14)(cid:2)(cid:31)(cid:10) #(cid:2)(cid:8)$(cid:9)(cid:9)(cid:14)(cid:15)#(cid:2)(cid:12)(cid:28)(cid:8)/(cid:28)(cid:17)(cid:14)(cid:2)!(cid:9)(cid:28)-(cid:7)(cid:15)(cid:17) 0(cid:2)(cid:12)(cid:16)(cid:14)(cid:28) (cid:14)(cid:2) (cid:14)(cid:14)(cid:2)#(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)1(cid:28)(cid:8)/(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)#(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)#(cid:14)!(cid:2)(cid:28)#(cid:2) (cid:11)##(cid:12)+22---(cid:20)(cid:31)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)(cid:31)2(cid:12)(cid:28)(cid:8)/(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) DS22229D-page 36 © 2009-2011 Microchip Technology Inc.

MCP6401/1R/1U/2/4/6/7/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2009-2011 Microchip Technology Inc. DS22229D-page 37

MCP6401/1R/1U/2/4/6/7/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22229D-page 38 © 2009-2011 Microchip Technology Inc.

MCP6401/1R/1U/2/4/6/7/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2009-2011 Microchip Technology Inc. DS22229D-page 39

MCP6401/1R/1U/2/4/6/7/9 APPENDIX A: REVISION HISTORY Revision B (June 2010) The following is the list of modifications: Revision D (September 2011) 1. Added the MCP6402 and MCP6404 package The following is the list of modifications: information. 2. Updated the ESD protection value on all pins in 1. Section1.0 “Electrical Characteristics”: Section1.1 “Absolute Maximum Ratings †”. Updated minor typographical corrections in both “DC Electrical Specifications” tables to 3. Added Figure2-36. show the correct unit for R (kΩ instead of kW). 4. Updated Table3-1. L 5. Updated Section4.1.2 “Input Voltage Limits”. Revision C (August 2011) 6. Added Section4.1.3 “Input Current Limits”. 7. Added Section4.5 “Unused Op Amps”. The following is the list of modifications: 8. Updated Section5.4 “Analog Demonstration 1. Added new MCP6406, MCP6407 and and Evaluation Boards”. MCP6409 devices and the related information 9. Updated the package markings information and throughout the document. drawings. 2. Created two package type drawings based on the temperature characterization (see E Temp 10. Updated the Product Identification System page. Package Types and H Temp Package Types). 3. Added MCP6406/7/9 specification tables in Revision A (December 2009) Section1.3 “MCP6406/7/9 Electrical Specifi- cations”. Original data sheet for the MCP6401/1R/1U/2/4/6/7/9 4. Updated characterization graphics in family of devices. Section2.0 “Typical Performance Curves”. 5. Updated Table3-1 in Section3.0 “Pin Descriptions” to show all the devices. 6. Updated markings examples in Section6.1 “Package Marking Information”. 7. Updated the package markings information to show all drawings available for each type of package. 8. Updated the Product Identification System page with the new devices and temperature specifications. DS22229D-page 40 © 2009-2011 Microchip Technology Inc.

MCP6401/1R/1U/2/4/6/7/9 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. -X /XX Examples: a) MCP6401T-E/LT: Tape and Reel, Device Temperature Package Extended Temperature, Range 5LD SC70 pkg b) MCP6401T-E/OT: Tape and Reel, Extended Temperature, Device: MCP6401T: Single Op Amp (Tape and Reel) 5LD SOT-23 pkg (SC70, SOT-23) c) MCP6401RT-E/OT: Tape and Reel, MCP6401RT: Single Op Amp (Tape and Reel) 5LD SOT-23 pkg (SOT-23) d) MCP6401UT-E/OT: Tape and Reel, MCP6401UT: Single Op Amp (Tape and Reel) Extended Temperature, (SOT-23) 5LD SOT-23 pkg MCP6402: Dual Op Amp MCP6402T: Dual Op Amp (Tape and Reel) e) MCP6402-E/SN: Extended Temperature, (SOIC, 2x3 TDFN) 8LD SOIC pkg MCP6404: Quad Op Amp f) MCP6402T-E/SN: Tape and Reel, MCP6404T: Quad Op Amp (Tape and Reel) Extended Temperature, (SOIC, TSSOP) 8LD SOIC pkg MCP6406T: Single Op Amp (Tape and Reel) g) MCP6402T-E/MNY: Tape and Reel, (SOT-23) Extended Temperature, MCP6407: Dual Op Amp 8LD 2x3 TDFN pkg MCP6407T: Dual Op Amp (Tape and Reel) (SOIC) h) MCP6404-E/SL: Extended Temperature, MCP6409: Quad Op Amp 14LD SOIC pkg MCP6409T: Quad Op Amp (Tape and Reel) i) MCP6404T-E/SL: Tape and Reel, (SOIC) Extended Temperature, 14LD SOIC pkg j) MCP6404-E/ST: Extended Temperature, Temperature Range: E = -40°C to +125°C (Extended Temperature) 14LD TSSOP pkg H = -40°C to +150°C (High Temperature) k) MCP6404T-E/ST: Tape and Reel, Extended Temperature, 14LD TSSOP pkg. Package: LT = Plastic Package (SC70), 5-lead OT = Plastic Small Outline Transistor (SOT-23), 5-lead a) MCP6401T-H/OT: Tape and Reel, SN = Plastic SOIC, (3.90 mm body), 8-lead High Temperature, MNY* = Plastic Dual Flat, No Lead, (2x3 TDFN), 8-lead 5LD SOT-23 pkg SL = Plastic SOIC (3.90 mm body), 14-lead ST = Plastic TSSOP (4.4mm body), 14-lead b) MCP6402-H/SN: High Temperature, 8LD SOIC pkg * Y = Nickel palladium gold manufacturing designator. c) MCP6402T-H/SN: Tape and Reel, Only available on the TDFN package. High Temperature, 8LD SOIC pkg d) MCP6404-H/SL: High Temperature, 14LD SOIC pkg e) MCP6404T-H/SL: Tape and Reel, High Temperature, 14LD SOIC pkg f) MCP6406T-H/OT: Tape and Reel, High Temperature, 5LD SOT-23 pkg g) MCP6407-H/SN: High Temperature, 8LD SOIC pkg h) MCP6407T-H/SN: Tape and Reel, High Temperature, 8LD SOIC pkg i) MCP6409-H/SL: High Temperature, 14LD SOIC pkg j) MCP6409T-H/SL: Tape and Reel, High Temperature, 14LD SOIC pkg © 2009-2011 Microchip Technology Inc. DS22229D-page 41

MCP6401/1R/1U/2/4/6/7/9 NOTES: DS22229D-page 42 © 2009-2011 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. PIC32 logo, rfPIC and UNI/O are registered trademarks of MICROCHIP MAKES NO REPRESENTATIONS OR Microchip Technology Incorporated in the U.S.A. and other WARRANTIES OF ANY KIND WHETHER EXPRESS OR countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MXDEV, MXLAB, SEEVAL and The Embedded Control QUALITY, PERFORMANCE, MERCHANTABILITY OR Solutions Company are registered trademarks of Microchip FITNESS FOR PURPOSE. Microchip disclaims all liability Technology Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, chipKIT, devices in life support and/or safety applications is entirely at chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, the buyer’s risk, and the buyer agrees to defend, indemnify and dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, hold harmless Microchip from any and all damages, claims, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, suits, or expenses resulting from such use. No licenses are Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, conveyed, implicitly or otherwise, under any Microchip MPLINK, mTouch, Omniscient Code Generation, PICC, intellectual property rights. PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2009-2011, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-61341-616-7 Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2009-2011 Microchip Technology Inc. DS22229D-page 43

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