MCP6291/2/3/4/5 1.0 mA, 10 MHz Rail-to-Rail Op Amp Features Description • Gain Bandwidth Product: 10MHz (typ.) The Microchip Technology Inc. MCP6291/2/3/4/5 family (cid:127) Supply Current: I = 1.0mA of operational amplifiers (op amps) provide wide Q bandwidth for the current. This family has a 10MHz (cid:127) Supply Voltage: 2.4V to 5.5V Gain Bandwidth Product (GBWP) and a 65° phase (cid:127) Rail-to-Rail Input/Output margin. This family also operates from a single supply (cid:127) Extended Temperature Range: -40°C to +125°C voltage as low as 2.4V, while drawing 1mA (typ.) (cid:127) Available in Single, Dual and Quad Packages quiescent current. In addition, the MCP6291/2/3/4/5 (cid:127) Single with Chip Select (CS) (MCP6293) supports rail-to-rail input and output swing, with a (cid:127) Dual with Chip Select (CS) (MCP6295) common mode input voltage range of VDD+300mV to V –300mV. This family of operational amplifiers is SS Applications designed with Microchip’s advanced CMOS process. The MCP6295 has a Chip Select input (CS) for dual op (cid:127) Automotive amps in an 8-pin package. This device is manufactured (cid:127) Portable Equipment by cascading the two op amps, with the output of (cid:127) Photodiode Amplifier opamp A being connected to the non-inverting input of (cid:127) Analog Filters opamp B. The CS input puts the device in a Low-power (cid:127) Notebooks and PDAs mode. (cid:127) Battery-Powered Systems The MCP6291/2/3/4/5 family operates over the Extended Temperature Range of -40°C to +125°C. It Available Tools also has a power supply range of 2.4V to 5.5V. (cid:127) SPICE Macro Model (at www.microchip.com) (cid:127) FilterLab ® Software (at www.microchip.com) Package Types MCP6291 MCP6291 MCP6291R MCP6292 PDIP, SOIC, MSOP SOT-23-5 SOT-23-5 PDIP, SOIC, MSOP VVNIINNC+_ 123 +- 876 VNVDOCDUT VVVOINUS+ST 123 + - 45 VVDIND– VVVOIDNU+DT 123 + - 45 VVSINS– VVVOIUINNTAAA+_ 123 - ++ - 876 VVVODINDUBT_B VSS 4 5 NC VSS 4 5 VINB+ MCP6293 MCP6293 MCP6294 MCP6295 PDIP, SOIC, MSOP SOT-23-6 PDIP, SOIC, TSSOP PDIP, SOIC, MSOP VVVNIINSNC+S_ 1234 +- 8765 CVVNDOCSDUT VVVOINSU+ST 123 + - 465 CVVDISND– VVVOIVINUNDATAA+D_ 1234 - + + - 11111432VVVVSOIINNSUDDT_+D VOUTA/VVVIIIVNNNABSA++S_ 1234 - + + - 8765 VVVCODISNDUBT_B VINB+ 5 10VINC+ VINB_ 6 -+ +- 9 VINC_ VOUTB 7 8 VOUTC  2004 Microchip Technology Inc. DS21812D-page 1

MCP6291/2/3/4/5 1.0 ELECTRICAL † Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is CHARACTERISTICS a stress rating only and functional operation of the device at those or any other conditions above those indicated in the Absolute Maximum Ratings † operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods V – V ........................................................................7.0V DD SS may affect device reliability. All Inputs and Outputs ...................V –0.3V to V +0.3V SS DD Difference Input Voltage ......................................|V – V | DD SS Output Short Circuit Current .................................Continuous Current at Input Pins ....................................................±2mA Current at Output and Supply Pins ............................±30mA Storage Temperature.....................................-65°C to +150°C Junction Temperature (T ) ..........................................+150°C J ESD Protection On All Pins (HBM/MM)................≥ 4kV/400V DC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, T = +25°C, V = +2.4V to +5.5V, V = GND, V = V /2, A DD SS CM DD R = 10kΩ to V /2 and V ≈V /2. L DD OUT DD Parameters Sym Min Typ Max Units Conditions Input Offset Input Offset Voltage V -3.0 — +3.0 mV V = V (Note1) OS CM SS Input Offset Voltage V -5.0 — +5.0 mV T = -40°C to +125°C, OS A (Extended Temperature) V = V (Note1) CM SS Input Offset Temperature Drift ∆V /∆T — ±1.7 — µV/°C T = -40°C to +125°C, OS A A V = V (Note1) CM SS Power Supply Rejection Ratio PSRR 70 90 — dB V = V (Note1) CM SS Input Bias, Input Offset Current and Impedance Input Bias Current I — ±1.0 — pA Note2 B At Temperature I — 50 200 pA T = +85°C (Note2) B A At Temperature I — 2 5 nA T = +125°C (Note2) B A Input Offset Current I — ±1.0 — pA Note3 OS Common Mode Input Impedance Z — 1013||6 — Ω||pF Note3 CM Differential Input Impedance Z — 1013||3 — Ω||pF Note3 DIFF Common Mode (Note4) Common Mode Input Range V V − 0.3 — V + 0.3 V CMR SS DD Common Mode Rejection Ratio CMRR 70 85 — dB V = -0.3V to 2.5V, V = 5V CM DD Common Mode Rejection Ratio CMRR 65 80 — dB V = -0.3V to 5.3V, V = 5V CM DD Open-Loop Gain DC Open-Loop Gain (Large Signal) A 90 110 — dB V = 0.2V to V – 0.2V, OL OUT DD V =V (Note1) CM SS Output Maximum Output Voltage Swing V , V V + 15 — V – 15 mV OL OH SS DD Output Short Circuit Current I — ±25 — mA SC Power Supply Supply Voltage V 2.4 — 5.5 V T = -40°C to +125°C DD A Quiescent Current per Amplifier I 0.7 1.0 1.3 mA I = 0 Q O Note 1: The MCP6295’s V for op amp B (pins V /V + and V –) is V + 100mV. CM OUTA INB INB SS 2: The current at the MCP6295’s V – pin is specified by I only. INB B 3: This specification does not apply to the MCP6295’s V /V + pin. OUTA INB 4: The MCP6295’s V – pin (op amp B) has a common mode range (V ) of V + 100mV to V – 100mV. INB CMR SS DD The MCP6295’s V /V + pin (op amp B) has a voltage range specified by V and V . OUTA INB OH OL DS21812D-page 2  2004 Microchip Technology Inc.

MCP6291/2/3/4/5 AC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, T = +25°C, V = +2.4V to +5.5V, V = GND, V = V /2, A DD SS CM DD V ≈V /2, R = 10kΩ to V /2 and C = 60pF. OUT DD L DD L Parameters Sym Min Typ Max Units Conditions AC Response Gain Bandwidth Product GBWP — 10.0 — MHz Phase Margin at Unity-Gain PM — 65 — ° Slew Rate SR — 7 — V/µs Noise Input Noise Voltage E — 3.5 — µV f = 0.1Hz to 10Hz ni P-P Input Noise Voltage Density e — 8.7 — nV/√Hz f = 10kHz ni Input Noise Current Density i — 3 — fA/√Hz f = 1kHz ni TEMPERATURE SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, V = +2.4V to +5.5V and V = GND. DD SS Parameters Sym Min Typ Max Units Conditions Temperature Ranges Operating Temperature Range T -40 — +125 °C Note A Storage Temperature Range T -65 — +150 °C A Thermal Package Resistances Thermal Resistance, 5L-SOT-23 θ — 256 — °C/W JA Thermal Resistance, 6L-SOT-23 θ — 230 — °C/W JA Thermal Resistance, 8L-PDIP θ — 85 — °C/W JA Thermal Resistance, 8L-SOIC θ — 163 — °C/W JA Thermal Resistance, 8L-MSOP θ — 206 — °C/W JA Thermal Resistance, 14L-PDIP θ — 70 — °C/W JA Thermal Resistance, 14L-SOIC θ — 120 — °C/W JA Thermal Resistance, 14L-TSSOP θ — 100 — °C/W JA Note: The Junction Temperature (T ) must not exceed the Absolute Maximum specification of +150°C. J  2004 Microchip Technology Inc. DS21812D-page 3

MCP6291/2/3/4/5 MCP6293/MCP6295 CHIP SELECT (CS) SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, T = +25°C, V = +2.4V to +5.5V, V = GND, A DD SS V = V /2, V ≈V /2, R = 10kΩ to V /2 and C = 60pF. CM DD OUT DD L DD L Parameters Sym Min Typ Max Units Conditions CS Low Specifications CS Logic Threshold, Low V V — 0.2V V IL SS DD CS Input Current, Low I — 0.01 — µA CS = V CSL SS CS High Specifications CS Logic Threshold, High V 0.8V — V V IH DD DD CS Input Current, High I — 0.7 2 µA CS = V CSH DD GND Current per Amplifier I — -0.7 — µA CS = V SS DD Amplifier Output Leakage — — 0.01 — µA CS = V DD Dynamic Specifications (Note1) CS Low to Valid Amplifier Output, t — 4 10 µs CS Low ≤ 0.2V , G = +1V/V, ON DD Turn-on Time V = V /2, V = 0.9V /2, IN DD OUT DD V = 5.0V DD CS High to Amplifier Output High-Z t — 0.01 — µs CS High ≥ 0.8V , G = +1V/V, OFF DD V = V /2, V = 0.1V /2 IN DD OUT DD Hysteresis V — 0.6 — V V = 5V HYST DD Note 1: The input condition (V ) specified applies to both op amp A and B of the MCP6295. The dynamic specification is tested IN at the output of op amp B (V ). OUTB CS V V IL IH t t OFF ON Hi-Z Hi-Z V OUT -0.7µA (typ.) -0.7µA (typ.) I SS -1.0mA (typ.) 0.7µA (typ.) 0.7µA (typ.) I CS 10nA (typ.) FIGURE 1-1: Timing Diagram for the ChipSelect (CS) pin on the MCP6293 and MCP6295. DS21812D-page 4  2004 Microchip Technology Inc.

MCP6291/2/3/4/5 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, T = +25°C, V = +2.4V to +5.5V, V = GND, V = V /2, V ≈V /2, A DD SS CM DD OUT DD R = 10kΩ to V /2 and C = 60pF. L DD L 12% 25% Occurrences 1178901%%%%% 8V4C0M S= aVmSSples Occurrences 1250%% 8VT4AC 0M= S=-4 aV0mS°SpCl etos +125°C Percentage of 123456%%%%%% Percentage of 150%% 0% 0% 8 4 0 6 2 8 4 0 4 8 2 6 0 4 8 -2. -2. -2. -1. -1. -0. -0. 0. 0. 0. 1. 1. 2. 2. 2. -10 -8 -6 -4 -2 0 2 4 6 8 10 Input Offset Voltage (mV) Input Offset Voltage Drift (µV/°C) FIGURE 2-1: Input Offset Voltage. FIGURE 2-4: Input Offset Voltage Drift. 30% 40% 210 Samples nces 35% 2T1A 0= S8a5m°Cples nces 25% TA = +125°C urre 30% urre 20% Occ 25% Occ 15% of 20% of ge 15% ge 10% nta 10% nta 5% Perce 05%% Perce 0% 0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 2 4 6 8 0 2 4 6 8 0 2 4 6 8 0 0 10 20 30 40 50 60 70 80 90 100 1 1 1 1 1 2 2 2 2 2 3 Input Bias Current (pA) Input Bias Current (pA) FIGURE 2-2: Input Bias Current at FIGURE 2-5: Input Bias Current at TA=+85 °C. TA=+125 °C. 800 V) 345000 VDD = 2.4V µV)770500 VDD = 5.5V ge (µ 300 age (660500 TTAA == + +12855°°CC et Volta 220500 TA = -40°C set Volt455505000 TTAA == +-4205°°CC put Offs 110500 TTTAAA === +++281552°°5CC°C nput Off334050000 n 50 I250 I 200 0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Common Mode Input Voltage (V) Common Mode Input Voltage (V) FIGURE 2-3: Input Offset Voltage vs. FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 2.4V. Common Mode Input Voltage at VDD = 5.5V.  2004 Microchip Technology Inc. DS21812D-page 5

MCP6291/2/3/4/5 TYPICAL PERFORMANCE CURVES (CONTINUED) Note: Unless otherwise indicated, T = +25°C, V = +2.4V to +5.5V, V = GND, V = V /2, V ≈V /2, A DD SS CM DD OUT DD R = 10kΩ to V /2 and C = 60pF. L DD L 700 10,000 µV) 660500 VRCeMp r=e sVeSnStative Part nts VVCDMD == 5V.D5DV nput Offset Voltage ( 223344550505050500000000 VVDDDD == 52..54VV ut Bias, Offset Curre(pA) 1,10100000 InIpnuptu Ot Bffisaest CCuurrrreenntt I 150 p n 100 I 1 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 25 35 45 55 65 75 85 95 105 115 125 Output Voltage (V) Ambient Temperature (°C) FIGURE 2-7: Input Offset Voltage vs. FIGURE 2-10: Input Bias, Input Offset Output Voltage. Currents vs. Ambient Temperature. 110 120 100 110 SRR (dB) 789000 PSRR+ PSRR- CMRR MRR (dB) 19000 CMRR RR, P 5600 RR, C 80 PVSCMR =R VSS M S C 40 P 70 30 60 20 11.E+00 11.E+001 101.E+002 11k.E+03 101.E+0k4 101.0E+05k 11M.E+06 -50 -25 0 25 50 75 100 125 Frequency (Hz) Ambient Temperature (°C) FIGURE 2-8: CMRR, PSRR vs. FIGURE 2-11: CMRR, PSRR vs. Ambient Frequency. Temperature. 55 2.5 ents 45 Input Bias Current nts 2.0 TVAD D= = + 51.255V°C Curr 35 urre 1.5 Input Bias Current as, Offset (pA) 12555 s, Offset C(nA) 01..50 Input Bi -1-55 TVAD D= = + 58.55°VC Input Offset Current Input Bia -00..50 Input Offset Current -25 -1.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Common Mode Input Voltage (V) Common Mode Input Voltage (V) FIGURE 2-9: Input Bias, Offset Currents FIGURE 2-12: Input Bias, Offset Currents vs. Common Mode Input Voltage at T =+85°C. vs. Common Mode Input Voltage at A T =+125°C. A DS21812D-page 6  2004 Microchip Technology Inc.

MCP6291/2/3/4/5 TYPICAL PERFORMANCE CURVES (CONTINUED) Note: Unless otherwise indicated, T = +25°C, V = +2.4V to +5.5V, V = GND, V = V /2, V ≈V /2, A DD SS CM DD OUT DD R = 10kΩ to V /2 and C = 60pF. L DD L 1.6 1000 V) 1.4 m Quiescent Current(mA/Amplifier) 000011......246802 TTTTAAAA ==== + ++ 1-28245550°°°°CCCC put Voltage Headroom ( 11000 VOL - VSS VDD - VOH 0.0 Ou 1 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.01 0.1 1 10 Power Supply Voltage (V) Output Current Magnitude (mA) FIGURE 2-13: Quiescent Current vs. FIGURE 2-16: Output Voltage Headroom Power Supply Voltage. vs. Output Current Magnitude. 120 0 16 90 100 -30 ct 14 85 p Gain (dB) 6800 Phase Gain --9600 p Phase (°) width ProduMHz) 11802 GGBBWWPP,, VVDDDD == 52..54VV 778050 Margin (°) Open-Loo 24000 ---111852000 Open-Loo Gain Band( 246 PPMM,, VVDDDD == 52..54VV 566505 Phase -20 -210 0 50 0.1.E-011 11.E+00 101.E+01 101.E+020 11.E+03k 101.E+04k 1001.E+05k 1M1.E+06 101.E+07M 101.E+080M -50 -25 0 25 50 75 100 125 Frequency (Hz) Ambient Temperature (°C) FIGURE 2-14: Open-Loop Gain, Phase vs. FIGURE 2-17: Gain Bandwidth Product, Frequency. Phase Margin vs. Ambient Temperature. 10 12 ge 10 Falling Edge, VDD = 5.5V olta s) VDD = 2.4V Output Vng (V)P-P 1 VVDDDD == 52..54VV Rate (V/µ 68 um Swi ew 4 Maxim Sl 2 Rising Edge, VVDDDD == 52..54VV 0 0.1 1k1.E+03 101.E+04k 1001.E+05k 1M1.E+06 10M1.E+07 -50 -25 0 25 50 75 100 125 Frequency (Hz) Ambient Temperature (°C) FIGURE 2-15: Maximum Output Voltage FIGURE 2-18: Slew Rate vs. Ambient Swing vs. Frequency. Temperature.  2004 Microchip Technology Inc. DS21812D-page 7

MCP6291/2/3/4/5 TYPICAL PERFORMANCE CURVES (CONTINUED) Note: Unless otherwise indicated, T = +25°C, V = +2.4V to +5.5V, V = GND, V = V /2, V ≈V /2, A DD SS CM DD OUT DD R = 10kΩ to V /2 and C = 60pF. L DD L 1,000 11 sity nsity 109 n e oise Voltage De(nV/Hz)(cid:151) 10100 Noise Voltage D(nV/Hz)(cid:165) 345678 fV =DD 1 =0 5k.H0zV ut N put 2 p n 1 n I I 1 0 1.E-01 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 0.1 1 10 100 1k 10k 100k 1M 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Frequency (Hz) Common Mode Input Voltage (V) FIGURE 2-19: Input Noise Voltage Density FIGURE 2-22: Input Noise Voltage Density vs. Frequency. vs. Common Mode Input Voltage at 10kHz. 35 n 140 Current 2350 eparatio 130 ptut Short Circuit (mA) 1125050 TTTAAA === + ++1282555°°°CCC nnel-to-Channel S(dB) 111200 Ou 0 TA = -40°C Cha 100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1 10 100 Power Supply Voltage (V) Frequency (kHz) FIGURE 2-20: Output Short Circuit Current FIGURE 2-23: Channel-to-Channel vs. Power Supply Voltage. Separation vs. Frequency (MCP6292, MCP6294 and MCP6295 only). 1.2 1.6 Op-Amp shuts off here VDD = 2.4V Op Amp shuts off VDD = 5.5V nt Current mplifier)001...680 Op-Amp turns on here Hysteresis nt Current mplifier)0111....8024 Op Amp turns on Hysteresis Quiesce(mA/A0.4 ChiSg hs wtoe plotw CloSw s two ehpigth Quiesce(mA/A00..46 ChiSg hs wtoe plotw CloSw s two ehpigth 0.2 0.2 0.0 0.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Chip Select Voltage (V) Chip Select Voltage (V) FIGURE 2-21: Quiescent Current vs. FIGURE 2-24: Quiescent Current vs. ChipSelect (CS) Voltage at V = 2.4V ChipSelect (CS) Voltage at V = 5.5V DD DD (MCP6293 and MCP6295 only). (MCP6293 and MCP6295 only). DS21812D-page 8  2004 Microchip Technology Inc.

MCP6291/2/3/4/5 TYPICAL PERFORMANCE CURVES (CONTINUED) Note: Unless otherwise indicated, T = +25°C, V = +2.4V to +5.5V, V = GND, V = V /2, V ≈V /2, A DD SS CM DD OUT DD R = 10kΩ to V /2 and C = 60pF. L DD L 5.0 5.0 G = +1V/V G = -1V/V 4.5 VDD = 5.0V 4.5 VDD = 5.0V 4.0 4.0 V) V) e ( 3.5 e ( 3.5 ag 3.0 ag 3.0 olt 2.5 olt 2.5 V V ut 2.0 ut 2.0 p p ut 1.5 ut 1.5 O O 1.0 1.0 0.5 0.5 0.0 0.0 0.E+00 1.E-06 2.E-06 3.E-06 4.E-06 5.E-06 6.E-06 7.E-06 8.E-06 9.E-06 1.E-05 0.E+00 1.E-06 2.E-06 3.E-06 4.E-06 5.E-06 6.E-06 7.E-06 8.E-06 9.E-06 1.E-05 Time (1 µs/div) Time (1 µs/div) FIGURE 2-25: Large-Signal Non-inverting FIGURE 2-28: Large-Signal Inverting Pulse Pulse Response. Response. G = +1V/V G = -1V/V div) div) V/ V/ m m ge (10 ge (10 olta olta V V ut ut p p ut ut O O Time (200 ns/div) Time (200 ns/div) FIGURE 2-26: Small-Signal Non-inverting FIGURE 2-29: Small-Signal Inverting Pulse Pulse Response. Response. 3.0 6.0 Chip Select, Output Voltages (V) 01122.....50505 OuCtpSVu OtV UHoTlitgahg-eZ OuVGtDVp D=Iu N =+t = 1O2 VV.n4/SVVS Chip Select, Output Voltages (V) 01122334455...........50505050505 OCuStp VVuOotU lHtTaiggeh-Z OutpVGuDV tD= I NO =+ =n 15 VV.5/SVVS 0.00.E+00 5.E-06 1.E-05 2.E-05 2.E-05 3.E-05 3.E-05 4.E-05 4.E-05 5.E-05 5.E-05 0.00.E+00 5.E-06 1.E-05 2.E-05 2.E-05 3.E-05 3.E-05 4.E-05 4.E-05 5.E-05 5.E-05 Time (5 µs/div) Time (5 µs/div) FIGURE 2-27: Chip Select (CS) to FIGURE 2-30: Chip Select (CS) to Amplifier Output Response Time at V = 2.4V Amplifier Output Response Time at V = 5.5V DD DD (MCP6293 and MCP6295 only). (MCP6293 and MCP6295 only).  2004 Microchip Technology Inc. DS21812D-page 9

MCP6291/2/3/4/5 3.0 PIN DESCRIPTIONS Descriptions of the pins are listed in Table3-1 (single op amps) and Table3-2 (dual and quad op amps). TABLE 3-1: PIN FUNCTION TABLE FOR SINGLE OP AMPS MCP6291 MCP6293 (PDIP, MCP6291 MCP6271R (PDIP, MCP6293 Symbol Description SOIC, (SOT-23-5) (SOT-23-5) SOIC, (SOT-23-6) MSOP) MSOP) 6 1 1 6 1 V Analog Output OUT 2 4 4 2 4 V – Inverting Input IN 3 3 3 3 3 V + Non-inverting Input IN 7 5 2 7 6 V Positive Power Supply DD 4 2 5 4 2 V Negative Power Supply SS — — — 8 5 CS Chip Select 1,5,8 — — 1,5 — NC No Internal Connection TABLE 3-2: PIN FUNCTION TABLE FOR DUAL AND QUAD OP AMPS MCP6292 MCP6294 MCP6295 Symbol Description 1 1 — V Analog Output (op amp A) OUTA 2 2 2 V – Inverting Input (op amp A) INA 3 3 3 V + Non-inverting Input (op amp A) INA 8 4 8 V Positive Power Supply DD 5 5 — V + Non-inverting Input (op amp B) INB 6 6 6 V – Inverting Input (op amp B) INB 7 7 7 V Analog Output (op amp B) OUTB — 8 — V Analog Output (op amp C) OUTC — 9 — V – Inverting Input (op amp C) INC — 10 — V + Non-inverting Input (op amp C) INC 4 11 4 V Negative Power Supply SS — 12 — V + Non-inverting Input (op amp D) IND — 13 — V – Inverting Input (op amp D) IND — 14 — V Analog Output (op amp D) OUTD — — 1 V /V + Analog Output (op amp A)/Non-inverting Input (op amp B) OUTA INB — — 5 CS Chip Select 3.1 Analog Outputs 3.4 CS Digital Input The output pins are low-impedance voltage sources. This is a CMOS, Schmitt-triggered input that places the part into a low power mode of operation. 3.2 Analog Inputs 3.5 Power Supply (V and V ) SS DD The non-inverting and inverting inputs are high- The positive power supply (V ) is 2.4V to 5.5V higher impedance CMOS inputs with low bias currents. DD than the negative power supply (V ). For normal SS 3.3 MCP6295’s V /V + Pin operation, the other pins are between V and V . OUTA INB SS DD For the MCP6295 only, the output of op amp A is Typically, these parts are used in a single (positive) supply configuration). In this case, V is connected to connected directly to the non-inverting input of SS ground and V is connected to the supply. V will DD DD opampB; this is the V /V + pin. This connection OUTA INB need a local bypass capacitor (typically 0.01µF to makes it possible to provide a Chip Select pin for duals 0.1µF) within 2mm of the V pin. These parts need to DD in 8-pin packages. use a bulk capacitor (within 100mm), which can be shared with nearby analog parts. DS21812D-page 10  2004 Microchip Technology Inc.

MCP6291/2/3/4/5 4.0 APPLICATION INFORMATION The MCP6291/2/3/4/5 family of op amps is manufac- – tured using Microchip’s state-of-the-art CMOS process, specifically designed for low-cost, low-power RIN MCP629X VOUT and general purpose applications. The low supply VIN + voltage, low quiescent current and wide bandwidth makes the MCP6291/2/3/4/5 ideal for battery-powered applications. (Maximum expected V )–V R ≥-------------------------------------------------------------I--N----------------D----D-- IN 2 mA 4.1 Rail-to-Rail Inputs V –(Minimum expected V ) R ≥-----S---S--------------------------------------------------------------------I--N----- The MCP6291/2/3/4/5 op amp is designed to prevent IN 2 mA phase reversal when the input pins exceed the supply voltages. Figure4-1 shows the input voltage exceeding FIGURE 4-2: Input Current Limiting the supply voltage without any phase reversal. Resistor (RIN). 4.2 Rail-to-Rail Output 6 VDD = 5.0V V) 5 G = +2V/V The output voltage range of the MCP6291/2/3/4/5 op e ( amp is VDD–15mV (min.) and VSS+15mV (max.) ut Voltag 34 VIN VOUT wVDhDen= 5R.5LV=. R1e0fekrΩ t o Fisig urceon2n-1e6c tfeodr motor e iVnfDoDrm/2a tioann.d p 2 Out 4.3 Capacitive Loads ut, 1 p Driving large capacitive loads can cause stability n 0 I problems for voltage feedback op amps. As the load -1 -15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 capacitance increases, the feedback loop’s phase Time (1 ms/div) margin decreases and the closed-loop bandwidth is reduced. This produces gain peaking in the frequency FIGURE 4-1: The MCP6291/2/3/4/5 Show response, with overshoot and ringing in the step No Phase Reversal. response. A unity-gain buffer (G = +1) is the most The input stage of the MCP6291/2/3/4/5 op amps use sensitive to capacitive loads, though all gains show the two differential CMOS input stages in parallel. One same general behavior. operates at low common mode input voltage (VCM), When driving large capacitive loads with these op while the other operates at high VCM. With this topol- amps (e.g., > 100pF when G = +1), a small series ogy, the device operates with VCM up to 0.3mV above resistor at the output (RISO in Figure4-3) improves the VDD and 0.3mV below VSS. The Input Offset Voltage feedback loop’s phase margin (stability) by making the (VOS) is measured at VCM=VSS–0.3mV and output load resistive at higher frequencies. The band- VDD+0.3mV to ensure proper operation. width will be generally lower than the bandwidth with no Input voltages that exceed the absolute maximum volt- capacitive load. age (V – 0.3V to V + 0.3V) can cause excessive SS DD current to flow into or out of the input pins. Current beyond ±2mA can cause reliability problems. Applica- tions that exceed this rating must be externally limited – RISO with a resistor, as shown in Figure4-2. MCP629X V OUT V + IN C L FIGURE 4-3: Output Resistor, R ISO stabilizes large capacitive loads. Figure4-4 gives recommended R values for differ- ISO ent capacitive loads and gains. The x-axis is the normalized load capacitance (C /G ), where G is the L N N circuit's noise gain. For non-inverting gains, G and the N Signal Gain are equal. For inverting gains, G is N 1+|Signal Gain| (e.g., -1 V/V gives G = +2 V/V). N  2004 Microchip Technology Inc. DS21812D-page 11

MCP6291/2/3/4/5 V /V + V – 100 OUTA INB INB ) W 1 6 (O S RI 2 ed VINA– B 7 VOUTB nd 3 A mme GN = 1 V/V VINA+ MCP6295 co GN ≥ 2 V/V e R 10 5 10 100 1,000 10,000 CS Normalized Load Capacitance; C/G (pF) L N FIGURE 4-5: Cascaded Gain Amplifier. FIGURE 4-4: Recommended R Values ISO for Capacitive Loads. The output of op amp A is loaded by the input imped- ance of op amp B, which is typically 1013Ω||6pF, as After selecting R for your circuit, double-check the ISO specified in the DC specification table (Refer to resulting frequency response peaking and step Section4.3 “Capacitive Loads” for further details response overshoot. Modify R 's value until the ISO regarding capacitive loads). response is reasonable. Bench evaluation and The common mode input range of these op amps is simulations with the MCP6291/2/3/4/5 SPICE macro specified in the data sheet as V –300mV and model are helpful. SS V +300mV. However, since the output of op amp A DD is limited to V and V (20mV from the rails with a 4.4 MCP629X Chip Select (CS) OL OH 10kΩ load), the non-inverting input range of op amp B The MCP6293 and MCP6295 are single and dual op is limited to the common mode input range of amps with Chip Select (CS), respectively. When CS is VSS+20mV and VDD–20mV. pulled high, the supply current drops to 0.7µA (typ.) and flows through the CS pin to V . When this 4.6 Supply Bypass SS happens, the amplifier output is put into a high-imped- With this family of operational amplifiers, the power ance state. By pulling CS low, the amplifier is enabled. supply pin (V for single supply) should have a local If the CS pin is left floating, the amplifier may not DD bypass capacitor (i.e., 0.01µF to 0.1µF) within 2mm operate properly. Figure1-1 shows the output voltage for good high-frequency performance. It also needs a and supply current response to a CS pulse. bulk capacitor (i.e., 1µF or larger) within 100mm to provide large, slow currents. This bulk capacitor can be 4.5 Cascaded Dual Op Amps shared with other analog parts. (MCP6295) The MCP6295 is a dual op amp with Chip Select (CS). 4.7 PCB Surface Leakage The Chip Select input is available on what would be the In applications where low input bias current is critical, non-inverting input of a standard dual op amp (pin 5). Printed Circuit Board (PCB) surface-leakage effects This is available because the output of op amp A need to be considered. Surface leakage is caused by connects to the non-inverting input of op amp B, as humidity, dust or other contamination on the board. shown in Figure4-5. The Chip Select input, which can Under low humidity conditions, a typical resistance be connected to a microcontroller I/O line, puts the between nearby traces is 1012Ω. A 5V difference would device in Low-power mode. Refer to Section4.3 cause 5pA of current to flow, which is greater than the “MCP6293/5 Chip Select (CS)”. MCP6291/2/3/4/5 family’s bias current at 25°C (1pA, typ.). The easiest way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). The guard ring is biased at the same voltage as the sensitive pin. An example of this type of layout is shown in Figure4-6. DS21812D-page 12  2004 Microchip Technology Inc.

MCP6291/2/3/4/5 4.8 Application Circuits V – V + IN IN V SS 4.8.1 MULTIPLE FEEDBACK LOW-PASS FILTER The MCP6291/2/3/4/5 op amp can be used in active- filter applications. Figure4-7 shows an inverting, third- order, multiple feedback low-pass filter that can be used as an anti-aliasing filter. Guard Ring R1 R2 R4 VOUT FIGURE 4-6: Example Guard Ring Layout VIN for Inverting Gain. C1 R3 C C4 3 1. For Inverting Gain and Transimpedance Amplifiers (convert current to voltage, such as photo detectors): a. Connect the guard ring to the non-inverting MCP6291 input pin (V +). This biases the guard ring IN V /2 DD to the same reference voltage as the op amp (e.g., V /2 or ground). DD b. Connect the inverting pin (VIN–) to the input FIGURE 4-7: Multiple Feedback Low- with a wire that does not touch the PCB Pass Filter. surface. This filter, and others, can be designed using 2. Non-inverting Gain and Unity-Gain Buffer: Microchip’s FilterLab® software, which is available on a. Connect the non-inverting pin (V +) to the IN our web site (www.microchip.com). input with a wire that does not touch the PCB surface. 4.8.2 PHOTODIODE AMPLIFIER b. Connect the guard ring to the inverting input Figure4-8 shows a photodiode biased in the photovol- pin (V –). This biases the guard ring to the IN taic mode for high precision. The resistor R converts common mode input voltage. the diode current I to the voltage V . The capacitor D OUT is used to limit the bandwidth or to stabilize the circuit against the diode’s capacitance (it is not always needed). C R I D V OUT light MCP6291 V /2 DD FIGURE 4-8: Photodiode Amplifier.  2004 Microchip Technology Inc. DS21812D-page 13

MCP6291/2/3/4/5 4.8.3 CASCADED OP AMP APPLICATIONS R R R R 4 3 2 1 The MCP6295 provides the flexibility of Low-power mode for dual op amps in an 8-pin package. The MCP6295 eliminates the added cost and space in battery-powered applications by using two single op amps with Chip Select lines or a 10-pin device with one B VOUT A Chip Select line for both op amps. Since the two op V IN MCP6295 amps are internally cascaded, this device cannot be used in circuits that require active or passive elements between the two op amps. However, there are several applications where this op amp configuration with CS ChipSelect line becomes suitable. The circuits below show possible applications for this device. FIGURE 4-10: Cascaded Gain Circuit Configuration. 4.8.3.1 Load Isolation 4.8.3.3 Difference Amplifier With the cascaded op amp configuration, op amp B can be used to isolate the load from op amp A. In applica- Figure4-11 shows op amp A as a difference amplifier tions where op amp A is driving capacitive or low resis- with Chip Select. In this configuration, it is recom- tance loads in the feedback loop (such as an integrator mended to use well-matched resistors (e.g., 0.1%) to circuit or filter circuit), the op amp may not have increase the Common Mode Rejection Ratio (CMRR). sufficient source current to drive the load. In this case, Op amp B can be used for additional gain or as a unity- op amp B can be used as a buffer. gain buffer to isolate the load from the difference amplifier. R R 4 3 B VOUTB R R 2 1 A V Load IN2 MCP6295 B VOUT R2 A V CS IN1 MCP6295 R 1 FIGURE 4-9: Isolating the Load with a Buffer. CS 4.8.3.2 Cascaded Gain FIGURE 4-11: Difference Amplifier Circuit. Figure4-10 shows a cascaded gain circuit configura- tion with Chip Select. Op amps A and B are configured in a non-inverting amplifier configuration. In this config- uration, it is important to note that the input offset volt- age of op amp A is amplified by the gain of op amp A and B, as shown below: V = V G G +V G G +V G OUT IN A B OSA A B OSB B Where: G = op amp A gain A G = op amp B gain B V = op amp A input offset voltage OSA V = op amp B input offset voltage OSB Therefore, it is recommended to set most of the gain with op amp A and use op amp B with relatively small gain (e.g., a unity-gain buffer). DS21812D-page 14  2004 Microchip Technology Inc.

MCP6291/2/3/4/5 4.8.3.4 Buffered Non-inverting Integrator 4.8.3.6 Second-Order MFB Low-Pass Filter with an Extra Pole-Zero Pair Figure4-12 shows a lossy non-inverting integrator that is buffered and has a Chip Select input. Op amp A is Figure4-14 is a second-order multiple feedback low- configured as a non-inverting integrator. In this config- pass filter with Chip Select. Use the FilterLab® software uration, matching the impedance at each input is from Microchip to determine the R and C values for the recommended. RF is used to provide a feedback loop op amp A’s second-order filter. Op amp B can be used at frequencies << 1/(2πR1C1) and makes this a lossy to add a pole-zero pair using C3, R6 and R7. integrator (it has a finite gain at DC). Op amp B is used to isolate the load from the integrator. R6 C3 R 1 R C 2 2 C 1 R 7 R R R 3 2 R1 A F B VOUT VIN R A B VOUT VIN MCP6295 C2 R54 MCP6295 C 1 CS CS R1C1=(R2||RF)C2 FIGURE 4-14: Second-Order Multiple Feedback Low-Pass Filter with an Extra Pole- FIGURE 4-12: Buffered Non-inverting Zero Pair. Integrator with Chip Select. 4.8.3.7 Second-Order Sallen-Key Low-Pass 4.8.3.5 Inverting Integrator with Active Filter with an Extra Pole-Zero Pair Compensation and Chip Select Figure4-15 is a second-order, Sallen-Key low-pass Figure4-13 uses an active compensator (op amp B) to filter with Chip Select. Use the FilterLab® software from compensate for the non-ideal op amp characteristics Microchip to determine the R and C values for the op introduced at higher frequencies. This circuit uses amp A’s second-order filter. Op amp B can be used to opamp B as a unity-gain buffer to isolate the integra- add a pole-zero pair using C , R and R . 3 5 6 tion capacitor C from op amp A and drives the capac- 1 itor with low-impedance source. Since both op amps are matched very well, they provide a high quality R2 R1 R5 C3 integrator. R 6 R1 C1 R4 R3 A B VOUT VIN VIN MCP6295 B C1 C 2 CS A VOUT MCP6295 FIGURE 4-15: Second-Order Sallen-Key Low-Pass Filter with an Extra Pole-Zero Pair and Chip Select. CS FIGURE 4-13: Integrator Circuit with Active Compensation.  2004 Microchip Technology Inc. DS21812D-page 15

MCP6291/2/3/4/5 4.8.3.8 Capacitorless Second-Order 5.0 DESIGN TOOLS Low-Pass filter with Chip Select Microchip provides the basic design tools needed for The low-pass filter shown in Figure4-16 does not the MCP6291/2/3/4/5 family of op amps. require external capacitors and uses only three exter- nal resistors; the op amp’s GBWP sets the corner 5.1 SPICE Macro Model frequency. R and R are used to set the circuit gain 1 2 and R is used to set the Q. To avoid gain peaking in The latest SPICE macro model for the 3 the frequency response, Q needs to be low (lower MCP6291/2/3/4/5 op amps is available on our web site values need to be selected for R ). Note that the at www.microchip.com. This model is intended to be an 3 amplifier bandwidth varies greatly over temperature initial design tool that works well in the op amp’s linear and process. However, this configuration provides a region of operation at room temperature. See the low cost solution for applications with high bandwidth macro model file for information on its capabilities. requirements. Bench testing is a very important part of any design and cannot be replaced with simulations. Also, simulation results using this macro model need to be validated by R R 2 1 V comparing them to the data sheet specifications and IN characteristic curves. R 3 5.2 FilterLab® Software A B VOUT Microchip’s FilterLab software is an innovative tool that V REF simplifies analog active-filter (using op amps) design. MCP6295 Available at no cost from our web site at www.microchip.com, the FilterLab design tool provides CS full schematic diagrams of the filter circuit with component values. It also outputs the filter circuit in FIGURE 4-16: Capacitorless Second-Order SPICE format, which can be used with the macro Low-Pass Filter with Chip Select. model to simulate actual filter performance. DS21812D-page 16  2004 Microchip Technology Inc.

MCP6291/2/3/4/5 6.0 PACKAGING INFORMATION 6.1 Package Marking Information 5-Lead SOT-23 (MCP6291 and MCP6291R) Example: Device Code XXNN CJ25 MCP6291 CJNN MCP6291R EVNN Note: Applies to 5-Lead SOT-23 6-Lead SOT-23 (MCP6283) Example: XXNN CM25 8-Lead MSOP Example: XXXXXX 6291E YWWNNN 436256 8-Lead PDIP (300 mil) Example: XXXXXXXX MCP6291 XXXXXNNN E/P256 YYWW 0436 8-Lead SOIC (150 mil) Example: XXXXXXXX MCP6291 XXXXYYWW E/SN0436 NNN 256 Legend: XX...X Customer specific information* YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard marking consists of Microchip part number, year code, week code, traceability code (facility code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please check with your Microchip Sales Office.  2004 Microchip Technology Inc. DS21812D-page 17

MCP6291/2/3/4/5 Package Marking Information (Continued) 14-Lead PDIP (300 mil) (MCP6294) Example: XXXXXXXXXXXXXX MCP6294-E/P XXXXXXXXXXXXXX YYWWNNN 0436256 14-Lead SOIC (150 mil) (MCP6294) Example: XXXXXXXXXX MCP6294ESL XXXXXXXXXX YYWWNNN 0436256 14-Lead TSSOP (MCP6294) Example: XXXXXX 6294EST YYWW 0436 NNN 256 DS21812D-page 18  2004 Microchip Technology Inc.

MCP6291/2/3/4/5 5-Lead Plastic Small Outline Transistor (OT) (SOT-23) E E1 p B p1 D n 1 α c A A2 φ A1 L β Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 5 5 Pitch p .038 0.95 Outside lead pitch (basic) p1 .075 1.90 Overall Height A .035 .046 .057 0.90 1.18 1.45 Molded Package Thickness A2 .035 .043 .051 0.90 1.10 1.30 Standoff A1 .000 .003 .006 0.00 0.08 0.15 Overall Width E .102 .110 .118 2.60 2.80 3.00 Molded Package Width E1 .059 .064 .069 1.50 1.63 1.75 Overall Length D .110 .116 .122 2.80 2.95 3.10 Foot Length L .014 .018 .022 0.35 0.45 0.55 Foot Angle φ 0 5 10 0 5 10 Lead Thickness c .004 .006 .008 0.09 0.15 0.20 Lead Width B .014 .017 .020 0.35 0.43 0.50 Mold Draft Angle Top α 0 5 10 0 5 10 Mold Draft Angle Bottom β 0 5 10 0 5 10 *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. EIAJ Equivalent: SC-74A Drawing No. C04-091  2004 Microchip Technology Inc. DS21812D-page 19

MCP6291/2/3/4/5 6-Lead Plastic Small Outline Transistor (CH) (SOT-23) E E1 B p1 D n 1 α c A A2 φ L A1 β Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 6 6 Pitch p .038 0.95 Outside lead pitch (basic) p1 .075 1.90 Overall Height A .035 .046 .057 0.90 1.18 1.45 Molded Package Thickness A2 .035 .043 .051 0.90 1.10 1.30 Standoff A1 .000 .003 .006 0.00 0.08 0.15 Overall Width E .102 .110 .118 2.60 2.80 3.00 Molded Package Width E1 .059 .064 .069 1.50 1.63 1.75 Overall Length D .110 .116 .122 2.80 2.95 3.10 Foot Length L .014 .018 .022 0.35 0.45 0.55 Foot Angle φ 0 5 10 0 5 10 Lead Thickness c .004 .006 .008 0.09 0.15 0.20 Lead Width B .014 .017 .020 0.35 0.43 0.50 Mold Draft Angle Top α 0 5 10 0 5 10 Mold Draft Angle Bottom β 0 5 10 0 5 10 *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. JEITA (formerly EIAJ) equivalent: SC-74A Drawing No. C04-120 DS21812D-page 20  2004 Microchip Technology Inc.

MCP6291/2/3/4/5 8-Lead Plastic Micro Small Outline Package (MS) (MSOP) E E1 p D 2 B n 1 α A A2 c φ A1 (F) L β Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch p .026 BSC 0.65 BSC Overall Height A - - .043 - - 1.10 Molded Package Thickness A2 .030 .033 .037 0.75 0.85 0.95 Standoff A1 .000 - .006 0.00 - 0.15 Overall Width E .193 TYP. 4.90 BSC Molded Package Width E1 .118 BSC 3.00 BSC Overall Length D .118 BSC 3.00 BSC Foot Length L .016 .024 .031 0.40 0.60 0.80 Footprint (Reference) F .037 REF 0.95 REF Foot Angle φ 0° - 8° 0° - 8° Lead Thickness c .003 .006 .009 0.08 - 0.23 Lead Width B .009 .012 .016 0.22 - 0.40 Mold Draft Angle Top α 55°° - 15° 5° - 15° Mold Draft Angle Bottom β 55°° --- 15° 5° - 15° *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MO-187 Drawing No. C04-111  2004 Microchip Technology Inc. DS21812D-page 21

MCP6291/2/3/4/5 8-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n 1 α E A A2 L c A1 β B1 p eB B Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch p .100 2.54 Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32 Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26 Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60 Overall Length D .360 .373 .385 9.14 9.46 9.78 Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43 Lead Thickness c .008 .012 .015 0.20 0.29 0.38 Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78 Lower Lead Width B .014 .018 .022 0.36 0.46 0.56 Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92 Mold Draft Angle Top α 5 10 15 5 10 15 Mold Draft Angle Bottom β 5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018 DS21812D-page 22  2004 Microchip Technology Inc.

MCP6291/2/3/4/5 8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 h α 45° c A A2 φ β L A1 Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch p .050 1.27 Overall Height A .053 .061 .069 1.35 1.55 1.75 Molded Package Thickness A2 .052 .056 .061 1.32 1.42 1.55 Standoff § A1 .004 .007 .010 0.10 0.18 0.25 Overall Width E .228 .237 .244 5.79 6.02 6.20 Molded Package Width E1 .146 .154 .157 3.71 3.91 3.99 Overall Length D .189 .193 .197 4.80 4.90 5.00 Chamfer Distance h .010 .015 .020 0.25 0.38 0.51 Foot Length L .019 .025 .030 0.48 0.62 0.76 Foot Angle φ 0 4 8 0 4 8 Lead Thickness c .008 .009 .010 0.20 0.23 0.25 Lead Width B .013 .017 .020 0.33 0.42 0.51 Mold Draft Angle Top α 0 12 15 0 12 15 Mold Draft Angle Bottom β 0 12 15 0 12 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057  2004 Microchip Technology Inc. DS21812D-page 23

MCP6291/2/3/4/5 14-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n 1 α E A A2 c L A1 β B1 eB B p Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 14 14 Pitch p .100 2.54 Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32 Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26 Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60 Overall Length D .740 .750 .760 18.80 19.05 19.30 Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43 Lead Thickness c .008 .012 .015 0.20 0.29 0.38 Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78 Lower Lead Width B .014 .018 .022 0.36 0.46 0.56 Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92 Mold Draft Angle Top α 5 10 15 5 10 15 Mold Draft Angle Bottom β 5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent:MS-001 Drawing No. C04-005 DS21812D-page 24  2004 Microchip Technology Inc.

MCP6291/2/3/4/5 14-Lead Plastic Small Outline (SL) – Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 α h 45° c A A2 φ A1 L β Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 14 14 Pitch p .050 1.27 Overall Height A .053 .061 .069 1.35 1.55 1.75 Molded Package Thickness A2 .052 .056 .061 1.32 1.42 1.55 Standoff § A1 .004 .007 .010 0.10 0.18 0.25 Overall Width E .228 .236 .244 5.79 5.99 6.20 Molded Package Width E1 .150 .154 .157 3.81 3.90 3.99 Overall Length D .337 .342 .347 8.56 8.69 8.81 Chamfer Distance h .010 .015 .020 0.25 0.38 0.51 Foot Length L .016 .033 .050 0.41 0.84 1.27 Foot Angle φ 0 4 8 0 4 8 Lead Thickness c .008 .009 .010 0.20 0.23 0.25 Lead Width B .014 .017 .020 0.36 0.42 0.51 Mold Draft Angle Top α 0 12 15 0 12 15 Mold Draft Angle Bottom β 0 12 15 0 12 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent:MS-012 Drawing No. C04-065  2004 Microchip Technology Inc. DS21812D-page 25

MCP6291/2/3/4/5 14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP) E E1 p D 2 n 1 B α A c φ β A1 A2 L Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 14 14 Pitch p .026 0.65 Overall Height A .043 1.10 Molded Package Thickness A2 .033 .035 .037 0.85 0.90 0.95 Standoff § A1 .002 .004 .006 0.05 0.10 0.15 Overall Width E .246 .251 .256 6.25 6.38 6.50 Molded Package Width E1 .169 .173 .177 4.30 4.40 4.50 Molded Package Length D .193 .197 .201 4.90 5.00 5.10 Foot Length L .020 .024 .028 0.50 0.60 0.70 Foot Angle φ 0 4 8 0 4 8 Lead Thickness c .004 .006 .008 0.09 0.15 0.20 Lead Width B1 .007 .010 .012 0.19 0.25 0.30 Mold Draft Angle Top α 0 5 10 0 5 10 Mold Draft Angle Bottom β 0 5 10 0 5 10 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005” (0.127mm) per side. JEDEC Equivalent:MO-153 Drawing No. C04-087 DS21812D-page 26  2004 Microchip Technology Inc.

MCP6291/2/3/4/5 APPENDIX A: REVISION HISTORY Revision A (June 2003) Original data sheet release. Revision B (October 2003) Revision C (June 2004) Revision D (December 2004) The following is the list of modifications: 1. Added SOT-23-5 packages for the MCP6291 and MCP6291R single op amps. 2. Added SOT-23-6 package for the MCP6293 single op amp. 3. Added Section3.0 “Pin Descriptions”. 4. Corrected application circuits (Section4.8 “Application Circuits”). 5. Added SOT-23-5 and SOT-23-6 packages and corrected package marking information (Section6.0 “Packaging Information”). 6. Added Appendix A: Revision History.  2004 Microchip Technology Inc. DS21812D-page 27

MCP6291/2/3/4/5 NOTES: DS21812D-page 28  2004 Microchip Technology Inc.

MCP6291/2/3/4/5 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. – X /XX Examples: a) MCP6291-E/SN: Extended Temperature, Device Temperature Package 8LD SOIC package. Range b) MCP6291-E/MS: Extended Temperature, 8LD MSOP package. c) MCP6291-E/P: Extended Temperature, 8LD PDIP package. Device: MCP6291: Single Op Amp MCP6291T: Single Op Amp d) MCP6291T-E/OT: Tape and Reel, (Tape and Reel) Extended Temperature, 5LD SOT-23 package. (SOIC, MSOP, SOT-23-5) MCP6291RT: Single Op Amp a) MCP6292-E/SN: Extended Temperature, (Tape and Reel) (SOT-23-5) 8LD SOIC package. MCP6292: Dual Op Amp b) MCP6292-E/MS: Extended Temperature, MCP6292T: Dual Op Amp 8LD MSOP package. (Tape and Reel) (SOIC, MSOP) c) MCP6292-E/P: Extended Temperature, MCP6293: Single Op Amp with Chip Select 8LD PDIP package. MCP6293T: Single Op Amp with Chip Select d) MCP6292T-E/SN: Tape and Reel, (Tape and Reel) Extended Temperature, (SOIC, MSOP, SOT-23-6) 8LD SOIC package. MCP6294: Quad Op Amp MCP6294T: Quad Op Amp a) MCP6293-E/SN: Extended Temperature, (Tape and Reel) (SOIC, TSSOP) 8LD SOIC package. MCP6295: Dual Op Amp with Chip Select b) MCP6293-E/MS: Extended Temperature, MCP6295T: Dual Op Amp with Chip Select 8LD MSOP package. (Tape and Reel) (SOIC, MSOP) c) MCP6293-E/P: Extended Temperature, 8LD PDIP package. d) MCP6293T-E/CH: Tape and Reel, Temperature Range: E = -40°C to +125°C Extended Temperature, 6LD SOT-23 package. a) MCP6294-E/P: Extended Temperature, Package: OT = Plastic Small Outline Transistor (SOT-23), 5-lead 14LD PDIP package. (MCP6291, MCP6291R) b) MCP6294T-E/SL: Tape and Reel, CH = Plastic Small Outline Transistor (SOT-23), 6-lead Extended Temperature, (MCP6293) 14LD SOIC package. MS = Plastic MSOP, 8-lead c) MCP6294-E/SL: Extended Temperature, P = Plastic DIP (300 mil Body), 8-lead, 14-lead 14LD SOIC package. SN = Plastic SOIC, (150 mil Body), 8-lead d) MCP6294-E/ST: Extended Temperature, SL = Plastic SOIC (150 mil Body), 14-lead 14LD TSSOP package. ST = Plastic TSSOP (4.4 mm Body), 14-lead a) MCP6295-E/SN: Extended Temperature, 8LD SOIC package. b) MCP6295-E/MS: Extended Temperature, 8LD MSOP package. c) MCP6295-E/P: Extended Temperature, 8LD PDIP package. d) MCP6295T-E/SN: Tape and Reel, Extended Temperature, 8LD SOIC package. Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office 2. The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. Customer Notification System Register on our web site (www.microchip.com) to receive the most current information on our products.  2004 Microchip Technology Inc. DS21812D-page 29

MCP6291/2/3/4/5 NOTES: DS21812D-page 30  2004 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: (cid:127) Microchip products meet the specification contained in their particular Microchip Data Sheet. (cid:127) Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. (cid:127) There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. (cid:127) Microchip is willing to work with the customer who is concerned about the integrity of their code. (cid:127) Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, Accuron, and may be superseded by updates. It is your responsibility to dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. PROMATE, PowerSmart, rfPIC, and SmartShunt are MICROCHIP MAKES NO REPRESENTATIONS OR WAR- registered trademarks of Microchip Technology Incorporated RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, in the U.S.A. and other countries. WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, PICMASTER, SEEVAL, SmartSensor and The Embedded MERCHANTABILITY OR FITNESS FOR PURPOSE. Control Solutions Company are registered trademarks of Microchip disclaims all liability arising from this information and Microchip Technology Incorporated in the U.S.A. its use. Use of Microchip’s products as critical components in Analog-for-the-Digital Age, Application Maestro, dsPICDEM, life support systems is not authorized except with express dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, written approval by Microchip. No licenses are conveyed, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial implicitly or otherwise, under any Microchip intellectual property Programming, ICSP, ICEPIC, MPASM, MPLIB, MPLINK, rights. MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2004, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company’s quality system processes and procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2004 Microchip Technology Inc. DS21812D-page 31

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: MCP6293-E/SN MCP6294-E/SL MCP6294-E/ST MCP6293-E/MS MCP6291-E/P MCP6291-E/SN MCP6291-E/MS MCP6294-E/P MCP6292-E/P MCP6292-E/SN MCP6291T-E/SN MCP6292T-E/MS MCP6292T-E/SN MCP6293T- E/SN MCP6294T-E/SL MCP6291T-E/MS MCP6293T-E/MS MCP6294T-E/ST MCP6293-E/P MCP6291RT-E/OT MCP6291T-E/OT MCP6293T-E/CH