MCP6281/1R/2/3/4/5 450 µA, 5 MHz Rail-to-Rail Op Amp Features Description • Gain Bandwidth Product: 5MHz (typical) The Microchip Technology Inc. MCP6281/1R/2/3/4/5 • Supply Current: I = 450µA (typical) family of operational amplifiers (op amps) provide wide Q bandwidth for the current. This family has a 5MHz Gain • Supply Voltage: 2.2V to 6.0V Bandwidth Product (GBWP) and a 65° phase margin. • Rail-to-Rail Input/Output This family also operates from a single supply voltage • Extended Temperature Range: -40°C to +125°C as low as 2.2V, while drawing 450µA (typical) quiescent • Available in Single, Dual, and Quad Packages current. Additionally, the MCP6281/1R/2/3/4/5 supports • Single with CS (MCP6283) rail-to-rail input and output swing, with a common mode • Dual with CS (MCP6285) input voltage range of VDD+300mV to VSS–300mV. This family of operational amplifiers is designed with Applications Microchip’s advanced CMOS process. The MCP6285 has a Chip Select (CS) input for dual op • Automotive amps in an 8-pin package. This device is manufactured • Portable Equipment by cascading the two op amps (the output of op amp A • Photodiode Amplifier connected to the non-inverting input of op amp B). The • Analog Filters CS input puts the device in Low-power mode. • Notebooks and PDAs The MCP6281/1R/2/3/4/5 family operates over the • Battery-Powered Systems Extended Temperature Range of -40°C to +125°C. It also has a power supply range of 2.2V to 6.0V. Design Aids • SPICE Macro Models • FilterLab® Software • Mindi™ Circuit Designer & Simulator • MAPS (Microchip Advanced Part Selector) • Analog Demonstration and Evaluation Boards • Application Notes Package Types MCP6281 MCP6281 MCP6281R MCP6282 PDIP, SOIC, MSOP SOT-23-5 SOT-23-5 PDIP, SOIC, MSOP VVNIINNC+_ 123 +- 876 VNVDOCDUT VVVOINUS+ST 123 + - 45 VVDIND– VVVOINDU+DT 123 + - 45 VVSINS– VVVOIUINNTAAA+_ 123 -+ +- 876 VVVODINDUBT_B VSS 4 5 NC VSS 4 5 VINB+ MCP6283 MCP6283 MCP6284 MCP6285 PDIP, SOIC, MSOP SOT-23-6 PDIP, SOIC, TSSOP PDIP, SOIC, MSOP VVVNIINSNC+S_ 1234 +- 8765 CVVNDOCSDUT VVVOINSU+ST 123 +- 465 CVVDISND_ VVVOIVINNUDAAT+DA_ 2134 -+ +- 11111432VVVVSOIINNSUDDT_+D VOUTA/VVVIIIVNNNABSA++S_ 1234 -+ +- 8756 VVVCODISNDUBT_B VINB+ 5 10VINC+ VINB_ 6 -+ +- 9 VINC_ VOUTB 7 8 VOUTC  2019 Microchip Technology Inc. DS20001811F-page 1

MCP6281/1R/2/3/4/5 1.0 ELECTRICAL † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the CHARACTERISTICS device. This is a stress rating only and functional operation of the device at those or any other conditions above those Absolute Maximum Ratings † indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended V –V ........................................................................7.0V DD SS periods may affect device reliability. Current at Input Pins ....................................................±2mA †† See Section4.1.2 “Input Voltage and Current Limits”. Analog Inputs (V +, V –)††........V –1.0VtoV +1.0V IN IN SS DD All Other Inputs and Outputs .........V –0.3V to V +0.3V SS DD Difference Input Voltage ......................................|V –V | DD SS Output Short Circuit Current .................................Continuous Current at Output and Supply Pins ............................±30mA Storage Temperature....................................–65°C to +150°C Maximum Junction Temperature (T )..........................+150°C J ESD Protection On All Pins (HBM; MM) 4kV; 400V DC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, T = +25C, V =+2.2V to +5.5V, V =GND, V V /2, A DD SS OUT DD V = V /2, V = V /2, R = 10kto V and CS is tied low. (refer to Figure1-2 and Figure1-3). CM DD L DD L L Parameters Sym Min Typ Max Units Conditions Input Offset Input Offset Voltage V -3.0 — +3.0 mV V = V (Note1) OS CM SS Input Offset Voltage V -5.0 — +5.0 mV T = -40°C to +125°C, OS A (Extended Temperature) V = V (Note1) CM SS Input Offset Temperature Drift V /T — ±1.7 — µV/°C T = -40°C to +125°C, OS A A V = V (Note1) CM SS Power Supply Rejection Ratio PSRR 70 90 — dB V = V (Note1) CM SS Input Bias, Input Offset Current and Impedance Input Bias Current I — ±1.0 — pA Note2 B At Temperature I — 50 200 pA T = +85°C (Note2) B A At Temperature I — 2 5 nA T = +125°C (Note2) B A Input Offset Current I — ±1.0 — pA Note3 OS Common Mode Input Impedance Z — 1013||6 — ||pF Note3 CM Differential Input Impedance Z — 1013||3 — ||pF Note3 DIFF Common Mode (Note4) Common Mode Input Range V V 0.3 — V + 0.3 V CMR SS DD Common Mode Rejection Ratio CMRR 70 85 — dB V = -0.3V to 2.5V, V = 5V CM DD Common Mode Rejection Ratio CMRR 65 80 — dB V = -0.3V to 5.3V, V = 5V CM DD Open-Loop Gain DC Open-Loop Gain (Large Signal) A 90 110 — dB V = 0.2V to V – 0.2V, OL OUT DD V =V (Note1) CM SS Output Maximum Output Voltage Swing V , V V + 15 — V – 15 mV 0.5V input overdrive OL OH SS DD Output Short Circuit Current I — ±25 — mA SC Power Supply Supply Voltage V 2.2 — 6.0 V (Note5) DD Quiescent Current per Amplifier I 300 450 570 µA I = 0 Q O Note 1: The MCP6285’s V for op amp B (pins V /V + and V –) is V + 100mV. CM OUTA INB INB SS 2: The current at the MCP6285’s V – pin is specified by I only. INB B 3: This specification does not apply to the MCP6285’s V /V + pin. OUTA INB 4: The MCP6285’s V – pin (op amp B) has a common mode range (V ) of V + 100mV to V – 100mV. INB CMR SS DD The MCP6285’s V /V + pin (op amp B) has a voltage range specified by V and V . OUTA INB OH OL 5: All parts with date codes November 2007 and later have been screened to ensure operation at V = 6.0V. However, DD the other minimum and maximum specifications are measured at 2.4V and/or 5.5V. DS20001811F-page 2  2019 Microchip Technology Inc.

MCP6281/1R/2/3/4/5 AC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, T = +25°C, V = +2.2V to +5.5V, V = GND, V V /2, A DD SS OUT DD V = V /2, V = V /2, R = 10kto V , C = 60pF and CS is tied low. (refer to Figure1-2 and Figure1-3). CM DD L DD L L L Parameters Sym Min Typ Max Units Conditions AC Response Gain Bandwidth Product GBWP — 5.0 — MHz Phase Margin at Unity-Gain PM — 65 — ° G = +1V/V Slew Rate SR — 2.5 — V/µs Noise Input Noise Voltage E — 5.2 — µV f = 0.1Hz to 10Hz ni P-P Input Noise Voltage Density e — 16 — nV/Hz f = 1kHz ni Input Noise Current Density i — 3 — fA/Hz f = 1kHz ni MCP6283/MCP6285 CHIP SELECT (CS) SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, T = +25°C, V = +2.2V to +5.5V, V = GND, V V /2, A DD SS OUT DD V = V /2, V = V /2, R = 10kto V , C = 60pF and CS is tied low. (refer to Figure1-2 and Figure1-3). CM DD L DD L L L Parameters Sym Min Typ Max Units Conditions CS Low Specifications CS Logic Threshold, Low V V — 0.2V V IL SS DD CS Input Current, Low I — 0.01 — µA CS = V CSL SS CS High Specifications CS Logic Threshold, High V 0.8V — V V IH DD DD CS Input Current, High I — 0.7 2 µA CS = V CSH DD GND Current per Amplifier I — -0.7 — µA CS = V SS DD Amplifier Output Leakage — — 0.01 — µA CS = V DD Dynamic Specifications (Note1) CS Low to Valid Amplifier t — 4 10 µs CS Low  0.2V , G = +1V/V, ON DD Output, Turn-on Time V = V /2, V = 0.9V /2, IN DD OUT DD V = 5.0V DD CS High to Amplifier Output High-Z t — 0.01 — µs CS High  0.8V , G = +1V/V, OFF DD V = V /2, V = 0.1V /2 IN DD OUT DD Hysteresis V — 0.6 — V V = 5V HYST DD Note 1: The input condition (V ) specified applies to both op amp A and B of the MCP6285. The dynamic specification is tested IN at the output of op amp B (V ). OUTB CS V V IL IH t t OFF ON Hi-Z Hi-Z V OUT -0.7µA -0.7µA (typical) -450µA (typical) I SS (typical) 0.7µA 0.7µA (typical) 10nA (typical) ICS (typical) FIGURE 1-1: Timing Diagram for the Chip Select (CS) pin on the MCP6283 and MCP6285.  2019 Microchip Technology Inc. DS20001811F-page 3

MCP6281/1R/2/3/4/5 TEMPERATURE SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, V = +2.2V to +5.5V and V = GND. DD SS Parameters Sym Min Typ Max Units Conditions Temperature Ranges Operating Temperature Range T -40 — +125 °C Note A Storage Temperature Range T -65 — +150 °C A Thermal Package Resistances Thermal Resistance, 5L-SOT-23  — 256 — °C/W JA Thermal Resistance, 6L-SOT-23  — 230 — °C/W JA Thermal Resistance, 8L-PDIP  — 85 — °C/W JA Thermal Resistance, 8L-SOIC  — 163 — °C/W JA Thermal Resistance, 8L-MSOP  — 206 — °C/W JA Thermal Resistance, 14L-PDIP  — 70 — °C/W JA Thermal Resistance, 14L-SOIC  — 120 — °C/W JA Thermal Resistance, 14L-TSSOP  — 100 — °C/W JA Note: The Junction Temperature (T ) must not exceed the Absolute Maximum specification of +150°C. J 1.1 Test Circuits The test circuits used for the DC and AC tests are shown in Figure1-2 and Figure1-2. The bypass capacitors are laid out according to the rules discussed in Section4.6 “Supply Bypass”. V VDD 0.1µF 1µF IN + RN VOUT MCP628X – C R L L VDD/2 RG RF V L FIGURE 1-2: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. VDD 1µF V /2 0.1µF DD + RN VOUT MCP628X – C R L L VIN RG RF V L FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions. DS20001811F-page 4  2019 Microchip Technology Inc.

MCP6281/1R/2/3/4/5 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, T = +25°C, V = +2.2V to +6.0V, V = GND, V = V /2, V V /2, A DD SS CM DD OUT DD V = V /2, R = 10k to V , C = 60pF and CS is tied low. L DD L L L 14% 30% nces 12% 8V3C2M S= aVmSSples ces 25% 8V3C2M S= aVmSSples curre 10% urren 20% TA = -40°C to +125°C Oc 8% cc ge of 6% e of O 15% enta 4% ntag 10% Perc 2% erce 5% 0% P 8 4 0 6 2 8 4 0 4 8 2 6 0 4 8 0% -2. -2. -2. -1. -1. -0. -0. 0. 0. 0. 1. 1. 2. 2. 2. -10 -8 -6 -4 -2 0 2 4 6 8 10 Input Offset Voltage (mV) Input Offset Voltage Drift (µV/°C) FIGURE 2-1: Input Offset Voltage. FIGURE 2-4: Input Offset Voltage Drift. 25% 35% 210 Samples 210 Samples Occurrences 1250%% TA = +85°C Occurrences 223050%%% TA = +125°C Percentage of 105%% Percentage of 110505%%%% 0% 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 20 30 40 50 60 70 80 90 100 2 4 8 12 16 20 24 28 32 36 Input Bias Current (pA) Input Bias Current (pA) FIGURE 2-2: Input Bias Current at FIGURE 2-5: Input Bias Current at T =+85 °C. T =+125 °C. A A 300 300 VDD = 2.2V VDD = 5.5V V) 250 V) 250 ge (µ 200 ge (µ 200 olta 150 olta 150 Offset V 10500 TA = +125°C Offset V 10500 TA = +125°C ut 0 TA = +85°C ut 0 TA = +85°C np -50 TA = +25°C np -50 TA = +25°C I TA = -40°C I TA = -40°C -100 -100 5 0 5 0 5 0 5 0 5 0 5 0 5 0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 0. 0. 0. 1. 1. 2. 2. 3. 3. 4. 4. 5. 5. 6. - Common Mode Input Voltage (V) Common Mode Input Voltage (V) FIGURE 2-3: Input Offset Voltage vs. FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage at V = 2.2V. Common Mode Input Voltage at V = 5.5V. DD DD  2019 Microchip Technology Inc. DS20001811F-page 5

MCP6281/1R/2/3/4/5 TYPICAL PERFORMANCE CURVES (CONTINUED) Note: Unless otherwise indicated, T = +25°C, V = +2.2V to +6.0V, V = GND, V = V /2, V V /2, A DD SS CM DD OUT DD V = V /2, R = 10k to V , C = 60pF and CS is tied low. L DD L L L 300 10,000 µV) 250 VRCeMp r=e sVeSSntative Part nts VVCDMD == 5V.D5DV nput Offset Voltage ( 112-05055000000 VDD = 2.2V VDD = 5.5V ut Bias, Offset Curre(pA) 1,10001000 InIpnuptu Ot Bffisaest CCuurrrreenntt I p n -100 I 1 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 25 35 45 55 65 75 85 95 105 115 125 Output Voltage (V) Ambient Temperature (°C) FIGURE 2-7: Input Offset Voltage vs. FIGURE 2-10: Input Bias, Input Offset Output Voltage. Currents vs. Ambient Temperature. 110 120 PSRR- 100 CMRR 110 R (dB) 8900 PSRR+ RR (dB) 100 CMRR CMRR, PSR 45670000 PSRR, CM 789000 PVSCMR =R VSS 30 60 20 11.E+00 11.E0+01 101.E+002 11.kE+03 101.E+0k4 101.E0+05k 11M.E+06 -50 -25 0 25 50 75 100 125 Frequency (Hz) Ambient Temperature (°C) FIGURE 2-8: CMRR, PSRR vs. FIGURE 2-11: CMRR, PSRR vs. Ambient Frequency. Temperature. 55 2.5 s TA = +125°C Current 3455 Input Bias Current urrents 12..50 VDD = 5.5V Input Bias Current as, Offset (pA) 12555 s, Offset C(nA) 01..50 Input Bi -1-55 TVAD D= = + 58.55°VC Input Offset Current Input Bia -00..05 Input Offset Current -25 -1.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Common Mode Input Voltage (V) Common Mode Input Voltage (V) FIGURE 2-9: Input Bias, Offset Currents FIGURE 2-12: Input Bias, Offset Currents vs. Common Mode Input Voltage at T =+85°C. vs. Common Mode Input Voltage at T =+125°C. A A DS20001811F-page 6  2019 Microchip Technology Inc.

MCP6281/1R/2/3/4/5 TYPICAL PERFORMANCE CURVES (CONTINUED) Note: Unless otherwise indicated, T = +25°C, V = +2.2V to +6.0V, V = GND, V = V /2, V V /2, A DD SS CM DD OUT DD V = V /2, R = 10k to V , C = 60pF and CS is tied low. L DD L L L 600 1000 V) 500 m nt Currentmplifier) 340000 eadroom ( 100 Quiesce(µA/a 120000 TTTAAA === +++1822555°°CC°C Voltage H 10 VOL - VSS TA = -40°C ut VDD - VOH p 0 u O 1 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.01 0.1 1 10 Power Supply Voltage (V) Output Current Magnitude (mA) FIGURE 2-13: Quiescent Current vs. FIGURE 2-16: Output Voltage Headroom Power Supply Voltage. vs. Output Current Magnitude. 120 0 6 90 op Gain (dB) 1068000 Phase Gain ---963000 op Phase (°) width Product MHz) 345 Gain Bandwidth Product VDDV =D D2 V=.2 D5VD. 5=V 5.5V 788505 Margin (°) Open-Lo 24000 ---111852000 Open-Lo Gain Band( 12 Phase Margin VDD = 2.2V 6750 Phase 0 60 -20 -210 0.1.E-011 11.E+00 11.E+010 101.E+020 11.E+03k 101.E+04k 101.E+050k 1M1.E+06 101.E+07M 1001.E+08M -50 -25 0 25 50 75 100 125 Frequency (Hz) Ambient Temperature (°C) FIGURE 2-14: Open-Loop Gain, Phase vs. FIGURE 2-17: Gain Bandwidth Product, Frequency. Phase Margin vs. Ambient Temperature. 10 4.5 age VDD = 5.5V 4.0 Falling EdgeF, aVlDliDn =g 5E.d5Vge, VDD = 2.2V olt s) 3.5 Output Vng (V)P-P 1 VDD = 2.2V Rate (V/µ 223...050 um Swi ew 1.5 Rising Edge, VDD = 5.5V xim Sl 1.0 Rising Edge, VDD = 2.2V a M 0.5 0.0 0.1 11.E+03k 101.E+04k 1001.E+05k 1M1.E+06 10M1.E+07 -50 -25 0 25 50 75 100 125 Frequency (Hz) Ambient Temperature (°C) FIGURE 2-15: Maximum Output Voltage FIGURE 2-18: Slew Rate vs. Ambient Swing vs. Frequency. Temperature.  2019 Microchip Technology Inc. DS20001811F-page 7

MCP6281/1R/2/3/4/5 TYPICAL PERFORMANCE CURVES (CONTINUED) Note: Unless otherwise indicated, T = +25°C, V = +2.2V to +6.0V, V = GND, V = V /2, V V /2, A DD SS CM DD OUT DD V = V /2, R = 10k to V , C = 60pF and CS is tied low. L DD L L L 1,000 30 y f = 1 kHz sity nsit 25 VDD = 5.0V n e e D Input Noise Voltage D(nV/Hz) 10100 Input Noise Voltage (nV/Hz) 11205005 1.E-01 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 0.1 1 10 100 1k 10k 100k 1M 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Frequency (Hz) Common Mode Input Voltage (V) FIGURE 2-19: Input Noise Voltage Density FIGURE 2-22: Input Noise Voltage Density vs. Frequency. vs. Common Mode Input Voltage at 1kHz. 35 n 140 Current 2350 eparatio 130 Ouptut Short Circuit (mA) 11205005 TTTTAAAA ==== + ++ 1-82245550°°°°CCCC Channel-to-Channel S(dB) 111012000 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1 10 100 Power Supply Voltage (V) Frequency (kHz) FIGURE 2-20: Output Short Circuit Current FIGURE 2-23: Channel-to-Channel vs. Power Supply Voltage. Separation vs. Frequency (MCP6282 and MCP6284 only). 1000 500 Op-Amp shuts off here 900 VDD = 5.5V 450 Quiescent Current (µA/Amplifier) 112233405050500000000 Op-AChmiSgp hs t wtuore nplostw on here HyClsoStwe s rtewos ehispigth Quiescent Current (µA/Amplifier) 234567800000000000000 CS swepthigh to low HCloySws st tewor eehspiigtsh 50 VDD = 2.2V 100 Op Amp toggles On/Off here 0 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Chip Select Voltage (V) Chip Select Voltage (V) FIGURE 2-21: Quiescent Current vs. FIGURE 2-24: Quiescent Current vs. Chip Select (CS) Voltage at V = 2.2V Chip Select (CS) Voltage at V = 5.5V DD DD (MCP6283 and MCP6285 only). (MCP6283 and MCP6285 only). DS20001811F-page 8  2019 Microchip Technology Inc.

MCP6281/1R/2/3/4/5 TYPICAL PERFORMANCE CURVES (CONTINUED) Note: Unless otherwise indicated, T = +25°C, V = +2.2V to +6.0V, V = GND, V = V /2, V V /2, A DD SS CM DD OUT DD V = V /2, R = 10k to V , C = 60pF and CS is tied low. L DD L L L 5.0 5.0 G = +1V/V G = -1V/V 4.5 VDD = 5.0V 4.5 VDD = 5.0V 4.0 4.0 age (V) 33..05 age (V) 33..05 olt 2.5 olt 2.5 V V ut 2.0 ut 2.0 p p ut 1.5 ut 1.5 O O 1.0 1.0 0.5 0.5 0.00.E+00 2.E-06 4.E-06 6.E-06 8.E-06 1.E-05 1.E-05 1.E-05 2.E-05 2.E-05 2.E-05 0.00.E+00 2.E-06 4.E-06 6.E-06 8.E-06 1.E-05 1.E-05 1.E-05 2.E-05 2.E-05 2.E-05 Time (2 µs/div) Time (2 µs/div) FIGURE 2-25: Large-Signal, Non-inverting FIGURE 2-28: Large-Signal, Inverting Pulse Response. Pulse Response. V/div) G = +1V/V mV/div) G = -1V/V 0 m 10 e (1 ge ( g a Output Volta Output Volt Time (500 ns/div) Time (500 ns/div) FIGURE 2-26: Small-Signal, Non-inverting FIGURE 2-29: Small-Signal, Inverting Pulse Response. Pulse Response. 2.5 6.0 oltages 2.0 CS Voltage VGVD I=DN =+= 1 2VV.S2/SVV oltages 455...505 CS Voltage VGVDI N=D = += V 15VS.S5/VV Output V(V) 1.5 VOUT Output On Output V(V) 334...050 VOUT Select, 1.0 Select, 122...505 Chip 0.5 Chip 01..50 Output High-Z Output On Output High-Z 0.0 0.0 0.E+00 5.E-06 1.E-05 2.E-05 2.E-05 3.E-05 3.E-05 4.E-05 4.E-05 5.E-05 5.E-05 0.0E+00 5.0E-06 1.0E-05 1.5E-05 Tim2.0E-05e (52.5E -05µs/d3.0Ei-05v) 3.5E-05 4.0E-05 4.5E-05 5.0E-05 Time (5 µs/div) FIGURE 2-27: Chip Select (CS) to FIGURE 2-30: Chip Select (CS) to Amplifier Output Response Time at VDD = 2.2V Amplifier Output Response Time at VDD = 5.5V (MCP6283 and MCP6285 only). (MCP6283 and MCP6285 only).  2019 Microchip Technology Inc. DS20001811F-page 9

MCP6281/1R/2/3/4/5 Note: Unless otherwise indicated, T = +25°C, V = +2.2V to +6.0V, V = GND, V = V /2, V V /2, A DD SS CM DD OUT DD V = V /2, R = 10k to V , C = 60pF and CS is tied low. L DD L L L 1.E1-00m2 6 A)1.E-10m3 VDD = 5.0V Magnitude (1111....11EEEE001----000001007654nµµµ Voltage (V) 345 VIN VOUT G = +2 V/V nt 1.E1-008n ut put Curre111...1EEE01---110001109pnp +++1-42820555°°°°CCCC put, Outp 12 n n 0 I1.E-112p I -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 -1 -15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 Input Voltage (V) Time (1 ms/div) FIGURE 2-31: Measured Input Current vs. FIGURE 2-32: The MCP6281/1R/2/3/4/5 Input Voltage (below V ). Show No Phase Reversal. SS DS20001811F-page 10  2019 Microchip Technology Inc.

MCP6281/1R/2/3/4/5 3.0 PIN DESCRIPTIONS Descriptions of the pins are listed in Table3-1 (single op amps) and Table3-2 (dual and quad op amps). TABLE 3-1: PIN FUNCTION TABLE FOR SINGLE OP AMPS MCP6281 MCP6281R MCP6283 PDIP, SOIC, PDIP, SOIC, Symbol Description SOT-23-5 SOT-23-5 SOT-23-6 MSOP MSOP 6 1 1 6 1 V Analog Output OUT 2 4 4 2 4 V – Inverting Input IN 3 3 3 3 3 V + Non-inverting Input IN 7 5 2 7 6 V Positive Power Supply DD 4 2 5 4 2 V Negative Power Supply SS — — — 8 5 CS Chip Select 1,5,8 — — 1,5 — NC No Internal Connection TABLE 3-2: PIN FUNCTION TABLE FOR DUAL AND QUAD OP AMPS MCP6282 MCP6284 MCP6285 Symbol Description PDIP, SOIC, MSOP PDIP, SOIC, TSSOP PDIP, SOIC, MSOP 1 1 — V Analog Output (op amp A) OUTA 2 2 2 V – Inverting Input (op amp A) INA 3 3 3 V + Non-inverting Input (op amp A) INA 8 4 8 V Positive Power Supply DD 5 5 — V + Non-inverting Input (op amp B) INB 6 6 6 V – Inverting Input (op amp B) INB 7 7 7 V Analog Output (op amp B) OUTB — 8 — V Analog Output (op amp C) OUTC — 9 — V – Inverting Input (op amp C) INC — 10 — V + Non-inverting Input (op amp C) INC 4 11 4 V Negative Power Supply SS — 12 — V + Non-inverting Input (op amp D) IND — 13 — V – Inverting Input (op amp D) IND — 14 — V Analog Output (op amp D) OUTD — — 1 V / Analog Output (op amp A)/Non- OUTA V + inverting Input (op amp B) INB — — 5 CS Chip Select 3.1 Analog Outputs 3.4 Chip Select Digital Input (CS) The output pins are low-impedance voltage sources. This is a CMOS, Schmitt-triggered input that places the part into a low-power mode of operation. 3.2 Analog Inputs 3.5 Power Supply Pins The non-inverting and inverting inputs are high- The positive power supply (V ) is 2.2V to 6.0V higher impedance CMOS inputs with low bias currents. DD than the negative power supply (V ). For normal SS operation, the other pins are between V and V . SS DD 3.3 MCP6285’s V /V + Pin OUTA INB Typically, these parts are used in a single (positive) For the MCP6285 only, the output of op amp A is supply configuration. In this case, V is connected to SS connected directly to the non-inverting input of ground and VDD is connected to the supply. VDD will opampB; this is the V /V + pin. This connection need bypass capacitors. OUTA INB makes it possible to provide a Chip Select pin for duals in 8-pin packages.  2019 Microchip Technology Inc. DS20001811F-page 11

MCP6281/1R/2/3/4/5 4.0 APPLICATION INFORMATION V , and dump any currents onto V . When DD DD implemented as shown, resistors R and R also limit 1 2 The MCP6281/1R/2/3/4/5 family of op amps is manu- the current through D and D . 1 2 factured using Microchip's state-of-the-art CMOS process. This family is specifically designed for low- V cost, low-power and general purpose applications. DD The low supply voltage, low quiescent current and wide bandwidth makes the MCP6281/1R/2/3/4/5 ideal D D for battery-powered applications. 1 2 V 1 + 4.1 Rail-to-Rail Inputs R 1 MCP628X – V 4.1.1 PHASE REVERSAL 2 R 2 The MCP6281/1R/2/3/4/5 op amp is designed to prevent phase reversal when the input pins exceed the R supply voltages. Figure2-32 shows the input voltage 3 exceeding the supply voltage without any phase V –(minimum expected V ) SS 1 R > reversal. 1 2mA V –(minimum expected V ) 4.1.2 INPUT VOLTAGE AND CURRENT R > SS 2 2 2mA LIMITS FIGURE 4-2: Protecting the Analog The ESD protection on the inputs can be depicted as shown in Figure4-1. This structure was chosen to Inputs. protect the input transistors, and to minimize input bias It is also possible to connect the diodes to the left of current (I ). The input ESD diodes clamp the inputs B resistors R and R . In this case, current through the 1 2 when they try to go more than one diode drop below diodes D and D needs to be limited by some other 1 2 V . They also clamp any voltages that go too far SS mechanism. The resistors then serve as in-rush current above V ; their breakdown voltage is high enough to DD limiters; the DC current into the input pins (V + and IN allow normal operation, and low enough to bypass V –) should be very small. IN quick ESD events within the specified limits. A significant amount of current can flow out of the inputs when the common mode voltage (V ) is below CM Bond ground (VSS); see Figure2-31. Applications that are V DD Pad high impedance may need to limit the usable voltage range. 4.1.3 NORMAL OPERATION Bond Input Bond VIN+ Pad Stage Pad VIN– The input stage of the MCP6281/1R/2/3/4/5 op amps use two differential CMOS input stages in parallel. One operates at low common mode input voltage (V ), CM while the other operates at high V . With this CM VSS Bond topology, the device operates with VCM up to 0.3V Pad above V and 0.3V below V . DD SS There is a transition in input behavior as V is FIGURE 4-1: Simplified Analog Input ESD CM changed. It occurs when V is near V –1.2V (see Structures. CM DD Figure2-3 and Figure2-6). For the best distortion In order to prevent damage and/or improper operation performance with non-inverting gains, avoid these of these op amps, the circuit they are in must limit the regions of operation. currents and voltages at the V + and V – pins (see IN IN Absolute Maximum Ratings † at the beginning of Section1.0 “Electrical Characteristics”). Figure4-2 shows the recommended approach to protecting these inputs. The internal ESD diodes prevent the input pins (V + and V –) from going too far below ground, and IN IN the resistors R and R limit the possible current drawn 1 2 out of the input pins. Diodes D and D prevent the 1 2 input pins (V + and V –) from going too far above IN IN DS20001811F-page 12  2019 Microchip Technology Inc.

MCP6281/1R/2/3/4/5 4.2 Rail-to-Rail Output After selecting R for your circuit, double-check the ISO resulting frequency response peaking and step The output voltage range of the MCP6281/1R/2/3/4/5 response overshoot. Modify R 's value until the ISO op amp is VDD–15mV (min.) and VSS+15mV (max.) response is reasonable. Bench evaluation and simula- when RL=10k is connected to VDD/2 and tions with the MCP6281/1R/2/3/4/5 SPICE macro VDD=5.5V. Refer to Figure2-16 for more information. model are helpful. 4.3 Capacitive Loads 4.4 MCP628X Chip Select (CS) Driving large capacitive loads can cause stability The MCP6283 and MCP6285 are single and dual op problems for voltage feedback op amps. As the load amps with Chip Select (CS), respectively. When CS is capacitance increases, the feedback loop’s phase pulled high, the supply current drops to 0.7µA (typical) margin decreases and the closed-loop bandwidth is and flows through the CS pin to V . When this hap- SS reduced. This produces gain peaking in the frequency pens, the amplifier output is put into a high-impedance response, with overshoot and ringing in the step state. By pulling CS low, the amplifier is enabled. The response. A unity-gain buffer (G = +1) is the most CS pin has an internal 5M (typical) pull-down resistor sensitive to capacitive loads, though all gains show the connected to V , so it will go low if the CS pin is left SS same general behavior. floating. Figure1-1 shows the output voltage and When driving large capacitive loads with these op supply current response to a CS pulse. amps (e.g., > 100pF when G = +1), a small series resistor at the output (R in Figure4-3) improves the 4.5 Cascaded Dual Op Amps ISO feedback loop’s phase margin (stability) by making the (MCP6285) output load resistive at higher frequencies. The bandwidth will generally be lower than the bandwidth The MCP6285 is a dual op amp with Chip Select (CS). with no capacitive load. The Chip Select input is available on what would be the non-inverting input of a standard dual op amp (pin 5). This pin is available because the output of op amp A connects to the non-inverting input of op amp B, as – shown in Figure4-5. The Chip Select input, which can R ISO be connected to a microcontroller I/O line, puts the MCP628X V OUT device in Low-power mode. Refer to Section4.4 + V IN C “MCP628X Chip Select (CS)”. L VOUTA/VINB+ VINB– FIGURE 4-3: Output Resistor, R ISO 1 6 stabilizes large capacitive loads. 2 – Figure4-4 gives recommended RISO values for differ- VINA– – B 7 VOUTB ent capacitive loads and gains. The x-axis is the A + 3 normalized load capacitance (C /G ), where G is the V + + L N N INA circuit's noise gain. For non-inverting gains, G and the MCP6285 N Signal Gain are equal. For inverting gains, G is N 1+|Signal Gain| (e.g., -1V/V gives G = +2V/V). N 5 CS 1,000 FIGURE 4-5: Cascaded Gain Amplifier. )(cid:58) (O The output of op amp A is loaded by the input imped- RIS ance of op amp B, which is typically 1013||6pF, as d de 100 specified in the DC specification table (Refer to en Section4.3 “Capacitive Loads” for further details m G = 1 V/V m N regarding capacitive loads). o G = 2 V/V c N Re GN (cid:116) 4 V/V The common mode input range of these op amps is 10 specified in the data sheet as VSS–300mV and 10 100 1,000 10,000 VDD+300mV. However, since the output of op amp A Normalized Load Capacitance; CL / GN (pF) is limited to VOL and VOH (20mV from the rails with a 10k load), the non-inverting input range of op amp B FIGURE 4-4: Recommended RISO Values is limited to the common mode input range of for Capacitive Loads. V +20mV and V –20mV. SS DD  2019 Microchip Technology Inc. DS20001811F-page 13

MCP6281/1R/2/3/4/5 4.6 Supply Bypass V – V + IN IN V With this family of operational amplifiers, the power SS supply pin (V for single-supply) should have a local DD bypass capacitor (i.e., 0.01µF to 0.1µF) within 2mm for good, high-frequency performance. It also needs a bulk capacitor (i.e., 1µF or larger) within 100mm to provide large, slow currents. This bulk capacitor can be shared with nearby analog parts. 4.7 Unused Op Amps Guard Ring An unused op amp in a quad package (MCP6284) FIGURE 4-7: Example Guard Ring Layout should be configured as shown in Figure4-6. These for Inverting Gain. circuits prevent the output from toggling and causing 1. For Inverting Gain and Transimpedance crosstalk. Circuits A sets the op amp at its minimum Amplifiers (convert current to voltage, such as noise gain. The resistor divider produces any desired photo detectors): reference voltage within the output voltage range of the op amp; the op amp buffers that reference voltage. a.Connect the guard ring to the non-inverting Circuit B uses the minimum number of components input pin (VIN+). This biases the guard ring and operates as a comparator, but it may draw more to the same reference voltage as the op current. amp (e.g., VDD/2 or ground). b.Connect the inverting pin (V –) to the input IN with a wire that does not touch the PCB ¼ MCP6284 (A) ¼ MCP6284 (B) surface. V V DD DD 2. Non-inverting Gain and Unity-Gain Buffer: a.Connect the non-inverting pin (V +) to the V IN R1 DD input with a wire that does not touch the PCB surface. V R REF b.Connect the guard ring to the inverting input 2 pin (V –). This biases the guard ring to the IN common mode input voltage. R V = V -----------2------- REF DD R +R 1 2 FIGURE 4-6: Unused Op Amps. 4.8 PCB Surface Leakage In applications where low input bias current is critical, Printed Circuit Board (PCB) surface-leakage effects need to be considered. Surface leakage is caused by humidity, dust or other contamination on the board. Under low humidity conditions, a typical resistance between nearby traces is 1012. A 5V difference would cause 5pA of current to flow, which is greater than the MCP6281/1R/2/3/4/5 family’s bias current at +25°C (1pA, typical). The easiest way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). The guard ring is biased at the same voltage as the sensitive pin. An example of this type of layout is shown in Figure4-7. DS20001811F-page 14  2019 Microchip Technology Inc.

MCP6281/1R/2/3/4/5 4.9 Application Circuits 4.9.3 CASCADED OP AMP APPLICATIONS 4.9.1 SALLEN-KEY HIGH-PASS FILTER The MCP6285 provides the flexibility of Low-power The MCP6281/1R/2/3/4/5 op amps can be used in mode for dual op amps in an 8-pin package. The active-filter applications. Figure4-8 shows a second- MCP6285 eliminates the added cost and space in order Sallen-Key high-pass filter with a gain of 1. The battery-powered applications by using two single op output bias voltage is set by the VDD/2 reference, which amps with Chip Select lines or a 10-pin device with one can be changed to any voltage within the output voltage Chip Select line for both op amps. Since the two op range. amps are internally cascaded, this device cannot be used in circuits that require active or passive elements between the two op amps. However, there are several applications where this op amp configuration with ChipSelect line becomes suitable. The circuits below R 1 show possible applications for this device. V + IN 4.9.3.1 Load Isolation C C 1 2 MCP6281 VOUT With the cascaded op amp configuration, op amp B can – R 2 be used to isolate the load from op amp A. In applica- tions where op amp A is driving capacitive or low resis- VDD/2 tance loads in the feedback loop (such as an integrator circuit or filter circuit), the op amp may not have sufficient source current to drive the load. In this case, FIGURE 4-8: Sallen-Key High-Pass Filter. op amp B can be used as a buffer. This filter, and others, can be designed using Microchip’s Design Aids; see Section5.2 “FilterLab® Software” and Section5.3 “Mindi™ Circuit Designer & Simulator”. – – B VOUTB 4.9.2 INVERTING MILLER INTEGRATOR A + + Load Analog integrators are used in filters, control loops and MCP6285 measurement circuits. Figure4-9 shows the most common implementation, the inverting Miller integrator. CS The non-inverting input is at V /2 so that the op amp DD properly biases up. The switch (SW) is used to zero the FIGURE 4-10: Isolating the Load with a output in some applications. Other applications use a feedback loop to keep the output within its linear range Buffer. of operation. 4.9.3.2 Cascaded Gain Figure4-11 shows a cascaded gain circuit configura- SW tion with Chip Select. Op amps A and B are configured in a non-inverting amplifier configuration. In this R C configuration, it is important to note that the input offset VIN VOUT voltage of op amp A is amplified by the gain of opampA and B, as shown below: + MCP6281 V = V G G +V G G +V G – OUT IN A B OSA A B OSB B V /2 DD Where: V OUT 1 = VIN sRC GA = op amp A gain G = op amp B gain B FIGURE 4-9: Miller Integrator. V = op amp A input offset voltage OSA V = op amp B input offset voltage OSB Therefore, it is recommended to set most of the gain with op amp A and use op amp B with relatively small gain (e.g., a unity-gain buffer).  2019 Microchip Technology Inc. DS20001811F-page 15

MCP6281/1R/2/3/4/5 R4 R3 R2 R1 R2 C2 RF – – B VOUT – V R1 +A + – B VOUT IN MCP6285 A + VIN + MCP6285 C1 CS R C =R R C 1 1 2 F 2 CS FIGURE 4-13: Buffered Non-inverting FIGURE 4-11: Cascaded Gain Circuit Integrator with Chip Select. Configuration. 4.9.3.5 Inverting Integrator with Active 4.9.3.3 Difference Amplifier Compensation and Chip Select Figure4-12 shows op amp A configured as a difference Figure4-14 uses an active compensator (op amp B) to amplifier with Chip Select. In this configuration, it is compensate for the non-ideal op amp characteristics recommended to use well-matched resistors (e.g., introduced at higher frequencies. This circuit uses 0.1%) to increase the Common Mode Rejection Ratio opamp B as a unity-gain buffer to isolate the integration (CMRR). Op amp B can be used to provide additional capacitor C from op amp A and drives the capacitor gain and isolate the load from the difference amplifier. 1 with low-impedance source. Since both op amps are matched very well, they provide a higher quality R R integrator. 4 3 R R 2 1 V IN2 – R1 C1 – B VOUT VIN R2 A + V + B IN1 MCP6285 + – R 1 – A VOUT + CS MCP6285 FIGURE 4-12: Difference Amplifier Circuit. CS 4.9.3.4 Buffered Non-inverting Integrator Figure4-13 shows a lossy non-inverting integrator that FIGURE 4-14: Integrator Circuit with Active is buffered and has a Chip Select input. Op amp A is Compensation. configured as a non-inverting integrator. In this config- uration, matching the impedance at each input is 4.9.3.6 Second-Order MFB Low-Pass Filter recommended. RF is used to provide a feedback loop with an Extra Pole-Zero Pair at frequencies << 1/(2R C ) and makes this a lossy 1 1 Figure4-15 is a second-order multiple feedback low- integrator (it has a finite gain at DC). Op amp B is used pass filter with Chip Select. Use the FilterLab® software to isolate the load from the integrator. from Microchip to determine the R and C values for the op amp A’s second-order filter. Op amp B can be used to add a pole-zero pair using C , R , and R . 3 6 7 DS20001811F-page 16  2019 Microchip Technology Inc.

MCP6281/1R/2/3/4/5 4.9.3.8 Capacitorless Second-Order R R6 C3 Low-Pass filter with Chip Select 1 The low-pass filter shown in Figure4-17 does not C1 require external capacitors and uses only three exter- R R R 7 nal resistors; the op amp's GBWP sets the corner 3 2 – VIN –A +B VOUT farnedq uRen cisy .u Rse1 da tnod sRe2t tahree Qu.s eTod atov osiedt gthaein cpirecaukiti ngga iinn C2 RR5 + MCP6285 the fre3quency response, Q needs to be low (lower 4 values need to be selected for R ). Note that the ampli- 3 fier bandwidth varies greatly over temperature and CS process. However, this configuration provides a low- cost solution for applications with high bandwidth FIGURE 4-15: Second-Order Multiple requirements. Feedback Low-Pass Filter with an Extra Pole-Zero Pair. R R 2 1 4.9.3.7 Second-Order Sallen-Key Low-Pass VIN Filter with an Extra Pole-Zero Pair R 3 Figure4-16 is a second-order Sallen-Key low-pass – filter with Chip Select. Use the FilterLab® software from +A +B VOUT Microchip to determine the R and C values for the op V – REF amp A’s second-order filter. Op amp B can be used to MCP6285 add a pole-zero pair using C , R and R . 3 5 6 CS R2 R1 R5 C3 FIGURE 4-17: Capacitorless Second-Order Low-Pass Filter with Chip Select. R – 6 R4 R3 –A +B VOUT V + IN MCP6285 C 1 C 2 CS FIGURE 4-16: Second-Order Sallen-Key Low-Pass Filter with an Extra Pole-Zero Pair and Chip Select.  2019 Microchip Technology Inc. DS20001811F-page 17

MCP6281/1R/2/3/4/5 5.0 DESIGN AIDS 5.5 Analog Demonstration and Evaluation Boards Microchip provides the basic design tools needed for the MCP6281/1R/2/3/4/5 family of op amps. Microchip offers a broad spectrum of Analog Demon- stration and Evaluation Boards that are designed to 5.1 SPICE Macro Model help you achieve faster time to market. For a complete listing of these boards and their corresponding user’s The latest SPICE macro model for the MCP6281/1R/2/ guides and technical information, visit the Microchip 3/4/5 op amps is available on the Microchip web site at web site at www.microchip.com/analogtools. www.microchip.com. This model is intended to be an Two of our boards that are especially useful are: initial design tool that works well in the op amp’s linear region of operation over the temperature range. See • P/N SOIC8EV: 8-Pin SOIC/MSOP/TSSOP/DIP the model file for information on its capabilities. Evaluation Board Bench testing is a very important part of any design and • P/N SOIC14EV: 14-Pin SOIC/TSSOP/DIP cannot be replaced with simulations. Also, simulation Evaluation Board results using this macro model need to be validated by comparing them to the data sheet specifications and 5.6 Application Notes characteristic curves. The following Microchip Application Notes are avail- 5.2 FilterLab® Software able on the Microchip web site at www.microchip. com/ appnotes and are recommended as supplemental ref- Microchip’s FilterLab® software is an innovative erence resources. software tool that simplifies analog active filter (using ADN003: “Select the Right Operational Amplifier for op amps) design. Available at no cost from the your Filtering Circuits,” DS21821 Microchip web site at www.microchip.com/filterlab, the AN722: “Operational Amplifier Topologies and DC FilterLab design tool provides full schematic diagrams Specifications,” DS00722 of the filter circuit with component values. It also outputs the filter circuit in SPICE format, which can be AN723: “Operational Amplifier AC Specifications and used with the macro model to simulate actual filter Applications,” DS00723 performance. AN884: “Driving Capacitive Loads With Op Amps,” DS00884 5.3 Mindi™ Circuit Designer & AN990: “Analog Sensor Conditioning Circuits–An Simulator Overview,” DS00990 Microchip’s Mindi™ Circuit Designer & Simulator aids These application notes and others are listed in the in the design of various circuits useful for active filter, design guide: amplifier and power-management applications. It is a “Signal Chain Design Guide,” DS21825 free online circuit designer & simulator available from the Microchip web site at www.microchip.com/mindi. This interactive circuit designer & simulator enables designers to quickly generate circuit diagrams, simu- late circuits. Circuits developed using the Mindi Circuit Designer & Simulator can be downloaded to a personal computer or workstation. 5.4 MAPS (Microchip Advanced Part Selector) MAPS is a software tool that helps semiconductor professionals efficiently identify Microchip devices that fit a particular design requirement. Available at no cost from the Microchip web site at www.microchip.com/ maps, the MAPS is an overall selection tool for Microchip’s product portfolio that includes Analog, Memory, MCUs and DSCs. Using this tool you can define a filter to sort features for a parametric search of devices and export side-by-side technical comparison reports. Helpful links are also provided for Data sheets, Purchase, and Sampling of Microchip parts. DS20001811F-page 18  2019 Microchip Technology Inc.

MCP6281/1R/2/3/4/5 6.0 PACKAGING INFORMATION 6.1 Package Marking Information 5-Lead SOT-23 (MCP6281 and MCP6281R) Example: Device Code XXNN MCP6281 CHNN CH25 MCP6281R EUNN Note: Applies to 5-Lead SOT-23. 6-Lead SOT-23 (MCP6283) Example: XXNN CL25 8-Lead MSOP Example: 6281E 722256 8-Lead PDIP (300 mil) Example: XXXXXXXX MCP6281 MCP6281 XXXXXNNN E/P256 OR E/P e 3 256 YYWW 0722 0722 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2019 Microchip Technology Inc. DS20001811F-page 19

MCP6281/1R/2/3/4/5 Package Marking Information (Continued) 8-Lead SOIC (150 mil) Example: XXXXXXXX MCP6281 MCP6281E XXXXYYWW E/SN0722 OR SN e3 0722 NNN 256 256 14-Lead PDIP (300 mil) (MCP6284) Example: XXXXXXXXXXXXXX MCP6284-E/P XXXXXXXXXXXXXX YYWWNNN 0722256 MCP6284 OR E/Pe3 0722256 14-Lead SOIC (150 mil) (MCP6284) Example: XXXXXXXXXX MCP6284ESL XXXXXXXXXX YYWWNNN 0722256 MCP6284 OR E/SL^e^3 0722256 14-Lead TSSOP (MCP6284) Example: XXXXXX 6284EST YYWW 0437 NNN 256 DS20001811F-page 20  2019 Microchip Technology Inc.

MCP6281/1R/2/3/4/5 5-Lead Plastic Small Outline Transistor (OT) [SOT23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 0.20 C 2X D e1 A D N E/2 E1/2 E1 E (DATUM D) (DATUM A-B) 0.15 C D 2X NOTE 1 1 2 e B NX b 0.20 C A-B D TOP VIEW A A2 A 0.20 C SEATING PLANE A SEE SHEET 2 A1 C SIDE VIEW Microchip Technology Drawing C04-091-OT Rev E Sheet 1 of 2  2019 Microchip Technology Inc. DS20001811F-page 21

MCP6281/1R/2/3/4/5 5-Lead Plastic Small Outline Transistor (OT) [SOT23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging c (cid:84) L L1 VIEW A-A SHEET 1 Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 5 Pitch e 0.95 BSC Outside lead pitch e1 1.90 BSC Overall Height A 0.90 - 1.45 Molded Package Thickness A2 0.89 - 1.30 Standoff A1 - - 0.15 Overall Width E 2.80 BSC Molded Package Width E1 1.60 BSC Overall Length D 2.90 BSC Foot Length L 0.30 - 0.60 Footprint L1 0.60 REF Foot Angle (cid:73) 0° - 10° Lead Thickness c 0.08 - 0.26 Lead Width b 0.20 - 0.51 Notes: 1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25mm per side. 2. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-091-OT Rev E Sheet 2 of 2 DS20001811F-page 22  2019 Microchip Technology Inc.

MCP6281/1R/2/3/4/5 5-Lead Plastic Small Outline Transistor (OT) [SOT23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging X SILK SCREEN 5 Y Z C G 1 2 E GX RECOMMENDED LAND PATTERN Units MILLIMETERS Dimension Limits MIN NOM MAX Contact Pitch E 0.95 BSC Contact Pad Spacing C 2.80 Contact Pad Width (X5) X 0.60 Contact Pad Length (X5) Y 1.10 Distance Between Pads G 1.70 Distance Between Pads GX 0.35 Overall Width Z 3.90 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-2091B [OT]  2019 Microchip Technology Inc. DS20001811F-page 23

MCP6281/1R/2/3/4/5 6-Lead Plastic Small Outline Transistor (CH, CHY) [SOT-23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2X 0.15 C A-B D e1 A D E 2 E1 E E1 2 2X 0.15 C D 2X 0.20 C A-B e B 6X b 0.20 C A-B D TOP VIEW A2 A C SEATING PLANE 6X A1 0.10 C SIDE VIEW R1 R L2 c GAUGE PLANE L (cid:300) (L1) END VIEW Microchip Technology Drawing C04-028C (CH) Sheet 1 of 2 DS20001811F-page 24  2019 Microchip Technology Inc.

MCP6281/1R/2/3/4/5 6-Lead Plastic Small Outline Transistor (CH, CHY) [SOT-23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Leads N 6 Pitch e 0.95 BSC Outside lead pitch e1 1.90 BSC Overall Height A 0.90 - 1.45 Molded Package Thickness A2 0.89 1.15 1.30 Standoff A1 0.00 - 0.15 Overall Width E 2.80 BSC Molded Package Width E1 1.60 BSC Overall Length D 2.90 BSC Foot Length L 0.30 0.45 0.60 Footprint L1 0.60 REF Seating Plane to Gauge Plane L1 0.25 BSC Foot Angle φ 0° - 10° Lead Thickness c 0.08 - 0.26 Lead Width b 0.20 - 0.51 Notes: 1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25mm per side. 2. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-028C (CH) Sheet 2 of 2  2019 Microchip Technology Inc. DS20001811F-page 25

MCP6281/1R/2/3/4/5 6-Lead Plastic Small Outline Transistor (CH, CHY) [SOT-23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging GX Y Z C G G SILK SCREEN X E RECOMMENDED LAND PATTERN Units MILLIMETERS Dimension Limits MIN NOM MAX Contact Pitch E 0.95 BSC Contact Pad Spacing C 2.80 Contact Pad Width (X3) X 0.60 Contact Pad Length (X3) Y 1.10 Distance Between Pads G 1.70 Distance Between Pads GX 0.35 Overall Width Z 3.90 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-2028B (CH) DS20001811F-page 26  2019 Microchip Technology Inc.

MCP6281/1R/2/3/4/5 Note: For the mostcurrent package drawings,please seetheMicrochip Packaging Specification located at http://www.microchip.com/packaging  2019 Microchip Technology Inc. DS20001811F-page 27

MCP6281/1R/2/3/4/5 Note: For the mostcurrent package drawings,please seetheMicrochip Packaging Specification located at http://www.microchip.com/packaging DS20001811F-page 28  2019 Microchip Technology Inc.

MCP6281/1R/2/3/4/5 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2019 Microchip Technology Inc. DS20001811F-page 29

MCP6281/1R/2/3/4/5 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A N B E1 NOTE 1 1 2 TOP VIEW E C A A2 PLANE L c A1 e eB 8X b1 8X b .010 C SIDE VIEW END VIEW Microchip Technology Drawing No. C04-018-P Rev E Sheet 1 of 2 DS20001811F-page 30  2019 Microchip Technology Inc.

MCP6281/1R/2/3/4/5 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging ALTERNATE LEAD DESIGN (NOTE 5) DATUM A DATUM A b b e e 2 2 e e Units INCHES Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e .100 BSC Top to Seating Plane A - - .210 Molded Package Thickness A2 .115 .130 .195 Base to Seating Plane A1 .015 - - Shoulder to Shoulder Width E .290 .310 .325 Molded Package Width E1 .240 .250 .280 Overall Length D .348 .365 .400 Tip to Seating Plane L .115 .130 .150 Lead Thickness c .008 .010 .015 Upper Lead Width b1 .040 .060 .070 Lower Lead Width b .014 .018 .022 Overall Row Spacing § eB - - .430 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. 5. Lead design above seating plane may vary, based on assembly vendor. Microchip Technology Drawing No. C04-018-P Rev E Sheet 2 of 2  2019 Microchip Technology Inc. DS20001811F-page 31

MCP6281/1R/2/3/4/5 14-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 2 3 D E A A2 L c A1 b1 b e eB Units INCHES Dimension Limits MIN NOM MAX Number of Pins N 14 Pitch e .100 BSC Top to Seating Plane A – – .210 Molded Package Thickness A2 .115 .130 .195 Base to Seating Plane A1 .015 – – Shoulder to Shoulder Width E .290 .310 .325 Molded Package Width E1 .240 .250 .280 Overall Length D .735 .750 .775 Tip to Seating Plane L .115 .130 .150 Lead Thickness c .008 .010 .015 Upper Lead Width b1 .045 .060 .070 Lower Lead Width b .014 .018 .022 Overall Row Spacing § eB – – .430 Notes: 1. Pin 1 visual index feature may vary, but must be located with the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. MicrochipTechnologyDrawingC04-005B DS20001811F-page 32  2019 Microchip Technology Inc.

MCP6281/1R/2/3/4/5 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2X 0.10 C A–B D A D NOTE 5 N E 2 E1 2 E1 E NOTE 1 1 2 e NX b B 0.25 C A–B D NOTE 5 TOP VIEW 0.10 C C A A2 SEATING PLANE 8X 0.10 C A1 SIDE VIEW h R0.13 h R0.13 H 0.23 L SEE VIEW C (L1) VIEW A–A VIEW C Microchip Technology Drawing No. C04-057-SN Rev E Sheet 1 of 2  2019 Microchip Technology Inc. DS20001811F-page 33

MCP6281/1R/2/3/4/5 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e 1.27 BSC Overall Height A - - 1.75 Molded Package Thickness A2 1.25 - - Standoff § A1 0.10 - 0.25 Overall Width E 6.00 BSC Molded Package Width E1 3.90 BSC Overall Length D 4.90 BSC Chamfer (Optional) h 0.25 - 0.50 Foot Length L 0.40 - 1.27 Footprint L1 1.04 REF Foot Angle 0° - 8° Lead Thickness c 0.17 - 0.25 Lead Width b 0.31 - 0.51 Mold Draft Angle Top 5° - 15° Mold Draft Angle Bottom 5° - 15° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. 5. Datums A & B to be determined at Datum H. Microchip Technology Drawing No. C04-057-SN Rev E Sheet 2 of 2 DS20001811F-page 34  2019 Microchip Technology Inc.

MCP6281/1R/2/3/4/5 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging SILK SCREEN C Y1 X1 E RECOMMENDED LAND PATTERN Units MILLIMETERS Dimension Limits MIN NOM MAX Contact Pitch E 1.27 BSC Contact Pad Spacing C 5.40 Contact Pad Width (X8) X1 0.60 Contact Pad Length (X8) Y1 1.55 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-2057-SN Rev E  2019 Microchip Technology Inc. DS20001811F-page 35

MCP6281/1R/2/3/4/5 14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2X 0.10 C A–B D A NOTE 5 D N E 2 E2 2 E1 E 2X 0.10 C D 2X N/2 TIPS NOTE 1 1 2 3 0.20 C e NX b B NOTE 5 0.25 C A–B D TOP VIEW 0.10 C C A A2 SEATING PLANE 14X A1 SIDE VIEW 0.10 C h h H R0.13 R0.13 c SEE VIEW C L VIEW A–A (L1) VIEW C Microchip Technology Drawing No. C04-065-SL Rev D Sheet 1 of 2 DS20001811F-page 36  2019 Microchip Technology Inc.

MCP6281/1R/2/3/4/5 14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 14 Pitch e 1.27 BSC Overall Height A - - 1.75 Molded Package Thickness A2 1.25 - - Standoff § A1 0.10 - 0.25 Overall Width E 6.00 BSC Molded Package Width E1 3.90 BSC Overall Length D 8.65 BSC Chamfer (Optional) h 0.25 - 0.50 Foot Length L 0.40 - 1.27 Footprint L1 1.04 REF Lead Angle 0° - - Foot Angle 0° - 8° Lead Thickness c 0.10 - 0.25 Lead Width b 0.31 - 0.51 Mold Draft Angle Top 5° - 15° Mold Draft Angle Bottom 5° - 15° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimension D does not include mold flash, protrusions or gate burrs, which shall not exceed 0.15 mm per end. Dimension E1 does not include interlead flash or protrusion, which shall not exceed 0.25 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. 5. Datums A & B to be determined at Datum H. Microchip Technology Drawing No. C04-065-SL Rev D Sheet 2 of 2  2019 Microchip Technology Inc. DS20001811F-page 37

MCP6281/1R/2/3/4/5 14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 14 SILK SCREEN C Y 1 2 X E RECOMMENDED LAND PATTERN Units MILLIMETERS Dimension Limits MIN NOM MAX Contact Pitch E 1.27 BSC Contact Pad Spacing C 5.40 Contact Pad Width (X14) X 0.60 Contact Pad Length (X14) Y 1.55 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-2065-SL Rev D DS20001811F-page 38  2019 Microchip Technology Inc.

MCP6281/1R/2/3/4/5 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2019 Microchip Technology Inc. DS20001811F-page 39

MCP6281/1R/2/3/4/5 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20001811F-page 40  2019 Microchip Technology Inc.

MCP6281/1R/2/3/4/5 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2019 Microchip Technology Inc. DS20001811F-page 41

MCP6281/1R/2/3/4/5 NOTES: DS20001811F-page 42  2019 Microchip Technology Inc.

MCP6281/1R/2/3/4/5 APPENDIX A: REVISION HISTORY Revision A (June 2003) • Original data sheet release. Revision F (December 2019) The following is the list of modifications: 1. Updated Section6.0 “Packaging Informa- tion”. Revision E (February 2008) The following is the list of modifications: 1. Updated notes to Section1.0 “Electrical Char- acteristics”. 2. Increased absolute maximum voltage range of input pins. Increased maximum operating supply voltage (V ). DD 3. Added Section1.1 “Test Circuits”. 4. Added Figure2-32. 5. Updated Table3-1 and Table3-2 in Section3.0 “Pin Descriptions”. 6. Added Section4.1.1 “Phase Reversal”, Section4.1.2 “Input Voltage and Current Limits”, and Section4.1.3 “Normal Opera- tion”. 7. Added Section4.7 “Unused Op Amps”. 8. Updated Section5.0 “Design AIDS”. 9. Updated package outline drawings in Section6.0 “Packaging Information”. Revision D (December 2004) The following is the list of modifications: 1. Added SOT-23-5 packages for the MCP6281 and MCP6281R single op amps. 2. Added SOT-23-6 package for the MCP6283 single op amp. 3. Added Section3.0 “Pin Descriptions”. 4. Corrected application circuits (Section4.9 “Application Circuits”). 5. Added SOT-23-5 and SOT-23-6 packages and corrected package marking information (Section6.0 “Packaging Information”). 6. Added Appendix A: Revision History. Revision C (June 2004) The following is the list of modifications: 1. Undocumented changes. Revision B (October 2003) The following is the list of modifications: 1. Undocumented changes.  2019 Microchip Technology Inc. DS20001811F-page 43

MCP6281/1R/2/3/4/5 NOTES: DS20001811F-page 44  2019 Microchip Technology Inc.

MCP6281/1R/2/3/4/5 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. – X /XX Examples: a) MCP6281-E/SN: Extended Temperature, Device Temperature Package 8LD SOIC package. Range b) MCP6281-E/MS: Extended Temperature, 8LD MSOP package. c) MCP6281-E/P: Extended Temperature, Device: MCP6281: Single Op Amp 8LD PDIP package. MCP6281T: Single Op Amp d) MCP6281T-E/OT: Tape and Reel, (Tape and Reel) Extended Temperature, (SOIC, MSOP, SOT-23-5) 5LD SOT-23 package. MCP6281RT: Single Op Amp e) MCP6281RT-E/OT: Tape and Reel, (Tape and Reel) (SOT-23-5) Extended Temperature, MCP6282: Dual Op Amp 5LD SOT-23 package. MCP6282T: Dual Op Amp a) MCP6282-E/SN: Extended Temperature, (Tape and Reel) (SOIC, MSOP) 8LD SOIC package. MCP6283: Single Op Amp with CS b) MCP6282-E/MS: Extended Temperature, MCP6283T: Single Op Amp with CS 8LD MSOP package. (Tape and Reel) c) MCP6282-E/P: Extended Temperature, (SOIC, MSOP, SOT-23-6) 8LD PDIP package. MCP6284: Quad Op Amp d) MCP6282T-E/SN: Tape and Reel, MCP6284T: Quad Op Amp Extended Temperature, (Tape and Reel) (SOIC, TSSOP) 8LD SOIC package. MCP6285: Dual Op Amp with CS MCP6285T: Dual Op Amp with CS a) MCP6283-E/SN: Extended Temperature, (Tape and Reel) (SOIC, MSOP) 8LD SOIC package. b) MCP6283-E/MS: Extended Temperature, 8LD MSOP package. Temperature Range: E = -40°C to +125°C c) MCP6283-E/P: Extended Temperature, 8LD PDIP package. d) MCP6283T-E/CH: Tape and Reel, Package: CH = Plastic Small Outline Transistor (SOT-23), 6-lead Extended Temperature, (MCP6283 only) 6LD SOT-23 package. MS = Plastic MSOP, 8-lead a) MCP6284-E/P: Extended Temperature, P = Plastic DIP (300 mil body), 8-lead, 14-lead 14LD PDIP package. OT = Plastic Small Outline Transistor (SOT-23), 5-lead b) MCP6284T-E/SL: Tape and Reel, (MCP6281, MCP6281R only) Extended Temperature, SL = Plastic SOIC (3.90mm body), 14-lead 14LD SOIC package. SN = Plastic SOIC, (3.90mm body), 8-lead c) MCP6284-E/SL: Extended Temperature, ST = Plastic TSSOP (4.4mm body), 14-lead 14LD SOIC package. d) MCP6284-E/ST: Extended Temperature, 14LD TSSOP package. a) MCP6285-E/SN: Extended Temperature, 8LD SOIC package. b) MCP6285-E/MS: Extended Temperature, 8LD MSOP package. c) MCP6285-E/P: Extended Temperature, 8LD PDIP package. d) MCP6285T-E/SN: Tape and Reel, Extended Temperature, 8LD SOIC package.  2019 Microchip Technology Inc. DS20001811F-page 45

MCP6281/1R/2/3/4/5 NOTES: DS20001811F-page 46  2019 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, Adaptec, and may be superseded by updates. It is your responsibility to AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT, ensure that your application meets with your specifications. chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, MICROCHIP MAKES NO REPRESENTATIONS OR LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, WARRANTIES OF ANY KIND WHETHER EXPRESS OR Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, IMPLIED, WRITTEN OR ORAL, STATUTORY OR PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, OTHERWISE, RELATED TO THE INFORMATION, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, INCLUDING BUT NOT LIMITED TO ITS CONDITION, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA QUALITY, PERFORMANCE, MERCHANTABILITY OR are registered trademarks of Microchip Technology Incorporated in FITNESS FOR PURPOSE. Microchip disclaims all liability the U.S.A. and other countries. arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at APT, ClockWorks, The Embedded Control Solutions Company, the buyer’s risk, and the buyer agrees to defend, indemnify and EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision hold harmless Microchip from any and all damages, claims, Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, suits, or expenses resulting from such use. No licenses are SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, conveyed, implicitly or otherwise, under any Microchip TimePictra, TimeProvider, Vite, WinPath, and ZL are registered intellectual property rights unless otherwise stated. trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2019, Microchip Technology Incorporated, All Rights Reserved. For information regarding Microchip’s Quality Management Systems, ISBN: 978-1-5224-5356-7 please visit www.microchip.com/quality.  2019 Microchip Technology Inc. DS20001811F-page 47

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