MCP6231/1R/1U/2/4 20 µA, 300 kHz Rail-to-Rail Op Amp Features Description • Gain Bandwidth Product: 300kHz (typical) The Microchip Technology Inc. MCP6231/1R/1U/2/4 operational amplifiers (op amps) provide wide bandwidth • Supply Current: I = 20µA (typical) Q for the quiescent current. The MCP6231/1R/1U/2/4 • Supply Voltage: 1.8V to 6.0V family has a 300 kHz gain bandwidth product and 65°C • Rail-to-Rail Input/Output (typical) phase margin. This family operates from a • Extended Temperature Range: -40°C to +125°C single supply voltage as low as 1.8V, while drawing • Available in 5-Pin SC70 and SOT-23 packages 20 µA (typical) quiescent current. In addition, the MCP6231/1R/1U/2/4 family supports rail-to-rail input Applications and output swing, with a Common-mode input voltage range of V + 300 mV to V – 300 mV. These op amps DD SS • Automotive are designed in one of Microchip’s advanced CMOS • Portable Equipment processes. • Transimpedance Amplifiers Package Types • Analog Filters MCP6231 MCP6231 • Notebooks and PDAs SOT-23-5 MSOP, PDIP, SOIC • Battery-Powered Systems VOUT 1 55 VDD NC 1 8 NC Design Aids 2 VIN- 2 – 7 VDD + – • SPICE Macro Models VIN+ 3 44 VIN- VIN+ 3 + 6 VOUT • FilterLab® Software VSS 4 5 NC • Mindi™ Circuit Designer and Simulator MCP6231R MCP6232 • Microchip Advanced Part Selector (MAPS) SOT-23-5 MSOP, PDIP, SOIC • Analog Demonstration and Evaluation Boards VOUT 1 5 VSS VOUTA 1 8 VDD • Application Notes VDD 2 + – VINA- 2 –+ 7 VOUTB VIN+ 3 4 VIN- VINA+ 3 +– 6 VINB- Typical Application VSS 4 5 VINB+ R G2 MCP6231U MCP6232 VIN2 SC70-5, SOT-23-5 2x3 TDFN* V RG1 VIN+ 1 5 VDD VOUTA 1 8 VDD IN1 RF VSS 2 + VINA- 2 EP 7 VOUTB VDD – VIN- 3 – 4 VOUT VINA+ 3 9 6 VINB- RX MCP6231 VOUT VSS 4 5 VINB+ + MCP6231 MCP6234 R R DFN* PDIP, SOIC, TSSOP Y Z NC 1 8 NC VOUTA 1 14VOUTD VIN- 2 EP 7 VDD VINA- 2 -+ +- 13VIND- VIN+ 3 9 6 VOUT VINA+ 3 12VIND+ Summing Amplifier Circuit VSS 4 5 NC VDD 4 11VSS VINB+ 5 10VINC+ VINB- 6 -+ +- 9 VINC- VOUTB 7 8 VOUTC * Includes Exposed Thermal Pad (EP); see Table3-1.  2004-2020 Microchip Technology Inc. DS20001881G-page 1

MCP6231/1R/1U/2/4 NOTES: DS20001881G-page 2  2004-2020 Microchip Technology Inc.

MCP6231/1R/1U/2/4 1.0 ELECTRICAL † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the CHARACTERISTICS device. This is a stress rating only and functional operation of the device at those or any other conditions above those Absolute Maximum Ratings† indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended V –V ........................................................................7.0V DD SS periods may affect device reliability. Current at Analog Input Pins (V +, V -)......................±2mA IN IN †† See Section4.1.2 “Input Voltage and Current Limits”. Analog Inputs (V +, V -)††..........V –1.0VtoV +1.0V IN IN SS DD All Other Inputs and Outputs .........V –0.3V to V +0.3V SS DD Difference Input Voltage ......................................|V –V | DD SS Output Short-Circuit Current ................................Continuous Current at Output and Supply Pins ............................±30mA Storage Temperature....................................-65°C to +150°C Maximum Junction Temperature (T )..........................+150°C J ESD Protection on All Pins (HBM; MM) 4kV; 300V DC ELECTRICAL CHARACTERISTICS Electrical Characteristics: Unless otherwise indicated, T = +25°C, V = +1.8V to +5.5V, V = GND, V = V /2, A DD SS CM DD R = 100kto V /2 and V V /2. L DD OUT DD Parameters Sym Min Typ Max Units Conditions Input Offset Input Offset Voltage V -5.0 — +5.0 mV V = V OS CM SS Extended Temperature V -7.0 — +7.0 mV T = -40°C to +125°C, OS A V = V (Note1) CM SS Input Offset Drift with Temperature V /T — ±3.0 — µV/°C T = -40°C to +125°C, OS A A V = V CM SS Power Supply Rejection Ratio PSRR — 83 — dB V = V CM SS Input Bias Current and Impedance Input Bias Current: I — ±1.0 — pA B At Temperature I — 20 — pA T = +85°C B A At Temperature I — 1100 — pA T = +125°C B A Input Offset Current I — ±1.0 — pA OS Common-Mode Input Impedance Z — 1013||6 — ||pF CM Differential Input Impedance Z — 1013||3 — ||pF DIFF Common-Mode Common-Mode Input Range V V –0.3 — V + 0.3 V CMR SS DD Common-Mode Rejection Ratio CMRR 61 75 — dB V = -0.3V to 5.3V, CM V = 5V DD Open-Loop Gain DC Open-Loop Gain (large signal) A 90 110 — dB V = 0.3V to V – 0.3V, OL OUT DD V =V CM SS Output Maximum Output Voltage Swing V , V V + 35 — V – 35 mV R =10k0.5V Input OL OH SS DD L Overdrive Output Short-Circuit Current I — ±6 — mA V = 1.8V SC DD I — ±23 — mA V = 5.5V SC DD Power Supply Supply Voltage V 1.8 — 6.0 V DD Quiescent Current per Amplifier I 10 20 30 µA I = 0, V = V – 0.5V Q O CM DD Note 1: The SC70 package is only tested at +25°C. 2: All parts with date codes of February 2007 and later have been screened to ensure operation at V =6.0V. However, DD the other minimum and maximum specifications are measured at 1.8V and 5.5V.  2004-2020 Microchip Technology Inc. DS20001881G-page 3

MCP6231/1R/1U/2/4 AC ELECTRICAL CHARACTERISTICS Electrical Characteristics: Unless otherwise indicated, T = +25°C, V = +1.8 to 5.5V, V = GND, V = V /2, A DD SS CM DD V V /2, R = 100k to V /2 and C = 60pF. OUT DD L DD L Parameters Sym Min Typ Max Units Conditions AC Response Gain Bandwidth Product GBWP — 300 — kHz Phase Margin PM — 65 — ° G = +1V/V Slew Rate SR — 0.15 — V/µs Noise Input Noise Voltage E — 6.0 — µV f = 0.1Hz to 10Hz ni P-P Input Noise Voltage Density e — 52 — nV/Hz f = 1kHz ni Input Noise Current Density i — 0.6 — fA/Hz f = 1kHz ni TEMPERATURE CHARACTERISTICS Electrical Characteristics: Unless otherwise indicated, V = +1.8V to +5.5V and V = GND. DD SS Parameters Sym Min Typ Max Units Conditions Temperature Ranges Extended Temperature Range T -40 — +125 °C A Operating Temperature Range T -40 — +125 °C Note1 A Storage Temperature Range T -65 — +150 °C A Thermal Package Resistances Thermal Resistance, 5L-SC70  — 331 — °C/W JA Thermal Resistance, 5L-SOT-23  — 256 — °C/W JA Thermal Resistance, 8L-DFN  — 84.5 — °C/W JA Thermal Resistance, 8L-MSOP  — 206 — °C/W JA Thermal Resistance, 8L-TDFN  — 41 — °C/W JA Thermal Resistance, 8L-PDIP  — 85 — °C/W JA Thermal Resistance, 8L-SOIC  — 163 — °C/W JA Thermal Resistance, 14L-PDIP  — 70 — °C/W JA Thermal Resistance, 14L-SOIC  — 120 — °C/W JA Thermal Resistance, 14L-TSSOP  — 100 — °C/W JA Note 1: The internal Junction Temperature (T ) must not exceed the absolute maximum specification of +150°C. J DS20001881G-page 4  2004-2020 Microchip Technology Inc.

MCP6231/1R/1U/2/4 1.1 Test Circuits The test circuits used for the DC and AC tests are shown in Figure1-1 and Figure1-2. The bypass capacitors are laid out according to the rules discussed in Section4.6 “PCB Surface Leakage”. VIN VDD 0.1µF1µF VDD/2 VDD 0.1µF1µF + + RN MCP623X VOUT RN MCP623X VOUT – CL RL – CL RL VDD/2 RG RF VIN RG RF VL VL FIGURE 1-1: AC and DC Test Circuit for FIGURE 1-2: AC and DC Test Circuit for Most Noninverting Gain Conditions. Most Inverting Gain Conditions.  2004-2020 Microchip Technology Inc. DS20001881G-page 5

MCP6231/1R/1U/2/4 NOTES: DS20001881G-page 6  2004-2020 Microchip Technology Inc.

MCP6231/1R/1U/2/4 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, T = +25°C, V = +1.8V to +5.5V, V = GND, V = V /2, V V /2, A DD SS CM DD OUT DD R = 100kto V /2 and C = 60pF. L DD L 20% 90 es 18% 630 Samples c V = V e of Occurren 111102468%%%%% CM SS R, PSRR (dB) 8805 PSRR (VCM = VSS) ercentag 246%%% CMR 75 CMRR (VVCDMD = = - 05..30VV )to +5.3V, P 0% 70 5 4 3 2 1 0 1 2 3 4 5 -50 -25 0 25 50 75 100 125 - - - - - Input Offset Voltage (mV) Ambient Temperature (°C) FIGURE 2-1: Input Offset Voltage. FIGURE 2-4: CMRR, PSRR vs. Ambient Temperature. 100 120 0 R = 10 kΩ RR (dB) 789000 PSRR- CMRR Gain (dB)1068000 Gain VCLM = VDD/2 ---963000 Phase (°) R, CM 5600 PSRR+ Loop 40 Phase -120 Loop PSR 40 pen- 20 -150 pen- 30 O 0 -180 O 2011.E0+01 11.E0+020 11.Ek+03 11.E0+04k 101.E+005k -20 -210 10..E1- 1.1E+11.E0+11.0E0+11.Ek+11.0Ek+110.E0+k11.EM+11.0EM+ Frequency (Hz) 01 00 01 Fr0e2que0n3cy (0H4z) 05 06 07 FIGURE 2-2: PSRR, CMRR vs. FIGURE 2-5: Open-Loop Gain, Phase vs. Frequency. Frequency. 20% 30% es 18% 630 Samples es 632 Samples nc 16% VCM = VDD/2 nc 25% VCM = VDD/2 urre 14% TA = +85°C urre 20% TA = +125°C cc 12% cc O O of 10% of 15% e 8% e g g 10% a 6% a ent 4% ent 5% c c er 2% er P 0% P 0% 0 6 12 18 24 30 36 42 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 Input Bias Current (pA) Input Bias Current (nA) FIGURE 2-3: Input Bias Current at +85°C. FIGURE 2-6: Input Bias Current at +125°C.  2004-2020 Microchip Technology Inc. DS20001881G-page 7

MCP6231/1R/1U/2/4 Note: Unless otherwise indicated, T = +25°C, V = +1.8V to +5.5V, V = GND, V = V /2, V V /2, A DD SS CM DD OUT DD R = 100kto V /2 and C = 60pF. L DD L 1,000 20% e Density urrences 111468%%% 6VT2AC 8M= S=-4 aV0mS°SpCl etos +125°C VoltagV/Hz) 100 of Occ 1102%% Input Noise (n 10 Percentage 02468%%%%% 1.0E.-101 1.E1+0 1.1E0+0 11.E0+00 1.1Ek+0 11.E0+k0 11.0E0+k0 12 10 -8 -6 -4 -2 0 2 4 6 8 10 12 - - 0 1Freque2ncy (Hz3) 4 5 Input Offset Voltage Drift (µV/°C) FIGURE 2-7: Input Noise Voltage Density FIGURE 2-10: Input Offset Voltage Drift. vs. Frequency. 550 100 Voltage (µV) 345500 VDD = 1.8V TTTTAAAA = === + ++-142820555°°°C°CCC Voltage (µV) -1-0550000 VCM = VSS nput Offset 250 nput Offset ---221505000 VDD = 1.8V VDD = 5.5V I 150 I -300 4 2 0 2 4 6 8 0 2 4 6 8 0 2 0. 0. 0. 0. 0. 0. 0. 1. 1. 1. 1. 1. 2. 2. 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 - - Common Mode Input Voltage (V) Output Voltage (V) FIGURE 2-8: Input Offset Voltage vs. FIGURE 2-11: Input Offset Voltage vs. Common-Mode Input Voltage at V = 1.8V. Output Voltage. DD 30 200 V = 5.5 V nt 25 +ISC nput Offset Voltage (µV)--1111-0555500000000 DD TTTTAAAA ==== -+++48210552°°°5CCC°C utput Short-Circuit Curre(mA)----2211112-5050050505 -ISC TTTTAAAA ==== ++-+48210552°°°5CCC°C I-200 O -30 0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 - Common Mode Input Voltage (V) Power Supply Voltage (V) FIGURE 2-9: Input Offset Voltage vs. FIGURE 2-12: Output Short-Circuit Current Common-Mode Input Voltage at V = 5.5V. vs. Ambient Temperature. DD DS20001881G-page 8  2004-2020 Microchip Technology Inc.

MCP6231/1R/1U/2/4 Note: Unless otherwise indicated, T = +25°C, V = +1.8V to +5.5V, V = GND, V = V /2, V V /2, A DD SS CM DD OUT DD R = 100kto V /2 and C = 60pF. L DD L 0.30 G = +1 V/V V = 5.5V DD v) RL = 10 kΩ µs) 0.25 Falling Edge mV/di V/ 0.20 0 Slew Rate ( 00..1105 ut Voltage (1 Rising Edge VDD = 1.8V utp 0.05 O -50 -25 0 25 50 75 100 125 Ambient Temperature (°C) Time (2 µs/div) FIGURE 2-13: Slew Rate vs. Ambient FIGURE 2-16: Small-Signal, Noninverting Temperature. Pulse Response. 1,000 5.0 m 4.5 VDD = 5.0V Headroo 100 VDD – VOH e (V) 34..50 G = +1 V/V e V) ag 3.0 Voltag(m 10 VOL – VSS ut Volt 22..05 put utp 1.5 ut O 1.0 O 1 0.5 1.1E0-µ02 11.E00-0µ1 1.1Em+00 11.E0+m01 0.0 Output Current Magnitude (A) Time (20 µs/div) FIGURE 2-14: Output Voltage Headroom vs. FIGURE 2-17: Large-Signal, Noninverting Output Current Magnitude. Pulse Response. 10 30 V = 0.9V g CM DD n 25 wi VDD = 5.5V ntA) x. Output Voltage S(V)P-P 1 VDD = 1.8V Quiescent Curreper Amplifier (µ 1120505 TTTTAAAA ==== +-++41820255°5°°CCC°C a M 0 0.1 1k 10k 100k 1M 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.E+03 1.E+04 1.E+05 1.E+06 Frequency (Hz) Power Supply Voltage (V) FIGURE 2-15: Maximum Output Voltage FIGURE 2-18: Quiescent Current vs. Swing vs. Frequency. Power Supply Voltage.  2004-2020 Microchip Technology Inc. DS20001881G-page 9

MCP6231/1R/1U/2/4 Note: Unless otherwise indicated, T = +25°C, V = +1.8V to +5.5V, V = GND, V = V /2, V V /2, A DD SS CM DD OUT DD R = 100kto V /2 and C = 60pF. L DD L 1.E1-00m2 6.0 urrent Magnitude (A)1111111.......11EEEEEEE0101-------10000000001100m9876543nnnµµµ ++12855°°CC utput Voltages (V) 2345....0000 VIN VOUT VGD =D =+ 25 .V0/VV Input C111...1EEE01---111001210ppp +-4205°°CC Input, O 01..00 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 -1.0 Input Voltage (V) Time (1 ms/div) FIGURE 2-19: Measured Input Current vs. FIGURE 2-20: The MCP6231/1R/1U/2/4 Input Voltage (below V ). Show No Phase Reversal. SS DS20001881G-page 10  2004-2020 Microchip Technology Inc.

MCP6231/1R/1U/2/4 3.0 PIN DESCRIPTIONS Descriptions of the pins are listed in Table3-1 (single op amps) and Table3-2 (dual and quad op amps). TABLE 3-1: PIN FUNCTION TABLE FOR SINGLE OP AMPS MCP6231 MCP6231R MCP6231U Symbol Description DFN, MSOP, SOT-23-5 SOT-23-5 SOT-23-5 PDIP, SOIC SC70 6 1 1 4 V Analog Output OUT 2 4 4 3 V - Inverting Input IN 3 3 3 1 V + Noninverting Input IN 7 5 2 5 V Positive Power Supply DD 4 2 5 2 V Negative Power Supply SS 1, 5, 8 — — — NC No Internal Connection 9 — — — EP Exposed Thermal Pad (EP); must be connected to V . SS TABLE 3-2: PIN FUNCTION TABLE FOR DUAL AND QUAD OP AMPS MCP6232 MCP6234 Symbol Description MSOP, PDIP, PDIP, SOIC, TSSOP SOIC, TDFN 1 1 V Analog Output (Op Amp A) OUTA 2 2 V - Inverting Input (Op Amp A) INA 3 3 V + Noninverting Input (Op Amp A) INA 8 4 V Positive Power Supply DD 5 5 V + Noninverting Input (Op Amp B) INB 6 6 V - Inverting Input (Op Amp B) INB 7 7 V Analog Output (Op Amp B) OUTB — 8 V Analog Output (Op Amp C) OUTC — 9 V - Inverting Input (Op Amp C) INC — 10 V + Noninverting Input (Op Amp C) INC 4 11 V Negative Power Supply SS — 12 V + Noninverting Input (Op Amp D) IND — 13 V - Inverting Input (Op Amp D) IND — 14 V Analog Output (Op Amp D) OUTD 9 — — Exposed Thermal Pad (EP); must be connected to V . SS  2004-2020 Microchip Technology Inc. DS20001881G-page 11

MCP6231/1R/1U/2/4 3.1 Analog Outputs 3.4 Exposed Thermal Pad (EP) The output pins are low-impedance voltage sources. There is an internal electrical connection between the Exposed Thermal Pad (EP) and the V pin; they must SS 3.2 Analog Inputs be connected to the same potential on the Printed Circuit Board (PCB). The noninverting and inverting inputs are high-impedance CMOS inputs with low bias currents. 3.3 Power Supply (V and V ) SS DD The positive power supply (V ) is 1.8V to 6.0V higher DD than the negative power supply (V ). For normal SS operation, the other pins are between V and V . SS DD Typically, these parts are used in a single (positive) supply configuration. In this case, V is connected to SS ground and V is connected to the supply. V will DD DD need bypass capacitors. DS20001881G-page 12  2004-2020 Microchip Technology Inc.

MCP6231/1R/1U/2/4 4.0 APPLICATION INFORMATION The MCP6231/1R/1U/2/4 family of op amps is V Bond DD manufactured using Microchip’s state-of-the-art CMOS Pad process and is specifically designed for low-cost, low-power and general purpose applications. The low supply voltage, low quiescent current and wide Bond Input Bond V + V - bandwidth makes the MCP6231/1R/1U/2/4 ideal for IN Pad Stage Pad IN battery-powered applications. 4.1 Rail-to-Rail Inputs Bond V SS Pad 4.1.1 PHASE REVERSAL The MCP6231/1R/1U/2/4 op amp is designed to FIGURE 4-2: Simplified Analog Input ESD prevent phase reversal when the input pins exceed the Structures. supply voltages. Figure4-1 shows the input voltage In order to prevent damage and/or improper operation exceeding the supply voltage without any phase of these op amps, the circuit they are in must limit the reversal. currents and voltages at the V + and V - pins (see IN IN Absolute Maximum Ratings† at the beginning of 6.0 Section1.0 “Electrical Characteristics”). Figure4-3 s (V) 5.0 VOUT VGD =D =+ 25 .V0/VV sinhpouwtss. tThhee r einctoemrnmale EndSeDd daipopdreosa pcrhe tvoe nptr othteec tininpgu tth peinses oltage 34..00 VIN (thVeIN +re asinsdto VrsIN, -R) 1fr oamn dg oRin2g, ltiomoi t fathr eb eploowss igbrloeu ncudr raenndt ut V drawn out of the input pins. Diodes D1 and D2 prevent p 2.0 the input pins (V + and V -) from going too far above ut IN IN nput, O 01..00 VitmhDepD lc eumarrenendnt te tddh uraomsu pgs hho aDwnny a , nrcedus Drisreto.nrtss Ro1 natnod RV2D,D a. lsoW lhimenit I 1 2 -1.0 Time (1 ms/div) V DD FIGURE 4-1: The MCP6231/1R/1U/2/4 Show No Phase Reversal. D D 1 2 4.1.2 INPUT VOLTAGE AND CURRENT V1 + LIMITS R1 MCP623X The ESD protection on the inputs can be depicted as V2 – shown in Figure4-2. This structure was chosen to R 2 protect the input transistors and to minimize input bias current (I ). The input ESD diodes clamp the inputs B R when they try to go more than one diode drop below 3 V . They also clamp any voltages that go too far V –(minimum expected V ) SS SS 1 R > above VDD; their breakdown voltage is high enough to 1 2mA allow normal operation and low enough to bypass quick V –(minimum expected V ) SS 2 ESD events within the specified limits. R2> 2mA FIGURE 4-3: Protecting the Analog Inputs. It is also possible to connect the diodes to the left of resistors, R and R . In this case, current through the 1 2 diodes, D and D , needs to be limited by some other 1 2 mechanism. The resistors then serve as in-rush current limiters; the DC current into the input pins (V + and IN V -) should be very small. IN  2004-2020 Microchip Technology Inc. DS20001881G-page 13

MCP6231/1R/1U/2/4 A significant amount of current can flow out of the inputs when the Common-mode voltage (V ) is below CM 10,01000k ground (V ); see Figure2-19. Applications that are SS high-impedance may need to limit the usable voltage Ω) range. (SO RI d e 4.1.3 NORMAL OPERATION d1,0010k n e The input stage of the MCP6231/1R/1U/2/4 op amps m GN = 1 V/V m G = 2 V/V use two differential CMOS input stages in parallel. One o N operates at low Common-mode input voltage (VCM), Rec GN  4 V/V while the other operates at high VCM. With this 110000 topology, the device operates with VCM up to 0.3V 1100p 110000p 110n00 11000n00 above V and 0.3V below V . Normalized Load Capacitance; CL/GN (F) DD SS FIGURE 4-5: Recommended R Values 4.2 Rail-to-Rail Output ISO for Capacitive Loads. The output voltage range of the MCP6231/1R/1U/2/4 After selecting R for your circuit, double-check the ISO op amps is V – 35 mV (maximum) and V + 35 mV DD SS resulting frequency response peaking and step (minimum) when R = 10 k is connected to V /2 and L DD response overshoot. Evaluation on the bench and V = 5.5V. Refer to Figure2-14 for more information. DD simulations with the MCP6231/1R/1U/2/4 SPICE macro model are very helpful. Modify R ’s value until ISO 4.3 Capacitive Loads the response is reasonable. Driving large capacitive loads can cause stability 4.4 Supply Bypass problems for voltage feedback op amps. As the load capacitance increases, the feedback loop’s phase With this op amp, the power supply pin (V for DD margin decreases and the closed-loop bandwidth is single-supply) should have a local bypass capacitor reduced. This produces gain peaking in the frequency (i.e., 0.01 µF to 0.1 µF) within 2 mm for good response, with overshoot and ringing in the step high-frequency performance. It can use a bulk capac- response. A unity gain buffer (G = +1) is the most itor (i.e., 1 µF or larger) within 100 mm to provide sensitive to capacitive loads, but all gains show the large, slow currents. This bulk capacitor can be same general behavior. shared with other nearby analog parts. When driving large capacitive loads with these opamps (e.g., >60pF when G = +1), a small series resistor at 4.5 Unused Op Amps the output (R in Figure4-4) improves the feedback ISO loop’s phase margin (stability) by making the output An unused op amp in a quad package (MCP6234) load resistive at higher frequencies. The bandwidth will should be configured as shown in Figure4-6. Both be generally lower than the bandwidth with no circuits prevent the output from toggling and causing capacitive load. crosstalk. Circuit A can use any reference voltage between the supplies, provides a buffered DC voltage and minimizes the supply current draw of the unused op amp. Circuit B minimizes the number of compo- — R nents, but may draw a little more supply current for the ISO unused op amp. MCP623X VOUT VIN + CL ¼ MCP6234 (A) ¼ MCP6234 (B) V V DD DD FIGURE 4-4: Output Resistor, R , V ISO R DD Stabilizes Large Capacitive Loads. 1 + + Fenigt urceap4a-5c itgivivee sl oraedcos mamnedn dgeadin sR.I STOh vea lux-easx ifso r ids ifftehre- R2 – VREF – normalized load capacitance (C /G ), where G is the L N N circuit’s noise gain. For noninverting gains, G and the N R signal gain are equal. For inverting gains, G is 2 N V = V -------------------- 1+|Signal Gain| (e.g., –1 V/V gives G = +2V/V). REF DD R +R N 1 2 FIGURE 4-6: Unused Op Amps. DS20001881G-page 14  2004-2020 Microchip Technology Inc.

MCP6231/1R/1U/2/4 4.6 PCB Surface Leakage 4.7 Application Circuits In applications where low input bias current is critical, 4.7.1 MATCHING THE IMPEDANCE AT Printed Circuit Board (PCB) surface leakage effects THE INPUTS need to be considered. Surface leakage is caused by humidity, dust or other contamination on the board. To minimize the effect of input bias current in an ampli- Under low humidity conditions, a typical resistance fier circuit (this is important for very high source between nearby traces is 1012. A 5V difference would impedance applications, such as pH meters and cause 5 pA of current to flow, which is greater than the transimpedance amplifiers), the impedances at the MCP6231/1R/1U/2/4 family’s bias current at +25°C inverting and noninverting inputs need to be matched. (1pA, typical). This is done by choosing the circuit resistor values so that the total resistance at each input is the same. The easiest way to reduce surface leakage is to use a Figure4-8 shows a summing amplifier circuit. guard ring around sensitive pins (or traces). The guard ring is biased at the same voltage as the sensitive pin. R An example of this type of layout is shown in G2 V IN2 Figure4-7. R G1 V IN1 R V – V + F IN IN V SS V DD – RX MCP623X VOUT + R R Y Z Guard Ring FIGURE 4-8: Summing Amplifier Circuit. FIGURE 4-7: Example Guard Ring Layout To match the inputs, set all voltage sources to ground for Inverting Gain. and calculate the total resistance at the input nodes. In this summing amplifier circuit, the resistance at the 1. Noninverting Gain and Unity-Gain Buffer: inverting input is calculated by setting V , V and IN1 IN2 a) Connect the noninverting pin (VIN+) to the VOUT to ground. In this case, RG1, RG2 and RF are in input with a wire that does not touch the parallel. The total resistance at the inverting input is: PCB surface. b) Connect the guard ring to the inverting input EQUATION 4-1: pin (VIN-). This biases the guard ring to the 1 R = Common-mode input voltage. VIN-  1 + 1 + 1 2. Inverting Gain and Transimpedance Amplifiers RG1 RG2 RF (convert current to voltage, such as photo Where: detectors): R - = Total Resistance at the Inverting Input a) Connect the guard ring to the noninverting VIN input pin (V +). This biases the guard ring IN to the same reference voltage as the At the noninverting input, V is the only voltage source. DD opamp (e.g., V /2 or ground). When V is set to ground, both R and R are in parallel. DD DD X Y b) Connect the inverting pin (V -) to the input The total resistance at the noninverting input is: IN with a wire that does not touch the PCB EQUATION 4-2: surface. 1 RVIN+ = -----1--------------1-------+RZ ------+------ R R  X Y Where: R + = Total Resistance at the Inverting Input VIN  2004-2020 Microchip Technology Inc. DS20001881G-page 15

MCP6231/1R/1U/2/4 To minimize output offset voltage and increase circuit accuracy, the resistor values need to meet the conditions: VAC + MCP623X VOUT EQUATION 4-3: – R + = R - VIN VIN R R G F V DC 4.7.2 COMPENSATING FOR THE PARASITIC CAPACITANCE C PARA C In analog circuit design, the PCB parasitic capacitance F can compromise the circuit behavior; Figure4-9 shows R a typical scenario. If the input of an amplifier sees C = C ----G--- F PARA R parasitic capacitance of several picofarad (C , F PARA which includes the Common-mode capacitance of FIGURE 4-9: Effect of Parasitic 6pF, typical), as well as large R and R , the frequency F G Capacitance at the Input. response of the circuit will include a zero. This parasitic zero introduces gain peaking and can cause circuit One solution is to use smaller resistor values to push instability. the zero to a higher frequency. Another solution is to compensate by introducing a pole at the point at which the zero occurs. This can be done by adding C in F parallel with the feedback resistor (R ). C needs to be F F selected so that the ratio, C :C , is equal to the ratio PARA F of R :R . F G DS20001881G-page 16  2004-2020 Microchip Technology Inc.

MCP6231/1R/1U/2/4 5.0 DESIGN AIDS 5.5 Analog Demonstration and Evaluation Boards Microchip provides the basic design tools needed for the MCP6231/1R/1U/2/4 family of op amps. Microchip offers a broad spectrum of Analog Demon- stration and Evaluation Boards that are designed to 5.1 SPICE Macro Model help you achieve faster time to market. For a complete listing of these boards and their corresponding user’s The latest SPICE macro model for the guides and technical information, visit the Microchip MCP6231/1R/1U/2/4 op amps is available on the website at: Microchip website at www.microchip.com. This model www.microchip.com/analogtools is intended to be an initial design tool that works well in the op amp’s linear region of operation over the Two of our boards that are especially useful are: temperature range. See the model file for information • P/N SOIC8EV: 8-Pin SOIC/MSOP/TSSOP/DIP on its capabilities. Evaluation Board Bench testing is a very important part of any design and • P/N SOIC14EV: 14-Pin SOIC/TSSOP/DIP cannot be replaced with simulations. Also, simulation Evaluation Board results using this macro model need to be validated by comparing them to the data sheet specifications and 5.6 Application Notes characteristic curves. The following Microchip Application Notes are available 5.2 FilterLab® Software on the Microchip website at www.microchip. com/ appnotes and are recommended as supplemental Microchip’s FilterLab® software is an innovative reference resources. software tool that simplifies analog active filter (using • ADN003: “Select the Right Operational Amplifier op amps) design. Available at no cost from the for your Filtering Circuits,” DS21821 Microchip website at www.microchip.com/filterlab, the FilterLab design tool provides full schematic diagrams • AN722: “Operational Amplifier Topologies and DC of the filter circuit with component values. It also Specifications,” DS00722 outputs the filter circuit in SPICE format, which can be • AN723: “Operational Amplifier AC Specifications used with the macro model to simulate actual filter and Applications,” DS00723 performance. • AN884: “Driving Capacitive Loads With OpAmps,” DS00884 5.3 Mindi™ Circuit Designer and • AN990: “Analog Sensor Conditioning Simulator Circuits–An Overview,” DS00990 These application notes and others are listed in the Microchip’s Mindi™ Circuit Designer and Simulator aids design guide: in the design of various circuits useful for active filter, amplifier and power management applications. It is a • “Signal Chain Design Guide,” DS21825 free online circuit designer and simulator available from the Microchip website at www.microchip.com/mindi. This interactive circuit designer and simulator enables designers to quickly generate circuit diagrams, and simulate circuits. Circuits developed using the Mindi Circuit Designer and Simulator can be downloaded to a personal computer or workstation. 5.4 Microchip Advanced Part Selector (MAPS) MAPS is a software tool that helps semiconductor professionals efficiently identify Microchip devices that fit a particular design requirement. Available at no cost from the Microchip website at www.microchip.com/ maps, MAPS is an overall selection tool for Microchip’s product portfolio that includes Analog, Memory, MCUs and DSCs. Using this tool you can define a filter to sort features for a parametric search of devices and export side-by-side technical comparison reports. Helpful links are also provided for data sheets, purchase and sampling of Microchip parts.  2004-2020 Microchip Technology Inc. DS20001881G-page 17

MCP6231/1R/1U/2/4 NOTES: DS20001881G-page 18  2004-2020 Microchip Technology Inc.

MCP6231/1R/1U/2/4 6.0 PACKAGING INFORMATION 6.1 Package Marking Information 5-Lead SC70 (MCP6231U Only) Example: XXNN AS25 5-Lead SOT-23 Example: Device Code 5 4 MCP6231 BJNN 5 4 MCP6231R BKNN XXNN MCP6231U BLNN BJ25 Note: Applies to 5-Lead SOT-23. 1 2 3 1 2 3 8-Lead DFN (2x3 mm) (MCP6231) Example: XXX AER YWW 929 NNN 256 8-Lead TDFN (2x3 mm) (MCP6232) Example: XXX AAE YWW 929 NNN 256 8-Lead MSOP Example: 6231E 6232E 929256 929256 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2004-2020 Microchip Technology Inc. DS20001881G-page 19

MCP6231/1R/1U/2/4 Package Marking Information (Continued) 8-Lead PDIP (300 mil) Example: XXXXXXXX MCP6232 MCP6232 XXXXXNNN E/P256 OR E/P e 3 256 YYWW 0929 0929 8-Lead SOIC (150 mil) Example: XXXXXXXX MCP6232 MCP6232E XXXXYYWW E/SN0929 OR SN e3 0929 NNN 256 256 14-Lead PDIP (300 mil) (MCP6234) Example: XXXXXXXXXXXXXX MCP6234 XXXXXXXXXXXXXX E/P^e^3 YYWWNNN 0929256 14-Lead SOIC (150 mil) (MCP6234) Example: XXXXXXXXXX MCP6234 XXXXXXXXXX E/SL^e^3 YYWWNNN 0929256 14-Lead TSSOP (MCP6234) Example: XXXXXXXX 6234E YYWW 0929 NNN 256 DS20001881G-page 20  2004-2020 Microchip Technology Inc.

MCP6231/1R/1U/2/4 5-Lead Plastic Small Outline Transistor (LT) [SC70] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A e e B 3 1 E1 E 2X 0.15 C 4 N NOTE 1 5X TIPS 0.30 C 2X 0.15 C 5X b 0.10 C A B TOP VIEW c C A A2 SEATING PLANE A1 L SIDE VIEW END VIEW Microchip Technology Drawing C04-061-LT Rev E Sheet 1 of 2  2004-2020 Microchip Technology Inc. DS20001881G-page 21

MCP6231/1R/1U/2/4 5-Lead Plastic Small Outline Transistor (LT) [SC70] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 5 Pitch e 0.65 BSC Overall Height A 0.80 - 1.10 Standoff A1 0.00 - 0.10 Molded Package Thickness A2 0.80 - 1.00 Overall Length D 2.00 BSC Overall Width E 2.10 BSC Molded Package Width E1 1.25 BSC Terminal Width b 0.15 - 0.40 Terminal Length L 0.10 0.20 0.46 Lead Thickness c 0.08 - 0.26 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-061-LT Rev E Sheet 2 of 2 DS20001881G-page 22  2004-2020 Microchip Technology Inc.

MCP6231/1R/1U/2/4 5-Lead Plastic Small Outline Transistor (LT) [SC70] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E Gx SILK SCREEN 3 2 1 C G 4 5 Y X RECOMMENDED LAND PATTERN Units MILLIMETERS Dimension Limits MIN NOM MAX Contact Pitch E 0.65 BSC Contact Pad Spacing C 2.20 Contact Pad Width X 0.45 Contact Pad Length Y 0.95 Distance Between Pads G 1.25 Distance Between Pads Gx 0.20 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-2061-LT Rev E  2004-2020 Microchip Technology Inc. DS20001881G-page 23

MCP6231/1R/1U/2/4 5-Lead Plastic Small Outline Transistor (OT) [SOT23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 0.20 C 2X D e1 A D N E/2 E1/2 E1 E (DATUM D) (DATUM A-B) 0.15 C D 2X NOTE 1 1 2 e B NX b 0.20 C A-B D TOP VIEW A A2 A 0.20 C SEATING PLANE A SEE SHEET 2 A1 C SIDE VIEW Microchip Technology Drawing C04-091-OT Rev F Sheet 1 of 2 DS20001881G-page 24  2004-2020 Microchip Technology Inc.

MCP6231/1R/1U/2/4 5-Lead Plastic Small Outline Transistor (OT) [SOT23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging c (cid:84) L L1 VIEW A-A SHEET 1 Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 5 Pitch e 0.95 BSC Outside lead pitch e1 1.90 BSC Overall Height A 0.90 - 1.45 Molded Package Thickness A2 0.89 - 1.30 Standoff A1 - - 0.15 Overall Width E 2.80 BSC Molded Package Width E1 1.60 BSC Overall Length D 2.90 BSC Foot Length L 0.30 - 0.60 Footprint L1 0.60 REF Foot Angle (cid:73) 0° - 10° Lead Thickness c 0.08 - 0.26 Lead Width b 0.20 - 0.51 Notes: 1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25mm per side. 2. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-091-OT Rev F Sheet 2 of 2  2004-2020 Microchip Technology Inc. DS20001881G-page 25

MCP6231/1R/1U/2/4 5-Lead Plastic Small Outline Transistor (OT) [SOT23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging X SILK SCREEN 5 Y Z C G 1 2 E GX RECOMMENDED LAND PATTERN Units MILLIMETERS Dimension Limits MIN NOM MAX Contact Pitch E 0.95 BSC Contact Pad Spacing C 2.80 Contact Pad Width (X5) X 0.60 Contact Pad Length (X5) Y 1.10 Distance Between Pads G 1.70 Distance Between Pads GX 0.35 Overall Width Z 3.90 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-2091-OT Rev F DS20001881G-page 26  2004-2020 Microchip Technology Inc.

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(cid:27)(cid:3)66(cid:7)(#) 3(cid:8)(cid:14)(cid:18)(cid:11)(cid:12)(cid:12)(cid:7)9(cid:5)(cid:13)(cid:17)(cid:26) % (cid:31)(cid:3)66(cid:7)(#) %(cid:15)(cid:30)(cid:23)(cid:9)(cid:14)(cid:13)(cid:7)(cid:4)(cid:11)(cid:13)(cid:7)1(cid:14)(cid:6)(cid:29)(cid:17)(cid:26) !(cid:27) (cid:2)(cid:3)(cid:31)6 : (cid:2)(cid:3)’’ %(cid:15)(cid:30)(cid:23)(cid:9)(cid:14)(cid:13)(cid:7)(cid:4)(cid:11)(cid:13)(cid:7)9(cid:5)(cid:13)(cid:17)(cid:26) %(cid:27) (cid:2)(cid:3)’6 : (cid:2)(cid:3);’ )(cid:23)(cid:6)(cid:17)(cid:11)(cid:24)(cid:17)(cid:7)9(cid:5)(cid:13)(cid:17)(cid:26) (cid:22) 6(cid:3)(cid:27)6 6(cid:3)(cid:27)’ 6(cid:3)(cid:31)6 )(cid:23)(cid:6)(cid:17)(cid:11)(cid:24)(cid:17)(cid:7)1(cid:14)(cid:6)(cid:29)(cid:17)(cid:26) 1 6(cid:3)(cid:31)6 6(cid:3) 6 6(cid:3)’6 )(cid:23)(cid:6)(cid:17)(cid:11)(cid:24)(cid:17)<(cid:17)(cid:23)<%(cid:15)(cid:30)(cid:23)(cid:9)(cid:14)(cid:13)(cid:7)(cid:4)(cid:11)(cid:13) = 6(cid:3)(cid:27)6 : : (cid:19)(cid:20)(cid:12)(cid:5)(cid:11)’ (cid:2)(cid:3) (cid:4)(cid:5)(cid:6)(cid:7)(cid:2)(cid:7)(cid:8)(cid:5)(cid:9)(cid:10)(cid:11)(cid:12)(cid:7)(cid:5)(cid:6)(cid:13)(cid:14)(cid:15)(cid:7)(cid:16)(cid:14)(cid:11)(cid:17)(cid:10)(cid:18)(cid:14)(cid:7)(cid:19)(cid:11)(cid:20)(cid:7)(cid:8)(cid:11)(cid:18)(cid:20)(cid:21)(cid:7)(cid:22)(cid:10)(cid:17)(cid:7)(cid:19)(cid:10)(cid:9)(cid:17)(cid:7)(cid:22)(cid:14)(cid:7)(cid:12)(cid:23)(cid:24)(cid:11)(cid:17)(cid:14)(cid:13)(cid:7)(cid:25)(cid:5)(cid:17)(cid:26)(cid:5)(cid:6)(cid:7)(cid:17)(cid:26)(cid:14)(cid:7)(cid:26)(cid:11)(cid:17)(cid:24)(cid:26)(cid:14)(cid:13)(cid:7)(cid:11)(cid:18)(cid:14)(cid:11)(cid:3) (cid:27)(cid:3) (cid:4)(cid:11)(cid:24)(cid:28)(cid:11)(cid:29)(cid:14)(cid:7)(cid:19)(cid:11)(cid:20)(cid:7)(cid:26)(cid:11)(cid:8)(cid:14)(cid:7)(cid:23)(cid:6)(cid:14)(cid:7)(cid:23)(cid:18)(cid:7)(cid:19)(cid:23)(cid:18)(cid:14)(cid:7)(cid:14)(cid:15)(cid:30)(cid:23)(cid:9)(cid:14)(cid:13)(cid:7)(cid:17)(cid:5)(cid:14)(cid:7)(cid:22)(cid:11)(cid:18)(cid:9)(cid:7)(cid:11)(cid:17)(cid:7)(cid:14)(cid:6)(cid:13)(cid:9)(cid:3) (cid:31)(cid:3) (cid:4)(cid:11)(cid:24)(cid:28)(cid:11)(cid:29)(cid:14)(cid:7)(cid:5)(cid:9)(cid:7)(cid:9)(cid:11)(cid:25)(cid:7)(cid:9)(cid:5)(cid:6)(cid:29)(cid:10)(cid:12)(cid:11)(cid:17)(cid:14)(cid:13)(cid:3) (cid:3) !(cid:5)(cid:19)(cid:14)(cid:6)(cid:9)(cid:5)(cid:23)(cid:6)(cid:5)(cid:6)(cid:29)(cid:7)(cid:11)(cid:6)(cid:13)(cid:7)(cid:17)(cid:23)(cid:12)(cid:14)(cid:18)(cid:11)(cid:6)(cid:24)(cid:5)(cid:6)(cid:29)(cid:7)(cid:30)(cid:14)(cid:18)(cid:7)"#$%(cid:7)&(cid:2) (cid:3)’$(cid:3) (#)* ((cid:11)(cid:9)(cid:5)(cid:24)(cid:7)!(cid:5)(cid:19)(cid:14)(cid:6)(cid:9)(cid:5)(cid:23)(cid:6)(cid:3)(cid:7)+(cid:26)(cid:14)(cid:23)(cid:18)(cid:14)(cid:17)(cid:5)(cid:24)(cid:11)(cid:12)(cid:12)(cid:20)(cid:7)(cid:14)(cid:15)(cid:11)(cid:24)(cid:17)(cid:7)(cid:8)(cid:11)(cid:12)(cid:10)(cid:14)(cid:7)(cid:9)(cid:26)(cid:23)(cid:25)(cid:6)(cid:7)(cid:25)(cid:5)(cid:17)(cid:26)(cid:23)(cid:10)(cid:17)(cid:7)(cid:17)(cid:23)(cid:12)(cid:14)(cid:18)(cid:11)(cid:6)(cid:24)(cid:14)(cid:9)(cid:3) ,%-* ,(cid:14)(cid:16)(cid:14)(cid:18)(cid:14)(cid:6)(cid:24)(cid:14)(cid:7)!(cid:5)(cid:19)(cid:14)(cid:6)(cid:9)(cid:5)(cid:23)(cid:6)(cid:21)(cid:7)(cid:10)(cid:9)(cid:10)(cid:11)(cid:12)(cid:12)(cid:20)(cid:7)(cid:25)(cid:5)(cid:17)(cid:26)(cid:23)(cid:10)(cid:17)(cid:7)(cid:17)(cid:23)(cid:12)(cid:14)(cid:18)(cid:11)(cid:6)(cid:24)(cid:14)(cid:21)(cid:7)(cid:16)(cid:23)(cid:18)(cid:7)(cid:5)(cid:6)(cid:16)(cid:23)(cid:18)(cid:19)(cid:11)(cid:17)(cid:5)(cid:23)(cid:6)(cid:7)(cid:30)(cid:10)(cid:18)(cid:30)(cid:23)(cid:9)(cid:14)(cid:9)(cid:7)(cid:23)(cid:6)(cid:12)(cid:20)(cid:3) $(cid:5)(cid:24)(cid:18)(cid:23)(cid:24)(cid:26)(cid:5)(cid:30)+(cid:14)(cid:24)(cid:26)(cid:6)(cid:23)(cid:12)(cid:23)(cid:29)(cid:20)!(cid:18)(cid:11)(cid:25)(cid:5)(cid:6)(cid:29))6 <(cid:2)(cid:27)(cid:31))  2004-2020 Microchip Technology Inc. DS20001881G-page 27

MCP6231/1R/1U/2/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20001881G-page 28  2004-2020 Microchip Technology Inc.

MCP6231/1R/1U/2/4 8-Lead Plastic Dual Flat, No Lead Package (MN) – 2x3x0.8 mm Body [TDFN] With 1.4x1.3 mm Exposed Pad (JEDEC Package type WDFN) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A B N (DATUM A) (DATUM B) E NOTE 1 2X 0.15 C 1 2 2X 0.15 C TOP VIEW 0.10 C (A3) C A SEATING PLANE 8X A1 0.08 C SIDE VIEW 0.10 C A B D2 L 1 2 0.10 C A B NOTE 1 E2 K N 8X b e 0.10 C A B 0.05 C BOTTOM VIEW Microchip Technology Drawing No. C04-129-MN Rev E Sheet 1 of 2  2004-2020 Microchip Technology Inc. DS20001881G-page 29

MCP6231/1R/1U/2/4 8-Lead Plastic Dual Flat, No Lead Package (MN) – 2x3x0.8 mm Body [TDFN] With 1.4x1.3 mm Exposed Pad (JEDEC Package type WDFN) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e 0.50 BSC Overall Height A 0.70 0.75 0.80 Standoff A1 0.00 0.02 0.05 Contact Thickness A3 0.20 REF Overall Length D 2.00 BSC Overall Width E 3.00 BSC Exposed Pad Length D2 1.35 1.40 1.45 Exposed Pad Width E2 1.25 1.30 1.35 Contact Width b 0.20 0.25 0.30 Contact Length L 0.25 0.30 0.45 Contact-to-Exposed Pad K 0.20 - - Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package may have one or more exposed tie bars at ends. 3. Package is saw singulated 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing No. C04-129-MN Rev E Sheet 2 of 2 DS20001881G-page 30  2004-2020 Microchip Technology Inc.

MCP6231/1R/1U/2/4 8-Lead Plastic Dual Flat, No Lead Package (MN) – 2x3x0.8 mm Body [TDFN] With 1.4x1.3 mm Exposed Pad (JEDEC Package type WDFN) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging X2 EV 8 ØV C Y2 EV Y1 1 2 SILK SCREEN X1 E RECOMMENDED LAND PATTERN Units MILLIMETERS Dimension Limits MIN NOM MAX Contact Pitch E 0.50 BSC Optional Center Pad Width X2 1.60 Optional Center Pad Length Y2 1.50 Contact Pad Spacing C 2.90 Contact Pad Width (X8) X1 0.25 Contact Pad Length (X8) Y1 0.85 Thermal Via Diameter V 0.30 Thermal Via Pitch EV 1.00 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. 2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process Microchip Technology Drawing No. C04-129-MN Rev. B  2004-2020 Microchip Technology Inc. DS20001881G-page 31

MCP6231/1R/1U/2/4 Note: For the mostcurrent package drawings,please seetheMicrochip Packaging Specification located at http://www.microchip.com/packaging DS20001881G-page 32  2004-2020 Microchip Technology Inc.

MCP6231/1R/1U/2/4 Note: For the mostcurrent package drawings,please seetheMicrochip Packaging Specification located at http://www.microchip.com/packaging  2004-2020 Microchip Technology Inc. DS20001881G-page 33

MCP6231/1R/1U/2/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20001881G-page 34  2004-2020 Microchip Technology Inc.

MCP6231/1R/1U/2/4 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A N B E1 NOTE 1 1 2 TOP VIEW E C A A2 PLANE L c A1 e eB 8X b1 8X b .010 C SIDE VIEW END VIEW Microchip Technology Drawing No. C04-018-P Rev E Sheet 1 of 2  2004-2020 Microchip Technology Inc. DS20001881G-page 35

MCP6231/1R/1U/2/4 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging ALTERNATE LEAD DESIGN (NOTE 5) DATUM A DATUM A b b e e 2 2 e e Units INCHES Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e .100 BSC Top to Seating Plane A - - .210 Molded Package Thickness A2 .115 .130 .195 Base to Seating Plane A1 .015 - - Shoulder to Shoulder Width E .290 .310 .325 Molded Package Width E1 .240 .250 .280 Overall Length D .348 .365 .400 Tip to Seating Plane L .115 .130 .150 Lead Thickness c .008 .010 .015 Upper Lead Width b1 .040 .060 .070 Lower Lead Width b .014 .018 .022 Overall Row Spacing § eB - - .430 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. 5. Lead design above seating plane may vary, based on assembly vendor. Microchip Technology Drawing No. C04-018-P Rev E Sheet 2 of 2 DS20001881G-page 36  2004-2020 Microchip Technology Inc.

MCP6231/1R/1U/2/4 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2X 0.10 C A–B D A D NOTE 5 N E 2 E1 2 E1 E NOTE 1 1 2 e NX b B 0.25 C A–B D NOTE 5 TOP VIEW 0.10 C C A A2 SEATING PLANE 8X 0.10 C A1 SIDE VIEW h R0.13 h R0.13 H 0.23 L SEE VIEW C (L1) VIEW A–A VIEW C Microchip Technology Drawing No. C04-057-SN Rev E Sheet 1 of 2  2004-2020 Microchip Technology Inc. DS20001881G-page 37

MCP6231/1R/1U/2/4 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e 1.27 BSC Overall Height A - - 1.75 Molded Package Thickness A2 1.25 - - Standoff § A1 0.10 - 0.25 Overall Width E 6.00 BSC Molded Package Width E1 3.90 BSC Overall Length D 4.90 BSC Chamfer (Optional) h 0.25 - 0.50 Foot Length L 0.40 - 1.27 Footprint L1 1.04 REF Foot Angle 0° - 8° Lead Thickness c 0.17 - 0.25 Lead Width b 0.31 - 0.51 Mold Draft Angle Top 5° - 15° Mold Draft Angle Bottom 5° - 15° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. 5. Datums A & B to be determined at Datum H. Microchip Technology Drawing No. C04-057-SN Rev E Sheet 2 of 2 DS20001881G-page 38  2004-2020 Microchip Technology Inc.

MCP6231/1R/1U/2/4 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging SILK SCREEN C Y1 X1 E RECOMMENDED LAND PATTERN Units MILLIMETERS Dimension Limits MIN NOM MAX Contact Pitch E 1.27 BSC Contact Pad Spacing C 5.40 Contact Pad Width (X8) X1 0.60 Contact Pad Length (X8) Y1 1.55 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-2057-SN Rev E  2004-2020 Microchip Technology Inc. DS20001881G-page 39

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MCP6231/1R/1U/2/4 14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2X 0.10 C A–B D A NOTE 5 D N E 2 E2 2 E1 E 2X 0.10 C D 2X N/2 TIPS NOTE 1 1 2 3 0.20 C e NX b B NOTE 5 0.25 C A–B D TOP VIEW 0.10 C C A A2 SEATING PLANE 14X A1 SIDE VIEW 0.10 C h h H R0.13 R0.13 c SEE VIEW C L VIEW A–A (L1) VIEW C Microchip Technology Drawing No. C04-065-SL Rev D Sheet 1 of 2  2004-2020 Microchip Technology Inc. DS20001881G-page 41

MCP6231/1R/1U/2/4 14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 14 Pitch e 1.27 BSC Overall Height A - - 1.75 Molded Package Thickness A2 1.25 - - Standoff § A1 0.10 - 0.25 Overall Width E 6.00 BSC Molded Package Width E1 3.90 BSC Overall Length D 8.65 BSC Chamfer (Optional) h 0.25 - 0.50 Foot Length L 0.40 - 1.27 Footprint L1 1.04 REF Lead Angle 0° - - Foot Angle 0° - 8° Lead Thickness c 0.10 - 0.25 Lead Width b 0.31 - 0.51 Mold Draft Angle Top 5° - 15° Mold Draft Angle Bottom 5° - 15° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimension D does not include mold flash, protrusions or gate burrs, which shall not exceed 0.15 mm per end. Dimension E1 does not include interlead flash or protrusion, which shall not exceed 0.25 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. 5. Datums A & B to be determined at Datum H. Microchip Technology Drawing No. C04-065-SL Rev D Sheet 2 of 2 DS20001881G-page 42  2004-2020 Microchip Technology Inc.

MCP6231/1R/1U/2/4 14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 14 SILK SCREEN C Y 1 2 X E RECOMMENDED LAND PATTERN Units MILLIMETERS Dimension Limits MIN NOM MAX Contact Pitch E 1.27 BSC Contact Pad Spacing C 5.40 Contact Pad Width (X14) X 0.60 Contact Pad Length (X14) Y 1.55 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-2065-SL Rev D  2004-2020 Microchip Technology Inc. DS20001881G-page 43

MCP6231/1R/1U/2/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20001881G-page 44  2004-2020 Microchip Technology Inc.

MCP6231/1R/1U/2/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2004-2020 Microchip Technology Inc. DS20001881G-page 45

MCP6231/1R/1U/2/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20001881G-page 46  2004-2020 Microchip Technology Inc.

MCP6231/1R/1U/2/4 APPENDIX A: REVISION HISTORY Revision C (March 2005) The following is the list of modifications: Revision G (March 2020) 1. Added the MCP6234 quad op amp. The following is the list of modifications: 2. Corrected plots in Section2.0 “Typical 1. Updated package drawings for the SC-70 Performance Curves”. package. 3. Added Section3.0 “Pin Descriptions”. 4. Added new SC-70 package markings. Added Revision F (October 2019) PDIP-14, SOIC-14, and TSSOP-14 packages and corrected package marking information The following is the list of modifications: (Section6.0 “Packaging Information”). 1. Updated Section6.0 “Packaging 5. Added Appendix A: “Revision History”. Information”. Revision B (August 2004) Revision E (August 2009) • Undocumented changes. The following is the list of modifications: 1. Added the 2x3 TDFN package for MCP6232. Revision A (March 2004) 2. Updated the 2x3 DFN package information for • Original Release of this Document. MCP6231. 3. Updated the “Temperature Characteristics” table. 4. Updated Section3.0 “Pin Descriptions”. 5. Updated the Package Outline Drawings in Section6.0 “Packaging Information”. 6. Updated the Product Identification System section. Revision D (May 2008) The following is the list of modifications: 1. Changed Heading “Available Tools” to “Design Aids”. 2. Design Aids: Name change for Mindi Simulator Tool. 3. Package Types: Added DFN to MCP6231 Device. 4. Absolute Maximum Ratings: Numerous changes in this section. 5. Updated notes to Section1.0 “Electrical Characteristics”. 6. Added Test Circuits to Section1.0 “Electrical Characteristics”. 7. Corrected Figure 2-7. 8. Added Figure2-19. 9. Numerous changes to Section3.0 “Pin Descriptions”. 10. Added Section4.1.1 “Phase Reversal”, Section4.1.2 “Input Voltage and Current Limits”, and Section4.1.3 “Normal Operation”. 11. Replaced Section5.0 “Design Aids” with additional information. 12. Updated Section6.0 “Packaging Information” with updated Package Outline Drawings.  2004-2020 Microchip Technology Inc. DS20001881G-page 47

MCP6231/1R/1U/2/4 NOTES: DS20001881G-page 48  2004-2020 Microchip Technology Inc.

MCP6231/1R/1U/2/4 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X -X /XX Examples: a) MCP6231-E/MC: Extended Temperature, Device Tape and Reel Temperature Package 8LD DFN package and/or Range b) MCP6231-E/MS: Extended Temperature, Alternate Pinout 8LD MSOP package c) MCP6231UT-E/LT: Tape and Reel, Device: MCP6231: Single Op Amp (MSOP, PDIP, SOIC) Extended Temperature, MCP6231T: Single Op Amp (Tape and Reel) 5LD SC70 package (MSOP, SOIC, SOT-23) d) MCP6231-E/P: Extended Temperature, MCP6231RT: Single Op Amp (Tape and Reel) 8LD PDIP package (SOT-23) MCP6231UT: Single Op Amp (Tape and Reel) e) MCP6231RT-E/OT: Tape and Reel, (SC70, SOT-23, TDFN) Extended Temperature, MCP6232: Dual Op Amp 5LD SOT-23 package MCP6232T: Dual Op Amp (Tape and Reel) f) MCP6231UT-E/OT: Tape and Reel, (MSOP, SOIC) Extended Temperature, MCP6234: Quad Op Amp 5LD SOT-23 package MCP6234T: Quad Op Amp (Tape and Reel) (TSSOP, SOIC) g) MCP6231-E/SN: Extended Temperature, 8LD SOIC package Temperature Range: E = -40°C to +125°C a) MCP6232-E/SN: Extended Temperature, 8LD SOIC package b) MCP6232-E/MS: Extended Temperature, Package: LT = Plastic Package (SC70), 5-Lead (MCP6231U only) 8LD MSOP package MC = Plastic Dual Flat No Lead (DFN) 2x3 mm, 8-Lead (MCP6231 only) c) MCP6232-E/P: Extended Temperature, MN = Plastic Dual Flat No Lead (TDFN) 2x3 mm, 8-Lead 8LD PDIP package (MCP6232 only) d) MCP6232T-E/SN: Tape and Reel, MS = Plastic Micro Small Outline (MSOP), 8-Lead Extended Temperature, P = Plastic DIP (300 mil Body), 8-Lead, 14-Lead 8LD SOIC package OT = Plastic Small Outline Transistor (SOT-23), 5-Lead (MCP6231, MCP6231R, MCP6231U) e) MCP6232T-E/MNY:Tape and Reel, SN = Plastic SOIC (150 mil Body), 8-Lead Extended Temperature, SL = Plastic SOIC (3.90 mm), 14-Lead 8LD TDFN package ST = Plastic TSSOP (4.4 mm Body), 14-Lead a) MCP6234-E/P: Extended Temperature, 14LD PDIP package b) MCP6234-E/SL: Extended Temperature, 14LD SOIC package c) MCP6234-E/ST: Extended Temperature, 14LD TSSOP package d) MCP6234T-E/SL: Tape and Reel, Extended Temperature, 14LD SOIC package e) MCP6234T-E/ST: Tape and Reel, Extended Temperature, 14LD TSSOP package  2004-2020 Microchip Technology Inc. DS20001881G-page 49

MCP6231/1R/1U/2/4 NOTES: DS20001881G-page 50  2004-2020 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, Adaptec, and may be superseded by updates. It is your responsibility to AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT, ensure that your application meets with your specifications. chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, MICROCHIP MAKES NO REPRESENTATIONS OR LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, WARRANTIES OF ANY KIND WHETHER EXPRESS OR Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, IMPLIED, WRITTEN OR ORAL, STATUTORY OR PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, OTHERWISE, RELATED TO THE INFORMATION, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, INCLUDING BUT NOT LIMITED TO ITS CONDITION, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA QUALITY, PERFORMANCE, MERCHANTABILITY OR are registered trademarks of Microchip Technology Incorporated in FITNESS FOR PURPOSE. Microchip disclaims all liability the U.S.A. and other countries. arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at APT, ClockWorks, The Embedded Control Solutions Company, the buyer’s risk, and the buyer agrees to defend, indemnify and EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision hold harmless Microchip from any and all damages, claims, Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, suits, or expenses resulting from such use. No licenses are SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, conveyed, implicitly or otherwise, under any Microchip TimePictra, TimeProvider, Vite, WinPath, and ZL are registered intellectual property rights unless otherwise stated. trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2004-2020, Microchip Technology Incorporated, All Rights Reserved. For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality. ISBN: 978-1-5224-5810-4  2004-2020 Microchip Technology Inc. DS20001881G-page 51

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