MCP6141/2/3/4 600 nA, Non-Unity Gain Rail-to-Rail Input/Output Op Amps Features Description • Low Quiescent Current: 600nA/amplifier (typical) The MCP6141/2/3/4 family of non-unity gain stable • Gain Bandwidth Product: 100kHz (typical) operational amplifiers (op amps) from Microchip Technology Inc. operate with a single supply voltage as • Stable for gains of 10V/V or higher low as 1.4V, while drawing less than 1µA (maximum) • Rail-to-Rail Input/Output of quiescent current per amplifier. These devices are • Wide Supply Voltage Range: 1.4V to 6.0V also designed to support rail-to-rail input and output • Available in Single, Dual, and Quad operation. This combination of features supports • Chip Select (CS) with MCP6143 battery-powered and portable applications. • Available in 5-lead and 6-lead SOT-23 Packages The MCP6141/2/3/4 amplifiers have a gain bandwidth • Temperature Ranges: product of 100kHz (typical) and are stable for gains of - Industrial: -40°C to +85°C 10V/V or higher. These specifications make these op amps appropriate for battery powered applications - Extended: -40°C to +125°C where a higher frequency response from the amplifier is required. Applications The MCP6141/2/3/4 family operational amplifiers are • Toll Booth Tags offered in single (MCP6141), single with Chip Select • Wearable Products (CS) (MCP6143), dual (MCP6142) and quad (MCP6144) configurations. The MCP6141 device is • Temperature Measurement available in the 5-lead SOT-23 package, and the • Battery Powered MCP6143 device is available in the 6-lead SOT-23 package. Design Aids • SPICE Macro Models Package Types • FilterLab® Software MCP6141 MCP6143 • Mindi™ Simulation Tool PDIP, SOIC, MSOP PDIP, SOIC, MSOP • Microchip Advanced Part Selector (MAPS) NC 1 8 NC NC 1 8 CS • Analog Demonstration and Evaluation Boards VIN– 2 – 7 VDD VIN– 2 – 7 VDD • Application Notes + + VIN+ 3 6 VOUT VIN+ 3 6 VOUT Related Devices VSS 4 5 NC VSS 4 5 NC MCP6141 MCP6143 • MCP6041/2/3/4: Unity Gain Stable Op Amps SOT-23-5 SOT-23-6 Typical Application VOUT 1 5 VDD VOUT 1 6 VDD VSS 2 +– VSS 2 +– 5 CS R 1 V + 3 4 V – V + 3 4 V – IN IN IN IN V 1 R MCP6142 MCP6144 2 PDIP, SOIC, MSOP PDIP, SOIC, TSSOP V R 2 F R3 VOUT VOUTA 1 8 VDD VOUTA 1 14 VOUTD V3 – VINA– 2 7 VOUTB VINA– 2 13 VIND– MCP614X VINA+ 3 6 VINB– VINA+ 3 12 VIND+ V + VSS 4 5 VINB+ VDD 4 11 VSS REF V + 5 10 V + INB INC V – 6 9 V – Inverting,SummingAmplifier INB INC V 7 8 V OUTB OUTC  2019 Microchip Technology Inc. DS20001668E-page 1

MCP6141/2/3/4 NOTES: DS20001668E-page 2  2019 Microchip Technology Inc.

MCP6141/2/3/4 1.0 ELECTRICAL † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the CHARACTERISTICS device. This is a stress rating only and functional operation of the device at those or any other conditions above those Absolute Maximum Ratings † indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended VDD–VSS........................................................................7.0V periods may affect device reliability. Current at Analog Input Pins.........................................±2mA †† See Section4.1.2 “Input Voltage and Current Limits”. Analog Inputs (V +, V –)††........V –1.0VtoV +1.0V IN IN SS DD All Other Inputs and Outputs .........V –0.3V to V +0.3V SS DD Difference Input Voltage ......................................|V –V | DD SS Output Short Circuit Current ................................Continuous Current at Output and Supply Pins ............................±30mA Storage Temperature...................................–65°C to +150°C Maximum Junction Temperature (T )..........................+150°C J ESD Protection On All Pins (HBM; MM) 4kV; 400V DC ELECTRICAL CHARACTERISTICS Electrical Characteristics: Unless otherwise indicated, V =+1.4V to +5.5V, V =GND, T =+25°C, V =V /2, DD SS A CM DD V V /2, V =V /2, R = 1Mto V and CS is tied low (refer to Figure1-2 and Figure1-3). OUT DD L DD L L Parameters Sym Min Typ Max Units Conditions Input Offset Input Offset Voltage V –3 — +3 mV V = V OS CM SS Drift with Temperature V /T — ±1.8 — µV/°C V = V , T = -40°C to +85°C OS A CM SS A V /T — ±10 — µV/°C V = V , OS A CM SS T = +85°C to +125°C A Power Supply Rejection PSRR 70 85 — dB V = V CM SS Input Bias Current and Impedance Input Bias Current I — 1 — pA B Industrial Temperature I — 20 100 pA T = +85° B A Extended Temperature I — 1200 5000 pA T = +125° B A Input Offset Current I — 1 — pA OS Common-mode Input Impedance Z — 1013||6 — ||pF CM Differential Input Impedance Z — 1013||6 — ||pF DIFF Common-mode Common-mode Input Range V V 0.3 — V +0.3 V CMR SS DD Common-mode Rejection Ratio CMRR 62 80 — dB V = 5V, V = -0.3V to 5.3V DD CM CMRR 60 75 — dB V = 5V, V = 2.5V to 5.3V DD CM CMRR 60 80 — dB V = 5V, V = -0.3V to 2.5V DD CM Open-Loop Gain DC Open-Loop Gain (large signal) A 95 115 — dB R = 50k to V , OL L L V = 0.1V to V 0.1V OUT DD Output Maximum Output Voltage Swing V , V V +10 — V 10 mV R = 50k to V , OL OH SS DD L L 0.5V input overdrive Linear Region Output Voltage Swing V V +100 — V 100 mV R = 50k to V , OVR SS DD L L A  95dB OL Output Short Circuit Current I — 2 — mA V = 1.4V SC DD I — 20 — mA V = 5.5V SC DD Power Supply Supply Voltage V 1.4 — 6.0 V Note1 DD Quiescent Current per Amplifier I 0.3 0.6 1.0 µA I = 0 Q O Note 1: All parts with date codes February 2008 and later have been screened to ensure operation at VDD = 6.0V. However, the other minimum and maximum specifications are measured at 1.8V and 5.5V  2019 Microchip Technology Inc. DS20001668E-page 3

MCP6141/2/3/4 AC ELECTRICAL CHARACTERISTICS Electrical Characteristics: Unless otherwise indicated, V =+1.4V to +5.5V, V =GND, T =+25°C, V =V /2, DD SS A CM DD V V /2, V =V /2, R = 1Mto V , C =60pF and CS is tied low (refer to Figure1-2 and Figure1-3). OUT DD L DD L L L Parameters Sym Min Typ Max Units Conditions AC Response Gain Bandwidth Product GBWP — 100 — kHz Slew Rate SR — 24 — V/ms Phase Margin PM — 60 — ° G = +10V/V Noise Input Voltage Noise E — 5.0 — µV f = 0.1Hz to 10Hz ni P-P Input Voltage Noise Density e — 170 — nV/Hz f = 1kHz ni Input Current Noise Density i — 0.6 — fA/Hz f = 1kHz ni MCP6143 CHIP SELECT (CS) ELECTRICAL CHARACTERISTICS Electrical Characteristics: Unless otherwise indicated, V =+1.4V to +5.5V, V =GND, T =+25°C, V =V /2, DD SS A CM DD V V /2, V =V /2, R = 1Mto V , and C =60pF (refer to Figure1-2 and Figure1-3). OUT DD L DD L L L Parameters Sym Min Typ Max Units Conditions CS Low Specifications CS Logic Threshold, Low V V — V +0.3 V IL SS SS CS Input Current, Low I — 5 — pA CS = V CSL SS CS High Specifications CS Logic Threshold, High V V –0.3 — V V IH DD DD CS Input Current, High I — 5 — pA CS = V CSH DD CS Input High, GND Current I — –20 — pA CS = V SS DD Amplifier Output Leakage, CS High I — 20 — pA CS = V OLEAK DD Dynamic Specifications CS Low to Amplifier Output Turn-on Time t — 2 50 ms G = +1V/V, CS = 0.3V to ON V = 0.9V /2 OUT DD CS High to Amplifier Output High-Z t — 10 — µs G = +1V/V, CS = V –0.3V to OFF DD V = 0.1V /2 OUT DD Hysteresis V — 0.6 — V V = 5.0V HYST DD CS VIL VIH t t OFF ON VOUT High-Z High-Z -0.6µA (typical) ISS -20pA -20pA (typical) (typical) I 5pA (typical) 5pA (typical) CS FIGURE 1-1: Chip Select (CS) Timing Diagram (MCP6143 only). DS20001668E-page 4  2019 Microchip Technology Inc.

MCP6141/2/3/4 TEMPERATURE CHARACTERISTICS Electrical Characteristics: Unless otherwise indicated, V =+1.4V to +5.5V, V =GND. DD SS Parameters Sym. Min. Typ. Max. Units Conditions Temperature Ranges Specified Temperature Range T -40 — +85 °C Industrial Temperature parts A T -40 — +125 °C Extended Temperature parts A Operating Temperature Range T -40 — +125 °C (Note1) A Storage Temperature Range T -65 — +150 °C A Thermal Package Resistances Thermal Resistance, 5L-SOT-23  — 256 — °C/W JA Thermal Resistance, 6L-SOT-23  — 230 — °C/W JA Thermal Resistance, 8L-MSOP  — 206 — °C/W JA Thermal Resistance, 8L-PDIP  — 85 — °C/W JA Thermal Resistance, 8L-SOIC  — 163 — °C/W JA Thermal Resistance, 14L-PDIP  — 70 — °C/W JA Thermal Resistance, 14L-SOIC  — 120 — °C/W JA Thermal Resistance, 14L-TSSOP  — 100 — °C/W JA Note 1: The MCP6141/2/3/4 family of Industrial Temperature op amps operates over this extended range, but with reduced performance. In any case, the internal Junction Temperature (T ) must not exceed the Absolute J Maximum specification of +150°C. 1.1 Test Circuits The test circuits used for the DC and AC tests are shown in Figure1-2 and Figure1-2. The bypass capacitors are laid out according to the rules discussed in Section4.6 “Supply Bypass”. VDD 1µF V 0.1µF IN + RN VOUT MCP614X – C R L L VDD/2 RG RF V L FIGURE 1-2: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. VDD 1µF V /2 0.1µF DD + RN VOUT MCP614X – C R L L VIN RG RF V L FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions.  2019 Microchip Technology Inc. DS20001668E-page 5

MCP6141/2/3/4 NOTES: DS20001668E-page 6  2019 Microchip Technology Inc.

MCP6141/2/3/4 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, T =+25°C, V =+1.4V to +5.5V, V =GND, V =V /2, V V /2, A DD SS CM DD OUT DD V =V /2, R =1M to V , C =60pF, and CS is tied low. L DD L L L Occurrences106789%%%%% 2V3C9M6 = S VaSmSples Occurrences111012789%%%%%% 2RVVT3ADCe 4DMp= r= S=+e a18sVm.5eS4°nSpVCtlae ttsoiv +e1 L2o5t°C ntage of 345%%% ntage of 3456%%%% erce 12%% erce 2% P P 1% 0% 0% -3 -2 -1 0 1 2 3 -10 -8 -6 -4 -2 0 2 4 6 8 10 Input Offset Voltage (mV) Input Offset Voltage Drift (µV/°C) FIGURE 2-1: Input Offset Voltage. FIGURE 2-4: Input Offset Voltage Drift with T =+85°C to +125°C and V =1.4V. A DD 12% 16% ccurrences1101789%%%%% 2TV2AC 6M=7 =- S4 V0aS°mSCp tloe s+85°C ccurrences 111024%%% 2RVVT3ADCe 4DMp= =r S=+e a58sVm.5eS5°SnpVCtlae ttsoiv +e1 L2o5t°C O O ge of 456%%% ge of 68%% a a nt 3% nt 4% ce 2% ce Per 1% Per 2% 0% 0% -10 -8 -6 -4 -2 0 2 4 6 8 10 -10 -8 -6 -4 -2 0 2 4 6 8 10 Input Offset Voltage Drift (µV/°C) Input Offset Voltage Drift (µV/°C) FIGURE 2-2: Input Offset Voltage Drift FIGURE 2-5: Input Offset Voltage Drift with T =-40°C to +85°C. with T =+85°C to +125°C and V =5.5V. A A DD 1000 1000 Input Offset Voltage (µV) ----2468864200000000000000000 VDD = 1.4V TTAA == +-4250°°CCTTA A= = + +18255°°CC Input Offset Voltage (µV) ----2468864200000000000000000 VDD = 5.5V TTATA TA == A = + -= 42+ 50+1°°82CC55°°CC -1000 -1000 4 2 0 2 4 6 8 0 2 4 6 8 5 0 5 0 5 0 5 0 5 0 5 0 5 0 0. 0. 0. 0. 0. 0. 0. 1. 1. 1. 1. 1. 0. 0. 0. 1. 1. 2. 2. 3. 3. 4. 4. 5. 5. 6. - - - Common Mode Input Voltage (V) Common Mode Input Voltage (V) FIGURE 2-3: Input Offset Voltage vs. FIGURE 2-6: Input Offset Voltage vs. Common-mode Input Voltage with V =1.4V. Common-mode Input Voltage with V =5.5V. DD DD  2019 Microchip Technology Inc. DS20001668E-page 7

MCP6141/2/3/4 Note: Unless otherwise indicated, T =+25°C, V =+1.4V to +5.5V, V =GND, V =V /2, V V /2, A DD SS CM DD OUT DD V =V /2, R =1M to V , C =60pF, and CS is tied low. L DD L L L 500 6 Offset Voltage (µV) 344505000 VDD = 1.4V utput Voltages (V) 2345 VGD =D =+ 151.0 VV/V VIN Input 300 VDD = 5.5V nput, O 01 VOUT 250 I 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -1 Output Voltage (V) 0 5 Ti1m0e (5 ms/1d5iv) 20 25 FIGURE 2-7: Input Offset Voltage vs. FIGURE 2-10: The MCP6141/2/3/4 Family Output Voltage. Shows No Phase Reversal. 1,000 300 Input Noise Voltage Density(nV/Hz) 100 Input Noise Voltage Density(nV/Hz)112205055000000 fV =DD 1 = k 5H.z0V 5 0 5 0 5 0 5 0 5 0 5 0 5 0.1 1 10 100 1000 0. 0. 0. 1. 1. 2. 2. 3. 3. 4. 4. 5. 5. - Frequency (Hz) Common Mode Input Voltage (V) FIGURE 2-8: Input Noise Voltage Density FIGURE 2-11: Input Noise Voltage Density vs. Frequency. vs. Common-mode Input Voltage. 100 100 PSRR– 90 PSRR+ 95 CMRR R (dB) 7800 R (dB) 90 PSRR (VCM = VSS) R R S 60 M 85 P C MRR, 50 SRR, 80 CMRR (VDD = 5.0V, C 40 P 75 VCM = -0.3V to +5.3V) 30 Referred to Input 70 20 1 10 100 1k 10k -50 -25 0 25 50 75 100 125 1 10 100 1,000 10,000 Frequency (Hz) Ambient Temperature (°C) FIGURE 2-9: CMRR, PSRR vs. FIGURE 2-12: CMRR, PSRR vs. Ambient Frequency. Temperature. DS20001668E-page 8  2019 Microchip Technology Inc.

MCP6141/2/3/4 Note: Unless otherwise indicated, T =+25°C, V =+1.4V to +5.5V, V =GND, V =V /2, V V /2, A DD SS CM DD OUT DD V =V /2, R =1M to V , C =60pF, and CS is tied low. L DD L L L 1001000k 1001000k nts VDD = 5.5V s VDD = 5.5V Input Bias and Offset Curre(pA)101100001110..10001110k0 VCM = VDD IB | IOS | Input Bias, Offset Current(pA)101100001011..000111100k TTAA == ++8152°5C°C | IOS |IB 45 55 65 75 85 95 105 115 125 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Ambient Temperature (°C) Common Mode Input Voltage (V) FIGURE 2-13: Input Bias, Offset Currents FIGURE 2-16: Input Bias, Offset Currents vs. Ambient Temperature. vs. Common-mode Input Voltage. 120 0 130 ain (dB)1068000 Phase ---963000 hase (°) Gain (dB)111200 VDD = 5.5V Open-Loop G -2240000 Gain ----211118520000 Open-Loop P C Open-Loop 107890000 VDD = 1.4V D VOUT = 0.1V to VDD – 0.1V -40 -240 60 01..0E1- 10..E1- 1.1E+ 11.E0+ 11.0E0+ 11.Ek+ 11.0Ek+ 110.E0+k 1.1E0+002 1.E1+k03 1.1E0+k04 11.E0+00k5 02 01 00Fre0q1uenc0y2 (Hz)03 04 05 Load Resistance (Ω) FIGURE 2-14: Open-Loop Gain, Phase vs. FIGURE 2-17: DC Open-Loop Gain vs. Frequency. Load Resistance. 140 140 n (dB)130 ain (dB) 112300 RL = 50 kΩ VDD = 5.5V ai120 G G p 110 p o en-Loo110100 pen-Lo 10900 VDD = 1.4V DC Op 90 RVOL U=T 5=0 0 k.1ΩV to VDD – 0.1V DC O 7800 80 0.00 0.05 0.10 0.15 0.20 0.25 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Output Voltage Headroom; Power Supply Voltage (V) VDD – VOH or VOL – VSS (V) FIGURE 2-15: DC Open-Loop Gain vs. FIGURE 2-18: DC Open-Loop Gain vs. Power Supply Voltage. Output Voltage Headroom.  2019 Microchip Technology Inc. DS20001668E-page 9

MCP6141/2/3/4 Note: Unless otherwise indicated, T =+25°C, V =+1.4V to +5.5V, V =GND, V =V /2, V V /2, A DD SS CM DD OUT DD V =V /2, R =1M to V , C =60pF, and CS is tied low. L DD L L L 140 120 120 110 110 130 uct 100 100 Channel-to-ChannelSeparation (dB) 11101290000 Gain Bandwidth Prod(kHz) 123456789000000000 V(DGGD =PB= M W+51.P00V) 123456789000000000 Phase Margin (°) Input Referred 0 0 80 5 0 5 0 5 0 5 0 5 0 5 0 5 1k 10k 0. 0. 0. 1. 1. 2. 2. 3. 3. 4. 4. 5. 5. 1.E+03 1.E+04 - Frequency (Hz) Common Mode Input Voltage FIGURE 2-19: Channel to Channel FIGURE 2-22: Gain Bandwidth Product, Separation vs. Frequency (MCP6142 and Phase Margin vs. Common-mode Input Voltage. MCP6144 only). 90 90 90 90 dwidth Product(kHz)4567800000 GBWP (G =P M+10) 4567800000 e Margin (°) dwidth Product(kHz) 4567800000 GBWP (G =P M+10) 4567800000 e Margin (°) n Ban 2300 2300 Phas n Ban 2300 2300 Phas Gai 10 VDD = 1.4V 10 Gai 10 VDD = 5.5V 10 0 0 0 0 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 Ambient Temperature (°C) Ambient Temperature (°C) FIGURE 2-20: Gain Bandwidth Product, FIGURE 2-23: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature with Phase Margin vs. Ambient Temperature with V =1.4V. V =5.5V. DD DD 0.8 35 nt TA = -40°C Quiescent Current(µA/Amplifier) 000000......234567 TTTA AA= == + ++1282555°°°CCC ut Short Circuit CurreMagnitude (mA)1122305050 TTTA AA= == + ++1282555°°°CCC 0.1 TA = -40°C utp 5 O 0.0 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Power Supply Voltage (V) Ambient Temperature (°C) FIGURE 2-21: Quiescent Current vs. FIGURE 2-24: Output Short Circuit Current Power Supply Voltage. vs. Power Supply Voltage. DS20001668E-page 10  2019 Microchip Technology Inc.

MCP6141/2/3/4 Note: Unless otherwise indicated, T =+25°C, V =+1.4V to +5.5V, V =GND, V =V /2, V V /2, A DD SS CM DD OUT DD V =V /2, R =1M to V , C =60pF, and CS is tied low. L DD L L L 1000 5.0 ge Headroom;V – V (mV)OLSS 100 ge Headroom,V – V (mV)OLSS 23344.....50505 VRDL D= = 5 50. 5kVΩ VOL – VVSDSD – VOH Output VoltaV – V or DDOH 10 VDD – VOH VOL – VSS Output VoltaV – V or DDOH 0112....5050 1 0.0 0.01 0.1 1 10 -50 -25 0 25 50 75 100 125 Output Current Magnitude (mA) Ambient Temperature (°C) FIGURE 2-25: Output Voltage Headroom FIGURE 2-28: Output Voltage Headroom vs. Output Current Magnitude. vs. Ambient Temperature. 40 10 35 ge w Rate (V/ms) 12235050 VDD = 5.5V High-to-Low m Output Voltawing (V)P-P 1 VVDDDD == 51..54VV Sle 10 Low-to-High muS xi 5 VDD = 1.4V Ma 0 0.1 -50 -25 0 25 50 75 100 125 100 1k 10k 1.E+02 1.E+03 1.E+04 Ambient Temperature (°C) Frequency (Hz) FIGURE 2-26: Slew Rate vs. Ambient FIGURE 2-29: Maximum Output Voltage Temperature. Swing vs. Frequency. 80 80 G = +11 V/V G = -10 V/V v)60 RL = 50 kΩ 60 RL = 50 kΩ di V/40 v)40 m di 0 20 V/20 2 m ge (0 20 0 -olta20 -ge (20 V a -ut 40 -olt40 p V -Out60 -60 -80 -80 0.0 0.1 0.2 0.3Ti0m.4e (100.05 µs0/d.6iv)0.7 0.8 0.9 1.0 0.0 0.1 0.2 0.3Ti0m.4e (100.05 µs0/d.6iv)0.7 0.8 0.9 1.0 FIGURE 2-27: Small Signal Non-inverting FIGURE 2-30: Small Signal Inverting Pulse Pulse Response. Response.  2019 Microchip Technology Inc. DS20001668E-page 11

MCP6141/2/3/4 Note: Unless otherwise indicated, T =+25°C, V =+1.4V to +5.5V, V =GND, V =V /2, V V /2, A DD SS CM DD OUT DD V =V /2, R =1M to V , C =60pF, and CS is tied low. L DD L L L 5.0 5.0 4.5 VDD = 5.0V 4.5 VDD = 5.0V G = +11 V/V G = -10 V/V 4.0 RL = 50 kΩ 4.0 RL = 50 kΩ e (V) 3.5 e (V) 3.5 g 3.0 g 3.0 a a olt 2.5 olt 2.5 V V ut 2.0 ut 2.0 p p ut 1.5 ut 1.5 O O 1.0 1.0 0.5 0.5 0.0 0.0 0 0 0 1Tim1e (2010 µs/1div)1 2 2 2 0 0 0 1Tim1e (2010 µs/1div)1 2 2 2 FIGURE 2-31: Large Signal Non-inverting FIGURE 2-34: Large Signal Inverting Pulse Pulse Response. Response. 25.0 5.0 5.5 122702...505 On VGVDI N=D = =+ + 1531.0. 0VVV/V On 344...505e (V) Output (V) 445...050 VOUT On Hysteresis oltage (V)11102557.....05005 High-Z VOUT 11223.....05050Output Voltag nternal CS Switch 0112233.......5050505 VGVDI N=D = =+ 3 15.1H0.0 iVVgV/hV-CtoS-Low Low-CtoS-HigVhOUT High-Z S V 2.5 CS 0.5 I 0.0 C 0.0 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 1 2 3Tim4e (15 ms6/div)7 8 9 10 CS Voltage (V) FIGURE 2-32: Chip Select (CS) to FIGURE 2-35: Internal Chip Select (CS) Amplifier Output Response Time (MCP6143 Hysteresis (MCP6143 only). only). 1.E1-00m2 A)1.E-10m3 e (1.E10-004µ d nitu1.E1-005µ g1.E-016µ a M1.1E0-007n ent 1.E1-008n urr1.E-019n +125°C C +85°C ut 1.1E0-100p +25°C np1.E1-101p -40°C I1.E-112p -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 Input Voltage (V) FIGURE 2-33: Input Current vs. Input Voltage (Below V ). SS DS20001668E-page 12  2019 Microchip Technology Inc.

MCP6141/2/3/4 3.0 PIN DESCRIPTIONS Descriptions of the pins are listed in Table3-1. TABLE 3-1: PIN FUNCTION TABLE MCP6141 MCP6142 MCP6143 MCP6144 MSOP, MSOP, MSOP, MSOP, Symbol Description PDIP, SOT-23-5 PDIP, PDIP, SOT-23-6 PDIP, SOIC SOIC SOIC SOIC 6 1 1 6 1 1 V ,V Analog Output (op amp A) OUT OUTA 2 4 2 2 4 2 V –,V – Inverting Input (op amp A) IN INA 3 3 3 3 3 3 V +,V + Non-inverting Input (op amp A) IN INA 7 5 8 7 6 4 V Positive Power Supply DD — — 5 — — 5 V + Non-inverting Input (op amp B) INB — — 6 — — 6 V – Inverting Input (op amp B) INB — — 7 — — 7 V Analog Output (op amp B) OUTB — — — — — 8 V Analog Output (op amp C) OUTC — — — — — 9 V – Inverting Input (op amp C) INC — — — — — 10 V + Non-inverting Input (op amp C) INC 4 2 4 4 2 11 V Negative Power Supply SS — — — — — 12 V + Non-inverting Input (op amp D) IND — — — — — 13 V – Inverting Input (op amp D) IND — — — — — 14 V Analog Output (op amp D) OUTD — — — 8 5 — CS Chip Select 1, 5, 8 — — 1, 5 — — NC No Internal Connection 3.1 Analog Outputs 3.4 Power Supply Pins The output pins are low-impedance voltage sources. The positive power supply pin (V ) is 1.4V to 6.0V DD higher than the negative power supply pin (V ). For SS 3.2 Analog Inputs normal operation, the other pins are at voltages between V and V . SS DD The non-inverting and inverting inputs are Typically, these parts are used in a single (positive) high-impedance CMOS inputs with low bias currents. supply configuration. In this case, V is connected to SS ground and V is connected to the supply. V will 3.3 CS Digital Input DD DD need bypass capacitors. This is a CMOS, Schmitt-triggered input that places the part into a low power mode of operation.  2019 Microchip Technology Inc. DS20001668E-page 13

MCP6141/2/3/4 NOTES: DS20001668E-page 14  2019 Microchip Technology Inc.

MCP6141/2/3/4 4.0 APPLICATIONS INFORMATION dump any currents onto V . When implemented as DD shown, resistors R and R also limit the current 1 2 The MCP6141/2/3/4 family of op amps is manufactured through D and D . 1 2 using Microchip’s state of the art CMOS process These op amps are stable for gains of 10V/V and higher. They are suitable for a wide range of general purpose, low VDD power applications. See Microchip’s related MCP6041/2/3/4 family of op D 1 amps for applications needing unity gain stability. V 1 + R 4.1 Rail-to-Rail Input 1 D2 MCP604X VOUT V – 2 4.1.1 PHASE REVERSAL R 2 The MCP6141/2/3/4 op amps are designed to not exhibit phase inversion when the input pins exceed the VSS–(minimumexpectedV1) R > supply voltages. Figure2-10 shows an input voltage 1 2mA exceeding both supplies with no phase inversion. V –(minimumexpectedV ) SS 2 R > 2 2mA 4.1.2 INPUT VOLTAGE AND CURRENT LIMITS FIGURE 4-2: Protecting the Analog Inputs. The ESD protection on the inputs can be depicted as shown in Figure4-1. This structure was chosen to It is also possible to connect the diodes to the left of the protect the input transistors, and to minimize input bias resistor R and R . In this case, the currents through 1 2 current (IB). The input ESD diodes clamp the inputs the diodes D1 and D2 need to be limited by some other when they try to go more than one diode drop below mechanism. The resistors then serve as in-rush current VSS. They also clamp any voltages that go too far limiters; the DC current into the input pins (VIN+ and above VDD; their breakdown voltage is high enough to VIN–) should be very small. allow normal operation and low enough to bypass quick A significant amount of current can flow out of the ESD events within the specified limits. inputs (through the ESD diodes) when the Common- mode voltage (V ) is below ground (V ); see CM SS Figure2-33. Applications that are high impedance may Bond VDD need to limit the usable voltage range. Pad 4.1.3 NORMAL OPERATION The input stage of the MCP6141/2/3/4 op amps uses Bond Input Bond V + V – two differential input stages in parallel. One operates at IN Pad Stage Pad IN a low Common-mode input voltage (V ), while the CM other operates at a high V . With this topology, the CM device operates with a V up to 300mV above V CM DD Bond and 300mV below V . The input offset voltage is V SS SS Pad measured at V =V –0.3V and V +0.3V to CM SS DD ensure proper operation. FIGURE 4-1: Simplified Analog Input ESD There are two transitions in input behavior as V is CM Structures. changed. The first occurs, when V is near CM V +0.4V, and the second occurs when V is near In order to prevent damage and/or improper operation SS CM V –0.5V (see Figure2-3 and Figure2-6). For the of these amplifiers, the circuit must limit the currents DD best distortion performance with non-inverting gains, (and voltages) at the input pins (see Absolute avoid these regions of operation. Maximum Ratings † at the beginning of Section1.0 “Electrical Characteristics”). Figure4-2 shows the recommended approach to protecting these inputs. The internal ESD diodes prevent the input pins (V + IN and V –) from going too far below ground, and the IN resistors R and R limit the possible current drawn out 1 2 of the input pins. Diodes D and D prevent the input 1 2 pins (V + and V –) from going too far above V and IN IN DD  2019 Microchip Technology Inc. DS20001668E-page 15

MCP6141/2/3/4 4.2 Rail-to-Rail Output 4.4 Stability There are two specifications that describe the output 4.4.1 NOISE GAIN swing capability of the MCP6141/2/3/4 family of op amps. The first specification (Maximum Output Voltage The MCP6141/2/3/4 op amp family is designed to give Swing) defines the absolute maximum swing that can high bandwidth and slew rate for circuits with high noise gain (G ) or signal gain. Low gain applications should be achieved under the specified load condition. Thus, N be realized using the MCP6041/2/3/4 op amp family; the output voltage swings to within 10mV of either supply rail with a 50k load to V /2. Figure2-10 this simplifies design and implementation issues. DD shows how the output voltage is limited when the input Noise gain is defined to be the gain from a voltage goes beyond the linear region of operation. source at the non-inverting input to the output when all The second specification that describes the output other voltage sources are zeroed (shorted out). Noise swing capability of these amplifiers is the Linear Output gain is independent of signal gain and depends only on Voltage Range. This specification defines the components in the feedback loop. The amplifier circuits maximum output swing that can be achieved while the in Figure4-3 and Figure4-4 have their noise gain amplifier still operates in its linear region. To verify calculated as follows: linear operation in this range, the large signal DC Open-Loop Gain (A ) is measured at points inside the EQUATION 4-2: OL supply rails. The measurement must meet the specified R AOL condition in the specification table. GN = 1+R-----F--10 V/V G 4.3 Output Loads and Battery Life In order for the amplifiers to be stable, the noise gain The MCP6141/2/3/4 op amp family has outstanding should meet the specified minimum noise gain. Note quiescent current, which supports battery-powered that a noise gain of G =+10V/V corresponds to a N applications. There is minimal quiescent current non-inverting signal gain of G=+10V/V, or to an glitching when Chip Select (CS) is raised or lowered. inverting signal gain of G=-9V/V. This prevents excessive current draw, and reduced battery life, when the part is turned off or on. R Heavy resistive loads at the output can cause IN excessive battery drain. Driving a DC voltage of 2.5V VIN + across a 100k load resistor will cause the supply MCP614X VOUT current to increase by 25µA, depleting the battery 43 – times as fast as IQ (0.6µA, typical) alone. RG RF High frequency signals (fast edge rate) across capacitive loads will also significantly increase supply current. For instance, a 0.1µF capacitor at the output presents an AC impedance of 15.9k (1/2πfC) to a FIGURE 4-3: Noise Gain for Non-inverting 100Hz sinewave. It can be shown that the average Gain Configuration. power drawn from the battery by a 5.0V sinewave P-P (1.77V ), under these conditions, is: rms R R G F V V EQUATION 4-1: IN OUT – P = (V - V ) (I + V fC ) Supply DD SS Q L(p-p) L R MCP614X = (5V)(0.6 µA + 5.0Vp-p · 100Hz · 0.1µF) IN + = 3.0 µW + 50 µW FIGURE 4-4: Noise Gain for Inverting This will drain the battery 18 times as fast as I alone. Q Gain Configuration. DS20001668E-page 16  2019 Microchip Technology Inc.

MCP6141/2/3/4 Figure4-5 shows three example circuits that are When driving large capacitive loads with these op unstable when used with the MCP6141/2/3/4 family. amps (e.g., >60pF when G=+10), a small series The unity gain buffer and low gain amplifier resistor at the output (R in Figure4-6) improves the ISO (non-inverting or inverting) are at gains that are too low feedback loop’s phase margin (stability) by making the for stability (see Equation4-2).The Miller integrator’s output load resistive at higher frequencies. The capacitor makes it reach unity gain at high frequencies, bandwidth will be generally lower than the bandwidth causing instability. with no capacitive load. Note: The three circuits shown in Figure4-5 are not to be used with the MCP6141/2/3/4 op R R R G F ISO amps. They are included for illustrative V V A OUT purposes only. – C L MCP614X Unity Gain Buffer V + B – FIGURE 4-6: Output Resistor, RISO stabilizes large capacitive loads. MCP614X V OUT V + Figure4-7 gives recommended R values for IN ISO different capacitive loads and gains. The x-axis is the LowGainAmplifier normalized load capacitance (CL/GN), where GN is the circuit’s noise gain. For non-inverting gains, G and the R R N G F Signal Gain are equal. For inverting gains, G is N V1 VOUT 1+|Signal Gain| (e.g., -9V/V gives GN=+10V/V). – R MCP614X N 1001,0000k0 V + 2 R Ω) 1+-----F--10 (O R S G RI d e d10,01000k n e Miller Integrator mm GN = +10 R C Reco GGNN = ++5200 V V IN OUT 1,010k0 – 1.E1+p00 1.1E0+p01 11.E0+00p2 1.E1+n03 MCP614X Normalized Load Capacitance; CL/GN (F) + FIGURE 4-7: Recommended R Values ISO for Capacitive Loads. FIGURE 4-5: Examples of Unstable After selecting R for your circuit, double check the ISO Circuits for the MCP6141/2/3/4 Family. resulting frequency response peaking and step response overshoot. Modify R ’s value until the 4.4.2 CAPACITIVE LOADS ISO response is reasonable. Bench evaluation and Driving large capacitive loads can cause stability simulations with the MCP6141/2/3/4 SPICE macro problems for voltage feedback op amps. As the load model are helpful. capacitance increases, the feedback loop’s phase margin decreases and the closed-loop bandwidth is 4.5 MCP6143 Chip Select reduced. This produces gain peaking in the frequency response, with overshoot and ringing in the step The MCP6143 is a single op amp with Chip Select response. A unity gain buffer (G=+1) is the most (CS). When CS is pulled high, the supply current drops sensitive to capacitive loads, though all gains show the to 50nA (typical) and flows through the CS pin to VSS. same general behavior. When this happens, the amplifier output is put into a high impedance state. By pulling CS low, the amplifier is enabled. If the CS pin is left floating, the amplifier will not operate properly. Figure1-1 shows the output voltage and supply current response to a CS pulse.  2019 Microchip Technology Inc. DS20001668E-page 17

MCP6141/2/3/4 4.6 Supply Bypass Guard Ring V – V + With this family of operational amplifiers, the power IN IN supply pin (V for single supply) should have a local DD bypass capacitor (i.e., 0.01µF to 0.1µF) within 2mm for good high frequency performance. It can use a bulk capacitor (i.e., 1µF or larger) within 100mm to provide large, slow currents. This bulk capacitor is not required for most applications and can be shared with other FIGURE 4-9: Example Guard Ring Layout nearby analog parts. for Inverting Gain. 4.7 Unused Op Amps 1. Non-inverting Gain and Unity Gain Buffer: a) Connect the non-inverting pin (V +) to the An unused op amp in a quad package (MCP6144) IN input with a wire that does not touch the should be configured as shown in Figure4-8. These PCB surface. circuits prevent the output from toggling and causing crosstalk. b) Connect the guard ring to the inverting input pin (V –). This biases the guard ring to the Circuit A sets the op amp near its minimum noise gain. IN Common-mode input voltage. The resistor divider produces any desired reference 2. Inverting Gain and Transimpedance Gain voltage within the output voltage range of the op amp; (convert current to voltage, such as photo the op amp buffers that reference voltage. Circuit B detectors) amplifiers: uses the minimum number of components and operates as a comparator, but it may draw more a) Connect the guard ring to the non-inverting current. input pin (VIN+). This biases the guard ring to the same reference voltage as the op amp (e.g., V /2 or ground). ¼ MCP6144 (A) ¼ MCP6144 (B) DD b) Connect the inverting pin (V –) to the input IN VDD VDD with a wire that does not touch the PCB surface. V R DD 1 + + – – V REF R 10R R R 2 2 V = V -------------------- REF DD R +R 1 2 FIGURE 4-8: Unused Op Amps. 4.8 PCB Surface Leakage In applications where low input bias current is critical, printed circuit board (PCB) surface leakage effects need to be considered. Surface leakage is caused by humidity, dust or other contamination on the board. Under low humidity conditions, a typical resistance between nearby traces is 1012. A 5V difference would cause 5pA of current to flow, which is greater than the MCP6141/2/3/4 family’s bias current at +25°C (1pA, typical). The easiest way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). The guard ring is biased at the same voltage as the sensitive pin. An example of this type of layout is shown in Figure4-9. DS20001668E-page 18  2019 Microchip Technology Inc.

MCP6141/2/3/4 4.9 Application Circuits 4.9.2 INVERTING SUMMING AMPLIFIER The MCP6141/2/3/4 op amp is well suited for the 4.9.1 BATTERY CURRENT SENSING inverting summing amplifier shown in Figure4-11 when The MCP6141/2/3/4 op amps’ Common-mode Input the resistors at the input (R , R , and R ) make the 1 2 3 Range, which goes 0.3V beyond both supply rails, noise gain at least 10V/V. The output voltage (V ) is OUT supports their use in high side and low side battery a weighted sum of the inputs (V , V , and V ), and is 1 2 3 current sensing applications. The very low quiescent shifted by the V input. The necessary calculations REF current (0.6µA, typical) help prolong battery life, and follow in Equation4-3. the rail-to-rail output supports detection low currents. . Figure4-10 shows a high side battery current sensor R 1 circuit. The 1k resistor is sized to minimize power V 1 losses. The battery current (I ) through the 1k DD R resistor causes its top terminal to be more negative 2 than the bottom terminal. This keeps the Common- V2 RF mode input voltage of the op amp below VDD, which is R3 VOUT within its allowed range. When no current is flowing, the V – 3 output will be at its Maximum Output Voltage Swing MCP614X (V ), which is virtually at V . OH DD V + REF . IDD FIGURE 4-11: Summing Amplifier. V 1.4V DD 1k EQUATION 4-3: to + 6.0V MCP6141 V Noise Gain: OUT – G = 1+R --1----+--1----+--1----10 V/V N FR R R  1 2 3 Signal Gains: G = –R R 100k 1M 1 F 1 G = –R R 2 F 2 VOUT = VDD–1 k11 V/VIDD G3 = –RFR3 FIGURE 4-10: High Side Battery Current Output Signal: Sensor. V = V G +V G +V G +V G OUT 1 1 2 2 3 3 REF N  2019 Microchip Technology Inc. DS20001668E-page 19

MCP6141/2/3/4 NOTES: DS20001668E-page 20  2019 Microchip Technology Inc.

MCP6141/2/3/4 5.0 DESIGN AIDS 5.5 Analog Demonstration and Evaluation Boards Microchip provides the basic design tools needed for the MCP6141/2/3/4 family of op amps. Microchip offers a broad spectrum of Analog Demonstration and Evaluation Boards that are 5.1 SPICE Macro Model designed to help you achieve faster time to market. For a complete listing of these boards and their The latest SPICE macro model for the MCP6141/2/3/4 corresponding user’s guides and technical information, op amps is available on the Microchip web site at visit the Microchip web site at www.micro- www.microchip.com. This model is intended to be an chip.com/analogtools. initial design tool that works well in the op amp’s linear Two of our boards that are especially useful are: region of operation over the temperature range. See the model file for information on its capabilities. • 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board, P/N SOIC8EV Bench testing is a very important part of any design and cannot be replaced with simulations. Also, simulation • 14-Pin SOIC/TSSOP/DIP Evaluation Board, P/N results using this macro model need to be validated by SOIC14EV comparing them to the data sheet specifications and characteristic curves. 5.6 Application Notes 5.2 FilterLab® Software The following Microchip Analog Design Note and Application Notes are available on the Microchip web Microchip’s FilterLab® software is an innovative site at www.microchip.com/appnotes and are software tool that simplifies analog active filter (using recommended as supplemental reference resources. op amps) design. Available at no cost from the • ADN003: “Select the Right Operational Amplifier Microchip web site at www.microchip.com/filterlab, the for your Filtering Circuits,” DS21821 FilterLab design tool provides full schematic diagrams • AN722: “Operational Amplifier Topologies and DC of the filter circuit with component values. It also Specifications,” DS00722 outputs the filter circuit in SPICE format, which can be • AN723: “Operational Amplifier AC Specifications used with the macro model to simulate actual filter and Applications,” DS00723 performance. • AN884: “Driving Capacitive Loads With Op Amps,” DS00884 5.3 Mindi™ Simulation Tool • AN990: “Analog Sensor Conditioning Circuits– Microchip’s Mindi™ simulation tool aids in the design of An Overview,” DS00990 various circuits useful for active filter, amplifier and These application notes and others are listed in the power-management applications. It is a free online design guide: simulation tool available from the Microchip web site at www.microchip.com/mindi. This interactive simulator • “Signal Chain Design Guide,” DS21825 enables designers to quickly generate circuit diagrams, simulate circuits. Circuits developed using the Mindi simulation tool can be downloaded to a personal computer or workstation. 5.4 Microchip Advanced Part Selector (MAPS) MAPS is a software tool that helps semiconductor professionals efficiently identify Microchip devices that fit a particular design requirement. Available at no cost from the Microchip website at www.microchip.com/ maps, the MAPS is an overall selection tool for Microchip’s product portfolio that includes Analog, Memory, MCUs and DSCs. Using this tool you can define a filter to sort features for a parametric search of devices and export side-by-side technical comparison reports. Helpful links are also provided for Data sheets, Purchase, and Sampling of Microchip parts.  2019 Microchip Technology Inc. DS20001668E-page 21

MCP6141/2/3/4 NOTES: DS20001668E-page 22  2019 Microchip Technology Inc.

MCP6141/2/3/4 6.0 PACKAGING INFORMATION 6.1 Package Marking Information 5-Lead SOT-23 (MCP6141) Example: Device E-Temp Code XXNN MCP6141 ASNN AS25 Note: Applies to 5-Lead SOT-23 6-Lead SOT-23 (MCP6143) Example: Device E-Temp Code XXNN MCP6143 AWNN AW25 Note: Applies to 6-Lead SOT-23 8-Lead MSOP Example: 6143I 931256 8-Lead PDIP (300 mil) Example: XXXXXXXX MCP6141 MCP6141 XXXXXNNN I/P256 OR E/P e 3 256 YYWW 1931 1931 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2019 Microchip Technology Inc. DS20001668E-page 23

MCP6141/2/3/4 Package Marking Information (Continued) 8-Lead SOIC (150 mil) Example: XXXXXXXX MCP6142 MCP6142E XXXXYYWW I/SN1931 OR SN e3 1931 NNN 256 256 14-Lead PDIP (300 mil) (MCP6144) Example: XXXXXXXXXXXXXX MCP6144-I/P XXXXXXXXXXXXXX YYWWNNN 1931256 MCP6144 OR I/P e3 1931256 14-Lead SOIC (150 mil) (MCP6144) Example: XXXXXXXXXX MCP6144ISL XXXXXXXXXX YYWWNNN 1931256 MCP6144 OR I/SL^e^3 1931256 DS20001668E-page 24  2019 Microchip Technology Inc.

MCP6141/2/3/4 Package Marking Information (Continued) 14-Lead TSSOP (MCP6144) Example: XXXXXXXX 6144ST YYWW 1931 NNN 256 6144EST 1931 OR 256  2019 Microchip Technology Inc. DS20001668E-page 25

MCP6141/2/3/4 5-Lead Plastic Small Outline Transistor (OT) [SOT23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 0.20 C 2X D e1 A D N E/2 E1/2 E1 E (DATUM D) (DATUM A-B) 0.15 C D 2X NOTE 1 1 2 e B NX b 0.20 C A-B D TOP VIEW A A2 A 0.20 C SEATING PLANE A SEE SHEET 2 A1 C SIDE VIEW Microchip Technology Drawing C04-091-OT Rev E Sheet 1 of 2 DS20001668E-page 26  2019 Microchip Technology Inc.

MCP6141/2/3/4 5-Lead Plastic Small Outline Transistor (OT) [SOT23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging c (cid:84) L L1 VIEW A-A SHEET 1 Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 5 Pitch e 0.95 BSC Outside lead pitch e1 1.90 BSC Overall Height A 0.90 - 1.45 Molded Package Thickness A2 0.89 - 1.30 Standoff A1 - - 0.15 Overall Width E 2.80 BSC Molded Package Width E1 1.60 BSC Overall Length D 2.90 BSC Foot Length L 0.30 - 0.60 Footprint L1 0.60 REF Foot Angle (cid:73) 0° - 10° Lead Thickness c 0.08 - 0.26 Lead Width b 0.20 - 0.51 Notes: 1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25mm per side. 2. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-091-OT Rev E Sheet 2 of 2  2019 Microchip Technology Inc. DS20001668E-page 27

MCP6141/2/3/4 5-Lead Plastic Small Outline Transistor (OT) [SOT23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging X SILK SCREEN 5 Y Z C G 1 2 E GX RECOMMENDED LAND PATTERN Units MILLIMETERS Dimension Limits MIN NOM MAX Contact Pitch E 0.95 BSC Contact Pad Spacing C 2.80 Contact Pad Width (X5) X 0.60 Contact Pad Length (X5) Y 1.10 Distance Between Pads G 1.70 Distance Between Pads GX 0.35 Overall Width Z 3.90 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-2091B [OT] DS20001668E-page 28  2019 Microchip Technology Inc.

MCP6141/2/3/4 6-Lead Plastic Small Outline Transistor (CH, CHY) [SOT-23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2X 0.15 C A-B D e1 A D E 2 E1 E E1 2 2X 0.15 C D 2X 0.20 C A-B e B 6X b 0.20 C A-B D TOP VIEW A2 A C SEATING PLANE 6X A1 0.10 C SIDE VIEW R1 R L2 c GAUGE PLANE L (cid:300) (L1) END VIEW Microchip Technology Drawing C04-028C (CH) Sheet 1 of 2  2019 Microchip Technology Inc. DS20001668E-page 29

MCP6141/2/3/4 6-Lead Plastic Small Outline Transistor (CH, CHY) [SOT-23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Leads N 6 Pitch e 0.95 BSC Outside lead pitch e1 1.90 BSC Overall Height A 0.90 - 1.45 Molded Package Thickness A2 0.89 1.15 1.30 Standoff A1 0.00 - 0.15 Overall Width E 2.80 BSC Molded Package Width E1 1.60 BSC Overall Length D 2.90 BSC Foot Length L 0.30 0.45 0.60 Footprint L1 0.60 REF Seating Plane to Gauge Plane L1 0.25 BSC Foot Angle φ 0° - 10° Lead Thickness c 0.08 - 0.26 Lead Width b 0.20 - 0.51 Notes: 1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25mm per side. 2. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-028C (CH) Sheet 2 of 2 DS20001668E-page 30  2019 Microchip Technology Inc.

MCP6141/2/3/4 6-Lead Plastic Small Outline Transistor (CH, CHY) [SOT-23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging GX Y Z C G G SILK SCREEN X E RECOMMENDED LAND PATTERN Units MILLIMETERS Dimension Limits MIN NOM MAX Contact Pitch E 0.95 BSC Contact Pad Spacing C 2.80 Contact Pad Width (X3) X 0.60 Contact Pad Length (X3) Y 1.10 Distance Between Pads G 1.70 Distance Between Pads GX 0.35 Overall Width Z 3.90 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-2028B (CH)  2019 Microchip Technology Inc. DS20001668E-page 31

MCP6141/2/3/4 Note: For the mostcurrent package drawings,please seetheMicrochip Packaging Specification located at http://www.microchip.com/packaging DS20001668E-page 32  2019 Microchip Technology Inc.

MCP6141/2/3/4 Note: For the mostcurrent package drawings,please seetheMicrochip Packaging Specification located at http://www.microchip.com/packaging  2019 Microchip Technology Inc. DS20001668E-page 33

MCP6141/2/3/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20001668E-page 34  2019 Microchip Technology Inc.

MCP6141/2/3/4 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A N B E1 NOTE 1 1 2 TOP VIEW E C A A2 PLANE L c A1 e eB 8X b1 8X b .010 C SIDE VIEW END VIEW Microchip Technology Drawing No. C04-018-P Rev E Sheet 1 of 2  2019 Microchip Technology Inc. DS20001668E-page 35

MCP6141/2/3/4 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging ALTERNATE LEAD DESIGN (NOTE 5) DATUM A DATUM A b b e e 2 2 e e Units INCHES Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e .100 BSC Top to Seating Plane A - - .210 Molded Package Thickness A2 .115 .130 .195 Base to Seating Plane A1 .015 - - Shoulder to Shoulder Width E .290 .310 .325 Molded Package Width E1 .240 .250 .280 Overall Length D .348 .365 .400 Tip to Seating Plane L .115 .130 .150 Lead Thickness c .008 .010 .015 Upper Lead Width b1 .040 .060 .070 Lower Lead Width b .014 .018 .022 Overall Row Spacing § eB - - .430 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. 5. Lead design above seating plane may vary, based on assembly vendor. Microchip Technology Drawing No. C04-018-P Rev E Sheet 2 of 2 DS20001668E-page 36  2019 Microchip Technology Inc.

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DS20001668E-page 37

MCP6141/2/3/4 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2X 0.10 C A–B D A D NOTE 5 N E 2 E1 2 E1 E NOTE 1 1 2 e NX b B 0.25 C A–B D NOTE 5 TOP VIEW 0.10 C C A A2 SEATING PLANE 8X 0.10 C A1 SIDE VIEW h R0.13 h R0.13 H 0.23 L SEE VIEW C (L1) VIEW A–A VIEW C Microchip Technology Drawing No. C04-057-SN Rev E Sheet 1 of 2 DS20001668E-page 38  2019 Microchip Technology Inc.

MCP6141/2/3/4 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e 1.27 BSC Overall Height A - - 1.75 Molded Package Thickness A2 1.25 - - Standoff § A1 0.10 - 0.25 Overall Width E 6.00 BSC Molded Package Width E1 3.90 BSC Overall Length D 4.90 BSC Chamfer (Optional) h 0.25 - 0.50 Foot Length L 0.40 - 1.27 Footprint L1 1.04 REF Foot Angle 0° - 8° Lead Thickness c 0.17 - 0.25 Lead Width b 0.31 - 0.51 Mold Draft Angle Top 5° - 15° Mold Draft Angle Bottom 5° - 15° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. 5. Datums A & B to be determined at Datum H. Microchip Technology Drawing No. C04-057-SN Rev E Sheet 2 of 2  2019 Microchip Technology Inc. DS20001668E-page 39

MCP6141/2/3/4 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging SILK SCREEN C Y1 X1 E RECOMMENDED LAND PATTERN Units MILLIMETERS Dimension Limits MIN NOM MAX Contact Pitch E 1.27 BSC Contact Pad Spacing C 5.40 Contact Pad Width (X8) X1 0.60 Contact Pad Length (X8) Y1 1.55 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-2057-SN Rev E DS20001668E-page 40  2019 Microchip Technology Inc.

MCP6141/2/3/4 14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2X 0.10 C A–B D A NOTE 5 D N E 2 E2 2 E1 E 2X 0.10 C D 2X N/2 TIPS NOTE 1 1 2 3 0.20 C e NX b B NOTE 5 0.25 C A–B D TOP VIEW 0.10 C C A A2 SEATING PLANE 14X A1 SIDE VIEW 0.10 C h h H R0.13 R0.13 c SEE VIEW C L VIEW A–A (L1) VIEW C Microchip Technology Drawing No. C04-065-SL Rev D Sheet 1 of 2  2019 Microchip Technology Inc. DS20001668E-page 41

MCP6141/2/3/4 14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 14 Pitch e 1.27 BSC Overall Height A - - 1.75 Molded Package Thickness A2 1.25 - - Standoff § A1 0.10 - 0.25 Overall Width E 6.00 BSC Molded Package Width E1 3.90 BSC Overall Length D 8.65 BSC Chamfer (Optional) h 0.25 - 0.50 Foot Length L 0.40 - 1.27 Footprint L1 1.04 REF Lead Angle 0° - - Foot Angle 0° - 8° Lead Thickness c 0.10 - 0.25 Lead Width b 0.31 - 0.51 Mold Draft Angle Top 5° - 15° Mold Draft Angle Bottom 5° - 15° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimension D does not include mold flash, protrusions or gate burrs, which shall not exceed 0.15 mm per end. Dimension E1 does not include interlead flash or protrusion, which shall not exceed 0.25 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. 5. Datums A & B to be determined at Datum H. Microchip Technology Drawing No. C04-065-SL Rev D Sheet 2 of 2 DS20001668E-page 42  2019 Microchip Technology Inc.

MCP6141/2/3/4 14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 14 SILK SCREEN C Y 1 2 X E RECOMMENDED LAND PATTERN Units MILLIMETERS Dimension Limits MIN NOM MAX Contact Pitch E 1.27 BSC Contact Pad Spacing C 5.40 Contact Pad Width (X14) X 0.60 Contact Pad Length (X14) Y 1.55 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-2065-SL Rev D  2019 Microchip Technology Inc. DS20001668E-page 43

MCP6141/2/3/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20001668E-page 44  2019 Microchip Technology Inc.

MCP6141/2/3/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2019 Microchip Technology Inc. DS20001668E-page 45

MCP6141/2/3/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20001668E-page 46  2019 Microchip Technology Inc.

MCP6141/2/3/4 APPENDIX A: REVISION HISTORY Revision E (November 2019) Revision B (November 2005) The following is the list of modifications: The following is the list of modifications: 1. Updated Section6.0 “Packaging Informa- 1. Added the following: tion”. a) SOT-23-5 package for the MCP6141 single op amps. Revision D (May 2009) b) SOT-23-6 package for the MCP6143 single op amps with Chip Select. The following is the list of modifications: c) Extended Temperature (-40°C to +125°C) 1. DC Electrical Charactistics table: Corrected op amps. formatting issue in Output section. 2. Updated specifications in Section1.0 2. AC Electrical Characteristics table: Slew Rate “Electrical Characteristics” for E-temp parts. - changed typical value from 3.0 to 24. Changed 3. Corrected and updated plots in Section2.0 Phase Margin from 65 to 60. Changed Phase “Typical Performance Curves”. Margin Condition from G=+1 to G=+10 V/V. 4. Added Section3.0 “Pin Descriptions”. 3. Updated Package Outline Drawings 5. Updated Section4.0 “Applications 4. Updated Revision History. Information” and added section on unused op amps. Revision C (December 2007) 6. Updated Section5.0 “Design Aids” to include • Updated Figures 2.4 and 2.5 FilterLab. • Expanded Analog Input Absolute Max Voltage 7. Added SOT-23-5 and SOT-23-6 packages and Range (applies retroactively) corrected package marking information in • Expanded maximum operating V (going Section6.0 “Packaging Information”. DD forward) 8. Added Appendix A: “Revision History”. • Section1.0 “Electrical Characteristics” updated Revision A (September 2002) • Section2.0 “Typical Performance Curves” • Original Release of this Document. updated • Section4.0 “Applications Information” - Updated input stage explanation • Section5.0 “Design Aids” updated  2019 Microchip Technology Inc. DS20001668E-page 47

MCP6141/2/3/4 NOTES:  2019 Microchip Technology Inc. DS20001668E-page 48

MCP6141/2/3/4 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. - X / XX Examples: a) MCP6141-I/P: Industrial Temperature 8 lead PDIP package. Device Temperature Package b) MCP6141T-E/OT: Tape and Reel, Range Extended Temperature 5 lead SOT-23 package. Device: MCP6141: Single Op Amp a) MCP6142-I/SN: Industrial Temperature MCP6141T: Single Op Amp 8 lead SOIC package. (Tape and Reel for SOT-23, SOIC, MSOP) b) MCP6142T-E/MS: Tape and Reel, MCP6142: Dual Op Amp Extended Temperature MCP6142T: Dual Op Amp 8 lead MSOP package. (Tape and Reel for SOIC and MSOP) MCP6143: Single Op Amp w/ CS a) MCP6143-I/P: Industrial Temperature, MCP6143T: Single Op Amp w/ CS 8 lead PDIP package. (Tape and Reel for SOT-23, SOIC, MSOP) b) MCP6143T-E/CH: Tape and Reel, MCP6144: Quad Op Amp Extended Temperature MCP6144T: Quad Op Amp 6 lead SOT-23 package. (Tape and Reel for SOIC and TSSOP) a) MCP6144-I/SL: Industrial Temperature 14 lead PDIP package. Temperature Range: I = -40C to +85C (industrial) b) MCP6144T-E/ST: Tape and Reel, E = -40C to +125C (extended) Extended Temperature 14 lead TSSOP package. Package: CH = Plastic Small Outline Transistor (SOT-23), 6-lead (Tape and Reel - MCP6143 only) MS = Plastic Micro Small Outline (MSOP), 8-lead OT = Plastic Small Outline Transistor (SOT-23), 5-lead (Tape and Reel - MCP6141 only) P = Plastic DIP (300 mil body), 8-lead, 14-lead SL = Plastic SOIC (3.9 mm body), 14-lead SN = Plastic SOIC (3.9 mm body), 8-lead ST = Plastic TSSOP (4.4 mm body), 14-lead  2019 Microchip Technology Inc. DS20001668E-page 49

MCP6141/2/3/4 NOTES: DS20001668E-page 50  2019 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, Adaptec, and may be superseded by updates. It is your responsibility to AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT, ensure that your application meets with your specifications. chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, MICROCHIP MAKES NO REPRESENTATIONS OR LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, WARRANTIES OF ANY KIND WHETHER EXPRESS OR Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, IMPLIED, WRITTEN OR ORAL, STATUTORY OR PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, OTHERWISE, RELATED TO THE INFORMATION, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, INCLUDING BUT NOT LIMITED TO ITS CONDITION, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA QUALITY, PERFORMANCE, MERCHANTABILITY OR are registered trademarks of Microchip Technology Incorporated in FITNESS FOR PURPOSE. Microchip disclaims all liability the U.S.A. and other countries. arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at APT, ClockWorks, The Embedded Control Solutions Company, the buyer’s risk, and the buyer agrees to defend, indemnify and EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision hold harmless Microchip from any and all damages, claims, Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, suits, or expenses resulting from such use. No licenses are SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, conveyed, implicitly or otherwise, under any Microchip TimePictra, TimeProvider, Vite, WinPath, and ZL are registered intellectual property rights unless otherwise stated. trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2019, Microchip Technology Incorporated, All Rights Reserved. For information regarding Microchip’s Quality Management Systems, ISBN: 978-1-5224-5303-1 please visit www.microchip.com/quality.  2019 Microchip Technology Inc. DS20001668E-page 51

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