MCP6141/2/3/4 600 nA, Non-Unity Gain Rail-to-Rail Input/Output Op Amps Features: Description: • Low Quiescent Current: 600nA/amplifier (typ.) The MCP6141/2/3/4 family of non-unity gain stable (cid:129) Gain Bandwidth Product: 100kHz (typ.) operational amplifiers (op amps) from Microchip Tech- nology Inc. operate with a single supply voltage as low (cid:129) Stable for gains of 10V/V or higher as 1.4V, while drawing less than 1μA (max.) of quies- (cid:129) Rail-to-Rail Input/Output cent current per amplifier. These devices are also (cid:129) Wide Supply Voltage Range: 1.4V to 5.5V designed to support rail-to-rail input and output opera- (cid:129) Available in Single, Dual, and Quad tion. This combination of features supports (cid:129) Chip Select (CS ) with MCP6143 battery-powered and portable applications. (cid:129) Available in 5-lead and 6-lead SOT-23 Packages The MCP6141/2/3/4 amplifiers have a gain bandwidth (cid:129) Temperature Ranges: product of 100kHz (typ.) and are stable for gains of - Industrial: -40°C to +85°C 10V/V or higher. These specifications make these op amps appropriate for battery powered applications - Extended: -40°C to +125°C where a higher frequency response from the amplifier is required. Applications: The MCP6141/2/3/4 family operational amplifiers are (cid:129) Toll Booth Tags offered in single (MCP6141), single with Chip Select (cid:129) Wearable Products (CS) (MCP6143), dual (MCP6142) and quad (MCP6144) configurations. The MCP6141 device is (cid:129) Temperature Measurement available in the 5-lead SOT-23 package, and the (cid:129) Battery Powered MCP6143 device is available in the 6-lead SOT-23 package. Available Tools: (cid:129) SPICE Macro Models (at www.microchip.com) Package Types (cid:129) FilterLab™ Software (at www.microchip.com) MCP6141 MCP6143 PDIP, SOIC, MSOP PDIP, SOIC, MSOP Related Devices: NC 1 8 NC NC 1 8 CS (cid:129) MCP6041/2/3/4: Unity Gain Stable Op Amps VIN– 2 7 VDD VIN– 2 7 VDD VIN+ 3 6 VOUT VIN+ 3 6 VOUT Typical Application VSS 4 5 NC VSS 4 5 NC R 1 MCP6141 MCP6143 V1 SOT-23-5 SOT-23-6 R 2 V 1 5 V V 1 6 V OUT DD OUT DD V 2 V 2 V 2 5 CS R R SS SS 3 F V + 3 4 V – V + 3 4 V – V V IN IN IN IN 3 OUT MCP6142 MCP6144 MCP614X PDIP, SOIC, MSOP PDIP, SOIC, TSSOP VREF VOUTA 1 8 VDD VOUTA 1 14 VOUTD VINA– 2 7 VOUTB VINA– 2 13 VIND– Inverting, Summing Amplifier VINA+ 3 6 VINB– VINA+ 3 12 VIND+ VSS 4 5 VINB+ VDD 4 11 VSS V + 5 10 V + INB INC V – 6 9 V – INB INC V 7 8 V OUTB OUTC © 2005 Microchip Technology Inc. DS21668B-page 1

MCP6141/2/3/4 1.0 ELECTRICAL † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the CHARACTERISTICS device. This is a stress rating only and functional operation of the device at those or any other conditions above those Absolute Maximum Ratings † indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended VDD–VSS........................................................................7.0V periods may affect device reliability. All Inputs and Outputs....................V –0.3V to V +0.3V SS DD Difference Input voltage ......................................|V –V | DD SS Output Short Circuit Current ..................................continuous Current at Input Pins ....................................................±2mA Current at Output and Supply Pins ............................±30mA Storage Temperature....................................–65°C to +150°C Junction Temperature..................................................+150°C ESD protection on all pins (HBM; MM)................≥ 4kV; 200V DC ELECTRICAL CHARACTERISTICS Electrical Characteristics: Unless otherwise indicated, V =+1.4V to +5.5V, V =GND, T =25°C, V =V /2, DD SS A CM DD V ≈V /2, and R = 1MΩ to V /2. OUT DD L DD Parameters Sym. Min. Typ. Max. Units Conditions Input Offset Input Offset Voltage V -3 — +3 mV V = V OS CM SS Drift with Temperature ΔV /ΔT — ±1.5 — μV/°C V = V , OS A CM SS T = -40°C to +125°C A Power Supply Rejection PSRR 70 85 — dB V = V CM SS Input Bias Current and Impedance Input Bias Current I — 1 — pA B Industrial Temperature I — 20 100 pA T = +85° B A Extended Temperature I — 1200 5000 pA T = +125° B A Input Offset Current I — 1 — pA OS Common Mode Input Impedance Z — 1013||6 — Ω||pF CM Differential Input Impedance Z — 1013||6 — Ω||pF DIFF Common Mode Common Mode Input Range V V −0.3 — V +0.3 V CMR SS DD Common Mode Rejection Ratio CMRR 62 80 — dB V = 5V, V = -0.3V to 5.3V DD CM CMRR 60 75 — dB V = 5V, V = 2.5V to 5.3V DD CM CMRR 60 80 — dB V = 5V, V = -0.3V to 2.5V DD CM Open Loop Gain DC Open Loop Gain (large signal) A 95 115 — dB R = 50kΩ to V /2, OL L DD V = 0.1V to V −0.1V OUT DD Output Maximum Output Voltage Swing V , V V +10 — V −10 mV R = 50kΩ to V /2, OL OH SS DD L DD 0.5V output overdrive Linear Region Output Voltage Swing V V +100 — V −100 mV R = 50kΩ to V /2, OVR SS DD L DD A ≥ 95 dB OL Output Short Circuit Current I — 2 — mA V = 1.4V SC DD I — 20 — mA V = 5.5V SC DD Power Supply Supply Voltage V 1.4 — 5.5 V DD Quiescent Current per amplifier I 0.3 0.6 1.0 μA I = 0 Q O DS21668B-page 2 © 2005 Microchip Technology Inc.

MCP6141/2/3/4 AC ELECTRICAL CHARACTERISTICS Electrical Characteristics: Unless otherwise indicated, V =+1.4V to +5.5V, V =GND, T =25°C, V =V /2, DD SS A CM DD V ≈V /2, R = 1MΩ to V /2, and C =60pF. OUT DD L DD L Parameters Sym. Min. Typ. Max. Units Conditions AC Response Gain Bandwidth Product GBWP — 100 — kHz Slew Rate SR — 24 — V/ms Phase Margin PM — 60 — ° G = +10 Noise Input Voltage Noise E — 5.0 — μV f = 0.1Hz to 10Hz ni P-P Input Voltage Noise Density e — 170 — nV/√Hz f = 1kHz ni Input Current Noise Density i — 0.6 — fA/√Hz f = 1kHz ni MCP6143 CHIP SELECT (CS) ELECTRICAL CHARACTERISTICS Electrical Characteristics: Unless otherwise indicated, V =+1.4V to +5.5V, V =GND, T =25°C, V =V /2, DD SS A CM DD V ≈V /2, R = 1MΩ to V /2, and C =60pF. OUT DD L DD L Parameters Sym. Min. Typ. Max. Units Conditions CS Low Specifications CS Logic Threshold, Low V V — V +0.3 V IL SS SS CS Input Current, Low I — 5 — pA CS = V CSL SS CS High Specifications CS Logic Threshold, High V V –0.3 — V V IH DD DD CS Input Current, High I — 5 — pA CS = V CSH DD CS Input High, GND Current I — -20 — pA CS = V SS DD Amplifier Output Leakage, CS High I — 20 — pA CS = V OLEAK DD Dynamic Specifications CS Low to Amplifier Output Turn-on Time t — 2 50 ms G = +1V/V, CS = 0.3V to ON V = 0.9V /2 OUT DD CS High to Amplifier Output High-Z t — 10 — μs G = +1V/V, CS = V –0.3V to OFF DD V = 0.1V /2 OUT DD Hysteresis V — 0.6 — V V = 5.0V HYST DD CS VIL VIH t t OFF ON VOUT High-Z High-Z ISS -20 pA (typ.) -0.6 μA (typ.) -20 pA (typ.) I 5 pA (typ.) 5 pA (typ.) CS FIGURE 1-1: Chip Select (CS) Timing Diagram (MCP6143 only). © 2005 Microchip Technology Inc. DS21668B-page 3

MCP6141/2/3/4 TEMPERATURE CHARACTERISTICS Electrical Characteristics: Unless otherwise indicated, V =+1.4V to +5.5V, V =GND. DD SS Parameters Sym. Min. Typ. Max. Units Conditions Temperature Ranges Specified Temperature Range T -40 — +85 °C Industrial Temperature parts A T -40 — +125 °C Extended Temperature parts A Operating Temperature Range T -40 — +125 °C (Note1) A Storage Temperature Range T -65 — +150 °C A Thermal Package Resistances Thermal Resistance, 5L-SOT-23 θ — 256 — °C/W JA Thermal Resistance, 6L-SOT-23 θ — 230 — °C/W JA Thermal Resistance, 8L-PDIP θ — 85 — °C/W JA Thermal Resistance, 8L-SOIC θ — 163 — °C/W JA Thermal Resistance, 8L-MSOP θ — 206 — °C/W JA Thermal Resistance, 14L-PDIP θ — 70 — °C/W JA Thermal Resistance, 14L-SOIC θ — 120 — °C/W JA Thermal Resistance, 14L-TSSOP θ — 100 — °C/W JA Note 1: The MCP6141/2/3/4 family of Industrial Temperature op amps operates over this extended range, but with reduced performance. In any case, the internal Junction Temperature (T ) should not exceed the Absolute J Maximum specification of +150°C. DS21668B-page 4 © 2005 Microchip Technology Inc.

MCP6141/2/3/4 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, T =25°C, V =+1.4V to +5.5V, V =GND, V =V /2, R =1MΩ to V /2, A DD SS CM DD L DD V ≈V /2, and C =60pF. OUT DD L 14% 16% nces12% 1V2D0D 0= S1a.4mVples nces14% 1V2D0D 0= S5a.5mVples urre10% urre12% Occ 8% Occ10% ge of 6% ge of 68%% nta 4% nta 4% Perce 2% Perce 2% 0% 0% -3 -2 -1 0 1 2 3 -3 -2 -1 0 1 2 3 Input Offset Voltage (mV) Input Offset Voltage (mV) FIGURE 2-1: Input Offset Voltage at FIGURE 2-4: Input Offset Voltage at V =1.4V. V =5.5V. DD DD 18% 30% Occurrences 11110246%%%% 2VT3AD 5D= =S - 4a10m.4°pCVl etos +125°C Occurrences 2205%% 2VT3AD 5D= = S- 4a50m.5°pCVl etos +125°C of 8% of 15% e e ag 6% ag 10% ent 4% ent c c 5% er 2% er P P 0% 0% -10 -8 -6 -4 -2 0 2 4 6 8 10 -10 -8 -6 -4 -2 0 2 4 6 8 10 Input Offset Voltage Drift (µV/°C) Input Offset Voltage Drift (µV/°C) FIGURE 2-2: Input Offset Voltage Drift at FIGURE 2-5: Input Offset Voltage Drift at V =1.4V. V =5.5V. DD DD 1000 1000 V = 1.4V V = 5.5V V) 800 DD V) 800 DD oltage (µ 246000000 TTA A= = + +12855°°CC oltage (µ 246000000 TTA A= = + +12855°°CC Offset V --4200000 Offset V --4200000 TA = +25°C put -600 TA = +25°C put -600 TA = -40°C In -800 TA = -40°C In -800 -1000 -1000 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Common Mode Input Voltage (V) Common Mode Input Voltage (V) FIGURE 2-3: Input Offset Voltage vs. FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage at V =1.4V. Common Mode Input Voltage at V =5.5V. DD DD © 2005 Microchip Technology Inc. DS21668B-page 5

MCP6141/2/3/4 Note: Unless otherwise indicated, T =25°C, V =+1.4V to +5.5V, V =GND, V =V /2, R =1MΩ to V /2, A DD SS CM DD L DD V ≈V /2, and C =60pF. OUT DD L 500 6 e (µV) 450 RL = 50 kΩ s (V) 5 VGD =D =+ 151.0 VV/V g e 4 Volta 400 VDD = 1.4V oltag 3 Offset 350 VDD = 5.5V utput V 2 VIN nput 300 ut, O 1 I 250 Inp 0 VOUT 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -1 Output Voltage (V) 0 5 Ti1m0e (5 ms/1d5iv) 20 25 FIGURE 2-7: Input Offset Voltage vs. FIGURE 2-10: The MCP6141/2/3/4 family Output Voltage. shows no phase reversal. Density 1,000 Density 235000 fV =DD 1 = k 5H.z0V oise Voltage (nV/Hz) oise Voltage (nV/Hz) 112050000 N N ut ut 50 p p n n I 100 I 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0.1 1 10 100 1000 0. 0. 0. 1. 1. 2. 2. 3. 3. 4. 4. 5. 5. - Frequency (Hz) Common Mode Input Voltage (V) FIGURE 2-8: Input Noise Voltage Density FIGURE 2-11: Input Noise Voltage Density vs. Frequency. vs. Common Mode Input Voltage. 90 100 PSRR– 80 PSRR+ 95 R (dB) 70 R (dB) 90 PSRR (VCM = VSS) R 60 R S CMRR M 85 MRR, P 4500 SRR, C 80 CMRR (VDD = 5.0V, C 30 P 75 VCM = -0.3V to +5.3V) Referred to Input 20 70 11 1100 110000 11,0k00 1100,0k00 -50 -25 0 25 50 75 100 125 Frequency (Hz) Ambient Temperature (°C) FIGURE 2-9: CMRR, PSRR vs. FIGURE 2-12: CMRR, PSRR vs. Ambient Frequency. Temperature. DS21668B-page 6 © 2005 Microchip Technology Inc.

MCP6141/2/3/4 Note: Unless otherwise indicated, T =25°C, V =+1.4V to +5.5V, V =GND, V =V /2, R =1MΩ to V /2, A DD SS CM DD L DD V ≈V /2, and C =60pF. OUT DD L s 11000k00 1001000k as and Offset Current(pA) 11011100k0100000 VVDCDM == 5V.D5DV IB Bias, Offset Currents(pA)110110010100000k TTAA == ++8152°5C°C VDD = 5.5V | I|OS IB Input Bi 0.011.11 | IOS | Input 00..1111 45 55 65 75 85 95 105 115 125 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Ambient Temperature (°C) Common Mode Input Voltage (V) FIGURE 2-13: Input Bias, Offset Currents FIGURE 2-16: Input Bias, Offset Currents vs. Ambient Temperature. vs. Common Mode Input Voltage. 120 0 130 100 -30 B) 120 Gain (dB) 6800 Phase --9600 Phase (°) p Gain (d 110100 VDD = 5.5V pen-Loop 24000 Gain ---111852000 pen-Loop Open-Loo 8900 VDD = 1.4V O -20 -210 O DC 70 V = 0.1V to V - 0.1V OUT DD -40 -240 60 110.Em- 110.E0m- 1.1E+ 11.E0+ 11.0E0+ 1.1Ek+ 11.0Ek+ 11.0E0+k 11.0E0+02 1.E1+k03 1.1E0+k04 11.E0+00k5 02 01 00Freq01uenc0y2 (Hz)03 04 05 Load Resistance (Ω) FIGURE 2-14: Open-Loop Gain, Phase vs. FIGURE 2-17: DC Open-Loop Gain vs. Frequency. Load Resistance. 140 140 ain (dB)112300 Gain (dB) 112300 RL = 50 kΩ VDD = 5.5V p G op 110 en-Loo110100 pen-Lo 19000 VDD = 1.4V p O C O 90 RL = 50 kΩ DC 80 D VOUT = 0.1V to VDD - 0.1V 70 80 0.00 0.05 0.10 0.15 0.20 0.25 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Output Voltage Headroom; Power Supply Voltage (V) VDD – VOH or VOL – VSS (V) FIGURE 2-15: DC Open-Loop Gain vs. FIGURE 2-18: DC Open-Loop Gain vs. Power Supply Voltage. Output Voltage Headroom. © 2005 Microchip Technology Inc. DS21668B-page 7

MCP6141/2/3/4 Note: Unless otherwise indicated, T =25°C, V =+1.4V to +5.5V, V =GND, V =V /2, R =1MΩ to V /2, A DD SS CM DD L DD V ≈V /2, and C =60pF. OUT DD L 140 120 120 ct 110 110 130 u 100 100 Channel-to-ChannelSeparation (dB) 11190120000 Gain Bandwidth Prod(kHz) 123456789000000000 V(GDGD BP== MW +51P.00V) 123456789000000000 Phase Margin (°) Input Referred 0 0 80 5 0 5 0 5 0 5 0 5 0 5 0 5 1.E1+k03 1.1E0+k04 -0. 0. 0. 1. 1. 2. 2. 3. 3. 4. 4. 5. 5. Frequency (Hz) Common Mode Input Voltage FIGURE 2-19: Channel-to-Channel FIGURE 2-22: Gain Bandwidth Product, Separation vs. Frequency (MCP6142 and Phase Margin vs. Common Mode Input Voltage. MCP6144 only). 90 90 90 90 Product 678000 (G P= M+10) 678000 n (°) Product 678000 GBWP PM 678000 n (°) Bandwidth (kHz) 345000 GBWP 345000 hase Margi Bandwidth (kHz) 345000 (G = +10) 345000 hase Margi n 20 20 P n 20 20 P Gai 10 VDD = 1.4V 10 Gai 10 VDD = 5.5V 10 0 0 0 0 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 Ambient Temperature (°C) Ambient Temperature (°C) FIGURE 2-20: Gain Bandwidth Product, FIGURE 2-23: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature at Phase Margin vs. Ambient Temperature at V =1.4V. V =5.5V. DD DD 0.8 35 nt 30 TA = -40°C nt 00..67 Curre 122505 TA = +25°C Quiescent Curre(µA/Amplifier) 00000.....12345 TTTAT AA=A == =+ ++1-82425550°°°°CCCC Output Short Circuit (mA)-----322111-050505050 TTAA == +-2450°°CC TTAA == ++8152°5C°C 0.0 -35 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Power Supply Voltage (V) Ambient Temperature (°C) FIGURE 2-21: Quiescent Current vs. FIGURE 2-24: Output Short Circuit Current Power Supply Voltage. vs. Power Supply Voltage. DS21668B-page 8 © 2005 Microchip Technology Inc.

MCP6141/2/3/4 Note: Unless otherwise indicated, T =25°C, V =+1.4V to +5.5V, V =GND, V =V /2, R =1MΩ to V /2, A DD SS CM DD L DD V ≈V /2, and C =60pF. OUT DD L 1000 5.0 ge Headroom,V – V (mV)OLSS 100 ge Headroom,V – V (mV)OLSS 23344.....50505 VRDL D= = 5 50. 5kVΩ VOL –V VDSDS – VOH Output VoltaV – V or DDOH 10 VDD – VOH VOL – VSS Output VoltaV – V or DDOH 0112....5050 1 0.0 0.01 0.1 1 10 -50 -25 0 25 50 75 100 125 Output Current Magnitude (mA) Ambient Temperature (°C) FIGURE 2-25: Output Voltage Headroom FIGURE 2-28: Output Voltage Headroom vs. Output Current Magnitude. vs. Ambient Temperature. 40 10 35 e g ate (V/ms) 223050 VDD = 5.5V High-to-Low utput Voltag (V)P-P 1 VVDDDD == 51..54VV R On w 15 m wi Sle 10 Low-to-High muS 5 VDD = 1.4V axi M 0 0.1 -50 -25 0 25 50 75 100 125 100 1k 10k 1.E+02 1.E+03 1.E+04 Ambient Temperature (°C) Frequency (Hz) FIGURE 2-26: Slew Rate vs. Ambient FIGURE 2-29: Maximum Output Voltage Temperature. Swing vs. Frequency. 80 80 G = +11 V/V G = -10 V/V div)60 RL = 50 kΩ 60 RL = 50 kΩ V/40 v)40 m di -oltage (20 22000 -ge (20 mV/22000 V a -put 40 -Volt40 ut -O60 -60 -80 -80 0.0 0.1 0.2 0.3Tim0.4e (100.05 µs0/d.6iv)0.7 0.8 0.9 1.0 0.0 0.1 0.2 0.3Ti0m.4e (100.05 µs0/d.6iv)0.7 0.8 0.9 1.0 FIGURE 2-27: Small Signal Non-inverting FIGURE 2-30: Small Signal Inverting Pulse Pulse Response. Response. © 2005 Microchip Technology Inc. DS21668B-page 9

MCP6141/2/3/4 Note: Unless otherwise indicated, T =25°C, V =+1.4V to +5.5V, V =GND, V =V /2, R =1MΩ to V /2, A DD SS CM DD L DD V ≈V /2, and C =60pF. OUT DD L 5.0 5.0 4.5 VDD = 5.0V 4.5 VDD = 5.0V G = +11 V/V G = -10 V/V e (V) 34..50 RL = 50 kΩ e (V) 34..50 RL = 50 kΩ ag 3.0 ag 3.0 olt 2.5 olt 2.5 V V ut 2.0 ut 2.0 p p ut 1.5 ut 1.5 O O 1.0 1.0 0.5 0.5 0.0 0.0 0 0 0 1Tim1e (2010 µs/1div)1 2 2 2 0 0 0 1Tim1e (2010 µs/1div)1 2 2 2 FIGURE 2-31: Large Signal Non-inverting FIGURE 2-33: Large Signal Inverting Pulse Pulse Response. Response. 27.5 5.0 5.5 CS Voltage (V)1122257025.....05050 VGVDI N=D = =+ + 1531..0 0VVV/VVOUT 23344.....50505 Voltage (V) witch Output (V) 233445......505050 VOUHT Oignh-CtoS-Low HyLsotwer-eCtosS-isHigh 11702...505 On High-Z On 112...050 Output nal CS S 112...050 VGD =D =+ 151. 0VV/V VOUT High-Z 5.0 CS 0.5 nter 0.5 VIN = 3.0V 2.5 0.0 I 0.0 0.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 1 2 3Tim4e (15 ms6/div)7 8 9 10 CS Voltage (V) FIGURE 2-32: Chip Select (CS) to FIGURE 2-34: Internal Chip Select (CS) Amplifier Output Response Time (MCP6143 Hysteresis (MCP6143 only). only). DS21668B-page 10 © 2005 Microchip Technology Inc.

MCP6141/2/3/4 3.0 PIN DESCRIPTIONS Descriptions of the pins are listed in Table3-1. TABLE 3-1: PIN FUNCTION TABLE MCP6141 MCP6143 (PDIP, MCP6141 (PDIP, MCP6143 MCP6142 MCP6144 Symbol Description SOIC, (SOT-23-5) SOIC, (SOT-23-6) MSOP) MSOP) 6 1 1 6 1 1 V ,V Analog Output (op amp A) OUT OUTA 2 4 2 2 4 2 V –,V – Inverting Input (op amp A) IN INA 3 3 3 3 3 3 V +,V + Non-inverting Input (op amp A) IN INA 7 5 8 7 6 4 V Positive Power Supply DD — — 5 — — 5 V + Non-inverting Input (op amp B) INB — — 6 — — 6 V – Inverting Input (op amp B) INB — — 7 — — 7 V Analog Output (op amp B) OUTB — — — — — 8 V Analog Output (op amp C) OUTC — — — — — 9 V – Inverting Input (op amp C) INC — — — — — 10 V + Non-inverting Input (op amp C) INC 4 2 4 4 2 11 V Negative Power Supply SS — — — — — 12 V + Non-inverting Input (op amp D) IND — — — — — 13 V – Inverting Input (op amp D) IND — — — — — 14 V Analog Output (op amp D) OUTD — — — 8 5 — CS Chip Select 1, 5, 8 — — 1, 5 — — NC No Internal Connection 3.1 Analog Outputs 3.4 Power Supply (V and V ) SS DD The output pins are low-impedance voltage sources. The positive power supply pin (V ) is 1.4V to 5.5V DD higher than the negative power supply pin (V ). For SS 3.2 Analog Inputs normal operation, the other pins are at voltages between V and V . SS DD The non-inverting and inverting inputs are high-imped- Typically, these parts are used in a single (positive) ance CMOS inputs with low bias currents. supply configuration. In this case, V is connected to SS ground and V is connected to the supply. V will 3.3 CS Digital Input DD DD need a local bypass capacitor (typically 0.01μF to This is a CMOS, Schmitt-triggered input that places the 0.1μF) within 2mm of the VDD pin. These can share a part into a low-power mode of operation. bulk capacitor with nearby analog parts (within 100mm), but it is not required. © 2005 Microchip Technology Inc. DS21668B-page 11

MCP6141/2/3/4 4.0 APPLICATIONS INFORMATION The second specification that describes the output swing capability of these amplifiers is the Linear Output The MCP6141/2/3/4 family of op amps is manufactured Voltage Range. This specification defines the maxi- using Microchip’s state-of-the-art CMOS process mum output swing that can be achieved while the These op amps are stable for gains of 10V/V and amplifier still operates in its linear region. To verify higher. They are suitable for a wide range of general linear operation in this range, the large signal DC purpose, low-power applications. Open-Loop Gain (A ) is measured at points inside the OL See Microchip’s related MCP6041/2/3/4 family of op supply rails. The measurement must meet the specified amps for applications needing unity gain stability. AOL condition in the specification table. 4.1 Rail-to-Rail Inputs 4.3 Output Loads and Battery Life The MCP6141/2/3/4 op amps are designed to prevent The MCP6141/2/3/4 op amp family has outstanding phase reversal when the input pins exceed the supply quiescent current, which supports battery-powered voltages. Figure2-10 shows the input voltage exceed- applications. There is minimal quiescent current glitch- ing the supply voltage without any phase reversal. ing when Chip Select (CS) is raised or lowered. This prevents excessive current draw, and reduced battery The input stage of the MCP6141/2/3/4 op amps uses life, when the part is turned off or on. two differential CMOS input stages in parallel. One operates at low Common mode input voltage (V ), Heavy resistive loads at the output can cause exces- CM while the other operates at high V . With this topol- sive battery drain. Driving a DC voltage of 2.5V across CM ogy, the device operates with V tp to 0.3V above V a 100kΩ load resistor will cause the supply current to CM DD and 0.3V below V . The input offset voltage (V ) is increase by 25μA, depleting the battery 43 times as SS OS measured at VCM=VSS–0.3V and VDD+0.3V to fast as IQ (0.6μA, typ.) alone. ensure proper operation. High frequency signals (fast edge rate) across capaci- Input voltages that exceed the Absolute Maximum Volt- tive loads will also significantly increase supply current. age Range (V –0.3V to V +0.3V) can cause For instance, a 0.1μF capacitor at the output presents SS DD excessive current to flow into or out of the input pins. an AC impedance of 15.9kΩ (1/2πfC) to a 100Hz sin- Current beyond ±2mA can cause reliability problems. ewave. It can be shown that the average power drawn Applications that exceed this rating must be externally from the battery by a 5.0Vp-p sinewave (1.77Vrms), limited with a resistor, as shown in Figure4-1. under these conditions, is R R EQUATION 4-1: IN F V A P = (V - V ) (I + V fC ) Supply DD SS Q L(p-p) L = (5V)(0.6 µA + 5.0Vp-p · 100Hz · 0.1µF) RIN MCP614X VOUT = 3.0 µW + 50 µW V B This will drain the battery 18 times as fast as I alone. Q (Maximum expected V )–V R ≥-------------------------------------------------------I--N---------------D----D-- IN 2 mA 4.4 Stability V –(Minimum expected V ) R ≥----S---S--------------------------------------------------------------I--N---- 4.4.1 NOISE GAIN IN 2 mA The MCP6141/2/3/4 op amp family is designed to give FIGURE 4-1: Input Current-Limiting high bandwidth and slew rate for circuits with high noise Resistor (RIN). gain (GN) or signal gain. Low gain applications should be realized using the MCP6041/2/3/4 op amp family; this simplifies design and implementation issues. 4.2 Rail-to-Rail Output Noise gain is defined to be the gain from a voltage There are two specifications that describe the output source at the non-inverting input to the output when all swing capability of the MCP6141/2/3/4 family of op other voltage sources are zeroed (shorted out). Noise amps. The first specification (Maximum Output Voltage gain is independent of signal gain and depends only on Swing) defines the absolute maximum swing that can components in the feedback loop. The amplifier circuits be achieved under the specified load condition. Thus, in Figure4-2 and Figure4-3 have their noise gain the output voltage swings to within 10mV of either sup- calculated as follows: ply rail with a 50kΩ load to V /2. Figure2-10 shows DD how the output voltage is limited when the input goes beyond the linear region of operation. DS21668B-page 12 © 2005 Microchip Technology Inc.

MCP6141/2/3/4 EQUATION 4-2: 4.4.2 CAPACITIVE LOADS R Driving large capacitive loads can cause stability G = 1+-----F--≥10 V/V problems for voltage feedback op amps. As the load N R G capacitance increases, the feedback loop’s phase margin decreases and the closed-loop bandwidth is In order for the amplifiers to be stable, the noise gain reduced. This produces gain peaking in the frequency should meet the specified minimum noise gain. Note response, with overshoot and ringing in the step that a noise gain of GN=+10V/V corresponds to a response. A unity gain buffer (G=+1) is the most non-inverting signal gain of G=+10V/V, or to an sensitive to capacitive loads, though all gains show the inverting signal gain of G=-9V/V. same general behavior. When driving large capacitive loads with these op RIN amps (e.g., >60pF when G=+10), a small series V resistor at the output (R in Figure4-5) improves the IN ISO MCP614X VOUT feedback loop’s phase margin (stability) by making the output load resistive at higher frequencies. The band- width will be generally lower than the bandwidth with no R R G F capacitive load. R R G F FIGURE 4-2: Noise Gain for Non-inverting V A Gain Configuration. R ISO MCP614X V OUT RG RF VB CL V V IN OUT RIN MCP614X FIGURE 4-5: Output Resistor, RISO stabilizes large capacitive loads. Figure4-6 gives recommended R values for differ- ISO ent capacitive loads and gains. The x-axis is the nor- FIGURE 4-3: Noise Gain for Inverting malized load capacitance (C /G ), where G is the Gain Configuration. L N N circuit’s noise gain. For non-inverting gains, G and the N Figure4-4 shows a unity gain buffer and Miller integra- Signal Gain are equal. For inverting gains, G is N tor that are unstable when used with the 1+|Signal Gain| (e.g., -9V/V gives G =+10V/V). N MCP6141/2/3/4 family. Note that the capacitor makes the integrator circuit reach unity gain at high 1001,00000k frequencies, which makes these op amps unstable. ):: (O Unity Gain Buffer RIS d e d10,01000k n e m MCP614X V m GN = +10 OUT o G = +20 c N VIN Re GN tt+50 1,0010k Miller Integrator 1.E1+p00 1.1E0+p01 11.E0+00p2 1.E1+n03 Normalized Load Capacitance; C /G (F) L N R C VIN VOUT FIGURE 4-6: Recommended RISO Values for Capacitive Loads. MCP614X After selecting R for your circuit, double check the ISO resulting frequency response peaking and step response overshoot. Modify R ’s value until the ISO response is reasonable. Bench evaluation and simula- FIGURE 4-4: Typical Unstable Circuits for tions with the MCP6141/2/3/4 SPICE macro model are the MCP6141/2/3/4 Family. helpful. © 2005 Microchip Technology Inc. DS21668B-page 13

MCP6141/2/3/4 4.5 MCP6143 Chip Select (CS) 4.8 PCB Surface Leakage The MCP6143 is a single op amp with Chip Select In applications where low input bias current is critical, (CS). When CS is pulled high, the supply current drops printed circuit board (PCB) surface leakage effects to 50nA (typ.) and flows through the CS pin to V . need to be considered. Surface leakage is caused by SS When this happens, the amplifier output is put into a humidity, dust or other contamination on the board. high impedance state. By pulling CS low, the amplifier Under low humidity conditions, a typical resistance is enabled. If the CS pin is left floating, the amplifier between nearby traces is 1012Ω. A 5V difference would may not operate properly. Figure1-1 shows the output cause 5pA of current to flow, which is greater than the voltage and supply current response to a CS pulse. MCP6141/2/3/4 family’s bias current at 25°C (1pA, typ.). 4.6 Supply Bypass The easiest way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). The guard With this family of operational amplifiers, the power ring is biased at the same voltage as the sensitive pin. supply pin (V for single supply) should have a local DD An example of this type of layout is shown in bypass capacitor (i.e., 0.01μF to 0.1μF) within 2mm Figure4-8. for good high frequency performance. It can use a bulk capacitor (i.e., 1μF or larger) within 100mm to provide large, slow currents. This bulk capacitor is not required Guard Ring V – V + IN IN for most applications and can be shared with other nearby analog parts. 4.7 Unused Op Amps An unused op amp in a quad package (MCP6144) should be configured as shown in Figure4-7. These FIGURE 4-8: Example Guard Ring Layout circuits prevent the output from toggling and causing for Inverting Gain. crosstalk. Circuits A and B are set near the minimum noise gain. Circuit A can use any reference voltage 1. Non-inverting Gain and Unity Gain Buffer: between the supplies, provides a buffered DC voltage, a) Connect the non-inverting pin (V +) to the IN and minimizes the supply current draw of the unused input with a wire that does not touch the op amp. Circuit B may draw a little more supply current PCB surface. for the unused op amp. Circuit C uses the minimum b) Connect the guard ring to the inverting input number of components and operates as a comparator; pin (V –). This biases the guard ring to the IN it may draw more current than either Circuit A or B. Common mode input voltage. 2. Inverting Gain and Trans-impedance Gain (con- ¼ MCP6144 (A) ¼ MCP6144 (B) vert current to voltage, such as photo detectors) V V amplifiers: DD DD a) Connect the guard ring to the non-inverting R VDD input pin (VIN+). This biases the guard ring to the same reference voltage as the op amp (e.g., V /2 or ground). DD b) Connect the inverting pin (V –) to the input IN R 10R with a wire that does not touch the PCB surface. R 15R ¼ MCP6144 (C) R V DD FIGURE 4-7: Unused Op Amps. DS21668B-page 14 © 2005 Microchip Technology Inc.

MCP6141/2/3/4 4.9 Application Circuits 4.9.2 INVERTING SUMMING AMPLIFIER The MCP6141/2/3/4 op amp is well suited for the 4.9.1 BATTERY CURRENT SENSING inverting summing amplifier shown in Figure4-10 The MCP6141/2/3/4 op amps’ Common Mode Input when the resistors at the input (R , R , and R ) make 1 2 3 Range, which goes 0.3V beyond both supply rails, sup- the noise gain at least 10V/V. The output voltage ports their use in high side and low side battery current (V ) is a weighted sum of the inputs (V , V , and V ), OUT 1 2 3 sensing applications. The very low quiescent current and is shifted by the V input. The necessary REF (0.6μA, typ.) help prolong battery life, and the calculations follow in Equation4-3. rail-to-rail output supports detection low currents. . Figure4-9 shows a high side battery current sensor R 1 circuit. The 1kΩ resistor is sized to minimize power V 1 losses. The battery current (IDD) through the 1kΩ R2 resistor causes its top terminal to be more negative V 2 than the bottom terminal. This keeps the Common R R mode input voltage of the op amp at V , which is 3 F DD V V within its allowed range. When no current is flowing, the 3 OUT output will be at its Maximum Output Voltage Swing (VOH), which is virtually at VDD. MCP614X . VREF V DD V DD FIGURE 4-10: Summing Amplifier. V OUT 1kΩ I MCP6141 EQUATION 4-3: DD Noise Gain: 100kΩ VSS 1.4V to G = 1+R ⎛--1----+--1----+--1----⎞ ≥10 V/V 5.5V N F⎝R R R ⎠ 1 2 3 1MΩ Signal Gains: VSS G = –R ⁄R 1 F 1 FIGURE 4-9: High Side Battery Current G2 = –RF⁄R2 Sensor. G = –R ⁄R 3 F 3 Output Signal: V = V G +V G +V G +V G OUT 1 1 2 2 3 3 REF N © 2005 Microchip Technology Inc. DS21668B-page 15

MCP6141/2/3/4 5.0 DESIGN TOOLS Microchip provides the basic design tools needed for the MCP6141/2/3/4 family of op amps. 5.1 SPICE Macro Model The latest SPICE macro model for the MCP6141/2/3/4 op amps is available on our web site at www.micro- chip.com. This model is intended to be an initial design tool that works well in the op amp’s linear region of operation at room temperature. See the model file for information on its capabilities. Bench testing is a very important part of any design and cannot be replaced with simulations. Also, simulation results using this macro model need to be validated by comparing them to the data sheet specifications and characteristic curves. 5.2 FilterLab® Software The FilterLab software is an innovative tool that simplifies analog active filter (using op amps) design. It is available free of charge from our web site at www.microchip.com. The FilterLab software tool provides full schematic diagrams of the filter circuit with component values. It also outputs the filter circuit in SPICE format, which can be used with the macro model to simulate actual filter performance. DS21668B-page 16 © 2005 Microchip Technology Inc.

MCP6141/2/3/4 6.0 PACKAGING INFORMATION 6.1 Package Marking Information 5-Lead SOT-23 (MCP6141) Example: Device E-Temp Code XXNN MCP6141 ASNN AS25 Note: Applies to 5-Lead SOT-23 6-Lead SOT-23 (MCP6143) Example: Device E-Temp Code XXNN MCP6143 AWNN AW25 Note: Applies to 6-Lead SOT-23 8-Lead MSOP Example: XXXXXX 6143I YWWNNN 536256 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2005 Microchip Technology Inc. DS21668B-page 17

MCP6141/2/3/4 Package Marking Information (Continued) 8-Lead PDIP (300 mil) Example: XXXXXXXX MCP6141 MCP6141 XXXXXNNN I/P256 E/P e 3 256 OR YYWW 0223 0536 8-Lead SOIC (150 mil) Example: XXXXXXXX MCP6142 MCP6142E XXXXYYWW I/SN0223 OR SN e3 0536 NNN 256 256 14-Lead PDIP (300 mil) (MCP6144) Example: XXXXXXXXXXXXXX MCP6144-I/P XXXXXXXXXXXXXX YYWWNNN 0434256 MCP6144 OR I/P e3 0536256 DS21668B-page 18 © 2005 Microchip Technology Inc.

MCP6141/2/3/4 Package Marking Information (Continued) 14-Lead SOIC (150 mil) (MCP6144) Example: XXXXXXXXXX MCP6144ISL XXXXXXXXXX YYWWNNN 0434256 MCP6144 OR I/SL^e^3 0536256 14-Lead TSSOP (MCP6144) Example: XXXXXXXX 6144ST YYWW 0534 NNN 256 6144EST 0534 OR 256 © 2005 Microchip Technology Inc. DS21668B-page 19

MCP6141/2/3/4 5-Lead Plastic Small Outline Transistor (OT) (SOT-23) E E1 p B p1 D n 1 α c A A2 φ A1 L β Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 5 5 Pitch p .038 0.95 Outside lead pitch (basic) p1 .075 1.90 Overall Height A .035 .046 .057 0.90 1.18 1.45 Molded Package Thickness A2 .035 .043 .051 0.90 1.10 1.30 Standoff A1 .000 .003 .006 0.00 0.08 0.15 Overall Width E .102 .110 .118 2.60 2.80 3.00 Molded Package Width E1 .059 .064 .069 1.50 1.63 1.75 Overall Length D .110 .116 .122 2.80 2.95 3.10 Foot Length L .014 .018 .022 0.35 0.45 0.55 Foot Angle f 0 5 10 0 5 10 Lead Thickness c .004 .006 .008 0.09 0.15 0.20 Lead Width B .014 .017 .020 0.35 0.43 0.50 Mold Draft Angle Top a 0 5 10 0 5 10 Mold Draft Angle Bottom b 0 5 10 0 5 10 *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. EIAJ Equivalent: SC-74A Drawing No. C04-091 Revised 09-12-05 DS21668B-page 20 © 2005 Microchip Technology Inc.

MCP6141/2/3/4 6-Lead Plastic Small Outline Transistor (CH) (SOT-23) E E1 B p1 D n 1 α c φ A A2 β L A1 Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 6 6 Pitch p .038 BSC 0.95 BSC Outside lead pitch p1 .075 BSC 1.90 BSC Overall Height A .035 .046 .057 0.90 1.18 1.45 Molded Package Thickness A2 .035 .043 .051 0.90 1.10 1.30 Standoff A1 .000 .003 .006 0.00 0.08 0.15 Overall Width E .102 .110 .118 2.60 2.80 3.00 Molded Package Width E1 .059 .064 .069 1.50 1.63 1.75 Overall Length D .110 .116 .122 2.80 2.95 3.10 Foot Length L .014 .018 .022 0.35 0.45 0.55 φ Foot Angle 0 5 10 0 5 10 Lead Thickness c .004 .006 .008 0.09 0.15 0.20 Lead Width B .014 .017 .020 0.35 0.43 0.50 Mold Draft Angle Top α 0 5 10 0 5 10 Mold Draft Angle Bottom β 0 5 10 0 5 10 *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. BSC: Basic Dimension. Theoretically exact value shown without tolerances. See ASME Y14.5M JEITA (formerly EIAJ) equivalent: SC-74A Revised 09-12-05 Drawing No. C04-120 © 2005 Microchip Technology Inc. DS21668B-page 21

MCP6141/2/3/4 8-Lead Plastic Micro Small Outline Package (MS) (MSOP) E E1 p D 2 B n 1 α c φ A A2 F L A1 β Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch p .026 BSC 0.65 BSC Overall Height A - - .043 - - 1.10 Molded Package Thickness A2 .030 .033 .037 0.75 0.85 0.95 Standoff A1 .000 - .006 0.00 - 0.15 Overall Width E .193 BSC 4.90 BSC Molded Package Width E1 .118 BSC 3.00 BSC Overall Length D .118 BSC 3.00 BSC Foot Length L .016 .024 .031 0.40 0.60 0.80 Footprint (Reference) F .037 REF 0.95 REF φ Foot Angle 0° - 8° 0° - 8° Lead Thickness c .003 .006 .009 0.08 - 0.23 Lead Width B .009 .012 .016 0.22 - 0.40 Mold Draft Angle Top α 5° - 15° 5° - 15° Mold Draft Angle Bottom β 5° - 15° 5° - 15° * Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. BSC: Basic Dimension. Theoretically exact value shown without tolerances. See ASME Y14.5M REF: Reference Dimension, usually without tolerance, for information purposes only. See ASME Y14.5M JEDEC Equivalent: MO-187 Revised 07-21-05 Drawing No. C04-111 DS21668B-page 22 © 2005 Microchip Technology Inc.

MCP6141/2/3/4 8-Lead Plastic Dual In-line (P) – 300 mil Body (PDIP) E1 D 2 n 1 α E A A2 L c A1 β B1 p eB B Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch p .100 2.54 Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32 Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26 Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60 Overall Length D .360 .373 .385 9.14 9.46 9.78 Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43 Lead Thickness c .008 .012 .015 0.20 0.29 0.38 Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78 Lower Lead Width B .014 .018 .022 0.36 0.46 0.56 Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92 Mold Draft Angle Top α 5 10 15 5 10 15 Mold Draft Angle Bottom β 5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018 © 2005 Microchip Technology Inc. DS21668B-page 23

MCP6141/2/3/4 8-Lead Plastic Micro Small Outline Package (MS) (MSOP) E1 D 2 n 1 α E A A2 L c A1 β B1 p eB B Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch p .100 2.54 Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32 Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26 Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60 Overall Length D .360 .373 .385 9.14 9.46 9.78 Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43 Lead Thickness c .008 .012 .015 0.20 0.29 0.38 Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78 Lower Lead Width B .014 .018 .022 0.36 0.46 0.56 Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92 Mold Draft Angle Top α 5 10 15 5 10 15 Mold Draft Angle Bottom β 5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018 DS21668B-page 24 © 2005 Microchip Technology Inc.

MCP6141/2/3/4 14-Lead Plastic Dual In-line (P) – 300 mil Body (PDIP) E1 D 2 n 1 α E A A2 c L A1 β B1 eB B p Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 14 14 Pitch p .100 2.54 Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32 Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26 Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60 Overall Length D .740 .750 .760 18.80 19.05 19.30 Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43 Lead Thickness c .008 .012 .015 0.20 0.29 0.38 Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78 Lower Lead Width B .014 .018 .022 0.36 0.46 0.56 Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92 Mold Draft Angle Top α 5 10 15 5 10 15 Mold Draft Angle Bottom β 5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-005 © 2005 Microchip Technology Inc. DS21668B-page 25

MCP6141/2/3/4 14-Lead Plastic Small Outline (SL) – Narrow, 150 mil Body (SOIC) E E1 p D 2 B n 1 α h 45° c A A2 φ A1 L β Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 14 14 Pitch p .050 1.27 Overall Height A .053 .061 .069 1.35 1.55 1.75 Molded Package Thickness A2 .052 .056 .061 1.32 1.42 1.55 Standoff § A1 .004 .007 .010 0.10 0.18 0.25 Overall Width E .228 .236 .244 5.79 5.99 6.20 Molded Package Width E1 .150 .154 .157 3.81 3.90 3.99 Overall Length D .337 .342 .347 8.56 8.69 8.81 Chamfer Distance h .010 .015 .020 0.25 0.38 0.51 Foot Length L .016 .033 .050 0.41 0.84 1.27 Foot Angle φ 0 4 8 0 4 8 Lead Thickness c .008 .009 .010 0.20 0.23 0.25 Lead Width B .014 .017 .020 0.36 0.42 0.51 Mold Draft Angle Top α 0 12 15 0 12 15 Mold Draft Angle Bottom β 0 12 15 0 12 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-065 DS21668B-page 26 © 2005 Microchip Technology Inc.

MCP6141/2/3/4 14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body (TSSOP) E E1 p D 2 n 1 B α A c φ β L A1 A2 Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 14 14 Pitch p .026 BSC 0.65 BSC Overall Height A .039 .041 .043 1.00 1.05 1.10 Molded Package Thickness A2 .033 .035 .037 0.85 0.90 0.95 Standoff A1 .002 .004 .006 0.05 0.10 0.15 Overall Width E .246 .251 .256 6.25 6.38 6.50 Molded Package Width E1 .169 .173 .177 4.30 4.40 4.50 Molded Package Length D .193 .197 .201 4.90 5.00 5.10 Foot Length L .020 .024 .028 0.50 0.60 0.70 φ Foot Angle 0° 4° 8° 0° 4° 8° Lead Thickness c .004 .006 .008 0.09 0.15 0.20 Lead Width B .007 .010 .012 0.19 0.25 0.30 Mold Draft Angle Top α 12° REF 12° REF Mold Draft Angle Bottom β 12° REF 12° REF * Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. BSC: Basic Dimension. Theoretically exact value shown without tolerances. See ASME Y14.5M REF: Reference Dimension, usually without tolerance, for information purposes only. See ASME Y14.5M JEDEC Equivalent: MO-153 AB-1 Drawing No. C04-087 Revised: 08-17-05 © 2005 Microchip Technology Inc. DS21668B-page 27

MCP6141/2/3/4 NOTES: DS21668B-page 28 © 2005 Microchip Technology Inc.

MCP6141/2/3/4 APPENDIX A: REVISION HISTORY Revision B (November 2005) The following is the list of modifications: 1. Added the following: a) SOT-23-5 package for the MCP6141 single op amps. b) SOT-23-6 package for the MCP6143 single op amps with Chip Select. c) Extended Temperature (-40°C to +125°C) op amps. 2. Updated specifications in Section1.0 “Electri- cal Characteristics” for E-temp parts. 3. Corrected and updated plots in Section2.0 “Typical Performance Curves”. 4. Added Section3.0 “Pin Descriptions”. 5. Updated Section4.0 “Applications Informa- tion” and added section on unused op amps. 6. Updated Section5.0 “Design Tools” to include FilterLab. 7. Added SOT-23-5 and SOT-23-6 packages and corrected package marking information in Section6.0 “Packaging Information”. 8. Added Appendix A: “REVISION HISTORY”. Revision A (September 2002) (cid:129) Original Release of this Document. © 2005 Microchip Technology Inc. DS21668B-page 29

MCP6141/2/3/4 NOTES: DS21668B-page 30 © 2005 Microchip Technology Inc.

MCP6141/2/3/4 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. - X / XX Examples: a) MCP6141-I/P: Industrial Temp., 8LD PDIP package. Device Temperature Package b) MCP6141T-E/OT: Tape and Reel, Range Extended Temp., 5LD SOT-23 package. Device: MCP6141: Single Op Amp MCP6141T: Single Op Amp a) MCP6142-I/SN: Industrial Temp., (Tape and Reel for SOT-23, SOIC, MSOP) 8LD SOIC package. MCP6142: Dual Op Amp MCP6142T: Dual Op Amp b) MCP6142T-E/MS: Tape and Reel, (Tape and Reel for SOIC and MSOP) Extended Temp., MCP6143: Single Op Amp w/ CS 8LD MSOP package. MCP6143T: Single Op Amp w/ CS (Tape and Reel for SOT-23, SOIC, MSOP) MCP6144: Quad Op Amp a) MCP6143-I/P: Industrial Temp., MCP6144T: Quad Op Amp 8LD PDIP package. (Tape and Reel for SOIC and TSSOP) b) MCP6143T-E/CH: Tape and Reel, Extended Temp., 6LD SOT-23 package. Temperature I = -40°C to +85°C (Industrial) Range: E = -40°C to +125°C (Extended) a) MCP6144-I/SL: Industrial Temp., 14LD PDIP package. Package: CH = Plastic Small Outline Transistor (SOT-23), 6-lead (Tape and Reel - MCP6143 only) b) MCP6144T-E/ST: Tape and Reel, MS = Plastic Micro Small Outline (MSOP), 8-lead Extended Temp., OT = Plastic Small Outline Transistor (SOT-23), 14LD TSSOP package. 5-lead (Tape and Reel - MCP6141 only) P = Plastic DIP (300 mil Body), 8-lead, 14-lead SL = Plastic SOIC (150 mil Body), 14-lead SN = Plastic SOIC (150 mil Body), 8-lead ST = Plastic TSSOP (4.4 mm Body), 14-lead © 2005 Microchip Technology Inc. DS21668B-page 31

MCP6141/2/3/4 NOTES: DS21668B-page 32 © 2005 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: (cid:129) Microchip products meet the specification contained in their particular Microchip Data Sheet. (cid:129) Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. (cid:129) There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. (cid:129) Microchip is willing to work with the customer who is concerned about the integrity of their code. (cid:129) Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, Accuron, and may be superseded by updates. It is your responsibility to dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, ensure that your application meets with your specifications. PICSTART, PROMATE, PowerSmart, rfPIC, and MICROCHIP MAKES NO REPRESENTATIONS OR WAR- SmartShunt are registered trademarks of Microchip RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, Technology Incorporated in the U.S.A. and other countries. WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, PICMASTER, SEEVAL, SmartSensor and The Embedded MERCHANTABILITY OR FITNESS FOR PURPOSE. Control Solutions Company are registered trademarks of Microchip disclaims all liability arising from this information and Microchip Technology Incorporated in the U.S.A. its use. Use of Microchip’s products as critical components in Analog-for-the-Digital Age, Application Maestro, dsPICDEM, life support systems is not authorized except with express dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, written approval by Microchip. No licenses are conveyed, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial implicitly or otherwise, under any Microchip intellectual property Programming, ICSP, ICEPIC, Linear Active Thermistor, rights. MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance and WiperLock are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2005, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company’s quality system processes and procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2005 Microchip Technology Inc. DS21668B-page 33

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