M MCP6141/2/3/4 600 nA, Non-Unity Gain Rail-to-Rail Input/Output Op Amps Features Description • Low Quiescent Current: 600nA/Amplifier (typ.) The MCP6141/2/3/4 family of non-unity gain stable • Stable for gains of 10V/V or higher operational amplifiers (op amps) from Microchip Technology, Inc. operate with a single supply voltage • Rail-to-Rail Input: -0.3V (min.) to V + 0.3V (max.) DD as low as 1.4V, while drawing less than 1µA (max.) of • Rail-to-Rail Output: quiescent current per amplifier. These devices are also - VSS+10mV (min.) to VDD-10mV (max.) designed to support rail-to-rail input and output swing. • Gain Bandwidth Product: 100kHz (typ.) The MCP6141/2/3/4 op amps have a gain bandwidth • Wide Supply Voltage Range: 1.4V to 5.5V (max.) product of 100kHz (typ.) and are stable for gains of • Available in Single, Dual and Quad 10V/V or higher. This specification makes these • Chip Select (CS) with MCP6143 devices appropriate for battery-powered applications where higher frequency responses from the amplifier Applications are required. The MCP6141/2/3/4 family of op amps are offered in • Toll Booth Tags single (MCP6141), single with a Chip Select (CS) fea- • Wearable Products ture (MCP6143), dual (MCP6142) and quad • Temperature Measurement (MCP6144) configurations. • Battery-Powered Typical Applications Available Tools V DD • Spice macro models (at www.microchip.com) V DD • FilterLab® Software (at www.microchip.com) Package Types 1kΩ IDD MCP614X MCP6141 MCP6142 PDIP, SOIC, MSOP PDIP, SOIC, MSOP +1.4V VSS to R I NC 1 8 NC OUTA 1 8 VDD 5.5V 100kΩ A -IN 2 - 7 V -INA 2 - + 7 OUTB +IN 3 + 6 ODUDT +INA 3 +B- 6 -INB RF = 1MΩ VSS 4 5 NC VSS 4 5 +INB High Side Battery Current Sensor MCP6143 MCP6144 Gn = 1+R-R---F-- ≥10V/V I PDIP, SOIC, MSOP PDIP, SOIC, TSSOP R NC 1 8 CS OUTA 1 14OUTD V 1 1 -IN 2 - 7 VDD -INA1 2 -A+ +D- 13-IND I1 R +IN 3 + 6 OUT +INA1 3 12+IND V 2 2 VSS 4 5 NC +IVNDBD54 1101+VISNSC V R3 I2 RF 3 -INB 6 -B+ +C- 9 -INC I3 IF OUTB1 7 8 OUTC V V OUT REF MCP614X Summing Amplifier  1 1 1 Gn = 1+RFR------+R------+R------ ≥10V/V 1 2 3  2002 Microchip Technology Inc. 21668A-page 1

MCP6141/2/3/4 1.0 ELECTRICAL PIN FUNCTION TABLE CHARACTERISTICS Name Function 1.1 Maximum Ratings† +IN/+INA/+INB/+INC/+IND Non-inverting Inputs -IN/-INA/-INB/-INC/-IND Inverting Inputs V - V .........................................................................7.0V DD SS V Positive Power Supply All inputs and outputs........................V -0.3V to V +0.3V DD SS DD V Negative Power Supply Difference Input voltage .......................................|V - V | SS DD SS OUT/OUTA/OUTB/OUTC/OUTD Outputs Output Short Circuit Current ..................................continuous CS Chip Select Current at Input Pins ....................................................±2mA Current at Output and Supply Pins ............................±30mA NC No internal connection Storage temperature.....................................-65°C to +150°C Junction Temperature, T ............................................+150°C J ESD protection on all pins (HBM:MM)..................≥ 4kV:200V †Notice: Stresses above those listed under “Maximum Rat- ings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Expo- sure to maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, all limits are specified for V = +1.4V to +5.5V, V = GND, T = 25°C, DD SS A V = V /2, R = 1MΩ to V /2, and V ~ V /2. CM DD L DD OUT DD Parameters Sym Min Typ Max Units Conditions Input Offset V = V CM SS Input Offset Voltage V -3.0 — +3.0 mV OS Drift with Temperature ∆V /∆T — ±1.5 — µV/°C T = -40°C to +85°C OS A Power Supply Rejection PSRR 70 85 — dB Input Bias Current and Impedance Input Bias Current I — 1.0 — pA B Input Bias Current Over-Temperature I — — 100 pA T = -40°C to +85°C B A Input Offset Current I — 1.0 — pA OS Common Mode Input Impedance Z — 1013||6 — Ω||pF CM Differential Input Impedance Z — 1013||6 — Ω||pF DIFF Common Mode Common-Mode Input Range VCMR V − 0.3 — V + 0.3 V SS DD Common-Mode Rejection Ratio CMRR 62 80 — dB V = 5V, DD V = -0.3V to 5.3V CM 60 75 — dB V = 5V, DD V = 2.5V to 5.3V CM 60 80 — dB V = 5V, DD V = -0.3V to 2.5V CM Open Loop Gain DC Open Loop Gain (large signal) A 95 115 — dB R = 50kΩ to V /2, OL L DD 100mV < V < OUT (V − 100mV) DD Output Maximum Output Voltage Swing V , V V + 10 — V − 10 mV R = 50kΩ to V /2 OL OH SS DD L DD Output Short Circuit Current I — 21 — mA V = 2.5V, V = 5V O OUT DD Power Supply Supply Voltage V 1.4 — 5.5 V DD Quiescent Current per amplifier I 0.3 0.6 1.0 µA I = 0 Q O 21668A-page 2 2002 Microchip Technology Inc.

MCP6141/2/3/4 AC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, all limits are specified for V = +5V, V = GND, T = 25 °C, DD SS A V = V /2, R = 1MΩ to V /2, C = 60pF, and V ~ V /2. CM DD L DD L OUT DD Parameters Sym Min Typ Max Units Conditions Gain Bandwidth Product GBWP — 100 — kHz Slew Rate SR — 24 — V/ms Phase Margin PM — 60 — ° G = +10 Input Voltage Noise E — 5.0 — µVp-p f = 0.1Hz to 10Hz n Input Voltage Noise Density e — 170 — nV/√Hz f = 1kHz n Input Current Noise Density i — 0.6 — fA/√Hz f = 1kHz n SPECIFICATIONS FOR MCP6143 CHIP SELECT FEATURE Electrical Characteristics: Unless otherwise indicated, all limits are specified for V = +1.4V to +5.5V, V = GND, T = 25 °C, DD SS A V = V /2, R = 1MΩ to V /2, C = 60pF, and V ~ V /2. CM DD L DD L OUT DD Parameters Sym Min Typ Max Units Conditions CS Low Specifications CS Logic Threshold, Low V V — V + 0.3 V For entire V range IL SS SS DD CS Input Current, Low I — 5.0 — pA CS = V CSL SS CS High Specifications CS Logic Threshold, High V V - 0.3 — V V For entire V range IH DD DD DD CS Input Current, High I — 5.0 — pA CS = V CSH DD CS Input High, GND Current I — 20 — pA CS = V Q DD Amplifier Output Leakage, CS High — 20 — pA CS = V DD Dynamic Specifications CS Low to Amplifier Output High t — 2.0 50 ms CS low = V + 0.3V, G = +1V/V, ON SS Turn-on Time V = 0.9V /2 OUT DD t — 10 — µs CS high = V - 0.3V, G = +1V/V CS High to Amplifier Output High Z OFF DD V = 0.1V /2 OUT DD Hysteresis V — 0.6 — V V = 5V HYST DD TEMPERATURE SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, all limits are specified for V = +1.4V to +5.5V, V = GND. DD SS Parameters Symbol Min Typ Max Units Conditions Temperature Ranges Specified Temperature Range T -40 — +85 °C A Operating Temperature Range T -40 — +125 °C Note1 A Storage Temperature Range T -65 — +150 °C A Thermal Package Resistances Thermal Resistance, 8L-PDIP θ — 85 — °C/W JA Thermal Resistance, 8L-SOIC θ — 163 — °C/W JA Thermal Resistance, 8L-MSOP θ — 206 — °C/W JA Thermal Resistance, 14L-PDIP θ — 70 — °C/W JA Thermal Resistance, 14L-SOIC θ — 108 — °C/W JA Thermal Resistance, 14L-TSSOP θ — 100 — °C/W JA Note 1: The MCP6141/2/3/4 family of op amps operates over this extended range, but with reduced performance.  2002 Microchip Technology Inc. 21668A-page 3

MCP6141/2/3/4 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, V = +5V, V = GND, T = 25°C, V = V /2, R = 1MΩ to V /2, C = 60pF, DD SS A CM DD L DD L and V ~V /2. OUT DD 16% 35% s 1200 Samples s 1200 Samples ce14% V = 5.5 V ce30% V = 1.4 V n DD n DD urre12% urre25% c10% c Oc Oc20% e of 68%% e of 15% g g nta 4% nta10% e e erc 2% erc 5% P P 0% 0% -3 -2 -1 0 1 2 3 -10 -5 0 5 10 Input Offset Voltage (mV) Input Offset Voltage Drift (µV/°C) FIGURE 2-1: Histogram of Input Offset FIGURE 2-4: Histogram of Input Offset Voltage with V = 5.5V. Voltage Drift with V = 1.4V. DD DD 16% 600 ces14% 1V20 0= S1a.4m Vples V) 400 VDD = 1.4 V n DD µ urre12% ge ( 200 Occ10% olta e of 68%% set V 0 ag Off -200 T = +85°C ent 4% ut TA = +25°C Perc 2% Inp -400 TAA = -40°C 0% -600 -3 -2 -1 0 1 2 3 -0.5 0.0 0.5 1.0 1.5 2.0 Input Offset Voltage (mV) Common Mode Input Voltage (V) FIGURE 2-2: Histogram of Input Offset FIGURE 2-5: Input Offset Voltage vs. Voltage with V = 1.4V. Common Mode Input Voltage vs. Temperature DD with V = 1.4V. DD 35% 600 nces30% 1V2DD0 0= S5a.5m Vples µV) 400 VDD = 5.5 V TA = +85°C curre25% age ( 200 TTAA == +-4205°°CC Oc20% olt e of 15% set V 0 centag105%% put Off--420000 TTTAAA === ++-482055°°°CCC Per In 0% -600 -10 -5 0 5 10 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 Input Offset Voltage Drift (µV/°C) Common Mode Input Voltage (V) FIGURE 2-3: Histogram of Input Offset FIGURE 2-6: Input Offset Voltage vs. Voltage Drift with VDD = 5.5V. Common Mode Input Voltage vs. Temperature with V = 5.5V. DD 21668A-page 4 2002 Microchip Technology Inc.

MCP6141/2/3/4 Note: Unless otherwise indicated, V = +5V, V = GND, T = 25°C, V = V /2, R = 1MΩ to V /2, C = 60pF, DD SS A CM DD L DD L and V ~V /2. OUT DD e (µV) 455000 RL = 50 k(cid:58) ents (pA) 4500 TVAD D= = 8 55°.5C V put Offset Voltag 334050000 VDD = 1.4 V VDD = 5.5 V Bias, Offset Curr 123000 Input Bias Current In ut Input Offset Current p 250 n 0 I 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Output Voltage (V) Common Mode Input Voltage (V) FIGURE 2-7: Input Offset Voltage vs. FIGURE 2-10: Input Bias, Offset Currents Output Voltage vs. Power Supply Voltage. vs. Common Mode Input Voltage with Temperature = 85°C. 1,000 300 y E = 4.7 µV , f = 0.1 to 10 Hz y f = 1 kHz ensit ennii = 167 nVP/-(cid:151)PHz, f = 1 kHz ensit 250 VDD = 5.0 V Input Noise Voltage D(nV/Hz)(cid:151)100 Input Noise Voltage D(nV/Hz)(cid:151)112050500000 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 0.1 1 10 100 1000 Frequency (Hz) Common Mode Input Voltage (V) FIGURE 2-8: Input Noise Voltage Density FIGURE 2-11: Input Noise Voltage Density vs. Frequency. vs. Common Mode Input Voltage. 100 100 90 PSRR- PSRR+ VRDeDfe =r r5e.d0 tVo Input 95 B) 80 B) d d PSRR ( 6700 CMRR PSRR ( 8950 PSRR (VCM = VSS) R, 50 R, R R 80 M 40 M C C 30 75 CMRR (VDD = 5.0 V, V = -0.3 V to +5.3 V) 20 CM 70 1 1100 110000 1000 -40 -20 0 20 40 60 80 Frequency (Hz) Ambient Temperature (°C) FIGURE 2-9: Common Mode Rejection FIGURE 2-12: Common Mode Rejection Ratio, Power Supply Rejection Ratio vs. Ratio, Power Supply Rejection Ratio vs. Ambient Frequency. Temperature.  2002 Microchip Technology Inc. 21668A-page 5

MCP6141/2/3/4 Note: Unless otherwise indicated, V = +5V, V = GND, T = 25°C, V = V /2, R = 1MΩ to V /2, C = 60pF, DD SS A CM DD L DD L and V ~V /2. OUT DD urrents 4500 VVCDMD == 5V.D5D V amplifier 00..67 et C per 0.5 as and Offs(pA) 2300 ICnupruret nBtias nt Current (mA) 000...234 TTA AT= A =8 =52 °5-C4°C0°C Bi 10 Input Offset ce ut Current es 0.1 Inp 0 Qui 0.0 25 35 45 55 65 75 85 0.00.51.01.52.02.53.03.54.04.55.05.56.06.57.0 Ambient Temperature (°C) Power Supply Voltage (V) FIGURE 2-13: Input Bias and Offset FIGURE 2-16: Quiescent Current Vs. Currents vs. Ambient Temperature. Power Supply Voltage vs. Temperature. 120 0 140 V = 5.5 V Open-Loop Gain (dB) 102468000000 V = 5P.5h aVse Gain ------111963852000000 Open-Loop Phase (°) Open-Loop Gain (dB) 1111890123000000 VDOVVDUTDO DU= T = 0= .1 50. 4.V5 V tVo t5o. 00 .V9 V -20 DD -210 DC 70 0.01 0.1 1 10 100 1k1000 10k10000 100k00000 60100 1k 10k 100k Frequency (Hz) 1 Load Resistance ((cid:58)) FIGURE 2-14: Open Loop Gain, Phase vs. FIGURE 2-17: DC Open Loop Gain vs. Frequency with V = 5.5V. Load Resistance vs. Power Supply Voltage. DD 140 ain 140 ain (dB) 112300 en Loop G 111123000 RL = 50 k(cid:58) VDD = 5.5 V en Loop G 11901000 gnal DC Op(dB) 1890000 VDD = 1.4 V C Op 80 RL = 50 k(cid:58) all Si 70 D 70 VOUT = 100 mV to VDD - 100 mV Sm 60 60 0.00 0.05 0.10 0.15 0.20 0.25 0.30 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Output Voltage Headroom; Power Supply Voltage (V) VDD-VOUT or VOUT-VSS (V) FIGURE 2-15: DC Open Loop Gain vs. FIGURE 2-18: Small Signal DC Open Loop Power Supply Voltage. Gain vs. Output Voltage Headroom vs. Power Supply. 21668A-page 6 2002 Microchip Technology Inc.

MCP6141/2/3/4 Note: Unless otherwise indicated, V = +5V, V = GND, T = 25°C, V = V /2, R = 1MΩ to V /2, C = 60pF, DD SS A CM DD L DD L and V ~V /2. OUT DD on 140 180 90 o-Channel Separati(dB)111123000 andwidth Product (kHz) 1111024668000000 GainP Bhaasned wMiadrtghi nProduct 345678000000 ase Margin (°) el-t 100 n B 40 20 Ph ann Input-Referred Gai 20 10 Ch 90 0 0 1010k0 11000k00 5 0 5 0 5 0 5 0 5 0 5 0 5 0. 0. 0. 1. 1. 2. 2. 3. 3. 4. 4. 5. 5. - Frequency (Hz) Common Mode Input Voltage (V) FIGURE 2-19: Channel to Channel FIGURE 2-22: Gain Bandwidth Product, Separation vs. Frequency (MCP6142 and Phase Margin vs. Common Mode Input Voltage. MCP6144 only). 120 90 120 90 uct 100 Gain Bandwidth Product 75 ct 100 Gain Bandwidth Product 75 Bandwidth Prod(kHz)468000 Phase Margin 346050hase Margin (°) Bandwidth Produ(kHz)468000 Phase Margin 346050 hase Margin (°) n P n P Gai 20 VDD = 5.5 V 15 Gai 20 VDD = 1.4 V 15 0 0 CL = 60 pF 0 0 -40 -20 0 20 40 60 80 -40 -20 0 20 40 60 80 Ambient Temperature (°C) Ambient Temperature (°C) FIGURE 2-20: Gain Bandwidth Product, FIGURE 2-23: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature with Phase Margin vs. Ambient Temperature with V = 5.5V. V = 1.4V. DD DD Closed Loop Gain Frequency (kHz)11246802 GVD =D =+ 150.5 VC VP/lVhosaesed MLoaorgpi nGain Frequency 134679505050Phase Margin (°) utput Short Circuit Current (pA)112233450505050 -+ISICSC, ,V VDDDD = = 1 1.4.4 V V -I+SICS,C V, VDDD D= =5 .55. 5V V 0 0 O 0 01.00p0 100.000p 01.n00 -40 -20 0 20 40 60 80 Load Capacitance (F) Ambient Temperature (°C) FIGURE 2-21: Closed Loop Gain FIGURE 2-24: Output Short Circuit Current Frequency, Phase Margin vs. Load Capacitance vs. Ambient Temperature vs. Power Supply with V =5.5V. Voltage. DD  2002 Microchip Technology Inc. 21668A-page 7

MCP6141/2/3/4 Note: Unless otherwise indicated, V = +5V, V = GND, T = 25°C, V = V /2, R = 1MΩ to V /2, C = 60pF, DD SS A CM DD L DD L and V ~V /2. OUT DD 50 10 P) s) 4405 Falling Edge g (VP- VDD = 5.5 V m 35 n ate (V/ 2350 ge Swi 1 VDD = 1.4 V w R 20 Rising Edge olta e 15 V Sl 10 put 5 ut O 0.1 0 110000 1100k0 11000k00 -40 -20 0 20 40 60 80 Ambient Temperature (°C) Frequency (Hz) FIGURE 2-25: Slew Rate vs. Ambient FIGURE 2-28: Output Voltage Swing vs. Temperature. Frequency vs. Power Supply Voltage. mV) 1,000 V) 4.0 V = 5.5 V om ( m (m 3.5 RDL D= 50 k(cid:58) o o 3.0 adr 100 VOL-VSS, VDD = 1.4 V dro 2.5 e a H e ge e H 2.0 VOL - VSS Output Volta 101 VOL-VSS, VDD = 5.5 V Output Voltag 011...505 VDD - VOH 1.1E0-µ05 11.0E0-0µ4 1.1Em-03 11.E0m-02 0.0 -40 -20 0 20 40 60 80 Output Current Magnitude (A) Ambient Temperature (°C) FIGURE 2-26: Output Voltage Headroom FIGURE 2-29: Output Voltage Headroom vs. Output Current Magnitude vs. Power Supply vs. Ambient Temperature with V = 5.5V. DD Voltage. 0.08 G = +11 V/V 0.08 G = -10 V/V div) 0.06 RL = 50 k(cid:58) div) 0.06 RF = 50 k(cid:58) V/ 0.04 V/ 0.04 m m Voltage (20 -000...000022 Voltage (20 -000...000022 ut ut p-0.04 p-0.04 ut ut O O -0.06 -0.06 -0.008.E+00 1.E-04 2.E-04 3.E-04 Tim4.E-04e (105.E-004 µs/6.dE-04iv) 7.E-04 8.E-04 9.E-04 1.E-03 -0.008.E+00 1.E-04 2.E-04 3.E-04 Tim4.E-04e (105.E-004 µs/6.dE-04iv) 7.E-04 8.E-04 9.E-04 1.E-03 FIGURE 2-27: Small Signal Non-Inverting FIGURE 2-30: Small Signal Inverting Pulse Pulse Response vs. Time. Response vs. Time. 21668A-page 8 2002 Microchip Technology Inc.

MCP6141/2/3/4 Note: Unless otherwise indicated, V = +5V, V = GND, T = 25°C, V = V /2, R = 1MΩ to V /2, C = 60pF, DD SS A CM DD L DD L and V ~V /2. OUT DD 5.0 5.0 G = +11 V/V G = -10 V/V 4.5 4.5 RL = 50 k(cid:58) RF = 50 k(cid:58) 4.0 4.0 e (V) 3.5 e (V) 3.5 ag 3.0 ag 3.0 olt 2.5 olt 2.5 V V ut 2.0 ut 2.0 p p ut 1.5 ut 1.5 O O 1.0 1.0 0.5 0.5 0.0 0.0 0.E+00 2.E-04 4.E-04 6.E-04 8.E-04 1.E-03 1.E-03 1.E-03 2.E-03 2.E-03 2.E-03 0.E+00 2.E-04 4.E-04 6.E-04 8.E-04 1.E-03 1.E-03 1.E-03 2.E-03 2.E-03 2.E-03 Time (200 µs/div) Time (200 µs/div) FIGURE 2-31: Large Signal Non-Inverting FIGURE 2-34: Large Signal Inverting Pulse Pulse Response vs. Time. Response vs. Time. 27.5 5.5 5.5 G = +11 V/V 25.0 5.0 5.0 22.5 VOUT on VIN = 3.0 V VOUT on 4.5 4.5 VOUT on oltage (V) 1111202570.....05050 VOUT Hi-Z 22334.....05050 put Voltage (V) utput Voltage (V) 122334......505050 ChiSg hs wtoe plotw HyClosStwe s rtewos ehispigthVOUT HI-Z ct V 7.5 1.5 Out O 1.0 G = +11 V/V ele 5.0 CS Voltage 1.0 0.5 VIN = 3.0 V S 2.5 0.5 0.0 p Chi 0.0 0.E+00 1.E-03 2.E-03 3.E-03 Tim4.E-03e (15.E -0m3 s/d6.E-0i3v) 7.E-03 8.E-03 9.E-03 1.E-02 0.0 0.0 0.5 1.0 C1h.5ip 2S.e0lec2t. 5Vol3t.a0ge3 (.V5) 4.0 4.5 5.0 FIGURE 2-32: Chip Select (CS) to FIGURE 2-35: Output Voltage vs. Chip Amplifier Output Response Time Select (CS) Voltage (MCP6143 only). (MCP6143 only). 6 G = +11 V/V V) 5 s ( e 4 g a olt 3 V put 2 ut V O IN put, 1 VOUT n 0 I -1 0.E+00 5.E-03 1.E-02 2.E-02 2.E-02 3.E-02 Time (5 ms/div) FIGURE 2-33: The MCP6141/2/3/4 family shows no phase reversal (for information only– the Maximum Absolute Input Voltage is still V - 0.3V and V + 0.3V). SS DD  2002 Microchip Technology Inc. 21668A-page 9

MCP6141/2/3/4 3.0 APPLICATIONS INFORMATION 3.3 Rail-to-Rail Output The MCP6141/2/3/4 family of operational amplifiers The MCP6141/2/3/4 family Maximum Output Voltage are fabricated on Microchip’s state-of-the-art CMOS Swing defines the maximum swing possible under a process. They are stable for noise gain of 10V/V or particular output load. According to the specification higher. Microchip also produces a unity gain stable table, the output can reach up to 10mV of either supply product, the MCP6041/2/3/4 family, which has similar rail with a 50kΩ load. specifications. The MCP6041/2/3/4 family has a band- 3.4 Input Voltage and Phase Reversal width of 1.4kHz at a noise gain of 10V/V, while the MCP6141/2/3/4 family has a bandwidth of 10kHz at a The MCP6141/2/3/4 op amp family uses CMOS tran- noise gain of 10V/V. These devices are suitable for a sistors at the input. It is designed to prevent phase wide range of applications requiring very low power reversal when the input pins exceed the supply volt- consumption. With these op amps, the power supply ages. Figure2-33 shows an input voltage exceeding pin needs to be bypassed with a 0.1µF capacitor. both supplies without output phase reversal. 3.1 Rail-to-Rail Input The maximum operating V that can be applied to the CM inputs is V -0.3V and V + 0.3V. Voltage on the SS DD The input stage of these devices uses two differential input that exceeds this absolute maximum rating can input stages in parallel; one operates at low VCM (com- cause excessive current to flow in or out of the input mon mode input voltage) and the other at high VCM. pins. Current beyond ±2mA can cause possible reli- With this topology, the MCP6141/2/3/4 family operates ability problems. Applications that exceed this rating with V up to 300mV past either supply rail. The Input CM must be externally limited with an input resistor, as Offset Voltage is measured at both V =V -0.3V CM SS shown in Figure3-1. and V +0.3V to ensure proper operation. DD 3.2 Output Loads and Battery Life The MCP6141/2/3/4 op amp family has low quiescent current, which supports battery-powered applications. RIN MCP614X VOUT There is minimal quiescent current glitch when chip V IN select (CS) is raised or lowered. This prevents exces- sive current draw and reduced battery life when the part is turned off or on. (Maximum expected V )–V R ≥-------------------------------------------------------I--N---------------D----D--- Heavy resistive loads at the output can cause exces- IN 2 mA sive battery drain. Driving a DC voltage of 2.5V across V –(Minimum expected V ) a 100kΩ load resistor will cause the supply current to R ≥----S---S--------------------------------------------------------------I--N----- IN 2 mA increase by 25µA, depleting the battery 43 times as fast as I (0.6µA typ) alone. Q FIGURE 3-1: An input resistor, R , IN High frequency signals (fast edge rate) across capaci- should be used to limit excessive input current if tive loads will also significantly increase supply current. the inputs exceed the absolute maximum For instance, a 0.1µF capacitor at the output presents specification. an AC impedance of 15.9kΩ (1/2πfC) to a 100Hz sinewave. It can be shown that the average power 3.5 Stability drawn from the battery by a 5.0V sinewave p-p (1.77Vrms) under these conditions is: The MCP6141/2/3/4 op amp family is designed to give high bandwidth and faster slew rate for circuits with EQUATION high noise (Gn) or signal gain. The related unity-gain stable MCP6041/2/3/4 op amp family has lower AC PSUPPLY = (VDD–VSS)(IQ+VL(p–p)fCL) performance, but it is preferable for low noise gain = (5V)(0.6µA+5.0V ⋅100Hz⋅0.1µF) applications. p–p = 3.0µW+50µW Noise gain is defined to be the gain from a voltage source at the non-inverting input to the output when all This will drain the battery 18 times as fast as I alone. other voltage sources are zeroed (shorted out). Noise Q gain is independent of signal gain and depends only on components in the feedback loop. 21668A-page 10 2002 Microchip Technology Inc.

MCP6141/2/3/4 Note that the integrator circuit in Figure3-3 becomes RG RF unity gain at high frequencies because of the capaci- tor. Therefore, this circuit is unstable for the MCP6141/2/3/4. MCP614X V 3.6 Capacitive Load and Stability OUT V IN Driving capacitive loads can cause stability problems with voltage feedback op amps. Figure2-21 shows how Non-inverting noise gain: 1 + RF/RG ≥ +10V/V increasing the load capacitance will decrease the phase margin. While a phase margin above 60° is ideal, 45° is VIN RG RF on the verge of instability. As can be seen, up to C =150pF can be placed on the MCP6141/2/3/4 op L amp outputs without any problems, while 250pF cre- ates a 45° phase margin. MCP614X VOUT When the op amp is required to drive large capacitive loads (C >150pF), a small series resistor (R in L ISO Figure3-4) at the output of the amplifier improves the phase margin. This resistor makes the output load Inverting noise gain: 1 + RF/RG ≥ +10V/V resistive at higher frequencies, which improves the phase margin. The bandwidth reduction caused by the FIGURE 3-2: Noise gain for inverting and capacitive load, however, is not changed. To select non-inverting amplifier configuration. R , start with 1kΩ, then use the MCP6141 SPICE ISO Figure3-2 shows non-inverting and inverting amplifier macro model and bench testing to adjust RISO until circuits. In order for the amplifiers to be stable, the there is a minimum frequency response peaking. noise gain should meet the specified requirement: EQUATION R R 2 1 R G = 1+-----F--≥10V/V n R G R ISO MCP614X VOUT Note that an inverting signal gain of G = -9 V/V corre- V sponds to a noise gain G = +10V/V. IN C n L Figure3-3 shows a unity gain buffer and integrator that are unstable when used with the MCP6141/2/3/4 fam- ily. However, they are suitable for the MCP6041/2/3/4 FIGURE 3-4: Amplifier circuit for heavy family. capacitive loads. 3.7 The MCP6143 Chip Select (CS) Option The MCP6143 is a single amplifier with a chip select MCP604X V OUT (CS) option. When CS is pulled high, the supply current V IN drops to 20pA (typ.) and goes through the CS pin to Unity gain buffer: V . When this happens, the amplifier is put into a high Unstable for MCP614X SS impedance state. By pulling CS low, the amplifier is R C enabled. If the CS pin is left floating, the amplifier will V not operate properly. Figure3-5 shows the output IN voltage and supply current response to a CS pulse. MCP604X VOUT Integrator: Unstable for MCP614X FIGURE 3-3: Typical Circuits that are not suitable for the MCP6141/2/3/4 family.  2002 Microchip Technology Inc. 21668A-page 11

MCP6141/2/3/4 Circuit schematics for different guard ring implementa- CS VIL VIH tions are shown in Figure3-7. Figure3-7A biases the guard ring to the input common mode voltage, which is t most effective for non-inverting gains. Figure3-7B t OFF ON biases the guard ring to a reference voltage (V , REF which can be ground), which is useful for inverting VOUT Hi-Z Hi-Z gains and precision photo sensing circuits. 0.6µA, typ Figure 3-7A 5pA, typ 5pA, typ I VDD V DD 0.6µA, typ I 20pA, typ 20pA, typ MCP614X VSS V REF 5pA, typ 5pA, typ I CS Figure 3-7B FIGURE 3-5: Timing Diagram for the CS function on the MCP6143 op amp. V DD 3.8 Layout Considerations Good PC board layout techniques will help you achieve MCP614X the performance shown in the specifications and typical V REF performance curves. It will also assist in minimizing Electro-Magnetic Compatibility (EMC) issues. FIGURE 3-7: Two possible guard ring 3.8.1 SURFACE LEAKAGE connection strategies to reduce surface leakage In applications where low input bias current is critical, effects. PC board surface leakage effects and signal coupling from trace to trace need to be considered. 3.8.2 COMPONENT PLACEMENT Surface leakage is caused by a difference in voltage In order to help prevent crosstalk: between traces, combined with high humidity, dust or • Separate digital components from analog compo- other contamination on the board. Under low humidity nents, and low speed devices from high speed conditions, a typical resistance between nearby traces is 1012Ω. A 5V difference would cause 5pA of current devices. to flow, which is greater than the input current of the • Keep sensitive traces short and straight. Separate MCP6141/2/3/4 family at 25°C (1pA, typ). them from interfering components and traces. This is especially important for high frequency The simplest technique to reduce surface leakage is (low rise time) signals. using a guard ring around sensitive pins (or traces). • Use a 0.1µF supply bypass capacitor within 0.1” The guard ring is biased at the same voltage as the (2.5mm) of the V pin. It must connect directly sensitive pin or trace. Figure3-6 shows an example of DD to the ground plane. a typical layout. IN- IN+ V SS Guard Ring FIGURE 3-6: Example of Guard Ring layout. 21668A-page 12 2002 Microchip Technology Inc.

MCP6141/2/3/4 3.8.3 SIGNAL COUPLING 3.9 Typical Applications The input pins of the MCP6141/2/3/4 family of op amps 3.9.1 BATTERY CURRENT SENSING are high impedance, which allows noise injection. This noise can be capacitively or magnetically coupled. In The MCP6141/2/3/4 op amps’ Common Mode Input either case, using a ground plane helps reduce noise Range, which goes 300mV beyond both supply rails, injection. supports their use in high side and low side battery current sensing applications. The very low quiescent When noise is coupled capacitively, the ground plane current (0.6µA, typ.) help prolong battery life, while the provides shunt capacitance to ground for high fre- rail-to-rail output allows you to detect low currents. quency signals (Figure3-8 shows the equivalent cir- cuit). The coupled current, I , produces a lower voltage Figure3-9 shows a high side battery current sensor cir- M (V ) on the victim trace when the trace to ground cuit. The feedback and input resistors are sized to min- TRACE2 plane capacitance (C ) is large and the terminating imize power losses. The battery current (I ) through SH2 DD resistor (R ) is small. Increasing the distance between the 1kΩ resistor causes its top terminal to be more T2 traces and using wider traces also helps. negative than the bottom terminal. This keeps the com- mon mode input voltage of the op amp ≤ V , which is DD within its allowed range. The output of the op amp can CM IM VTRACE2 reach V - 0.1mV (see Figure2-26), which is a DD V TRACE1 smaller error than the offset voltage. CSH1 CSH2 RT2 V DD V DD FIGURE 3-8: Equivalent circuit for capacitive coupling between traces on a PC 1kΩ IDD MCP614X board (with ground plane). +1.4V V When noise is coupled magnetically, the ground plane to 100kΩ SS reduces the mutual inductance between traces. This 5.5V occurs because the ground return current at high fre- 1MΩ quencies will follow a path directly beneath the signal trace. Increasing the separation between traces makes a significant difference. Changing the direction of one FIGURE 3-9: High Side Battery Current of the traces can also reduce magnetic coupling. Sensor. If these techniques are not enough, it may help to place 3.9.2 SUMMING AMPLIFIER guard traces next to the victim trace. They should be on both sides of the victim trace and be as close as possi- The rail-to-rail input and output, the 600 nA (typ.) qui- ble. Connect the guard traces to ground plane at both escent current and the wide bandwidth make the ends and in the middle for long traces. MCP6141/2/3/4 family of operational amplifiers fit well in a summing amplifier circuit, as shown in Figure3-10. R 1 V 1 I R 1 2 V 2 R3 I2 RF V 3 I3 IF - V VREF + OUT MCP614X FIGURE 3-10: Summing amplifier circuit.  2002 Microchip Technology Inc. 21668A-page 13

MCP6141/2/3/4 In this configuration, the amplifier outputs the sum of the three input voltages. The ratio of the sum and the output voltage is defined using the feedback and input resistors. V is used to offset the output voltage. This REF family of amplifiers is stable for noise gain (G ) of 10V/ n V or higher. The G and the signal gain of the summing n amplifier is calculated as shown below: EQUATION Noise Gain:  1 1 1 Gn = 1+RFR------+R------+R------ ≥10V/V 1 2 3 Signal Gain: –R V = -------F--×V 01 R 1 1 –R V = -------F--×V 02 R 2 2 –R V = -------F--×V 03 R 3 3 V04 = 1+R-R---F--+R-R---F--+R-R---F-- ×VREF 1 2 3 V = V +V +V +V OUT 01 02 03 04 V –V V –V V –V REF 1 REF 2 REF 3 VOUT = RF ----------R-------------+----------R-------------+----------R------------- +VREF 1 2 3 At a noise gain of 10V/V, the amplifier bandwidth is approximately 10kHz. The bandwidth to quiescent cur- rent ratio of MCP6141/2/3/4 makes this device an appropriate choice for battery-powered applications. 21668A-page 14 2002 Microchip Technology Inc.

MCP6141/2/3/4 4.0 SPICE MACRO MODEL The Spice macro model for the MCP6141, MCP6142, MCP6143 and MCP6144 simulates the typical ampli- fier performance of offset voltage, DC power supply rejection, input capacitance, DC common mode rejec- tion, open loop gain over frequency, phase margin, out- put swing, DC power supply current, power supply current change with supply voltage, input common mode range, output voltage range vs. load and input voltage noise. The characteristics of the MCP6141, MCP6142, MCP6143 and MCP6144 amplifiers are similar in terms of performance and behavior. This single op amp macro model supports all four devices, with the excep- tion of the chip select function of the MCP6143, which is not modeled. The listing for this macro model is shown on the next page. The most recent revision of the model can be downloaded from Microchip’s web site at www.microchip.com.  2002 Microchip Technology Inc. 21668A-page 15

MCP6141/2/3/4 Software License Agreement The software supplied herewith by Microchip Technology Incorporated (the “Company”) is intended and supplied to you, the Com- pany’s customer, for use solely and exclusively on Microchip products. The software is owned by the Company and/or its supplier, and is protected under applicable copyright laws. All rights are reserved. Any use in violation of the foregoing restrictions may subject the user to criminal sanctions under applicable laws, as well as to civil liability for the breach of the terms and conditions of this license. THIS SOFTWARE IS PROVIDED IN AN “AS IS” CONDITION. NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATU- TORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICU- LAR PURPOSE APPLY TO THIS SOFTWARE. THE COMPANY SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. .SUBCKT MCP6141 1 2 3 4 5 * | | | | | * | | | | Output * | | | Negative Supply * | | Positive Supply * | Inverting Input * Non-inverting Input * * Macromodel for the MCP6141/2/3/4 op amp family: * MCP6141 (single) * MCP6142 (dual) * MCP6143 (single w/ CS; chip select is not modeled) * MCP6144 (quad) * * Revision History: * REV A: 06-Sep-02, KEB (created model) * * Recommendations: * Use PSPICE (or SPICE 2G6; other simulators may require translation) * For a quick, effective design, use a combination of: data sheet * specs, bench testing, and simulations with this macromodel * For high impedance circuits, set GMIN=100F in the .OPTIONS * statement * * Supported: * Typical performance at room temperature (25 degrees C) * DC, AC, Transient, and Noise analyses. * Most specs, including: offsets, DC PSRR, DC CMRR, input impedance, * open loop gain, voltage ranges, supply current, ... , etc. * * Not Supported: * Chip select (MCP6143) * Variation in specs vs. Power Supply Voltage * Distortion (detailed non-linear behavior) * Temperature analysis * Process variation * Behavior outside normal operating region * * Input Stage V10 3 10 -300M R10 10 11 258K R11 10 12 258K C11 11 12 3.53P C12 1 0 6.00P E12 1 14 POLY(4) 20 0 21 0 26 0 27 0 1.00M 117 117 1 1 I12 14 0 1.50P M12 11 14 15 15 NMI L=2.00U W=5.00U C13 14 2 6.00P M14 12 2 15 15 NMI L=2.00U W=5.00U I14 2 0 500E-15 C14 2 0 6.00P  2002 Microchip Technology Inc. 21668A-page 16

MCP6141/2/3/4 I15 15 4 300N V16 16 4 200M D16 16 15 DL V13 3 13 50.0M D13 14 13 DL * * Noise, PSRR, and CMRR I20 21 20 423U D20 20 0 DN1 D21 0 21 DN1 G26 0 26 POLY(1) 3 4 308U -56.0U R26 26 0 1 G27 0 27 POLY(2) 1 3 2 4 -979U 178U 178U R27 27 0 1 * * Open Loop Gain, Slew Rate G30 0 30 POLY(1) 12 11 0 1.00K R30 30 0 1 E31 31 0 POLY(1) 3 4 29.3 1.05 D31 30 31 DL E32 0 32 POLY(1) 3 4 57.0 2.04 D32 32 30 DL G33 0 33 POLY(1) 30 0 0 562 R33 33 0 1 C33 33 0 838M G34 0 34 POLY(1) 33 0 0 1.00 R34 34 0 1.00 C34 34 0 8.53U G35 0 35 POLY(2) 34 0 33 34 0 1.00 1.22 R35 35 0 1.00 * * Output Stage G50 0 50 POLY(1) 57 5 0 1.00 D51 50 51 DL R51 51 0 1K D52 52 50 DL R52 52 0 1K G53 3 0 POLY(1) 51 0 300N 1M G54 0 4 POLY(1) 52 0 300N -1M E55 55 0 POLY(2) 3 0 51 0 -10M 1 -100M D55 57 55 DLS E56 56 0 POLY(2) 4 0 52 0 10M 1 -100M D56 56 57 DLS G57 0 57 POLY(3) 3 0 4 0 35 0 0 17.8U 17.8U 35.5U R57 57 0 28.2K R58 57 5 1.00 C58 5 0 2.00P * * Models .MODEL NMI NMOS .MODEL DL D N=1 IS=1F .MODEL DLS D N=10M IS=1F .MODEL DN1 D IS=1F KF=1.17E-18 AF=1 * .ENDS MCP6141  2002 Microchip Technology Inc. 21668A-page 17

MCP6141/2/3/4 5.0 PACKAGING INFORMATION 5.1 Package Marking Information 8-Lead PDIP (300 mil) Example: XXXXXXXX MCP6141 XXXXXNNN I/P058 YYWW 0223 8-Lead SOIC (150 mil) Example: XXXXXXXX MCP6142 XXXXYYWW I/SN0223 NNN 058 8-Lead MSOP Example: XXXXXX 6143I YWWNNN 223058 Legend: XX...X Customer specific information* YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard marking consists of Microchip part number, year code, week code, traceability code (facility code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. 21668A-page 18 2002 Microchip Technology Inc.

MCP6141/2/3/4 5.1 Package Marking Information (Continued) 14-Lead PDIP (300 mil) (MCP6144) Example: XXXXXXXXXXXXXX MCP6144-I/P XXXXXXXXXXXXXX YYWWNNN 0223058 14-Lead SOIC (150 mil) (MCP6144) Example: XXXXXXXXXX MCP6144ISL XXXXXXXXXX YYWWNNN 0223058 14-Lead TSSOP (MCP6144) Example: XXXXXX 6144ST YYWW 0223 NNN 058  2002 Microchip Technology Inc. 21668A-page 19

MCP6141/2/3/4 8-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n 1 α E A A2 L c A1 β B1 p eB B Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch p .100 2.54 Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32 Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26 Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60 Overall Length D .360 .373 .385 9.14 9.46 9.78 Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43 Lead Thickness c .008 .012 .015 0.20 0.29 0.38 Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78 Lower Lead Width B .014 .018 .022 0.36 0.46 0.56 Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92 Mold Draft Angle Top α 5 10 15 5 10 15 Mold Draft Angle Bottom β 5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018 21668A-page 20 2002 Microchip Technology Inc.

MCP6141/2/3/4 8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 h α 45° c A A2 φ β L A1 Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch p .050 1.27 Overall Height A .053 .061 .069 1.35 1.55 1.75 Molded Package Thickness A2 .052 .056 .061 1.32 1.42 1.55 Standoff § A1 .004 .007 .010 0.10 0.18 0.25 Overall Width E .228 .237 .244 5.79 6.02 6.20 Molded Package Width E1 .146 .154 .157 3.71 3.91 3.99 Overall Length D .189 .193 .197 4.80 4.90 5.00 Chamfer Distance h .010 .015 .020 0.25 0.38 0.51 Foot Length L .019 .025 .030 0.48 0.62 0.76 Foot Angle φ 0 4 8 0 4 8 Lead Thickness c .008 .009 .010 0.20 0.23 0.25 Lead Width B .013 .017 .020 0.33 0.42 0.51 Mold Draft Angle Top α 0 12 15 0 12 15 Mold Draft Angle Bottom β 0 12 15 0 12 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057  2002 Microchip Technology Inc. 21668A-page 21

MCP6141/2/3/4 8-Lead Plastic Micro Small Outline Package (MS) (MSOP) E p E1 D 2 B n 1 α A A2 c φ A1 (F) L β Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch p .026 0.65 Overall Height A .044 1.18 Molded Package Thickness A2 .030 .034 .038 0.76 0.86 0.97 Standoff § A1 .002 .006 0.05 0.15 Overall Width E .184 .193 .200 4.67 4.90 .5.08 Molded Package Width E1 .114 .118 .122 2.90 3.00 3.10 Overall Length D .114 .118 .122 2.90 3.00 3.10 Foot Length L .016 .022 .028 0.40 0.55 0.70 Footprint (Reference) F .035 .037 .039 0.90 0.95 1.00 Foot Angle φ 0 6 0 6 Lead Thickness c .004 .006 .008 0.10 0.15 0.20 Lead Width B .010 .012 .016 0.25 0.30 0.40 Mold Draft Angle Top α 7 7 Mold Draft Angle Bottom β 7 7 *Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. Drawing No. C04-111 21668A-page 22 2002 Microchip Technology Inc.

MCP6141/2/3/4 14-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n 1 α E A A2 c L A1 β B1 eB B p Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 14 14 Pitch p .100 2.54 Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32 Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26 Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60 Overall Length D .740 .750 .760 18.80 19.05 19.30 Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43 Lead Thickness c .008 .012 .015 0.20 0.29 0.38 Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78 Lower Lead Width B .014 .018 .022 0.36 0.46 0.56 Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92 Mold Draft Angle Top α 5 10 15 5 10 15 Mold Draft Angle Bottom β 5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-005  2002 Microchip Technology Inc. 21668A-page 23

MCP6141/2/3/4 14-Lead Plastic Small Outline (SL) – Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 α h 45° c A A2 φ A1 L β Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 14 14 Pitch p .050 1.27 Overall Height A .053 .061 .069 1.35 1.55 1.75 Molded Package Thickness A2 .052 .056 .061 1.32 1.42 1.55 Standoff § A1 .004 .007 .010 0.10 0.18 0.25 Overall Width E .228 .236 .244 5.79 5.99 6.20 Molded Package Width E1 .150 .154 .157 3.81 3.90 3.99 Overall Length D .337 .342 .347 8.56 8.69 8.81 Chamfer Distance h .010 .015 .020 0.25 0.38 0.51 Foot Length L .016 .033 .050 0.41 0.84 1.27 Foot Angle φ 0 4 8 0 4 8 Lead Thickness c .008 .009 .010 0.20 0.23 0.25 Lead Width B .014 .017 .020 0.36 0.42 0.51 Mold Draft Angle Top α 0 12 15 0 12 15 Mold Draft Angle Bottom β 0 12 15 0 12 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-065 21668A-page 24 2002 Microchip Technology Inc.

MCP6141/2/3/4 14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP) E E1 p D 2 n 1 B α A c φ β A1 A2 L Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 14 14 Pitch p .026 0.65 Overall Height A .043 1.10 Molded Package Thickness A2 .033 .035 .037 0.85 0.90 0.95 Standoff § A1 .002 .004 .006 0.05 0.10 0.15 Overall Width E .246 .251 .256 6.25 6.38 6.50 Molded Package Width E1 .169 .173 .177 4.30 4.40 4.50 Molded Package Length D .193 .197 .201 4.90 5.00 5.10 Foot Length L .020 .024 .028 0.50 0.60 0.70 Foot Angle φ 0 4 8 0 4 8 Lead Thickness c .004 .006 .008 0.09 0.15 0.20 Lead Width B1 .007 .010 .012 0.19 0.25 0.30 Mold Draft Angle Top α 0 5 10 0 5 10 Mold Draft Angle Bottom β 0 5 10 0 5 10 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005” (0.127mm) per side. JEDEC Equivalent: MO-153 Drawing No. C04-087  2002 Microchip Technology Inc. 21668A-page 25

MCP6141/2/3/4 NOTES: 21668A-page 26 2002 Microchip Technology Inc.

MCP6141/2/3/4 ON-LINE SUPPORT SYSTEMS INFORMATION AND UPGRADE HOT LINE Microchip provides on-line support on the Microchip World Wide Web site. The Systems Information and Upgrade Line provides The web site is used by Microchip as a means to make system users a listing of the latest versions of all of files and information easily available to customers. To Microchip's development systems software products. view the site, the user must have access to the Internet Plus, this line provides information on how customers and a web browser, such as Netscape® or Microsoft® can receive the most current upgrade kits.The Hot Line Internet Explorer. Files are also available for FTP Numbers are: download from our FTP site. 1-800-755-2345 for U.S. and most of Canada, and Connecting to the Microchip Internet Web Site 1-480-792-7302 for the rest of the world. The Microchip web site is available at the following URL: 092002 www.microchip.com The file transfer site is available by using an FTP ser- vice to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A vari- ety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: • Latest Microchip Press Releases • Technical Support Section with Frequently Asked Questions • Design Tips • Device Errata • Job Postings • Microchip Consultant Program Member Listing • Links to other useful web sites related to Microchip Products • Conferences for products, Development Systems, technical information and more • Listing of seminars and events  2002 Microchip Technology Inc. DS21668A-page 27

MCP6141/2/3/4 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: MCP6141/2/3/4 Literature Number: DS21668A Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS21668A-page 28  2002 Microchip Technology Inc.

MCP6141/2/3/4 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX Examples: Device Temperature Package a) MCP6141-I/P: Industrial temperature, Range PDIP package. b) MCP6141T-I/SN: Tape and Reel, Indus- trial temperature, SOIC package. Device: MCP6141: CMOS Single Op Amp MCP6141T: CMOS Single Op Amp a) MCP6142-I/SN: Industrial temperature, (Tape and Reel for SOIC, MSOP) SOIC package. MCP6142: CMOS Dual Op Amp MCP6142T: CMOS Dual Op Amp b) MCP6142-I/MS: Industrial temperature, (Tape and Reel for SOIC and TSSOP) MSOP package. MCP6143: CMOS Single Op Amp w/CS Function MCP6143T: CMOS Single Op Amp w/CS Function a) MCP6143-I/MS: Industrial temperature, (Tape and Reel for SOIC and MSOP) MSOP package. MCP6144: CMOS Quad Op Amp MCP6144T: CMOS Quad Op Amp b) MCP6143-I/P: Industrial temperature, (Tape and Reel for SOIC and TSSOP) PDIP package. a) MCP6144-I/SL: Industrial temperature, Temperature Range: I = -40°C to +85°C SIOC package. b) MCP6144T-I/ST: Tape and Reel, Indus- Package: MS = Plastic MSOP, 8-lead trial temperature, TSSOP package. P = Plastic DIP (300 mil Body), 8-lead, 14-lead SN = Plastic SOIC (150 mil Body), 8-lead SL = Plastic SOIC (150 mil Body), 14-lead ST = Plastic TSSOP (4.4mm Body), 14-lead Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office 2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 3. The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.  2002 Microchip Technology Inc. DS21668A-page 29

MCP6141/2/3/4 NOTES: DS21668A-page 30  2002 Microchip Technology Inc.

Information contained in this publication regarding device Trademarks applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to The Microchip name and logo, the Microchip logo, KEELOQ, ensure that your application meets with your specifications. MPLAB, PIC, PICmicro, PICSTART and PRO MATE are No representation or warranty is given and no liability is registered trademarks of Microchip Technology Incorporated assumed by Microchip Technology Incorporated with respect in the U.S.A. and other countries. to the accuracy or use of such information, or infringement of FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL patents or other intellectual property rights arising from such and The Embedded Control Solutions Company are use or otherwise. Use of Microchip’s products as critical com- registered trademarks of Microchip Technology Incorporated ponents in life support systems is not authorized except with in the U.S.A. express written approval by Microchip. No licenses are con- veyed, implicitly or otherwise, under any intellectual property dsPIC, dsPICDEM.net, ECONOMONITOR, FanSense, rights. FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified.  2002 Microchip Technology Inc. DS21668A - page 31

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: MCP6143-E/P MCP6143-I/MS MCP6143-I/SN MCP6144-E/P MCP6143-E/SN MCP6144-I/SL MCP6144-I/ST MCP6141-I/SN MCP6141-I/MS MCP6141T-I/SN MCP6142T-I/MS MCP6144T-I/SL MCP6144T-I/ST MCP6143T- I/SN MCP6141T-I/MS MCP6142T-I/SN MCP6143T-I/MS MCP6142-I/P MCP6142-E/MS MCP6142-E/SN MCP6144- I/P MCP6141-I/P MCP6142-I/SN MCP6143-I/P MCP6144-E/SL MCP6144-E/ST MCP6141-E/MS MCP6141-E/SN MCP6142-E/P MCP6141-E/P MCP6143-E/MS MCP6142-I/MS MCP6142T-E/SN MCP6144T-E/SL MCP6144T-E/ST MCP6141T-E/MS MCP6143T-E/SN MCP6143T-E/MS MCP6141T-E/SN MCP6142T-E/MS MCP6142T-E/MSVAO MCP6144T-E/STVAO MCP6142-E/MSVAO