MCP6071/2/4 110 µA, High Precision Op Amps Features Description • Low Offset Voltage: ±150µV (maximum) The Microchip Technology Inc. MCP6071/2/4 family of • Low Quiescent Current: 110µA (typical) operational amplifiers (op amps) has low input offset voltage (±150µV, maximum) and rail-to-rail input and • Rail-to-Rail Input and Output output operation. This family is unity gain stable and • Wide Supply Voltage Range: 1.8V to 6.0V has a gain bandwidth product of 1.2MHz (typical). • Gain Bandwidth Product: 1.2MHz (typical) These devices operate with a single supply voltage as • Unity Gain Stable low as 1.8V, while drawing low quiescent current per • Extended Temperature Range: -40°C to +125°C amplifier (110µA, typical). These features make the • No Phase Reversal family of op amps well suited for single-supply, high precision, battery-powered applicaitons. Applications The MCP6071/2/4 family is offered in single (MCP6071), dual (MCP6072), and quad (MCP6074) • Automotive configurations. • Portable Instrumentation The MCP6071/2/4 is designed with Microchip’s • Sensor Conditioning advanced CMOS process. All devices are available in • Battery Powered Systems the extended temperature range, with a power supply • Medical Instrumentation range of 1.8V to 6.0V. • Test Equipment Package Types • Analog Filters MCP6071 MCP6072 Design Aids SOIC SOIC • SPICE Macro Models NC 1 8 NC VOUTA 1 8 VDD • FilterLab® Software VIN– 2 7 VDD VINA– 2 7 VOUTB • Mindi™ Circuit Designer & Simulator VIN+ 3 6 VOUT VINA+ 3 6 VINB– • MAPS (Microchip Advanced Part Selector) VSS 4 5 NC VSS 4 5 VINB+ • Analog Demonstration and Evaluation Boards MCP6071 MCP6072 • Application Notes 2x3 TDFN 2x3 TDFN Typical Application NC 1 8 NC VOUTA 1 8 VDD VIN– 2 EP 7 VDD VINA– 2 EP 7 VOUTB VIN+ 3 9 6 VOUT VINA+ 3 9 6 VINB– R L V 4 5 NC V 4 5 V + SS SS INB V ZIN OUT MCP6074 MCP6071 SOIC, TSSOP VOUTA 1 14 VOUTD C VINA– 2 13 VIND– Z = R +jωL R VINA+ 3 12 VIND+ IN L L = R RC Gyrator VDD 4 11 VSS L VINB+ 5 10 VINC+ VINB– 6 9 VINC– VOUTB 7 8 VOUTC * Includes Exposed Thermal Pad (EP); see Table3-1. © 2009 Microchip Technology Inc. DS22142A-page 1

MCP6071/2/4 NOTES: DS22142A-page 2 © 2009 Microchip Technology Inc.

MCP6071/2/4 1.0 ELECTRICAL CHARACTERISTICS 1.1 Absolute Maximum Ratings † V – V ........................................................................7.0V † Notice: Stresses above those listed under “Absolute DD SS Current at Input Pins.....................................................±2mA Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional Analog Inputs (VIN+, VIN-)††..........VSS –1.0V to VDD +1.0V operation of the device at those or any other conditions All Other Inputs and Outputs .........V –0.3V to V +0.3V SS DD above those indicated in the operational listings of this Difference Input Voltage ......................................|VDD – VSS| specification is not implied. Exposure to maximum rat- Output Short-Circuit Current .................................continuous ing conditions for extended periods may affect device Current at Output and Supply Pins ............................±30mA reliability. Storage Temperature....................................-65°C to +150°C †† See 4.1.2 “Input Voltage And Current Limits” Maximum Junction Temperature (T )..........................+150°C J ESD protection on all pins (HBM; MM)................≥ 4kV; 400V 1.2 Specifications TABLE 1-1: DC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, V = +1.8V to +6.0V, V = GND, T = +25°C, V = V /2, DD SS A CM DD V ≈V /2, V = V /2 and R = 10kΩ to V . (Refer to Figure1-1). OUT DD L DD L L Parameters Sym Min Typ Max Units Conditions Input Offset Input Offset Voltage V -150 — +150 µV V = 3.0V, OS DD V = V /3 CM DD Input Offset Drift with Temperature ΔV /ΔT — ±1.5 — µV/°C T = -40°C to +85°C, OS A A V = 3.0V, V = V /3 DD CM DD ΔV /ΔT — ±4.0 — µV/°C T = +85°C to +125°C, OS A A V = 3.0V, V = V /3 DD CM DD Power Supply Rejection Ratio PSRR 70 87 — dB V = V CM SS Input Bias Current and Impedance Input Bias Current I — ±1.0 100 pA B I — 60 — pA T = +85°C B A I — 1100 5000 pA T = +125°C B A Input Offset Current I — ±1.0 — pA OS Common Mode Input Impedance Z — 1013||6 — Ω||pF CM Differential Input Impedance Z — 1013||6 — Ω||pF DIFF Common Mode Common Mode Input Voltage Range V V −0.15 — V +0.15 V V = 1.8V (Note 1) CMR SS DD DD V V −0.3 — V +0.3 V V = 6.0V (Note 1) CMR SS DD DD Common Mode Rejection Ratio CMRR 72 89 — dB V = -0.15V to 1.95V, CM V = 1.8V DD 74 91 — dB V = -0.3V to 6.3V, CM V = 6.0V DD 72 87 — dB V = 3.0V to 6.3V, CM V = 6.0V DD 74 89 — dB V = -0.3V to 3.0V, CM V = 6.0V DD Note 1: Figure2-13 shows how V changed across temperature. CMR © 2009 Microchip Technology Inc. DS22142A-page 3

MCP6071/2/4 TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise indicated, V = +1.8V to +6.0V, V = GND, T = +25°C, V = V /2, DD SS A CM DD V ≈V /2, V = V /2 and R = 10kΩ to V . (Refer to Figure1-1). OUT DD L DD L L Parameters Sym Min Typ Max Units Conditions Open-Loop Gain DC Open-Loop Gain A 95 115 — dB 0.2V < V <(V -0.2V) OL OUT DD (Large Signal) V = V CM SS Output Maximum Output Voltage Swing V V V +15 — V –15 mV G = +2V/V, OL, OH SS DD 0.5V input overdrive Output Short-Circuit Current I — ±7 — mA V = 1.8V SC DD — ±28 — mA V = 6.0V DD Power Supply Supply Voltage V 1.8 — 6.0 V DD Quiescent Current per Amplifier I 50 110 170 µA I = 0, V = 6.0V Q O DD V = 0.9V CM DD Note 1: Figure2-13 shows how V changed across temperature. CMR TABLE 1-2: AC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, T = +25°C, V = +1.8 to +6.0V, V = GND, V = V /2, A DD SS CM DD V ≈V /2, V = V /2, R = 10kΩ to V and C = 60pF. (Refer to Figure1-1). OUT DD L DD L L L Parameters Sym Min Typ Max Units Conditions AC Response Gain Bandwidth Product GBWP — 1.2 — MHz Phase Margin PM — 57 — ° G = +1V/V Slew Rate SR — 0.5 — V/µs Noise Input Noise Voltage E — 4.3 — µVp-p f = 0.1Hz to 10Hz ni Input Noise Voltage Density e — 19 — nV/√Hz f = 10kHz ni Input Noise Current Density i — 0.6 — fA/√Hz f = 1kHz ni TABLE 1-3: TEMPERATURE SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, V = +1.8V to +6.0V and V = GND. DD SS Parameters Sym Min Typ Max Units Conditions Temperature Ranges Operating Temperature Range T -40 — +125 °C Note1 A Storage Temperature Range T -65 — +150 °C A Thermal Package Resistances Thermal Resistance, 8L-2x3 TDFN θ — 41 — °C/W JA Thermal Resistance, 8L-SOIC θ — 149.5 — °C/W JA Thermal Resistance, 14L-SOIC θ — 95.3 — °C/W JA Thermal Resistance, 14L-TSSOP θ — 100 — °C/W JA Note1: The internal junction temperature (T ) must not exceed the absolute maximum specification of +150°C. J DS22142A-page 4 © 2009 Microchip Technology Inc.

MCP6071/2/4 1.3 Test Circuits The circuit used for most DC and AC tests is shown in Figure1-1. This circuit can independently set VCM and CF V ; see Equation1-1. Note that V is not the OUT CM 6.8pF circuit’s common mode voltage ((V +V )/2), and that P M V includes V plus the effects (on the input offset OST OS R R error, V ) of temperature, CMRR, PSRR and A . G F OST OL 100kΩ 100kΩ V V /2 EQUATION 1-1: P DD V DD V G = R ⁄R IN+ DM F G C C V = (V +V ⁄2)⁄2 B1 B2 CM P DD MCP607X 100nF 1µF V = V –V OST IN– IN+ V = (V ⁄2)+(V –V )+V (1+G ) OUT DD P M OST DM VIN– Where: V V M OUT GDM = Differential Mode Gain (V/V) RG RF RL CL VCM = Op Amp’s Common Mode (V) 100kΩ 100kΩ 10kΩ 60pF Input Voltage VOST = Op Amp’s Total Input Offset (mV) CF Voltage 6.8pF VL FIGURE 1-1: AC and DC Test Circuit for Most Specifications. © 2009 Microchip Technology Inc. DS22142A-page 5

MCP6071/2/4 NOTES: DS22142A-page 6 © 2009 Microchip Technology Inc.

MCP6071/2/4 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, T = +25°C, V = +1.8V to +6.0V, V = GND, V = V /2, V ≈V /2, A DD SS CM DD OUT DD V = V /2, R = 10kΩ to V and C = 60pF. L DD L L L 14% 1000 s 1244 Samples Occurence11028%%% VVDCDM == 3V.D0DV/3 oltage (µV) 246800000000 VDD = 6.0V Representative Part ge of 6% set V -2000 Percenta 24%% Input Off ---864000000 TTTTAAAA ==== -+++42810552°°°5CCC°C 0% -1000 -150 -120 -90In-60put O-30ffset0 Volt30age (60µV) 90 120 150 -0.5 0.0 0.5Co1.0mm1.5on2.0 Mo2.5de 3.0Inp3.5ut V4.0olta4.5ge5.0 (V)5.5 6.0 6.5 FIGURE 2-1: Input Offset Voltage with FIGURE 2-4: Input Offset Voltage vs. V = 3.0V. Common Mode Input Voltage with V = 6.0V. DD DD 27% 1000 e of Occurences1112225814%%%%% 1VVT2ADC 4DM= 4 = =- S 4 3V0a.D0°mDCV/p3 tloe s+85°C set Voltage (µV) -2246800000000000 VDD = 3.0V Representative Part centag 69%% put Off --640000 TTTAAA === -++428055°°°CCC Per 3% In-1-080000 TA = +125°C 0% -20Inp-16ut O-12ffset-8 Drif-4t with0 Tem4per8atur12e (µV16/°C)20 -0.5 -0.2 0.1Co0.4mm0.7on 1.0Mod1.3e In1.6pu1.9t Vo2.2ltag2.5e (2.8V) 3.1 3.4 FIGURE 2-2: Input Offset Voltage Drift FIGURE 2-5: Input Offset Voltage vs. with V = 3.0V and T ≤ +85°C. Common Mode Input Voltage with V = 3.0V. DD A DD 27% 1000 curences122814%%% TA = +851°2C4V 4VtC oMDS D a+= m=1 V 23pD5.lD0°e/CVs3 age (µV) 468000000 VDD = 1.8V Representative Part Oc15% olt 200 Percentage of 12369%%%% Input Offset V ----8642000000000 TTTTAAAA ==== -+++42810552°°°5CCC°C 0% -1000 -20 -16 -12 -8 -4 0 4 8 12 16 20 0.5 0.3 0.1 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 Input Offset Drift with Temperature (µV/°C) - - -Common Mode Input Voltage (V) FIGURE 2-3: Input Offset Voltage Drift FIGURE 2-6: Input Offset Voltage vs. with V = 3.0V and T ≥ +85°C. Common Mode Input Voltage with V = 1.8V. DD A DD © 2009 Microchip Technology Inc. DS22142A-page 7

MCP6071/2/4 Note: Unless otherwise indicated, T = +25°C, V = +1.8V to +6.0V, V = GND, V = V /2, V ≈V /2, A DD SS CM DD OUT DD V = V /2, R = 10kΩ to V and C = 60pF. L DD L L L 350 y 40 age (µV) 125500 Representative Part e Densit 3305 fV =DD 1 =0 6k.H0zV et Volt -5500 VDD = 6.0V VoltagV/Hz)√2205 Input Offs---321555000 VDD = 1.8V VDD = 3.0V Input Noise (n110505 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 Output Voltage (V) - Common Mode Input Voltage (V) FIGURE 2-7: Input Offset Voltage vs. FIGURE 2-10: Input Noise Voltage Density Output Voltage. vs. Common Mode Input Voltage. 1000 110 V) 800 TA = -40°C Representative Part 100 PSRR- Representative Part ge (µ 460000 TTAA == ++2855°°CC dB)90 CMRR Offset Volta --4220000000 TA = +125°C RR, PSRR (56780000 PSRR+ ut -600 CM40 Inp-1-080000 30 5 0 5 0 5 0 5 0 5 0 5 20 1. 2. 2. 3. 3. 4. 4. 5. 5. 6. 6. 1100 110000 1 10k00 1 10000k0 1 1000000k0 1 010M0000 Power Supply Voltage (V) Frequency (Hz) FIGURE 2-8: Input Offset Voltage vs. FIGURE 2-11: CMRR, PSRR vs. Power Supply Voltage. Frequency. 1,000 110 sity 105 CMRR (VDD = 6.0V, VCM = -0.3V to 6.3V) en B)100 D d 95 e Voltage nV/Hz)√100 R, CMRR ( 889050 PSRR (VDD = 1.8V to 6.0V, VCM = VSS) ois( SR 75 N P 70 ut 65 p In 10 60 1 .0E.-11 1 .1E + 0 110.E + 1 101.0E + 2 11k. E + 3 101k.E + 4 1001k.E+5 -50 -25 0 25 50 75 100 125 Ambient Temperature (°C) Frequency (Hz) FIGURE 2-9: Input Noise Voltage Density FIGURE 2-12: CMRR, PSRR vs. Ambient vs. Frequency. Temperature. DS22142A-page 8 © 2009 Microchip Technology Inc.

MCP6071/2/4 Note: Unless otherwise indicated, T = +25°C, V = +1.8V to +6.0V, V = GND, V = V /2, V ≈V /2, A DD SS CM DD OUT DD V = V /2, R = 10kΩ to V and C = 60pF. L DD L L L e 0.35 150 g 0.30 mon Mode Input VoltaRange Limit (V)----0000000000..........21100011220505050505 V D D - V O H @@@ VVVDDDDDD VVV===OOO 316LLL.. .080--- VVVVVVSSSSSS @@@ VVVDDDDDD === 136...800VVV Quiescent Current (µA/Amplifier)1111101234890000000 VVDCDM == 60..09VV DD VDD = 1.8V m -0.25 70 VCM = 0.9VDD o -0.30 C -0.35 60 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 Ambient Temperature (°C) Ambient Temperature (°C) FIGURE 2-13: Common Mode Input FIGURE 2-16: Quiescent Current vs Voltage Range Limit vs. Ambient Temperature. Ambient Temperature with V = 0.9V . CM DD 10000 180 Input Bias and Offset Currents (pA) 101001000 VVDCDM == 6VI.nD0DpVut Bias CurrentInput Offset Current Quiescent Current (µA/Amplifier)11110246246800000000 VVDCDM == 60..09VV DD TTTTAAAA ==== +++-41820255°5°°CCC°C 1 0 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 25 45 65 85 105 125 0. 0. 1. 1. 2. 2. 3. 3. 4. 4. 5. 5. 6. 6. 7. Ambient Temperature (°C) Power Supply Voltage (V) FIGURE 2-14: Input Bias, Offset Currents FIGURE 2-17: Quiescent Current vs. vs. Ambient Temperature. Power Supply Voltage with V = 0.9V . CM DD 10000 120 0 A) VDD = 6.0V 100 Open-Loop Gain -30 urrent (p 1000 TA = +125°C Gain (dB) 6800 Open-Loop Phase --9600 Phase (°) put Bias C 10100 TA = +85°C pen-Loop 2400 --115200pen-Loop In O 0 VDD = 6.0V -180O 1 -20 -210 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 1 0.E.-101 1 . E1+ 0 0 11.E0+ 0 1 11.0E0+0 2 11.Ek+ 0 3 110.Ek+0 4 110.E0+0k5 1 1.EM+0 6 11.0E+M07 Common Mode Input Votlage (V) Frequency (Hz) FIGURE 2-15: Input Bias Current vs. FIGURE 2-18: Open-Loop Gain, Phase vs. Common Mode Input Voltage. Frequency. © 2009 Microchip Technology Inc. DS22142A-page 9

MCP6071/2/4 Note: Unless otherwise indicated, T = +25°C, V = +1.8V to +6.0V, V = GND, V = V /2, V ≈V /2, A DD SS CM DD OUT DD V = V /2, R = 10kΩ to V and C = 60pF. L DD L L L 150 1.8 180 DC-Open-Loop Gain (dB)111111111011223344505050505 RVSL S= + 1 00. 2kVΩ < VOUT < VDD - 0.2V Gain Bandwidth Product (MHz)000001111.........024680246 VGD =D =+G 16 a.V0in/VV Bandwidth ProPdhuacste Margin 024681111000002460000 Phase Margin (°) 100 505050505050505 0.0.0.1.1.2.2.3.3.4.4.5.5.6.6. 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 - Power Supply Voltage (V) Common Mode Input Voltage (V) FIGURE 2-19: DC Open-Loop Gain vs. FIGURE 2-22: Gain Bandwidth Product, Power Supply Voltage. Phase Margin vs. Common Mode Input Voltage. 150 1.8 180 Open-Loop Gain (dB)111111111122334405050505 VDD = 6.0VVDD = 1.8V Bandwidth Product (MHz)001111......680246 Gain Bandwidth Product 6811110002460000 hase Margin (°) DC-110005 Large Signal AOL Gain 00..24 VGD =D =+ 16 .V0/VV Phase Margin 2400 P 0.00 0.05 0.10 0.15 0.20 0.25 0.0 0 Output Voltage Headroom -50 -25 0 25 50 75 100 125 VDD - VOH or VOL - VSS (V) Ambient Temperature (°C) FIGURE 2-20: DC Open-Loop Gain vs. FIGURE 2-23: Gain Bandwidth Product, Output Voltage Headroom. Phase Margin vs. Ambient Temperature. 150 1.8 180 Channel to Channel Separation (dB)11111012349000000 Input Referred Gain Bandwidth Product (MHz)00001111........24680246 VGD =D =+G 11 a.V8i/nVV BandwidthP hParosed uMcatrgin 24681111000002460000 Phase Margin (°) 80 0.0 0 1 . 0 01E00+ 0 2 1 . 010kE + 0 3 1 .1000kE + 0 4 11.0000kE + 0 5 11M.00E+06 -50 -25 0 25 50 75 100 125 Frequency (Hz) Ambient Temperature (°C) FIGURE 2-21: Channel-to-Channel FIGURE 2-24: Gain Bandwidth Product, Separation vs. Frequency ( MCP6072/4 only). Phase Margin vs. Ambient Temperature. DS22142A-page 10 © 2009 Microchip Technology Inc.

MCP6071/2/4 Note: Unless otherwise indicated, T = +25°C, V = +1.8V to +6.0V, V = GND, V = V /2, V ≈V /2, A DD SS CM DD OUT DD V = V /2, R = 10kΩ to V and C = 60pF. L DD L L L nt 40 16.0 utput Short Circuit Curre(mA)1122330505055 TTTTAAAA ==== -+++42810552°°°5CCC°C utput Voltage Headroom - V or V - V (mV)DDOHSSOL1110242468.......0000000 VSS -V VDDO L- VOH O 0 OV 0 5 0 5 0 5 0 5 0 5 0 5 0 0.0 0. 0. 1. 1. 2. 2. 3. 3. 4. 4. 5. 5. 6. -50 -25 0 25 50 75 100 125 Power Supply Voltage (V) Ambient Temperature (°C) FIGURE 2-25: Ouput Short Circuit Current FIGURE 2-28: Output Voltage Headroom vs. Power Supply Voltage. vs. Ambient Temperature. 10 1.0 )P-P VDD = 6.0V 0.9 Falling Edge, VDD = 6.0V ng (V VDD = 1.8V ms)00..78 Falling Edge, VDD = 1.8V wi V/0.6 ge S 1 ate (0.5 a R0.4 Volt ew 0.3 ut Sl0.2 Rising Edge, VDD = 6.0V utp 0.1 Rising Edge, VDD = 1.8V O0.1 0.0 1 10k0 0 1 10000k0 1 0 1000000k 1 0 0 010M00 -50 -25 0 25 50 75 100 125 Frequency (Hz) Ambient Temperature (°C) FIGURE 2-26: Output Voltage Swing vs. FIGURE 2-29: Slew Rate vs. Ambient Frequency. Temperature. m to 5650 (VDD - VOH)/IOUT VDD = 1.8V v) o of Output HeadrooCurrent (mV/mA)112233445050505050 (VDD - VOH)/IOUT ((VVOOLL -- VVSSSS))//((--IIOOUUTT)) VDD = 6.0V put Voltage (50 mV/di VGD =D =+ 16 .V0/VV Rati 05 Out 0.1 1 10 Output Current (mA) Time (2 µs/div) FIGURE 2-27: Ratio of Output Voltage FIGURE 2-30: Small Signal Non-Inverting Headroom to Output Current vs. Output Current. Pulse Response. © 2009 Microchip Technology Inc. DS22142A-page 11

MCP6071/2/4 Note: Unless otherwise indicated, T = +25°C, V = +1.8V to +6.0V, V = GND, V = V /2, V ≈V /2, A DD SS CM DD OUT DD V = V /2, R = 10kΩ to V and C = 60pF. L DD L L L 7.0 mV/div) VGD =D =-1 6 V.0/VV V) 56..00 VOUT 50 ge ( 4.0 VIN ge ( olta 3.0 a V put Volt Output 12..00 Out 0.0 VDD = 6.0V G = +2 V/V -1.0 Time (2 µs/div) Time (0.2 ms/div) FIGURE 2-31: Small Signal Inverting Pulse FIGURE 2-34: The MCP6071/2/4 Shows Response. No Phase Reversal. 6.0 1000 5.5 5.0 ut oltage (V)3344....0505 oop Outpance (Ω)100 V Ld Output 122...505 VDD = 6.0V Closed Impe 10 G1101N1 :V V/V/V 1.0 G = +1 V/V 1 V/V 0.5 1 0.0 1100 110000 1 10k00 1 01000k0 1 1000000k0 1 0 10M0000 Time (0.02 ms/div) Frequency (Hz) FIGURE 2-32: Large Signal Non-Inverting FIGURE 2-35: Closed Loop Output Pulse Response. Impedance vs. Frequency. 6.0 1.1E-m03 5.5 110.E0-0µ4 V)45..50 VGD =D =-1 6 V.0/VV 11.E0-0µ5 e (4.0 1.E1-0µ6 ag3.5 A) 110.E0-0n7 utput Volt1223....5050 -I (IN 111101...EEE001---100nnp098 TTTTAAAA ==== -+++42810552°°°5CCC°C O 1.0 11.E0-1p1 0.5 1.E1-1p2 0.0 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 Time (0.02 ms/div) V (V) IN FIGURE 2-33: Large Signal Inverting Pulse FIGURE 2-36: Measured Input Current vs. Response. Input Voltage (below V ). SS DS22142A-page 12 © 2009 Microchip Technology Inc.

MCP6071/2/4 3.0 PIN DESCRIPTIONS Descriptions of the pins are listed in Table3-1. TABLE 3-1: PIN FUNCTION TABLE MCP6071 MCP6072 MCP6074 SOIC, Symbol Description SOIC 2x3 TDFN SOIC 2x3 TDFN TSSOP 6 6 1 1 1 V , V Analog Output (op amp A) OUT OUTA 2 2 2 2 2 V –, V – Inverting Input (op amp A) IN INA 3 3 3 3 3 V +, V + Non-inverting Input (op amp A) IN INA 7 7 8 8 4 V Positive Power Supply DD — — 5 5 5 V + Non-inverting Input (op amp B) INB — — 6 6 6 V – Inverting Input (op amp B) INB — — 7 7 7 V Analog Output (op amp B) OUTB — — — — 8 V Analog Output (op amp C) OUTC — — — — 9 V – Inverting Input (op amp C) INC — — — — 10 V + Non-inverting Input (op amp C) INC 4 4 4 4 11 V Negative Power Supply SS — — — — 12 V + Non-inverting Input (op amp D) IND — — — — 13 V – Inverting Input (op amp D) IND — — — — 14 V Analog Output (op amp D) OUTD 1, 5, 8 1, 5, 8 — — — NC No Internal Connection — 9 — 9 — EP Exposed Thermal Pad (EP); must be connected to V . SS 3.1 Analog Outputs 3.3 Power Supply Pins The output pins are low-impedance voltage sources. The positive power supply (V ) is 1.8V to 6.0V higher DD than the negative power supply (V ). For normal SS 3.2 Analog Inputs operation, the other pins are at voltages between VSS and V . DD The non-inverting and inverting inputs are high- Typically, these parts are used in a single (positive) impedance CMOS inputs with low bias currents. supply configuration. In this case, V is connected to SS ground and V is connected to the supply. V will DD DD need bypass capacitors. 3.4 Exposed Thermal Pad (EP) There is an internal electrical connection between the Exposed Thermal Pad (EP) and the V pin; they must SS be connected to the same potential on the Printed Circuit Board (PCB). © 2009 Microchip Technology Inc. DS22142A-page 13

MCP6071/2/4 NOTES: DS22142A-page 14 © 2009 Microchip Technology Inc.

MCP6071/2/4 4.0 APPLICATION INFORMATION V DD The MCP6071/2/4 family of op amps is manufactured using Microchip’s state-of-the-art CMOS process and is specifically designed for low-power, high precision D D 1 2 applications. V 1 4.1 Rail-to-Rail Input R1 MCP607X V 4.1.1 PHASE REVERASAL 2 R 2 The MCP6071/2/4 op amps are designed to prevent phase reversal when the input pins exceed the supply R voltages. Figure2-34 shows the input voltage exceed- 3 ing the supply voltage without any phase reversal. VSS–(minimum expected V1) R > 1 2mA 4.1.2 INPUT VOLTAGE AND CURRENT V –(minimum expected V ) SS 2 LIMITS R2> 2mA The ESD protection on the inputs can be depicted as FIGURE 4-2: Protecting the Analog shown in Figure4-1. This structure was chosen to Inputs. protect the input transistors and to minimize input bias current (IB). The input ESD diodes clamp the inputs It is also possible to connect the diodes to the left of the when they try to go more than one diode drop below resistors R and R . In this case, the currents through 1 2 VSS. They also clamp any voltage that go too far above the diodes D1 and D2 need to be limited by some other VDD; their breakdown voltage is high enough to allow mechanism. The resistors then serve as in-rush current normal operation and low enough to bypass ESD limiters; the DC currents into the input pins (V and IN+ events within the specified limits. V ) should be very small. A significant amount of IN- current can flow out of the inputs when the common mode voltage (V ) is below ground (V ). (See CM SS Bond V Figure2-36). DD Pad 4.1.3 NORMAL OPERATION The input stage of the MCP6071/2/4 op amps uses two V + Bond Input Bond V – differential input stages in parallel. One operates at a IN Pad Stage Pad IN low common mode input voltage (V ), while the other CM operates at a high V . With this topology, the device CM operates with a V up to 300mV above V and CM DD Bond 300mV below VSS. (See Figure2-13) .The input offset V SS Pad voltage is measured at VCM = VSS–0.3V and V +0.3V to ensure proper operation. DD FIGURE 4-1: Simplified Analog Input ESD The transition between the input stages occurs when Structures. V is near V –1.1V (See Figures2-4,2-5 and CM DD Figure2-6). For the best distortion performance and In order to prevent damage and/or improper operation gain linearity, with non-inverting gains, avoid this region of these op amps, the circuit they are in must limit the of operation. voltages and currents at the V and V pins (see IN+ IN- Absolute Maximum Ratings at the beginning of 4.2 Rail-to-Rail Output Section1.0 “Electrical Characteristics”). Figure4-2 shows the recommended approach to protecting these The output voltage range of the MCP6071/2/4 op amps inputs. The internal ESD diodes prevent the input pins is V +15mV (minimum) and V – 15mV (maxi- SS DD (VIN+ and VIN-) from going too far below ground, and mum) when RL=10kΩ is connected to VDD/2 and the resistors R1 and R2 limit the possible current drawn VDD=6.0V. Refer to Figures2-27 and 2-28 for more out of the input pins. Diodes D1 and D2 prevent the information. input pins (V and V ) from going too far above V . IN+ IN- DD When implemented as shown, resistors R and R also 1 2 limit the current through D and D . 1 2 © 2009 Microchip Technology Inc. DS22142A-page 15

MCP6071/2/4 4.3 Capacitive Loads After selecting R for your circuit, double-check the ISO resulting frequency response peaking and step Driving large capacitive loads can cause stability response overshoot. Modify R ’s value until the ISO problems for voltage feedback op amps. As the load response is reasonable. Bench evaluation and simula- capacitance increases, the feedback loop’s phase tions with the MCP6071/2/4 SPICE macro model are margin decreases and the closed-loop bandwidth is very helpful. reduced. This produces gain peaking in the frequency response, with overshoot and ringing in the step 4.4 Supply Bypass response. While a unity-gain buffer (G = +1) is the most sensitive to capacitive loads, all gains show the same With this family of operational amplifiers, the power general behavior. supply pin (V for single-supply) should have a local DD bypass capacitor (i.e., 0.01µF to 0.1µF) within 2mm When driving large capacitive loads with these op for good high frequency performance. It can use a bulk amps (e.g., > 100pF when G = +1), a small series resistor at the output (R in Figure4-3) improves the capacitor (i.e., 1µF or larger) within 100mm to provide ISO feedback loop’s phase margin (stability) by making the large, slow currents. This bulk capacitor can be shared output load resistive at higher frequencies. The with other analog parts. bandwidth will be generally lower than the bandwidth with no capacitance load. 4.5 Unused Op Amps An unused op amp in a quad package (MCP6074) should be configured as shown in Figure4-5. These circuits prevent the output from toggling and causing – R ISO crosstalk. Circuits A sets the op amp at its minimum MCP607X VOUT noise gain. The resistor divider produces any desired V + reference voltage within the output voltage range of the IN C L op amp; the op amp buffers that reference voltage. Circuit B uses the minimum number of components and operates as a comparator, but it may draw more FIGURE 4-3: Output Resistor, R current. ISO Stabilizes Large Capacitive Loads. Figure4-4 gives recommended RISO values for ¼ MCP6074 (A) ¼ MCP6074 (B) different capacitive loads and gains. The x-axis is the V V normalized load capacitance (C /G ), where G is the DD DD L N N circuit's noise gain. For non-inverting gains, G and the N V Signal Gain are equal. For inverting gains, GN is R1 DD 1+|Signal Gain| (e.g., -1V/V gives G = +2V/V). N V R REF 2 1000 d R (Ω)ISO 100 VRDLD = = 1 60. 0k ΩV VREF = VDD×R----1---R--+--2---R----2-- e nd GN: e 1 V/V m 10 2 V/V FIGURE 4-5: Unused Op Amps. m o ≥ 5 V/V c e R 1 11.0Ep-1 1 1 .1E0-100p 1 .1En-0 9 1 1.E0-n0 8 1 0.E.1-0µ7 1 .1Eµ-0 6 Normalized Load Capacitance; C/G (F) L N FIGURE 4-4: Recommended R Values ISO for Capacitive Loads. DS22142A-page 16 © 2009 Microchip Technology Inc.

MCP6071/2/4 4.6 PCB Surface Leakage In applications where low input bias current is critical, Printed Circuit Board (PCB) surface leakage effects need to be considered. Surface leakage is caused by humidity, dust or other contamination on the board. Under low humidity conditions, a typical resistance between nearby traces is 1012Ω. A 5V difference would cause 5pA of current to flow; which is greater than the MCP6071/2/4 family’s bias current at +25°C (±1.0pA, typical). The easiest way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). The guard ring is biased at the same voltage as the sensitive pin. An example of this type of layout is shown in Figure4-6. Guard Ring V – V + V IN IN SS FIGURE 4-6: Example Guard Ring Layout for Inverting Gain. 1. Non-inverting Gain and Unity-Gain Buffer: a. Connect the non-inverting pin (V +) to the IN input with a wire that does not touch the PCB surface. b. Connect the guard ring to the inverting input pin (V –). This biases the guard ring to the IN common mode input voltage. 2. Inverting Gain and Transimpedance Gain Ampli- fiers (convert current to voltage, such as photo detectors): a. Connect the guard ring to the non-inverting input pin (V +). This biases the guard ring IN to the same reference voltage as the op amp (e.g., V /2 or ground). DD b. Connect the inverting pin (V –) to the input IN with a wire that does not touch the PCB surface. © 2009 Microchip Technology Inc. DS22142A-page 17

MCP6071/2/4 4.7 Application Circuits 4.7.2 INSTRUMENTATION AMPLIFIER The MCP6071/2/4 op amps are well suited for condi- 4.7.1 GYRATOR tioning sensor signals in battery-powered applications. The MCP6071/2/4 op amps can be used in gyrator Figure4-8 shows a two op amp instrumentation applicaitons. The gyrator is an electric circuit which can amplifier, using the MCP6072, that works well for make a capacitive circuit behave inductively. Figure4- applications requiring rejection of common mode noise 7 shows an example of a gyrator simulating induc- at higher gains. The reference voltage (VREF) is tance, with an approximately equivalent circuit below. supplied by a low impedance source. In single supply The two ZIN have similar values in typical applications. applications, VREF is typically VDD/2. The primary application for a gyrator is to reduce the size and cost of a system by removing the need for R G bulky, heavy and expensive inductors. For example, RLC bandpass filter characteristics can be realized with capacitors, resistors and operational amplifiers VREF R1 R2 R2 R1 VOUT without using inductors. Moreover, gyrators will typi- cally have higher accuracy than real inductors, due to V the lower cost of precision capacitors than inductors. 2 ½ ½ . MCP6072 MCP6072 V 1 R L V R 2R ZIN OUT V = (V –V )⎛1+----1--+--------1-⎞ +V MCP6071 OUT 1 2 ⎝ R R ⎠ REF 2 G C FIGURE 4-8: Two Op Amp Gyrator Instrumentation Amplifier. R Z = R +jωL IN L To obtain the best CMRR possible, and not limit the L = R RC performance by the resistor tolerances, set a high gain L with the R resistor. G R Z L IN 4.7.3 PRECISION COMPARATOR Use high gain before a comparator to improve the Equivalent Circuit latter’s input offset performance. Figure4-9 shows a L gain of 11V/V placed before a comparator. The reference voltage V can be any value between the REF supply rails. FIGURE 4-7: Gyrator. V IN MCP6071 1MΩ MCP6541 V 100kΩ OUT V REF FIGURE 4-9: Precision, Non-inverting Comparator. DS22142A-page 18 © 2009 Microchip Technology Inc.

MCP6071/2/4 5.0 DESIGN AIDS 5.5 Analog Demonstration and Evaluation Boards Microchip provides the basic design tools needed for the MCP6071/2/4 family of op amps. Microchip offers a broad spectrum of Analog Demonstration and Evaluation Boards that are 5.1 SPICE Macro Model designed to help you achieve faster time to market. For a complete listing of these boards and their The latest SPICE macro model for the MCP6071/2/4 corresponding user’s guides and technical information, op amps is available on the Microchip web site at visit the Microchip web site at www.microchip.com/ www.microchip.com. This model is intended to be an analogtools. initial design tool that works well in the op amp’s linear Some boards that are especially useful are: region of operation over the temperature range. See the model file for information on its capabilities. • MCP6XXX Amplifier Evaluation Board 1 Bench testing is a very important part of any design and • MCP6XXX Amplifier Evaluation Board 2 cannot be replaced with simulations. Also, simulation • MCP6XXX Amplifier Evaluation Board 3 results using this macro model need to be validated by • MCP6XXX Amplifier Evaluation Board 4 comparing them to the data sheet specifications and • Active Filter Demo Board Kit characteristic curves. • 5/6-Pin SOT-23 Evaluation Board, P/N VSUPEV2 5.2 FilterLab® Software • 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board, P/N SOIC8EV Microchip’s FilterLab® software is an innovative • 14-Pin SOIC/TSSOP/DIP Evaluation Board, P/N software tool that simplifies analog active filter (using SOIC14EV op amps) design. Available at no cost from the Microchip web site at www.microchip.com/filterlab, the 5.6 Application Notes FilterLab design tool provides full schematic diagrams of the filter circuit with component values. It also The following Microchip Analog Design Note and outputs the filter circuit in SPICE format, which can be Application Notes are available on the Microchip web used with the macro model to simulate actual filter site at www.microchip. com/appnotes and are recom- performance. mended as supplemental reference resources. • ADN003: “Select the Right Operational Amplifier 5.3 Mindi™ Circuit Designer & for your Filtering Circuits”, DS21821 Simulator • AN722: “Operational Amplifier Topologies and DC Specifications”, DS00722 Microchip’s Mindi™ Circuit Designer & Simulator aids • AN723: “Operational Amplifier AC Specifications in the design of various circuits useful for active filter, and Applications”, DS00723 amplifier and power-management applications. It is a free online circuit designer & simulator available from • AN884: “Driving Capacitive Loads With Op the Microchip web site at www.microchip.com/mindi. Amps”, DS00884 This interactive circuit designer & simulator enables • AN990: “Analog Sensor Conditioning Circuits– designers to quickly generate circuit diagrams, An Overview”, DS00990 simulate circuits. Circuits developed using the Mindi • AN1177: “Op Amp Precision Design: DC Errors”, Circuit Designer & Simulator can be downloaded to a DS01177 personal computer or workstation. • AN1228: “Op Amp Precision Design: Random Noise”, DS01228 5.4 MAPS (Microchip Advanced Part These application notes and others are listed in the Selector) design guide: MAPS is a software tool that helps semiconductor • “Signal Chain Design Guide”, DS21825 professionals efficiently identify Microchip devices that fit a particular design requirement. Available at no cost from the Microchip website at www.microchip.com/ maps, the MAPS is an overall selection tool for Microchip’s product portfolio that includes Analog, Memory, MCUs and DSCs. Using this tool you can define a filter to sort features for a parametric search of devices and export side-by-side technical comparasion reports. Helpful links are also provided for Datasheets, Purchase, and Sampling of Microchip parts. © 2009 Microchip Technology Inc. DS22142A-page 19

MCP6071/2/4 NOTES: DS22142A-page 20 © 2009 Microchip Technology Inc.

MCP6071/2/4 6.0 PACKAGING INFORMATION 6.1 Package Marking Information 8-Lead SOIC (150 mil) (MCP6071, MCP6072) Example: XXXXXXXX MCP6071E XXXXYYWW SN^e^30910 NNN 256 8-Lead 2x3 TDFN (MCP6071, MCP6072) Example: XXX AHE YWW 910 NN 25 14-Lead SOIC (150 mil) (MCP6074) Example: XXXXXXXXXX MCP6074 XXXXXXXXXX E/SL^e^3 YYWWNNN 0910256 14-Lead TSSOP (MCP6074) Example: XXXXXX MCP6074E YYWW 0910 256 NNN Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2009 Microchip Technology Inc. DS22142A-page 21

MCP6071/2/4 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:10)(cid:8)(cid:17)(cid:18)(cid:12)(cid:10)(cid:13)(cid:19)(cid:5)(cid:8)(cid:20)(cid:15)(cid:21)(cid:22)(cid:8)(cid:23)(cid:8)(cid:21)(cid:6)(cid:24)(cid:24)(cid:25)(cid:26)(cid:27)(cid:8)(cid:28)(cid:29)(cid:30)(cid:31)(cid:8)(cid:16)(cid:16)(cid:8) (cid:25)(cid:7)!(cid:8)"(cid:15)(cid:17)#$% (cid:21)(cid:25)(cid:12)(cid:5)& 2(cid:21)(cid:20)(cid:14)%(cid:22)(cid:13)(cid:14)&(cid:21) %(cid:14)(cid:19)!(cid:20)(cid:20)(cid:13)(cid:24)%(cid:14)(cid:10)(cid:11)(cid:19)3(cid:11)(cid:12)(cid:13)(cid:14)"(cid:20)(cid:11))(cid:18)(cid:24)(cid:12) ’(cid:14)(cid:10)(cid:25)(cid:13)(cid:11) (cid:13)(cid:14) (cid:13)(cid:13)(cid:14)%(cid:22)(cid:13)(cid:14)(cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:14)(cid:30)(cid:11)(cid:19)3(cid:11)(cid:12)(cid:18)(cid:24)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:19)(cid:18)$(cid:18)(cid:19)(cid:11)%(cid:18)(cid:21)(cid:24)(cid:14)(cid:25)(cid:21)(cid:19)(cid:11)%(cid:13)"(cid:14)(cid:11)%(cid:14) (cid:22)%%(cid:10)144)))(cid:28)&(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:28)(cid:19)(cid:21)&4(cid:10)(cid:11)(cid:19)3(cid:11)(cid:12)(cid:18)(cid:24)(cid:12) D e N E E1 NOTE1 1 2 3 b h α h c A A2 φ A1 L L1 β 5(cid:24)(cid:18)% (cid:17)(cid:27)66(cid:27)(cid:17)-(cid:23)-(cid:8)(cid:3) (cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)(cid:14)6(cid:18)&(cid:18)% (cid:17)(cid:27)7 78(cid:17) (cid:17)(cid:7)9 7!&((cid:13)(cid:20)(cid:14)(cid:21)$(cid:14)(cid:30)(cid:18)(cid:24) 7 : (cid:30)(cid:18)%(cid:19)(cid:22) (cid:13) (cid:29)(cid:28)(cid:16)(cid:15)(cid:14)0(cid:3)+ 8(cid:31)(cid:13)(cid:20)(cid:11)(cid:25)(cid:25)(cid:14);(cid:13)(cid:18)(cid:12)(cid:22)% (cid:7) < < (cid:29)(cid:28)(cid:15). (cid:17)(cid:21)(cid:25)"(cid:13)"(cid:14)(cid:30)(cid:11)(cid:19)3(cid:11)(cid:12)(cid:13)(cid:14)(cid:23)(cid:22)(cid:18)(cid:19)3(cid:24)(cid:13) (cid:7)(cid:16) (cid:29)(cid:28)(cid:16). < < (cid:3)%(cid:11)(cid:24)"(cid:21)$$(cid:14)(cid:14)* (cid:7)(cid:29) (cid:4)(cid:28)(cid:29)(cid:4) < (cid:4)(cid:28)(cid:16). 8(cid:31)(cid:13)(cid:20)(cid:11)(cid:25)(cid:25)(cid:14)=(cid:18)"%(cid:22) - >(cid:28)(cid:4)(cid:4)(cid:14)0(cid:3)+ (cid:17)(cid:21)(cid:25)"(cid:13)"(cid:14)(cid:30)(cid:11)(cid:19)3(cid:11)(cid:12)(cid:13)(cid:14)=(cid:18)"%(cid:22) -(cid:29) ,(cid:28)(cid:6)(cid:4)(cid:14)0(cid:3)+ 8(cid:31)(cid:13)(cid:20)(cid:11)(cid:25)(cid:25)(cid:14)6(cid:13)(cid:24)(cid:12)%(cid:22) (cid:2) (cid:5)(cid:28)(cid:6)(cid:4)(cid:14)0(cid:3)+ +(cid:22)(cid:11)&$(cid:13)(cid:20)(cid:14)?(cid:21)(cid:10)%(cid:18)(cid:21)(cid:24)(cid:11)(cid:25)@ (cid:22) (cid:4)(cid:28)(cid:16). < (cid:4)(cid:28).(cid:4) 2(cid:21)(cid:21)%(cid:14)6(cid:13)(cid:24)(cid:12)%(cid:22) 6 (cid:4)(cid:28)(cid:5)(cid:4) < (cid:29)(cid:28)(cid:16)(cid:15) 2(cid:21)(cid:21)%(cid:10)(cid:20)(cid:18)(cid:24)% 6(cid:29) (cid:29)(cid:28)(cid:4)(cid:5)(cid:14)(cid:8)-2 2(cid:21)(cid:21)%(cid:14)(cid:7)(cid:24)(cid:12)(cid:25)(cid:13) (cid:3) (cid:4)A < :A 6(cid:13)(cid:11)"(cid:14)(cid:23)(cid:22)(cid:18)(cid:19)3(cid:24)(cid:13) (cid:19) (cid:4)(cid:28)(cid:29)(cid:15) < (cid:4)(cid:28)(cid:16). 6(cid:13)(cid:11)"(cid:14)=(cid:18)"%(cid:22) ( (cid:4)(cid:28),(cid:29) < (cid:4)(cid:28).(cid:29) (cid:17)(cid:21)(cid:25)"(cid:14)(cid:2)(cid:20)(cid:11)$%(cid:14)(cid:7)(cid:24)(cid:12)(cid:25)(cid:13)(cid:14)(cid:23)(cid:21)(cid:10) (cid:4) .A < (cid:29).A (cid:17)(cid:21)(cid:25)"(cid:14)(cid:2)(cid:20)(cid:11)$%(cid:14)(cid:7)(cid:24)(cid:12)(cid:25)(cid:13)(cid:14)0(cid:21)%%(cid:21)& (cid:5) .A < (cid:29).A (cid:21)(cid:25)(cid:12)(cid:5)(cid:11)& (cid:29)(cid:28) (cid:30)(cid:18)(cid:24)(cid:14)(cid:29)(cid:14)(cid:31)(cid:18) !(cid:11)(cid:25)(cid:14)(cid:18)(cid:24)"(cid:13)#(cid:14)$(cid:13)(cid:11)%!(cid:20)(cid:13)(cid:14)&(cid:11)(cid:26)(cid:14)(cid:31)(cid:11)(cid:20)(cid:26)’(cid:14)(!%(cid:14)&! %(cid:14)((cid:13)(cid:14)(cid:25)(cid:21)(cid:19)(cid:11)%(cid:13)"(cid:14))(cid:18)%(cid:22)(cid:18)(cid:24)(cid:14)%(cid:22)(cid:13)(cid:14)(cid:22)(cid:11)%(cid:19)(cid:22)(cid:13)"(cid:14)(cid:11)(cid:20)(cid:13)(cid:11)(cid:28) (cid:16)(cid:28) *(cid:14)(cid:3)(cid:18)(cid:12)(cid:24)(cid:18)$(cid:18)(cid:19)(cid:11)(cid:24)%(cid:14)+(cid:22)(cid:11)(cid:20)(cid:11)(cid:19)%(cid:13)(cid:20)(cid:18) %(cid:18)(cid:19)(cid:28) ,(cid:28) (cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24) (cid:14)(cid:2)(cid:14)(cid:11)(cid:24)"(cid:14)-(cid:29)(cid:14)"(cid:21)(cid:14)(cid:24)(cid:21)%(cid:14)(cid:18)(cid:24)(cid:19)(cid:25)!"(cid:13)(cid:14)&(cid:21)(cid:25)"(cid:14)$(cid:25)(cid:11) (cid:22)(cid:14)(cid:21)(cid:20)(cid:14)(cid:10)(cid:20)(cid:21)%(cid:20)! (cid:18)(cid:21)(cid:24) (cid:28)(cid:14)(cid:17)(cid:21)(cid:25)"(cid:14)$(cid:25)(cid:11) (cid:22)(cid:14)(cid:21)(cid:20)(cid:14)(cid:10)(cid:20)(cid:21)%(cid:20)! (cid:18)(cid:21)(cid:24) (cid:14) (cid:22)(cid:11)(cid:25)(cid:25)(cid:14)(cid:24)(cid:21)%(cid:14)(cid:13)#(cid:19)(cid:13)(cid:13)"(cid:14)(cid:4)(cid:28)(cid:29).(cid:14)&&(cid:14)(cid:10)(cid:13)(cid:20)(cid:14) (cid:18)"(cid:13)(cid:28) (cid:5)(cid:28) (cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)(cid:18)(cid:24)(cid:12)(cid:14)(cid:11)(cid:24)"(cid:14)%(cid:21)(cid:25)(cid:13)(cid:20)(cid:11)(cid:24)(cid:19)(cid:18)(cid:24)(cid:12)(cid:14)(cid:10)(cid:13)(cid:20)(cid:14)(cid:7)(cid:3)(cid:17)-(cid:14)/(cid:29)(cid:5)(cid:28).(cid:17)(cid:28) 0(cid:3)+1 0(cid:11) (cid:18)(cid:19)(cid:14)(cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)(cid:28)(cid:14)(cid:23)(cid:22)(cid:13)(cid:21)(cid:20)(cid:13)%(cid:18)(cid:19)(cid:11)(cid:25)(cid:25)(cid:26)(cid:14)(cid:13)#(cid:11)(cid:19)%(cid:14)(cid:31)(cid:11)(cid:25)!(cid:13)(cid:14) (cid:22)(cid:21))(cid:24)(cid:14))(cid:18)%(cid:22)(cid:21)!%(cid:14)%(cid:21)(cid:25)(cid:13)(cid:20)(cid:11)(cid:24)(cid:19)(cid:13) (cid:28) (cid:8)-21 (cid:8)(cid:13)$(cid:13)(cid:20)(cid:13)(cid:24)(cid:19)(cid:13)(cid:14)(cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)’(cid:14)! !(cid:11)(cid:25)(cid:25)(cid:26)(cid:14))(cid:18)%(cid:22)(cid:21)!%(cid:14)%(cid:21)(cid:25)(cid:13)(cid:20)(cid:11)(cid:24)(cid:19)(cid:13)’(cid:14)$(cid:21)(cid:20)(cid:14)(cid:18)(cid:24)$(cid:21)(cid:20)&(cid:11)%(cid:18)(cid:21)(cid:24)(cid:14)(cid:10)!(cid:20)(cid:10)(cid:21) (cid:13) (cid:14)(cid:21)(cid:24)(cid:25)(cid:26)(cid:28) (cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:23)(cid:13)(cid:19)(cid:22)(cid:24)(cid:21)(cid:25)(cid:21)(cid:12)(cid:26)(cid:2)(cid:20)(cid:11))(cid:18)(cid:24)(cid:12)+(cid:4)(cid:5)(cid:9)(cid:4).(cid:15)0 DS22142A-page 22 © 2009 Microchip Technology Inc.

MCP6071/2/4 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:10)(cid:8)(cid:17)(cid:18)(cid:12)(cid:10)(cid:13)(cid:19)(cid:5)(cid:8)(cid:20)(cid:15)(cid:21)(cid:22)(cid:8)(cid:23)(cid:8)(cid:21)(cid:6)(cid:24)(cid:24)(cid:25)(cid:26)(cid:27)(cid:8)(cid:28)(cid:29)(cid:30)(cid:31)(cid:8)(cid:16)(cid:16)(cid:8) (cid:25)(cid:7)!(cid:8)"(cid:15)(cid:17)#$% (cid:21)(cid:25)(cid:12)(cid:5)& 2(cid:21)(cid:20)(cid:14)%(cid:22)(cid:13)(cid:14)&(cid:21) %(cid:14)(cid:19)!(cid:20)(cid:20)(cid:13)(cid:24)%(cid:14)(cid:10)(cid:11)(cid:19)3(cid:11)(cid:12)(cid:13)(cid:14)"(cid:20)(cid:11))(cid:18)(cid:24)(cid:12) ’(cid:14)(cid:10)(cid:25)(cid:13)(cid:11) (cid:13)(cid:14) (cid:13)(cid:13)(cid:14)%(cid:22)(cid:13)(cid:14)(cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:14)(cid:30)(cid:11)(cid:19)3(cid:11)(cid:12)(cid:18)(cid:24)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:19)(cid:18)$(cid:18)(cid:19)(cid:11)%(cid:18)(cid:21)(cid:24)(cid:14)(cid:25)(cid:21)(cid:19)(cid:11)%(cid:13)"(cid:14)(cid:11)%(cid:14) (cid:22)%%(cid:10)144)))(cid:28)&(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:28)(cid:19)(cid:21)&4(cid:10)(cid:11)(cid:19)3(cid:11)(cid:12)(cid:18)(cid:24)(cid:12) © 2009 Microchip Technology Inc. DS22142A-page 23

MCP6071/2/4 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)’(cid:18)(cid:6)(cid:10)(cid:8)((cid:10)(cid:6)(cid:12)(cid:27)(cid:8)(cid:21)(cid:25)(cid:8)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:14))(cid:6)*(cid:5)(cid:8)(cid:20)+(cid:21)(cid:22)(cid:8)(cid:23)(cid:8),-(cid:28)-(cid:31)(cid:29)./(cid:8)(cid:16)(cid:16)(cid:8) (cid:25)(cid:7)!(cid:8)"0’((cid:21)% (cid:21)(cid:25)(cid:12)(cid:5)& 2(cid:21)(cid:20)(cid:14)%(cid:22)(cid:13)(cid:14)&(cid:21) %(cid:14)(cid:19)!(cid:20)(cid:20)(cid:13)(cid:24)%(cid:14)(cid:10)(cid:11)(cid:19)3(cid:11)(cid:12)(cid:13)(cid:14)"(cid:20)(cid:11))(cid:18)(cid:24)(cid:12) ’(cid:14)(cid:10)(cid:25)(cid:13)(cid:11) (cid:13)(cid:14) (cid:13)(cid:13)(cid:14)%(cid:22)(cid:13)(cid:14)(cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:14)(cid:30)(cid:11)(cid:19)3(cid:11)(cid:12)(cid:18)(cid:24)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:19)(cid:18)$(cid:18)(cid:19)(cid:11)%(cid:18)(cid:21)(cid:24)(cid:14)(cid:25)(cid:21)(cid:19)(cid:11)%(cid:13)"(cid:14)(cid:11)%(cid:14) (cid:22)%%(cid:10)144)))(cid:28)&(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:28)(cid:19)(cid:21)&4(cid:10)(cid:11)(cid:19)3(cid:11)(cid:12)(cid:18)(cid:24)(cid:12) DS22142A-page 24 © 2009 Microchip Technology Inc.

MCP6071/2/4 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)’(cid:18)(cid:6)(cid:10)(cid:8)((cid:10)(cid:6)(cid:12)(cid:27)(cid:8)(cid:21)(cid:25)(cid:8)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:14))(cid:6)*(cid:5)(cid:8)(cid:20)+(cid:21)(cid:22)(cid:8)(cid:23)(cid:8),-(cid:28)-(cid:31)(cid:29)./(cid:8)(cid:16)(cid:16)(cid:8) (cid:25)(cid:7)!(cid:8)"0’((cid:21)% (cid:21)(cid:25)(cid:12)(cid:5)& 2(cid:21)(cid:20)(cid:14)%(cid:22)(cid:13)(cid:14)&(cid:21) %(cid:14)(cid:19)!(cid:20)(cid:20)(cid:13)(cid:24)%(cid:14)(cid:10)(cid:11)(cid:19)3(cid:11)(cid:12)(cid:13)(cid:14)"(cid:20)(cid:11))(cid:18)(cid:24)(cid:12) ’(cid:14)(cid:10)(cid:25)(cid:13)(cid:11) (cid:13)(cid:14) (cid:13)(cid:13)(cid:14)%(cid:22)(cid:13)(cid:14)(cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:14)(cid:30)(cid:11)(cid:19)3(cid:11)(cid:12)(cid:18)(cid:24)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:19)(cid:18)$(cid:18)(cid:19)(cid:11)%(cid:18)(cid:21)(cid:24)(cid:14)(cid:25)(cid:21)(cid:19)(cid:11)%(cid:13)"(cid:14)(cid:11)%(cid:14) (cid:22)%%(cid:10)144)))(cid:28)&(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:28)(cid:19)(cid:21)&4(cid:10)(cid:11)(cid:19)3(cid:11)(cid:12)(cid:18)(cid:24)(cid:12) © 2009 Microchip Technology Inc. DS22142A-page 25

MCP6071/2/4 12(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:10)(cid:8)(cid:17)(cid:18)(cid:12)(cid:10)(cid:13)(cid:19)(cid:5)(cid:8)(cid:20)(cid:15)(cid:4)(cid:22)(cid:8)(cid:23)(cid:8)(cid:21)(cid:6)(cid:24)(cid:24)(cid:25)(cid:26)(cid:27)(cid:8)(cid:28)(cid:29)(cid:30)(cid:31)(cid:8)(cid:16)(cid:16)(cid:8) (cid:25)(cid:7)!(cid:8)"(cid:15)(cid:17)#$% (cid:21)(cid:25)(cid:12)(cid:5)& 2(cid:21)(cid:20)(cid:14)%(cid:22)(cid:13)(cid:14)&(cid:21) %(cid:14)(cid:19)!(cid:20)(cid:20)(cid:13)(cid:24)%(cid:14)(cid:10)(cid:11)(cid:19)3(cid:11)(cid:12)(cid:13)(cid:14)"(cid:20)(cid:11))(cid:18)(cid:24)(cid:12) ’(cid:14)(cid:10)(cid:25)(cid:13)(cid:11) (cid:13)(cid:14) (cid:13)(cid:13)(cid:14)%(cid:22)(cid:13)(cid:14)(cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:14)(cid:30)(cid:11)(cid:19)3(cid:11)(cid:12)(cid:18)(cid:24)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:19)(cid:18)$(cid:18)(cid:19)(cid:11)%(cid:18)(cid:21)(cid:24)(cid:14)(cid:25)(cid:21)(cid:19)(cid:11)%(cid:13)"(cid:14)(cid:11)%(cid:14) (cid:22)%%(cid:10)144)))(cid:28)&(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:28)(cid:19)(cid:21)&4(cid:10)(cid:11)(cid:19)3(cid:11)(cid:12)(cid:18)(cid:24)(cid:12) D N E E1 NOTE1 1 2 3 e h b α h c φ A A2 A1 L L1 β 5(cid:24)(cid:18)% (cid:17)(cid:27)66(cid:27)(cid:17)-(cid:23)-(cid:8)(cid:3) (cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)(cid:14)6(cid:18)&(cid:18)% (cid:17)(cid:27)7 78(cid:17) (cid:17)(cid:7)9 7!&((cid:13)(cid:20)(cid:14)(cid:21)$(cid:14)(cid:30)(cid:18)(cid:24) 7 (cid:29)(cid:5) (cid:30)(cid:18)%(cid:19)(cid:22) (cid:13) (cid:29)(cid:28)(cid:16)(cid:15)(cid:14)0(cid:3)+ 8(cid:31)(cid:13)(cid:20)(cid:11)(cid:25)(cid:25)(cid:14);(cid:13)(cid:18)(cid:12)(cid:22)% (cid:7) < < (cid:29)(cid:28)(cid:15). (cid:17)(cid:21)(cid:25)"(cid:13)"(cid:14)(cid:30)(cid:11)(cid:19)3(cid:11)(cid:12)(cid:13)(cid:14)(cid:23)(cid:22)(cid:18)(cid:19)3(cid:24)(cid:13) (cid:7)(cid:16) (cid:29)(cid:28)(cid:16). < < (cid:3)%(cid:11)(cid:24)"(cid:21)$$(cid:14)(cid:14)* (cid:7)(cid:29) (cid:4)(cid:28)(cid:29)(cid:4) < (cid:4)(cid:28)(cid:16). 8(cid:31)(cid:13)(cid:20)(cid:11)(cid:25)(cid:25)(cid:14)=(cid:18)"%(cid:22) - >(cid:28)(cid:4)(cid:4)(cid:14)0(cid:3)+ (cid:17)(cid:21)(cid:25)"(cid:13)"(cid:14)(cid:30)(cid:11)(cid:19)3(cid:11)(cid:12)(cid:13)(cid:14)=(cid:18)"%(cid:22) -(cid:29) ,(cid:28)(cid:6)(cid:4)(cid:14)0(cid:3)+ 8(cid:31)(cid:13)(cid:20)(cid:11)(cid:25)(cid:25)(cid:14)6(cid:13)(cid:24)(cid:12)%(cid:22) (cid:2) :(cid:28)>.(cid:14)0(cid:3)+ +(cid:22)(cid:11)&$(cid:13)(cid:20)(cid:14)?(cid:21)(cid:10)%(cid:18)(cid:21)(cid:24)(cid:11)(cid:25)@ (cid:22) (cid:4)(cid:28)(cid:16). < (cid:4)(cid:28).(cid:4) 2(cid:21)(cid:21)%(cid:14)6(cid:13)(cid:24)(cid:12)%(cid:22) 6 (cid:4)(cid:28)(cid:5)(cid:4) < (cid:29)(cid:28)(cid:16)(cid:15) 2(cid:21)(cid:21)%(cid:10)(cid:20)(cid:18)(cid:24)% 6(cid:29) (cid:29)(cid:28)(cid:4)(cid:5)(cid:14)(cid:8)-2 2(cid:21)(cid:21)%(cid:14)(cid:7)(cid:24)(cid:12)(cid:25)(cid:13) (cid:3) (cid:4)A < :A 6(cid:13)(cid:11)"(cid:14)(cid:23)(cid:22)(cid:18)(cid:19)3(cid:24)(cid:13) (cid:19) (cid:4)(cid:28)(cid:29)(cid:15) < (cid:4)(cid:28)(cid:16). 6(cid:13)(cid:11)"(cid:14)=(cid:18)"%(cid:22) ( (cid:4)(cid:28),(cid:29) < (cid:4)(cid:28).(cid:29) (cid:17)(cid:21)(cid:25)"(cid:14)(cid:2)(cid:20)(cid:11)$%(cid:14)(cid:7)(cid:24)(cid:12)(cid:25)(cid:13)(cid:14)(cid:23)(cid:21)(cid:10) (cid:4) .A < (cid:29).A (cid:17)(cid:21)(cid:25)"(cid:14)(cid:2)(cid:20)(cid:11)$%(cid:14)(cid:7)(cid:24)(cid:12)(cid:25)(cid:13)(cid:14)0(cid:21)%%(cid:21)& (cid:5) .A < (cid:29).A (cid:21)(cid:25)(cid:12)(cid:5)(cid:11)& (cid:29)(cid:28) (cid:30)(cid:18)(cid:24)(cid:14)(cid:29)(cid:14)(cid:31)(cid:18) !(cid:11)(cid:25)(cid:14)(cid:18)(cid:24)"(cid:13)#(cid:14)$(cid:13)(cid:11)%!(cid:20)(cid:13)(cid:14)&(cid:11)(cid:26)(cid:14)(cid:31)(cid:11)(cid:20)(cid:26)’(cid:14)(!%(cid:14)&! %(cid:14)((cid:13)(cid:14)(cid:25)(cid:21)(cid:19)(cid:11)%(cid:13)"(cid:14))(cid:18)%(cid:22)(cid:18)(cid:24)(cid:14)%(cid:22)(cid:13)(cid:14)(cid:22)(cid:11)%(cid:19)(cid:22)(cid:13)"(cid:14)(cid:11)(cid:20)(cid:13)(cid:11)(cid:28) (cid:16)(cid:28) *(cid:14)(cid:3)(cid:18)(cid:12)(cid:24)(cid:18)$(cid:18)(cid:19)(cid:11)(cid:24)%(cid:14)+(cid:22)(cid:11)(cid:20)(cid:11)(cid:19)%(cid:13)(cid:20)(cid:18) %(cid:18)(cid:19)(cid:28) ,(cid:28) (cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24) (cid:14)(cid:2)(cid:14)(cid:11)(cid:24)"(cid:14)-(cid:29)(cid:14)"(cid:21)(cid:14)(cid:24)(cid:21)%(cid:14)(cid:18)(cid:24)(cid:19)(cid:25)!"(cid:13)(cid:14)&(cid:21)(cid:25)"(cid:14)$(cid:25)(cid:11) (cid:22)(cid:14)(cid:21)(cid:20)(cid:14)(cid:10)(cid:20)(cid:21)%(cid:20)! (cid:18)(cid:21)(cid:24) (cid:28)(cid:14)(cid:17)(cid:21)(cid:25)"(cid:14)$(cid:25)(cid:11) (cid:22)(cid:14)(cid:21)(cid:20)(cid:14)(cid:10)(cid:20)(cid:21)%(cid:20)! (cid:18)(cid:21)(cid:24) (cid:14) (cid:22)(cid:11)(cid:25)(cid:25)(cid:14)(cid:24)(cid:21)%(cid:14)(cid:13)#(cid:19)(cid:13)(cid:13)"(cid:14)(cid:4)(cid:28)(cid:29).(cid:14)&&(cid:14)(cid:10)(cid:13)(cid:20)(cid:14) (cid:18)"(cid:13)(cid:28) (cid:5)(cid:28) (cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)(cid:18)(cid:24)(cid:12)(cid:14)(cid:11)(cid:24)"(cid:14)%(cid:21)(cid:25)(cid:13)(cid:20)(cid:11)(cid:24)(cid:19)(cid:18)(cid:24)(cid:12)(cid:14)(cid:10)(cid:13)(cid:20)(cid:14)(cid:7)(cid:3)(cid:17)-(cid:14)/(cid:29)(cid:5)(cid:28).(cid:17)(cid:28) 0(cid:3)+1 0(cid:11) (cid:18)(cid:19)(cid:14)(cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)(cid:28)(cid:14)(cid:23)(cid:22)(cid:13)(cid:21)(cid:20)(cid:13)%(cid:18)(cid:19)(cid:11)(cid:25)(cid:25)(cid:26)(cid:14)(cid:13)#(cid:11)(cid:19)%(cid:14)(cid:31)(cid:11)(cid:25)!(cid:13)(cid:14) (cid:22)(cid:21))(cid:24)(cid:14))(cid:18)%(cid:22)(cid:21)!%(cid:14)%(cid:21)(cid:25)(cid:13)(cid:20)(cid:11)(cid:24)(cid:19)(cid:13) (cid:28) (cid:8)-21 (cid:8)(cid:13)$(cid:13)(cid:20)(cid:13)(cid:24)(cid:19)(cid:13)(cid:14)(cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)’(cid:14)! !(cid:11)(cid:25)(cid:25)(cid:26)(cid:14))(cid:18)%(cid:22)(cid:21)!%(cid:14)%(cid:21)(cid:25)(cid:13)(cid:20)(cid:11)(cid:24)(cid:19)(cid:13)’(cid:14)$(cid:21)(cid:20)(cid:14)(cid:18)(cid:24)$(cid:21)(cid:20)&(cid:11)%(cid:18)(cid:21)(cid:24)(cid:14)(cid:10)!(cid:20)(cid:10)(cid:21) (cid:13) (cid:14)(cid:21)(cid:24)(cid:25)(cid:26)(cid:28) (cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:23)(cid:13)(cid:19)(cid:22)(cid:24)(cid:21)(cid:25)(cid:21)(cid:12)(cid:26)(cid:2)(cid:20)(cid:11))(cid:18)(cid:24)(cid:12)+(cid:4)(cid:5)(cid:9)(cid:4)>.0 DS22142A-page 26 © 2009 Microchip Technology Inc.

MCP6071/2/4 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:10)(cid:8)(cid:17)(cid:18)(cid:12)(cid:10)(cid:13)(cid:19)(cid:5)(cid:8)(cid:20)(cid:15)(cid:21)(cid:22)(cid:8)(cid:23)(cid:8)(cid:21)(cid:6)(cid:24)(cid:24)(cid:25)(cid:26)(cid:27)(cid:8)(cid:28)(cid:29)(cid:30)(cid:31)(cid:8)(cid:16)(cid:16)(cid:8) (cid:25)(cid:7)!(cid:8)"(cid:15)(cid:17)#$% (cid:21)(cid:25)(cid:12)(cid:5)& 2(cid:21)(cid:20)(cid:14)%(cid:22)(cid:13)(cid:14)&(cid:21) %(cid:14)(cid:19)!(cid:20)(cid:20)(cid:13)(cid:24)%(cid:14)(cid:10)(cid:11)(cid:19)3(cid:11)(cid:12)(cid:13)(cid:14)"(cid:20)(cid:11))(cid:18)(cid:24)(cid:12) ’(cid:14)(cid:10)(cid:25)(cid:13)(cid:11) (cid:13)(cid:14) (cid:13)(cid:13)(cid:14)%(cid:22)(cid:13)(cid:14)(cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:14)(cid:30)(cid:11)(cid:19)3(cid:11)(cid:12)(cid:18)(cid:24)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:19)(cid:18)$(cid:18)(cid:19)(cid:11)%(cid:18)(cid:21)(cid:24)(cid:14)(cid:25)(cid:21)(cid:19)(cid:11)%(cid:13)"(cid:14)(cid:11)%(cid:14) (cid:22)%%(cid:10)144)))(cid:28)&(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:28)(cid:19)(cid:21)&4(cid:10)(cid:11)(cid:19)3(cid:11)(cid:12)(cid:18)(cid:24)(cid:12) © 2009 Microchip Technology Inc. DS22142A-page 27

MCP6071/2/4 12(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)03(cid:13)(cid:19)(cid:8)(cid:15)3(cid:24)(cid:13)(cid:19))(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:10)(cid:8)(cid:17)(cid:18)(cid:12)(cid:10)(cid:13)(cid:19)(cid:5)(cid:8)(cid:20)(cid:15)0(cid:22)(cid:8)(cid:23)(cid:8)2(cid:29)2(cid:8)(cid:16)(cid:16)(cid:8) (cid:25)(cid:7)!(cid:8)"0(cid:15)(cid:15)(cid:17)(cid:9)% (cid:21)(cid:25)(cid:12)(cid:5)& 2(cid:21)(cid:20)(cid:14)%(cid:22)(cid:13)(cid:14)&(cid:21) %(cid:14)(cid:19)!(cid:20)(cid:20)(cid:13)(cid:24)%(cid:14)(cid:10)(cid:11)(cid:19)3(cid:11)(cid:12)(cid:13)(cid:14)"(cid:20)(cid:11))(cid:18)(cid:24)(cid:12) ’(cid:14)(cid:10)(cid:25)(cid:13)(cid:11) (cid:13)(cid:14) (cid:13)(cid:13)(cid:14)%(cid:22)(cid:13)(cid:14)(cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:14)(cid:30)(cid:11)(cid:19)3(cid:11)(cid:12)(cid:18)(cid:24)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:19)(cid:18)$(cid:18)(cid:19)(cid:11)%(cid:18)(cid:21)(cid:24)(cid:14)(cid:25)(cid:21)(cid:19)(cid:11)%(cid:13)"(cid:14)(cid:11)%(cid:14) (cid:22)%%(cid:10)144)))(cid:28)&(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:28)(cid:19)(cid:21)&4(cid:10)(cid:11)(cid:19)3(cid:11)(cid:12)(cid:18)(cid:24)(cid:12) D N E E1 NOTE1 1 2 e b c φ A A2 A1 L1 L 5(cid:24)(cid:18)% (cid:17)(cid:27)66(cid:27)(cid:17)-(cid:23)-(cid:8)(cid:3) (cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)(cid:14)6(cid:18)&(cid:18)% (cid:17)(cid:27)7 78(cid:17) (cid:17)(cid:7)9 7!&((cid:13)(cid:20)(cid:14)(cid:21)$(cid:14)(cid:30)(cid:18)(cid:24) 7 (cid:29)(cid:5) (cid:30)(cid:18)%(cid:19)(cid:22) (cid:13) (cid:4)(cid:28)>.(cid:14)0(cid:3)+ 8(cid:31)(cid:13)(cid:20)(cid:11)(cid:25)(cid:25)(cid:14);(cid:13)(cid:18)(cid:12)(cid:22)% (cid:7) < < (cid:29)(cid:28)(cid:16)(cid:4) (cid:17)(cid:21)(cid:25)"(cid:13)"(cid:14)(cid:30)(cid:11)(cid:19)3(cid:11)(cid:12)(cid:13)(cid:14)(cid:23)(cid:22)(cid:18)(cid:19)3(cid:24)(cid:13) (cid:7)(cid:16) (cid:4)(cid:28):(cid:4) (cid:29)(cid:28)(cid:4)(cid:4) (cid:29)(cid:28)(cid:4). (cid:3)%(cid:11)(cid:24)"(cid:21)$$(cid:14) (cid:7)(cid:29) (cid:4)(cid:28)(cid:4). < (cid:4)(cid:28)(cid:29). 8(cid:31)(cid:13)(cid:20)(cid:11)(cid:25)(cid:25)(cid:14)=(cid:18)"%(cid:22) - >(cid:28)(cid:5)(cid:4)(cid:14)0(cid:3)+ (cid:17)(cid:21)(cid:25)"(cid:13)"(cid:14)(cid:30)(cid:11)(cid:19)3(cid:11)(cid:12)(cid:13)(cid:14)=(cid:18)"%(cid:22) -(cid:29) (cid:5)(cid:28),(cid:4) (cid:5)(cid:28)(cid:5)(cid:4) (cid:5)(cid:28).(cid:4) (cid:17)(cid:21)(cid:25)"(cid:13)"(cid:14)(cid:30)(cid:11)(cid:19)3(cid:11)(cid:12)(cid:13)(cid:14)6(cid:13)(cid:24)(cid:12)%(cid:22) (cid:2) (cid:5)(cid:28)(cid:6)(cid:4) .(cid:28)(cid:4)(cid:4) .(cid:28)(cid:29)(cid:4) 2(cid:21)(cid:21)%(cid:14)6(cid:13)(cid:24)(cid:12)%(cid:22) 6 (cid:4)(cid:28)(cid:5). (cid:4)(cid:28)>(cid:4) (cid:4)(cid:28)(cid:15). 2(cid:21)(cid:21)%(cid:10)(cid:20)(cid:18)(cid:24)% 6(cid:29) (cid:29)(cid:28)(cid:4)(cid:4)(cid:14)(cid:8)-2 2(cid:21)(cid:21)%(cid:14)(cid:7)(cid:24)(cid:12)(cid:25)(cid:13) (cid:3) (cid:4)A < :A 6(cid:13)(cid:11)"(cid:14)(cid:23)(cid:22)(cid:18)(cid:19)3(cid:24)(cid:13) (cid:19) (cid:4)(cid:28)(cid:4)(cid:6) < (cid:4)(cid:28)(cid:16)(cid:4) 6(cid:13)(cid:11)"(cid:14)=(cid:18)"%(cid:22) ( (cid:4)(cid:28)(cid:29)(cid:6) < (cid:4)(cid:28),(cid:4) (cid:21)(cid:25)(cid:12)(cid:5)(cid:11)& (cid:29)(cid:28) (cid:30)(cid:18)(cid:24)(cid:14)(cid:29)(cid:14)(cid:31)(cid:18) !(cid:11)(cid:25)(cid:14)(cid:18)(cid:24)"(cid:13)#(cid:14)$(cid:13)(cid:11)%!(cid:20)(cid:13)(cid:14)&(cid:11)(cid:26)(cid:14)(cid:31)(cid:11)(cid:20)(cid:26)’(cid:14)(!%(cid:14)&! %(cid:14)((cid:13)(cid:14)(cid:25)(cid:21)(cid:19)(cid:11)%(cid:13)"(cid:14))(cid:18)%(cid:22)(cid:18)(cid:24)(cid:14)%(cid:22)(cid:13)(cid:14)(cid:22)(cid:11)%(cid:19)(cid:22)(cid:13)"(cid:14)(cid:11)(cid:20)(cid:13)(cid:11)(cid:28) (cid:16)(cid:28) (cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24) (cid:14)(cid:2)(cid:14)(cid:11)(cid:24)"(cid:14)-(cid:29)(cid:14)"(cid:21)(cid:14)(cid:24)(cid:21)%(cid:14)(cid:18)(cid:24)(cid:19)(cid:25)!"(cid:13)(cid:14)&(cid:21)(cid:25)"(cid:14)$(cid:25)(cid:11) (cid:22)(cid:14)(cid:21)(cid:20)(cid:14)(cid:10)(cid:20)(cid:21)%(cid:20)! (cid:18)(cid:21)(cid:24) (cid:28)(cid:14)(cid:17)(cid:21)(cid:25)"(cid:14)$(cid:25)(cid:11) (cid:22)(cid:14)(cid:21)(cid:20)(cid:14)(cid:10)(cid:20)(cid:21)%(cid:20)! (cid:18)(cid:21)(cid:24) (cid:14) (cid:22)(cid:11)(cid:25)(cid:25)(cid:14)(cid:24)(cid:21)%(cid:14)(cid:13)#(cid:19)(cid:13)(cid:13)"(cid:14)(cid:4)(cid:28)(cid:29).(cid:14)&&(cid:14)(cid:10)(cid:13)(cid:20)(cid:14) (cid:18)"(cid:13)(cid:28) ,(cid:28) (cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)(cid:18)(cid:24)(cid:12)(cid:14)(cid:11)(cid:24)"(cid:14)%(cid:21)(cid:25)(cid:13)(cid:20)(cid:11)(cid:24)(cid:19)(cid:18)(cid:24)(cid:12)(cid:14)(cid:10)(cid:13)(cid:20)(cid:14)(cid:7)(cid:3)(cid:17)-(cid:14)/(cid:29)(cid:5)(cid:28).(cid:17)(cid:28) 0(cid:3)+1 0(cid:11) (cid:18)(cid:19)(cid:14)(cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)(cid:28)(cid:14)(cid:23)(cid:22)(cid:13)(cid:21)(cid:20)(cid:13)%(cid:18)(cid:19)(cid:11)(cid:25)(cid:25)(cid:26)(cid:14)(cid:13)#(cid:11)(cid:19)%(cid:14)(cid:31)(cid:11)(cid:25)!(cid:13)(cid:14) (cid:22)(cid:21))(cid:24)(cid:14))(cid:18)%(cid:22)(cid:21)!%(cid:14)%(cid:21)(cid:25)(cid:13)(cid:20)(cid:11)(cid:24)(cid:19)(cid:13) (cid:28) (cid:8)-21 (cid:8)(cid:13)$(cid:13)(cid:20)(cid:13)(cid:24)(cid:19)(cid:13)(cid:14)(cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)’(cid:14)! !(cid:11)(cid:25)(cid:25)(cid:26)(cid:14))(cid:18)%(cid:22)(cid:21)!%(cid:14)%(cid:21)(cid:25)(cid:13)(cid:20)(cid:11)(cid:24)(cid:19)(cid:13)’(cid:14)$(cid:21)(cid:20)(cid:14)(cid:18)(cid:24)$(cid:21)(cid:20)&(cid:11)%(cid:18)(cid:21)(cid:24)(cid:14)(cid:10)!(cid:20)(cid:10)(cid:21) (cid:13) (cid:14)(cid:21)(cid:24)(cid:25)(cid:26)(cid:28) (cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:23)(cid:13)(cid:19)(cid:22)(cid:24)(cid:21)(cid:25)(cid:21)(cid:12)(cid:26)(cid:2)(cid:20)(cid:11))(cid:18)(cid:24)(cid:12)+(cid:4)(cid:5)(cid:9)(cid:4):(cid:15)0 DS22142A-page 28 © 2009 Microchip Technology Inc.

MCP6071/2/4 APPENDIX A: REVISION HISTORY Revision A (March 2009) • Original Release of this Document. © 2009 Microchip Technology Inc. DS22142A-page 29

MCP6071/2/4 NOTES: DS22142A-page 30 © 2009 Microchip Technology Inc.

MCP6071/2/4 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX Examples: a) MCP6071-E/SN: 8LD SOIC pkg Device Temperature Package b) MCP6071T-E/SN: Tape and Reel, Range 8LD SOIC pkg c) MCP6071-E/MNY: 8LD 2x3 TDFN pkg d) MCP6071T-E/MNY: Tape and Reel, Device: MCP6071: Single Op Amp MCP6071T: Single Op Amp (Tape and Reel) 8LD 2x3 TDFN pkg (SOIC and 2x3 TDFN) MCP6072: Dual Op Amp a) MCP6072-E/SN: 8LD SOIC pkg MCP6072T: Dual Op Amp (Tape and Reel) b) MCP6072T-E/SN: Tape and Reel, (SOIC and 2x3 TDFN) MCP6074: Quad Op Amp 8LD SOIC pkg MCP6074T: Quad Op Amp (Tape and Reel) c) MCP6072-E/MN: 8LD 2x3 TDFN pkg (SOIC and TSSOP) d) MCP6072T-E/MN: Tape and Reel 8LD 2x3 TDFN pkg Temperature Range: E = -40°C to +125°C a) MCP6074-E/SL: 14LD SOIC pkg b) MCP6074T-E/SL: Tape and Reel, Package: MNY * = Plastic Dual Flat, No Lead, (2x3 TDFN ) 8-leadd 14LD SOIC pkg SL = Plastic SOIC (150 mil Body), 14-lead SN = Plastic SOIC, (150 mil Body), 8-lead c) MCP6074-E/ST: 14LD TSSOP pkg ST = Plastic TSSOP (4.4mm Body), 14-lead d) MCP6074T-E/ST: Tape and Reel, * Y = Nickel palladium gold manufacturing designator. Only 14LD TSSOP pkg available on the TDFN package. © 2009 Microchip Technology Inc. DS22142A-page 31

MCP6071/2/4 NOTES: DS22142A-page 32 © 2009 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, Accuron, and may be superseded by updates. It is your responsibility to dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, ensure that your application meets with your specifications. PICSTART, rfPIC, SmartShunt and UNI/O are registered MICROCHIP MAKES NO REPRESENTATIONS OR trademarks of Microchip Technology Incorporated in the WARRANTIES OF ANY KIND WHETHER EXPRESS OR U.S.A. and other countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Linear Active Thermistor, MXDEV, MXLAB, INCLUDING BUT NOT LIMITED TO ITS CONDITION, SEEVAL, SmartSensor and The Embedded Control Solutions QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, CodeGuard, devices in life support and/or safety applications is entirely at dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, the buyer’s risk, and the buyer agrees to defend, indemnify and ECONOMONITOR, FanSense, In-Circuit Serial hold harmless Microchip from any and all damages, claims, Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB suits, or expenses resulting from such use. No licenses are Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP, conveyed, implicitly or otherwise, under any Microchip PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, intellectual property rights. PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2009 Microchip Technology Inc. DS22142A-page 33

Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office Asia Pacific Office India - Bangalore Austria - Wels 2355 West Chandler Blvd. Suites 3707-14, 37th Floor Tel: 91-80-3090-4444 Tel: 43-7242-2244-39 Chandler, AZ 85224-6199 Tower 6, The Gateway Fax: 91-80-3090-4080 Fax: 43-7242-2244-393 Tel: 480-792-7200 Harbour City, Kowloon India - New Delhi Denmark - Copenhagen Fax: 480-792-7277 Hong Kong Tel: 91-11-4160-8631 Tel: 45-4450-2828 Technical Support: Tel: 852-2401-1200 Fax: 91-11-4160-8632 Fax: 45-4485-2829 http://support.microchip.com Web Address: Fax: 852-2401-3431 India - Pune France - Paris www.microchip.com Australia - Sydney Tel: 91-20-2566-1512 Tel: 33-1-69-53-63-20 Tel: 61-2-9868-6733 Fax: 33-1-69-30-90-79 Fax: 91-20-2566-1513 Atlanta Fax: 61-2-9868-6755 Germany - Munich Duluth, GA Japan - Yokohama China - Beijing Tel: 49-89-627-144-0 Tel: 678-957-9614 Tel: 81-45-471- 6166 Tel: 86-10-8528-2100 Fax: 49-89-627-144-44 Fax: 678-957-1455 Fax: 81-45-471-6122 Fax: 86-10-8528-2104 Italy - Milan Boston Korea - Daegu Westborough, MA China - Chengdu Tel: 82-53-744-4301 Tel: 39-0331-742611 Tel: 774-760-0087 Tel: 86-28-8665-5511 Fax: 82-53-744-4302 Fax: 39-0331-466781 Fax: 774-760-0088 Fax: 86-28-8665-7889 Korea - Seoul Netherlands - Drunen Chicago China - Hong Kong SAR Tel: 82-2-554-7200 Tel: 31-416-690399 Itasca, IL Tel: 852-2401-1200 Fax: 82-2-558-5932 or Fax: 31-416-690340 Tel: 630-285-0071 Fax: 852-2401-3431 82-2-558-5934 Spain - Madrid Fax: 630-285-0075 China - Nanjing Malaysia - Kuala Lumpur Tel: 34-91-708-08-90 Cleveland Tel: 86-25-8473-2460 Tel: 60-3-6201-9857 Fax: 34-91-708-08-91 Independence, OH Fax: 86-25-8473-2470 Fax: 60-3-6201-9859 UK - Wokingham Tel: 216-447-0464 China - Qingdao Malaysia - Penang Tel: 44-118-921-5869 Fax: 216-447-0643 Tel: 86-532-8502-7355 Tel: 60-4-227-8870 Fax: 44-118-921-5820 Dallas Fax: 86-532-8502-7205 Fax: 60-4-227-4068 Addison, TX China - Shanghai Philippines - Manila Tel: 972-818-7423 Tel: 86-21-5407-5533 Tel: 63-2-634-9065 Fax: 972-818-2924 Fax: 86-21-5407-5066 Fax: 63-2-634-9069 Detroit China - Shenyang Singapore Farmington Hills, MI Tel: 86-24-2334-2829 Tel: 65-6334-8870 Tel: 248-538-2250 Fax: 86-24-2334-2393 Fax: 65-6334-8850 Fax: 248-538-2260 China - Shenzhen Taiwan - Hsin Chu Kokomo Tel: 86-755-8203-2660 Tel: 886-3-572-9526 Kokomo, IN Fax: 86-755-8203-1760 Fax: 886-3-572-6459 Tel: 765-864-8360 Fax: 765-864-8387 China - Wuhan Taiwan - Kaohsiung Tel: 86-27-5980-5300 Tel: 886-7-536-4818 Los Angeles Fax: 86-27-5980-5118 Fax: 886-7-536-4803 Mission Viejo, CA Tel: 949-462-9523 China - Xiamen Taiwan - Taipei Fax: 949-462-9608 Tel: 86-592-2388138 Tel: 886-2-2500-6610 Fax: 86-592-2388130 Fax: 886-2-2508-0102 Santa Clara Santa Clara, CA China - Xian Thailand - Bangkok Tel: 408-961-6444 Tel: 86-29-8833-7252 Tel: 66-2-694-1351 Fax: 408-961-6445 Fax: 86-29-8833-7256 Fax: 66-2-694-1350 Toronto China - Zhuhai Mississauga, Ontario, Tel: 86-756-3210040 Canada Fax: 86-756-3210049 Tel: 905-673-0699 Fax: 905-673-6509 02/04/09 DS22142A-page 34 © 2009 Microchip Technology Inc.

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: MCP6071T-E/SN MCP6072T-E/SN MCP6071-E/SN MCP6074-E/SL MCP6072T-E/MNY MCP6074T-E/ST MCP6074T-E/SL MCP6072-E/SN MCP6071T-E/MNY MCP6074-E/ST MCP6071T-E/OTVAO MCP6072T-E/SNVAO