MCP6031/2/3/4 0.9 µA, High-Precision Op Amps Features Description • Rail-to-Rail Input and Output The Microchip Technology Inc. MCP6031/2/3/4 family • Low Offset Voltage: 150µV (maximum) of operational amplifiers (op amps) operates with a single-supply voltage as low as 1.8V, while drawing • Ultra-Low Quiescent Current: 0.9µA (typical) ultra-low quiescent current per amplifier (0.9 µA, • Wide Power Supply Voltage: 1.8V to 5.5V typical). This family also has low input offset voltage • Gain Bandwidth Product: 10kHz (typical) (150 µV, maximum) and rail-to-rail input and output • Unity Gain Stable operation. This combination of features supports • Chip Select (CS) capability: MCP6033 battery-powered and portable applications. • Extended Temperature Range: The MCP6031/2/3/4 family is unity gain stable and has - -40°C to +125°C a gain bandwidth product of 10 kHz (typical). These • No Phase Reversal specifications make these op amps appropriate for low-frequency applications, such as battery current monitoring and sensor conditioning. Applications The MCP6031/2/3/4 family is offered in single • Toll Booth Tags (MCP6031), single with power-saving Chip Select (CS) • Wearable Products input (MCP6033), dual (MCP6032) and quad • Battery Current Monitoring (MCP6034) configurations. • Sensor Conditioning The MCP6031/2/3/4 family is designed with Microchip’s • Battery Powered advanced CMOS process. All devices are available in the extended temperature range, with a power supply Design Aids range of 1.8V to 5.5V. • SPICE Macro Models Package Types • FilterLab® Software MCP6031 MCP6033 • Mindi™ Circuit Designer and Simulator DFN, SOIC, MSOP DFN, SOIC, MSOP • MAPS (Microchip Advanced Part Selector) NC 1 8 NC NC 1 8 CS • Analog Demonstration and Evaluation Boards • Application Notes VIN- 2 – 7 VDD VIN- 2 – 7 VDD VIN+ 3 + 6 VOUT VIN+ 3 + 6 VOUT Typical Application VSS 4 5 NC VSS 4 5 NC I MCP6031 MCP6034 DD V DD SOT-23 SOIC, TSSOP 1.4V to 10 + VOUT 1 5 VDD VOUTA 1 14VOUTD 5.5V VOUT VSS 2 VINA- 2 –+ +– 13VIND- 100k MCP6031 VIN+ 3 +– 4 VIN- VINA+ 3 12VIND+ – VDD 4 11 VSS 1M MCP6032 VINB+ 5 10VINC+ SOIC, MSOP VINB- 6 9 VINC- IDD = ---1---0V----D-V---D/--V---–----V----O--1--U-0--T-------- VVOIUNTAA- 12 –+ 87 VVODDUTBVOUTB 7 –+ +– 8 VOUTC High-Side Battery Current Sensor VINA+ 3 +– 6 VINB- VSS 4 5 VINB+  2007-2019 Microchip Technology Inc. DS20002041C-page 1

MCP6031/2/3/4 1.0 ELECTRICAL † Notice: Stresses above those listed under “Absolute CHARACTERISTICS Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions Absolute Maximum Ratings† above those indicated in the operational listings of this V – V ........................................................................7.0V specification is not implied. Exposure to maximum rat- DD SS Current at Input Pins.....................................................±2mA ing conditions for extended periods may affect device Analog Inputs (V +, V -)††..........V –1.0V to V +1.0V reliability. IN IN SS DD All Other Inputs and Outputs .........VSS –0.3V to VDD +0.3V †† See Section4.1.2 “Input Voltage and Current Difference Input Voltage ......................................|VDD – VSS| Limits”. Output Short-Circuit Current .................................continuous Current at Output and Supply Pins ............................±30mA Storage Temperature.....................................-65°C to +150°C Maximum Junction Temperature (T )..........................+150°C J ESD Protection on All Pins (HBM; MM) 4kV; 400V DC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated: V = +1.8V to +5.5V, V = GND, T = +25°C, DD SS A V = V /2, V V /2, V = V /2, R = 1Mto V and CS is tied low. (Refer to Figure1-2 and Figure1-3.) CM DD OUT DD L DD L L Parameters Sym Min Typ Max Units Conditions Input Offset Input Offset Voltage V -150 — +150 µV V = 3.0V, V = V /3 OS DD CM DD Input Offset Drift with Temperature V /T — ±3.0 — µV/°C T = -40°C to +125°C, OS A A V = 3.0V, V = V /3 DD CM DD Power Supply Rejection Ratio PSRR 70 88 — dB V = V CM SS Input Bias Current and Impedance Input Bias Current I — ±1.0 100 pA B I — 60 — pA T = +85°C B A I — 2000 5000 pA T = +125°C B A Input Offset Current I — ±1.0 — pA OS Common-mode Input Impedance Z — 1013||6 — ||pF CM Differential Input Impedance Z — 1013||6 — ||pF DIFF Common-mode Common-mode Input Voltage V V –0.3 — V + 0.3 V CMR SS DD Range Common-mode Rejection Ratio CMRR 70 95 — dB V = -0.3V to 2.1V, CM V = 1.8V DD 72 93 — dB V = -0.3V to 5.8V, CM V = 5.5V DD 70 89 — dB V = 2.75V to 5.8V, CM V = 5.5V DD 72 93 — dB V = -0.3V to 2.75V, CM V = 5.5V DD Open-Loop Gain DC Open-Loop Gain A 95 115 — dB 0.2V < V < (V – 0.2V), OL OUT DD (Large Signal) R = 50k to V L L DS20002041C-page 2  2007-2019 Microchip Technology Inc.

MCP6031/2/3/4 DC ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise indicated: V = +1.8V to +5.5V, V = GND, T = +25°C, DD SS A V = V /2, V V /2, V = V /2, R = 1Mto V and CS is tied low. (Refer to Figure1-2 and Figure1-3.) CM DD OUT DD L DD L L Parameters Sym Min Typ Max Units Conditions Output Maximum Output Voltage Swing V , V V + 10 — V – 10 mV R = 50k to V , OL OH SS DD L L 0.5V input overdrive Output Short-Circuit Current I — ±5 — mA V = 1.8V SC DD — ±23 — mA V = 5.5V DD Power Supply Supply Voltage V 1.8 — 5.5 V DD Quiescent Current per Amplifier I 0.4 0.9 1.35 µA I = 0, V = V Q O CM DD, V = 5.5V DD AC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated: T = +25°C, V = +1.8 to +5.5V, V = GND, V = V /2, A DD SS CM DD V V /2, V = V /2, C = 60pF, R = 1Mto V and CS is tied low. (Refer to Figure1-2 and Figure1-3.) OUT DD L DD L L L Parameters Sym Min Typ Max Units Conditions AC Response Gain Bandwidth Product GBWP — 10 — kHz Phase Margin PM — 65 — ° G = +1V/V Slew Rate SR — 4.0 — V/ms Noise Input Noise Voltage E — 3.9 — µVp-p f = 0.1Hz to 10Hz ni Input Noise Voltage Density e — 165 — nV/Hz f = 1kHz ni Input Noise Current Density i — 0.6 — fA/Hz f = 1kHz ni  2007-2019 Microchip Technology Inc. DS20002041C-page 3

MCP6031/2/3/4 MCP6033 CHIP SELECT ELECTRICAL CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, V =+1.8V to +5.5V, V =GND, T =+25°C, V =V /2, DD SS A CM DD V =V /2, V = V /2, C = 60pF, R = 1Mto V and CS is tied low (Refer to Figure1-1). OUT DD L DD L L L Parameters Sym Min Typ Max Units Conditions CS Low Specifications CS Logic Threshold, Low V V — 0.2 V V IL SS DD CS Input Current, Low I — -10 — pA CS = V CSL SS CS High Specifications CS Logic Threshold, High V 0.8 V — V V IH DD DD CS Input Current, High I — 10 — pA CS = V CSH DD GND Current I — -400 — pA CS = V SS DD Amplifier Output Leakage I — 10 — pA CS = V O(LEAK) DD CS Dynamic Specifications CS Low to Amplifier Output t — 4 100 ms CS  0.2 V to V = 0.9 V /2, ON DD OUT DD Turn-on Time G = +1V/V, V = V /2, IN DD R = 50kto V = V L L SS CS High to Amplifier Output t — 10 — µs CS  0.8 V to V = 0.1 V /2, OFF DD OUT DD High-Z G = +1V/V, V = V /2, IN DD R = 50kto V = V L L SS CS Hysteresis V — 0.3 V — V HYST DD CS V V IL IH t t ON OFF VOUT High-Z High-Z -0.9µA (typical) I -400pA -400pA SS (typical) (typical) I CS 10pA (typical) FIGURE 1-1: Timing Diagram for the CS Pin on the MCP6033. DS20002041C-page 4  2007-2019 Microchip Technology Inc.

MCP6031/2/3/4 TEMPERATURE SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated: V = +1.8V to +5.5V and V = GND. DD SS Parameters Sym Min Typ Max Units Conditions Temperature Ranges Operating Temperature Range T -40 — +125 °C Note1 A Storage Temperature Range T -65 — +150 °C A Thermal Package Resistances Thermal Resistance, 5-Lead SOT-23  — 256 — °C/W JA Thermal Resistance, 8-Lead DFN  — 84 — °C/W JA Thermal Resistance, 8-Lead SOIC  — 163 — °C/W JA Thermal Resistance, 8-Lead MSOP  — 206 — °C/W JA Thermal Resistance, 14-Lead SOIC  — 120 — °C/W JA Thermal Resistance, 14-Lead TSSOP  — 100 — °C/W JA Note 1: The internal junction temperature (T ) must not exceed the absolute maximum specification of +150°C. J 1.1 Test Circuits The test circuits used for the DC and AC tests are shown in Figure1-2 and Figure1-3. The bypass V DD capacitors are laid out according to the rules discussed in Section4.6 “Supply Bypass”. 2.2µF VDD/2 0.1µF V + DD RN VOUT MCP603X 2.2µF VIN 0.1µF – CL RL + V RN MCP603X VOUT IN VL R R G F – CL RL V /2 FIGURE 1-3: AC and DC Test Circuit for DD V Most Inverting Gain Conditions. L R R G F FIGURE 1-2: AC and DC Test Circuit for Most Noninverting Gain Conditions.  2007-2019 Microchip Technology Inc. DS20002041C-page 5

MCP6031/2/3/4 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated: T = +25°C, V = +1.8V to +5.5V, V = GND, V = V /2, V V /2, A DD SS CM DD OUT DD V = V /2, R = 1Mto V , C = 60pF and CS is tied low. L DD L L L 400 14% e of Occurences110268%%%% 6VV4DC0DM =S= a3Vm.D0DpV/l3es set Voltage (μV)-1123000000000 TTTTAAAA ==== ++-+42810552°°°5CCC°C entag 4% ut Off-200 Perc 2% Inp--430000 VDD = 5.5V 0% 5 0 5 0 5 0 5 0 5 0 5 0 5 0 -150-120 -90 -60 -30 0 30 60 90 120 150 0. 0. 0. 1. 1. 2. 2. 3. 3. 4. 4. 5. 5. 6. - Input Offset Voltage (μV) Common Mode Input Voltage (V) FIGURE 2-1: Input Offset Voltage with FIGURE 2-4: Input Offset Voltage vs. V = 3.0V. Common-mode Input Voltage with V = 5.5V. DD DD 22% 400 Percentage of Occurences1111120246802468%%%%%%%%%% 6VVT4ADC 0DM= =S =- 4 a3V0m.D0°DpCV/l3 etos +85°C Input Offset Voltage (μV) ---1233210000000000000 VDD = 1.8V TTTTAAAA ==== +-++41280255°5°°CCC°C 0% -400 4 2 0 2 4 6 8 0 2 4 6 8 0 2 -20 -16 -12 -8 -4 0 4 8 12 16 20 0. 0. 0. 0. 0. 0. 0. 1. 1. 1. 1. 1. 2. 2. - - Input Offset Drift with Temperature (μV/°C) Common Mode Input Voltage (V) FIGURE 2-2: Input Offset Voltage Drift FIGURE 2-5: Input Offset Voltage vs. with V = 3.0V and T  +85°C. Common-mode Input Voltage with V = 1.8V. DD A DD 14% 250 Occurences11028%%% 6VVT4ADC 0DM= = S=+ a38Vm.5D0°DpVC/l3e tso +125°C oltage (μV) 11205050000 VDD = 3.0V VDD = 5.5V e of 6% et V -500 g s ercenta 24%% nput Off ---211050000 VDD = 1.8V P 0% I -250 -30 -24 -18 -12 -6 0 6 12 18 24 30 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Input Offset Drift with Temperature (μV/°C) Output Voltage (V) FIGURE 2-3: Input Offset Voltage Drift FIGURE 2-6: Input Offset Voltage vs. with V = 3.0V and T  +85°C. Output Voltage. DD A DS20002041C-page 6  2007-2019 Microchip Technology Inc.

MCP6031/2/3/4 Note: Unless otherwise indicated: T = +25°C, V = +1.8V to +5.5V, V = GND, V = V /2, V V /2, A DD SS CM DD OUT DD V = V /2, R = 1Mto V , C = 60pF and CS is tied low. L DD L L L 1,000 y 110 nsit 105 CMRR (VDD = 1.8V, CMRR (VDD = 5.5V, De B)100 VCM = -0.3V to 2.1V) VCM = -0.3V to 5.8V) e d 95 oise Voltag(nV/Hz) RR, CMRR ( 78895050 PSRR (VDD = 1.8V to 5.5V, VCM = VSS) N S ut P 70 p 65 n I 100 60 10E.-11 1E1+0 1E10+1 11E0+02 1E1k+3 11E0+k4 11E00+k5 -50 -25 0 25 50 75 100 125 Frequency (Hz) Ambient Temperature (°C) FIGURE 2-7: Input Noise Voltage Density FIGURE 2-10: Common-mode Rejection vs. Frequency. Ratio, Power Supply Rejection Ratio vs. Ambient Temperature. put Noise Voltage Density (nV/Hz)111120257025705050505 fV =DD 1 = k 5H.z5V Input Bias and Offset Currents (pA)10100100010000 VVDCDM == 5V.5DDVInput Bias Current In 0 1 Input Offset Current 5 0 5 0 5 0 5 0 5 0 5 0 5 0 -0. 0. 0. 1. 1. 2. 2. 3. 3. 4. 4. 5. 5. 6. 25 45 65 85 105 125 Common Mode Input Voltage (V) Ambient Temperature (°C) FIGURE 2-8: Input Noise Voltage Density FIGURE 2-11: Input Bias, Offset Currents vs. Common-mode Input Voltage. vs. Ambient Temperature. 100 90 PSRR- 10000 B) 80 pA) VDD = 5.5V R, PSRR (d 45670000 PSRR+ CMRR s Current ( 1000 TA = +125°C MR 30 Bia 100 C 20 ut 10 VDD = 5.5V Inp TA = +85°C 0 10 0.1 1 10 100 1000 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Frequency (Hz) Common Mode Input Voltage (V) FIGURE 2-9: Common-mode Rejection FIGURE 2-12: Input Bias Current vs. Ratio, Power Supply Rejection Ratio vs. Common-mode Input Voltage. Frequency.  2007-2019 Microchip Technology Inc. DS20002041C-page 7

MCP6031/2/3/4 Note: Unless otherwise indicated: T = +25°C, V = +1.8V to +5.5V, V = GND, V = V /2, V V /2, A DD SS CM DD OUT DD V = V /2, R = 1Mto V , C = 60pF and CS is tied low. L DD L L L 1.2 120 0 Quiescent Current (μA/Amplifier) 00000000011...........12345678901 VVDDDD == 51..58VV @@ VVCCMM == VVDDDDVVDDDD == 51..58VV @@ VVCCMM == VVSSSS Open-Loop Gain (V/V)102468000000 VDD = 5.5V Open-Loop GOaipnen-Loop Phase ------963111000852000 Open-Loop Phase (°) 0.0 -20 -210 -50 -25 0 25 50 75 100 125 0.000100..0011 0.1 1 10 100 110k0 1100k0110E0+k Ambient Temperature (°C) Frequency (Hz) 0 00 05 FIGURE 2-13: Quiescent Current vs FIGURE 2-16: Open-Loop Gain, Phase vs. Ambient Temperature. Frequency. 1.2 nt Current mplifier)000011......678901 VCM = VDD op Gain (dB) 111111011223505050 Quiesce(μA/A00000.....12345 TTTTAAAA ==== +++-41820255°5°°CCC°C DC Open-Lo 108990505 RVSLS = + 5 00. 2kVΩ < VOUT < VDD - 0.2V 0.0 80 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Power Supply Voltage (V) Power Supply Voltage V (V) DD FIGURE 2-14: Quiescent Current vs. FIGURE 2-17: DC Open-Loop Gain vs. Power Supply Voltage with V = V . Power Supply Voltage. CM DD 1.2 130 scent Current A/Amplifier) 00000011........45678901 VCM = VSS TA = +125°C en-Loop Gain (dB) 11111100112290505055 VDD = 5.5V VDD = 1.8V Quie(μ 000...123 TTTAAA === ++-482055°°°CCC DC Op 889050 RL = 50 kΩ Large Signal AOL 0.0 0.00 0.05 0.10 0.15 0.20 0.25 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 0. 0. 1. 1. 2. 2. 3. 3. 4. 4. 5. 5. 6. 6. 7. Output Voltage Headroom Power Supply Voltage (V) VDD - VOUT or VOUT - VSS (V) FIGURE 2-15: Quiescent Current vs. FIGURE 2-18: DC Open-Loop Gain vs. Power Supply Voltage with V = V . Output Voltage Headroom. CM SS DS20002041C-page 8  2007-2019 Microchip Technology Inc.

MCP6031/2/3/4 Note: Unless otherwise indicated: T = +25°C, V = +1.8V to +5.5V, V = GND, V = V /2, V V /2, A DD SS CM DD OUT DD V = V /2, R = 1Mto V , C = 60pF and CS is tied low. L DD L L L 130 20 90 Channel-to-Channel Seperation (dB)111012789000000 Input Referred Gain Bandwidth Product (kHz)11111024682468 GVGD a=Din =+ 1B1 a.V8n/VVdwidth Product Phase Margin 1234567800000000 Phase Margin (°) 60 0 0 100 1,000 10,000 -50 -25 0 25 50 75 100 125 Frequency (Hz) Ambient Temperature (°C) FIGURE 2-19: Channel-to-Channel FIGURE 2-22: Gain Bandwidth Product, Separation vs. Frequency ( MCP6032/4 only). Phase Margin vs. Ambient Temperature. 20 180 35 dwidth Product (kHz)11111024688 Gain Bandwidth Product Phase Margin 81111002460000 e Margin (°) Circuit Current mA)12235050 TTTTAAAA ==== +-++41280255°5°°CCC°C Gain Ban 246 VGD =D =+ 15 .V5/VV 246000 Phas ut Short (105 p 0 0 ut 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 O 0. 0. 0. 1. 1. 2. 2. 3. 3. 4. 4. 5. 5. 6. 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 - Common Mode Input Voltage (V) Power Supply Voltage (V) FIGURE 2-20: Gain Bandwidth Product, FIGURE 2-23: Ouput Short-Circuit Current Phase Margin vs. Common-mode Input Voltage. vs. Power Supply Voltage. 10 Product 11124680 Phase Margin 67890000 n (°) wing (V)P-P VDD = V5D.5DV = 3V.D0DV = 1.8V Gain Bandwidth (kHz) 11022468 VGGD =aD i=+n 1 5B .Va5/nVVdwidth Product 1234500000 Phase Margi Output Voltage S 1 0 0 0.1 -50 -25 0 25 50 75 100 125 10 100 110K00 10100K00 Ambient Temperature (°C) Frequency (Hz) FIGURE 2-21: Gain Bandwidth Product, FIGURE 2-24: Output Voltage Swing vs. Phase Margin vs. Ambient Temperature. Frequency.  2007-2019 Microchip Technology Inc. DS20002041C-page 9

MCP6031/2/3/4 Note: Unless otherwise indicated: T = +25°C, V = +1.8V to +5.5V, V = GND, V = V /2, V V /2, A DD SS CM DD OUT DD V = V /2, R = 1Mto V , C = 60pF and CS is tied low. L DD L L L 1000 ge Headroom - V (mV)OLSS 100 VOL -V VDSDS -@ VO VHD @D = V 1D.D8 =V 1.8V e (20 mV/div) aV g Output VoltV - V, DDOH 10 VOL - VSS @V VDDDD - =V O5H.5 @V VDD = 5.5V Output Volta VGD =D =+ 15 .V5/VV 1 10μ 100µ 1m 10m Output Current (A) Time (100 μs/Div) FIGURE 2-25: Output Voltage Headroom FIGURE 2-28: Small-Signal Noninverting vs. Output Current. Pulse Response. 5.0 ge HeadroomV - V (mV)SSOL 23344.....50505 VRDLD = = 5 50. 5kVΩ VDD - VOH ge (20 mV/div) VGD =D =-1 5 V.5/VV Output VoltaV - V or DDOH 0112....5050 VSS - VOL Output Volta 0.0 -50 -25 0 25 50 75 100 125 Ambient Temperature (°C) Time (100 μs/Div) FIGURE 2-26: Output Voltage Headroom FIGURE 2-29: Small-Signal Inverting Pulse vs. Ambient Temperature. Response. 7.0 5.5 6.0 FFaalllliinngg EEddggee,, VVDDDD == 51..58VV 45..50 V/ms)5.0 e (V) 34..50 Rate (4.0 Voltag 23..50 Slew 23..00 RRiissiinngg EEddggee,, VVDDDD == 51..58VV Output 112...050 VGD =D =+ 15 .V5/VV 1.0 0.5 -50 -25 0 25 50 75 100 125 0.0 Ambient Temperature (°C) Time (0.5 ms/div) FIGURE 2-27: Slew Rate vs. Ambient FIGURE 2-30: Large-Signal Noninverting Temperature. Pulse Response. DS20002041C-page 10  2007-2019 Microchip Technology Inc.

MCP6031/2/3/4 Note: Unless otherwise indicated: T = +25°C, V = +1.8V to +5.5V, V = GND, V = V /2, V V /2, A DD SS CM DD OUT DD V = V /2, R = 1Mto V , C = 60pF and CS is tied low. L DD L L L 5.5 4.0 V) V) 445...050 VGD =D =-1 5 V.5/VV uptut ( 33..05 Output On VDD = 5.5V ge ( 3.5 h O 2.5 Hysteresis olta 3.0 witc 2.0 V 2.5 S 1.5 CS Input CS Input put 2.0 CS 1.0 High to Low Low to High ut 1.5 al O n 0.5 1.0 er Output High-Z 0.5 nt 0.0 I 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Time (0.5 ms/div) Chip Select Voltage (V) FIGURE 2-31: Large-Signal Inverting Pulse FIGURE 2-34: Chip Select (CS) Hysteresis Response. (MCP6033 only) with V = 5.5V. DD 6.0 2.1 5.0 VIN VOUT 1.8 VDD = 3.0V ge (V) 4.0 age (V) 11..25 Output On Hysteresis utput Volta 123...000 Ouptut Volt 00..69 CHSig hIn tpou Lt ow CLoSw In tpou Ht igh O 0.3 0.0 VDD = 5.0V Output High-Z G = +2 V/V 0.0 -1.0 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 Time (2 ms/div) Chip Select Voltage (V) FIGURE 2-32: The MCP6031/2/3/4 Family FIGURE 2-35: Chip Select (CS) Hysteresis Shows No Phase Reversal. (MCP6033 only) with V = 3.0V. DD 6.0 7.0 1.5 V) 345...000 6.0 V)1.2 VDD = 1.8V hip Select Voltage ( -----54321012........00000000 VGRDL = D= =+ 5 150 .V 5k/VΩV to VCSSh ip SelectOutput On 2345....0000 Output Voltage (V) Ouptut Voltage (000...369 HOiCguShtp Itnuopt L uOotn w Hysteresis LoCwS tIon pHuigt h C -6.0 Output Output 1.0 Output High-Z -7.0 High-Z High-Z 0.0 -8.0 0.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 Time (1 ms/div) Chip Select Voltage (V) FIGURE 2-33: Chip Select (CS) to FIGURE 2-36: Chip Select (CS) Hysteresis Amplifier Output Response Time (MCP6033 (MCP6033 only) with V = 1.8V. DD only).  2007-2019 Microchip Technology Inc. DS20002041C-page 11

MCP6031/2/3/4 Note: Unless otherwise indicated: T = +25°C, V = +1.8V to +5.5V, V = GND, V = V /2, V V /2, A DD SS CM DD OUT DD V = V /2, R = 1Mto V , C = 60pF and CS is tied low. L DD L L L 100100000k 1.001E0-0m2 Closed Loop Output Impedance (Ω) 10101011000100110000k0k0 G1111 0NV 1:V/ VV/V/V -I (A)IN11111111........00000000 00000000111EEEEEEEE001011--------000010110000000mnpµnnµµ09876543 +++1282555°°°CCC -40°C 1.00E1-01p1 11 1.00E-11p2 11 1100 110000 1100k0 11000k00 1100000k00 -1.0-0.9-0.8-0.7-0.6-0.5-0.4-0.3-0.2-0.1 0.0 Frequency (Hz) VIN (V) FIGURE 2-37: Closed-Loop Output FIGURE 2-38: Measured Input Current vs. Impedance vs. Frequency. Input Voltage (below V ). SS DS20002041C-page 12  2007-2019 Microchip Technology Inc.

MCP6031/2/3/4 3.0 PIN DESCRIPTIONS Descriptions of the pins are listed in Table3-1. TABLE 3-1: PIN FUNCTION TABLE MCP6031 MCP6032 MCP6033 MCP6034 DFN, DFN, MSOP, SOIC, Symbol Description SOT-23 MSOP, MSOP, SOIC TSSOP SOIC SOIC 1 6 1 6 1 V , V Analog Output (Op Amp A) OUT OUTA 4 2 2 2 2 V -, V - Inverting Input (Op Amp A) IN INA 3 3 3 3 3 V +, V + Noninverting Input (Op Amp A) IN INA 5 7 8 7 4 V Positive Power Supply DD — — 5 — 5 V + Noninverting Input (Op Amp B) INB — — 6 — 6 V - Inverting Input (Op Amp B) INB — — 7 — 7 V Analog Output (Op Amp B) OUTB — — — — 8 V Analog Output (Op Amp C) OUTC — — — — 9 V - Inverting Input (Op Amp C) INC — — — — 10 V + Noninverting Input (Op Amp C) INC 2 4 4 4 11 V Negative Power Supply SS — — — — 12 V + Noninverting Input (Op Amp D) IND — — — — 13 V - Inverting Input (Op Amp D) IND — — — — 14 V Analog Output (Op Amp D) OUTD — — — 8 — CS Chip Select — 1, 5, 8 — 1, 5 — NC No Internal Connection 3.1 Analog Outputs 3.4 Power Supply Pins The output pins are low-impedance voltage sources. The positive power supply (V ) is 1.8V to 5.5V higher DD than the negative power supply (V ). For normal SS 3.2 Analog Inputs operation, the other pins are at voltages between VSS and V . DD The noninverting and inverting inputs are Typically, these parts are used in a single (positive) high-impedance CMOS inputs with low bias currents. supply configuration. In this case, V is connected to SS ground and V is connected to the supply. V will 3.3 Chip Select Digital Input DD DD need bypass capacitors. This is a CMOS, Schmitt-trigerred input that places the device into a Low-Power mode of operation.  2007-2019 Microchip Technology Inc. DS20002041C-page 13

MCP6031/2/3/4 4.0 APPLICATION INFORMATION V DD The MCP6031/2/3/4 family of op amps is manufactured using Microchip’s state-of-the-art CMOS process and is specifically designed for low-power, high-precision D D 1 2 applications. V1 + R 4.1 Rail-to-Rail Input 1 MCP603X 4.1.1 PHASE REVERASAL V2 – R 2 The MCP6031/2/3/4 op amps are designed to prevent phase reversal when the input pins exceed the supply R voltages. Figure2-32 shows the input voltage exceeding 3 the supply voltage without any phase reversal. VSS–(minimum expected V1) R > 1 2mA 4.1.2 INPUT VOLTAGE AND CURRENT V –(minimum expected V ) SS 2 LIMITS R2 > 2mA The ESD protection on the inputs can be depicted as FIGURE 4-2: Protecting the Analog Inputs. shown in Figure4-1. This structure was chosen to protect the input transistors and to minimize input bias It is also possible to connect the diodes to the left of the current (I ). The input ESD diodes clamp the inputs resistors, R and R . In this case, the currents through B 1 2 when they try to go more than one diode drop below the diodes, D1 and D2, need to be limited by some other V . They also clamp any voltage that goes too far mechanism. The resistors then serve as inrush current SS above V . Their breakdown voltage is high enough to limiters; the DC currents into the input pins (V + and DD IN allow normal operation and low enough to bypass ESD VIN-) should be very small. A significant amount of events within the specified limits. current can flow out of the inputs when the Common-mode voltage (V ) is below ground (V ). CM SS Bond 4.1.3 NORMAL OPERATION V DD Pad The input stage of the MCP6031/2/3/4 op amps uses two differential input stages in parallel. One operates at a low Common-mode input voltage (V ), while the CM V + Bond Input Bond V - other operates at a high VCM. With this topology, the IN Pad Stage Pad IN device operates with a VCM up to 300 mV above VDD and 300 mV below V . The input offset voltage is SS measured at V = V – 0.3V and V + 0.3V to CM SS DD ensure proper operation. Bond V SS Pad There are two transitions in input behavior as VCM is changed. The first occurs, when V is near V + 0.4V, CM SS FIGURE 4-1: Simplified Analog Input ESD and the second occurs when VCM is near VDD – 0.5V. For the best distortion performance with noninverting Structures. gains, avoid these regions of operation. In order to prevent damage and/or improper operation of these op amps, the circuit they are in must limit the voltages and currents at the V + and V - pins (see IN IN “Absolute Maximum Ratings†” at the beginning of Section1.0 “Electrical Characteristics”). Figure4-2 shows the recommended approach to protecting these inputs. The internal ESD diodes prevent the input pins (V + and V -) from going too far below ground, and IN IN the resistors, R and R , limit the possible current 1 2 drawn out of the input pins. Diodes, D and D , prevent 1 2 the input pins (V + and V -) from going too far above IN IN V . When implemented as shown, resistors, R and DD 1 R , also limit the current through D and D . 2 1 2 DS20002041C-page 14  2007-2019 Microchip Technology Inc.

MCP6031/2/3/4 4.2 Rail-to-Rail Output The output voltage range of the MCP6031/2/3/4 op amps is VSS + 10 mV (minimum) and VDD – 10 mV – RISO (maximum) when R = 50 k is connected to V /2 L DD MCP603X VOUT and V = 5.5V. Refer to Figures2-25 and2-26 for DD V + more information. IN CL 4.3 Output Loads and Battery Life FIGURE 4-3: Output Resistor, R , The MCP6031/2/3/4 op amp family has outstanding ISO Stabilizes Large Capacitive Loads. quiescent current, which supports battery-powered applications. There is minimal quiescent current glitch- Figure4-4 gives recommended R values for ISO ing when Chip Select (CS) is raised or lowered. This different capacitive loads and gains. The x-axis is the prevents excessive current draw and reduced battery normalized load capacitance (C /G ), where G is the L N N life when the part is turned off or on. circuit’s noise gain. For noninverting gains, G and the N Signal Gain are equal. For inverting gains, G is Heavy resistive loads at the output can cause exces- N 1+|Signal Gain| (e.g., -1V/V gives G = +2V/V). sive battery drain. Driving a DC voltage of 2.5V across N a 100 k load resistor will cause the supply current to increase by 25 µA, depleting the battery 28 times as 1000010M0 fast as I (0.9µA, typical) alone. Q Ω) High-frequency signals (fast edge rate) across capaci- (O S tive loads will also significantly increase supply current. RI 10100000k0 For instance, a 0.1 µF capacitor at the output presents ed d sainn eAwCa viem. pIet dcaannc eb eo f s1h5o.w9 nk th a(t1 /t2hef Ca)v etora ag e1 0p0o wHezr mmen 101000k0 G1 NV:/V 2 V/V drawn from the battery by a 5.0 Vp-p sinewave eco 5 V/V (1.77V ) under these conditions is R rms 1010k0 EQUATION 4-1: 1.1E0-p11 11.E00-1p0 1.E1-n09 11.E0-n08 11.0E0-0n7 1.1Eµ-06 Normalized Load Capacitance; C/G (F) L N P = (V – V ) (I + V fC ) Supply DD SS Q L(p-p) L FIGURE 4-4: Recommended R Values = (5V)(0.9 µA + 5.0 Vp-p · 100 Hz · 0.1 µF) for Capacitive Loads. ISO = 4.5 µW + 50 µW After selecting R for your circuit, double-check the ISO resulting frequency response peaking and step This will drain the battery about 12 times as fast as I Q response overshoot. Modify R ’s value until the alone. ISO response is reasonable. Bench evaluation and simula- 4.4 Capacitive Loads tions with the MCP6031/2/3/4 SPICE macro model are very helpful. Driving large capacitive loads can cause stability problems for voltage feedback op amps. As the load 4.5 MCP6033 Chip Select capacitance increases, the feedback loop’s phase margin decreases and the closed-loop bandwidth is The MCP6033 is a single op amp with Chip Select reduced. This produces gain peaking in the frequency (CS). When CS is pulled high, the supply current drops response, with overshoot and ringing in the step to 0.4 nA (typical) and flows through the CS pin to VSS. response. While a unity gain buffer (G = +1) is the most When this happens, the amplifier output is put into a sensitive to capacitive loads, all gains show the same high-impedance state. By pulling CS low, the amplifier general behavior. is enabled. If the CS pin is left floating, the amplifier will not operate properly. Figure1-1 shows the output When driving large capacitive loads with these voltage and supply current response to a CS pulse. opamps (e.g., >100 pF when G = +1), a small series resistor at the output (R in Figure4-3) improves the ISO feedback loop’s phase margin (stability) by making the output load resistive at higher frequencies. The bandwidth will be generally lower than the bandwidth with no capacitance load.  2007-2019 Microchip Technology Inc. DS20002041C-page 15

MCP6031/2/3/4 4.6 Supply Bypass With this family of operational amplifiers, the power Guard Ring V - V + V IN IN SS supply pin (V for single supply) should have a local DD bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm for good high-frequency performance. It can use a bulk capacitor (i.e., 1 µF or larger) within 100 mm to provide large, slow currents. This bulk capacitor can be shared with other analog parts. 4.7 Unused Op Amps FIGURE 4-6: Example Guard Ring Layout for Inverting Gain. An unused op amp in a quad package (MCP6034) should be configured as shown in Figure4-5. These 1. Noninverting Gain and Unity Gain Buffer: circuits prevent the output from toggling and causing a) Connect the noninverting pin (V +) to the crosstalk. Circuit A sets the op amp at its minimum IN input with a wire that does not touch the noise gain. The resistor divider produces any desired PCB surface. reference voltage within the output voltage range of the b) Connect the guard ring to the inverting input op amp; the op amp buffers that reference voltage. pin (V -). This biases the guard ring to the Circuit B uses the minimum number of components IN Common-mode input voltage. and operates as a comparator, but it may draw more current. 2. Inverting Gain and Transimpedance Gain Ampli- fiers (convert current to voltage, such as photo detectors): ¼ MCP6034 (A) ¼ MCP6034 (B) a) Connect the guard ring to the noninverting VDD VDD input pin (VIN+). This biases the guard ring to the same reference voltage as the op R VDD amp (e.g., VDD/2 or ground). 1 + b) Connect the inverting pin (V -) to the input + IN with a wire that does not touch the PCB V – R2 – REF surface. R V = V -----------2------- REF DD R +R 1 2 FIGURE 4-5: Unused Op Amps. 4.8 PCB Surface Leakage In applications where low input bias current is critical, Printed Circuit Board (PCB) surface leakage effects need to be considered. Surface leakage is caused by humidity, dust or other contamination on the board. Under low humidity conditions, a typical resistance between nearby traces is 1012. A 5V difference would cause 5 pA of current to flow, which is greater than the MCP6031/2/3/4 family’s bias current at +25°C (±1.0pA, typical). The easiest way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). The guard ring is biased at the same voltage as the sensitive pin. An example of this type of layout is shown in Figure4-6. DS20002041C-page 16  2007-2019 Microchip Technology Inc.

MCP6031/2/3/4 4.9 Application Circuits 4.9.2 PRECISION COMPARATOR Use high gain before a comparator to improve the latter’s 4.9.1 BATTERY CURRENT SENSING input offset performance. Figure4-8 shows a gain of The MCP6031/2/3/4 op amps’ Common-mode input 11V/V placed before a comparator. The reference range, which goes 0.3V beyond both supply rails, voltage, VREF, can be any value between the supply rails. supports their use in high-side and low-side battery current sensing applications. The ultra-low quiescent current (0.9 µA, typical) helps prolong battery life and VIN + the rail-to-rail output supports detection of low currents. MCP6031 – Figure4-7 shows a high-side battery current sensor circuit. The 10 resistor is sized to minimize power + losses. The battery current (IDD) through the 10 100k 1M MCP6541 VOUT resistor causes its top terminal to be more negative than VREF – the bottom terminal. This keeps the Common-mode input voltage of the op amp below V , which is within DD its allowed range. The output of the op amp will also be FIGURE 4-8: Precision, Noninverting below V , which is within its maximum output voltage Comparator. DD swing specification. 4.9.3 DRIVING MCP3421  A/D CONVERTER I DD VDD A RSH and CSH snubber reduces the output impedance 1.4V of the MCP6031 op amp, which reduces the gain error 10 to + caused by switching transients, which occur at the 5.5V VOUT MCP3421 ADC’s sampling rate. The snubber also MCP6031 100k maintains feedback stability, and avoids AC response – peaking and step response overshoot and ringing 1M (caused by the op amp’s inductive output impedance resonating with the ADC’s input capacitance). The cost for this improvement is low. Best of all, using an op amp V –V I = ----------D----D-------------O----U---T-------- with higher supply current is avoided (see Figure4-9). DD 10V/V10 This figure also includes a resistor to balance the impedance at the ADC’s inputs (R ) at the sampling BAL FIGURE 4-7: High-Side Battery Current frequency; it may not be needed in all designs. Sensor. MCP6031 ZIND MCP3421 VIN + 1.00k 2.25M +  – RSH – 1.00k R BAL C SH 1.00k 2.2µF FIGURE 4-9: Driving the MCP3421 Using an R-C Snubber.  2007-2019 Microchip Technology Inc. DS20002041C-page 17

MCP6031/2/3/4 5.0 DESIGN AIDS 5.5 Analog Demonstration and Evaluation Boards Microchip provides the basic design tools needed for the MCP6031/2/3/4 family of op amps. Microchip offers a broad spectrum of Analog Demon- stration and Evaluation Boards that are designed to 5.1 SPICE Macro Model help you achieve faster time to market. For a complete listing of these boards and their corresponding user’s The latest SPICE macro model for the MCP6031/2/3/4 guides and technical information, visit the Microchip op amps is available on the Microchip website at website at www.microchip.com/analogtools. www.microchip.com. This model is intended to be an Two of our boards that are especially useful are: initial design tool that works well in the op amp’s linear region of operation over the temperature range. See • P/N SOIC8EV: 8-Pin SOIC/MSOP/TSSOP/DIP the model file for information on its capabilities. Evaluation Board Bench testing is a very important part of any design and • P/N SOIC14EV: 14-Pin SOIC/TSSOP/DIP cannot be replaced with simulations. Also, simulation Evaluation Board results using this macro model need to be validated by comparing them to the data sheet specifications and 5.6 Application Notes characteristic curves. The following Microchip Analog Design Note and 5.2 FilterLab® Software Application Notes are available on the Microchip website at www.microchip.com/appnotes and are Microchip’s FilterLab® software is an innovative recommended as supplemental reference resources. software tool that simplifies analog active filter (using ADN003: “Select the Right Operational Amplifier for op amps) design. Available at no cost from the your Filtering Circuits”, DS21821 Microchip website at www.microchip.com/filterlab, the AN722: “Operational Amplifier Topologies and DC FilterLab design tool provides full schematic diagrams Specifications”, DS00722 of the filter circuit with component values. It also outputs the filter circuit in SPICE format, which can be AN723: “Operational Amplifier AC Specifications and used with the macro model to simulate actual filter Applications”, DS00723 performance. AN884: “Driving Capacitive Loads With Op Amps”, DS00884 5.3 Mindi™ Circuit Designer and AN990: “Analog Sensor Conditioning Circuits–An Simulator Overview”, DS00990 Microchip’s Mindi™ Circuit Designer and Simulator aids These application notes and others are listed in the in the design of various circuits useful for active filter, design guide: amplifier and power management applications. It is a “Signal Chain Design Guide”, DS21825 free online circuit designer and simulator available from the Microchip website at www.microchip.com/mindi. This interactive circuit designer and simulator enables designers to quickly generate circuit diagrams and simulate circuits. Circuits developed using the Mindi Circuit Designer and Simulator can be downloaded to a personal computer or workstation. 5.4 MAPS (Microchip Advanced Part Selector) MAPS is a software tool that helps semiconductor professionals efficiently identify Microchip devices that fit a particular design requirement. Available at no cost from the Microchip website at www.microchip.com/ maps, the MAPS is an overall selection tool for Microchip’s product portfolio that includes Analog, Memory, MCUs and DSCs. Using this tool you can define a filter to sort features for a parametric search of devices and export side-by-side technical comparison reports. Helpful links are also provided for Data Sheets, Purchase and Sampling of Microchip parts. DS20002041C-page 18  2007-2019 Microchip Technology Inc.

MCP6031/2/3/4 6.0 PACKAGING INFORMATION 6.1 Package Marking Information 5-Lead SOT-23 (MCP6031) Example: E-Temp Device XXNN Code EA25 MCP6031T-E/OT EANN 8-Lead 2x3 mm DFN (MCP6031 and MCP6033) Example: XXX ABV YWW 809 NN 25 8-Lead MSOP Example: XXXXXX 6031E YWWNNN 909256 8-Lead SOIC (3.90 mm) Example: XXXXXXXX MCP6033E XXXXYYWW SN^e^31909 NNN 256 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2007-2019 Microchip Technology Inc. DS20002041C-page 19

MCP6031/2/3/4 Package Marking Information (Continued) 14-Lead SOIC (3.90 mm) (MCP6034) Example: XXXXXXXXXX MCP6034 XXXXXXXXXX E/SLe3 YYWWNNN 1911256 14-Lead TSSOP (MCP6034) Example: XXXXXXXX 6034EST YYWW 1911 NNN 256 DS20002041C-page 20  2007-2019 Microchip Technology Inc.

MCP6031/2/3/4 5-Lead Plastic Small Outline Transistor (OT) [SOT23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 0.20 C 2X D e1 A D N E/2 E1/2 E1 E (DATUM D) (DATUM A-B) 0.15 C D 2X NOTE 1 1 2 e B NX b 0.20 C A-B D TOP VIEW A A2 A 0.20 C SEATING PLANE A SEE SHEET 2 A1 C SIDE VIEW Microchip Technology Drawing C04-091-OT Rev F Sheet 1 of 2  2007-2019 Microchip Technology Inc. DS20002041C-page 21

MCP6031/2/3/4 5-Lead Plastic Small Outline Transistor (OT) [SOT23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging c (cid:84) L L1 VIEW A-A SHEET 1 Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 5 Pitch e 0.95 BSC Outside lead pitch e1 1.90 BSC Overall Height A 0.90 - 1.45 Molded Package Thickness A2 0.89 - 1.30 Standoff A1 - - 0.15 Overall Width E 2.80 BSC Molded Package Width E1 1.60 BSC Overall Length D 2.90 BSC Foot Length L 0.30 - 0.60 Footprint L1 0.60 REF Foot Angle (cid:73) 0° - 10° Lead Thickness c 0.08 - 0.26 Lead Width b 0.20 - 0.51 Notes: 1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25mm per side. 2. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-091-OT Rev F Sheet 2 of 2 DS20002041C-page 22  2007-2019 Microchip Technology Inc.

MCP6031/2/3/4 5-Lead Plastic Small Outline Transistor (OT) [SOT23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging X SILK SCREEN 5 Y Z C G 1 2 E GX RECOMMENDED LAND PATTERN Units MILLIMETERS Dimension Limits MIN NOM MAX Contact Pitch E 0.95 BSC Contact Pad Spacing C 2.80 Contact Pad Width (X5) X 0.60 Contact Pad Length (X5) Y 1.10 Distance Between Pads G 1.70 Distance Between Pads GX 0.35 Overall Width Z 3.90 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-2091-OT Rev F  2007-2019 Microchip Technology Inc. DS20002041C-page 23

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MCP6031/2/3/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2007-2019 Microchip Technology Inc. DS20002041C-page 25

MCP6031/2/3/4 Note: For the mostcurrent package drawings,please seetheMicrochip Packaging Specification located at http://www.microchip.com/packaging DS20002041C-page 26  2007-2019 Microchip Technology Inc.

MCP6031/2/3/4 Note: For the mostcurrent package drawings,please seetheMicrochip Packaging Specification located at http://www.microchip.com/packaging  2007-2019 Microchip Technology Inc. DS20002041C-page 27

MCP6031/2/3/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20002041C-page 28  2007-2019 Microchip Technology Inc.

MCP6031/2/3/4 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2X 0.10 C A–B D A D NOTE 5 N E 2 E1 2 E1 E NOTE 1 1 2 e NX b B 0.25 C A–B D NOTE 5 TOP VIEW 0.10 C C A A2 SEATING PLANE 8X 0.10 C A1 SIDE VIEW h R0.13 h R0.13 H 0.23 L SEE VIEW C (L1) VIEW A–A VIEW C Microchip Technology Drawing No. C04-057-SN Rev E Sheet 1 of 2  2007-2019 Microchip Technology Inc. DS20002041C-page 29

MCP6031/2/3/4 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e 1.27 BSC Overall Height A - - 1.75 Molded Package Thickness A2 1.25 - - Standoff § A1 0.10 - 0.25 Overall Width E 6.00 BSC Molded Package Width E1 3.90 BSC Overall Length D 4.90 BSC Chamfer (Optional) h 0.25 - 0.50 Foot Length L 0.40 - 1.27 Footprint L1 1.04 REF Foot Angle 0° - 8° Lead Thickness c 0.17 - 0.25 Lead Width b 0.31 - 0.51 Mold Draft Angle Top 5° - 15° Mold Draft Angle Bottom 5° - 15° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. 5. Datums A & B to be determined at Datum H. Microchip Technology Drawing No. C04-057-SN Rev E Sheet 2 of 2 DS20002041C-page 30  2007-2019 Microchip Technology Inc.

MCP6031/2/3/4 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging SILK SCREEN C Y1 X1 E RECOMMENDED LAND PATTERN Units MILLIMETERS Dimension Limits MIN NOM MAX Contact Pitch E 1.27 BSC Contact Pad Spacing C 5.40 Contact Pad Width (X8) X1 0.60 Contact Pad Length (X8) Y1 1.55 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-2057-SN Rev E  2007-2019 Microchip Technology Inc. DS20002041C-page 31

MCP6031/2/3/4 14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2X 0.10 C A–B D A NOTE 5 D N E 2 E2 2 E1 E 2X 0.10 C D 2X N/2 TIPS NOTE 1 1 2 3 0.20 C e NX b B NOTE 5 0.25 C A–B D TOP VIEW 0.10 C C A A2 SEATING PLANE 14X A1 SIDE VIEW 0.10 C h h H R0.13 R0.13 c SEE VIEW C L VIEW A–A (L1) VIEW C Microchip Technology Drawing No. C04-065-SL Rev D Sheet 1 of 2 DS20002041C-page 32  2007-2019 Microchip Technology Inc.

MCP6031/2/3/4 14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 14 Pitch e 1.27 BSC Overall Height A - - 1.75 Molded Package Thickness A2 1.25 - - Standoff § A1 0.10 - 0.25 Overall Width E 6.00 BSC Molded Package Width E1 3.90 BSC Overall Length D 8.65 BSC Chamfer (Optional) h 0.25 - 0.50 Foot Length L 0.40 - 1.27 Footprint L1 1.04 REF Lead Angle 0° - - Foot Angle 0° - 8° Lead Thickness c 0.10 - 0.25 Lead Width b 0.31 - 0.51 Mold Draft Angle Top 5° - 15° Mold Draft Angle Bottom 5° - 15° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimension D does not include mold flash, protrusions or gate burrs, which shall not exceed 0.15 mm per end. Dimension E1 does not include interlead flash or protrusion, which shall not exceed 0.25 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. 5. Datums A & B to be determined at Datum H. Microchip Technology Drawing No. C04-065-SL Rev D Sheet 2 of 2  2007-2019 Microchip Technology Inc. DS20002041C-page 33

MCP6031/2/3/4 14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 14 SILK SCREEN C Y 1 2 X E RECOMMENDED LAND PATTERN Units MILLIMETERS Dimension Limits MIN NOM MAX Contact Pitch E 1.27 BSC Contact Pad Spacing C 5.40 Contact Pad Width (X14) X 0.60 Contact Pad Length (X14) Y 1.55 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-2065-SL Rev D DS20002041C-page 34  2007-2019 Microchip Technology Inc.

MCP6031/2/3/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2007-2019 Microchip Technology Inc. DS20002041C-page 35

MCP6031/2/3/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20002041C-page 36  2007-2019 Microchip Technology Inc.

MCP6031/2/3/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2007-2019 Microchip Technology Inc. DS20002041C-page 37

MCP6031/2/3/4 NOTES: DS20002041C-page 38  2007-2019 Microchip Technology Inc.

MCP6031/2/3/4 APPENDIX A: REVISION HISTORY Revision C (October 2019) The following is the list of modifications: 1. Updated Section6.0 “Packaging Information”. Revision B (March 2008) The following is the list of modifications: 1. Added SOT-23-5 and 2x3 DFN packages. 2. Added test circuits. 3. Corrected V temperature drift information. OS 4. Added Section 4.9.3. 5. Updated Package Marking Information. 6. Updated all package outline drawings and added package outline drawings for SOT-23-5 and 2x3 DFN packages. 7. Added Landing Pattern drawings for 2x3 DFN and 8-lead SOIC packages. 8. Updated information in Product Identification System for SOT-23-5 and 2x3 DFN packages. Revision A (March 2007) • Original Release of this Document.  2007-2019 Microchip Technology Inc. DS20002041C-page 39

MCP6031/2/3/4 NOTES: DS20002041C-page 40  2007-2019 Microchip Technology Inc.

MCP6031/2/3/4 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX Examples: a) MCP6031-E/SN: 8-Lead SOIC Package. Device Temperature Package b) MCP6031T-E/SN: Tape and Reel, Range 8-Lead SOIC Package. c) MCP6031-E/MS: 8-Lead MSOP Package. Device: MCP6031: Single Op Amp d) MCP6031T-E/MS: Tape and Reel, MCP6031T: Single Op Amp (Tape and Reel) 8-Lead MSOP Package. MCP6032: Dual Op Amp e) MCP6031-E/MC: 8-Lead DFN Package. MCP6032T: Dual Op Amp (Tape and Reel) MCP6033: Single Op Amp with Chip Select f) MCP6031T-E/MC: Tape and Reel, MCP6033T: Single Op Amp with Chip Select 8-Lead DFN Package. (Tape and Reel) g) MCP6031T-E/OT: Tape and Reel, MCP6034: Quad Op Amp MCP6034T: Quad Op Amp (Tape and Reel) 5-Lead SOT-23 Package. a) MCP6032-E/SN: 8-Lead SOIC Package. Temperature Range: E = -40°C to +125°C b) MCP6032T-E/SN: Tape and Reel, 8-Lead SOIC Package. Package: MC = Plastic Dual Flat, No Lead, (2x3 mm DFN) 8-Lead** c) MCP6032-E/MS: 8-Lead MSOP Package. MS = Plastic MSOP, 8-Lead OT = Plastic Small Outline Transistor (SOT-23), 5-Lead* d) MCP6032T-E/MS: Tape and Reel SL = Plastic SOIC (3.90 mm Body), 14-Lead 8-Lead MSOP Package. SN = Plastic SOIC, (3.90 mm Body), 8-Lead ST = Plastic TSSOP (4.4 mm Body), 14-Lead a) MCP6033-E/SN: 8-Lead SOIC Package. * This package is only available on the MCP6031 device. ** These packages are only available on the MCP6031 b) MCP6033T-E/SN: Tape and Reel, and MCP6033 devices. 8-Lead SOIC Package. c) MCP6033-E/MS: 8-Lead MSOP Package. d) MCP6033T-E/MS: Tape and Reel, 8-Lead MSOP Package. e) MCP6033-E/MC: 8-Lead DFN Package. f) MCP6033T-E/MC: Tape and Reel, 8-Lead DFN Package. a) MCP6034-E/SL: 14-Lead SOIC Package. b) MCP6034T-E/SL: Tape and Reel, 14-Lead SOIC Package. c) MCP6034-E/ST: 14-Lead TSSOP Package. d) MCP6034T-E/ST: Tape and Reel, 14-Lead TSSOP Package.  2007-2019 Microchip Technology Inc. DS20002041C-page 41

MCP6031/2/3/4 NOTES: DS20002041C-page 42  2007-2019 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, Adaptec, and may be superseded by updates. It is your responsibility to AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT, ensure that your application meets with your specifications. chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, MICROCHIP MAKES NO REPRESENTATIONS OR LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, WARRANTIES OF ANY KIND WHETHER EXPRESS OR Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, IMPLIED, WRITTEN OR ORAL, STATUTORY OR PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, OTHERWISE, RELATED TO THE INFORMATION, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, INCLUDING BUT NOT LIMITED TO ITS CONDITION, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA QUALITY, PERFORMANCE, MERCHANTABILITY OR are registered trademarks of Microchip Technology Incorporated in FITNESS FOR PURPOSE. Microchip disclaims all liability the U.S.A. and other countries. arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at APT, ClockWorks, The Embedded Control Solutions Company, the buyer’s risk, and the buyer agrees to defend, indemnify and EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision hold harmless Microchip from any and all damages, claims, Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, suits, or expenses resulting from such use. No licenses are SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, conveyed, implicitly or otherwise, under any Microchip TimePictra, TimeProvider, Vite, WinPath, and ZL are registered intellectual property rights unless otherwise stated. trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2007-2019, Microchip Technology Incorporated, All Rights Reserved. For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality. ISBN: 978-1-5224-5293-5  2007-2019 Microchip Technology Inc. DS20002041C-page 43

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