MCP6021/1R/2/3/4 Rail-to-Rail Input/Output, 10 MHz Op Amps Features Description • Rail-to-Rail Input/Output The MCP6021, MCP6021R, MCP6022, MCP6023 and • Wide Bandwidth: 10MHz (typical) MCP6024 from Microchip Technology Inc. are rail-to- rail input and output operational amplifiers with high • Low Noise: 8.7nV/Hz at 10kHz (typical) performance. Key specifications include: wide band- • Low Offset Voltage: width (10 MHz), low noise (8.7 nV/Hz), low input offset - Industrial Temperature: ±500µV (max.) voltage and low distortion (0.00053% THD+N). The - Extended Temperature: ±250µV (max.) MCP6023 also offers a Chip Select pin (CS) that gives • Mid-Supply V : MCP6021 and MCP6023 power savings when the part is not in use. REF • Low Supply Current: 1mA (typical) The single MCP6021 and MCP6021R are available in • Total Harmonic Distortion: SOT-23-5 packages. The single MCP6021, single - 0.00053% (typical, G = 1 V/V) MCP6023 and dual MCP6022 are available in 8-lead PDIP, SOIC and TSSOP packages. The Extended • Unity Gain Stable Temperature single MCP6021 is available in 8-lead • Power Supply Range: 2.5V to 5.5V MSOP. The quad MCP6024 is offered in 14-lead PDIP, • Temperature Range: SOIC and TSSOP packages. - Industrial: -40°C to +85°C The MCP6021/1R/2/3/4 family is available in Industrial - Extended: -40°C to +125°C and Extended temperature ranges. It has a power supply range of 2.5V to 5.5V. Applications Package Types • Automotive • Multi-Pole Active Filters MCP6021 MCP6022 SOT-23-5 PDIP, SOIC, TSSOP • Audio Processing • DAC Buffer VOUT 1 5 VDD VOUTA 1 8 VDD • Test Equipment VSS 2 VINA- 2 7 VOUTB • Medical Instrumentation VIN+ 3 4 VIN- VINA+ 3 6 VINB- VSS 4 5 VINB+ Design Aids MCP6021R SOT-23-5 MCP6023 • SPICE Macro Models PDIP, SOIC, TSSOP • FilterLab® Software VOUT 1 5 VSS • MPLAB® Mindi™ Analog Simulator VDD 2 NC 1 8 CS • Microchip Advanced Part Selector (MAPS) VIN+ 3 4 VIN- VIN- 2 7 VDD • Analog Demonstration and Evaluation Boards VIN+ 3 6 VOUT MCP6021 • Application Notes VSS 4 5 VREF PDIP, SOIC, MSOP, TSSOP MCP6024 Typical Application PDIP, SOIC, TSSOP NC 1 8 NC 5.6pF DPehteocttoor VIN- 2 7 VDD VOUTA 1 14VOUTD 100k VIN+ 3 6 VOUT VINA- 2 13VIND- VSS 4 5 VREF VINA+ 3 12VIND+ 100pF VDD 4 11VSS MCP6021 VINB+ 5 10VINC+ VDD/2 VINB- 6 9 VINC- Transimpedance Amplifier VOUTB 7 8 VOUTC  2001-2017 Microchip Technology Inc. DS20001685E-page 1

MCP6021/1R/2/3/4 NOTES: DS20001685E-page 2  2001-2017 Microchip Technology Inc.

MCP6021/1R/2/3/4 1.0 ELECTRICAL † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the CHARACTERISTICS device. This is a stress rating only and functional operation of the device at those or any other conditions above those Absolute Maximum Ratings† indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended V –V ........................................................................7.0V DD SS periods may affect device reliability. Current Analog Input Pins (V +, V -)..........................±2mA IN IN Analog Inputs (V +, V -)††.........V –1.0V to V +1.0V †† See Section4.1.2, Input Voltage Limits. IN IN SS DD All Other Inputs and Outputs..........V –0.3V to V +0.3V SS DD Difference Input Voltage ......................................|V –V | DD SS Output Short-Circuit Current ................................Continuous Current at Output and Supply Pins ............................±30mA Storage Temperature....................................-65°C to +150°C Maximum Junction Temperature.................................+150°C ESD Protection on All Pins (HBM;MM)2kV;200V DC ELECTRICAL CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, T = +25°C, V = +2.5V to +5.5V, V = GND, V = V /2, V V /2 A DD SS CM DD OUT DD and R =10kto V /2. L DD Parameters Sym. Min. Typ. Max. Units Conditions Input Offset Input Offset Voltage: Industrial Temperature Parts V -500 — +500 µV V = 0V OS CM Extended Temperature Parts V -250 — +250 µV V = 0V, V = 5.0V OS CM DD Extended Temperature Parts V -2.5 — +2.5 mV V = 0V, V = 5.0V, OS CM DD T = -40°C to +125°C A Input Offset Voltage Temperature Drift V /T — ±3.5 — µV/°C T = -40°C to +125°C OS A A Power Supply Rejection Ratio PSRR 74 90 — dB V = 0V CM Input Current and Impedance Input Bias Current: I — 1 — pA B Industrial Temperature Parts I — 30 150 pA T = +85°C B A Extended Temperature Parts I — 640 5,000 pA T = +125°C B A Input Offset Current I — ±1 — pA OS Common-Mode Input Impedance Z — 1013||6 — ||pF CM Differential Input Impedance Z — 1013||3 — ||pF DIFF Common-Mode Common-Mode Input Range V V – 0.3 — V + 0.3 V CMR SS DD Common-Mode Rejection Ratio CMRR 74 90 — dB V = 5V, V = -0.3V to 5.3V DD CM CMRR 70 85 — dB V = 5V, V = 3.0V to 5.3V DD CM CMRR 74 90 — dB V = 5V, V = -0.3V to 3.0V DD CM Voltage Reference (MCP6021 and MCP6023 only) V Accuracy (V –V /2) V -50 — +50 mV REF REF DD REF_ACC V Temperature Drift V /T — ±100 — µV/°C T = -40°C to +125°C REF REF A A Open-Loop Gain DC Open-Loop Gain (Large Signal) A 90 110 — dB V = 0V, OL CM V = V + 0.3V to V – 0.3V OUT SS DD Output Maximum Output Voltage Swing V , V V + 15 — V – 20 mV 0.5V input overdrive OL OH SS DD Output Short Circuit Current I — ±30 — mA V = 2.5V SC DD I — ±22 — mA V = 5.5V SC DD Power Supply Supply Voltage V 2.5 — 5.5 V DD Quiescent Current per Amplifier I 0.5 1.0 1.35 mA I = 0 Q O  2001-2017 Microchip Technology Inc. DS20001685E-page 3

MCP6021/1R/2/3/4 AC ELECTRICAL CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, T = +25°C, V = +2.5V to +5.5V, V = GND, V = V /2, V V /2, A DD SS CM DD OUT DD R =10kto V /2 and C = 60 pF. L DD L Parameters Sym. Min. Typ. Max. Units Conditions AC Response Gain Bandwidth Product GBWP — 10 — MHz Phase Margin PM — 65 — ° G = +1V/V Settling Time, 0.2% t — 250 — ns G = +1V/V, V = 100mV SETTLE OUT p-p Slew Rate SR — 7.0 — V/µs Total Harmonic Distortion Plus Noise f = 1kHz, G = +1 V/V THD + N — 0.00053 — % V = 0.25V to 3.25V (1.75V ± 1.50V ), OUT PK V = 5.0V, BW = 22kHz DD f = 1kHz, G = +1 V/V, R = 600 THD + N — 0.00064 — % V = 0.25V to 3.25V (1.75V ± 1.50V ), L OUT PK V = 5.0V, BW = 22kHz DD f = 1kHz, G = +1V/V THD + N — 0.0014 — % V = 4V , V = 5.0V, BW = 22kHz OUT P-P DD f = 1kHz, G = +10V/V THD + N — 0.0009 — % V = 4V , V = 5.0V, BW = 22kHz OUT P-P DD f = 1kHz, G = +100V/V THD + N — 0.005 — % V = 4V , V = 5.0V, BW = 22kHz OUT P-P DD Noise Input Noise Voltage E — 2.9 — µVp-p f = 0.1 Hz to 10 Hz ni Input Noise Voltage Density e — 8.7 — nV/Hz f = 10 kHz ni Input Noise Current Density i — 3 — fA/Hz f = 1 kHz ni MCP6023 CHIP SELECT (CS) ELECTRICAL CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, T = +25°C, V = +2.5V to +5.5V, V = GND, V = V /2, A DD SS CM DD V V /2, R =10kto V /2 and C = 60 pF. OUT DD L DD L Parameters Sym. Min. Typ. Max. Units Conditions CS Low Specifications CS Logic Threshold, Low V V — 0.2V V IL SS DD CS Input Current, Low I -1.0 0.01 — µA CS = V CSL SS CS High Specifications CS Logic Threshold, High V 0.8V — V V IH DD DD CS Input Current, High I — 0.01 2.0 µA CS = V CSH DD GND Current I -2 -0.05 — µA CS = V SS DD Amplifier Output Leakage I — 0.01 — µA CS = V O(LEAK) DD CS Dynamic Specifications CS Low to Amplifier Output Turn-on Time t — 2 10 µs G = +1, V = V , ON IN SS CS = 0.2 V to V = 0.45 V time DD OUT DD CS High to Amplifier Output High-Z Time t — 0.01 — µs G = +1, V = V , OFF IN SS CS = 0.8 V to V = 0.05 V time DD OUT DD Hysteresis V — 0.6 — V V = 5.0V, internal switch HYST DD DS20001685E-page 4  2001-2017 Microchip Technology Inc.

MCP6021/1R/2/3/4 TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, V = +2.5V to +5.5V and V = GND. DD SS Parameters Sym. Min. Typ. Max. Units Conditions Temperature Ranges Industrial Temperature Range T -40 — +85 °C A Extended Temperature Range T -40 — +125 °C A Operating Temperature Range T -40 — +125 °C (Note1) A Storage Temperature Range T -65 — +150 °C A Thermal Package Resistances Thermal Resistance, 5L-SOT-23  — 256 — °C/W JA Thermal Resistance, 8L-PDIP  — 85 — °C/W JA Thermal Resistance, 8L-SOIC  — 163 — °C/W JA Thermal Resistance, 8L-MSOP  — 206 — °C/W JA Thermal Resistance, 8L-TSSOP  — 124 — °C/W JA Thermal Resistance, 14L-PDIP  — 70 — °C/W JA Thermal Resistance, 14L-SOIC  — 120 — °C/W JA Thermal Resistance, 14L-TSSOP  — 100 — °C/W JA Note 1: The industrial temperature devices operate over this Extended temperature range, but with reduced performance. In any case, the internal Junction Temperature (T ) must not exceed the absolute maximum specification of +150°C. J 1.1 Test Circuits CS The test circuits used for the DC and AC tests are shown in Figure1-2 and Figure1-3. The bypass t t ON OFF capacitors are laid out according to the rules discussed in Section4.7 “Supply Bypass”. V High-Z Amplifier On High-Z OUT -1 mA VDD 1µF ISS -50nA (typical) -50nA VIN RN 0.1µF (typical) (typical) 1k(cid:58) CB1CB2 VOUT ICS MCP6021 10nA 10nA 10nA (typical) (typical) (typical) CL RL 60pF 10k(cid:58) VDD/2 RG RF FIGURE 1-1: Timing Diagram for the CS VL 2k(cid:58) 2k(cid:58) Pin on the MCP6023. FIGURE 1-2: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. VDD 1µF VDD/2 RN 0.1µF 1k(cid:58) CB1CB2 VOUT MCP6021 CL RL 60pF 10k(cid:58) VIN RG RF V L 2k(cid:58) 2k(cid:58) FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions.  2001-2017 Microchip Technology Inc. DS20001685E-page 5

MCP6021/1R/2/3/4 NOTES: DS20001685E-page 6  2001-2017 Microchip Technology Inc.

MCP6021/1R/2/3/4 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, T = +25°C, V =+2.5V to +5.5V, V = GND, V = V /2, V  V /2, A DD SS CM DD OUT DD R =10ktoV /2 and C =60 pF. L DD L 16% s I-Temp 1192 Samples 24% Occurance111024%%% Parts TVACM= =+ 205V°C curances 1112246802%%%%% I-PTaermtsp 1VT1AC9M=2= -S 400aV°mCp tloe s+85°C of 8% Oc 12% centage 246%%% ntage of 14680%%%% er ce 2% P 0% er 0% 00 00 00 00 00 0 00 00 00 00 00 P 20 16 12 -8 -4 0 4 8 12 16 20 5 4 3 2 1 1 2 3 4 5 - - - - - -Inp-ut O-ffset Voltage (µV) Input Offset Voltage Drift (µV/°C) FIGURE 2-1: Input Offset Voltage FIGURE 2-4: Input Offset Voltage Drift (Industrial Temperature Parts). (Industrial Temperature Parts). 24% ccurances111222468024%%%%%% EP-Taermtsp TV4V3ADC8DM= =S =+ a520m.5V0°pVCle s Occurances1112246802%%%%% EP-Taermtsp T4V3AC8M= S=- 4a00mV°pCl etos +125°C e of O1102%% ge of 1102%% g 8% a 8% nta 6% ent 6% erce 24%% Perc 24%% P 0% 0% 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 6 2 8 4 4 8 2 6 0 4 0 6 2 8 4 0 4 8 2 6 0 2 2 1 1 - - 1 1 2 2 2 1 1 - - 1 1 2 - - - -Input Offset Voltage (µV) - -Inpu-t Offset Voltage Drift (µV/°C) FIGURE 2-2: Input Offset Voltage FIGURE 2-5: Input Offset Voltage Drift (Extended Temperature Parts). (Extended Temperature Parts). 500 500 Input Offset Voltage (µV) ----4321123400000000000000000 VDD= 2.5V -+++41280255°5°°CCC°C Input Offset Voltage (µV)-----5432112340000000000000000000 VDD= 5.5V -+++42810552°°°5CCC°C -500 5 0 5 0 5 0 5 0 5 0 5 0 5 0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0. 0. 0. 1. 1. 2. 2. 3. 3. 4. 4. 5. 5. 6. Common Mode Input Voltage (V) - Common Mode Input Voltage (V) FIGURE 2-3: Input Offset Voltage vs. FIGURE 2-6: Input Offset Voltage vs. Common-Mode Input Voltage with V = 2.5V. Common-Mode Input Voltage with V = 5.5V. DD DD  2001-2017 Microchip Technology Inc. DS20001685E-page 7

MCP6021/1R/2/3/4 Note: Unless otherwise indicated, T = +25°C, V =+2.5V to +5.5V, V = GND, V = V /2, V  V /2, A DD SS CM DD OUT DD R =10ktoV /2 and C =60 pF. L DD L 100 200 V) 50 V)150 VCM= VDD/2 µ µ e ( 0 e (100 g g olta -50 olta 50 VDD= 5.5V et V-100 et V 0 Offs-150 Offs -50 VDD= 2.5V ut -200 ut -100 p V = 5.0V p In-250 VDCDM= 0V In-150 -300 -200 -50 -25 0 25 50 75 100 125 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Ambient Temperature (°C) Output Voltage (V) FIGURE 2-7: Input Offset Voltage vs. FIGURE 2-10: Input Offset Voltage vs. Temperature. Output Voltage. 1,000 24 nsity nsity 2202 VDD= 5.0V De De 18 e 100 e 16 oltag√Hz) oltag√Hz) 1124 f = 1 kHz se V(nV/ se V(nV/ 108 oi 10 oi 6 f = 10 kHz ut N ut N 24 p p n n 0 I I 5 0 5 0 5 0 5 0 5 0 5 0 5 1 0. 0. 0. 1. 1. 2. 2. 3. 3. 4. 4. 5. 5. 01.E.-011 1.E1+00 11.E+001 11.0E+020 11.E+0k3 11.0E+04k 101.E+050k 11.E+M06 - Common Mode Input Voltage (V) Frequency (Hz) FIGURE 2-8: Input Noise Voltage Density FIGURE 2-11: Input Noise Voltage Density vs. Frequency. vs. Common-Mode Input Voltage. 110 100 PSRR+ 105 90 PSRR- PSRR (dB) 678000 CMRR (dB)1990050 CMRR RR, 50 CMRR RR, 85 PSRR (VCM= 0V) CM 40 PS 80 30 75 20 70 101.E+020 11.E+k03 101.E+04k 101.E+005k 11M.E+06 -50 -25 0 25 50 75 100 125 Frequency (Hz) Ambient Temperature (°C) FIGURE 2-9: CMRR, PSRR vs. FIGURE 2-12: CMRR, PSRR vs. Frequency. Temperature. DS20001685E-page 8  2001-2017 Microchip Technology Inc.

MCP6021/1R/2/3/4 Note: Unless otherwise indicated, T = +25°C, V =+2.5V to +5.5V, V = GND, V = V /2, V  V /2, A DD SS CM DD OUT DD R =10ktoV /2 and C =60 pF. L DD L nput Bias, Offset Currents (pA)110,,01001000000 VDD= 5.5V IIIBIOBO,S, S T,T, ATTAA=A= = =++ 1++8215852°5°5C°C°CC Bias, Offset Currents (pA)110,,01001000000 VVCDMD== 5V.D5DV IB IOS I ut 10.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Inp 1 25 35 45 55 65 75 85 95 105 115 125 Common Mode Input Voltage (V) Ambient Temperature (°C) FIGURE 2-13: Input Bias, Offset Currents FIGURE 2-16: Input Bias, Offset Currents vs. Common-Mode Input Voltage. vs. Temperature. 1.2 1.2 1.1 1.1 1.0 V = 5.5V Quiescent Current (mA/amplifier)00000001........34567890 +++-41820255°5°°CCC°C Quiescent Current (mA/amplifier)0000000.......3456789 DD VDD= 2.5V 0.2 0.2 0.1 0.1 V = V -0.5V CM DD 0.0 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -50 -25 0 25 50 75 100 125 Power Supply Voltage (V) Ambient Temperature (°C) FIGURE 2-14: Quiescent Current vs. FIGURE 2-17: Quiescent Current vs. Supply Voltage. Temperature. 35 120 0 110 -15 ShortCircuit Current(cid:16)(mA)1122305050 +++1282555°°°CCC en-Loop Gain (dB)1234567890000000000 Gain Phase ---------1111976435320050500505pen-Loop Phase (°) ut -40°C Op 10 -165O p 5 0 -180 Out -10 -195 0 -20 -210 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 11.E+00 11.E0+01 101.E+002 11.Ek+03 101.E+0k4 101.E0+05k 11M.E+06 101.E+0M7 101.E0+08M Supply Voltage (V) Frequency (Hz) FIGURE 2-15: Output Short-Circuit Current FIGURE 2-18: Open-Loop Gain, Phase vs. vs. Supply Voltage. Frequency.  2001-2017 Microchip Technology Inc. DS20001685E-page 9

MCP6021/1R/2/3/4 Note: Unless otherwise indicated, T = +25°C, V =+2.5V to +5.5V, V = GND, V = V /2, V  V /2, A DD SS CM DD OUT DD R =10ktoV /2 and C =60 pF. L DD L 130 120 n-Loop Gain (dB) 111012000 VDVDD=D 5=. 52V.5V en-Loop Gain (dB)111100110505 VDD= 2.5V VDD= 5.5V e p p O C O 90 DC 95 D 80110.E+020 11.E+k03 11.E0+04k 101.E+050k 90 Load Resistance (ΩΩ) -50 -25 0 25 50 75 100 125 Ambient Temperature (°C) FIGURE 2-19: DC Open-Loop Gain vs. FIGURE 2-22: DC Open-Loop Gain vs. Load Resistance. Temperature. 120 14 105 Loop Gain (dB)110100 VCM= VDD/2 VDD= 5.5V Product (MHz) 11028 Gain Bandwidth Product 679050 gin, G = +1 (°) n- 90 h 6 Phase Margin, G = +1 45 ar C Ope 80 VDD= 2.5V dwidt 4 30 ase M D 70 n Ban 2 VDD= 5.0V 15 Ph 0.00 0.05 0.10 0.15 0.20 0.25 0.30 ai 0 0 G Output Voltage Headroom (V); 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 V - V or V - V Common Mode Input Voltage (V) DD OH OL SS FIGURE 2-20: Small Signal DC Open-Loop FIGURE 2-23: Gain Bandwidth Product, Gain vs. Output Voltage Headroom. Phase Margin vs. Common-Mode Input Voltage. 10 100 14 105 Gain Bandwidth Product (MHz) 0123456789-50GGPPMMBBWW,,- 2VVPP5DD,,DD VV==DD DD52..==055 VV52..55VV25 50 75 100 1250123456789000000000 Phase Margin, G = +1 (°) Gain Bandwidth Product (MHz) 1102024680.0VVDC0DM.==5 5VG.1D0aD.Vi0/n2 B1a.n5dw2i.d0th2 PP.hr5oads3ue.c 0Mta3rg.5in,4 G.0 = 4+.15 5.00134679505050 Phase Margin, G = +1 (°) Ambient Temperature (°C) Output Voltage (V) FIGURE 2-21: Gain Bandwidth Product, FIGURE 2-24: Gain Bandwidth Product, Phase Margin vs. Temperature. Phase Margin vs. Output Voltage. DS20001685E-page 10  2001-2017 Microchip Technology Inc.

MCP6021/1R/2/3/4 Note: Unless otherwise indicated, T = +25°C, V =+2.5V to +5.5V, V = GND, V = V /2, V  V /2, A DD SS CM DD OUT DD R =10ktoV /2 and C =60 pF. L DD L 11 10 e (V/µs)106789 RFaislliinngg,, VVDDDD== 55..55VV put Voltage V)P-P VVDDDD== 52..55VV Slew Rat 345 RFaislliinngg,, VVDDDD== 22..55VV mum OutSwing ( 1 2 xi a 1 M 0 -50 -25 0 25 50 75 100 125 0.1101.E+0k4 101.E0+05k 11.ME+06 10M1.E+07 Ambient Temperature (°C) Frequency (Hz) FIGURE 2-25: Slew Rate vs. Temperature. FIGURE 2-28: Maximum Output Voltage Swing vs. Frequency. 0.1000% 0.1000% f = 1 kHz G = +100 V/V BW = 22 kHz Meas V = 5.0V DD %)0.0100% G = +100 V/V %)0.0100% G = +10 V/V N ( N ( D+ D+ TH0.0010% G = +10 V/V TH0.0010% G = +1 V/V f = 20 kHz BW = 80 kHz Meas V = 5.0V G = +1 V/V DD 0.0001% 0.0001% 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Output Voltage (V ) Output Voltage (V ) P-P P-P FIGURE 2-26: Total Harmonic Distortion FIGURE 2-29: Total Harmonic Distortion plus Noise vs. Output Voltage with f = 1kHz. plus Noise vs. Output Voltage with f = 20kHz. 6 utput Voltage (V) 2345 VIN VOUT GVD =D +=2 5 V.0/VV ChannelSeparation(dB)111122330505 Input, O 01 annel-to- 111105 G = +1 V/V h C 105 -1 11.E+0k3 11.0E+04k 101.E+005k 11.E+M06 0 10 20 T3i0me (4100 µs5/0div)60 70 80 90 100 Frequency (Hz) FIGURE 2-27: The MCP6021/1R/2/3/4 FIGURE 2-30: Channel-to-Channel Family Shows No Phase Reversal Under Separation vs. Frequency (MCP6022 and Overdrive. MCP6024 only).  2001-2017 Microchip Technology Inc. DS20001685E-page 11

MCP6021/1R/2/3/4 Note: Unless otherwise indicated, T = +25°C, V =+2.5V to +5.5V, V = GND, V = V /2, V  V /2, A DD SS CM DD OUT DD R =10ktoV /2 and C =60 pF. L DD L 1,000 10 Output Voltage Headroom;V – Vor V – V(mV)DDOHOLSS 11000 VOL – VSS VDD – VOH Output Voltage HeadroomV – Vor V – V(mV)DDOHOLSS 123456789 VVODL D– – V VSSOH 1 0 0.01 0.1 1 10 -50 -25 0 25 50 75 100 125 Output Current Magnitude (mA) Ambient Temperature (°C) FIGURE 2-31: Output Voltage Headroom FIGURE 2-34: Output Voltage Headroom vs. Output Current. vs. Temperature. 6.E-02 G = +1 V/V 6.E-02 G = -1 V/V v)5.E-02 v)5.E-02 RF= 1 kΩ di4.E-02 di4.E-02 mV/3.E-02 mV/3.E-02 0 2.E-02 0 2.E-02 e (11.E-02 e (11.E-02 ag0.E+00 ag0.E+00 olt-1.E-02 olt-1.E-02 utput V--32..EE--0022 utput V---432...EEE---000222 O-4.E-02 O -5.E-02 -5.E-02 -6.E-002.E+00 2.E-07 4.E-07 T6.iE-07me (28.E-0700 ns1.E-0/6div)1.E-06 1.E-06 2.E-06 2.E-06 2.E-06 -6.E-002.E+00 2.E-07 4.E-07 6.E-0T7ime8 .E-0(7200 1.nE-06s/div1.E-06) 1.E-06 2.E-06 2.E-06 2.E-06 FIGURE 2-32: Small Signal Non-Inverting FIGURE 2-35: Small Signal Inverting Pulse Pulse Response. Response. 5.0 5.0 G = +1 V/V G = -1 V/V 4.5 4.5 R = 1 kΩ F V) 4.0 V) 4.0 Voltage ( 233...505 Voltage ( 233...505 put 2.0 put 2.0 Out 1.5 Out 1.5 1.0 1.0 0.5 0.5 0.0 0.0 0.E+00 5.E-07 1.E-06 Tim2.E-06e (52.E0-060 ns3.E-0/6div)3.E-06 4.E-06 4.E-06 5.E-06 5.E-06 0.E+00 5.E-07 1.E-06 2.E-0T6 ime2.E-0 6(5003.E- 06ns/d3.E-i06v) 4.E-06 4.E-06 5.E-06 5.E-06 FIGURE 2-33: Large Signal Non-Inverting FIGURE 2-36: Large Signal Inverting Pulse Pulse Response. Response. DS20001685E-page 12  2001-2017 Microchip Technology Inc.

MCP6021/1R/2/3/4 Note: Unless otherwise indicated, T = +25°C, V =+2.5V to +5.5V, V = GND, V = V /2, V  V /2, A DD SS CM DD OUT DD R =10ktoV /2 and C =60 pF. L DD L 50 50 40 40 Representative Part Accuracy;V/2 (mV)DD 1230000 Accuracy;V/2 (mV)DD 1230000 VDD= 5.5V VREFV–REF --2100 VREFV–REF --2100 VDD= 2.5V -30 -30 -40 -40 -50 -50 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -50 -25 0 25 50 75 100 125 Power Supply Voltage (V) Ambient Temperature (°C) FIGURE 2-37: V Accuracy vs. Supply FIGURE 2-40: V Accuracy vs. REF REF Voltage (MCP6021 and MCP6023 only). Temperature (MCP6021 and MCP6023 only). 1.6 1.6 Quiescent Current (mA/amplifier) 0000111.......2468024 GVVOtD u=DpChr= n= +iSA gs1 12 hm .s o2.V 5wtp5n/oVVeV hploetwre HysClOstoehSwpru e s Attswsomi seohppfifgt hhere Quiescent Current (mA/amplifier) 000111......468024 OtGVuDp r=Dn A =s+m 1o5 p.Vn5 /VhChVeiSgr hes wtoe plotw HyClsotSwe rs Osetwohsp uie hsAtpisgmt hopff here IN 0.2 V = 2.75V 0.0 IN 0.0 0.5 1.0 1.5 2.0 2.5 0.0 Chip Select Voltage (V) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Chip Select Voltage (V) FIGURE 2-38: Chip Select (CS) Hysteresis FIGURE 2-41: Chip Select (CS) Hysteresis (MCP6023 only) with V = 2.5V. (MCP6023 only) with V = 5.5V. DD DD 5.5 5.0 VDD= 5.0V 1.E1-00m2 4.5 CS Voltage G = +1 V/V A)1.E-10m3 ge,V) 4.0 VIN= VSS de (1.1E0-004µ Chip Select VoltaOutput Voltage ( 0112233.......5050505 Ouotnput OutpuVt HOUiTgh-Z Ouotnput ut Current Magnitu111111......11EEEEEE1001------100000100010098765nnnpµµ +++1282555°°°CCC 0.0 np1.E1-101p -40°C -0.5 0.0E+00 5.0E-06 Ti1m.0E-05e (5 µ1.5Es-05/div)2.0E-05 2.5E-05 3.0E-05 3.5E-05 I1.E-112p -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 Input Voltage (V) FIGURE 2-39: Chip Select (CS) to FIGURE 2-42: Measured Input Current vs. Amplifier Output Response Time (MCP6023 Input Voltage (Below V ) Only). SS  2001-2017 Microchip Technology Inc. DS20001685E-page 13

MCP6021/1R/2/3/4 NOTES: DS20001685E-page 14  2001-2017 Microchip Technology Inc.

MCP6021/1R/2/3/4 3.0 PIN DESCRIPTIONS Descriptions of the pins are listed in Table3-1. TABLE 3-1: PIN FUNCTION TABLE MCP6021 MCP6021 MCP6022 MCP6023 MCP6024 PDIP, SOIC, Symbol Description PDIP, SOIC, PDIP, SOIC, PDIP, SOIC, MSOP, SOT-23-5 SOT-23-5(2) TSSOP TSSOP TSSOP TSSOP(1) 6 1 1 1 6 1 V ,V Analog Output (Op Amp A) OUT OUTA 2 4 4 2 2 2 V -,V - Inverting Input (Op Amp A) IN INA 3 3 3 3 3 3 V +,V + Non-Inverting Input (Op Amp A) IN INA 7 5 2 8 7 4 V Positive Power Supply DD — — — 5 — 5 V + Non-Inverting Input (Op Amp B) INB — — — 6 — 6 V – Inverting Input (Op Amp B) INB — — — 7 — 7 V Analog Output (Op Amp B) OUTB — — — — — 8 V Analog Output (Op Amp C) OUTC — — — — — 9 V – Inverting Input (Op Amp C) INC — — — — — 10 V + Non-Inverting Input (Op Amp C) INC 4 2 5 4 4 11 V Negative Power Supply SS — — — — — 12 V + Non-Inverting Input (Op Amp D) IND — — — — — 13 V – Inverting Input (Op Amp D) IND — — — — — 14 V Analog Output (Op Amp D) OUTD 5 — — — 5 — V Reference Voltage REF — — — — 8 — CS Chip Select 1, 8 — — — 1 — NC No Internal Connection Note 1: The MCP6021 in the 8-pin TSSOP package is only available for I-temp (Industrial Temperature) parts. 2: The MCP6021R is only available in the 5-pin SOT-23 package and for E-temp (Extended Temperature) parts. 3.1 Analog Outputs 3.4 Chip Select Digital Input (CS) The operational amplifier output pins are low-impedance This is a CMOS, Schmitt triggered input that places the voltage sources. part into a Low-Power mode of operation. 3.2 Analog Inputs 3.5 Power Supply (V and V ) SS DD The operational amplifier non-inverting and inverting The positive power supply pin (V ) is 2.5V to 5.5V DD inputs are high-impedance CMOS inputs with low bias higher than the negative power supply pin (V ). For SS currents. normal operation, the other pins are at voltages between V and V . SS DD 3.3 Reference Voltage (V ) REF Typically, these parts are used in a single (positive) MCP6021 and MCP6023 supply configuration. In this case, V is connected to SS ground and V is connected to the supply. V will DD DD Mid-supply reference voltage is provided by the single need a bypass capacitor. operational amplifiers (except in the SOT-23-5 package). This is an unbuffered, resistor voltage divider internal to the part.  2001-2017 Microchip Technology Inc. DS20001685E-page 15

MCP6021/1R/2/3/4 NOTES: DS20001685E-page 16  2001-2017 Microchip Technology Inc.

MCP6021/1R/2/3/4 4.0 APPLICATIONS INFORMATION V DD The MCP6021/1R/2/3/4 family of operational amplifiers is fabricated on Microchip’s state-of-the-art CMOS process. The amplifiers are unity-gain stable and suitable D1 D2 U1 for a wide range of general purpose applications. V 1 4.1 Rail-to-Rail Input MCP602X VOUT V 2 4.1.1 PHASE REVERSAL The MCP6021/1R/2/3/4 operational amplifiers are FIGURE 4-2: Protecting the Analog Inputs. designed to prevent phase reversal when the input pins exceed the supply voltages. Figure2-42 shows the 4.1.3 INPUT CURRENT LIMITS input voltage exceeding the supply voltage without any In order to prevent damage and/or improper operation phase reversal. of these amplifiers, the circuit must limit the voltages at 4.1.2 INPUT VOLTAGE LIMITS the input pins. See the Absolute Maximum Ratings† section. Figure4-3 shows one approach to protecting In order to prevent damage and/or improper operation these inputs. The resistors, R and R , limit the pos- 1 2 of these amplifiers, the circuit must limit the voltages at sible currents in or out of the input pins (and the ESD the input pins. See the Absolute Maximum Ratings† diodes, D and D ). The diode currents will go through 1 2 section. either V or V . DD SS The ESD protection on the inputs can be depicted as shown in Figure4-1. This structure was chosen to V protect the input transistors and to minimize Input Bias DD (I ) current. B D1 D2 U1 Bond V1 V V DD Pad R OUT 1 MCP602X V 2 R 2 Bond Input Bond V + V (cid:16) IN Pad Stage Pad IN V –min (V ,V ) SS 1 2 min(R ,R )> 1 2 2mA max(V ,V )–V 1 2 DD min(R ,R )> V Bond 1 2 2mA SS Pad FIGURE 4-3: Protecting the Analog Inputs. FIGURE 4-1: Simplified Analog Input ESD 4.1.4 NORMAL OPERATION Structures. The input stage of the MCP6021/1R/2/3/4 operational The input ESD diodes clamp the inputs when they try amplifiers uses two differential CMOS input stages in to go more than one diode drop below V . They also SS parallel. One operates at a low Common-Mode Voltage clamp any voltages that go well above V . Their DD (V ) input, while the other operates at high V . With CM CM breakdown voltage is high enough to allow normal this topology, the device operates with V up to 0.3V CM operation, but not low enough to protect against slow above V and 0.3V below V . DD SS overvoltage (beyond V ) events. Very fast ESD DD events (that meet the specifications) are limited so that 4.2 Rail-to-Rail Output damage does not occur. In some applications, it may be necessary to prevent excessive voltages from The maximum output voltage swing is the maximum reaching the operational amplifier inputs. Figure4-2 swing possible under a particular output load. According shows one approach to protecting these inputs. to the specification table, the output can reach within A significant amount of current can flow out of the 20mV of either supply rail when RL = 10 k. See inputs when the Common-Mode Voltage (V ) is below Figure2-31 and Figure2-34 for more information CM ground (V ). See Figure2-42. concerning typical performance. SS  2001-2017 Microchip Technology Inc. DS20001685E-page 17

MCP6021/1R/2/3/4 4.3 Capacitive Loads 4.4 Gain Peaking Driving large capacitive loads can cause stability Figure2-35 and Figure2-36 use R = 1 k to avoid F problems for voltage feedback operational amplifiers. (frequency response) gain peaking and (step response) As the load capacitance increases, the feedback loop’s overshoot. The capacitance to ground at the inverting phase margin decreases and the closed loop input (C ) is the op amp’s Common-mode input capaci- G bandwidth is reduced. This produces gain peaking in tance plus board parasitic capacitance. C is in parallel G the frequency response, with overshoot and ringing in with R , which causes an increase in gain at high frequen- G the step response. cies for non-inverting gains greater than 1 V/V (unity gain). C also reduces the phase margin of the feedback When driving large capacitive loads with these opera- G loop for both non-inverting and inverting gains. tional amplifiers (e.g., >60pF when G = +1), a small series resistor at the output (R in Figure4-4) ISO improves the feedback loop’s phase margin (stability) V IN by making the load resistive at higher frequencies. The V OUT bandwidth will be generally lower than the bandwidth with no capacitive load. R C F G VIN RISO RG MCP602X VOUT C L FIGURE 4-6: Non-Inverting Gain Circuit with Parasitic Capacitance. FIGURE 4-4: Output Resistor, R , The largest value of RF in Figure4-6 that should be ISO used is a function of noise gain (see G in Section4.3 Stabilizes Large Capacitive Loads. N “Capacitive Loads”) and C . Figure4-7 shows results G Figure4-5 gives recommended RISO values for for various conditions. Other compensation techniques different capacitive loads and gains. The x-axis is the may be used, but they tend to be more complicated to normalized load capacitance (CL/GN), where GN is the design. circuit’s noise gain. For non-inverting gains, G and the N SignalGain are equal. For inverting gains, GN is 1.E1+0005k 1+|SignalGain| (e.g., -1V/V gives GN = +2V/V). GN> +1 V/V W) 1,000 (1.E+1004k CG= 7 pF G ≥+1 RF CG= 20 pF Ω) N m (SO mu d RI axi1.E+013k nde 100 M CCG== 5100 0p pFF e G m m 1.E+10020 o 1 10 c Re Noise Gain; GN(V/V) 10 FIGURE 4-7: Non-Inverting Gain Circuit 10 100 1,000 10,000 with Parasitic Capacitance. Normalized Capacitance; C/G (pF) L N FIGURE 4-5: Recommended R Values 4.5 MCP6023 Chip Select (CS) ISO for Capacitive Loads. The MCP6023 is a single amplifier with Chip Select After selecting R for your circuit, double-check the (CS). When CS is pulled high, the supply current drops ISO resulting frequency response peaking and step to 10 nA (typical) and flows through the CS pin to VSS. response overshoot. Modify R ’s value until the When this happens, the amplifier output is put into a ISO response is reasonable. Evaluation on the bench and high-impedance state. By pulling CS low, the amplifier simulations with the MCP6021/1R/2/3/4 Spice macro is enabled. The CS pin has an internal 5 MΩ (typical) model are helpful. pull-down resistor connected to VSS, so it will go low if the CS pin is left floating. Figure1-1 and Figure2-39 show the output voltage and supply current response to a CS pulse. DS20001685E-page 18  2001-2017 Microchip Technology Inc.

MCP6021/1R/2/3/4 4.6 MCP6021 and MCP6023 Reference Voltage R R G F V V The single operational amplifiers (MCP6021 and IN OUT MCP6023), not in the SOT-23-5 package, have an internal mid-supply reference voltage connected to the VREF pin (see Figure4-8). The MCP6021 has CS inter- VREF nally tied to V , which always keeps the operational SS amplifier on and always provides a mid-supply refer- C ence. With the MCP6023, taking the CS pin high B conserves power by shutting down both the operational amplifier and the V circuitry. Taking the CS pin low REF turns on the operational amplifier and VREF circuitry. FIGURE 4-10: Inverting Gain Circuit Using V (MCP6021 and MCP6023 only). REF VDD If you don’t need the mid-supply reference, leave the V pin open. REF 50k 4.7 Supply Bypass VREF With this family of operational amplifiers, the power supply pin (V for single supply) should have a local DD 50k bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm for good, high-frequency performance. It also needs a bulk capacitor (i.e., 1 µF or larger) within 100 mm to CS provide large, slow currents. This bulk capacitor can be shared with nearby analog parts. 5M 4.8 Unused Operational Amplifiers An unused operational amplifier in a quad package VSS (MCP6024) should be configured as shown in Figure4-11. These circuits prevent the output from tog- (CS tied internally to V for MCP6021) gling and causing crosstalk. Circuit A sets the opera- SS tional amplifier at its minimum noise gain. The resistor FIGURE 4-8: Simplified Internal V divider produces any desired reference voltage within REF Circuit (MCP6021 and MCP6023 only). the output voltage range of the operational amplifier. The operational amplifier buffers that reference See Figure4-9 for a non-inverting gain circuit using the voltage. Circuit B uses the minimum number of compo- internal mid-supply reference. The DC Blocking nents and operates as a comparator, but it may draw Capacitor (C ) also reduces noise by coupling the B more current. operational amplifier input to the source. ¼ MCP6024 (A) ¼ MCP6024 (B) R R G F V V DD DD V VOUT R1 DD CB VREF V VIN R2 REF FIGURE 4-9: Non-Inverting Gain Circuit Using VREF (MCP6021 and MCP6023 only). V = V +-------R----2--------- REF DD R +R To use the internal mid-supply reference for an 1 2 inverting gain circuit, connect the V pin to the REF FIGURE 4-11: Unused Operational non-inverting input, as shown in Figure4-10. The capacitor, C , helps reduce power supply noise on the Amplifiers. B output.  2001-2017 Microchip Technology Inc. DS20001685E-page 19

MCP6021/1R/2/3/4 4.9 PCB Surface Leakage Use a solid ground plane and connect the bypass local capacitor(s) to this plane with minimal length traces. In applications where low input bias current is critical, This cuts down inductive and capacitive crosstalk. PCB (Printed Circuit Board) surface leakage effects Separate digital from analog, low speed from high need to be considered. Surface leakage is caused by speed and low power from high power. This will reduce humidity, dust or other contamination on the board. interference. Under low humidity conditions, a typical resistance between nearby traces is 1012. A 5V difference would Keep sensitive traces short and straight. Separate cause 5pA of current to flow, which is greater than the them from interfering components and traces. This is MCP6021/1R/2/3/4 family’s bias current at +25°C especially important for high-frequency (low rise time) (1pA, typical). signals. The easiest way to reduce surface leakage is to use a Sometimes it helps to place guard traces next to victim guard ring around sensitive pins (or traces). The guard traces. They should be on both sides of the victim trace ring is biased at the same voltage as the sensitive pin. and as close as possible. Connect the guard trace to Figure4-12 shows an example of this type of layout. the ground plane at both ends and in the middle for long traces. Guard Ring V - V + Use coax cables (or low-inductance wiring) to route IN IN signal and power to and from the PCB. 4.11 Typical Applications 4.11.1 A/D CONVERTER DRIVER AND ANTI-ALIASING FILTER FIGURE 4-12: Example Guard Ring Layout. Figure4-13 shows a third-order Butterworth filter that can be used as an A/D Converter driver. It has a band- 1. Non-Inverting Gain and Unity Gain Buffer. width of 20 kHz and a reasonable step response. It will a) Connect the guard ring to the inverting input work well for conversion rates of 80ksps and greater (it pin (V -); this biases the guard ring to the IN has 29dB attenuation at 60kHz). Common-mode input voltage. b) Connect the non-inverting pin (V +) to the IN input with a wire that does not touch the 1.0nF PCB surface. MCP602X 8.45k 14.7k 33.2k 2. Inverting (Figure4-12) and Transimpedance Gain Amplifiers (convert current to voltage, such as photo detectors). 1.2nF 100pF a) Connect the guard ring to the non-inverting input pin (V +). This biases the guard ring IN to the same reference voltage as the FIGURE 4-13: A/D Converter Driver and operational amplifier’s input (e.g., VDD/2 or Anti-Aliasing Filter with a 20kHz Cutoff ground). Frequency. b) Connect the inverting pin (V -) to the input IN This filter can easily be adjusted to another bandwidth with a wire that does not touch the PCB by multiplying all capacitors by the same factor. surface. Alternatively, the resistors can all be scaled by another common factor to adjust the bandwidth. 4.10 High-Speed PCB Layout Due to their speed capabilities, a little extra care in the PCB (Printed Circuit Board) layout can make a signifi- cant difference in the performance of these operational amplifiers. Good PC board layout techniques will help you achieve the performance shown in Section1.0 “Electrical Characteristics” and Section2.0 “Typical Performance Curves”, while also helping you minimize EMC (Electro-Magnetic Compatibility) issues. DS20001685E-page 20  2001-2017 Microchip Technology Inc.

MCP6021/1R/2/3/4 4.11.2 OPTICAL DETECTOR AMPLIFIER Figure4-14 shows the MCP6021 operational amplifier 5.6pF Photo used as a transimpedance amplifier in a photo detector Detector circuit. The photo detector looks like a capacitive 100k current source, so the 100 k resistor gains the input signal to a reasonable level. The 5.6pF capacitor stabilizes this circuit and produces a flat frequency 100pF response with a bandwidth of 370kHz. MCP6021 V /2 DD FIGURE 4-14: Transimpedance Amplifier for an Optical Detector.  2001-2017 Microchip Technology Inc. DS20001685E-page 21

MCP6021/1R/2/3/4 NOTES: DS20001685E-page 22  2001-2017 Microchip Technology Inc.

MCP6021/1R/2/3/4 5.0 DESIGN AIDS 5.5 Analog Demonstration and Evaluation Boards Microchip provides the basic design tools needed for the MCP6021/1R/2/3/4 family of operational amplifiers. Microchip offers a broad spectrum of analog demon- stration and evaluation boards that are designed to 5.1 SPICE Macro Model help you achieve faster time to market. For a complete listing of these boards, and their corresponding user’s The latest SPICE macro model available for the guides and technical information, visit the Microchip MCP6021/1R/2/3/4 operational amplifiers is on web site at www.microchip.com/analogtools. Microchip’s web site at www.microchip.com. This Some boards that are especially useful are: model is intended as an initial design tool that works well in the operational amplifier’s linear region of oper- • MCP6XXX Amplifier Evaluation Board 1 ation at room temperature. There is information on its • MCP6XXX Amplifier Evaluation Board 2 capabilities within the macro model file. • MCP6XXX Amplifier Evaluation Board 3 Bench testing is a very important part of any design and • MCP6XXX Amplifier Evaluation Board 4 cannot be replaced with simulations. Also, simulation • Active Filter Demo Board Kit results using this macro model need to be validated by • 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board, comparing them to the data sheet specifications and P/N: SOIC8EV characteristic curves. • 14-Pin SOIC/TSSOP/DIP Evaluation Board, 5.2 FilterLab® Software P/N: SOIC14EV Microchip’s FilterLab® software is an innovative software 5.6 Application Notes tool that simplifies analog active filter (using operational amplifiers) design. Available at no cost from the The following Microchip Application Notes are Microchip web site at www.microchip.com/filterlab, the available on the Microchip web site at www.microchip. FilterLab design tool provides full schematic diagrams of com/appnotes and are recommended as supplemental the filter circuit with component values. It also outputs reference resources. the filter circuit in SPICE format, which can be used with • ADN003, “Select the Right Operational Amplifier the macro model to simulate actual filter performance. for your Filtering Circuits” (DS21821) • AN722, “Operational Amplifier Topologies and DC 5.3 MPLAB® Mindi™ Analog Specifications” (DS00722) Simulator • AN723, “Operational Amplifier AC Specifications and Applications” (DS00723) Microchip’s Mindi™ circuit designer and simulator aids • AN884, “Driving Capacitive Loads With Op Amps” in the design of various circuits useful for active filter, (DS00884) amplifier and power management applications. It is a free online circuit designer and simulator available from • AN990, “Analog Sensor Conditioning Circuits – the Microchip web site at www.microchip.com/mindi. An Overview” (DS00990) This interactive circuit designer and simulator enables • AN1177, “Op Amp Precision Design: DC Errors” designers to quickly generate circuit diagrams and (DS01177) simulate circuits. Circuits developed using the MPLAB • AN1228, “Op Amp Precision Design: Random Mindi analog simulator can be downloaded to a Noise” (DS01228) personal computer or workstation. These application notes and others are listed in the design guide: “Signal Chain Design Guide” (DS21825). 5.4 Microchip Advanced Part Selector (MAPS) MAPS is a software tool that helps semiconductor pro- fessionals efficiently identify Microchip devices that fit a particular design requirement. Available at no cost from the Microchip web site at www.microchip.com/maps, the MAPS is an overall selection tool for Microchip’s product portfolio, that includes analog, memory, MCUs and DSCs. Using this tool you can define a filter to sort features for a parametric search of devices and export side-by-side technical comparison reports. Helpful links are also provided for data sheets, purchasing and sampling of Microchip parts.  2001-2017 Microchip Technology Inc. DS20001685E-page 23

MCP6021/1R/2/3/4 NOTES: DS20001685E-page 24  2001-2017 Microchip Technology Inc.

MCP6021/1R/2/3/4 6.0 PACKAGING INFORMATION 6.1 Package Marking Information 5-Lead SOT-23 (MCP6021/MCP6021R) Example: Device E-Temp Code EY25 MCP6021 EYNN MCP6021R EZNN Note: Applies to 5-Lead SOT-23. 8-Lead PDIP (300 mil) Example: MCP6021 MCP6021 OR I/P256 E/Pe3256 1603 1603 8-Lead SOIC (150 mil) Example: MCP6021 MCP6021E OR I/SN1603 SNe31603 256 256 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC® designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2001-2017 Microchip Technology Inc. DS20001685E-page 25

MCP6021/1R/2/3/4 Package Marking Information (Continued) 8-Lead MSOP Example: 6021E 903256 8-Lead TSSOP Example: 6021 E903 256 14-Lead PDIP (300 mil) (MCP6024) Example: MCP6024-I/P 0903256 OR MCP6024-E/Pe3 0903256 DS20001685E-page 26  2001-2017 Microchip Technology Inc.

MCP6021/1R/2/3/4 Package Marking Information (Continued) 14-Lead SOIC (150 mil) (MCP6024) Example: MCP6024-I/SL 1603256 OR MCP6024 E/SLe3 1603256 14-Lead TSSOP (MCP6024) Example: 6024E 1603 256  2001-2017 Microchip Technology Inc. DS20001685E-page 27

MCP6021/1R/2/3/4 5-Lead Plastic Small Outline Transistor (OT) [SOT23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 0.20 C 2X D e1 A D N E/2 E1/2 E1 E (DATUM D) (DATUM A-B) 0.15 C D 2X NOTE 1 1 2 e B NX b 0.20 C A-B D TOP VIEW A A2 A 0.20 C SEATING PLANE A SEE SHEET 2 C A1 SIDE VIEW Microchip Technology Drawing C04-028D [OT] Sheet 1 of(cid:3)(cid:21) DS20001685E-page 28  2001-2017 Microchip Technology Inc.

MCP6021/1R/2/3/4 5-Lead Plastic Small Outline Transistor (OT) [SOT23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging c (cid:84) L L1 VIEW A-A SHEET 1 Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 6 Pitch e 0.95 BSC Outside lead pitch e1 1.90 BSC Overall Height A 0.90 - 1.45 Molded Package Thickness A2 0.89 - 1.30 Standoff A1 - - 0.15 Overall Width E 2.80 BSC Molded Package Width E1 1.60 BSC Overall Length D 2.90 BSC Foot Length L 0.30 - 0.60 Footprint L1 0.60 REF Foot Angle (cid:73) 0° - 10° Lead Thickness c 0.08 - 0.26 Lead Width b 0.20 - 0.51 Notes: 1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25mm per side. 2. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-091D [OT] Sheet 2 of(cid:3)(cid:21)  2001-2017 Microchip Technology Inc. DS20001685E-page 29

MCP6021/1R/2/3/4 5-Lead Plastic Small Outline Transistor (OT) [SOT23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging X SILK SCREEN 5 Y Z C G 1 2 E GX RECOMMENDED LAND PATTERN Units MILLIMETERS Dimension Limits MIN NOM MAX Contact Pitch E 0.95 BSC Contact Pad Spacing C 2.80 Contact Pad Width (X5) X 0.60 Contact Pad Length (X5) Y 1.10 Distance Between Pads G 1.70 Distance Between Pads GX 0.35 Overall Width Z 3.90 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-2091A [OT] DS20001685E-page 30  2001-2017 Microchip Technology Inc.

MCP6021/1R/2/3/4 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A N B E1 NOTE 1 1 2 TOP VIEW E C A A2 PLANE L c A1 e eB 8X b1 8X b .010 C SIDE VIEW END VIEW Microchip Technology Drawing No. C04-018D Sheet 1 of 2  2001-2017 Microchip Technology Inc. DS20001685E-page 31

MCP6021/1R/2/3/4 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging ALTERNATE LEAD DESIGN (VENDOR DEPENDENT) DATUM A DATUM A b b e e 2 2 e e Units INCHES Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e .100 BSC Top to Seating Plane A - - .210 Molded Package Thickness A2 .115 .130 .195 Base to Seating Plane A1 .015 - - Shoulder to Shoulder Width E .290 .310 .325 Molded Package Width E1 .240 .250 .280 Overall Length D .348 .365 .400 Tip to Seating Plane L .115 .130 .150 Lead Thickness c .008 .010 .015 Upper Lead Width b1 .040 .060 .070 Lower Lead Width b .014 .018 .022 Overall Row Spacing § eB - - .430 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-018D Sheet 2 of 2 DS20001685E-page 32  2001-2017 Microchip Technology Inc.

MCP6021/1R/2/3/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2001-2017 Microchip Technology Inc. DS20001685E-page 33

MCP6021/1R/2/3/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20001685E-page 34  2001-2017 Microchip Technology Inc.

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MCP6021/1R/2/3/4 Note: For the mostcurrent package drawings,please seetheMicrochip Packaging Specification located at http://www.microchip.com/packaging DS20001685E-page 36  2001-2017 Microchip Technology Inc.

MCP6021/1R/2/3/4 Note: For the mostcurrent package drawings,please seetheMicrochip Packaging Specification located at http://www.microchip.com/packaging  2001-2017 Microchip Technology Inc. DS20001685E-page 37

MCP6021/1R/2/3/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20001685E-page 38  2001-2017 Microchip Technology Inc.

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DS20001685E-page 39

MCP6021/1R/2/3/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20001685E-page 40  2001-2017 Microchip Technology Inc.

MCP6021/1R/2/3/4 +*(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8),(cid:18)(cid:6)(cid:10)(cid:8)#(cid:19)(cid:3)(cid:4)(cid:13)(cid:19)(cid:5)(cid:8)(cid:20)(cid:9)(cid:22)(cid:8)(cid:23)(cid:8)(cid:28)(cid:31)(cid:31)(cid:8)(cid:16)(cid:13)(cid:10)(cid:8) (cid:25)(cid:7)!(cid:8)"(cid:9),#(cid:9)% (cid:21)(cid:25)(cid:12)(cid:5)& (cid:30)(cid:10)(cid:9)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2)!(cid:10)"(cid:31)(cid:2)(cid:8)#(cid:9)(cid:9)(cid:14)(cid:15)(cid:31)(cid:2)(cid:12)(cid:28)(cid:8)$(cid:28)(cid:17)(cid:14)(cid:2)%(cid:9)(cid:28)&(cid:7)(cid:15)(cid:17)"’(cid:2)(cid:12)(cid:16)(cid:14)(cid:28)"(cid:14)(cid:2)"(cid:14)(cid:14)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)((cid:28)(cid:8)$(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7))(cid:7)(cid:8)(cid:28)(cid:31)(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)(cid:31)(cid:14)%(cid:2)(cid:28)(cid:31)(cid:2) (cid:11)(cid:31)(cid:31)(cid:12)*++&&&(cid:20)!(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)!+(cid:12)(cid:28)(cid:8)$(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) N NOTE1 E1 1 2 3 D E A A2 L c A1 b1 b e eB @(cid:15)(cid:7)(cid:31)" (cid:19)E?K8(cid:22) (cid:21)(cid:7)!(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:2)A(cid:7)!(cid:7)(cid:31)" (cid:6)(cid:19)E EG(cid:6) (cid:6)(cid:25)H E#!7(cid:14)(cid:9)(cid:2)(cid:10))(cid:2)((cid:7)(cid:15)" E 1(cid:23) ((cid:7)(cid:31)(cid:8)(cid:11) (cid:14) (cid:20)1(cid:4)(cid:4)(cid:2)>(cid:22)? (cid:13)(cid:10)(cid:12)(cid:2)(cid:31)(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)(cid:31)(cid:7)(cid:15)(cid:17)(cid:2)((cid:16)(cid:28)(cid:15)(cid:14) (cid:25) L L (cid:20)(cid:3)1(cid:4) (cid:6)(cid:10)(cid:16)%(cid:14)%(cid:2)((cid:28)(cid:8)$(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)$(cid:15)(cid:14)"" (cid:25)(cid:3) (cid:20)11; (cid:20)1<(cid:4) (cid:20)1(cid:24); >(cid:28)"(cid:14)(cid:2)(cid:31)(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)(cid:31)(cid:7)(cid:15)(cid:17)(cid:2)((cid:16)(cid:28)(cid:15)(cid:14) (cid:25)1 (cid:20)(cid:4)1; L L (cid:22)(cid:11)(cid:10)#(cid:16)%(cid:14)(cid:9)(cid:2)(cid:31)(cid:10)(cid:2)(cid:22)(cid:11)(cid:10)#(cid:16)%(cid:14)(cid:9)(cid:2)N(cid:7)%(cid:31)(cid:11) 8 (cid:20)(cid:3)(cid:24)(cid:4) (cid:20)<1(cid:4) (cid:20)<(cid:3); (cid:6)(cid:10)(cid:16)%(cid:14)%(cid:2)((cid:28)(cid:8)$(cid:28)(cid:17)(cid:14)(cid:2)N(cid:7)%(cid:31)(cid:11) 81 (cid:20)(cid:3)(cid:23)(cid:4) (cid:20)(cid:3);(cid:4) (cid:20)(cid:3)(cid:29)(cid:4) G3(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)A(cid:14)(cid:15)(cid:17)(cid:31)(cid:11) (cid:21) (cid:20)(cid:5)<; (cid:20)(cid:5);(cid:4) (cid:20)(cid:5)(cid:5); (cid:13)(cid:7)(cid:12)(cid:2)(cid:31)(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)(cid:31)(cid:7)(cid:15)(cid:17)(cid:2)((cid:16)(cid:28)(cid:15)(cid:14) A (cid:20)11; (cid:20)1<(cid:4) (cid:20)1;(cid:4) A(cid:14)(cid:28)%(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)$(cid:15)(cid:14)"" (cid:8) (cid:20)(cid:4)(cid:4)(cid:29) (cid:20)(cid:4)1(cid:4) (cid:20)(cid:4)1; @(cid:12)(cid:12)(cid:14)(cid:9)(cid:2)A(cid:14)(cid:28)%(cid:2)N(cid:7)%(cid:31)(cid:11) 71 (cid:20)(cid:4)(cid:23); (cid:20)(cid:4)J(cid:4) (cid:20)(cid:4)(cid:5)(cid:4) A(cid:10)&(cid:14)(cid:9)(cid:2)A(cid:14)(cid:28)%(cid:2)N(cid:7)%(cid:31)(cid:11) 7 (cid:20)(cid:4)1(cid:23) (cid:20)(cid:4)1(cid:29) (cid:20)(cid:4)(cid:3)(cid:3) G3(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)(cid:26)(cid:10)&(cid:2)(cid:22)(cid:12)(cid:28)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:2)Q (cid:14)> L L (cid:20)(cid:23)<(cid:4) (cid:21)(cid:25)(cid:12)(cid:5)(cid:11)& 1(cid:20) ((cid:7)(cid:15)(cid:2)1(cid:2)3(cid:7)"#(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)%(cid:14)6(cid:2))(cid:14)(cid:28)(cid:31)#(cid:9)(cid:14)(cid:2)!(cid:28)(cid:18)(cid:2)3(cid:28)(cid:9)(cid:18)’(cid:2)7#(cid:31)(cid:2)!#"(cid:31)(cid:2)7(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)(cid:31)(cid:14)%(cid:2)&(cid:7)(cid:31)(cid:11)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)(cid:31)(cid:8)(cid:11)(cid:14)%(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) Q(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7))(cid:7)(cid:8)(cid:28)(cid:15)(cid:31)(cid:2)?(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)(cid:31)(cid:14)(cid:9)(cid:7)"(cid:31)(cid:7)(cid:8)(cid:20) <(cid:20) (cid:21)(cid:7)!(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)"(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)%(cid:2)81(cid:2)%(cid:10)(cid:2)(cid:15)(cid:10)(cid:31)(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)#%(cid:14)(cid:2)!(cid:10)(cid:16)%(cid:2))(cid:16)(cid:28)"(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)(cid:31)(cid:9)#"(cid:7)(cid:10)(cid:15)"(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)%(cid:2))(cid:16)(cid:28)"(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)(cid:31)(cid:9)#"(cid:7)(cid:10)(cid:15)"(cid:2)"(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)(cid:31)(cid:2)(cid:14)6(cid:8)(cid:14)(cid:14)%(cid:2)(cid:20)(cid:4)1(cid:4)R(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)"(cid:7)%(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)!(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)%(cid:2)(cid:31)(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6)8(cid:2)=1(cid:23)(cid:20);(cid:6)(cid:20) >(cid:22)?*(cid:2)>(cid:28)"(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)!(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)(cid:31)(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)6(cid:28)(cid:8)(cid:31)(cid:2)3(cid:28)(cid:16)#(cid:14)(cid:2)"(cid:11)(cid:10)&(cid:15)(cid:2)&(cid:7)(cid:31)(cid:11)(cid:10)#(cid:31)(cid:2)(cid:31)(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)"(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)&(cid:7)(cid:15)(cid:17)?(cid:4)(cid:23)(cid:27)(cid:4)(cid:4);>  2001-2017 Microchip Technology Inc. DS20001685E-page 41

MCP6021/1R/2/3/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20001685E-page 42  2001-2017 Microchip Technology Inc.

MCP6021/1R/2/3/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2001-2017 Microchip Technology Inc. DS20001685E-page 43

MCP6021/1R/2/3/4 (cid:21)(cid:25)(cid:12)(cid:5)& (cid:30)(cid:10)(cid:9)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2)!(cid:10)"(cid:31)(cid:2)(cid:8)#(cid:9)(cid:9)(cid:14)(cid:15)(cid:31)(cid:2)(cid:12)(cid:28)(cid:8)$(cid:28)(cid:17)(cid:14)(cid:2)%(cid:9)(cid:28)&(cid:7)(cid:15)(cid:17)"’(cid:2)(cid:12)(cid:16)(cid:14)(cid:28)"(cid:14)(cid:2)"(cid:14)(cid:14)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)((cid:28)(cid:8)$(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7))(cid:7)(cid:8)(cid:28)(cid:31)(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)(cid:31)(cid:14)%(cid:2)(cid:28)(cid:31)(cid:2) (cid:11)(cid:31)(cid:31)(cid:12)*++&&&(cid:20)!(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)!+(cid:12)(cid:28)(cid:8)$(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) DS20001685E-page 44  2001-2017 Microchip Technology Inc.

MCP6021/1R/2/3/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2001-2017 Microchip Technology Inc. DS20001685E-page 45

MCP6021/1R/2/3/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20001685E-page 46  2001-2017 Microchip Technology Inc.

MCP6021/1R/2/3/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2001-2017 Microchip Technology Inc. DS20001685E-page 47

MCP6021/1R/2/3/4 NOTES: DS20001685E-page 48  2001-2017 Microchip Technology Inc.

MCP6021/1R/2/3/4 APPENDIX A: REVISION HISTORY Revision B (November 2003) • Second Release of this Document Revision E (January 2017) Revision A (November 2001) The following is the list of modifications: 1. Updated the AC Electrical Characteristics table. • Original Release of this Document 2. Added Section4.1.2, Input Voltage Limits and Section4.1.3, Input Current Limits. 3. Added package information for 8-pin TSSOP. 4. Various typographical edits. Revision D (February 2009) The following is the list of modifications: 1. Changed all references to 6.0V back to 5.5V throughout document. 2. Design Aids: Name change for Mindi Simulation Tool. 3. Section1.0, Electrical Characteristics, Section “”: Corrected “Maximum Output Voltage Swing” condition from 0.9V Input Overdrive to 0.5V Input Overdrive. 4. Section1.0, Electrical Characteristics, Section “AC Electrical Characteristics”: Changed Phase Margin condition from G = +1 to G= +1 V/V. 5. Section1.0, Electrical Characteristics, Section “AC Electrical Characteristics”: Changed Settling Time, 0.2% condition from G = +1 to G=+1 V/V. 6. Section1.0, Electrical Characteristics: Added Section1.1, Test Circuits 7. Section5.0, Design Aids: Name change for Mindi Simulation Tool. Added new boards to Section5.5, Analog Demonstration and Evalua- tion Boards and new application notes to Section5.6, Application Notes. 8. Updates Appendix A: “Revision History” Revision C (December 2005) The following is the list of modifications: 1. Added SOT-23-5 package option for single op amps MCP6021 and MCP6021R (E-temp only). 2. Added MSOP-8 package option for E-temp single op amp (MCP6021). 3. Corrected package drawing on front page for dual op amp (MCP6022). 4. Clarified spec conditions (I , PM and THD+N) SC in Section2.0, Typical Performance Curves. 5. Added Section3.0, Pin Descriptions. 6. Updated Section4.0, Applications Information for THD+N, unused op amps, and gain peaking discussions. 7. Corrected and updated package marking infor- mation in Section6.0, Packaging Information. 8. Added Appendix A: “Revision History”.  2001-2017 Microchip Technology Inc. DS20001685E-page 49

MCP6021/1R/2/3/4 NOTES: DS20001685E-page 50  2001-2017 Microchip Technology Inc.

MCP6021/1R/2/3/4 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. [X](1) X /XX Examples: a) MCP6021T-E/OT: Tape and Reel, Device Tape and Reel Temperature Package Extended temperature, Option Range 5LD SOT-23. b) MCP6021-E/P: Extended temperature, 8LD PDIP. Device: MCP6021 Single Op Amp c) MCP6021-E/SN: Extended temperature, 8LD SOIC. MCP6021T Single Op Amp (Tape and Reel for SOT-23, SOIC, TSSOP, a) MCP6021RT-E/OT: Tape and Reel, MSOP) Extended temperature, MCP6021R Single Op Amp 5LD SOT-23. MCP6021RT Single Op Amp (Tape and Reel for SOT-23) a) MCP6022-I/P: Industrial temperature, 8LD PDIP. MCP6022 Dual Op Amp b) MCP6022-E/P: Extended temperature, MCP6022T Dual Op Amp 8LD PDIP. (Tape and Reel for SOIC and TSSOP) c) MCP6022T-E/ST: Tape and Reel, MCP6023 Single Op Amp w/CS Extended temperature, MCP6023T Single Op Amp w/CS 8LD TSSOP. (Tape and Reel for SOIC and TSSOP) MCP6024 Quad Op Amp a) MCP6023-I/P: Industrial temperature, MCP6024T Quad Op Amp 8LD PDIP. (Tape and Reel for SOIC and TSSOP) b) MCP6023-E/P: Extended temperature, 8LD PDIP. c) MCP6023-E/SN: Extended temperature, Tape and Reel Blank= Standard packaging (tube or tray) 8LD SOIC. Option: T = Tape and Reel(1) a) MCP6024-I/SL: Industrial temperature, 14LD SOIC. Temperature I = -40C to +85C (Industrial) b) MCP6024-E/SL: Extended temperature, Range: E = -40C to +125C (Extended) 14LD SOIC. c) MCP6024T-E/ST: Tape and Reel, Extended temperature, Package: OT = Plastic Small Outline Transistor (SOT-23), 5-Lead 14LD TSSOP. (MCP6021, E-Temp; MCP6021R, E-Temp) MS = Plastic MSOP, 8-Lead (MCP6021, E-Temp) Note1: Tape and Reel identifier only appears in the P = Plastic DIP (300 mil Body), 8-Lead, 14-Lead catalog part number description. This identi- SN = Plastic SOIC (150 mil Body), 8-Lead fier is used for ordering purposes and is not SL = Plastic SOIC (150 mil Body), 14-Lead printed on the device package. Check with ST = Plastic TSSOP, 8-Lead (MCP6021, I-Temp; MCP6022, your Microchip Sales Office for package I-Temp, E-Temp; MCP6023, I-Temp, E-Temp) availability with the Tape and Reel option. ST = Plastic TSSOP, 14-Lead  2001-2017 Microchip Technology Inc. DS20001685E-page 51

MCP6021/1R/2/3/4 NOTES: DS20001685E-page 52  2001-2017 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, AnyRate, AVR, and may be superseded by updates. It is your responsibility to AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory, ensure that your application meets with your specifications. CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELOQ, MICROCHIP MAKES NO REPRESENTATIONS OR KEELOQ logo, Kleer, LANCheck, LINK MD, maXStylus, WARRANTIES OF ANY KIND WHETHER EXPRESS OR maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB, IMPLIED, WRITTEN OR ORAL, STATUTORY OR OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip OTHERWISE, RELATED TO THE INFORMATION, Designer, QTouch, RightTouch, SAM-BA, SpyNIC, SST, SST INCLUDING BUT NOT LIMITED TO ITS CONDITION, Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered QUALITY, PERFORMANCE, MERCHANTABILITY OR trademarks of Microchip Technology Incorporated in the U.S.A. FITNESS FOR PURPOSE. Microchip disclaims all liability and other countries. arising from this information and its use. Use of Microchip ClockWorks, The Embedded Control Solutions Company, devices in life support and/or safety applications is entirely at EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, the buyer’s risk, and the buyer agrees to defend, indemnify and mTouch, Precision Edge, and Quiet-Wire are registered hold harmless Microchip from any and all damages, claims, trademarks of Microchip Technology Incorporated in the U.S.A. suits, or expenses resulting from such use. No licenses are Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any conveyed, implicitly or otherwise, under any Microchip Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, intellectual property rights unless otherwise stated. CodeGuard, CryptoAuthentication, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in Microchip received ISO/TS-16949:2009 certification for its worldwide the U.S.A. headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California Silicon Storage Technology is a registered trademark of Microchip and India. The Company’s quality system processes and procedures Technology Inc. in other countries. are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and GestIC is a registered trademark of Microchip Technology analog products. In addition, Microchip’s quality system for the design Germany II GmbH & Co. KG, a subsidiary of Microchip Technology and manufacture of development systems is ISO 9001:2000 certified. Inc., in other countries. All other trademarks mentioned herein are property of their QUALITY MANAGEMENT SYSTEM respective companies. © 2001-2017, Microchip Technology Incorporated, All Rights CERTIFIED BY DNV Reserved. ISBN: 978-1-5224-1278-6 == ISO/TS 16949 ==  2001-2017 Microchip Technology Inc. DS20001685E-page 53

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