M MCP601/2/3/4 2.7V to 5.5V Single-Supply CMOS Op Amps Features Description • Single-Supply: 2.7V to 5.5V The Microchip Technology Inc. MCP601/2/3/4 family of • Rail-to-Rail Output low-power operational amplifiers (op amps) are offered in single (MCP601), single with Chip Select (CS) • Input Range Includes Ground (MCP603), dual (MCP602) and quad (MCP604) • Gain Bandwidth Product: 2.8MHz (typ.) configurations. These op amps utilize an advanced • Unity-Gain Stable CMOS technology that provides low bias current, high- • Low Quiescent Current: 230µA/amplifier (typ.) speed operation, high open-loop gain and rail-to-rail • Chip Select (CS): MCP603 only output swing. This product offering operates with a • Temperature Ranges: single supply voltage that can be as low as 2.7V, while drawing 230µA (typ.) of quiescent current per - Industrial: -40°C to +85°C amplifier. In addition, the common mode input voltage - Extended: -40°C to +125°C range goes 0.3V below ground, making these • Available in Single, Dual and Quad amplifiers ideal for single-supply operation. These devices are appropriate for low-power, battery- Typical Applications operated circuits due to the low quiescent current, for A/D convert driver amplifiers because of their wide • Portable Equipment bandwidth or for anti-aliasing filters by virtue of their low • A/D Converter Driver input bias current. • Photo Diode Pre-amp The MCP601, MCP602 and MCP603 are available in • Analog Filters standard 8-lead PDIP, SOIC and TSSOP packages. • Data Acquisition The MCP601 and MCP601R are also available in a • Notebooks and PDAs standard 5-lead SOT-23 package, while the MCP603 is • Sensor Interface available in a standard 6-lead SOT-23 package. The MCP604 is offered in standard 14-lead PDIP, SOIC and Available Tools TSSOP packages. The MCP601/2/3/4 family is available in the Industrial • SPICE Macro Models at www.microchip.com and Extended temperature ranges and has a power • FilterLab® Software at www.microchip.com supply range of 2.7V to 5.5V. Package Types MCP601 MCP602 MCP603 MCP604 PDIP, SOIC, TSSOP PDIP, SOIC, TSSOP PDIP, SOIC, TSSOP PDIP, SOIC, TSSOP NC 1 8 NC VOUTA 1 8 VDD NC 1 8 CS VOUTA 1 14 VOUTD VIN– 2 7 VDD VINA– 2 7 VOUTB VIN– 2 7 VDD VINA– 2 13 VIND– VIN+ 3 6 VOUT VINA+ 3 6 VINB– VIN+ 3 6 VOUT VINA+ 3 12 VIND+ VSS 4 5 NC VSS 4 5 VINB+ VSS 4 5 NC VDD 4 11 VSS MCP601 MCP601R MCP603 VINB+ 5 10 VINC+ SOT23-5 SOT23-5 SOT23-6 VINB– 6 9 VINC– VOUT 1 5 VDD VOUT 1 5 VSS VOUT 1 6 VDD VOUTB 7 8 VOUTC V 2 V 2 V 2 5 CS SS DD SS VIN+ 3 4 VIN– VIN+ 3 4 VIN– VIN+ 3 4 VIN–  2004 Microchip Technology Inc. DS21314F-page 1

MCP601/2/3/4 1.0 ELECTRICAL PIN FUNCTION TABLE CHARACTERISTICS Name Function V +, V +, V +, V +, V + Non-inverting Inputs Absolute Maximum Ratings † IN INA INB INC IND V –, V –, V –, V –, V – Inverting Inputs IN INA INB INC IND V - V .........................................................................7.0V DD SS V Positive Power Supply DD All inputs and outputs......................V - 0.3V to V + 0.3V SS DD V Negative Power Supply Difference Input voltage........................................|V - V | SS DD SS Output Short Circuit Current...................................continuous VOUT, VOUTA, VOUTB, VOUTC, Outputs Current at Input Pin.......................................................±2mA VOUTD Current at Output and Supply Pins.............................±30mA CS Chip Select Storage temperature.....................................-65°C to +150°C NC No Internal Connection Junction temperature..................................................+150°C ESD protection on all pins (HBM; MM)................≥ 3kV; 200V † Notice: Stresses above those listed under “Maximum Rat- ings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. DC CHARACTERISTICS Electrical Specifications: Unless otherwise specified, T = +25°C, V = +2.7V to +5.5V, V = GND, V = V /2, A DD SS CM DD V ≈ V /2 and R = 100kΩ to V /2. OUT DD L DD Parameters Sym Min Typ Max Units Conditions Input Offset Input Offset Voltage V -2 ±0.7 +2 mV OS Industrial Temperature V -3 ±1 +3 mV T = -40°C to +85°C (Note1) OS A Extended Temperature V -4.5 ±1 +4.5 mV T = -40°C to +125°C (Note1) OS A Input Offset Temperature Drift ∆V /∆T — ±2.5 — µV/°C T = -40°C to +125°C OS A A Power Supply Rejection PSRR 80 88 — dB V = 2.7V to 5.5V DD Input Current and Impedance Input Bias Current I — 1 — pA B Industrial Temperature I — 20 60 pA T = +85°C (Note1) B A Extended Temperature I — 450 5000 pA T = +125°C (Note1) B A Input Offset Current I — ±1 — pA OS Common Mode Input Impedance ZCM — 1013||6 — Ω||pF Differential Input Impedance ZDIFF — 1013||3 — Ω||pF Common Mode Common Mode Input Range V V – 0.3 — V – 1.2 V CMR SS DD Common Mode Rejection Ratio CMRR 75 90 — dB V = 5.0V, V = -0.3V to 3.8V DD CM Open-loop Gain DC Open-loop Gain (large signal) A 100 115 — dB R = 25kΩ to V /2, OL L DD V = 100mV to V – 100mV OUT DD A 95 110 — dB R = 5kΩ to V /2, OL L DD V = 100mV to V – 100mV OUT DD Output Maximum Output Voltage Swing V , V V + 15 — V – 20 mV R = 25kΩ to V /2, Output overdrive = 0.5V OL OH SS DD L DD V , V V + 45 — V – 60 mV R = 5kΩ to V /2, Output overdrive = 0.5V OL OH SS DD L DD Linear Output Voltage Swing V V + 100 — V – 100 mV R = 25kΩ to V /2, A ≥ 100dB OUT SS DD L DD OL V V + 100 — V – 100 mV R = 5kΩ to V /2, A ≥ 95dB OUT SS DD L DD OL Output Short Circuit Current I — ±22 — mA V = 5.5V SC DD I — ±12 — mA V = 2.7V SC DD Power Supply Supply Voltage V 2.7 — 5.5 V DD Quiescent Current per Amplifier I — 230 325 µA I = 0 Q O Note 1: These specifications are not tested in either the SOT-23 or TSSOP packages with date codes older than YYWW = 0408. In these cases, the minimum and maximum values are by design and characterization only. DS21314F-page 2  2004 Microchip Technology Inc.

MCP601/2/3/4 AC CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, T = +25°C, V = +2.7V to +5.5V, V = GND, V = V /2, A DD SS CM DD V ≈ V /2, R = 100kΩ to V /2 and C = 50pF. OUT DD L DD L Parameters Sym Min Typ Max Units Conditions Frequency Response Gain Bandwidth Product GBWP — 2.8 — MHz Phase Margin PM — 50 — ° G = +1V/V Step Response Slew Rate SR — 2.3 — V/µs G = +1V/V Settling Time (0.01%) t — 4.5 — µs G = +1V/V, 3.8V step settle Noise Input Noise Voltage E — 7 — µV f = 0.1Hz to 10Hz ni P-P Input Noise Voltage Density e — 29 — nV/√Hz f = 1kHz ni e — 21 — nV/√Hz f = 10kHz ni Input Noise Current Density i — 0.6 — fA/√Hz f = 1kHz ni MCP603 CHIP SELECT CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, T = +25°C, V = +2.7V to +5.5V, V = GND, V = V /2, A DD SS CM DD V ≈ V /2, R = 100kΩ to V /2 and C = 50pF. OUT DD L DD L Parameters Sym Min Typ Max Units Conditions DC Characteristics CS Logic Threshold, Low V V — 0.2 V V IL SS DD CS Input Current, Low I -1.0 — — µA CS = 0.2V CSL DD CS Logic Threshold, High V 0.8 V — V V IH DD DD CS Input Current, High I — 0.7 2.0 µA CS = V CSH DD Shutdown V current I -2.0 -0.7 — µA CS = V SS Q_SHDN DD Amplifier Output Leakage in Shutdown I — 1 — nA O_SHDN CS Threshold Hysteresis HYST — 0.3 — V Internal switch Timing CS Low to Amplifier Output Turn-on t — 3.1 10 µs CS ≤ 0.2V , G = +1V/V ON DD Time CS High to Amplifier Output High-Z Time t — 100 — ns CS ≥ 0.8V , G = +1V/V, No load. OFF DD CS t t ON OFF V Hi-Z Output Active Hi-Z OUT I 2nA (typ.) 230µA (typ.) DD I -700nA (typ.) -230µA (typ.) SS CS 700nA (typ.) 2nA (typ.) Current FIGURE 1-1: MCP603 Chip Select (CS) Timing Diagram.  2004 Microchip Technology Inc. DS21314F-page 3

MCP601/2/3/4 TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, V = +2.7V to +5.5V and V = GND. DD SS Parameters Sym Min Typ Max Units Conditions Temperature Ranges Specified Temperature Range T -40 — +85 °C Industrial temperature parts A T -40 — +125 °C Extended temperature parts A Operating Temperature Range T -40 — +125 °C Note A Storage Temperature Range T -65 — +150 °C A Thermal Package Resistances Thermal Resistance, 5L-SOT23 θ — 256 — °C/W JA Thermal Resistance, 6L-SOT23 θ — 230 — °C/W JA Thermal Resistance, 8L-PDIP θ — 85 — °C/W JA Thermal Resistance, 8L-SOIC θ — 163 — °C/W JA Thermal Resistance, 8L-TSSOP θ — 124 — °C/W JA Thermal Resistance, 14L-PDIP θ — 70 — °C/W JA Thermal Resistance, 14L-SOIC θ — 120 — °C/W JA Thermal Resistance, 14L-TSSOP θ — 100 — °C/W JA Note: The Industrial temperature parts operate over this extended range, but with reduced performance. The Extended temperature specs do not apply to Industrial temperature parts. In any case, the internal Junction temperature (T ) must not exceed the absolute maximum specification of 150°C. J DS21314F-page 4  2004 Microchip Technology Inc.

MCP601/2/3/4 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, T = +25°C, V = +2.7V to +5.5V, V = GND, V = V /2, A DD SS CM DD R = 100kΩ to V /2, V ≈ V /2 and C = 50pF. L DD OUT DD L 120 0 300 I = 0 -40°C Loop Gain (dB) 12468000000 Phase Gain -----119635200000 Loop Phase (°) cent Current per mplifier (µA) 112205050000 O +++1282555°°°CCC n- n- esA Ope 0 -180 Ope Qui 50 -20 -210 0 -40 -240 01.E.-011 11.E+00 101.E+01 1010.E+02 11k.E+03 101.Ek+04 1001.E+0k5 1M1.E+06 10M1.E+07 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Frequency (Hz) Supply Voltage (V) FIGURE 2-1: Open-Loop Gain, Phase vs. FIGURE 2-4: Quiescent Current vs. Frequency. Supply Voltage. 3.5 300 3.0 VDD = 5.0V er 250 IO = 0 w Rate (V/µs) 122...505 RisFinagll iEndgg Eedge cent Current pmplifier (µA) 112050000 VDD = 2V.7DVD = 5.5V Sle 01..50 QuiesA 50 0.0 0 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 Ambient Temperature (°C) Ambient Temperature (°C) FIGURE 2-2: Slew Rate vs. Temperature. FIGURE 2-5: Quiescent Current vs. Temperature. 5.5 110 10µ10,000 andwidth Product (MHz) 2233445.......0505050 PGMB,W GP = +1 456789100000000 Margin, G = +1 (°) seVoltageDensity√(V/Hz) 1µ1,000 Gain B 011...505 123000 Phase putNoi 100n100 n 0.0 0 I 10n -50 -25 0 25 50 75 100 125 0110.E-.011 11.E+00 11.E0+01 101.E+020 11.E+0k3 101.E+0k4 101.E+005k 11.ME+06 Ambient Temperature (°C) Frequency(Hz) FIGURE 2-3: Gain Bandwidth Product, FIGURE 2-6: Input Noise Voltage Density Phase Margin vs. Temperature. vs. Frequency.  2004 Microchip Technology Inc. DS21314F-page 5

MCP601/2/3/4 Note: Unless otherwise indicated, T = +25°C, V = +2.7V to +5.5V, V = GND, V = V /2, A DD SS CM DD R = 100kΩ to V /2, V ≈ V /2 and C = 50pF. L DD OUT DD L 16% 18% urrences 1124%% 1200 Samples urrences 111246%%% 1T2A 0=0 - S40a mtop +le1s25°C Occ 10% Occ 10% of 8% of 8% ge 6% ge 6% nta 4% nta 4% Perce 2% Perce 2% 0% 0% -2.0-1.6-1.2-0.8-0.4 0.0 0.4 0.8 1.2 1.6 2.0 -10 -8 -6 -4 -2 0 2 4 6 8 10 Input Offset Voltage (mV) Input Offset Voltage Drift (µV/°C) FIGURE 2-7: Input Offset Voltage. FIGURE 2-10: Input Offset Voltage Drift. 0.5 100 V) 0.4 oltage (m 000...123 VVDD == 25..75VV RR (dB) 9905 PSRR V 0.0 DD S Offset --00..21 MRR, P 85 CMRR ut -0.3 C 80 p n -0.4 I -0.5 75 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 Ambient Temperature (°C) Ambient Temperature (°C) FIGURE 2-8: Input Offset Voltage vs. FIGURE 2-11: CMRR, PSRR vs. Temperature. Temperature. 800 800 Offset Voltage (µV) 123456700000000000000 VDD = 2.7V TTTTAAAA = === + ++-142820555°°°C°CCC Offset Voltage (µV) 123456700000000000000 VDD = 5.5TV = +125°CTTTTAAAA = === + ++-142820555°°°°CCCC Input -1000 TA = +125°C Input -1000 A -200 -200 5 0 5 0 5 0 5 0 5 0 5 0 -0.5 0.0 0.5 1.0 1.5 2.0 0. 0. 0. 1. 1. 2. 2. 3. 3. 4. 4. 5. - Common Mode Input Voltage (V) Common Mode Input Voltage (V) FIGURE 2-9: Input Offset Voltage vs. FIGURE 2-12: Input Offset Voltage vs. Common Mode Input Voltage with V = 2.7V. Common Mode Input Voltage with V = 5.5V. DD DD DS21314F-page 6  2004 Microchip Technology Inc.

MCP601/2/3/4 Note: Unless otherwise indicated, T = +25°C, V = +2.7V to +5.5V, V = GND, V = V /2, A DD SS CM DD R = 100kΩ to V /2, V ≈ V /2 and C = 50pF. L DD OUT DD L n 150 100 eparatio 140 No Load B) 8900 PPSSRRRR+- el S 130 R (d 70 CMRR o Chann(dB) 111200 RR, PSR 456000 el t CM 30 nn 100 Cha 90 1200 VDD = 5.0V 11.E+k03 11.0E+04k 101.E+005k 11M.E+06 101.E+000 1.E+01 11.E+0k2 1.E+03 11.E+004k 1.E+05 1010.E+06k Frequency (Hz) Frequency (Hz) FIGURE 2-13: Channel-to-Channel FIGURE 2-16: CMRR, PSRR vs. Separation vs. Frequency. Frequency. Bias and Offset Currents (pA) 110001000 VVDCDM == 54..53VV IB IOS BiasandOffsetCurrents(pA) 110100000 VmDaDx=.V5C.5MVR≥4.3VIOS, +12IIBB5,,°C++18255°C°C Input 1 Input 1 IOS, +85°C 25 35 45 55 65 75 85 95 105 115125 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Ambient Temperature (°C) CommonModeInputVoltage(V) FIGURE 2-14: Input Bias Current, Input FIGURE 2-17: Input Bias Current, Input Offset Current vs. Ambient Temperature. Offset Current vs. Common Mode Input Voltage. 120 120 R =25kΩ B) dB) L ain(d 110 VDD=5.5V Gain( 110 G p p o 100 o 100 o o L n-L en- Ope 90 VDD=2.7V Op 90 C C D D 80 80101.E+020 11.E+0k3 11.E+004 k 101.E0+05k 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 LoadResistance(Ω) SupplyVoltage(V) FIGURE 2-15: DC Open-Loop Gain vs. FIGURE 2-18: DC Open-Loop Gain vs. Load Resistance. Supply Voltage.  2004 Microchip Technology Inc. DS21314F-page 7

MCP601/2/3/4 Note: Unless otherwise indicated, T = +25°C, V = +2.7V to +5.5V, V = GND, V = V /2, A DD SS CM DD R = 100kΩ to V /2, V ≈ V /2 and C = 50pF. L DD OUT DD L 3.5 100 130 GainBandwidthProduct(MHz) 011223......505050 VDD=5.0V PMG,BGW=P+1 456789000000 PhaseMargin,G=+1(°) DCOpen-LoopGain(dB) 11190120000 VVVVDDDDDDDD====255.2.75..5V7VVV,,,R,RRRLLLL====225555kkkkΩΩΩΩ 0.0 30 80 1.E+02 1.E+03 1.E+04 1.E+05 100 1k 10k 100k -50 -25 0 25 50 75 100 125 LoadResistance(Ω) AmbientTemperature(°C) FIGURE 2-19: Gain Bandwidth Product, FIGURE 2-22: DC Open-Loop Gain vs. Phase Margin vs. Load Resistance. Temperature. 1,000 1000 V =5.5V droom (mV); nd V - VOLSS 100 VDD-VOH droom(mV);ndV-VOLSS 100 RDLDtiedtoVDD/2 VVDODL--VVSOSH,, RRLL==55kkΩΩ Output HeaV - V aDDOH 10 VOL-VSS OutputHeaV-VaDDOH 10 VVDD--VVOH,, RRL==2255kkΩΩ OL SS L 1 1 0.01 0.1 1 10 -50 -25 0 25 50 75 100 125 Output Current Magnitude (mA) AmbientTemperature(°C) FIGURE 2-20: Output Voltage Headroom FIGURE 2-23: Output Voltage Headroom vs. Output Current. vs. Temperature. e 10 VDD = 5.0V ent 30 TA = -40°C um Output VoltagSwing (V)P-P 1 Short Circuit Curragnitude (mA) 11220505 TTTAAA === + ++1282555°°°CCC Maxim utput M 5 O 0.1 0 101.E+04k 101.E0+05k 11M.E+06 101.E+M07 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Frequency (Hz) Supply Voltage (V) FIGURE 2-21: Maximum Output Voltage FIGURE 2-24: Output Short-Circuit Current Swing vs. Frequency. vs. Supply Voltage. DS21314F-page 8  2004 Microchip Technology Inc.

MCP601/2/3/4 Note: Unless otherwise indicated, T = +25°C, V = +2.7V to +5.5V, V = GND, V = V /2, A DD SS CM DD R = 100kΩ to V /2, V ≈ V /2 and C = 50pF. L DD OUT DD L 5.0 5.0 V = 5.0V V = 5.0V 4.5 DD 4.5 DD G = +1 G = -1 4.0 4.0 V) V) e ( 3.5 e ( 3.5 ag 3.0 ag 3.0 olt 2.5 olt 2.5 V V ut 2.0 ut 2.0 p p ut 1.5 ut 1.5 O O 1.0 1.0 0.5 0.5 0.0 0.0 0.E+00 1.E-06 2.E-06 3.E-06 4.E-06 5.E-06 6.E-06 7.E-06 8.E-06 9.E-06 1.E-05 0.E+00 1.E-06 2.E-06 3.E-06 4.E-06 5.E-06 6.E-06 7.E-06 8.E-06 9.E-06 1.E-05 Time (1 µs/div) Time (1 µs/div) FIGURE 2-25: Large Signal Non-Inverting FIGURE 2-28: Large Signal Inverting Pulse Pulse Response. Response. 2.59 2.59 VDD = 5.0V VDD = 5.0V v) 2.57 G = +1 v) 2.57 G = -1 di di V/ 2.55 V/ 2.55 m m 0 2.53 0 2.53 2 2 e ( 2.51 e ( 2.51 g g a a olt 2.49 olt 2.49 V V ut 2.47 ut 2.47 p p ut 2.45 ut 2.45 O O 2.43 2.43 2.401.E+00 1.E-06 2.E-06 3.E-06 4.E-06 5.E-06 6.E-06 7.E-06 8.E-06 9.E-06 1.E-05 2.401.E+00 1.E-06 2.E-06 3.E-06 4.E-06 5.E-06 6.E-06 7.E-06 8.E-06 9.E-06 1.E-05 Time (1 µs/div) Time (1 µs/div) FIGURE 2-26: Small Signal Non-Inverting FIGURE 2-29: Small Signal Inverting Pulse Pulse Response. Response. 5.5 0 V = 5.5V 5.0 CS -100 DD OutputVoltage,hipSelectVoltage(V) 11223344........05050505 VOUTActive VGVRDILN=D===+12150.5.00VVkΩtoGND Quiescent Current through V (µA)SS ------765432000000000000 C 0.5 -800 0.0 V High-Z -0.5 OUT 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.0E+00 5.0E-06 1.0E-05 1.5E-05 2.0E-05 2.5E-05 3.0E-05 3.5E-05 4.0E-05 4.5E-05 5.0E-05 Time(5µs/div) Chip Select Voltage (V) FIGURE 2-27: Chip Select Timing FIGURE 2-30: Quiescent Current Through (MCP603). V vs. Chip Select Voltage (MCP603). SS  2004 Microchip Technology Inc. DS21314F-page 9

MCP601/2/3/4 Note: Unless otherwise indicated, T = +25°C, V = +2.7V to +5.5V, V = GND, V = V /2, A DD SS CM DD R = 100kΩ to V /2, V ≈ V /2 and C = 50pF. L DD OUT DD L 0.8 6 urrent (µA) 000...567 VDD = 5.5V oltages (V) 45 VGD =D =+ 2+5.0V C V Pin 0.4 put 3 elect 00..23 d Out 2 VIN Chip S 00..01 nput an 01 VOUT 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 (I -1 0.0E+00 5.0E-06 1.0E-05 1.5E-05 2.0E-05 2.5E-05 Chip Select Voltage (V) Time (5 µs/div) FIGURE 2-31: Chip Select Pin Input FIGURE 2-33: The MCP601/2/3/4 family of Current vs. Chip Select Voltage. op amps shows no phase reversal under input overdrive. 3.0 ch Amplifier On VDD = 5.0V p Select SwitVoltage (V) 122...505 CS Hi to Low CS Low to Hi Chiput 1.0 al ut nO er 0.5 nt Amplifier Hi-Z I 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Chip Select Voltage (V) FIGURE 2-32: Hysteresis of Chip Select’s Internal Switch. DS21314F-page 10  2004 Microchip Technology Inc.

MCP601/2/3/4 3.0 APPLICATIONS INFORMATION The second specification that describes the output swing capability of these amplifiers is the Linear Output The MCP601/2/3/4 family of op amps are fabricated on Voltage Swing. This specification defines the maximum Microchip’s state-of-the-art CMOS process. They are output swing that can be achieved while the amplifier is unity-gain stable and suitable for a wide range of still operating in its linear region. To verify linear general purpose applications. operation in this range, the large signal (DC Open-Loop Gain (A )) is measured at points 100mV inside the OL 3.1 Input supply rails. The measurement must exceed the specified gains in the specification table. The MCP601/2/3/4 amplifier family is designed to not exhibit phase reversal when the input pins exceed the 3.3 MCP603 Chip Select (CS) supply rails. Figure2-33 shows an input voltage that exceeds both supplies with no resulting phase The MCP603 is a single amplifier with Chip Select inversion. (CS). When CS is pulled high, the supply current drops The Common Mode Input Voltage Range (V ) to -0.7µA (typ.), which is pulled through the CS pin to CMR includes ground in single-supply systems (VSS), but VSS. When this happens, the amplifier output is put into does not include V . This means that the amplifier a high-impedance state. Pulling CS low enables the DD input behaves linearly as long as the Common Mode amplifier and, if the CS pin is left floating, the amplifier Input Voltage (V ) is kept within the specified V may not operate properly. Figure1-1 is the Chip Select CM CMR limits (V – 0.3V to V – 1.2V at +25°C). timing diagram and shows the output voltage, supply SS DD currents and CS current in response to a CS pulse. Input voltages that exceed the input voltage range Figure2-27 shows the measured output voltage (V – 0.3V to V – 1.2V at +25°C) can cause exces- SS DD response to a CS pulse. sive current to flow into or out of the input pins. Current beyond ±2mA may cause reliability problems. 3.4 Capacitive Loads Applications that exceed this rating must externally limit the input current with a resistor (R ), as shown in IN Driving large capacitive loads can cause stability Figure3-1. problems for voltage feedback op amps. As the load capacitance increases, the feedback loop’s phase margin decreases and the closed-loop bandwidth is R IN reduced. This produces gain peaking in the frequency V + IN response with overshoot and ringing in the step MCP60X response. When driving large capacitive loads with these op – amps (e.g., > 40pF when G = +1), a small series resistor at the output (R in Figure3-2) improves the ISO feedback loop’s phase margin (stability) by making the output load resistive at higher frequencies. The R ≥(---m----a---x---i-m-----u---m---- --e--x---p---e---c--t--e---d--- -V----I--N----)---–-----V----D---D--- bandwidth will be generally lower than the bandwidth IN 2 mA with no capacitive load. V –(minimum expected V ) R ≥----S---S-------------------------------------------------------------I--N----- IN 2 mA + RISO MCP60X V OUT FIGURE 3-1: R limits the current flow IN – into an input pin. CL 3.2 Rail-to-Rail Output RG RF There are two specifications that describe the output FIGURE 3-2: Output resistor R ISO swing capability of the MCP601/2/3/4 family of op amps. stabilizes large capacitive loads. The first specification (Maximum Output Voltage Swing) defines the absolute maximum swing that can be Figure3-3 gives recommended RISO values for achieved under the specified load conditions. For different capacitive loads and gains. The x-axis is the instance, the output voltage swings to within 15mV of normalized load capacitance (CL/GN) in order to make the negative rail with a 25kΩ load to VDD/2. Figure2-33 it easier to interpret the plot for arbitrary gains. GN is the shows how the output voltage is limited when the input circuit’s noise gain. For non-inverting gains, GN and the goes beyond the linear region of operation. gain are equal. For inverting gains, GN = 1 + |Gain| (e.g., -1V/V gives G = +2V/V). N  2004 Microchip Technology Inc. DS21314F-page 11

MCP601/2/3/4 1. Connect the guard ring to the inverting input pin 1k1,000 (VIN–) for non-inverting gain amplifiers, includ- ing unity-gain buffers. This biases the guard ring )(cid:58) to the common mode input voltage. (O RIS 2. Connect the guard ring to the non-inverting input ended 100100 GN = +1 ptriann s(iVmINp+ed) afnocre ianmveprtliifniegr sg (acionn vaemrtps licfiuerrrse nat ntdo mm GN (cid:116) +2 voltage, such as photo detectors). This biases co the guard ring to the same reference voltage as e R the op amp (e.g., V /2 or ground). DD 10 110010p 101000p 11,0n00 1010,00n0 3.7 Typical Applications Normalized Load Capacitance; C / G (F) L N 3.7.1 ANALOG FILTERS FIGURE 3-3: Recommended R values ISO for capacitive loads. Figure3-5 and Figure3-6 show low-pass, second- order, Butterworth filters with a cutoff frequency of Once you’ve selected R for your circuit, double- ISO 10Hz. The filter in Figure3-5 has a non-inverting gain check the resulting frequency response peaking and of +1V/V, and the filter in Figure3-6 has an inverting step response overshoot in your circuit. Evaluation on gain of -1V/V. the bench and simulations with the MCP601/2/3/4 SPICE macro model are very helpful. Modify R ’s ISO value until the response is reasonable. C G = +1V/V 1 47nF fP = 10Hz 3.5 Supply Bypass With this family of op amps, the power supply pin (VDD R1 R2 for single-supply) should have a local bypass capacitor 382kΩ 641kΩ (i.e., 0.01µF to 0.1µF) within 2mm for good high-fre- V + IN quency performance. It also needs a bulk capacitor (i.e., 1µF or larger) within 100mm to provide large, C2 MCP60X VOUT 22nF slow currents. This bulk capacitor can be shared with – other parts. 3.6 PCB Surface Leakage FIGURE 3-5: Second-Order, Low-Pass Sallen-Key Filter. In applications where low input bias current is critical, printed circuit board (PCB) surface leakage effects need to be considered. Surface leakage is caused by G = -1V/V R humidity, dust or other contamination on the board. 2 618kΩ fP = 10Hz Under low humidity conditions, a typical resistance between nearby traces is 1012Ω. A 5V difference would cause 5pA of current to flow. This is greater R R C 1 3 1 than the MCP601/2/3/4 family’s bias current at +25°C 618kΩ 1.00MΩ 8.2nF (1pA, typ.). V V IN OUT The easiest way to reduce surface leakage is to use a C 2 + guard ring around sensitive pins (or traces). The guard 47nF ring is biased at the same voltage as the sensitive pin. MCP60X An example of this type of layout is shown in V /2 – Figure3-4. DD FIGURE 3-6: Second-Order, Low-Pass Guard Ring V V IN– IN+ Multiple-Feedback Filter. The MCP601/2/3/4 family of op amps have low input bias current, which allows the designer to select larger resistor values and smaller capacitor values for these filters. This helps produce a compact PCB layout. These filters, and others, can be designed using FIGURE 3-4: Example Guard Ring layout. Microchip’s FilterLab® software. DS21314F-page 12  2004 Microchip Technology Inc.

MCP601/2/3/4 3.7.2 INSTRUMENTATION AMPLIFIER 3.7.3 PHOTO DETECTION CIRCUITS The MCP601/2/3/4 op amps can be used to easily Instrumentation amplifiers have a differential input that convert the signal from a sensor that produces an subtracts one input voltage from another and rejects output current (such as a photo diode) into a voltage (a common mode signals. These amplifiers also provide a transimpedance amplifier). This is implemented with a single-ended output voltage. single resistor (R2) in the feedback loop of the amplifiers shown in Figure3-9 and Figure3-10. The The three-op amp instrumentation amplifier is illustrated optional capacitor (C ) sometimes provides stability for in Figure3-7. One advantage of this approach is unity- 2 these circuits. gain operation, while one disadvantage is that the common mode input range is reduced as R /R gets A photodiode configured in the Photovoltaic mode has 2 G larger. zero voltage potential placed across it (Figure3-9). In this mode, the light sensitivity and linearity is maximized, making it best suited for precision V1 + R R applications. The key amplifier specifications for this 3 4 MCP60X application are: low input bias current, low noise, – – common mode input voltage range (including ground) and rail-to-rail output. MCP60X V OUT R R 2 + C G 2 R R R 2 3 4 R 2 – V MCP60X VREF ID1 V OUT DD V2 + D – 1 Light MCP60X VOUT = (V1–V2)1+2-R---R----2-RR----4-- +VREF + G 3 V = I R OUT D1 2 FIGURE 3-7: Three-Op Amp Instrumentation Amplifier. FIGURE 3-9: Photovoltaic Mode Detector. The two-op amp instrumentation amplifier is shown in In contrast, a photodiode that is configured in the Figure3-8. While its power consumption is lower than Photoconductive mode has a reverse bias voltage the three-op amp version, its main drawbacks are that across the photo-sensing element (Figure3-10). This the common mode range is reduced with higher gains decreases the diode capacitance, which facilitates and it must be configured in gains of two or higher. high-speed operation (e.g., high-speed digital communications). The design trade-off is increased R diode leakage current and linearity errors. The op amp G V needs to have a wide Gain Bandwidth Product OUT R R R R (GBWP). 1 2 2 1 - - C 2 V REF MCP60X MCP60X V + + R 2 2 ID1 VOUT V1 VDD – VOUT = (V1–V2)1+R-R---1--+2--R--R----1- +VREF Light D1 MCP60X 2 G V + V = I R BIAS OUT D1 2 FIGURE 3-8: Two-Op Amp V < 0V BIAS Instrumentation Amplifier. Both instrumentation amplifiers should use a bulk FIGURE 3-10: Photoconductive Mode bypass capacitor of at least 1µF. The CMRR of these Detector. amplifiers will be set by both the op amp CMRR and resistor matching.  2004 Microchip Technology Inc. DS21314F-page 13

MCP601/2/3/4 4.0 DESIGN TOOLS Microchip provides the basic design tools needed for the MCP601/2/3/4 family of op amps. 4.1 SPICE Macro Model The latest SPICE macro model of the MCP601/2/3/4 op amps is available on Microchip’s web site at www.microchip.com. This model is intended as an initial design tool that works well in the op amp’s linear region of operation at room temperature. See the SPICE model firmware for information on its capabilities. Bench testing is a very important part of any design and cannot be replaced with simulations. Also, simulation results using this macro model need to be validated by comparing them to the data sheet specs and plots. 4.2 FilterLab® 2.0 FilterLab® 2.0 is an innovative software tool that simplifies analog active-filter (using op amps) design. Available at no cost from Microchip’s web site at www.microchip.com, the FilterLab active-filter software design tool provides full schematic diagrams of the filter circuit with component values. It also outputs the filter circuit in SPICE format, which can be used with the macro model to simulate actual filter performance. DS21314F-page 14  2004 Microchip Technology Inc.

MCP601/2/3/4 5.0 PACKAGING INFORMATION 5.1 Package Marking Information 5-Lead SOT-23 (MCP601 and MCP601R Only) Example: XXNN 04NN 6-Lead SOT-23A (MCP603 Only) Example: XXNN 04NN Legend: XX...X Customer specific information* YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard OTP marking consists of Microchip part number, year code, week code, and traceability code.  2004 Microchip Technology Inc. DS21314F-page 15

MCP601/2/3/4 Package Marking Information 8-Lead PDIP (300 mil) Example: XXXXXXXX MCP601 XXXXXNNN I/P256 YYWW 0424 8-Lead SOIC (150 mil) Example: XXXXXXXX MCP601 XXXXYYWW I/SN0324 NNN 256 8-Lead TSSOP Example: XXXX 601 XYWW I324 NNN 256 14-Lead PDIP (300 mil) (MCP604 Only) Example: XXXXXXXXXXXXXX MCP604-I/P XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN 0424256 14-Lead SOIC (150 mil) (MCP604 Only) Example: XXXXXXXXXXX MCP604ISL XXXXXXXXXXX XXXXXXXXXXX YYWWNNN 0424256 14-Lead TSSOP (4.4mm) (MCP604 Only) Example: XXXXXXXX 604I YYWW 0324 NNN 256 DS21314F-page 16  2004 Microchip Technology Inc.

MCP601/2/3/4 5-Lead Plastic Small Outline Transistor (OT) (SOT-23) E E1 p B p1 D n 1 α c A A2 φ A1 β L Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 5 5 Pitch p .038 0.95 Outside lead pitch (basic) p1 .075 1.90 Overall Height A .035 .046 .057 0.90 1.18 1.45 Molded Package Thickness A2 .035 .043 .051 0.90 1.10 1.30 Standoff § A1 .000 .003 .006 0.00 0.08 0.15 Overall Width E .102 .110 .118 2.60 2.80 3.00 Molded Package Width E1 .059 .064 .069 1.50 1.63 1.75 Overall Length D .110 .116 .122 2.80 2.95 3.10 Foot Length L .014 .018 .022 0.35 0.45 0.55 Foot Angle φ 0 5 10 0 5 10 Lead Thickness c .004 .006 .008 0.09 0.15 0.20 Lead Width B .014 .017 .020 0.35 0.43 0.50 Mold Draft Angle Top α 0 5 10 0 5 10 Mold Draft Angle Bottom β 0 5 10 0 5 10 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-178 Drawing No. C04-091  2004 Microchip Technology Inc. DS21314F-page 17

MCP601/2/3/4 6-Lead Plastic Small Outline Transistor (CH) (SOT-23) E E1 B p1 D n 1 α c A A2 φ A1 L β Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 6 6 Pitch p .038 0.95 Outside lead pitch (basic) p1 .075 1.90 Overall Height A .035 .046 .057 0.90 1.18 1.45 Molded Package Thickness A2 .035 .043 .051 0.90 1.10 1.30 Standoff A1 .000 .003 .006 0.00 0.08 0.15 Overall Width E .102 .110 .118 2.60 2.80 3.00 Molded Package Width E1 .059 .064 .069 1.50 1.63 1.75 Overall Length D .110 .116 .122 2.80 2.95 3.10 Foot Length L .014 .018 .022 0.35 0.45 0.55 Foot Angle φ 0 5 10 0 5 10 Lead Thickness c .004 .006 .008 0.09 0.15 0.20 Lead Width B .014 .017 .020 0.35 0.43 0.50 Mold Draft Angle Top α 0 5 10 0 5 10 Mold Draft Angle Bottom β 0 5 10 0 5 10 *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. JEITA (formerly EIAJ) equivalent: SC-74A Drawing No. C04-120 DS21314F-page 18  2004 Microchip Technology Inc.

MCP601/2/3/4 8-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n 1 α E A A2 L c A1 β B1 p eB B Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch p .100 2.54 Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32 Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26 Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60 Overall Length D .360 .373 .385 9.14 9.46 9.78 Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43 Lead Thickness c .008 .012 .015 0.20 0.29 0.38 Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78 Lower Lead Width B .014 .018 .022 0.36 0.46 0.56 Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92 Mold Draft Angle Top α 5 10 15 5 10 15 Mold Draft Angle Bottom β 5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018  2004 Microchip Technology Inc. DS21314F-page 19

MCP601/2/3/4 8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 h α 45° c A A2 φ β L A1 Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch p .050 1.27 Overall Height A .053 .061 .069 1.35 1.55 1.75 Molded Package Thickness A2 .052 .056 .061 1.32 1.42 1.55 Standoff § A1 .004 .007 .010 0.10 0.18 0.25 Overall Width E .228 .237 .244 5.79 6.02 6.20 Molded Package Width E1 .146 .154 .157 3.71 3.91 3.99 Overall Length D .189 .193 .197 4.80 4.90 5.00 Chamfer Distance h .010 .015 .020 0.25 0.38 0.51 Foot Length L .019 .025 .030 0.48 0.62 0.76 Foot Angle φ 0 4 8 0 4 8 Lead Thickness c .008 .009 .010 0.20 0.23 0.25 Lead Width B .013 .017 .020 0.33 0.42 0.51 Mold Draft Angle Top α 0 12 15 0 12 15 Mold Draft Angle Bottom β 0 12 15 0 12 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057 DS21314F-page 20  2004 Microchip Technology Inc.

MCP601/2/3/4 8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP) E E1 p D 2 1 n B α A c φ A1 A2 β L Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch p .026 0.65 Overall Height A .043 1.10 Molded Package Thickness A2 .033 .035 .037 0.85 0.90 0.95 Standoff § A1 .002 .004 .006 0.05 0.10 0.15 Overall Width E .246 .251 .256 6.25 6.38 6.50 Molded Package Width E1 .169 .173 .177 4.30 4.40 4.50 Molded Package Length D .114 .118 .122 2.90 3.00 3.10 Foot Length L .020 .024 .028 0.50 0.60 0.70 Foot Angle φ 0 4 8 0 4 8 Lead Thickness c .004 .006 .008 0.09 0.15 0.20 Lead Width B .007 .010 .012 0.19 0.25 0.30 Mold Draft Angle Top α 0 5 10 0 5 10 Mold Draft Angle Bottom β 0 5 10 0 5 10 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005” (0.127mm) per side. JEDEC Equivalent: MO-153 Drawing No. C04-086  2004 Microchip Technology Inc. DS21314F-page 21

MCP601/2/3/4 14-Lead Plastic Dual In-line (P) –300 mil (PDIP) E1 D 2 n 1 α E A A2 c L A1 β B1 eB B p Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 14 14 Pitch p .100 2.54 Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32 Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26 Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60 Overall Length D .740 .750 .760 18.80 19.05 19.30 Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43 Lead Thickness c .008 .012 .015 0.20 0.29 0.38 Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78 Lower Lead Width B .014 .018 .022 0.36 0.46 0.56 Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92 Mold Draft Angle Top α 5 10 15 5 10 15 Mold Draft Angle Bottom β 5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-005 DS21314F-page 22  2004 Microchip Technology Inc.

MCP601/2/3/4 14-Lead Plastic Small Outline (SL) –Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 α h 45° c A A2 φ A1 L β Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 14 14 Pitch p .050 1.27 Overall Height A .053 .061 .069 1.35 1.55 1.75 Molded Package Thickness A2 .052 .056 .061 1.32 1.42 1.55 Standoff § A1 .004 .007 .010 0.10 0.18 0.25 Overall Width E .228 .236 .244 5.79 5.99 6.20 Molded Package Width E1 .150 .154 .157 3.81 3.90 3.99 Overall Length D .337 .342 .347 8.56 8.69 8.81 Chamfer Distance h .010 .015 .020 0.25 0.38 0.51 Foot Length L .016 .033 .050 0.41 0.84 1.27 Foot Angle φ 0 4 8 0 4 8 Lead Thickness c .008 .009 .010 0.20 0.23 0.25 Lead Width B .014 .017 .020 0.36 0.42 0.51 Mold Draft Angle Top α 0 12 15 0 12 15 Mold Draft Angle Bottom β 0 12 15 0 12 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-065  2004 Microchip Technology Inc. DS21314F-page 23

MCP601/2/3/4 14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP) E E1 p D 2 n 1 B α A c φ β A1 A2 L Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 14 14 Pitch p .026 0.65 Overall Height A .043 1.10 Molded Package Thickness A2 .033 .035 .037 0.85 0.90 0.95 Standoff § A1 .002 .004 .006 0.05 0.10 0.15 Overall Width E .246 .251 .256 6.25 6.38 6.50 Molded Package Width E1 .169 .173 .177 4.30 4.40 4.50 Molded Package Length D .193 .197 .201 4.90 5.00 5.10 Foot Length L .020 .024 .028 0.50 0.60 0.70 Foot Angle φ 0 4 8 0 4 8 Lead Thickness c .004 .006 .008 0.09 0.15 0.20 Lead Width B .007 .010 .012 0.19 0.25 0.30 Mold Draft Angle Top α 0 5 10 0 5 10 Mold Draft Angle Bottom β 0 5 10 0 5 10 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005” (0.127mm) per side. JEDEC Equivalent: MO-153 Drawing No. C04-087 DS21314F-page 24  2004 Microchip Technology Inc.

MCP601/2/3/4 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Examples: PART NO. X /XX a) MCP601-I/P: Single Op Amp, Device Temperature Package Industrial Temperature, Range 8LD PDIP package. b) MCP601-E/SN: Single Op Amp, Extended Temperature, 8LD SOIC package. Device MCP601 Single Op Amp c) MCP601T-I/OT: Tape and Reel, MCP601T Single Op Amp Industrial Temperature, (Tape and Reel for SOT23, SOIC and TSSOP) Single Op Amp, MCP601RTSingle Op Amp 5-LD SOT23 package. (Tape and Reel for SOT23-5) d) MCP601T-E/ST: Tape and Reel, MCP602 Dual Op Amp Extended Temperature, MCP602T Dual Op Amp Single Op Amp, (Tape and Reel for SOIC and TSSOP) 8LD TSSOP package MCP603 Single Op Amp with Chip Select MCP603T Single Op Amp with Chip Select e) MCP601RT-E/OT: Tape and Reel, (Tape and Reel for SOT23, SOIC and TSSOP) Extended Temperature, MCP604 Quad Op Amp Single Op Amp, Rotated, MCP604T Quad Op Amp 5-LD SOT23 package. (Tape and Reel for SOIC and TSSOP) a) MCP602-I/SN: Dual Op Amp, Industrial Temperature, Temperature Range I = -40°C to +85°C 8LD SOIC package. E = -40°C to +125°C b) MCP602-E/P: Dual Op Amp, Extended Temperature, 8LD PDIP package. Package OT = Plastic SOT23, 5-lead (MCP601 only) c) MCP602T-E/ST: Tape and Reel, CH = Plastic SOT23, 6-lead (MCP603 only) Extended Temperature, P = Plastic DIP (300 mil Body), 8, 14-lead Dual Op Amp, SN = Plastic SOIC (150 mil Body), 8-lead 8LD TSSOP package. SL = Plastic SOIC (150 mil Body), 14-lead ST = Plastic TSSOP (4.4mm Body), 8, 14-lead a) MCP603-I/SN: Industrial Temperature, Single Op Amp with Chip Select,8LD SOIC package. b) MCP603-E/P: Extended Temperature, Single Op Amp with Chip Select, 8LD PDIP package. c) MCP603T-E/ST: Tape and Reel, Extended Temperature, Single Op Amp with Chip Select, 8LD TSSOP package. d) MCP603T-I/SN: Tape and Reel, Industrial Temperature, Single Op Amp with Chip Select, 8LD SOIC package. a) MCP604-I/P: Industrial Temperature, Quad Op Amp, 14LD PDIP package. b) MCP604-E/SL: Extended Temperature, Quad Op Amp, 14LD SOIC package. c) MCP604T-I/ST: Tape and Reel, Industrial Temperature, Quad Op Amp, 14LD TSSOP package. Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office 2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 3. The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.  2004 Microchip Technology Inc. DS21314F-page 25

MCP601/2/3/4 NOTES: DS21314F-page 26  2004 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is intended through suggestion only The Microchip name and logo, the Microchip logo, Accuron, and may be superseded by updates. It is your responsibility to dsPIC, KEELOQ, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. PROMATE, PowerSmart and rfPIC are registered No representation or warranty is given and no liability is trademarks of Microchip Technology Incorporated in the assumed by Microchip Technology Incorporated with respect U.S.A. and other countries. to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such AmpLab, FilterLab, microID, MXDEV, MXLAB, PICMASTER, use or otherwise. Use of Microchip’s products as critical SEEVAL, SmartShunt and The Embedded Control Solutions components in life support systems is not authorized except Company are registered trademarks of Microchip Technology with express written approval by Microchip. No licenses are Incorporated in the U.S.A. conveyed, implicitly or otherwise, under any intellectual Application Maestro, dsPICDEM, dsPICDEM.net, property rights. dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, Select Mode, SmartSensor, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2004, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company’s quality system processes and procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS21314F-page 27  2004 Microchip Technology Inc.

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: MCP604-I/SL MCP602-E/P MCP604-I/P MCP603-I/P MCP601-E/P MCP604-E/P MCP601-I/P MCP603T-I/CH MCP603T-I/SN MCP602T-I/SN MCP601T-I/ST MCP603T-I/ST MCP601T-I/SN MCP604T-I/ST MCP604T-I/SL MCP601T-I/OT MCP602T-I/ST MCP602-E/SN MCP602-E/ST MCP603-E/P MCP604-E/ST MCP604-E/SL MCP602-I/SN MCP601-E/SN MCP601-E/ST MCP603-E/SN MCP603-E/ST MCP601RT-E/OT MCP602-I/ST MCP601-I/ST MCP601-I/SN MCP601RT-I/OT MCP603-I/ST MCP603-I/SN MCP602-I/P MCP602T-E/ST MCP602T- E/SN MCP604T-E/SL MCP601T-E/ST MCP603T-E/ST MCP604T-E/ST MCP601T-E/SN MCP603T-E/SN MCP601T-E/OT