MCP4921/4922 12-Bit DAC with SPI™ Interface Features Description • 12-Bit Resolution The Microchip Technology Inc. MCP492X are 2.7– (cid:127) ±0.2 LSB DNL (typ) 5.5V, low-power, low DNL, 12-Bit Digital-to-Analog Con- verters (DACs) with optional 2x buffered output and SPI (cid:127) ±2 LSB INL (typ) interface. (cid:127) Single or Dual Channel The MCP492X are DACs that provide high accuracy (cid:127) Rail-to-Rail Output and low noise performance for industrial applications (cid:127) SPI™ Interface with 20MHz Clock Support where calibration or compensation of signals (such as (cid:127) Simultaneous Latching of the Dual DACs w/LDAC temperature, pressure and humidity) are required. (cid:127) Fast Settling Time of 4.5µs The MCP492X are available in the extended tempera- (cid:127) Selectable Unity or 2x Gain Output ture range and PDIP, SOIC, MSOP and TSSOP (cid:127) 450kHz Multiplier Mode packages. (cid:127) External V Input The MCP492X devices utilize a resistive string archi- REF tecture, with its inherent advantages of low DNL error, (cid:127) 2.7V to 5.5V Single-Supply Operation low ratio metric temperature coefficient and fast settling (cid:127) Extended Temperature Range:-40°C to +125°C time. These devices are specified over the extended Applications temperature range. The MCP492X include double- buffered inputs, allowing simultaneous updates using (cid:127) Set Point or Offset Trimming the LDAC pin. These devices also incorporate a (cid:127) Sensor Calibration Power-On Reset (POR) circuit to ensure reliable (cid:127) Digitally-Controlled Multiplier/Divider power-up. (cid:127) Portable Instrumentation (Battery-Powered) Package Types (cid:127) Motor Feedback Loop Control 8-Pin PDIP, SOIC, MSOP Block Diagram VDD 1 M 8 VOUTA CS SDI SCK LDAC CS 2 C 7 AVSS P Interface Logic Po wer-on VDD SSCDKI 34 4921 65 VLDREAFCA Reset AVSS Input Input 14-Pin PDIP, SOIC, TSSOP Register A Register B VDD 1 14VOUTA DACA DACB NC 2 M 13VREFA Register Register CS 3 C 12AVSS VRE AF String String VBREF SCK 4 P49 11 VREFB DACA DACB SDI 5 22 10VOUTB Buffer NC 6 9 SHDN Buffer NC 7 8 LDAC Gain Gain Logic Output Logic Op Amps Output Logic VOUTA SHDN VOUTB  2004 Microchip Technology Inc. DS21897A-page 1

MCP4921/4922 1.0 ELECTRICAL † Notice: Stresses above those listed under “Maximum Rat- ings” may cause permanent damage to the device. This is a CHARACTERISTICS stress rating only and functional operation of the device at those or any other conditions above those indicated in the Absolute Maximum Ratings † operational listings of this specification is not implied. Expo- sure to maximum rating conditions for extended periods may VDD............................................................................................................. 6.5V affect device reliability. All inputs and outputs w.r.t .............AV –0.3V to V +0.3V SS DD Current at Input Pins ....................................................±2mA Current at Supply Pins ...............................................±50mA Current at Output Pins ...............................................±25mA Storage temperature.....................................-65°C to +150°C Ambient temp. with power applied................-55°C to +125°C ESD protection on all pins ...........≥ 4kV (HBM), ≥ 400V (MM) Maximum Junction Temperature (T )..........................+150°C J 5V AC/DC CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, V = 5V, AV = 0V, V = 2.048V, output buffer gain (G) = 2x, R = 5kΩ DD SS REF L to GND, C = 100pF T = -40 to +85°C. Typical values at +25°C. L A Parameters Sym Min Typ Max Units Conditions Power Requirements Input Voltage V 2.7 — 5.5 DD Input Current - MCP4921 I — 175 350 µA Input unbuffered, digital inputs DD Input Current - MCP4922 — 350 700 grounded, output unloaded, code at 0x000 Hardware Shutdown Current I — 0.3 2 µA SHDN Software Shutdown Current I — 3.3 6 µA SHDN_SW Power-on-Reset Threshold V — 2.0 — V POR DC Accuracy Resolution n 12 — — Bits INL Error INL -12 2 12 LSB DNL DNL -0.75 ±0.2 +0.75 LSB Device is Monotonic Offset Error V — ±0.02 1 % of FSR Code 0x000h OS Offset Error Temperature V /°C — 0.16 — ppm/°C -45°C to 25°C OS Coefficient — -0.44 — ppm/°C +25°C to 85°C Gain Error g — -0.10 1 % of FSR Code 0xFFFh, not including offset E error. ∆ Gain Error Temperature G/°C — -3 — ppm/°C Coefficient Input Amplifier (V Input) REF Input Range - Buffered Mode V 0.040 — V – 0.040 V Note1 REF DD Input Range - Unbuffered V 0 — V V Code = 2048 REF DD Mode VREF = 0.2v p-p, f = 100Hz and 1kHz Input Impedance R — 165 — kΩ Unbuffered Mode VREF Input Capacitance - C — 7 — pF VREF Unbuffered Mode Multiplier Mode f — 450 — kHz V = 2.5V ±0.2Vp-p, Unbuffered, VREF REF -3dB Bandwidth G = 1 f — 400 — kHz V = 2.5V ±0.2 Vp-p, Unbuffered, VREF REF G = 2 Multiplier Mode - THD — -73 — dB V = 2.5V ±0.2Vp-p, VREF REF Total Harmonic Distortion Frequency = 1kHz Note 1: By design, not production tested. 2: Too small to quantify. DS21897A-page 2  2004 Microchip Technology Inc.

MCP4921/4922 5V AC/DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, V = 5V, AV = 0V, V = 2.048V, output buffer gain (G) = 2x, R = 5kΩ DD SS REF L to GND, C = 100pF T = -40 to +85°C. Typical values at +25°C. L A Parameters Sym Min Typ Max Units Conditions Output Amplifier Output Swing V — 0.010 — Accuracy is better than 1 LSB for OUT to V V = 10mV to (V – 40mV) DD OUT DD – 0.040 θ Phase Margin m — 66 — degrees Slew Rate SR — 0.55 — V/µs Short Circuit Current I — 15 24 mA SC Settling Time t — 4.5 — µs Within 1/2 LSB of final value from 1/4 settling to 3/4 full-scale range Dynamic Performance DAC-to-DAC Crosstalk — 10 — nV-s Note2 Major Code Transition Glitch — 45 — nV-s 1 LSB change around major carry (0111...1111 to 1000...0000) Digital Feedthrough — 10 — nV-s Note2 Analog Crosstalk — 10 — nV-s Note2 Note 1: By design, not production tested. 2: Too small to quantify. 3V AC/DC CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, V = 3V, AV = 0V, V = 2.048V external, output buffer gain (G) = 1x, DD SS REF R = 5kΩ to GND, C = 100pF T = -40 to +85°C. Typical values at 25°C L L A Parameters Sym Min Typ Max Units Conditions Power Requirements Input Voltage V 2.7 — 5.5 DD Input Current - MCP4921 I — 125 250 µA Input unbuffered, digital inputs DD Input Current - MCP4922 — 250 500 grounded, output unloaded, code at 0x000 Hardware Shutdown Current I — 0.25 2 µA SHDN Software Shutdown Current I — 2 6 µA SHDN_SW Power-On Reset threshold V — 2.0 — V POR DC Accuracy Resolution n 12 — — Bits INL Error INL -12 ±3 +12 LSB DNL DNL -0.75 ±0.3 +0.75 LSB Device is Monotonic Offset Error V — ±0.02 1 % of FSR Code 0x000h OS Offset Error Temperature V /°C — 0.5 — ppm/°C -45°C to 25°C OS Coefficient — -0.77 — ppm/°C +25°C to 85°C Gain Error g — -0.15 1 % of FSR Code 0xFFFh, not including offset E error. ∆ Gain Error Temperature G/°C — -3 — ppm/°C Coefficient Input Amplifier (V Input) REF Input Range - Buffered Mode V 0.040 — V -0.040 V Note1 REF DD Input Range - Unbuffered V 0 — V V Code = 2048, REF DD Mode VREF = 0.2v p-p, f = 100Hz and 1kHz Input Impedance R — 165 — kΩ Unbuffered Mode VREF Note 1: By design, not production tested. 2: Too small to quantify.  2004 Microchip Technology Inc. DS21897A-page 3

MCP4921/4922 3V AC/DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, V = 3V, AV = 0V, V = 2.048V external, output buffer gain (G) = 1x, DD SS REF R = 5kΩ to GND, C = 100pF T = -40 to +85°C. Typical values at 25°C L L A Parameters Sym Min Typ Max Units Conditions Input Capacitance – C — 7 — pF VREF Unbuffered Mode Multiplier Mode f — 440 — kHz V = 2.048V ±0.1Vp-p, unbuffered, VREF REF -3dB Bandwidth G = 1 f — 390 — kHz V = 2.048V ±0.1Vp-p, unbuffered, VREF REF G = 2 Multiplier Mode – THD — -73 — dB V = 2.5V ±0.1Vp-p, VREF REF Total Harmonic Distortion Frequency = 1kHz Output Amplifier Output Swing V — 0.010 — Accuracy is better than 1LSB for OUT to V V = 10mV to (V – 40mV) DD OUT DD – 0.040 θ Phase Margin m — 66 — degrees Slew Rate SR — 0.55 — V/µs Short Circuit Current I — 14 24 mA SC Settling Time t — 4.5 — µs Within 1/2 LSB of final value from 1/4 settling to 3/4 full-scale range Dynamic Performance DAC-to-DAC Crosstalk — 10 — nV-s Note2 Major Code Transition Glitch — 45 — nV-s 1 LSB change around major carry (0111...1111 to 1000...0000) Digital Feedthrough — 10 — nV-s Note2 Analog Crosstalk — 10 — nV-s Note2 Note 1: By design, not production tested. 2: Too small to quantify. 5V EXTENDED TEMPERATURE SPECIFICATIONS Electrical Specifications: Unless otherwise indicated, V = 5V, AV = 0V, V = 2.048V, output buffer gain (G) = 2x, R = 5kΩ DD SS REF L to GND, C = 100pF. Typical values at +125°C by characterization or simulation. L Parameters Sym Min Typ Max Units Conditions Power Requirements Input Voltage V 2.7 — 5.5 DD Input Current - MCP4921 I — 200 — µA Input unbuffered, digital inputs DD Input Current - MCP4922 — 400 — grounded, output unloaded, code at 0x000 Hardware Shutdown Current I — 1.5 — µA SHDN Software Shutdown Current I — 5 — µA SHDN_SW Power-On Reset threshold V — 1.85 — V POR DC Accuracy Resolution n 12 — — Bits INL Error INL — ±4 — LSB DNL DNL — ±0.25 — LSB Device is Monotonic Offset Error V — ±0.02 — % of FSR Code 0x000h OS Offset Error Temperature V /°C — -5 — ppm/°C +25°C to +125°C OS Coefficient Note 1: By design, not production tested. 2: Too small to quantify. DS21897A-page 4  2004 Microchip Technology Inc.

MCP4921/4922 5V EXTENDED TEMPERATURE SPECIFICATIONS (CONTINUED) Electrical Specifications: Unless otherwise indicated, V = 5V, AV = 0V, V = 2.048V, output buffer gain (G) = 2x, R = 5kΩ DD SS REF L to GND, C = 100pF. Typical values at +125°C by characterization or simulation. L Parameters Sym Min Typ Max Units Conditions Gain Error g — -0.10 — % of FSR Code 0xFFFh, not including offset E error ∆ Gain Error Temperature G/°C — -3 — ppm/°C Coefficient Input Amplifier (V Input) REF Input Range - Buffered Mode V — 0.040 to — V Note1 REF V - Code = 2048, DD 0.040 V = 0.2v p-p, f = 100Hz and 1kHz REF Input Range - Unbuffered V 0 — V V REF DD Mode Input Impedance R — 174 — kΩ Unbuffered Mode VREF Input Capacitance - C — 7 — pF VREF Unbuffered Mode Multiplying Mode f — 450 — kHz V = 2.5V ±0.1Vp-p, Unbuffered, VREF REF -3dB Bandwidth G=1 f — 400 — kHz V = 2.5V ±0.1Vp-p, Unbuffered, VREF REF G = 2 Multiplying Mode - Total THD — — — dB V = 2.5V ±0.1Vp-p, VREF REF Harmonic Distortion Frequency = 1kHz Output Amplifier Output Swing V — 0.010 to — Accuracy is better than 1LSB for OUT V – V = 10mV to (V – 40mV) DD OUT DD 0.040 θ Phase Margin m — 66 — degrees Slew Rate SR — 0.55 — V/µs Short Circuit Current I — 17 — mA SC Settling Time t — 4.5 — µs Within 1/2 LSB of final value from 1/4 settling to 3/4 full-scale range Dynamic Performance DAC to DAC Crosstalk — 10 — nV-s Note2 Major Code Transition Glitch — 45 — nV-s 1 LSB change around major carry (0111...1111 to 1000...0000) Digital Feedthrough — 10 — nV-s Note2 Analog Crosstalk — 10 — nV-s Note2 Note 1: By design, not production tested. 2: Too small to quantify.  2004 Microchip Technology Inc. DS21897A-page 5

MCP4921/4922 AC CHARACTERISTICS (SPI TIMING SPECIFICATIONS) Electrical Specifications: Unless otherwise indicated, V = 2.7V – 5.5V, T = -40 to +125°C. DD A Typical values are at +25°C. Parameters Sym Min Typ Max Units Conditions Schmitt Trigger High-Level V 0.7V — — V IH DD Input Voltage (All digital input pins) Schmitt Trigger Low-Level V — — 0.2V V IL D Input Voltage D (All digital input pins) Hysteresis of Schmitt Trigger V — 0.05V — HYS DD Inputs Input Leakage Current I -1 — 1 µA SHDN = LDAC = CS = SDI = LEAKAGE SCK + V = V or AV REF DD SS Digital Pin Capacitance C , — 10 — pF V = 5.0V, T = +25°C, IN DD A (All inputs/outputs) C f = 1MHz (Note1) OUT cLK Clock Frequency F — — 20 MHz T = +25°C (Note1) CLK A Clock High Time t 15 — — ns Note1 HI Clock Low Time t 15 — — ns Note1 LO CS Fall to First Rising CLK t 40 — — ns Applies only when CS falls with CSSR Edge CLK high. (Note1) Data Input Setup Time t 15 — — ns Note1 SU Data Input Hold Time t 10 — — ns Note1 HD SCK Rise to CS Rise Hold t 15 — — ns Note1 CHS Time CS High Time t 15 — — ns Note1 CSH LDAC Pulse Width t 100 — — ns Note1 LD LDAC Setup Time t 40 — — ns Note1 LS SCK Idle Time before CS Fall t 40 — — ns Note1 IDLE Note 1: By design and characterization, not production tested. t CSH CS t IDLE tCSSR tHI tLO tCHS Mode 1,1 SCKMode 0,0 t t SU HD SI MSB in LSB in LDAC tLS tLD FIGURE 1-1: SPI™ Input Timing. DS21897A-page 6  2004 Microchip Technology Inc.

MCP4921/4922 TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, V =+2.7V to +5.5V, AV =GND. DD SS Parameters Sym Min Typ Max Units Conditions Temperature Ranges Specified Temperature Range T -40 — +125 °C A Operating Temperature Range T -40 — +125 °C Note1 A Storage Temperature Range T -65 — +150 °C A Thermal Package Resistances Thermal Resistance, 8L-PDIP θ — 85 — °C/W JA Thermal Resistance, 8L-SOIC θ — 163 — °C/W JA Thermal Resistance, 8L-MSOP θ — 206 — °C/W JA Thermal Resistance, 14L-PDIP θ — 70 — °C/W JA Thermal Resistance, 14L-SOIC θ — 120 — °C/W JA Thermal Resistance, 14L-TSSOP θ — 100 — °C/W JA Note 1: The MCP492X family of DACs operate over this extended temperature range, but with reduced performance. Operation in this range must not cause T to exceed the Maximum Junction Temperature of J 150°C.  2004 Microchip Technology Inc. DS21897A-page 7

MCP4921/4922 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, T = +25°C, V = 5V , AV = 0V, V = 2.048V, Gain = 2, R = 5kΩ, C = 100pF. A DD SS REF L L 0.3 0.0766 0.0764 0.2 B) S 0.0762 B) 0.1 L (L 0.076 S N L (L 0 e D 0.0758 N ut 0.0756 D -0.1 ol s 0.0754 b -0.2 A 0.0752 -0.3 0.075 0 1024 2048 3072 4096 -40 -20 0 20 40 60 80 100 120 Code (Decimal) Ambient Temperature (ºC) FIGURE 2-1: DNL vs. Code. FIGURE 2-4: Absolute DNL vs. Ambient Temperature. 0.2 0.35 0.3 B) 0.1 S 0.25 L SB) NL ( 0.2 L (L 0 e D 0.15 N ut D ol 0.1 -0.1 s b A 0.05 -0.2 0 0 1024 2048 3072 4096 1 2 3 4 5 Code (Decimal) 125C 85C 25C Voltage Reference (V) FIGURE 2-2: DNL vs. Code and Ambient FIGURE 2-5: Absolute DNL vs. Voltage Temperature. Reference. 0.4 0.3 0.2 B) 0.1 S L L ( 0 DN-0.1 -0.2 -0.3 -0.4 0 1024 2048 3072 4096 Code (Decimal) 1 2 3 4 5.5 FIGURE 2-3: DNL vs. Code and V . REF Gain=1. DS21897A-page 8  2004 Microchip Technology Inc.

MCP4921/4922 Note: Unless otherwise indicated, T = +25°C, V = 5V , AV = 0V, V = 2.048V, Gain = 2, R = 5kΩ, C = 100pF. A DD SS REF L L 5 3 Ambient Temperature V 4 REF 3 125C 85 25 2 1 2 3 4 5.5 2 1 NL (LSB) -011 NL (LSB) -01 I -2 I -2 -3 -4 -3 -5 -4 0 1024 2048 3072 4096 0 1024 2048 3072 4096 Code (Decimal) Code (Decimal) FIGURE 2-6: INL vs. Code and Ambient FIGURE 2-9: INL vs. Code and V . REF Temperature. 2.5 2 2 B) 0 S ute INL (L 1.51 INL (LSB) -2 ol -4 bs 0.5 A 0 -6 -40 -20 0 20 40 60 80 100 120 0 1024 2048 3072 4096 Ambient Temperature (ºC) Code (Decimal) FIGURE 2-7: Absolute INL vs. Ambient FIGURE 2-10: INL vs. Code. Temperature. Note: Single device graph (Figure2-10) for illustration of 64 code effect. 3 B) 2.5 S L 2 L ( N e I 1.5 ut ol 1 s b A 0.5 0 1 2 3 4 5 Voltage Reference (V) FIGURE 2-8: Absolute INL vs. V . REF  2004 Microchip Technology Inc. DS21897A-page 9

MCP4921/4922 Note: Unless otherwise indicated, T = +25°C, V = 5V, AV = 0V, V = 2.048V, Gain = 2. A DD SS REF 210 5.5V 400 5.5V 5.0V 5.0V 190 4.0V 4.0V 350 3.0V 3.0V 2.7V A)170 2.7V A) VDD (µD VDD (µD300 D150 D I I 250 130 110 200 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 Ambient Temperature (°C) Ambient Temperature (ºC) FIGURE 2-11: MCP4921 I vs. Ambient FIGURE 2-14: MCP4922 I vs. Ambient DD DD Temperature and V . Temperature and V . DD DD 18 20 16 18 14 16 ce12 ce14 n n12 e10 e ccurr 8 ccurr180 O 6 O 6 4 4 2 2 0 0 3 5 7 9 1 3 5 7 9 1 3 5 7 5 5 5 5 5 5 5 5 5 5 5 5 4 4 4 4 5 5 5 5 5 6 6 6 6 1 2 3 4 5 6 7 8 9 0 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 3 3 3 I (µA) I (µA) DD DD FIGURE 2-12: MCP4921 I Histogram FIGURE 2-15: MCP4922 I Histogram DD DD (V = 2.7V). (V = 2.7V). DD DD 9 16 8 14 7 12 ce 6 ce 10 urren 45 urren 8 Occ 3 Occ 6 4 2 1 2 0 0 0 5 0 5 0 5 0 5 0 5 0 5 151 156 161 166 171 176 181 186 191 196 201 5 6 8 9 1 2 4 5 7 8 0 1 2 2 2 2 3 3 3 3 3 3 4 4 IDD (µA) IDD (µA) FIGURE 2-13: MCP4921 I Histogram FIGURE 2-16: MCP4922 I Histogram DD DD (V = 5.0V). (V = 5.0V). DD DD DS21897A-page 10  2004 Microchip Technology Inc.

MCP4921/4922 Note: Unless otherwise indicated, T = +25°C, V = 5V , AV = 0V, V = 2.048V, Gain = 2, R = 5kΩ, C = 100pF. A DD SS REF L L 2 -0.08 VDD 5.5V 5.5V 1.5 5.0V -0.1 %) I (µA)SHDN 1 432...007VVV Gain Error ( -0.12 54..00VV 0.5 VDD -0.14 32..07VV 0 -0.16 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 Ambient Temperature (ºC) Ambient Temperature (ºC) FIGURE 2-17: Hardware Shutdown FIGURE 2-20: Gain Error vs. Ambient Current vs. Ambient Temperature and V . Temperature and V . DD DD 6 4 VDD 5.5V 5 5.5V 5.0V 3.5 V) 5.0V A)4 4.0V d ( 3 I (µSHDN_SW123 V32D..07DVV V Hi ThresholIN 12..552 432...007VVV 0 1 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 Ambient Temperature (ºC) Ambient Temperature (ºC) FIGURE 2-18: Software Shutdown Current FIGURE 2-21: V High Threshold vs IN vs. Ambient Temperature and V . Ambient Temperature and V . DD DD 0.12 1.6 VDD 0.1 V) 1.5 Offset Error (%) 0000....00002468 V5D.5DV Low Threshold (N1111....12341 554...500VVV 0 VI 3.0V 5.0V 0.9 4.0V 2.7V -0.02 32..07VV 0.8 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 Ambient Temperature (ºC) Ambient Temperature (ºC) FIGURE 2-19: Offset Error vs. Ambient FIGURE 2-22: V Low Threshold vs IN Temperature and V . Ambient Temperature and V . DD DD  2004 Microchip Technology Inc. DS21897A-page 11

MCP4921/4922 Note: Unless otherwise indicated, T = +25°C, V = 5V , AV = 0V, V = 2.048V, Gain = 2, R = 5kΩ, C = 100pF. A DD SS REF L L sis (V) 122..72.5525 V55..D50DVV AV)(V)SS 000..00.000034455 V5.D5DV ystere 11.2.55 4.0V mit (Y- 0.003 5.0V V_ HINSPI 00.7.551 32..07VV LiUT_LOW 00.0.000225 432...007VVV 0.25 O V 0 0.0015 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 Ambient Temperature (ºC) Ambient Temperature (ºC) FIGURE 2-23: Input Hysteresis vs. Ambient FIGURE 2-26: V Low Limit vs. Ambient OUT Temperature and V . Temperature and V . DD DD 18 175 5.5V - VDD e 2.7V 17 5.5V ImpedancRED Ohm)116750 VDD (mA)HORTED 111456 4532....0007VVVV EF_UNBUFFE(k160 IOUT_HI_S 111123 R V 155 10 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 Ambient Temperature (ºC) Ambient Temperature (ºC) FIGURE 2-24: V Input Impedance vs. FIGURE 2-27: I High Short vs. REF OUT Ambient Temperature and V . Ambient Temperature and V . DD DD 0.045 6.0 5.5V 0.04 5.0V Y)(V)0.035 4.0V 5.0 VREF=4.0 mit (V-DD000.0..002235 32..07VV (V)OUT 34..00 Output Shorted to VDD LiHI0.015 VDD V 2.0 VOUT_00.0.0015 1.0 Output Shorted to VSS 0 0.0 -40 -20 0 20 40 60 80 100 120 0 2 4 6 8 10 12 14 16 Ambient Temperature (ºC) IOUT (mA) FIGURE 2-25: V High Limit vs. Ambient FIGURE 2-28: I vs V . Gain = 1. OUT OUT OUT Temperature and V . DD DS21897A-page 12  2004 Microchip Technology Inc.

MCP4921/4922 Note: Unless otherwise indicated, T = +25°C, V = 5V , AV = 0V, V = 2.048V, Gain = 2, R = 5kΩ, C = 100pF. A DD SS REF L L V OUT V OUT SCK LDAC LDAC Time (1µs/div) Time (1µs/div) FIGURE 2-29: V Rise Time 100%. FIGURE 2-32: V Rise Time 25% - 75% OUT OUT V OUT V OUT SCK SCK LDAC LDAC Time (1µs/div) Time (1µs/div) FIGURE 2-30: V Fall Time. FIGURE 2-33: V Rise Time Exit OUT OUT Shutdown. ) B d ( n o V ti OUT c e SCK ej R e pl p Ri LDAC Time (1µs/div) Frequency (Hz) FIGURE 2-31: V Rise Time 50%. FIGURE 2-34: PSRR vs. Frequency. OUT  2004 Microchip Technology Inc. DS21897A-page 13

MCP4921/4922 Note: Unless otherwise indicated, T = +25°C, V = 5V , AV = 0V, V = 2.50V, Gain = 2, R = 5kΩ, C = 100pF. A DD SS REF L L 0 D = 160 D = 416 0 D = 160 D = 672 D = 416 D = 672 -45 D = 928 -2 D = 928 D = 1184 on (dB) -4 DDDD ==== 1111146984954062 – qVOUT -90 DDD === 111469495062 ati -6 D = 2208 EF D = 2208 Attenu -8 DDD === 222479627406 qVR-135 DDD === 222479627406 D = 3232 -10 D = 3488 D = 3232 D = 3744 D = 3488 -12 -180 D = 3744 100 1,000 100 1,000 Frequency (kHz) Frequency (kHz) FIGURE 2-35: Multiplier Mode Bandwidth. FIGURE 2-37: Phase Shift. Figure 2-35 calculation: Attenuation (dB) = 20 log (V /V ) – 20 log (G(D/4096)) OUT REF 600 580 560 Hz) 540 h (k 520 dt 500 G = 1 wi 480 d Ban 460 G = 2 440 420 400 16041667292811841440169619522208246427202976323234883744 Worst Case Codes (decimal) FIGURE 2-36: -3db Bandwidth vs. Worst Codes. DS21897A-page 14  2004 Microchip Technology Inc.

MCP4921/4922 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table3-1. TABLE 3-1: PIN FUNCTION TABLE MCP4921 MCP4922 Symbol Function Pin No. Pin No. 1 1 V Positive Power Supply Input (2.7V to 5.5V) DD — 2 NC No Connection 2 3 CS Chip Select Input 3 4 SCK Serial Clock Input 4 5 SDI Serial Data Input — 6 NC No Connection — 7 NC No Connection 5 8 LDAC Syncronization input used to transfer DAC settings from serial latches to the output latches. — 9 SHDN Hardware Shutdown Input — 10 V DAC Output OUTB B — 11 V DAC Voltage Input (AV to V ) REFB B SS DD 7 12 AV Analog ground SS 6 13 V DAC Voltage Input (AV to V ) REFA A SS DD 8 14 V DAC Output OUTA A 3.1 Positive Power Supply Input (V ) 3.6 Hardware Shutdown Input (SHDN) DD V is the positive power supply input. The input power SHDN is the hardware shutdown input that requires an DD supply is relative to AV and can range from 2.7V to active-low input signal to configure the DACs in their SS 5.5V. A decoupling capacitor on V is recommended low-power Standby mode. DD to achieve maximum performance. 3.7 DAC Outputs (V , V ) x OUTA OUTB 3.2 Chip Select (CS) V and V are DAC outputs. The DAC output OUTA OUTB CS is the chip select input, which requires an active-low amplifier drives these pins with a range of AV to V . SS DD signal to enable serial clock and data functions. 3.8 DAC Voltage Reference Inputs X 3.3 Serial Clock Input (SCK) (V , V ) REFA REFB SCK is the SPI compatible serial clock input. V and V are DAC voltage reference inputs. REFA REFB The analog signal on these pins is utilized to set the ref- 3.4 Serial Data Input (SDI) erence voltage on the string DAC. The input signal can range from AV to V . SS DD SDI is the SPI compatible serial data input. 3.9 Analog Ground (AV ) 3.5 Latch DAC Input (LDAC) SS AV is the analog ground pin. SS LDAC (the latch DAC syncronization input) transfers the input latch registers to the DAC registers (output latches) when low. Can also be tied low if transfer on the rising edge of CS is desired.  2004 Microchip Technology Inc. DS21897A-page 15

MCP4921/4922 4.0 GENERAL OVERVIEW The MCP492X devices are voltage output string DACs. INL < 0 These devices include input amplifiers, rail-to-rail out- 111 put amplifiers, reference buffers, shutdown and reset- Actual management circuitry. Serial communication conforms 110 transfer to the SPI protocol. The MCP492X operates from 2.7V function to 5.5V supplies. 101 The coding of these devices is straight binary and the Digital 100 ideal output voltage is given by Equation4-1, where G Input is the selected gain (1x or 2x), D represents the digital N Code 011 input value and n represents the number of bits of Ideal transfer resolution (n = 12). function 010 EQUATION 4-1: LSB SIZE 001 V GD V = ----R----E---F------------N-- 000 OUT n 2 INL < 0 DAC Output 1LSB is the ideal voltage difference between two successive codes. Table4-1 illustrates how to calculate LSB. FIGURE 4-1: INL Accuracy. T ABLE 4-1: LSB SIZES 4.0.2 DNL ACCURACY Device V , GAIN LSB SIZE REF DNL error is the measure of variations in code widths MCP492X External V , 1x V /4096 REF REF from the ideal code width. A DNL error of zero would MCP492X External V , 2x 2V /4096 REF REF imply that every code is exactly 1LSB wide. 4.0.1 INL ACCURACY INL error for these devices is the maximum deviation between an actual code transition point and its corre- 111 sponding ideal transition point once offset and gain 110 errors have been removed. These endpoints are from Actual transfer 0x000 to 0xFFF. Refer to Figure4-1. 101 function Positive INL means transition(s) later than ideal. Digital 100 Negative INL means transition(s) earlier than ideal. Input Ideal transfer function Code 011 010 Wide code, > 1 LSB 001 000 Narrow code < 1 LSB DAC Output FIGURE 4-2: DNL Accuracy. 4.0.3 OFFSET ERROR Offset error is the deviation from zero voltage output when the digital input code is zero. 4.0.4 GAIN ERROR Gain error is the deviation from the ideal output, V – 1LSB, excluding the effects of offset error. REF DS21897A-page 16  2004 Microchip Technology Inc.

MCP4921/4922 4.1 Circuit Descriptions If the power supply voltage is less than the POR threshold (V = 2.0V, typical), the DACs will be held POR 4.1.1 OUTPUT AMPLIFIERS in their reset state. They will remain in that state until V > V and a subsequent write command is The DACs’ outputs are buffered with a low-power, DD POR received. precision CMOS amplifier. This amplifier provides low offset voltage and low noise. The output stage enables Figure4-3 shows a typical power supply transient the device to operate with output voltages close to the pulse and the duration required to cause a reset to power supply rails. Refer to Section1.0 “Electrical occur, as well as the relationship between the duration Characteristics” for range and load conditions. and trip voltage. A 0.1µF decoupling capacitor mounted as close as possible to the V pin provides In addition to resistive load driving capability, the ampli- DD additional transient immunity. fier will also drive high capacitive loads without oscilla- tion. The amplifiers’ strong outputs allow V to be OUT used as a programmable voltage reference in a system. 5V Selecting a gain of 2 reduces the bandwidth of the amplifier in Multiplying mode. Refer to Section1.0 es VPOR g “Electrical Characteristics” for the Multiplying mode olta VDD - VPOR bandwidth for given load conditions. V y pl Transient Duration 4.1.1.1 Programmable Gain Block p u S The rail-to-rail output amplifier has configurable gain allowing optimal full-scale outputs for differing voltage Time reference inputs. The output amplifier gain has two 10 selections, a gain of 1V/V (GA = 1) or a gain of 2V/V TA = +25°C (GA = 0). µs) 8 The output range is ideally 0.000V to 4095/4096 * VREF on ( when G = 1, and 0.000 to 4095/4096 * VREF when ati 6 G=2. The default value for this bit is a gain of 2, yield- ur D ing an ideal full-scale output of 0.000V to 4.096V when nt 4 Transients above the curve utilizing a 2.048V V . Note that the near rail-to-rail e REF si will cause a reset CMOS output buffer’s ability to approach AV and n 2 SS a V establish practical range limitations. The output Tr Transients below the curve DD will NOT cause a reset swing specification in Section1.0 “Electrical Charac- 0 1 2 3 4 5 teristics” defines the range for a given load condition. V – V (V) DD POR 4.1.2 VOLTAGE REFERENCE FIGURE 4-3: Typical Transient AMPLIFIERS Response. The input buffer amplifiers for the MCP492X devices 4.1.4 SHUTDOWN MODE provide low offset voltage and low noise. A configura- tion bit for each DAC allows the VREF input to bypass Shutdown mode can be entered by using either hard- the input buffer amplifiers, achieving a Buffered or ware or software commands. The hardware pin Unbuffered mode. The default value for this bit is (SHDN) is only available on the MCP4922. During unbuffered. Buffered mode provides a very high input Shutdown mode, the supply current is isolated from impedance, with only minor limitations on the input most of the internal circuitry. The serial interface range and frequency response. Unbuffered mode remains active, thus allowing a write command to provides a wide input range (0V to VDD), with a typical bring the device out of Shutdown mode. When the input impedance of 165kΩ w/7pF. output amplifiers are shut down, the feedback resis- tance (typically 500kΩ) produces a high-impedance 4.1.3 POWER-ON RESET CIRCUIT path to AV . The device will remain in Shutdown SS The Power-On Reset (POR) circuit ensures that the mode until the SHDN pin is brought high and a write DACs power-up with SHDN = 0 (high-impedance). The command with SD = 1 is latched into the device. devices will continue to have a high-impedance output When a DAC is changed from Shutdown to Active until a valid write command is performed to either of the mode, the output settling time takes < 10µs, but DAC registers and the LDAC pin meets the input low greater than the standard Active mode settling time threshold. (4.5µs).  2004 Microchip Technology Inc. DS21897A-page 17

MCP4921/4922 5.0 SERIAL INTERFACE 5.2 Write Command The write command is initiated by driving the CS pin 5.1 Overview low, followed by clocking the four configuration bits and the 12 data bits into the SDI pin on the rising edge of The MCP492X family is designed to interface directly SCK. The CS pin is then raised, causing the data to with the Serial Peripheral Interface (SPI) port, available be latched into the selected DAC’s input registers. The on many microcontrollers, and supports Mode 0,0 and MCP492X utilizes a double-buffered latch structure to Mode 1,1. Commands and data are sent to the device allow both DAC ’s and DAC ’s outputs to be via the SDI pin, with data being clocked-in on the rising A B syncronized with the LDAC pin, if desired. Upon the edge of SCK. The communications are unidirectional LDAC pin achieving a low state, the values held in the and, thus, data cannot be read out of the MCP492X. DAC’s input registers are transferred into the DACs’ The CS pin must be held low for the duration of a write output registers. The outputs will transition to the value command. The write command consists of 16 bits and and held in the DAC register. is used to configure the DAC’s control and data latches. X Register5-1 details the input registers used to config- All writes to the MCP492X are 16-bit words. Any ure and load the DAC and DAC registers. Refer to clocks past 16 will be ignored. The most significant A B Figure1-1 and Section1.0 “Electrical Characteris- four bits are configuration bits. The remaining 12 bits tics” AC Electrical Characteristics table for detailed are data bits. No data can be transferred into the input and output timing specifications for both Mode 0,0 device with CS high. This transfer will only occur if 16 and Mode 1,1 operation. clocks have been transferred into the device. If the ris- ing edge of CS occurs prior, shifting of data into the input registers will be aborted. REGISTER 5-1: WRITE COMMAND REGISTER Upper Half: W-x W-x W-x W-0 W-x W-x W-x W-x A/B BUF GA SHDN D11 D10 D9 D8 bit 15 bit 8 Lower Half: W-x W-x W-x W-x W-x W-x W-x W-x D7 D6 D5 D4 D3 D2 D1 D0 bit 7 bit 0 bit 15 A/B: DAC or DAC Select bit A B 1 = Write to DACB 0 = Write to DACA bit 14 BUF: V Input Buffer Control bit REF 1 = Buffered 0 = Unbuffered bit 13 GA: Output Gain Select bit 1 = 1x (VOUT = VREF * D/4096) 0 = 2x (VOUT = 2 * VREF * D/4096) bit 12 SHDN: Output Power Down Control bit 1 = Output Power Down Control bit 0 = Output buffer disabled, Output is high impedance bit 11-0 D11:D0: DAC Data bits 12 bit number “D” which sets the output value. Contains a value between 0 and 4095. Legend R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR 1 = bit is set 0 = bit is cleared x = bit is unknown DS21897A-page 18  2004 Microchip Technology Inc.

MCP4921/4922 CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 (mode 1,1) SCK (mode 0,0) config bits 12 data bits SDI A/B BUF GA SHDN D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LDAC V OUT FIGURE 5-1: Write Command.  2004 Microchip Technology Inc. DS21897A-page 19

MCP4921/4922 6.0 TYPICAL APPLICATIONS Note: At the time of this data sheet’s release, V V DD DD circuit examples had not completed testing. Your results may vary. 0.1µF0.1µF The MCP492X devices are general purpose DACs intended to be used in applications where a precision, VDD VREFA low-power DAC with moderate bandwidth is required. CS 1 V Applications generally suited for the MCP492X devices OUTA X SDI i(cid:127)nScleutd Peo:int or Offset Trimming 0.1µF VREFB P492 oller C r (cid:127) Sensor Calibration VOUTB M ont c (cid:127) Digitally-Controlled Multiplier/Divider VREFA ro c (cid:127)(cid:127) PMoorttoarb Flee Iendsbtraucmk eLnotoapti oCno (nBtraottlery Powered) VOUTA 492X SDI AVSS SSDCOK ® croMi 6.1 Digital Interface VREFB CP LDAC mi C M The MCP492X utilizes a 3-wire syncronous serial VOUTB CS0 PI protocol to transfer the DACs’ setup and output values from the digital source. The serial protocol can be inter- faced to SPI™ or Microwire peripherals common on many microcontrollers, including Microchip’s AV AV SS SS PICmicro® MCUs & dsPICTM DSC family of microcon- trollers. In addition to the three serial connections (CS, FIGURE 6-1: Typical Connection SCK and SDI), the LDAC signal syncronizes when the serial settings are latched into the DAC’s output from Diagram. the serial input latch. Figure6-1 illustrates the required connections. Note that LDAC is active-low. If desired, 6.3 Layout Considerations this input can be tied low to reduce the required con- Inductively-coupled AC transients and digital switching nections from 4 to 3. Write commands will be latched noise can degrade the input and output signal integrity, directly into the output latch when a valid 16 clock potentially masking the MCP492X’s performance. transmission has been received and CS has been Careful board layout will minimize these effects and raised. increase the signal-to-noise ratio (SNR). Bench testing has shown that a multi-layer board utilizing a low-induc- 6.2 Power Supply Considerations tance ground plane, isolated inputs, isolated outputs The typical application will require a by-pass capacitor and proper decoupling are critical to achieving the in order to filter high-frequency noise. The noise can performance that the silicon is capable of providing. be induced onto the power supply's traces or as a result Particularly harsh environments may require shielding of changes on the DAC's output. The bypass capacitor of critical signals. helps to minimize the effect of these noise sources on Breadboards and wire-wrapped boards are not signal integrity. Figure6-1 illustrates an appropriate recommended if low noise is desired. bypass strategy. In this example, the recommended bypass capacitor value is 0.1µF. This capacitor should be placed as close to the device power pin (V ) as possible (within DD 4mm). The power source supplying these devices should be as clean as possible. If the application circuit has sep- arate digital and analog power supplies, AV and DD AV should reside on the analog plane. SS DS21897A-page 20  2004 Microchip Technology Inc.

MCP4921/4922 6.4 Single-Supply Operation 6.4.1.1 Decreasing The Output Step Size The MCP492X is a rail-to-rail (R-R) input and output If the output range is reduced relative to AVSS, simply DAC designed to operate with a VDD range of 2.7V to reducing VREF will reduce the magnitude of each out- 5.5V. Its output amplifier is robust enough to drive com- put step. If the application is calibrating the threshold mon, small-signal loads directly, thus eliminating the of a diode, transistor or resistor tied to AVSS or VREF, cost and size of an external buffer for most applications. a theshold range of 0.8V may be desired to provide 200µV resolution. Two common methods to achieve a 6.4.1 DC SET POINT OR CALIBRATION 0.8V range is to either reduce VREF to 0.82V or use a voltage divider on the DAC’s output. If a V is avail- A common application for a DAC with the MCP492X’s REF able with the desired output value, using that V is an performance is digitally-controlled set points and/or REF option. Occasionally, when using a low-voltage V , calibration of variable parameters, such as sensor off- REF the noise floor causes SNR error that is intolerable. set or slope. 12-bit resolution provides 4096 output The voltage divider method provides some advantages steps. If a 4.096V V is provided, an LSB would REF when V needs to be very low or when the desired represent 1mV of resolution. If a smaller output step REF output voltage is not available. In this case, a larger size is desired, the output range would need to be value V is used while two resistors scale the output reduced. REF range down to the precise desired level. Using a com- mon V output has availability and cost advantages. REF Example6-1 illustrates this concept. Note that the volt- age divider can be connected to AV or V , SS REF depending on the application’s requirements. The MCP492X’s low, ±0.75 (max.) DNL performance is critical to meeting calibration accuracy in production. V DD V + CC R sense V V REF DD Comparator VOUT R1 Vtrip MCP492X V – R 0.1uF CC 2 SPI™ 3 D G = Gain select (1x or 2x) V = V G------- OUT REF 12 D = Digital value of DAC (0 – 4096) 2 R V = V -----------2------- trip OUTR +R  1 2 EXAMPLE 6-1: Set Point or Threshold Calibration.  2004 Microchip Technology Inc. DS21897A-page 21

MCP4921/4922 6.4.1.2 Building a “Window” DAC If the threshold is not near V or AV , then creating REF SS a “window” around the threshold has several advan- When calibrating a set point or threshold of a sensor, tages. One simple method to create this “window” is to rarely does the sensor utilize the entire output range of use a voltage divider network with a pull-up and pull- the DAC. If the LSB size is adequate to meet the appli- down resistor. Example6-2 and Example6-4 cation’s accuracy needs, then the resolution is sacri- illustrates this concept. ficed without consequences. If greater accuracy is needed, then the output range will need to be reduced The MCP492X’s low, ±0.75 (max.) DNL performance to increase the resolution around the desired threshold. is critical to meet calibration accuracy in production. V VCC+ Rsense CC+ VREF VDD R3 Comparator R VOUT 1 Vtrip MCP492X V R 0.1µF CC- 2 SPI™ 3 V CC- D V = V G------- G = Gain select (1x or 2x) OUT REF 12 2 D = Digital value of DAC (0 – 4096) R R R = -------2-------3---- R1 23 R +R Thevenin 2 3 VOUT VO Equivalent (V R )+(V R ) V = -------C---C---+--------2-----------------C---C----------3---- R 23 R +R 23 2 3 V R +V R Vtrip = ----O----U----TR-------2-+-3----R---------2--3-------1- V23 2 23 EXAMPLE 6-2: Single-Supply “Window” DAC. DS21897A-page 22  2004 Microchip Technology Inc.

MCP4921/4922 6.5 Bipolar Operation Example6-3 illustrates a simple bipolar voltage source configuration. R and R allow the gain to be selected, 1 2 Bipolar operation is achievable using the MCP492X by while R and R shift the DAC's output to a selected 3 4 using an external operational amplifier (op amp). This offset. Note that R4 can be tied to V , instead of REF configuration is desirable due to the wide variety and AV , if a higher offset is desired. Note that a pull-up to SS availability of op amps. This allows a general purpose V could be used, instead of R , if a higher offset is REF 4 DAC, with its cost and availability advantages, to meet desired. almost any desired output voltage range, power and noise performance. R 2 V REF V V REF DD V + R CC 1 VOUT R3 V + VO IN MCP492X V – CC R 0.1µF 4 SPI™ 3 D V = V G------- OUT REF 12 2 V R V = ----O----U----T-------4- G = Gain select (1x or 2x) IN+ R3+R4 D = Digital value of DAC (0 – 4096) R R V = V 1+----2-- –V ----2-- O IN+ R  REFR  1 1 EXAMPLE 6-3: Digitally-Controlled Bipolar Voltage Source. 6.5.1 DESIGN A BIPOLAR DAC USING 4. Next, solve for R and R by setting the DAC to 3 4 EXAMPLE6-3 4096, knowing that the output needs to be +2.05V. An output step magnitude of 1mV with an output range of ±2.05V is desired for a particular application. ---------R----4---------- = 2----.-0---5---V------+----0---.--5---V----R---E----F- = 2--- (R +R ) 1.5V 3 1. Calculate the range: +2.05V – (-2.05V) = 4.1V. 3 4 REF 2. Calculate the resolution needed: If R = 20kΩ, then R = 10kΩ 4 3 4.1V/1mV = 4100 Since 212 = 4096, 12-bit resolution is desired. 3. The amplifier gain (R /R ), multiplied by V , 2 1 REF must be equal to the desired minimum output to achieve bipolar operation. Since any gain can be realized by choosing resistor values (R +R ), 1 2 the V source needs to be determined first. If REF a V of 4.1V is used, solve for the gain by REF setting the DAC to 0, knowing that the output needs to be -2.05V. The equation can be simplified to: –----R----2- = –----2---.-0---5-- = –----2---.-0---5-- R----2-- = 1--- R V 4.1 R 2 1 REF 1 If R = 20kΩ and R = 10kΩ, the gain will be 0.5. 1 2  2004 Microchip Technology Inc. DS21897A-page 23

MCP4921/4922 6.6 Selectable Gain and Offset Bipolar This circuit is typically used in Multiplier mode and is Voltage Output Using A Dual DAC ideal for linearizing a sensor whose slope and offset varies. Refer to Section6.9 “Using Multiplier Mode” In some applications, precision digital control of the for more information on Multiplier mode. output range is desirable. Example6-4 illustrates how The equation to design a bipolar “window” DAC would to use the MCP4922 to achieve this in a bipolar or be utilized if R , R and R are populated. single-supply application. 3 4 5 R 2 VREFA VDD V + CC R 1 V OUTA MCP492X V + CC VREFB VDD DACA (Gain Adjust) VO R 5 R V 3 OUTB MCP492X SPI™ DACB (Offset Adjust) R4 0.1uF V – 3 CC V – CC D D V = (V G )-----B-- V = (V G )-----A-- OUTB REFB B 12 OUTA REFA A 12 2 2 V R +V R AVSS = GND V = ----O----U----T---B-------4-------------C---C----------3- IN+ R +R 3 4 G = Gain select (1x or 2x) V = V 1+R----2-- –V R----2-- D = Digital value of DAC (0 – 4096) O IN+ R  OUTAR  1 1 Offset Adjust Gain Adjust Bipolar “Window” DAC using R and R 4 5 Thevenin V R +V R R R V = ----C----C---+-------4-------------C---C----------5- R = -------4-------5---- Equivalent 45 R +R 45 R +R 4 5 4 5 V R +V R R R V = ----O----U----T---B-------4--5-------------4--5-------3- V = V 1+----2-- –V ----2-- IN+ R +R O IN+ R  OUTAR  3 45 1 1 Offset Adjust Gain Adjust EXAMPLE 6-4: Bipolar Voltage Source With Selectable Gain and Offset. DS21897A-page 24  2004 Microchip Technology Inc.

MCP4921/4922 6.7 Designing A Double-Precision 1. Calculate the resolution needed: DAC Using A Dual DAC 4.1V/1uV = 4.1e06. Since 222 = 4.2e06, 22-bit resolution is desired. Since DNL = ±0.75 LSB, Example6-5 illustrates how to design a single-supply this design can be attempted with the voltage output capable of up to 24-bit resolution from a MCP492X. dual 12-bit DAC. This design is simply a voltage divider 2. Since DAC ‘s V has a resolution of 1mV, B OUTB with a buffered output. its output only needs to be “pulled” 1/1000 to As an example, if a similar application to the one devel- meet the 1µV target. Dividing VOUTA by 1000 oped in Section6.5.1 “Design a bipolar dac using would allow the application to compensate for Example6-3” required a resolution of 1µV instead of DACB‘s DNL error. 1mV and a range of 0V to 4.1V, then 12-bit resolution 3. If R is 100Ω, then R needs to be 100kΩ. 2 1 would not be adequate. 4. The resulting transfer function is not perfectly linear, as shown in the equation of Example6-5. VREF VDD V + CC DAC (Fine Adjust) A MCP492X V V O OUTA R 1 V DD R >> R 1 2 VOUTB R2 V – MCP492X 0.1µF CC DAC (Course Adjust) B SPI™ 3 D D V = V G -----A-- V = V G -----B-- G = Gain select (1x or 2x) OUTA REFA A212 OUTB REFB B212 D = Digital value of DAC (0 – 4096) V R +V R V = ----O----U----T---A-------2-------------O---U----T---B-------1- O R +R 1 2 EXAMPLE 6-5: Simple, Double-Precision DAC.  2004 Microchip Technology Inc. DS21897A-page 25

MCP4921/4922 6.8 Building A Programmable Current 6.9 Using Multiplier Mode Source The MCP492X is ideally suited for use as a multiplier/ Example6-6 illustrates a variation on a voltage follower divider in a signal chain. Common applications include: design where a sense resistor is used to convert the precision programmable gain/attenuator amplifiers and DAC’s voltage output into a digitally-selectable current loop controls (motor feedback). The wide input range source. (0V – VDD) is an Unbuffered mode and near R-R range in Buffered mode: the >400kHz bandwidth, selectible Adding the resistor network from Example6-2 would 1x/2x gain and its low power consumption give be advantageous in this application. The smaller R sense maximum flexibility to meet the application's needs. is, the less power dissipated across it. However, this also reduces the resolution that the current can be To configure the MCP492X in Multiplier mode, connect controlled with. The voltage divider, or “window”, DAC the input signal to VREF and serially configure the configuration would allow the range to be reduced, thus DAC’s input buffer, gain and output value. The DAC’s increasing resolution around the range of interest. output can utilize any of Examples 6-1 to 6-6, depend- When working with very small sensor voltages, plan on ing on the application requirements. Example6-7 is an eliminating the amplifier's offset error by storing the illustration of how the DAC can operate in a motor DAC's setting under known sensor conditions. control feedback loop. If the Gain Select bit is configured for 1x mode (GA=1), the resulting input signal will be attenuated by D/4096. V V If the Gain Select bit is configured for 2x mode (GA=0), REF DD codes <2048 attenuate the signal, while codes >2048 VCC+ LOAD gain the signal. VOUT = VIN (D/2048). V OUT A 12-bit DAC provides significantly more gain/attenua- MCP492X I L tion resolution when compared to typical Programmable Gain Amplifiers. Adding an op amp to buffer the output, SPI™ VCC– Ib as illustrated in Examples 6-2 to 6-6, extends the 3 output range and power to meet the precise needs of R the application. D sense V = V G------- OUT REF 12 2 V I RPM_SET I = ---L- b β V RPM I = -V----O----U----T--×-----β------- VDD ZFB L R β+1 V + sense CC + V G = Gain select (1x or 2x) OUT MCP492X V D = Digital value of DAC (0 – 4096) REF SPI™ – V – EXAMPLE 6-6: Digitally-Controlled Current CC 3 Source. R sense EXAMPLE 6-7: Multiplier Mode. DS21897A-page 26  2004 Microchip Technology Inc.

MCP4921/4922 7.0 DEVELOPMENT SUPPORT 7.1 Evaluation & Demonstration 7.2 Application Notes and Tech Briefs Boards Application notes illustrating the performace and imple- The Mixed Signal PICtailTM Board supports the mentation of the MCP492X are planned but currently MCP492X family of devices. Please refer to not released. Please refer to www.microchip.com for www.microchip.com for further information on this further information. products capabilities and availability.  2004 Microchip Technology Inc. DS21897A-page 27

MCP4921/4922 8.0 PACKAGING INFORMATION 8.1 Package Marking Information 8-Lead MSOP Example: XXXXXX 4921E YWWNNN 412256 8-Lead PDIP (300 mil) Example: XXXXXXXX MCP4921 XXXXXNNN E/P256 YYWW 0412 8-Lead SOIC (150 mil) Example: XXXXXXXX MCP4921 XXXXYYWW E/SN0412 NNN 256 Legend: XX...X Customer specific information* YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard marking consists of Microchip part number, year code, week code, traceability code (facility code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. DS21897A-page 28  2004 Microchip Technology Inc.

MCP4921/4922 Package Marking Information (Continued) 14-Lead PDIP (300 mil) (MCP4922) Example: XXXXXXXXXXXXXX MCP4922E/P XXXXXXXXXXXXXX YYWWNNN 0412256 14-Lead SOIC (150 mil) (MCP4922) Example: XXXXXXXXXX MCP4922E/SL XXXXXXXXXX YYWWNNN 0412256 14-Lead TSSOP (MCP4922) Example: XXXXXX 4922E/ST YYWW 0412 NNN 256  2004 Microchip Technology Inc. DS21897A-page 29

MCP4921/4922 8-Lead Plastic Micro Small Outline Package (MS) (MSOP) E E1 p D 2 B n 1 α A A2 c φ A1 (F) L β Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch p .026 BSC 0.65 BSC Overall Height A - - .043 - - 1.10 Molded Package Thickness A2 .030 .033 .037 0.75 0.85 0.95 Standoff A1 .000 - .006 0.00 - 0.15 Overall Width E .193 TYP. 4.90 BSC Molded Package Width E1 .118 BSC 3.00 BSC Overall Length D .118 BSC 3.00 BSC Foot Length L .016 .024 .031 0.40 0.60 0.80 Footprint (Reference) F .037 REF 0.95 REF Foot Angle φ 0° - 8° 0° - 8° Lead Thickness c .003 .006 .009 0.08 - 0.23 Lead Width B .009 .012 .016 0.22 - 0.40 Mold Draft Angle Top α 55°° - 15° 5° - 15° Mold Draft Angle Bottom β 55°° --- 15° 5° - 15° *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MO-187 Drawing No. C04-111 DS21897A-page 30  2004 Microchip Technology Inc.

MCP4921/4922 8-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n 1 α E A A2 L c A1 β B1 p eB B Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch p .100 2.54 Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32 Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26 Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60 Overall Length D .360 .373 .385 9.14 9.46 9.78 Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43 Lead Thickness c .008 .012 .015 0.20 0.29 0.38 Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78 Lower Lead Width B .014 .018 .022 0.36 0.46 0.56 Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92 Mold Draft Angle Top α 5 10 15 5 10 15 Mold Draft Angle Bottom β 5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018  2004 Microchip Technology Inc. DS21897A-page 31

MCP4921/4922 8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 h α 45° c A A2 φ β L A1 Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch p .050 1.27 Overall Height A .053 .061 .069 1.35 1.55 1.75 Molded Package Thickness A2 .052 .056 .061 1.32 1.42 1.55 Standoff § A1 .004 .007 .010 0.10 0.18 0.25 Overall Width E .228 .237 .244 5.79 6.02 6.20 Molded Package Width E1 .146 .154 .157 3.71 3.91 3.99 Overall Length D .189 .193 .197 4.80 4.90 5.00 Chamfer Distance h .010 .015 .020 0.25 0.38 0.51 Foot Length L .019 .025 .030 0.48 0.62 0.76 Foot Angle φ 0 4 8 0 4 8 Lead Thickness c .008 .009 .010 0.20 0.23 0.25 Lead Width B .013 .017 .020 0.33 0.42 0.51 Mold Draft Angle Top α 0 12 15 0 12 15 Mold Draft Angle Bottom β 0 12 15 0 12 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057 DS21897A-page 32  2004 Microchip Technology Inc.

MCP4921/4922 14-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n 1 α E A A2 c L A1 β B1 eB B p Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 14 14 Pitch p .100 2.54 Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32 Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26 Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60 Overall Length D .740 .750 .760 18.80 19.05 19.30 Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43 Lead Thickness c .008 .012 .015 0.20 0.29 0.38 Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78 Lower Lead Width B .014 .018 .022 0.36 0.46 0.56 Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92 Mold Draft Angle Top α 5 10 15 5 10 15 Mold Draft Angle Bottom β 5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-005  2004 Microchip Technology Inc. DS21897A-page 33

MCP4921/4922 14-Lead Plastic Small Outline (SL) – Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 α h 45° c A A2 φ A1 L β Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 14 14 Pitch p .050 1.27 Overall Height A .053 .061 .069 1.35 1.55 1.75 Molded Package Thickness A2 .052 .056 .061 1.32 1.42 1.55 Standoff § A1 .004 .007 .010 0.10 0.18 0.25 Overall Width E .228 .236 .244 5.79 5.99 6.20 Molded Package Width E1 .150 .154 .157 3.81 3.90 3.99 Overall Length D .337 .342 .347 8.56 8.69 8.81 Chamfer Distance h .010 .015 .020 0.25 0.38 0.51 Foot Length L .016 .033 .050 0.41 0.84 1.27 Foot Angle φ 0 4 8 0 4 8 Lead Thickness c .008 .009 .010 0.20 0.23 0.25 Lead Width B .014 .017 .020 0.36 0.42 0.51 Mold Draft Angle Top α 0 12 15 0 12 15 Mold Draft Angle Bottom β 0 12 15 0 12 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-065 DS21897A-page 34  2004 Microchip Technology Inc.

MCP4921/4922 14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP) E E1 p D 2 n 1 B α A c φ β A1 A2 L Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 14 14 Pitch p .026 0.65 Overall Height A .043 1.10 Molded Package Thickness A2 .033 .035 .037 0.85 0.90 0.95 Standoff § A1 .002 .004 .006 0.05 0.10 0.15 Overall Width E .246 .251 .256 6.25 6.38 6.50 Molded Package Width E1 .169 .173 .177 4.30 4.40 4.50 Molded Package Length D .193 .197 .201 4.90 5.00 5.10 Foot Length L .020 .024 .028 0.50 0.60 0.70 Foot Angle φ 0 4 8 0 4 8 Lead Thickness c .004 .006 .008 0.09 0.15 0.20 Lead Width B1 .007 .010 .012 0.19 0.25 0.30 Mold Draft Angle Top α 0 5 10 0 5 10 Mold Draft Angle Bottom β 0 5 10 0 5 10 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005” (0.127mm) per side. JEDEC Equivalent: MO-153 Drawing No. C04-087  2004 Microchip Technology Inc. DS21897A-page 35

MCP4921/4922 NOTES: DS21897A-page 36  2004 Microchip Technology Inc.

MCP4921/4922 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX Examples: a) MCP4921T-E/SN: Tape and Reel Device Temperature Package Extended Temperature, Range 8LD SOIC package. b) MCP4921T-E/MS: Tape and Reel Extended Temperature, 8LD MSOP package. Device: MCP4921: 12-Bit DAC with SPI Interface c) MCP4921-E/SN: Extended Temperature, MCP4921T: 12-Bit DAC with SPI Interface 8LD SOIC package. (Tape and Reel) (SOIC, MSOP) d) MCP4921-E/MS: Extended Temperature, MCP4922: 12-Bit DAC with SPI Interface 8LD MSOP package. MCP4922T: 12-Bit DAC with SPI Interface e) MCP4921-E/P: Extended Temperature, (Tape and Reel) (SOIC, MSOP) 8LD PDIP package. a) MCP4922T-E/SL: Tape and Reel Temperature Range: E = -40°C to +125°C Extended Temperature, 14LD SOIC package. b) MCP4922T-E/ST: Tape and Reel Package: MS = Plastic MSOP, 8-lead Extended Temperature, P = Plastic DIP (300 mil Body), 8-lead, 14-lead 14LD TSSOP package. SN = Plastic SOIC, (150 mil Body), 8-lead c) MCP4922-E/P: Extended Temperature, SL = Plastic SOIC (150 mil Body), 14-lead 14LD PDIP package. ST = Plastic TSSOP (4.4mm Body), 14-lead d) MCP4922-E/SL: Extended Temperature, 14LD SOIC package. e) MCP4922-E/ST: Extended Temperature, 14LD TSSOP package. Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office 2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 3. The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.  2004 Microchip Technology Inc. DS21897A-page 37

MCP4921/4922 NOTES: DS21897A-page 38  2004 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: (cid:127) Microchip products meet the specification contained in their particular Microchip Data Sheet. (cid:127) Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. (cid:127) There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. (cid:127) Microchip is willing to work with the customer who is concerned about the integrity of their code. (cid:127) Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is intended through suggestion only The Microchip name and logo, the Microchip logo, Accuron, and may be superseded by updates. It is your responsibility to dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, ensure that your application meets with your specifications. PICSTART, PROMATE, PowerSmart, rfPIC, and No representation or warranty is given and no liability is SmartShunt are registered trademarks of Microchip assumed by Microchip Technology Incorporated with respect Technology Incorporated in the U.S.A. and other countries. to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL, use or otherwise. Use of Microchip’s products as critical SmartSensor and The Embedded Control Solutions Company components in life support systems is not authorized except are registered trademarks of Microchip Technology with express written approval by Microchip. No licenses are Incorporated in the U.S.A. conveyed, implicitly or otherwise, under any intellectual Analog-for-the-Digital Age, Application Maestro, dsPICDEM, property rights. dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2004, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company’s quality system processes and procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2004 Microchip Technology Inc. DS21897A-page 39

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: MCP4921-E/SN MCP4921-E/MS MCP4922-E/SL MCP4922-E/ST MCP4922-E/P MCP4922T-E/ST MCP4922T- E/SL MCP4921T-E/SN MCP4921T-E/MS MCP4921-E/P