MCP454X/456X/464X/466X 2 7/8-Bit Single/Dual I C Digital POT with Nonvolatile Memory Features Description • Single or Dual Resistor Network Options The MCP45XX and MCP46XX devices offer a wide • Potentiometer or Rheostat Configuration Options range of product offerings using an I2C interface. This • Resistor Network Resolution family of devices support 7-bit and 8-bit resistor - 7-bit: 128 Resistors (129 Steps) networks, nonvolatile memory configurations, and - 8-bit: 256 Resistors (257 Steps) Potentiometer and Rheostat pinouts. • R Resistances Options of: AB WiperLock Technology allows application-specific - 5k calibration settings to be secured in the EEPROM. - 10k - 50k Package Types (top view) - 100k • Zero-Scale to Full-Scale Wiper Operation MCP45X1 MCP45X2 • Low Wiper Resistance: 75 (typical) Single Potentiometer Single Rheostat • Low Tempco: - Absolute (Rheostat): 50ppm typical HVC / A0 1 8 VDD HVC / A0 1 8 VDD SCL 2 7 P0B SCL 2 7 A1 (0°C to 70°C) SDA 3 6 P0W SDA 3 6 P0B - Ratiometric (Potentiometer): 15ppm typical V 4 5 P0A V 4 5 P0W SS SS • Nonvolatile Memory MSOP MSOP - Automatic Recall of Saved Wiper Setting - WiperLock™ Technology HVC / A0 1 8 VDD HVC / A0 1 8 VDD - 10 General Purpose Memory Locations • I2C Serial Interface SCL 2 EP 7 P0B SCL 2 EP 7 A1 9 9 SDA 3 6 P0W SDA 3 6 P0B - 100kHz, 400kHz and 3.4MHz Support • Serial Protocol Allows: VSS 4 5 P0A VSS 4 5 P0W - High-Speed Read/Write to Wiper DFN 3x3 (MF) * DFN 3x3 (MF) * - Read/Write to EEPROM MCP46X1 Dual Potentiometers - Write Protect to be Enabled/Disabled - WiperLock to be Enabled/Disabled HVC/A0 1 14 VDD A0 • Resistor Network Terminal Disconnect Feature SSDCAL 23 1123 AA21 HVC/ VDDA1A2 via the Terminal Control (TCON) Register VSS 4 11 WP 16151413 • Write Protect Feature: P1B 5 10 P0B SCL 1 12WP P1W 6 9 P0W - Hardware Write Protect (WP) Control Pin P1A 7 8 P0A SDA 2 EP 11NC - Software Write Protect (WP) Configuration Bit VSS 3 17 10P0B • Brown-out Reset Protection (1.5V typical) TSSOP VSS 4 9 P0W • Serial Interface Inactive Current (2.5uA typical) 5 6 7 8 •• HWigidhe- VOoplteargaeti nTgo lVeroaltnatg Dei:g ital Inputs: Up to 12.5V P1BP1WP1A P0A - 2.7V to 5.5V - Device Characteristics Specified QFN-16 4x4 (ML) * - 1.8V to 5.5V - Device Operation MCP46X2 Dual Rheostat • Wide Bandwidth (-3dB) Operation: - 2MHz (typ.) for 5.0k Device HVC/A0 1 10 VDD HVC / A0 1 10VDD • Extended Temperature Range (-40°C to +125°C) SCL 2 9 A1 SCL 2 9 A1 SDA 3 8 P0B SDA 3 EP 8 P0B PV1SBS 45 76 PP10WW VSS 4 11 7 P0W P1B 5 6 P1W MSOP DFN 3x3 (MF) * * Includes Exposed Thermal Pad (EP); see Table3-1.  2008-2013 Microchip Technology Inc. DS22107B-page 1

MCP454X/456X/464X/466X Device Block Diagram VDD Power-up/ Resistor P0A Brown-out V Network 0 SS Control (Pot 0) P0W A2 I2C Serial Wiper 0 & TCON A1 Interface Register Module & HVC/A0 P0B Control SCL Logic I2C Interface SDA (TWeciphenroLloogcky™) Resistor P1A Network 1 WP (Pot 1) P1W Wiper 1 Memory (16x9) & TCON Wiper0 (V & NV) Register P1B Wiper1 (V & NV) TCON STATUS For Dual Resistor Network Devices Only Data EEPROM (10 x 9-bits) Device Features Device # of POTs ConWfigipuerar tion Control Interface Memory Type WiperLock Technology POR Wiper Setting RARB eOspisttioanncse ( k(ty)picaW-l( )iRpW)er # of Steps ORpaeVnrgDaDeti n(2g) MCP4531 (3) 1 Potentiometer (1) I2C RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 129 1.8V to 5.5V MCP4532 (3) 1 Rheostat I2C RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 129 1.8V to 5.5V MCP4541 1 Potentiometer (1) I2C EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0 75 129 2.7V to 5.5V MCP4542 1 Rheostat I2C EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0 75 129 2.7V to 5.5V MCP4551 (3) 1 Potentiometer (1) I2C RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 257 1.8V to 5.5V MCP4552 (3) 1 Rheostat I2C RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 257 1.8V to 5.5V MCP4561 1 Potentiometer (1) I2C EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0 75 257 2.7V to 5.5V MCP4562 1 Rheostat I2C EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0 75 257 2.7V to 5.5V MCP4631 (3) 2 Potentiometer (1) I2C RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 129 1.8V to 5.5V MCP4632 (3) 2 Rheostat I2C RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 129 1.8V to 5.5V MCP4641 2 Potentiometer (1) I2C EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0 75 129 2.7V to 5.5V MCP4642 2 Rheostat I2C EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0 75 129 2.7V to 5.5V MCP4651 (3) 2 Potentiometer (1) I2C RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 257 1.8V to 5.5V MCP4652 (3) 2 Rheostat I2C RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 257 1.8V to 5.5V MCP4661 2 Potentiometer (1) I2C EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0 75 257 2.7V to 5.5V MCP4662 2 Rheostat I2C EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0 75 257 2.7V to 5.5V Note 1: Floating either terminal (A or B) allows the device to be used as a Rheostat (variable resistor). 2: Analog characteristics only tested from 2.7V to 5.5V unless otherwise noted. 3: Please check Microchip web site for device release and availability DS22107B-page 2  2008-2013 Microchip Technology Inc.

MCP454X/456X/464X/466X 1.0 ELECTRICAL CHARACTERISTICS 1.1 Absolute Maximum Ratings† Voltage on V with respect to V ...........................................................................................................-0.6V to +7.0V DD SS Voltage on HVC/A0, A1, A2, SCL, SDA and WP with respect to V .......................................................-0.6V to 12.5V SS Voltage on all other pins (PxA, PxW, and PxB) with respect to V ..................................................-0.3V to V + 0.3V SS DD Input clamp current, IIK (VI < 0, VI > VDD, VI > VPP ON HV pins)...........................................................................±20mA Output clamp current, I (V < 0 or V > V ) ..................................................................................................±20mA OK O O DD Maximum output current sunk by any Output pin....................................................................................................25mA Maximum output current sourced by any Output pin .............................................................................................25mA Maximum current out of V pin...........................................................................................................................100mA SS Maximum current into V pin..............................................................................................................................100mA DD Maximum current into PXA, PXW & PXB pins......................................................................................................±2.5mA Storage temperature...............................................................................................................................-65°C to +150°C Ambient temperature with power applied................................................................................................-40°C to +125°C Package power dissipation (T = +50°C, T = +150°C) A J MSSOP-8.......................................................................................................................................................473mW MSSOP-10.....................................................................................................................................................495mW DFN-8 (3x3)......................................................................................................................................................1.76W DFN-10 (3x3)....................................................................................................................................................1.87W TSSOP-14.........................................................................................................................................................1.00W QFN-16 (4x4)....................................................................................................................................................2.18W Soldering temperature of leads (10 seconds).......................................................................................................+300°C ESD protection on all pins 4kV (HBM), 300V (MM) Maximum Junction Temperature (T ) ...................................................................................................................+150°C J † Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended peri- ods may affect device reliability.  2008-2013 Microchip Technology Inc. DS22107B-page 3

MCP454X/456X/464X/466X AC/DC CHARACTERISTICS Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C  T  +125°C (extended) A DC Characteristics All parameters apply across the specified operating ranges unless noted. V = +2.7V to 5.5V, 5k, 10k, 50k, 100k devices. DD Typical specifications represent values for V = 5.5V, T = +25°C. DD A Parameters Sym Min Typ Max Units Conditions Supply Voltage V 2.7 — 5.5 V DD 1.8 — 2.7 V Serial Interface only. HVC pin voltage V V — 12.5V V V  The HVC pin will be at one HV SS DD range 4.5V of three input levels (V , V or V ). (Note6) V — V + V V < IL IH IHH SS DD DD 8.0V 4.5V VDD Start Voltage VBOR — — 1.65 V RAM retention voltage (VRAM) < VBOR to ensure Wiper Reset VDD Rise Rate to VDDRR (Note9) V/ms ensure Power-on Reset Delay after device T — 10 20 µs BORD exits the reset state (V > V ) DD BOR Supply Current I — — 600 µA Serial Interface Active, DD (Note10) HVC/A0 = V (or V ) (Note11) IH IL Write all 0’s to Volatile Wiper 0 V = 5.5V, F = 3.4MHz DD SCL — — 250 µA Serial Interface Active, HVC/A0 = V (or V ) (Note11) IH IL Write all 0’s to Volatile Wiper 0 V = 5.5V, F = 100kHz DD SCL — — 575 µA EE Write Current (Write Cycle) (Nonvolatile device only), V = 5.5V, F = 400kHz, DD SCL Write all 0’s to Nonvolatile Wiper 0 SCL = V or V IL IH — 2.5 5 µA Serial Interface Inactive, (Stop condition, SCL = SDA = V ), IH Wiper = 0 V = 5.5V, HVC/A0 = V DD IH Note 1: Resistance is defined as the resistance between terminal A to terminal B. 2: INL and DNL are measured at V with V = V and V = V . W A DD B SS 3: MCP4XX1 only. 4: MCP4XX2 only, includes V and V . WZSE WFSE 5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted. 6: This specification by design. 7: Non-linearity is affected by wiper resistance (R ), which changes significantly overvoltage and W temperature. 8: The MCP4XX1 is externally connected to match the configurations of the MCP45X2 and MCP46X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network. 11: When HVC/A0 = V , the I current is less due to current into the HVC/A0 pin. See I specification. IHH DD PU DS22107B-page 4  2008-2013 Microchip Technology Inc.

MCP454X/456X/464X/466X AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C  T  +125°C (extended) A DC Characteristics All parameters apply across the specified operating ranges unless noted. V = +2.7V to 5.5V, 5k, 10k, 50k, 100k devices. DD Typical specifications represent values for V = 5.5V, T = +25°C. DD A Parameters Sym Min Typ Max Units Conditions Resistance R 4.0 5 6.0 k -502 devices(Note1) AB (± 20%) 8.0 10 12.0 k -103 devices(Note1) 40.0 50 60.0 k -503 devices(Note1) 80.0 100 120.0 k -104 devices(Note1) Resolution N 257 Taps 8-bit No Missing Codes 129 Taps 7-bit No Missing Codes Step Resistance R — R / —  8-bit Note6 S AB (256) — R / —  7-bit Note6 AB (128) Nominal |R - R | / — 0.2 1.25 % MCP46X1 devices only AB0 AB1 Resistance Match R AB |R - R | — 0.25 1.5 % MCP46X2 devices only, BW0 BW1 / R Code = Full-Scale BW Wiper Resistance R — 75 160  V = 5.5 V, I = 2.0mA, code = 00h W DD W (Note3, Note4) — 75 300  V = 2.7 V, I = 2.0mA, code = 00h DD W Nominal R /T — 50 — ppm/°C T = -20°C to +70°C AB A Resistance — 100 — ppm/°C T = -40°C to +85°C A Tempco — 150 — ppm/°C T = -40°C to +125°C A Ratiometeric V /T — 15 — ppm/°C Code = Mid-scale (80h or 40h) WB Tempco Resistor Terminal V V V Vss — V V Note5, Note6 A, W, B DD Input Voltage Range (Terminals A, B and W) Note 1: Resistance is defined as the resistance between terminal A to terminal B. 2: INL and DNL are measured at V with V = V and V = V . W A DD B SS 3: MCP4XX1 only. 4: MCP4XX2 only, includes V and V . WZSE WFSE 5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted. 6: This specification by design. 7: Non-linearity is affected by wiper resistance (R ), which changes significantly overvoltage and W temperature. 8: The MCP4XX1 is externally connected to match the configurations of the MCP45X2 and MCP46X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network. 11: When HVC/A0 = V , the I current is less due to current into the HVC/A0 pin. See I specification. IHH DD PU  2008-2013 Microchip Technology Inc. DS22107B-page 5

MCP454X/456X/464X/466X AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C  T  +125°C (extended) A DC Characteristics All parameters apply across the specified operating ranges unless noted. V = +2.7V to 5.5V, 5k, 10k, 50k, 100k devices. DD Typical specifications represent values for V = 5.5V, T = +25°C. DD A Parameters Sym Min Typ Max Units Conditions Maximum current I — — 2.5 mA Terminal A I , T AW through Terminal W = Full-Scale (FS) (A, W or B) — — 2.5 mA Terminal B I , BW Note6 W = Zero Scale (ZS) — — 2.5 mA Terminal W I or I , AW BW W = FS or ZS — — 1.38 mA I , V = 0V, AB B V = 5.5V, A R = 4000 AB(MIN) — — 0.688 mA I , V = 0V, AB B V = 5.5V, Terminal A A R = 8000 and AB(MIN) — — 0.138 mA I , V = 0V, Terminal B AB B V = 5.5V, A R = 40000 AB(MIN) — — 0.069 mA I , V = 0V, AB B V = 5.5V, A R = 80000 AB(MIN) Leakage current I — 100 — nA MCP4XX1 PxA = PxW = PxB = V WL SS into A, W or B — 100 — nA MCP4XX2 PxB = PxW = V SS — 100 — nA Terminals Disconnected (R1HW = R0HW = 0) Note 1: Resistance is defined as the resistance between terminal A to terminal B. 2: INL and DNL are measured at V with V = V and V = V . W A DD B SS 3: MCP4XX1 only. 4: MCP4XX2 only, includes V and V . WZSE WFSE 5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted. 6: This specification by design. 7: Non-linearity is affected by wiper resistance (R ), which changes significantly overvoltage and W temperature. 8: The MCP4XX1 is externally connected to match the configurations of the MCP45X2 and MCP46X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network. 11: When HVC/A0 = V , the I current is less due to current into the HVC/A0 pin. See I specification. IHH DD PU DS22107B-page 6  2008-2013 Microchip Technology Inc.

MCP454X/456X/464X/466X AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C  T  +125°C (extended) A DC Characteristics All parameters apply across the specified operating ranges unless noted. V = +2.7V to 5.5V, 5k, 10k, 50k, 100k devices. DD Typical specifications represent values for V = 5.5V, T = +25°C. DD A Parameters Sym Min Typ Max Units Conditions Full-Scale Error V -6.0 -0.1 — LSb 5k 8-bit 3.0V  V  5.5V WFSE DD (MCP4XX1 only) -4.0 -0.1 — LSb 7-bit 3.0V  V  5.5V DD (8-bit code = 100h, -3.5 -0.1 — LSb 10k 8-bit 3.0V  V  5.5V 7-bit code = 80h) DD -2.0 -0.1 — LSb 7-bit 3.0V  V  5.5V DD -0.8 -0.1 — LSb 50k 8-bit 3.0V  V  5.5V DD -0.5 -0.1 — LSb 7-bit 3.0V  V  5.5V DD -0.5 -0.1 — LSb 100k 8-bit 3.0V  V  5.5V DD -0.5 -0.1 — LSb 7-bit 3.0V  V  5.5V DD Zero-Scale Error V — +0.1 +6.0 LSb 5k 8-bit 3.0V  V  5.5V WZSE DD (MCP4XX1 only) — +0.1 +3.0 LSb 7-bit 3.0V  V  5.5V DD (8-bit code = 00h, — +0.1 +3.5 LSb 10k 8-bit 3.0V  V  5.5V 7-bit code = 00h) DD — +0.1 +2.0 LSb 7-bit 3.0V  V  5.5V DD — +0.1 +0.8 LSb 50k 8-bit 3.0V  V  5.5V DD — +0.1 +0.5 LSb 7-bit 3.0V  V  5.5V DD — +0.1 +0.5 LSb 100k 8-bit 3.0V  V  5.5V DD — +0.1 +0.5 LSb 7-bit 3.0V  V  5.5V DD Potentiometer INL -1 ±0.5 +1 LSb 8-bit 3.0V  V  5.5V DD Integral MCP4XX1 devices only -0.5 ±0.25 +0.5 LSb 7-bit Non-linearity (Note2) Potentiometer DNL -0.5 ±0.25 +0.5 LSb 8-bit 3.0V  V  5.5V DD Differential MCP4XX1 devices only -0.25 ±0.125 +0.25 LSb 7-bit Non-linearity (Note2) Note 1: Resistance is defined as the resistance between terminal A to terminal B. 2: INL and DNL are measured at V with V = V and V = V . W A DD B SS 3: MCP4XX1 only. 4: MCP4XX2 only, includes V and V . WZSE WFSE 5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted. 6: This specification by design. 7: Non-linearity is affected by wiper resistance (R ), which changes significantly overvoltage and W temperature. 8: The MCP4XX1 is externally connected to match the configurations of the MCP45X2 and MCP46X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network. 11: When HVC/A0 = V , the I current is less due to current into the HVC/A0 pin. See I specification. IHH DD PU  2008-2013 Microchip Technology Inc. DS22107B-page 7

MCP454X/456X/464X/466X AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C  T  +125°C (extended) A DC Characteristics All parameters apply across the specified operating ranges unless noted. V = +2.7V to 5.5V, 5k, 10k, 50k, 100k devices. DD Typical specifications represent values for V = 5.5V, T = +25°C. DD A Parameters Sym Min Typ Max Units Conditions Bandwidth -3dB BW — 2 — MHz 5k 8-bit Code = 80h (See Figure2-58, — 2 — MHz 7-bit Code = 40h load = 30pF) — 1 — MHz 10k 8-bit Code = 80h — 1 — MHz 7-bit Code = 40h — 200 — kHz 50k 8-bit Code = 80h — 200 — kHz 7-bit Code = 40h — 100 — kHz 100k 8-bit Code = 80h — 100 — kHz 7-bit Code = 40h Note 1: Resistance is defined as the resistance between terminal A to terminal B. 2: INL and DNL are measured at V with V = V and V = V . W A DD B SS 3: MCP4XX1 only. 4: MCP4XX2 only, includes V and V . WZSE WFSE 5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted. 6: This specification by design. 7: Non-linearity is affected by wiper resistance (R ), which changes significantly overvoltage and W temperature. 8: The MCP4XX1 is externally connected to match the configurations of the MCP45X2 and MCP46X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network. 11: When HVC/A0 = V , the I current is less due to current into the HVC/A0 pin. See I specification. IHH DD PU DS22107B-page 8  2008-2013 Microchip Technology Inc.

MCP454X/456X/464X/466X AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C  T  +125°C (extended) A DC Characteristics All parameters apply across the specified operating ranges unless noted. V = +2.7V to 5.5V, 5k, 10k, 50k, 100k devices. DD Typical specifications represent values for V = 5.5V, T = +25°C. DD A Parameters Sym Min Typ Max Units Conditions Rheostat Integral R-INL -1.5 ±0.5 +1.5 LSb 5k 8-bit 5.5V, I = 900µA W Non-linearity -8.25 +4.5 +8.25 LSb 3.0V, I = 480µA W MCP45X1 (Note7) (Note4, Note8) -1.125 ±0.5 +1.125 LSb 7-bit 5.5V, I = 900µA MCP4XX2 devices W only (Note4) -6.0 +4.5 +6.0 LSb 3.0V, IW = 480µA (Note7) -1.5 ±0.5 +1.5 LSb 10k 8-bit 5.5V, I = 450µA W -5.5 +2.5 +5.5 LSb 3.0V, I = 240µA W (Note7) -1.125 ±0.5 +1.125 LSb 7-bit 5.5V, I = 450µA W -4.0 +2.5 +4.0 LSb 3.0V, I = 240µA W (Note7) -1.5 ±0.5 +1.5 LSb 50k 8-bit 5.5V, I = 90µA W -2.0 +1 +2.0 LSb 3.0V, I = 48µA W (Note7) -1.125 ±0.5 +1.125 LSb 7-bit 5.5V, I = 90µA W -1.5 +1 +1.5 LSb 3.0V, I = 48µA W (Note7) -1.0 ±0.5 +1.0 LSb 100k 8-bit 5.5V, I = 45µA W -1.5 +0.25 +1.5 LSb 3.0V, I = 24µA W (Note7) -0.8 ±0.5 +0.8 LSb 7-bit 5.5V, I = 45µA W -1.125 +0.25 +1.125 LSb 3.0V, I = 24µA W (Note7) Note 1: Resistance is defined as the resistance between terminal A to terminal B. 2: INL and DNL are measured at V with V = V and V = V . W A DD B SS 3: MCP4XX1 only. 4: MCP4XX2 only, includes V and V . WZSE WFSE 5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted. 6: This specification by design. 7: Non-linearity is affected by wiper resistance (R ), which changes significantly overvoltage and W temperature. 8: The MCP4XX1 is externally connected to match the configurations of the MCP45X2 and MCP46X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network. 11: When HVC/A0 = V , the I current is less due to current into the HVC/A0 pin. See I specification. IHH DD PU  2008-2013 Microchip Technology Inc. DS22107B-page 9

MCP454X/456X/464X/466X AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C  T  +125°C (extended) A DC Characteristics All parameters apply across the specified operating ranges unless noted. V = +2.7V to 5.5V, 5k, 10k, 50k, 100k devices. DD Typical specifications represent values for V = 5.5V, T = +25°C. DD A Parameters Sym Min Typ Max Units Conditions Rheostat R-DNL -0.5 ±0.25 +0.5 LSb 5k 8-bit 5.5V, I = 900µA W Differential -1.0 +0.5 +1.0 LSb 3.0V, I = 480µA W Non-linearity (Note7) MCP45X1 -0.375 ±0.25 +0.375 LSb 7-bit 5.5V, I = 900µA (Note4, Note8) W MCP4XX2 devices -0.75 +0.5 +0.75 LSb 3.0V, IW = 480µA only (Note7) (Note4) -0.5 ±0.25 +0.5 LSb 10k 8-bit 5.5V, I = 450µA W -1.0 +0.25 +1.0 LSb 3.0V, I = 240µA W (Note7) -0.375 ±0.25 +0.375 LSb 7-bit 5.5V, I = 450µA W -0.75 +0.5 +0.75 LSb 3.0V, I = 240µA W (Note7) -0.5 ±0.25 +0.5 LSb 50k 8-bit 5.5V, I = 90µA W -0.5 ±0.25 +0.5 LSb 3.0V, I = 48µA W (Note7) -0.375 ±0.25 +0.375 LSb 7-bit 5.5V, I = 90µA W -0.375 ±0.25 +0.375 LSb 3.0V, I = 48µA W (Note7) -0.5 ±0.25 +0.5 LSb 100k 8-bit 5.5V, I = 45µA W -0.5 ±0.25 +0.5 LSb 3.0V, I = 24µA W (Note7) -0.375 ±0.25 +0.375 LSb 7-bit 5.5V, I = 45µA W -0.375 ±0.25 +0.375 LSb 3.0V, I = 24µA W (Note7) Capacitance (P ) C — 75 — pF f =1MHz, Code = Full-Scale A AW Capacitance (P ) C — 120 — pF f =1MHz, Code = Full-Scale w W Capacitance (P ) C — 75 — pF f =1MHz, Code = Full-Scale B BW Note 1: Resistance is defined as the resistance between terminal A to terminal B. 2: INL and DNL are measured at V with V = V and V = V . W A DD B SS 3: MCP4XX1 only. 4: MCP4XX2 only, includes V and V . WZSE WFSE 5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted. 6: This specification by design. 7: Non-linearity is affected by wiper resistance (R ), which changes significantly overvoltage and W temperature. 8: The MCP4XX1 is externally connected to match the configurations of the MCP45X2 and MCP46X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network. 11: When HVC/A0 = V , the I current is less due to current into the HVC/A0 pin. See I specification. IHH DD PU DS22107B-page 10  2008-2013 Microchip Technology Inc.

MCP454X/456X/464X/466X AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C  T  +125°C (extended) A DC Characteristics All parameters apply across the specified operating ranges unless noted. V = +2.7V to 5.5V, 5k, 10k, 50k, 100k devices. DD Typical specifications represent values for V = 5.5V, T = +25°C. DD A Parameters Sym Min Typ Max Units Conditions Digital Inputs/Outputs (SDA, SCK, HVC/A0, A1, A2, WP) Schmitt Trigger V 0.45V — — V All 2.7V  V  5.5V IH DD DD High-Input Inputs (Allows 2.7V Digital V with DD Threshold except 5V Analog V ) DD SDA 0.5V — — V 1.8V  V  2.7V DD DD and SCL 0.7V — V V 100kHz DD MAX SDA 0.7V — V V 400kHz DD MAX and 0.7V — V V 1.7MHz DD MAX SCL 0.7V — V V 3.4Mhz DD MAX Schmitt Trigger V — — 0.2V V All inputs except SDA and SCL IL DD Low-Input -0.5 — 0.3V V 100kHz DD Threshold SDA -0.5 — 0.3V V 400kHz DD and -0.5 — 0.3V V 1.7MHz DD SCL -0.5 — 0.3V V 3.4Mhz DD Hysteresis of V — 0.1V — V All inputs except SDA and SCL HYS DD Schmitt Trigger N.A. — — V V < 2.0V DD Inputs (Note6) 100kHz N.A. — — V V  2.0V DD SDA 0.1V — — V V < 2.0V DD DD and 400kHz 0.05V — — V V  2.0V DD SCL DD 0.1V — — V 1.7MHz DD 0.1V — — V 3.4Mhz DD High-Voltage Input V 8.5 — 12.5 (6) V Threshold for WiperLock™ Technology IHHEN Entry Voltage High-Voltage Input V — — V + V IHHEX DD Exit Voltage 0.8V (6) High-Voltage Limit V — — 12.5 (6) V Pin can tolerate V or less. MAX MAX Note 1: Resistance is defined as the resistance between terminal A to terminal B. 2: INL and DNL are measured at V with V = V and V = V . W A DD B SS 3: MCP4XX1 only. 4: MCP4XX2 only, includes V and V . WZSE WFSE 5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted. 6: This specification by design. 7: Non-linearity is affected by wiper resistance (R ), which changes significantly overvoltage and W temperature. 8: The MCP4XX1 is externally connected to match the configurations of the MCP45X2 and MCP46X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network. 11: When HVC/A0 = V , the I current is less due to current into the HVC/A0 pin. See I specification. IHH DD PU  2008-2013 Microchip Technology Inc. DS22107B-page 11

MCP454X/456X/464X/466X AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C  T  +125°C (extended) A DC Characteristics All parameters apply across the specified operating ranges unless noted. V = +2.7V to 5.5V, 5k, 10k, 50k, 100k devices. DD Typical specifications represent values for V = 5.5V, T = +25°C. DD A Parameters Sym Min Typ Max Units Conditions Output Low V V — 0.2V V V < 2.0V, I = 1mA OL SS DD DD OL Voltage (SDA) V — 0.4 V V  2.0V, I = 3mA SS DD OL Weak Pull-up / I — — 1.75 mA Internal V pull-up, V pull-down PU DD IHH Pull-down Current V = 5.5V, V = 12.5V DD IHH — 170 — µA HVC pin, V = 5.5V, V = 3V DD HVC HVC Pull-up / R — 16 — k V = 5.5V, V = 3V HVC DD HVC Pull-down Resistance Input Leakage Cur- I -1 — 1 µA V = V and V = V IL IN DD IN SS rent Pin Capacitance C , C — 10 — pF f = 3.4MHz IN OUT C RAM (Wiper) Value Value Range N 0h — 1FFh hex 8-bit device 0h — 1FFh hex 7-bit device TCON POR/BOR N 1FFh hex All Terminals connected TCON Value EEPROM Endurance E — 1M — Cycles ndurance EEPROM Range N 0h — 1FFh hex Initial Factory N 80h hex 8-bit WiperLock Technology = Off Setting 40h hex 7-bit WiperLock Technology = Off EEPROM t — 5 10 ms WC Programming Write Cycle Time Power Requirements Power Supply PSS — 0.0015 0.0035 %/% 8-bit V = 2.7V to 5.5V, DD Sensitivity V = 2.7V, Code = 80h A (MCP45X2 and — 0.0015 0.0035 %/% 7-bit V = 2.7V to 5.5V, DD MCP46X2 only) V = 2.7V, Code = 40h A Note 1: Resistance is defined as the resistance between terminal A to terminal B. 2: INL and DNL are measured at V with V = V and V = V . W A DD B SS 3: MCP4XX1 only. 4: MCP4XX2 only, includes V and V . WZSE WFSE 5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted. 6: This specification by design. 7: Non-linearity is affected by wiper resistance (R ), which changes significantly overvoltage and W temperature. 8: The MCP4XX1 is externally connected to match the configurations of the MCP45X2 and MCP46X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network. 11: When HVC/A0 = V , the I current is less due to current into the HVC/A0 pin. See I specification. IHH DD PU DS22107B-page 12  2008-2013 Microchip Technology Inc.

MCP454X/456X/464X/466X SCL 91 93 90 92 SDA START STOP Condition Condition FIGURE 1-1: I2C Bus Start/Stop Bits Timing Waveforms. TABLE 1-1: I2C BUS START/STOP BITS REQUIREMENTS I2C AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature –40C  TA  +125C (Extended) Operating Voltage VDD range is described in AC/DC characteristics Param. Symbol Characteristic Min Max Units Conditions No. F Standard mode 0 100 kHz C = 400pF, 1.8V - 5.5V SCL b Fast mode 0 400 kHz C = 400pF, 2.7V - 5.5V b High-Speed 1.7 0 1.7 MHz C = 400pF, 4.5V - 5.5V b High-Speed 3.4 0 3.4 MHz C = 100pF, 4.5V - 5.5V b D102 Cb Bus capacitive 100kHz mode — 400 pF loading 400kHz mode — 400 pF 1.7MHz mode — 400 pF 3.4MHz mode — 100 pF 90 TSU:STA START condition 100kHz mode 4700 — ns Only relevant for repeated Setup time 400kHz mode 600 — ns START condition 1.7MHz mode 160 — ns 3.4MHz mode 160 — ns 91 THD:STA START condition 100kHz mode 4000 — ns After this period the first Hold time 400kHz mode 600 — ns clock pulse is generated 1.7MHz mode 160 — ns 3.4MHz mode 160 — ns 92 TSU:STO STOP condition 100kHz mode 4000 — ns Setup time 400kHz mode 600 — ns 1.7MHz mode 160 — ns 3.4MHz mode 160 — ns 93 THD:STO STOP condition 100kHz mode 4000 — ns Hold time 400kHz mode 600 — ns 1.7MHz mode 160 — ns 3.4MHz mode 160 — ns  2008-2013 Microchip Technology Inc. DS22107B-page 13

MCP454X/456X/464X/466X 103 100 102 101 SCL 90 106 91 107 92 SDA In 109 109 110 SDA Out FIGURE 1-2: I2C Bus Data Timing. T ABLE 1-2: I2C BUS DATA REQUIREMENTS (SLAVE MODE) I2C AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature –40C  TA  +125C (Extended) Operating Voltage V range is described in AC/DC characteristics DD Param. Sym Characteristic Min Max Units Conditions No. 100 THIGH Clock high time 100kHz mode 4000 — ns 1.8V-5.5V 400kHz mode 600 — ns 2.7V-5.5V 1.7MHz mode 120 ns 4.5V-5.5V 3.4MHz mode 60 — ns 4.5V-5.5V 101 TLOW Clock low time 100kHz mode 4700 — ns 1.8V-5.5V 400kHz mode 1300 — ns 2.7V-5.5V 1.7MHz mode 320 ns 4.5V-5.5V 3.4MHz mode 160 — ns 4.5V-5.5V Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (minimum 300ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 2: A fast-mode (400kHz) I2C-bus device can be used in a standard-mode (100kHz) I2C-bus system, but the requirement t 250ns must then be met. This will automatically be the case if the device does not SU;DAT stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line. T max.+t =1000+250=1250ns (according to the standard-mode I2C bus specification) before R SU;DAT the SCL line is released. 3: The MCP46X1/MCP46X2 device must provide a data hold time to bridge the undefined part between V IH and V of the falling edge of the SCL signal. This specification is not a part of the I2C specification, but IL must be tested in order to ensure that the output data will meet the setup and hold specifications for the receiving device. 4: Use Cb in pF for the calculations. 5: Not tested. 6: A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do not unintentionally create a Start or Stop condition. 7: Ensured by the T 3.4MHz specification test. AA DS22107B-page 14  2008-2013 Microchip Technology Inc.

MCP454X/456X/464X/466X TABLE 1-2: I2C BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED) I2C AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature –40C  TA  +125C (Extended) Operating Voltage V range is described in AC/DC characteristics DD Param. Sym Characteristic Min Max Units Conditions No. 102A (5) TRSCL SCL rise time 100kHz mode — 1000 ns Cb is specified to be from 10 to 400pF (100pF maxi- 400kHz mode 20 + 0.1Cb 300 ns mum for 3.4MHz mode) 1.7MHz mode 20 80 ns 1.7MHz mode 20 160 ns After a Repeated Start con- dition or an Acknowledge bit 3.4MHz mode 10 40 ns 3.4MHz mode 10 80 ns After a Repeated Start condition or an Acknowl- edge bit 102B (5) TRSDA SDA rise time 100kHz mode — 1000 ns Cb is specified to be from 10 to 400pF (100pF max 400kHz mode 20 + 0.1Cb 300 ns for 3.4MHz mode) 1.7MHz mode 20 160 ns 3.4MHz mode 10 80 ns 103A (5) TFSCL SCL fall time 100kHz mode — 300 ns Cb is specified to be from 10 to 400pF (100pF max 400kHz mode 20 + 0.1Cb 300 ns for 3.4MHz mode) 1.7MHz mode 20 80 ns 3.4MHz mode 10 40 ns 103B (5) TFSDA SDA fall time 100kHz mode — 300 ns Cb is specified to be from 400kHz mode 20 + 0.1Cb (4) 300 ns 10 to 400pF (100pF max for 3.4MHz mode) 1.7MHz mode 20 160 ns 3.4MHz mode 10 80 ns 106 T Data input hold 100kHz mode 0 — ns 1.8V-5.5V, Note6 HD:DAT time 400kHz mode 0 — ns 2.7V-5.5V, Note6 1.7MHz mode 0 — ns 4.5V-5.5V, Note6 3.4MHz mode 0 — ns 4.5V-5.5V, Note6 Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (minimum 300ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 2: A fast-mode (400kHz) I2C-bus device can be used in a standard-mode (100kHz) I2C-bus system, but the requirement t 250ns must then be met. This will automatically be the case if the device does not SU;DAT stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line. T max.+t =1000+250=1250ns (according to the standard-mode I2C bus specification) before R SU;DAT the SCL line is released. 3: The MCP46X1/MCP46X2 device must provide a data hold time to bridge the undefined part between V IH and V of the falling edge of the SCL signal. This specification is not a part of the I2C specification, but IL must be tested in order to ensure that the output data will meet the setup and hold specifications for the receiving device. 4: Use Cb in pF for the calculations. 5: Not tested. 6: A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do not unintentionally create a Start or Stop condition. 7: Ensured by the T 3.4MHz specification test. AA  2008-2013 Microchip Technology Inc. DS22107B-page 15

MCP454X/456X/464X/466X TABLE 1-2: I2C BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED) I2C AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature –40C  TA  +125C (Extended) Operating Voltage V range is described in AC/DC characteristics DD Param. Sym Characteristic Min Max Units Conditions No. 107 T Data input setup 100kHz mode 250 — ns Note2 SU:DAT time 400kHz mode 100 — ns 1.7MHz mode 10 — ns 3.4MHz mode 10 — ns 109 T Output valid 100kHz mode — 3450 ns Note1 AA from clock 400kHz mode — 900 ns 1.7MHz mode — 150 ns Cb = 100pF, Note1, Note7 — 310 ns Cb = 400pF, Note1, Note5 3.4MHz mode — 150 ns Cb = 100pF, Note1 110 TBUF Bus free time 100kHz mode 4700 — ns Time the bus must be free before a new transmission 400kHz mode 1300 — ns can start 1.7MHz mode N.A. — ns 3.4MHz mode N.A. — ns T Input filter spike 100kHz mode — 50 ns Philips Spec states N.A. SP suppression 400kHz mode — 50 ns (SDA and SCL) 1.7MHz mode — 10 ns Spike suppression 3.4MHz mode — 10 ns Spike suppression Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (minimum 300ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 2: A fast-mode (400kHz) I2C-bus device can be used in a standard-mode (100kHz) I2C-bus system, but the requirement t 250ns must then be met. This will automatically be the case if the device does not SU;DAT stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line. T max.+t =1000+250=1250ns (according to the standard-mode I2C bus specification) before R SU;DAT the SCL line is released. 3: The MCP46X1/MCP46X2 device must provide a data hold time to bridge the undefined part between V IH and V of the falling edge of the SCL signal. This specification is not a part of the I2C specification, but IL must be tested in order to ensure that the output data will meet the setup and hold specifications for the receiving device. 4: Use Cb in pF for the calculations. 5: Not tested. 6: A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do not unintentionally create a Start or Stop condition. 7: Ensured by the T 3.4MHz specification test. AA DS22107B-page 16  2008-2013 Microchip Technology Inc.

MCP454X/456X/464X/466X TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, V =+2.7V to +5.5V, V =GND. DD SS Parameters Sym Min Typ Max Units Conditions Temperature Ranges Specified Temperature Range T -40 — +125 °C A Operating Temperature Range T -40 — +125 °C A Storage Temperature Range T -65 — +150 °C A Thermal Package Resistances Thermal Resistance, 8L-DFN (3x3)  — 56.7 — °C/W JA Thermal Resistance, 8L-MSOP  — 211 — °C/W JA Thermal Resistance, 8L-SOIC  — 149.5 — °C/W JA Thermal Resistance, 10L-DFN (3x3)  — 57 — °C/W JA Thermal Resistance, 10L-MSOP  — 202 — °C/W JA Thermal Resistance, 14L-MSOP  — N/A — °C/W JA Thermal Resistance, 14L-SOIC  — 95.3 — °C/W JA Thermal Resistance, 16L-QFN  — 47 — °C/W JA  2008-2013 Microchip Technology Inc. DS22107B-page 17

MCP454X/456X/464X/466X NOTES: DS22107B-page 18  2008-2013 Microchip Technology Inc.

MCP454X/456X/464X/466X 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS 250 1000 450 3.4MHz, 5.5V 800 400 350 3.4MHz, 2.7V 200 600 I (uA)DD 122350500000 1.7MHz, 2.7V 4001k10H.07zkM,H 5Hz.z5, ,V5 5.5.5VV R (kOhms)HVC110500 IHVC --0244200000000 I (µA)HVC 100 400kHz, 2.7V 100kHz, 2.7V 50 -600 50 RHVC -800 0 0 -1000 -40 0 40 80 120 2 3 4 5 6 7 8 9 10 Temperature (°C) V (V) HVC FIGURE 2-1: Device Current (I ) vs. I2C FIGURE 2-4: HVC Pull-up/Pull-down DD Frequency (f ) and Ambient Temperature Resistance (R ) and Current (I ) vs. HVC SCL HVC HVC (V = 2.7V and 5.5V). Input Voltage (V ) (V = 5.5V). DD HVC DD 3 12 dby (uA)2.25 5.5V hreshold (V) 1068 5.55.V5V E Exinttry 2.7V Entry n1.5 T Ista 1 C V PP 4 2.7V Exit V 2 2.7V H 0.5 0 -40 0 40 80 120 -40 -20 0 20 40 60 80 100 120 Temperature (°C) Ambient Temperature (°C) FIGURE 2-2: Device Current (I ) and FIGURE 2-5: HVC High Input Entry/Exit SHDN V . (HVC = V ) vs. Ambient Temperature. Threshold vs. Ambient Temperature and V . DD DD DD 420 400 A) 380 µ (E 360 RIT 5.5V IW 340 320 300 -40 0 40 80 120 Temperature (°C) FIGURE 2-3: Write Current (I ) vs. WRITE Ambient Temperature.  2008-2013 Microchip Technology Inc. DS22107B-page 19

MCP454X/456X/464X/466X Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS 120 -40C Rw 25C Rw 85C Rw 125C Rw 0.3 120 -40C Rw 25C Rw 85C Rw 125C Rw 1.25 R) W 100 --4400CC DINNLL 2255CC IDNNLL 8855CC IDNNLL 112255CC IDNNLL 0.2 R) W 100 --4400CC IDNNLL 2255CC IDNNLL 8855CC IDNNLL 112255CC IDNNLL 0.75 Wiper Resistance ((ohms) 468000 125°C8D5N°CL -40°C 25°CINL RW --0000.1..21Error (LSb) Wiper Resistance ((ohms) 468000 125°C85°C 25°C-40°CINL RW DNL --000.2..72555Error (LSb) 20 -0.3 20 -1.25 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 Wiper Setting (decimal) Wiper Setting (decimal) FIGURE 2-6: 5k Pot Mode – R (), FIGURE 2-8: 5k Rheo Mode – R (), W W INL (LSb), DNL (LSb) vs. Wiper Setting and INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (V = 5.5V). Ambient Temperature (V = 5.5V). DD DD 300 300 0.3 -40C Rw 25C Rw 85C Rw 125C Rw ) W 260 ---444000CCC IRDNwNLL 222555CCC IRDNwNLL 888555CCC IRDNwNLL 111222555CCC RDINwNLL 0.2 ) W 260 --4400CC IDNNLL 2255CC IDNNLL 8855CC IDNNLL 112255CC DINNLL 6 Wiper Resistance (R(ohms)11120482600000 DNL 85°C12I5N°RCLW --0000.1..21Error (LSb) Wiper Resistance (R(ohms)11120482600000 -40°C RW INL 024 Error (LSb) -40°C 25°C 125°C 85°C25°C DNL 20 -0.3 20 -2 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 Wiper Setting (decimal) Wiper Setting (decimal) FIGURE 2-7: 5k Pot Mode – R (), FIGURE 2-9: 5k Rheo Mode – R (), W W INL (LSb), DNL (LSb) vs. Wiper Setting and INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (V = 3.0V). Ambient Temperature (V = 3.0V). DD DD DS22107B-page 20  2008-2013 Microchip Technology Inc.

MCP454X/456X/464X/466X Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS 5300 6000 ) B RA 5250 5000 e ( al Resistanc(Ohms) 55125000 2.7V R (Ohms)WB234000000000 -40°C n mi 5100 1000 25°C o 5.5V 85°C N 125°C 5050 0 -40 0 40 80 120 0 32 64 96 128 160 192 224 256 Ambient Temperature (°C) Wiper Setting (decimal) FIGURE 2-10: 5k – Nominal Resistance FIGURE 2-11: 5k – R () vs. Wiper WB () vs. Ambient Temperature and V . Setting and Ambient Temperature. DD  2008-2013 Microchip Technology Inc. DS22107B-page 21

MCP454X/456X/464X/466X Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS FIGURE 2-12: 5k – Low-Voltage FIGURE 2-15: 5k – Low-Voltage Decrement Wiper Settling Time (V = 5.5V) Increment Wiper Settling Time (V = 5.5V) DD DD (1µs/Div). (1µs/Div). FIGURE 2-13: 5k – Low-Voltage FIGURE 2-16: 5k – Low-Voltage Decrement Wiper Settling Time (V = 2.7V) Increment Wiper Settling Time (V = 2.7V) DD DD (1µs/Div). (1µs/Div). FIGURE 2-14: 5k – Power-Up Wiper Response Time (20ms/Div). DS22107B-page 22  2008-2013 Microchip Technology Inc.

MCP454X/456X/464X/466X Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS 120 0.3 120 1 -40C Rw 25C Rw 85C Rw 125C Rw -40C Rw 25C Rw 85C Rw 125C Rw ) W 100 --4400CC IDNNLL 2255CC IDNNLL 8855CC IDNNLL 112255CC IDNNLL 0.2 ) W 100 --4400CC DINNLL 2255CC IDNNLL 8855CC IDNNLL 112255CC IDNNLL R R 0.5 Wiper Resistance ((ohms) 468000 125°C 85D°CN2L5°C -40°C INL RW --0000.1..21Error (LSb) Wiper Resistance ((ohms) 468000 125°C85°C 25°C -40°INCL RW DNL -00.5Error (LSb) 20 -0.3 20 -1 0 25 50 75 100125150175200225250 0 32 64 96 128 160 192 224 256 Wiper Setting (decimal) Wiper Setting (decimal) FIGURE 2-17: 10k Pot Mode – R (), FIGURE 2-19: 10k Rheo Mode – R (), W W INL (LSb), DNL (LSb) vs. Wiper Setting and INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (V = 5.5V). Ambient Temperature (V = 5.5V). DD DD 300 4 300 0.3 -40C Rw 25C Rw 85C Rw 125C Rw -40C Rw 25C Rw 85C Rw 125C Rw -40C INL 25C INL 85C INL 125C INL ) W 260 --4400CC IDNNLL 2255CC IDNNLL 8855CC IDNNLL 112255CC DINNLL 0.2 ) W 260 -40C DNL 25C DNL 85C DNL 125C DNL 3 R R INL Wiper Resistance ((ohms)11120482600000 DNL -40°C IRNWL --0000.1..21Error (LSb) Wiper Resistance ((ohms)11120482600000 -40°C DNL RW -0121 Error (LSb) 125°C 85°C 25°C 125°C 85°C 25°C 20 -0.3 20 -2 0 32 64 96 128 160 192 224 256 0 25 50 75 100125150175200225250 Wiper Setting (decimal) Wiper Setting (decimal) FIGURE 2-18: 10k Pot Mode – R (), FIGURE 2-20: 10k Rheo Mode – R (), W W INL (LSb), DNL (LSb) vs. Wiper Setting and INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (V = 3.0V). Ambient Temperature (V = 3.0V). DD DD  2008-2013 Microchip Technology Inc. DS22107B-page 23

MCP454X/456X/464X/466X Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS 10300 12000 ) B 10250 A 10000 R 10200 al Resistance ((Ohms) 11110000001105050000 5.52V.7V R (Ohms)WB 468000000000 -40°C min 9950 1.8V 2000 2855°°CC o 9900 N 125°C 9850 0 -40 0 40 80 120 0 32 64 96 128 160 192 224 256 Ambient Temperature (°C) Wiper Setting (decimal) FIGURE 2-21: 10k – Nominal Resistance FIGURE 2-22: 10k – R () vs. Wiper WB () vs. Ambient Temperature and V . Setting and Ambient Temperature. DD DS22107B-page 24  2008-2013 Microchip Technology Inc.

MCP454X/456X/464X/466X Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS FIGURE 2-23: 10k – Low-Voltage FIGURE 2-26: 10k – Low-Voltage Decrement Wiper Settling Time (V = 5.5V) Increment Wiper Settling Time (V = 5.5V) DD DD (1µs/Div). (1µs/Div). FIGURE 2-24: 10k – Low-Voltage FIGURE 2-27: 10k – Low-Voltage Decrement Wiper Settling Time (V = 2.7V) Increment Wiper Settling Time (V = 2.7V) DD DD (1µs/Div). (1µs/Div). FIGURE 2-25: 10k – Power-Up Wiper Response Time (1µs/Div).  2008-2013 Microchip Technology Inc. DS22107B-page 25

MCP454X/456X/464X/466X Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS 120 0.3 120 0.3 -40C Rw 25C Rw 85C Rw 125C Rw -40C Rw 25C Rw 85C Rw 125C Rw -40C INL 25C INL 85C INL 125C INL -40C INL 25C INL 85C INL 125C INL )W 100 -40C DNL 25C DNL 85C DNL 125C DNL 0.2 )W 100 -40C DNL 25C DNL 85C DNL 125C DNL 0.2 R R INL er Resistance ((ohms) 6800 DNL INL -000.1.1Error (LSb) er Resistance ((ohms) 6800 DNL -000.1.1Error (LSb) Wip 40 25°C -40°C RW -0.2 Wip 40 125°C 85°C 25°C -40°C RW -0.2 125°C 85°C 20 -0.3 20 -0.3 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 Wiper Setting (decimal) Wiper Setting (decimal) FIGURE 2-28: 50k Pot Mode – R (), FIGURE 2-30: 50k Rheo Mode – R (), W W INL (LSb), DNL (LSb) vs. Wiper Setting and INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (V = 5.5V). Ambient Temperature (V = 5.5V). DD DD 300 1 300 0.3 -40C Rw 25C Rw 85C Rw 125C Rw Wiper Resistance (R)W(ohms)11122048266000000 ---444000CCCD IRDNNwNLLL 222555CCC -IRD4NwN0LL°C 888IRN555CCCWL IRDNwNLL 111222555CCC RDINwNLL --00000..12..21Error (LSb) Wiper Resistance (R) W(ohms)11122048266000000 --4400CCD IDNNNLLL 2255CC IDNNI-LN4L0L°C88R55CCW IDNNLL 112255CC DINNLL ---0000000...257...7525555 Error (LSb) 125°C 85°C 25°C 125°C 85°C 25°C 20 -0.3 20 -1 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 Wiper Setting (decimal) Wiper Setting (decimal) FIGURE 2-29: 50k Pot Mode – R (), FIGURE 2-31: 50k Rheo Mode – R (), W W INL (LSb), DNL (LSb) vs. Wiper Setting and INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (V = 3.0V). Ambient Temperature (V = 3.0V). DD DD DS22107B-page 26  2008-2013 Microchip Technology Inc.

MCP454X/456X/464X/466X Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS 52500 60000 ) AB 52000 50000 R nal Resistance ((Ohms) 55550011050500000000 21..78VV R (Ohms)WB234000000000000 -2450°°CC omi 49500 10000 85°C N 5.5V 125°C 49000 0 -40 0 40 80 120 0 32 64 96 128 160 192 224 256 Ambient Temperature (°C) Wiper Setting (decimal) FIGURE 2-32: 50k – Nominal Resistance FIGURE 2-33: 50k – R () vs. Wiper WB () vs. Ambient Temperature and V . Setting and Ambient Temperature. DD  2008-2013 Microchip Technology Inc. DS22107B-page 27

MCP454X/456X/464X/466X Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS FIGURE 2-34: 50k – Low-Voltage FIGURE 2-37: 50k – Low-Voltage Decrement Wiper Settling Time (V = 5.5V) Increment Wiper Settling Time (V = 5.5V) DD DD (1µs/Div). (1µs/Div). FIGURE 2-35: 50k – Low-Voltage FIGURE 2-38: 50k – Low-Voltage Decrement Wiper Settling Time (V = 2.7V) Increment Wiper Settling Time (V = 2.7V) DD DD (1µs/Div). (1µs/Div). FIGURE 2-36: 50k – Power-Up Wiper Response Time (1µs/Div). DS22107B-page 28  2008-2013 Microchip Technology Inc.

MCP454X/456X/464X/466X Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS 120 0.2 120 0.3 -40C Rw 25C Rw 85C Rw 125C Rw -40C Rw 25C Rw 85C Rw 125C Rw ) W 100 --4400CC DINNLL 2255CC IDNNLL 8855CC IDNNLL 112255CC IDNNLL ) W 100 --4400CC DINNLL 2255CC IDNNLL 8855CC IDNNLL 112255CC IDNNLL 0.2 R 0.1 R INL er Resistance ((ohms) 6800 DNL INL -00.1Error (LSb) er Resistance ((ohms) 6800 DNL -000.1.1Error (LSb) Wip 40 25°C -40°C RW Wip 40 125°C 85°C 25°C-40°C RW -0.2 125°C 85°C 20 -0.2 20 -0.3 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 Wiper Setting (decimal) Wiper Setting (decimal) FIGURE 2-39: 100k Pot Mode – R (), FIGURE 2-41: 100k Rheo Mode – R W W INL (LSb), DNL (LSb) vs. Wiper Setting and (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (V = 5.5V). Ambient Temperature (V = 5.5V). DD DD 300 0.6 300 0.2 -40C Rw 25C Rw 85C Rw 125C Rw -40C Rw 25C Rw 85C Rw 125C Rw -40C INL 25C INL 85C INL 125C INL per Resistance (R) W(ohms)111220482600000 --4400CC DDINNNLLL 2255CC IDNNLL I88RN55CCLW IDNNLL 112255CC IDNNLL --000000...011..10555Error (LSb) per Resistance (Rw) (ohms)111220482600000 -D40NCL DNL 25C DNINLL 85CR DWNL 125C DNL -0000..24.2 Error (LSb) Wi 60 -40°C -0.15 Wi 60 -40°C -0.4 125°C85°C 25°C 125°C 85°C 25°C 20 -0.2 20 -0.6 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 Wiper Setting (decimal) Wiper Setting (decimal) FIGURE 2-40: 100k Pot Mode – R (), FIGURE 2-42: 100k Rheo Mode – R W W INL (LSb), DNL (LSb) vs. Wiper Setting and (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (V = 3.0V). Ambient Temperature (V = 3.0V). DD DD  2008-2013 Microchip Technology Inc. DS22107B-page 29

MCP454X/456X/464X/466X Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS 103500 120000 ) B 103000 A 100000 R 102500 Nominal Resistance ((Ohms) 1111100000990011299050505000000000000000 2.571.V5.8VV Rwb (Ohms) 24680000000000000000 -28145520°°5°CC°CC 98500 0 -40 0 40 80 120 0 32 64 96 128 160 192 224 256 Ambient Temperature (°C) Wiper Setting (decimal) FIGURE 2-43: 100k – Nominal FIGURE 2-44: 100k – R () vs. Wiper WB Resistance () vs. Ambient Temperature and Setting and Ambient Temperature. V . DD DS22107B-page 30  2008-2013 Microchip Technology Inc.

MCP454X/456X/464X/466X Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS FIGURE 2-45: 100k – Low-Voltage FIGURE 2-47: 100k – Low-Voltage Decrement Wiper Settling Time (V = 5.5V) Increment Wiper Settling Time (V =5.5V) DD DD (1µs/Div). (1µs/Div). FIGURE 2-46: 100k – Low-Voltage FIGURE 2-48: 100k – Low-Voltage Decrement Wiper Settling Time (V = 2.7V) Increment Wiper Settling Time (V = 2.7V) DD DD (1µs/Div). (1µs/Div)  2008-2013 Microchip Technology Inc. DS22107B-page 31

MCP454X/456X/464X/466X Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS 0.12 0.1 0.09 0.1 0.08 0.07 0.08 5.5V 0.06 5.5V %0.05 %0.06 0.04 0.04 0.03 3.0V 0.02 0.02 0.01 3.0V 0 0 -40 0 40 80 120 -40 0 40 80 120 Temperature (°C) Temperature (°C) FIGURE 2-49: Resistor Network 0 to FIGURE 2-51: Resistor Network 0 to Resistor Network 1 R (5k) Mismatch vs. V Resistor Network 1 R (50k) Mismatch vs. AB DD AB and Temperature. V and Temperature. DD 0.04 0.05 0.03 0.04 0.02 0.03 5.5V 5.5V 0.01 0.02 % 0 % 0.01 -0.01 0 3.0V 3.0V -0.02 -0.01 -0.03 -0.02 -0.04 -0.03 -40 0 40 80 120 -40 10 60 110 Temperature (°C) Temperature (°C) FIGURE 2-50: Resistor Network 0 to FIGURE 2-52: Resistor Network 0 to Resistor Network 1 R (10k) Mismatch vs. Resistor Network 1 R (100k) Mismatch vs. AB AB V and Temperature. V and Temperature. DD DD DS22107B-page 32  2008-2013 Microchip Technology Inc.

MCP454X/456X/464X/466X Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS 4 230 3.5 210 2.7V 5.5V 190 3 170 V) mV) 150 V (IH 2.5 (OL 130 5.5V 2 V 110 2.7V 90 1.5 70 1 50 -40 0 40 80 120 -40 0 40 80 120 Temperature (°C) Temperature (°C) FIGURE 2-53: V (SDA, SCL) vs. V and FIGURE 2-55: V (SDA) vs. V and IH DD OL DD Temperature. Temperature (I = 3mA). OL 2 5.5V V) V (IL 1.5 2.7V 1 -40 0 40 80 120 Temperature (°C) FIGURE 2-54: V (SDA, SCL) vs. V and IL DD Temperature.  2008-2013 Microchip Technology Inc. DS22107B-page 33

MCP454X/456X/464X/466X Note: Unless otherwise indicated, T = +25°C, 2.1 Test Circuits A V = 5V, V = 0V. DD SS 4.2 +5V 4.0 A V s) 3.8 IN W + VOUT m (C 3.6 B - tW 3.4 Offset GND 3.2 2.5V DC 3.0 -40 0 40 80 120 Temperature (°C) FIGURE 2-58: -3db Gain vs. Frequency FIGURE 2-56: Nominal EEPROM Write Test. Cycle Time vs. V and Temperature. DD 1.2 floating 1 5.5V V A 0.8 A V V) W (D 0.6 2.7V W D V 0.4 I W R = V /I BW W W 0.2 B R = (V -V )/I V W W A W 0 B -40 0 40 80 120 Temperature (°C) FIGURE 2-59: R and R Measurement. FIGURE 2-57: POR/BOR Trip Point vs. BW W V and Temperature. DD DS22107B-page 34  2008-2013 Microchip Technology Inc.

MCP454X/456X/464X/466X 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table3-1. Additional descriptions of the device pins follow. TABLE 3-1: PINOUT DESCRIPTION FOR THE MCP454X/456X/464X/466X Pin Single Dual Weak Pull-up/ Standard Function Buffer Rheo Pot (1) Rheo Pot Symbol I/O down (1) Type 8L 8L 10L 14L 16L 1 1 1 1 16 HVC/A0 I HV w/ST “smart” High Voltage Command / Address 0. 2 2 2 2 1 SCL I HV w/ST No I2C clock input. 3 3 3 3 2 SDA I/O HV w/ST No I2C serial data I/O. Open Drain output 4 4 4 4 3, 4 V — P — Ground SS — — 5 5 5 P1B A Analog No Potentiometer 1 Terminal B — — 6 6 6 P1W A Analog No Potentiometer 1 Wiper Terminal — — — 7 7 P1A A Analog No Potentiometer 1 Terminal A — 5 — 8 8 P0A A Analog No Potentiometer 0 Terminal A 5 6 7 9 9 P0W A Analog No Potentiometer 0 Wiper Terminal 6 7 8 10 10 P0B A Analog No Potentiometer 0 Terminal B — — — 11 12 WP I HV w/ST “smart” Hardware EEPROM Write Protect — — — 12 13 A2 I HV w/ST “smart” Address 2 7 — 9 13 14 A1 I HV w/ST “smart” Address 1 8 8 10 14 15 V — P — Positive Power Supply Input DD — — — — 11 NC — — — No Connection 9 9 11 — 17 EP — — — Exposed Pad (Note2) Legend: HV w/ST = High Voltage tolerant input (with Schmidtt trigger input) A = Analog pins (Potentiometer terminals) I = digital input (high Z) O = digital output I/O = Input / Output P = Power Note 1: The pin’s “smart” pull-up shuts off while the pin is forced low. This is done to reduce the standby and shut- down current. 2: The DFN and QFN packages have a contact on the bottom of the package. This contact is conductively connected to the die substrate, and therefore should be unconnected or connected to the same ground as the device’s V pin. SS  2008-2013 Microchip Technology Inc. DS22107B-page 35

MCP454X/456X/464X/466X 3.1 High Voltage Command / Address 0 3.7 Potentiometer Terminal A (HVC/A0) The terminal A pin is available on the MCP4XX1 The HVC/A0 pin is the Address 0 input for the I2C devices, and is connected to the internal potentiome- interface as well as the High Voltage Command pin. At ter’s terminal A. the device’s POR/BOR, the value of the A0 address bit The potentiometer’s terminal A is the fixed connection is latched. This input, along with the A2 and A1 pins, to the Full-Scale wiper value of the digital potentiome- completes the device address. This allows up to eight ter. This corresponds to a wiper value of 0x100 for 8-bit MCP45xx/46xx devices on a single I2C bus. devices or 0x80 for 7-bit devices. During normal operation, the the voltage on this pin The terminal A pin does not have a polarity relative to determines if the I2C command is a normal command the terminal W or B pins. The terminal A pin can or a High Voltage command (when HVC/A0 = VIHH). support both positive and negative current. The voltage on terminal A must be between V and V . SS DD 3.2 Serial Clock (SCL) The terminal A pin is not available on the MCP4XX2 The SCL pin is the serial interfaces Serial Clock pin. devices, and the internally terminal A signal is floating. This pin is connected to the Host Controllers SCL pin. MCP46X1 devices have two terminal A pins, one for The MCP45XX/46XX is a slave device, so its SCL pin each resistor network. accepts only external clock signals. 3.8 Write Protect (WP) 3.3 Serial Data (SDA) The WP pin is used to force the nonvolatile memory to The SDA pin is the serial interfaces Serial Data pin. be write protected. This pin is connected to the Host Controllers SDA pin. The SDA pin is an open-drain N-channel driver. 3.9 Address 2 (A2) 3.4 Ground (V ) The A2 pin is the I2C interface’s Address 2 pin. Along SS with the A1 and A0 pins, up to 8 MCP45XX/46XX The VSS pin is the device ground reference. devices can be on a single I2C bus. 3.5 Potentiometer Terminal B 3.10 Address 1 (A1) The terminal B pin is connected to the internal The A2 pin is the I2C interface’s Address 1 pin. Along potentiometer’s terminal B. with the A2 and A0 pins, up to 8 MCP45XX/46XX The potentiometer’s terminal B is the fixed connection devices can be on a single I2C bus. to the Zero Scale wiper value of the digital potentiome- ter. This corresponds to a wiper value of 0x00 for both 3.11 Positive Power Supply Input (VDD) 7-bit and 8-bit devices. The V pin is the device’s positive power supply input. DD The terminal B pin does not have a polarity relative to The input power supply is relative to V . SS the terminal W or A pins. The terminal B pin can While the device V < V (2.7V), the electrical support both positive and negative current. The voltage DD min performance of the device may not meet the data sheet on terminal B must be between V and V . SS DD specifications. MCP46XX devices have two terminal B pins, one for each resistor network. 3.12 No Connect (NC) 3.6 Potentiometer Wiper (W) Terminal These pins should be either connected to VDD or VSS. The terminal W pin is connected to the internal potenti- 3.13 Exposed Pad (EP) ometer’s terminal W (the wiper). The wiper terminal is the adjustable terminal of the digital potentiometer. The This pad is conductively connected to the device’s sub- terminal W pin does not have a polarity relative to strate. This pad should be tied to the same potential as terminals A or B pins. The terminal W pin can support the V pin (or left unconnected). This pad could be SS both positive and negative current. The voltage on used to assist as a heat sink for the device when con- terminal W must be between V and V . nected to a PCB heat sink. SS DD MCP46XX devices have two terminal W pins, one for each resistor network. DS22107B-page 36  2008-2013 Microchip Technology Inc.

MCP454X/456X/464X/466X 4.0 FUNCTIONAL OVERVIEW 4.1.2 BROWN-OUT RESET When the device powers down, the device V will This Data Sheet covers a family of thirty-two Digital DD cross the V /V voltage. Potentiometer and Rheostat devices that will be POR BOR referred to as MCP4XXX. The MCP4XX1 devices are Once the V voltage decreases below the V /V DD POR BOR the Potentiometer configuration, while the MCP4XX2 voltage the following happens: devices are the Rheostat configuration. • Serial Interface is disabled As the Device Block Diagram shows, there are four • EEPROM Writes are disabled main functional blocks. These are: If the V voltage decreases below the V voltage DD RAM • POR/BOR Operation the following happens: • Memory Map • Volatile wiper registers may become corrupted • Resistor Network • TCON register may become corrupted • Serial Interface (I2C) As the voltage recovers above the V /V voltage POR BOR The POR/BOR operation and the Memory Map are see Section4.1.1 “Power-on Reset”. discussed in this section and the Resistor Network and I2C operation are described in their own sections. The Serial commands not completed due to a brown-out condition may cause the memory location (volatile and Device Commands commands are discussed in nonvolatile) to become corrupted. Section7.0 “Device Commands”. 4.2 Memory Map 4.1 POR/BOR Operation The device memory is 16 locations that are 9-bits wide The Power-on Reset is the case where the device has (16x9 bits). This memory space contains both volatile power applied to it, starting from the V level. The SS and nonvolatile locations (see Table4-1). Brown-out Reset occurs when power is applied to the device, and that power (voltage) drops below the spec- TABLE 4-1: MEMORY MAP ified range. The device’s RAM retention voltage (V ) is lower Address Function Memory Type RAM than the POR/BOR voltage trip point (VPOR/VBOR). The 00h Volatile Wiper 0 RAM maximum V /V voltage is less than 1.8V. POR BOR 01h Volatile Wiper 1 RAM When V /V < V < 2.7V, the electrical POR BOR DD 02h Nonvolatile Wiper 0 EEPROM performance may not meet the data sheet specifications. In this region, the device is capable of 03h Nonvolatile Wiper 1 EEPROM reading and writing to its EEPROM and incrementing, 04h Volatile TCON Register RAM decrementing, reading and writing to its volatile 05h Status Register RAM memory if the proper serial command is executed. 06h Data EEPROM EEPROM 4.1.1 POWER-ON RESET 07h Data EEPROM EEPROM When the device powers up, the device V will cross 08h Data EEPROM EEPROM DD the VPOR/VBOR voltage. Once the VDD voltage crosses 09h Data EEPROM EEPROM the V /V voltage the following happens: POR BOR 0Ah Data EEPROM EEPROM • Volatile wiper register is loaded with value in the 0Bh Data EEPROM EEPROM corresponding nonvolatile wiper register 0Ch Data EEPROM EEPROM • The TCON register is loaded its default value 0Dh Data EEPROM EEPROM • The device is capable of digital operation 0Eh Data EEPROM EEPROM 0Fh Data EEPROM EEPROM  2008-2013 Microchip Technology Inc. DS22107B-page 37

MCP454X/456X/464X/466X 4.2.1 NONVOLATILE MEMORY 4.2.1.4 Special Features (EEPROM) There are three nonvolatile bits that are not directly This memory can be grouped into two uses of nonvol- mapped into the address space. These bits control the atile memory. These are: following functions: • General Purpose Registers • EEPROM Write Protect • Nonvolatile Wiper Registers • WiperLock Technology for Nonvolatile Wiper 0 The nonvolatile wipers starts functioning below the • WiperLock Technology for Nonvolatile Wiper 1 devices VPOR/VBOR trip point. The operation of WiperLock Technology is discussed in Section5.3. The state of the WL0, WL1, and WP bits 4.2.1.1 General Purpose Registers is reflected in the STATUS register (see Register4-1). These locations allow the user to store up to 10 (9-bit) locations worth of information. EEPROM Write Protect 4.2.1.2 Nonvolatile Wiper Registers All internal EEPROM memory can be Write Protected. When EEPROM memory is Write Protected, Write These locations contain the wiper values that are commands to the internal EEPROM are prevented. loaded into the corresponding volatile wiper register whenever the device has a POR/BOR event. There are Write Protect (WP) can be enabled/disabled by two up to two registers, one for each resistor network. methods. These are: The nonvolatile wiper register enables stand-alone • External WP Hardware pin (MCP46X1 devices operation of the device (without Microcontroller control) only) after being programmed to the desired value. • Nonvolatile configuration bit High Voltage commands are required to enable and 4.2.1.3 Factory Initialization of Nonvolatile disable the nonvolatile WP bit. These commands are Memory (EEPROM) shown in Section7.8 “Modify Write Protect or Wip- The Nonvolatile Wiper values will be initialized to erLock Technology (High Voltage)”. mid-scale value. This is shown in Table4-2. To write to EEPROM, both the external WP pin and the The General purpose EEPROM memory will be internal WP EEPROM bit must be disabled. Write programmed to a default value of 0xFF. Protect does not block commands to the volatile registers. It is good practice in the manufacturing flow to configure the device to your desired settings. 4.2.2 VOLATILE MEMORY (RAM) TABLE 4-2: DEFAULT FACTORY There are four Volatile Memory locations. These are: SETTINGS SELECTION • Volatile Wiper 0 Wiper g • Volatile Wiper 1 Resistance Code Typical ValueRAB Default POR Wiper Setting 8-bCitod7e-bit WiperLock™ Technology and rite Protect Settin ••TrehtST(eeDet naruvtmtiauoolisnl naR aRtveilloe esClg tisaoimstgnoteeterr m roN( Vlo e(RrtTywAC MosO)rt.kaN rd)ts eR vefiucgenissct teoiornn lyin)g at the RAM W -502 5.0k Mid-scale 80h 40h Disabled -103 10.0k Mid-scale 80h 40h Disabled -503 50.0k Mid-scale 80h 40h Disabled -104 100.0k Mid-scale 80h 40h Disabled DS22107B-page 38  2008-2013 Microchip Technology Inc.

MCP454X/456X/464X/466X 4.2.2.1 Status (STATUS) Register This register contains four status bits. These bits show the state of the WiperLock bits, the Write Protect bit, and if an EEPROM write cycle is active. The STATUS register can be accessed via the READ commands. Register4-1 describes each STATUS register bit. The STATUS register is placed at Address 05h. REGISTER 4-1: STATUS REGISTER (ADDRESS = 0x05) R-1 R-1 R-1 R-1 R-1 R-0 R-x R-x R-x D8:D4 EEWA WL1 (1) WL0 (1) WP (1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 8-4 D8:D4: Reserved. Forced to “1” bit 3 EEWA: EEPROM Write Active Status bit This bit indicates if the EEPROM Write Cycle is occurring. 1 = An EEPROM Write cycle is currently occurring. Only serial commands to the Volatile memory locations are allowed (addresses 00h, 01h, 04h, and 05h) 0 = An EEPROM Write cycle is NOT currently occurring bit 2 WL1: WiperLock Status bit for Resistor Network 1 (Refer to Section5.3 “WiperLock™ Technology” for further information) WiperLock (WL) prevents the Volatile and Nonvolatile Wiper 1 addresses and the TCON register bits R1HW, R1A, R1W, and R1B from being written to. High Voltage commands are required to enable and disable WiperLock Technology. 1 = Wiper and TCON register bits R1HW, R1A, R1W, and R1B of Resistor Network 1 (Pot 1) are “Locked” (Write Protected) 0 = Wiper and TCON of Resistor Network 1 (Pot 1) can be modified Note: The WL1 bit always reflects the result of the last programming cycle to the nonvolatile WL1 bit. After a POR or BOR event, the WL1 bit is loaded with the nonvolatile WL1 bit value. bit 1 WL0: WiperLock Status bit for Resistor Network 0 (Refer to Section5.3 “WiperLock™ Technology” for further information) The WiperLock Technology bits (WLx) prevents the Volatile and Nonvolatile Wiper 0 addresses and the TCON register bits R0HW, R0A, R0W, and R0B from being written to. High Voltage commands are required to enable and disable WiperLock Technology. 1 = Wiper and TCON register bits R0HW, R0A, R0W, and R0B of Resistor Network 0 (Pot 0) are “Locked” (Write Protected) 0 = Wiper and TCON of Resistor Network 0 (Pot 0) can be modified Note: The WL0 bit always reflects the result of the last programming cycle to the nonvolatile WL0 bit. After a POR or BOR event, the WL0 bit is loaded with the nonvolatile WL0 bit value. Note 1: Requires a High Voltage command to modify the state of this bit (for nonvolatile devices only). This bit is not directly written, but reflects the system state (for this feature).  2008-2013 Microchip Technology Inc. DS22107B-page 39

MCP454X/456X/464X/466X REGISTER 4-1: STATUS REGISTER (ADDRESS = 0x05) (CONTINUED) bit 0 WP: EEPROM Write Protect Status bit (Refer to the section EEPROM Write Protect for further information) This bit indicates the status of the write protection on the EEPROM memory. When Write Protect is enabled, writes to all nonvolatile memory are prevented. This includes the General Purpose EEPROM memory, and the nonvolatile Wiper registers. Write Protect does not block modification of the volatile wiper register values or the volatile TCON register value (via Increment, Decrement, or Write commands). This status bit is an OR of the devices Write Protect pin (WP) and the internal nonvolatile WP bit. High Voltage commands are required to enable and disable the internal WP EEPROM bit. 1 = EEPROM memory is Write Protected 0 = EEPROM memory can be written Note 1: Requires a High Voltage command to modify the state of this bit (for nonvolatile devices only). This bit is not directly written, but reflects the system state (for this feature). DS22107B-page 40  2008-2013 Microchip Technology Inc.

MCP454X/456X/464X/466X 4.2.2.2 Terminal Control (TCON) Register This register contains eight control bits. Four bits are for Wiper 0, and four bits are for Wiper 1. Register4-2 describes each bit of the TCON register. The state of each resistor network terminal connection is individually controlled. That is, each terminal connection (A, B and W) can be individually connected/ disconnected from the resistor network. This allows the system to minimize the currents through the digital potentiometer. The value that is written to this register will appear on the resistor network terminals when the serial command has completed. When the WL1 bit is enabled, writes to the TCON register bits R1HW, R1A, R1W, and R1B are inhibited. When the WL0 bit is enabled, writes to the TCON register bits R0HW, R0A, R0W, and R0B are inhibited. On a POR/BOR this register is loaded with 1FFh (9-bits), for all terminals connected. The Host Controller needs to detect the POR/BOR event and then update the Volatile TCON register value. Additionally, there is a bit which enables the operation of General Call commands.  2008-2013 Microchip Technology Inc. DS22107B-page 41

MCP454X/456X/464X/466X REGISTER 4-2: TCON BITS (ADDRESS = 0x04) (1) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 GCEN R1HW R1A R1W R1B R0HW R0A R0W R0B bit 8 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 8 GCEN: General Call Enable bit This bit specifies if I2C General Call commands are accepted 1 = Enable Device to “Accept” the General Call Address (0000h) 0 = The General Call Address is disabled bit 7 R1HW: Resistor 1 Hardware Configuration Control bit This bit forces Resistor 1 into the “shutdown” configuration of the Hardware pin 1 = Resistor 1 is NOT forced to the hardware pin “shutdown” configuration 0 = Resistor 1 is forced to the hardware pin “shutdown” configuration bit 6 R1A: Resistor 1 Terminal A (P1A pin) Connect Control bit This bit connects/disconnects the Resistor 1 Terminal A to the Resistor 1 Network 1 = P1A pin is connected to the Resistor 1 Network 0 = P1A pin is disconnected from the Resistor 1 Network bit 5 R1W: Resistor 1 Wiper (P1W pin) Connect Control bit This bit connects/disconnects the Resistor 1 Wiper to the Resistor 1 Network 1 = P1W pin is connected to the Resistor 1 Network 0 = P1W pin is disconnected from the Resistor 1 Network bit 4 R1B: Resistor 1 Terminal B (P1B pin) Connect Control bit This bit connects/disconnects the Resistor 1 Terminal B to the Resistor 1 Network 1 = P1B pin is connected to the Resistor 1 Network 0 = P1B pin is disconnected from the Resistor 1 Network bit 3 R0HW: Resistor 0 Hardware Configuration Control bit This bit forces Resistor 0 into the “shutdown” configuration of the Hardware pin 1 = Resistor 0 is NOT forced to the hardware pin “shutdown” configuration 0 = Resistor 0 is forced to the hardware pin “shutdown” configuration bit 2 R0A: Resistor 0 Terminal A (P0A pin) Connect Control bit This bit connects/disconnects the Resistor 0 Terminal A to the Resistor 0 Network 1 = P0A pin is connected to the Resistor 0 Network 0 = P0A pin is disconnected from the Resistor 0 Network bit 1 R0W: Resistor 0 Wiper (P0W pin) Connect Control bit This bit connects/disconnects the Resistor 0 Wiper to the Resistor 0 Network 1 = P0W pin is connected to the Resistor 0 Network 0 = P0W pin is disconnected from the Resistor 0 Network bit 0 R0B: Resistor 0 Terminal B (P0B pin) Connect Control bit This bit connects/disconnects the Resistor 0 Terminal B to the Resistor 0 Network 1 = P0B pin is connected to the Resistor 0 Network 0 = P0B pin is disconnected from the Resistor 0 Network Note 1: These bits do not affect the wiper register values. DS22107B-page 42  2008-2013 Microchip Technology Inc.

MCP454X/456X/464X/466X 5.0 RESISTOR NETWORK 5.1 Resistor Ladder Module The Resistor Network has either 7-bit or 8-bit resolu- The resistor ladder is a series of equal value resistors tion. Each Resistor Network allows zero scale to (RS) with a connection point (tap) between the two full-scale connections. Figure5-1 shows a block dia- resistors. The total number of resistors in the series gram for the resistive network of a device. (ladder) determines the RAB resistance (see Figure5-1). The end points of the resistor ladder are The Resistor Network is made up of several parts. connected to analog switches which are connected to These include: the device Terminal A and Terminal B pins. The R AB • Resistor Ladder (and R ) resistance has small variations over voltage S • Wiper and temperature. • Shutdown (Terminal Connections) For an 8-bit device, there are 256 resistors in a string Devices have either one or two resistor networks, between terminal A and terminal B. The wiper can be These are referred to as Pot 0 and Pot 1. set to tap onto any of these 256 resistors thus providing 257 possible settings (including terminal A and terminal A B). For a 7-bit device, there are 128 resistors in a string 8-Bit 7-Bit between terminal A and terminal B. The wiper can be N = N = 256 128 set to tap onto any of these 128 resistors thus providing (100h) (80h) 129 possible settings (including terminal A and terminal R (1) R W B). S 255 127 Equation5-1 shows the calculation for the step resistance. RS RW (1) (FFh) (7Fh) 254 126 EQUATION 5-1: RS CALCULATION (FEh) (7Eh) R (1) R W R RAB S RS = ---2---5A---6-B--- 8-bit Device W R AB 1 1 RS = ---1---2---8----- 7-bit Device (01h) (01h) R (1) R W S 0 0 (00h) (00h) R (1) W Analog Mux B Note1: The wiper resistance is dependent on several factors including, wiper code, device V , Terminal voltages (on A, B, DD and W), and temperature. Also for the same conditions, each tap selection resistance has a small variation. This R variation has greater effects on W some specifications (such as INL) for the smaller resistance devices (5.0k) compared to larger resistance devices (100.0k). FIGURE 5-1: Resistor Block Diagram.  2008-2013 Microchip Technology Inc. DS22107B-page 43

MCP454X/456X/464X/466X 5.2 Wiper 5.3 WiperLock™ Technology Each tap point (between the R resistors) is a The MCP4XXX device’s WiperLock technology allows S connection point for an analog switch. The opposite application-specific calibration settings to be secured in side of the analog switch is connected to a common the EEPROM without requiring the use of an additional signal which is connected to the Terminal W (Wiper) write-protect pin. There are two WiperLock Technology pin. configuration bits (WL0 and WL1). These bits prevent the Nonvolatile and Volatile addresses and bits for the A value in the volatile wiper register selects which specified resistor network from being written. analog switch to close, connecting the W terminal to the selected node of the resistor ladder. The WiperLock technology prevents the serial commands from doing the following: The wiper can connect directly to Terminal B or to Terminal A. A zero-scale connection, connects the Ter- • Changing a volatile wiper value minal W (wiper) to Terminal B (wiper setting of 000h). A • Writing to a nonvolatile wiper memory location full-scale connection, connects the Terminal W (wiper) • Changing the volatile TCON register value to Terminal A (wiper setting of 100h or 80h). In these For either Resistor Network 0 or Resistor Network 1 configurations, the only resistance between the Termi- (Potx), the WLx bit controls the following: nal W and the other Terminal (A or B) is that of the ana- log switches. • Nonvolatile Wiper Register • Volatile Wiper Register A wiper setting value greater than full-scale (wiper • Volatile TCON register bits RxHW, RxA, RxW, and setting of 100h for 8-bit device or 80h for 7-bit devices) RxB will also be a Full-Scale setting (Terminal W (wiper) connected to Terminal A). Table5-1 illustrates the full High Voltage commands are required to enable and wiper setting map. disable WiperLock. Please refer to the Modify Write Protect or WiperLock Technology (High Voltage) Equation5-2 illustrates the calculation used to deter- command for operation. mine the resistance between the wiper and terminal B. 5.3.1 POR/BOR OPERATION WHEN EQUATION 5-2: RWB CALCULATION WIPERLOCK TECHNOLOGY R N ENABLED AB R = --------------+R 8-bit Device WB 256 W The WiperLock Technology state is not affected by a POR/BOR event. A POR/BOR event will load the N = 0 to 256 (decimal) Volatile Wiper register value with the Nonvolatile Wiper R N register value, refer to Section4.1. R = ----A----B------+R 7-bit Device WB 128 W TABLE 5-2: DEFAULT FACTORY N = 0 to 128 (decimal) SETTINGS SELECTION R Wiper Code O TABLE 5-1: VOLATILE WIPER VALUE VS. Pg 7-bWit iPpeort S8e-tbtiint gPWotIPER POSIPTrIoOpNe rMtieAsP ResistanceCode Typical R ValueAB ory Default Wiper Settin 8-bit 7-bit ct 3FFh 3FFh Reserved (Full-Scale (W = A)), Fa 081h 101h Increment and Decrement -502 5.0 k Mid-scale 80h 40h commands ignored -103 10.0 k Mid-scale 80h 40h 080h 100h Full-Scale (W = A), Increment commands ignored -503 50.0 k Mid-scale 80h 40h 07Fh 0FFh W = N -104 100.0 k Mid-scale 80h 40h 041h 081 040h 080h W = N (Mid-Scale) 03Fh 07Fh W = N 001h 001 000h 000h Zero Scale (W = B) Decrement command ignored DS22107B-page 44  2008-2013 Microchip Technology Inc.

MCP454X/456X/464X/466X 5.4 Shutdown 5.4.2 INTERACTION OF RxHW BIT AND RxA, RxW, AND RxB BITS (TCON Shutdown is used to minimize the device’s current REGISTER) consumption. The MCP4XXX achieves this through the Terminal Control Register (TCON). Using the TCON bits allows each resistor network (Pot 0 and Pot 1) to be individually “shutdown”. 5.4.1 TERMINAL CONTROL REGISTER The state of the RxHW bit does NOT corrupt the other (TCON) bit values in the TCON register nor the value of the The Terminal Control (TCON) register is a volatile Volatile Wiper Registers. When the Shutdown mode is register used to configure the connection of each exited (RxHW changes state from “0” to “1”): resistor network terminal pin (A, B, and W) to the • The device returns to the Wiper setting specified Resistor Network. This bits are described in by the Volatile Wiper value Register4-2. • The RxA, RxB, and RxW bits return to controlling When the RxHW bit is a “0”, the selected resistor net- the terminal connection state of that resistor net- work is forced into the following state: work • The PxA terminal is disconnected • The PxW terminal is simultaneously connected to the PxB terminal (see Figure5-2) • The Serial Interface is NOT disabled, and all Serial Interface activity is executed • Any EEPROM write cycles are completed Alternate low power configurations may be achieved with the RxA, RxW, and RxB bits. Note1: The RxHW bits are identical to the RxHW bits of the MCP41XX/42XX devices. The MCP42XX devices also have a SHDN pin which forces the resistor network into the same state as that resistor networks RxHW bit. 2: When RxHW = “0”, the state of the TCON register RxA, RxW, and RxB bits is over- ridden (ignored). When the state of the RxHW bit returns to “1”, the TCON register RxA, RxW, and RxB bits return to controlling the terminal connection state. In other words, the RxHW bit does not corrupt the state of the RxA, RxW, and RxB bits. A k r o w W et N r o st si e R B FIGURE 5-2: Resistor Network Shutdown Configuration.  2008-2013 Microchip Technology Inc. DS22107B-page 45

MCP454X/456X/464X/466X NOTES: DS22107B-page 46  2008-2013 Microchip Technology Inc.

MCP454X/456X/464X/466X 6.0 SERIAL INTERFACE (I2C) 6.1 Signal Descriptions The MCP45XX/46XX devices support the I2C serial The I2C interface uses up to five pins (signals). These protocol. The MCP45XX/46XX I2C’s module operates are: in Slave mode (does not generate the serial clock). • SDA (Serial Data) Figure6-1 shows a typical I2C Interface connection. All • SCL (Serial Clock) I2C interface signals are high-voltage tolerant. • A0 (Address 0 bit) The MCP45XX/46XX devices use the two-wire I2C • A1 (Address 1 bit) • A2 (Address 2 bit) serial interface. This interface can operate in standard, fast or High-Speed mode. A device that sends data 6.1.1 SERIAL DATA (SDA) onto the bus is defined as transmitter, and a device receiving data as receiver. The bus has to be controlled The Serial Data (SDA) signal is the data signal of the by a master device which generates the serial clock device. The value on this pin is latched on the rising (SCL), controls the bus access and generates the edge of the SCL signal when the signal is an input. START and STOP conditions. The MCP45XX/46XX With the exception of the START and STOP conditions, device works as slave. Both master and slave can the high or low state of the SDA pin can only change operate as transmitter or receiver, but the master when the clock signal on the SCL pin is low. During the device determines which mode is activated. Communi- high period of the clock the SDA pin’s value (high or cation is initiated by the master (microcontroller) which low) must be stable. Changes in the SDA pin’s value sends the START bit, followed by the slave address while the SCL pin is HIGH will be interpreted as a byte. The first byte transmitted is always the slave START or a STOP condition. address byte, which contains the device code, the address bits, and the R/W bit. 6.1.2 SERIAL CLOCK (SCL) Refer to the Phillips I2C document for more details of The Serial Clock (SCL) signal is the clock signal of the the I2C specifications. device. The rising edge of the SCL signal latches the value on the SDA pin. The MCP45XX/46XX supports three I2C interface clock modes: Typical I2C Interface Connections • Standard Mode: clock rates up to 100kHz Host MCP4XXX • Fast Mode: clock rates up to 400kHz Controller • High-Speed Mode (HS mode): clock rates up to SCL SCL 3.4MHz SDA SDA The MCP4XXX will not strech the clock signal (SCL) since memory read acceses occur fast enough. I/O (1) HVC/A0 (2) Depending on the clock rate mode, the interface will A1 (2, 3) display different characteristics. A2 (2, 3) 6.1.3 THE ADDRESS BITS (A2:A1:A0) There are up to three hardware pins used to specify the Note1: If High voltage commands are desired, device address. The number of adress pins is some type of external circuitry needs to determined by the part number. be implemented. Address 0 is multiplexed with the High Voltage 2: These pins have internal pull-ups. If Command (HVC) function. So the state of A0 is latched faster rise times are required, then on the MCP4XXX’s POR/BOR event. external pull-ups should be added. The state of the A2 and A1 pins should be static, that is 3: This pin could be tied high, low, or they should be tied high or tied low. connected to an I/O pin of the Host Controller. 6.1.3.1 The High Voltage Command (HVC) FIGURE 6-1: Typical I2C Interface Block Signal Diagram. The High Voltage Command (HVC) signal is multi- plexed with Address 0 (A0) and is used to indicate that the command, or sequence of commands, are in the High Voltage mode. High Voltage commands allow the device’s WiperLock Technology and write protect features to be enabled and disabled. The HVC pin has an internal resistor connection to the MCP45XX/46XXs internal V signal. DD  2008-2013 Microchip Technology Inc. DS22107B-page 47

MCP454X/456X/464X/466X 6.2 I2C Operation 6.2.1.3 Acknowledge (A) Bit The MCP45XX/46XX’s I2C module is compatible with The A bit (see Figure6-4) is typically a response from the Philips I2C specification. The following lists some of the receiving device to the transmitting device. the modules features: Depending on the context of the transfer sequence, the A bit may indicate different things. Typically the Slave • 7-bit slave addressing device will supply an A response after the Start bit and • Supports three clock rate modes: eight “data” bits have been received. An A bit has the - Standard mode, clock rates up to 100kHz SDA signal low. - Fast mode, clock rates up to 400kHz - High-speed mode (HS mode), clock rates up to 3.4MHz SDA D0 A • Support Multi-Master Applications • General call addressing SCL 8 9 • Internal weak pull-ups on interface signals The I2C 10-bit addressing mode is not supported. FIGURE 6-4: Acknowledge Waveform. The Philips I2C specification only defines the field types, field lengths, timings, etc. of a frame. The frame Not A (A) Response content defines the behavior of the device. The frame content for the MCP4XXX is defined in Section7.0. The A bit has the SDA signal high. Table6-1 shows some of the conditions where the Slave Device will 6.2.1 I2C BIT STATES AND SEQUENCE issue a Not A (A). Figure6-8 shows the I2C transfer sequence. The serial If an error condition occurs (such as an A instead of A), clock is generated by the master. The following defini- then an START bit must be issued to reset the tions are used for the bit states: command state machine. • Start bit (S) • Data bit TABLE 6-1: MCP45XX/MCP46XX A / A • Acknowledge (A) bit (driven low) / RESPONSES No Acknowledge (A) bit (not driven low) Acknowledge • Repeated Start bit (Sr) • Stop bit (P) Event Bit Comment Response 6.2.1.1 Start Bit General Call A Only if GCEN bit is The Start bit (see Figure6-2) indicates the beginning of set a data transfer sequence. The Start bit is defined as the Slave Address A SDA signal falling when the SCL signal is “High”. valid Slave Address A not valid 1st Bit 2nd Bit SDA Device Mem- A After device has ory Address received address SCL and specified and command S command FIGURE 6-2: Start Bit. (AD3:AD0 and C1:C0) are an 6.2.1.2 Data Bit invalid combi- The SDA signal may change state while the SCL signal nation is Low. While the SCL signal is High, the SDA signal Communica- A After device has MUST be stable (see Figure6-5). tion during received address EEPROM write and command, cycle and valid condi- SDA 1st Bit 2nd Bit tions for EEPROM write SCL Bus Collision N.A. I2C Module Data Bit Resets, or a “Don’t Care” if the colli- FIGURE 6-3: Data Bit. sion occurs on the Masters “Start bit”. DS22107B-page 48  2008-2013 Microchip Technology Inc.

MCP454X/456X/464X/466X 6.2.1.4 Repeated Start Bit 6.2.1.5 Stop Bit The Repeated Start bit (see Figure6-5) indicates the The Stop bit (see Figure6-6) Indicates the end of the current Master Device wishes to continue communicat- I2C Data Transfer Sequence. The Stop bit is defined as ing with the current Slave Device without releasing the the SDA signal rising when the SCL signal is “High”. I2C bus. The Repeated Start condition is the same as A Stop bit resets the I2C interface of all MCP4XXX the Start condition, except that the Repeated Start bit devices. follows a Start bit (with the Data bits + A bit) and not a Stop bit. The Start bit is the beginning of a data transfer SDA A / A sequence and is defined as the SDA signal falling when the SCL signal is “High”. SCL Note1: A bus collision during the Repeated Start P condition occurs if: FIGURE 6-6: Stop Condition Receive or • SDA is sampled low when SCL goes Transmit Mode. from low to high. 6.2.2 CLOCK STRETCHING • SCL goes low before SDA is asserted low. This may indicate that another “Clock Stretching” is something that the receiving master is attempting to transmit a device can do, to allow additional time to “respond” to data"1". the “data” that has been received. The MCP4XXX will not strech the clock signal (SCL) since memory read acceses occur fast enough. SDA 1st Bit 6.2.3 ABORTING A TRANSMISSION If any part of the I2C transmission does not meet the command format, it is aborted. This can be intentionally accomplished with a START or STOP condition. This is SCL done so that noisy transmissions (usually an extra START or STOP condition) are aborted before they Sr = Repeated Start corrupt the device. FIGURE 6-5: Repeat Start Condition Waveform. SDA SCL S 1st Bit 2nd Bit 3rd Bit 4th Bit 5th Bit 6th Bit 7th Bit 8th Bit A / A P FIGURE 6-7: Typical 8-Bit I2C Waveform Format. SDA SCL START Data allowed Data or STOP Condition to change A valid Condition FIGURE 6-8: I2C Data States and Bit Sequence.  2008-2013 Microchip Technology Inc. DS22107B-page 49

MCP454X/456X/464X/466X 6.2.4 ADDRESSING Slave Address The address byte is the first byte received following the START condition from the master device. The address S A6 A5 A4 A3 A2 A1 A0 R/W A/A contains four (or more) fixed bits and (up to) three user “0”“1” “0”“1” defined hardware address bits (pins A2, A1, and A0). See Table6-2 These 7-bits address the desired I2C device. The Start R/W bit A7:A4 address bits are fixed to “0101” and the device bit R/W = 0 = write appends the value of following three address pins (A2, R/W = 1 = read A1, A0). Address pins that are not present on the A bit (controlled by slave device) device are pulled up (a bit value of ‘1’). A = 0 = Slave Device Acknowledges byte Since there are up to three adress bits controlled by A = 1 = Slave Device does not Acknowledge byte hardware pins, there may be up to eight MCP4XXX devices on the same I2C bus. FIGURE 6-9: Slave Address Bits in the I2C Control Byte. Figure6-9 shows the slave address byte format, which contains the seven address bits. There is also a read/ TABLE 6-2: DEVICE SLAVE ADDRESSES write bit. Table6-2 shows the fixed address for device. Device Address Comment MCP45X1 ‘0101 11’b + A0 Supports up to 2 Hardware Address Pins devices. Note1 The hardware address bits (A2, A1, and A0) MCP45X2 ‘0101 1’b + A1:A0 Supports up to 4 correspond to the logic level on the associated address devices. Note1 pins. This allows up to eight devices on the bus. MCP46X1 ‘0101’b + A2:A1:A0 Supports up to 8 These pins have a weak pull-up enabled when the V devices. Note1 DD < VBOR. The weak pull-up utilizes the “smart” pull-up MCP46X2 ‘0101 1’b + A1:A0 Supports up to 4 technology and exhibits the same characteristics as the devices. Note1 High-voltage tolerant I/O structure. Note 1: A0 is used for High-Voltage commands The state of the A0 address pin is latch on POR/BOR. and the value is latched at POR. This is required since High Voltage commands force 6.2.5 SLOPE CONTROL this pin (HVC/A0) to the V level. IHH The MCP45XX/46XX implements slope control on the SDA output. As the device transitions from HS mode to FS mode, the slope control parmameter will change from the HS specification to the FS specification. For Fast (FS) and High-Speed (HS) modes, the device has a spike suppression and a Schmidt trigger at SDA and SCL inputs. DS22107B-page 50  2008-2013 Microchip Technology Inc.

MCP454X/456X/464X/466X 6.2.6 HS MODE After switching to the High-Speed mode, the next The I2C specification requires that a high-speed mode transferred byte is the I2C control byte, which specifies the device to communicate with, and any number of device must be ‘activated’ to operate in high-speed data bytes plus acknowledgements. The Master (3.4Mbit/s) mode. This is done by the Master sending Device can then either issue a Repeated Start bit to a special address byte following the START bit. This address a different device (at High-Speed) or a Stop bit byte is referred to as the high-speed Master Mode to return to Fast/Standard bus speed. After the Stop bit, Code (HSMMC). any other Master Device (in a Multi-Master system) can The MCP45XX/46XX device does not acknowledge arbitrate for the I2C bus. this byte. However, upon receiving this command, the See Figure6-10 for an illustration of the HS mode com- device switches to HS mode. The device can now com- mand sequence. municate at up to 3.4Mbit/s on SDA and SCL lines. The device will switch out of the HS mode on the next For more information on the HS mode, or other I2C STOP condition. modes, please refer to the Phillips I2C specification. The master code is sent as follows: 6.2.6.1 Slope Control 1. START condition (S) The slope control on the SDA output is different 2. High-Speed Master Mode Code (0000 1XXX), between the Fast/Standard Speed and the High-Speed The XXX bits are unique to the high-speed (HS) Clock modes of the interface. mode Master. 3. No Acknowledge (A) 6.2.6.2 Pulse Gobbler The pulse gobbler on the SCL pin is automatically adjusted to suppress spikes < 10ns during HS mode. F/S-mode HS-mode P F/S-mode S ‘0 0 0 0 1 X X X’b A Sr‘Slave Address’R/W A “Data” A/A HS-mode continues Sr‘Slave Address’R/W A HS Select Byte Control Byte Command/Data Byte(s) S = Start bit Control Byte Sr = Repeated Start bit A = Acknowledge bit A = Not Acknowledge bit R/W = Read/Write bit P = Stop bit (Stop condition terminates HS Mode) FIGURE 6-10: HS Mode Sequence.  2008-2013 Microchip Technology Inc. DS22107B-page 51

MCP454X/456X/464X/466X 6.2.7 GENERAL CALL TABLE 6-3: GENERAL CALL COMMANDS The General Call is a method that the “Master” device 7-bit can communicate with all other “Slave” devices. In a Command Comment Multi-Master application, the other Master devices are (1, 2, 3) operating in Slave mode. The General Call address has two documented formats. These are shown in ‘1000 00d’b Write Next Byte (Third Byte) to Volatile Figure6-11. We have added a MCP45XX/46XX format Wiper 0 Register in this figure as well. ‘1001 00d’b Write Next Byte (Third Byte) to Volatile This will allow customers to have multiple I2C Digital Wiper 1 Register Potentiometers on the bus and have them operate in a ‘1100 00d’b Write Next Byte (Third Byte) to TCON synchronous fashion (analogous to the DAC Sync pin Register functionality). If these MCP45XX/46XX 7-bit com- ‘1000 010’b Increment Wiper 0 Register mands conflict with other I2C devices on the bus, then or the customer will need two I2C busses and ensure that ‘1000 011’b the devices are on the correct bus for their desired application functionality. ‘1001 010’b Increment Wiper 1 Register or Dual Pot devices can not update both Pot0 and Pot1 ‘1001 011’b from a single command. To address this, there are General Call commands for the Wiper 0, Wiper 1, and ‘1000 100’b Decrement Wiper 0 Register the TCON registers. or ‘1000 101’b Table6-3 shows the General Call Commands. Three commands are specified by the I2C specification and ‘1001 100’b Decrement Wiper 1 Register are not applicable to the MCP45XX/46XX (so com- or mand is Not Acknowledged) The MCP45XX/46XX ‘1001 101’b General Call Commands are Acknowledge. Any other Note 1: Any other code is Not Acknowledged. command is Not Acknowledged. These codes may be used by other devices on the I2C bus. Note: Only one General Call command per issue 2: The 7-bit command always appends a “0” of the General Call control byte. Any addi- to form 8-bits. . tional General Call commands are ignored 3: “d” is the D8 bit for the 9-bit write value. and Not Acknowledged. DS22107B-page 52  2008-2013 Microchip Technology Inc.

MCP454X/456X/464X/466X Second Byte S 0 0 0 0 0 0 0 0 A X X X X X X X 0 A P General Call Address “7-bit Command” Reserved 7-bit Commands (By I2C Specification - Philips # 9398 393 40011, Ver. 2.1 January 2000) ‘0000 011’b - Reset and write programmable part of slave address by hardware. ‘0000 010’b - Write programmable part of slave address by hardware. ‘0000 000’b - NOT Allowed MCP45XX/MCP46XX 7-bit Commands ‘1000 01x’b - Increment Wiper 0 Register. ‘1001 01x’b - Increment Wiper 1 Register. ‘1000 10x’b - Decrement Wiper 0 Register. ‘1001 10x’b - Decrement Wiper 1 Register. The Following is a Microchip Extension to this General Call Format Second Byte Third Byte S 0 0 0 0 0 0 0 0 A X X X X X X d 0 A d d d d d d d d A P General Call Address “7-bit Command” “0” for General Call Command MCP45XX/MCP46XX 7-bit Commands ‘1000 00d’b - Write Next Byte (Third Byte) to Volatile Wiper 0 Register. ‘1001 00d’b - Write Next Byte (Third Byte) to Volatile Wiper 1 Register. ‘1100 00d’b - Write Next Byte (Third Byte) to TCON Register. The Following is a “Hardware General Call” Format Second Byte n occurrences of (Data + A) S 0 0 0 0 0 0 0 0 A X X X X X X X 1 A X X X X X X X X A P General Call Address “7-bit Command” This indicates a “Hardware General Call” MCP45XX/MCP46XX will ignore this byte and all following bytes (and A), until a Stop bit (P) is encountered. FIGURE 6-11: General Call Formats.  2008-2013 Microchip Technology Inc. DS22107B-page 53

MCP454X/456X/464X/466X NOTES: DS22107B-page 54  2008-2013 Microchip Technology Inc.

MCP454X/456X/464X/466X 7.0 DEVICE COMMANDS Normal serial commands are those where the HVC pin is driven to V or V . With High-Voltage Serial Com- IH IL The MCP4XXX’s I2C command formats are specified in mands, the HVC pin is driven to V . In each mode, IHH this section. The I2C protocol does not specify how there are four possible commands. commands are formatted. Additionally, there are two commands used to enable The MCP4XXX supports four basic commands. or disable the special features (Write Protect and Wiper Depending on the location accessed, this determines Lock Technology) of the device. The commands are the commands that are supported. special cases of the Increment and Decrement For the Volatile Wiper Registers, these commands are: High-Voltage Serial Command. • Write Data Table7-2 shows the supported commands for each • Read Data memory location. • Increment Data Table7-3 shows an overview of all the device com- • Decrement Data mands and their interaction with other device features. For the Nonvolatile wiper EEPROM, general purpose data EEPROM, and the TCON Register these com- 7.1 Command Byte mands are: The MCP4XXX’s Command Byte has three fields: the • Write Data Address, the Command Operation, and 2 Data bits, • Read Data see Figure7-1. Currently only one of the data bits is These commands have formats for both a single defined (D8). command or continuous commands. These commands The device memory is accessed when the Master are shown in Table7-1. sends a proper Command Byte to select the desired Each command has two operational states. The operation. The memory location getting accessed is operational state determines if the device commands contained in the Command Byte’s AD3:AD0 bits. The control the special features (Write Protect and Wiper- action desired is contained in the Command Byte’s Lock Technology). These operational states are C1:C0 bits, see Table7-1. C1:C0 determines if the referred to as: desired memory location will be read, written, Incremented (wiper setting +1) or Decremented (wiper • Normal Serial Commands setting -1). The Increment and Decrement commands • High-Voltage Serial Commands are only valid on the volatile wiper registers, and in High Voltage commands to enable/disable WiperLock TABLE 7-1: I2C COMMANDS Technology and Software Write Protect. Command Operates on If the Address bits and Command bits are not a valid # of Bit Volatile/ combination, then the MCP4XXX will generate a Not Operation Mode Clocks (1) Nonvolatile Acknowledge pulse to indicate the invalid combination. memory The I2C Master device must then force a Start Condi- Write Data Single 29 Both tion to reset the MCP4XXX’s 2C module. Continuous 18n + 11 Volatile Only D9 and D8 are the most significant bits for the digital Read Data Single 29 Both potentiometer’s wiper setting. The 8-bit devices utilize Random 48 Both D8 as their MSb while the 7-bit devices utilize D7 (from Continuous 18n + 11 Both (2) the data byte) as it’s MSb. Increment Single 20 Volatile Only (3) Continuous 9n + 11 Volatile Only COMMAND BYTE Decrement Single 20 Volatile Only (3) Continuous 9n + 11 Volatile Only A A A A A C C D D A D D D D 1 0 9 8 Note 1: “n” indicates the number of times the 3 2 1 0 command operation is to be repeated. 2: This command is useful to determine if a MCP4XXX MSbits (Data) nonvolatile memory write cycle has Memory Address completed. Command Operation bits 3: High Voltage Increment and Decrement 00 = Write Data commands on select nonvolatile memory 01 = Increment locations enable/disable WiperLock 10 = Decrement Technology and the software Write 11 = Read Data Protect feature. FIGURE 7-1: Command Byte Format.  2008-2013 Microchip Technology Inc. DS22107B-page 55

MCP454X/456X/464X/466X TABLE 7-2: MEMORY MAP AND THE SUPPORTED COMMANDS Address Data Command Operation Comment (10-bits) (1) Value Function 00h Volatile Wiper 0 Write Data nn nnnn nnnn Read Data (3) nn nnnn nnnn Increment Wiper — Decrement Wiper — 01h Volatile Wiper 1 Write Data nn nnnn nnnn Read Data (3) nn nnnn nnnn Increment Wiper — Decrement Wiper — 02h Non Volatile Wiper 0 Write Data nn nnnn nnnn Read Data (3) nn nnnn nnnn High Voltage Increment — Wiper Lock 0 Disable High Voltage Decrement — Wiper Lock 0 Enable 03h Non Volatile Wiper 1 Write Data nn nnnn nnnn Read Data (3) nn nnnn nnnn High Voltage Increment — Wiper Lock 1 Disable High Voltage Decrement — Wiper Lock 1 Enable 04h (2) Volatile TCON Register Write Data nn nnnn nnnn Read Data (3) nn nnnn nnnn 05h (2) Status Register Read Data (3) nn nnnn nnnn 06h (2) Data EEPROM Write Data nn nnnn nnnn Read Data (3) nn nnnn nnnn 07h (2) Data EEPROM Write Data nn nnnn nnnn Read Data (3) nn nnnn nnnn 08h (2) Data EEPROM Write Data nn nnnn nnnn Read Data (3) nn nnnn nnnn 09h (2) Data EEPROM Write Data nn nnnn nnnn Read Data (3) nn nnnn nnnn 0Ah (2) Data EEPROM Write Data nn nnnn nnnn Read Data (3) nn nnnn nnnn 0Bh (2) Data EEPROM Write Data nn nnnn nnnn Read Data (3) nn nnnn nnnn 0Ch (2) Data EEPROM Write Data nn nnnn nnnn Read Data (3) nn nnnn nnnn 0Dh (2) Data EEPROM Write Data nn nnnn nnnn Read Data (3) nn nnnn nnnn 0Eh (2) Data EEPROM Write Data nn nnnn nnnn Read Data (3) nn nnnn nnnn 0Fh Data EEPROM Write Data nn nnnn nnnn Read Data (3) nn nnnn nnnn High Voltage Increment — Write Protect Disable High Voltage Decrement — Write Protect Enable Note 1: The Data Memory is only 9-bits wide, so the MSb is ignored by the device. 2: Increment or Decrement commands are invalid for these addresses. 3: I2C read operation will read 2 bytes, of which the 10-bits of data are contained within. DS22107B-page 56  2008-2013 Microchip Technology Inc.

MCP454X/456X/464X/466X 7.2 Data Byte 7.3 Error Condition Only the Read Command and the Write Command If the four address bits received (AD3:AD0) and the two have Data Byte(s). command bits received (C1:C0) are a valid combina- tion, the MCP4XXX will Acknowledge the I2C bus. The Write command concatenates the 8-bits of the Data Byte with the one data bit (D8) contained in the If the address bits and command bits are an invalid Command Byte to form 9-bits of data (D8:D0). The combination, then the MCP4XXX will Not Acknowledge Command Byte format supports up to 9-bits of data so the I2C bus. that the 8-bit resistor network can be set to Full-Scale Once an error condition has occurred, any following (100h or greater). This allows wiper connections to commands are ignored until the I2C bus is reset with a Terminal A and to TerminalB. The D9 bit is currently Start Condition. unused. 7.3.1 ABORTING A TRANSMISSION A Restart or Stop condition in the expected data bit position will abort the current command sequence and data will not be written to the MCP4XXX. TABLE 7-3: COMMANDS Operates on High Works Writes Impact on Volatile/ Voltage when Command Name Value in WiperLock or Nonvolatile (V ) on Wiper is EEPROM IHH Write Protect memory HVC pin? “locked”? Write Data Yes (1) Both — unlocked (1) No Read Data — Both — unlocked (1) No Increment Wiper — Volatile Only — unlocked (1) No Decrement Wiper — Volatile Only — unlocked (1) No High Voltage Write Data Yes Both Yes unchanged No High Voltage Read Data — Both Yes unchanged Yes High Voltage Increment Wiper — Volatile Only Yes unchanged No High Voltage Decrement Wiper — Volatile Only Yes unchanged No Modify Write Protect or WiperLock — (2) Nonvolatile Only Yes locked/ Yes Technology (High Voltage) - Enable (2) protected(2) Modify Write Protect or WiperLock — (3) Nonvolatile Only Yes unlocked/ Yes Technology (High Voltage) - Disable (3) unprotected(3) Note 1: This command will only complete, if wiper is “unlocked” (WiperLock Technology is Disabled). 2: If the command is executed using address 02h or 03h, that corresponding wiper is locked or if with address 0Fh, then Write Protect is enabled. 3: If the command is executed using with address 02h or 03h, that corresponding wiper is unlocked or if with address 0Fh, then Write Protect is disabled.  2008-2013 Microchip Technology Inc. DS22107B-page 57

MCP454X/456X/464X/466X 7.4 Write Data 7.4.3 CONTINUOUS WRITES TO Normal and High Voltage VOLATILE MEMORY A continuous write mode of operation is possible when The Write Command can be issued to both the Volatile writing to the volatile memory registers (address 00h, and Nonvolatile memory locations. The format of the command, see Figure7-2, includes the I2C Control 01h, and 04h). This continuous write mode allows writes without a Stop or Restart condition or repeated Byte, an A bit, the MCP4XXX Command Byte, an A bit, transmissions of the I2C Control Byte. Figure7-3 the MCP4XXX Data Byte, an A bit, and a Stop (or shows the sequence for three continuous writes. The Restart) condition. The MCP4XXX generates the A/A writes do not need to be to the same volatile memory bits. address. The sequence ends with the master sending A Write command to a Volatile memory location a STOP or RESTART condition. changes that location after a properly formatted Write Command and the A/A clock have been received. 7.4.4 CONTINUOUS WRITES TO A Write command to a Nonvolatile memory location will NONVOLATILE MEMORY only start a write cycle after a properly formatted Write If a continuous write is attempted on Nonvolatile Command have been received and the Stop condition memory, the missing Stop condition will cause the com- has occurred. mand to be an error condition (A). A Start bit is required to reset the command state machine. Note: Writes to certain memory locations will be dependant on the state of the WiperLock 7.4.5 THE HIGH VOLTAGE COMMAND Technology bits and the Write Protect bit. (HVC) SIGNAL 7.4.1 SINGLE WRITE TO VOLATILE The High Voltage Command (HVC) signal is MEMORY multiplexed with Address 0 (A0) and is used to indicate that the command, or sequence of commands, are in For volatile memory locations, data is written to the the High Voltage operational state. High Voltage MCP4XXX after every byte transfer (during the commands allow the device’s WiperLock Technology Acknowledge). If a Stop or Restart condition is gener- and write protect features to be enabled and disabled. ated during a data transfer (before the A), the data will not be written to the MCP4XXX. After the A bit, the The HVC pin has an internal resistor connection to the master can initiate the next sequence with a Stop or MCP45XX/46XXs internal VDD signal. Restart condition. Refer to Figure7-2 for the byte write sequence. 7.4.2 SINGLE WRITE TO NONVOLATILE MEMORY The sequence to write to a single nonvolatile memory location is the same as a single write to volatile memory with the exception that the EEPROM write cycle (t ) is wc started after a properly formatted command, including the Stop bit, is received. After the Stop condition occurs, the serial interface may immediately be re-enabled by initiating a Start condition. During an EEPROM write cycle, access to volatile memory (addresses 00h, 01h, 04h, and 05h) is allowed when using the appropriate command sequence. Commands that address nonvolatile memory are ignored until the EEPROM write cycle (t ) completes. wc This allows the Host Controller to operate on the Volatile Wiper registers, the TCON register, and to Read the Status Register. The EEWA bit in the Status register indicates the status of an EEPROM Write Cycle. Once a write command to a Nonvolatile memory location has been received, no other commands should be received before the Stop condition occurs. Figure7-2 show the waveform for a single write. DS22107B-page 58  2008-2013 Microchip Technology Inc.

MCP454X/456X/464X/466X Write bit Device Fixed Variable Memory Address Address Address Command Write “Data” bits ADADADAD S 0 1 0 1 A2 A1 A0 0 A 3 2 1 0 0 0 x D8 A D7 D6D5 D4 D3 D2 D1D0 A P Control Byte WRITE Command Write Data bits FIGURE 7-2: I2C Write Sequence. Write bit Device Fixed Variable Memory Address Address Address Command Write “Data” bits ADADADAD S 0 1 0 1 A2 A1 A0 0 A 0 0 x D8 AD7 D6D5 D4 D3 D2 D1D0 A 3 2 1 0 Control Byte WRITE Command Write Data bits ADADADAD 0 0 x D8 A D7D6 D5 D4 D3 D2D1D0 A 3 2 1 0 WRITE Command Write Data bits STOP bit ADADADAD 0 0 x D8 A D7 D6D5 D4 D3 D2 D1D0 A P 3 2 1 0 WRITE Command Write Data bits Note: Only functions when writing the volatile wiper registers (AD3:AD0 = 00h, 01h, and 04h) or the TCON register FIGURE 7-3: I2C Continuous Volatile Wiper Write.  2008-2013 Microchip Technology Inc. DS22107B-page 59

MCP454X/456X/464X/466X 7.5 Read Data 7.5.2 CONTINUOUS READS Normal and High Voltage Continuous reads allows the device’s memory to be read quickly. Continuous reads are possible to all mem- The Read Command can be issued to both the Volatile ory locations. If a nonvolatile memory write cycle is and Nonvolatile memory locations. The format of the occurring, then Read commands may only access the command, see Figure7-4, includes the Start condition, I2C Control Byte (with R/W bit set to “0”), A bit, volatile memory locations. MCP4XXX Command Byte, A bit, followed by a Figure7-6 shows the sequence for three continuous Repeated Start bit, I2C Control Byte (with R/W bit set to reads. “1”), and the MCP4XXX transmitting the requested For continuous reads, instead of transmitting a Stop Data High Byte, and A bit, the Data Low Byte, the Mas- or Restart condition after the data transfer, the master ter generating the A, and Stop condition. reads the next data byte. The sequence ends with the The I2C Control Byte requires the R/W bit equal to a master Not Acknowledging and then sending a Stop or logic one (R/W = 1) to generate a read sequence. The Restart. memory location read will be the last address 7.5.3 THE HIGH VOLTAGE COMMAND contained in a valid write MCP4XXX Command Byte or address 00h if no write operations have occurred since (HVC) SIGNAL the device was reset (Power-on Reset or Brown-out The High Voltage Command (HVC) signal is Reset). multiplexed with Address 0 (A0) and is used to indicate During a write cycle (Write or High Voltage Write to a that the command, or sequence of commands, are in Nonvolatile memory location) the Read command can the High Voltage mode. High Voltage commands allow only read the Volatile memory locations. By reading the the device’s WiperLock Technology and write protect Status Register (04h), the Host Controller can features to be enabled and disabled. determine when the write cycle has completed (via the The HVC pin has an internal resistor connection to the state of the EEWA bit). MCP4XXXs internal V signal. DD Read operations initially include the same address byte 7.5.4 IGNORING AN I2C TRANSMISSION AND sequence as the write sequence (shown in Figure6-9). “FALLING OFF” THE BUS This sequence is followed by another control byte (including the Start condition and Ackowledge) with the The MCP4XXX expects to receive entire, valid I2C R/W bit equal to a logic one (R/W = 1) to indicate a commands and will assume any command not defined read. The MCP4XXX will then transmit the data con- as a valid command is due to a bus corruption and will tained in the addressed register. This is followed by the enter a passive high condition on the SDA signal. All master generating an A bit in preparation for more data, signals will be ignored until the next valid Start or an A bit followed by a Stop. The sequence is ended condition and Control Byte are received. with the master generating a Stop or Restart condition. The internal address pointer is maintained. If this address pointer is for a nonvolatile memory address and the read control byte addresses the device during a Nonvolatile Write Cycle (t ) the device will respond WC with an A bit. 7.5.1 SINGLE READ Figure7-4 show the waveforms for a single read. For single reads the master sends a STOP or RESTART condition after the data byte is sent from the slave. 7.5.1.1 Random Read Figure7-5 shows the sequence for a Random Reads. Refer to Figure7-5 for the random byte read sequence. DS22107B-page 60  2008-2013 Microchip Technology Inc.

MCP454X/456X/464X/466X Read bit STOP bit Fixed Variable Address Address Read Data bits S 0 1 0 1 A2 A1 A0 1 A 0 0 0 0 0 0 0 D8 A1D7 D6 D5 D4D3 D2 D1D0 A2 P Control Byte Read bits Note1: Master Device is responsible for A / A signal. If a A signal occurs, the MCP45XX/46XX will abort this transfer and release the bus. 2: The Master Device will Not Acknowledge, and the MCP45XX/46XX will release the bus so the Master Device can generate a Stop or Repeated Start condition. 3: The MCP45xx/46xx retains the last “Device Memory Address” that it has received. This is the MCP45XX/46XX does not “corrupt” the “Device Memory Address” after Repeated Start or Stop conditions. 4: The Device Memory Address pointer defaults to 00h on POR and BOR conditions. FIGURE 7-4: I2C Read (Last Memory Address Accessed). Write bit Repeated Start bit Device Fixed Variable Memory Address Address Address Command ADADADAD S 0 1 0 1 A2 A1 A0 0 A 1 1 x X A Sr 3 2 1 0 Control Byte READ Command STOP bit Read bit Read Data bits 0 1 0 1 A2 A1 A0 1 A 0 0 0 0 0 0 0 D8 A1 D7 D6D5 D4 D3 D2 D1D0 A2 P Control Byte Read bits Note1: Master Device is responsible for A / A signal. If a A signal occurs, the MCP45XX/46XX will abort this transfer and release the bus. 2: The Master Device will Not Acknowledge, and the MCP45XX/46XX will release the bus so the Master Device can generate a Stop or Repeated Start condition. 3: The MCP45XX/46XX retains the last “Device Memory Address” that it has received. This is the MCP45XX/46XX does not “corrupt” the “Device Memory Address” after Repeated Start or Stop conditions. FIGURE 7-5: I2C Random Read.  2008-2013 Microchip Technology Inc. DS22107B-page 61

MCP454X/456X/464X/466X Read bit Fixed Variable Address Address Read Data bits S 0 1 0 1 A2 A1 A0 1 A 0 0 0 0 0 0 0 D8 A1D7D6 D5 D4 D3 D2D1D0 A1 Control Byte Read bits Read Data bits 0 0 0 0 0 0 0 D8 A1D7D6 D5 D4 D3 D2D1D0 A1 STOP bit Read Data bits 0 0 0 0 0 0 0 D8 A1 D7 D6 D5 D4D3 D2 D1D0 A2 P Note1: Master Device is responsible for A / A signal. If a A signal occurs, the MCP45XX/46XX will abort this transfer and release the bus. 2: The Master Device will Not Acknowledge, and the MCP45XX/46XX will release the bus so the Master Device can generate a Stop or Repeated Start condition. FIGURE 7-6: I2C Continuous Reads. DS22107B-page 62  2008-2013 Microchip Technology Inc.

MCP454X/456X/464X/466X 7.6 Increment Wiper The advantage of using an Increment Command Normal and High Voltage instead of a read-modify-write series of commands is speed and simplicity. The wiper will transition after each The Increment Command provide a quick and easy Command Acknowledge when accessing the volatile method to modify the potentiometer’s wiper by +1 with wiper registers. minimal overhead. The Increment Command will only function on the volatile wiper setting memory locations TABLE 7-4: INCREMENT OPERATION VS. 00h and 01h. The Increment Command to Nonvolatile VOLATILE WIPER VALUE addresses will be ignored and will generate a A. Current Wiper Note: Table7-2 shows the valid addresses for Setting Wiper (W) Increment Command the Increment Wiper command. Other Properties 7-bit 8-bit Operates? addresses are invalid. Pot Pot When executing an Increment Command, the volatile 3FFh 3FFh Reserved No wiper setting will be altered from n to n+1 for each 081h 101h (Full-Scale (W = A)) Increment Command received. The value will incre- ment up to 100h max on 8-bit devices and 80h on 7-bit 080h 100h Full-Scale (W = A) No devices. If multiple Increment Commands are received 07Fh 0FFh W = N after the value has reached 100h (or 80h), the value will 041h 081 not be incremented further. Table7-4 shows the 040h 080h W = N (Mid-Scale) Yes Increment Command versus the current volatile wiper 03Fh 07Fh W = N value. 001h 001 The Increment Command will most commonly be 000h 000h Zero Scale (W = B) Yes performed on the Volatile Wiper locations until a desired condition is met. The value in the Volatile Wiper register would need to be read using a Read operation in order to write the new setting to the corresponding 7.6.1 THE HIGH VOLTAGE COMMAND Nonvolatile wiper memory using a Write operation. The (HVC) SIGNAL MCP4XXX is responsible for generating the A bits. The High Voltage Command (HVC) signal is multi- Refer to Figure7-7 for the Increment Command plexed with Address 0 (A0) and is used to indicate that sequence. The sequence is terminated by the Stop the command, or sequence of commands, are in the condition. So when executing a continuous command High Voltage mode. Signals > V (~8.5V) on the IHH string, the Increment command can be followed by any HVC/A0 pin puts MCP45XX/46XX devices into High other valid command. This means that writes do not Voltage mode. High Voltage commands allow the need to be to the same volatile memory address. device’s WiperLock Technology and write protect features to be enabled and disabled. Note: The command sequence can go from an Note: There is a required delay after the HVC pin increment to any other valid command for is driven to the V level to the 1st edge the specified address. Issuing an incre- IHH of the SCL pin. ment or decrement to a nonvolatile loca- tion will cause an error condition (A will be The HVC pin has an internal resistor connection to the generated). MCP45XX/46XXs internal V signal. DD Write bit Device Fixed Variable Memory Address Address Address Command ADADADAD ADADADAD S 0 1 0 1 A2 A1 A0 0 A 3 2 1 0 0 1 x X A 4 3 2 1 0 1 x X A P (2) Control Byte INCR Command (n+1) INCR Command (n+2) Note1: Increment Command (INCR) only functions when accessing the volatile wiper reg- isters (AD3:AD0 = 0h and 1h). 2: This command sequence does not need to terminate (using the Stop bit) and can change to any other desired command sequence (Increment, Read, or Write). FIGURE 7-7: I2C Increment Command Sequence.  2008-2013 Microchip Technology Inc. DS22107B-page 63

MCP454X/456X/464X/466X 7.7 Decrement Wiper The advantage of using an Decrement Command Normal and High Voltage instead of a read-modify-write series of commands is speed and simplicity. The wiper will transition after each The Decrement Command provide a quick and easy Command Acknowledge when accessing the volatile method to modify the potentiometer’s wiper by -1 with wiper registers. minimal overhead. The Decrement Command will only function on the volatile wiper setting memory locations TABLE 7-5: DECREMENT OPERATION VS. 00h and 01h. Decrement Commands to Nonvolatile VOLATILE WIPER VALUE addresses will be ignored and will generate an A bit. Current Wiper Note: Table7-2 shows the valid addresses for Setting Wiper (W) Decrement Command the Decrement Wiper command. Other Properties 7-bit 8-bit Operates? addresses are invalid. Pot Pot When executing a Decrement Command, the volatile 3FFh 3FFh Reserved No wiper setting will be altered from n to n-1 for each 081h 101h (Full-Scale (W = A)) Decrement Command received. The value will decrement down to 000h min. If multiple Decrement 080h 100h Full-Scale (W = A) Yes Commands are received after the value has reached 07Fh 0FFh W = N 000h, the value will not be decremented further. 041h 081 Table7-5 shows the Increment Command versus the 040h 080h W = N (Mid-Scale) Yes current volatile wiper value. 03Fh 07Fh W = N The Decrement Command will most commonly be 001h 001 performed on the Volatile Wiper locations until a 000h 000h Zero Scale (W = B) No desired condition is met. The value in the Volatile Wiper register would need to be read using a Read operation in order to write the new setting to the corresponding Nonvolatile wiper memory using a Write operation. The 7.7.1 THE HIGH VOLTAGE COMMAND MCP4XXX is responsible for generating the A bits. (HVC) SIGNAL Refer to Figure7-8 for the Decrement Command The High Voltage Command (HVC) signal is sequence. The sequence is terminated by the Stop multiplexed with Address 0 (A0) and is used to indicate condition. So when executing a continuous command that the command, or sequence of commands, are in string, the Increment command can be followed by any the High Voltage mode. Signals > V (~8.5V) on the IHH other valid command. This means that writes do not HVC/A0 pin puts MCP45XX/46XX devices into High need to be to the same volatile memory address. Voltage mode. High Voltage commands allow the device’s WiperLock Technology and write protect Note: The command sequence can go from an features to be enabled and disabled. increment to any other valid command for the specified address. Issuing an Note: There is a required delay after the HVC pin increment or decrement to a nonvolatile is driven to the V level to the 1st edge IHH location will cause an error condition (A of the SCL pin. will be generated). The HVC pin has an internal resistor connection to the MCP45XX/46XXs internal V signal. DD Write bit Device Fixed Variable Memory Address Address Address Command ADADADAD ADADADAD S 0 1 0 1 A2 A1 A0 0 A 1 0 X X A 1 0 X X A P (2) 3 2 1 0 4 3 2 1 Control Byte DECR Command (n-1) DECR Command (n-2) Note1: Decrement Command (DECR) only functions when accessing the volatile wiper registers (AD3:AD0 = 0h and 1h). 2: This command sequence does not need to terminate (using the Stop bit) and can change to any other desired command sequence (INCR, Read, or Write). FIGURE 7-8: I2C Decrement Command Sequence. DS22107B-page 64  2008-2013 Microchip Technology Inc.

MCP454X/456X/464X/466X 7.8 Modify Write Protect or WiperLock 7.8.1 SINGLE MODIFY (ENABLE OR Technology (High Voltage) DISABLE) WRITE PROTECT OR Enable and Disable WIPERLOCK TECHNOLOGY (HIGH VOLTAGE) These commands are special cases of the High Volt- Figure7-9 (Disable) and Figure7-10 (Enable) show age Decrement Wiper and the High Voltage Incre- the formats for a single Modify Write Protect or Wiper- ment Wiper commands to the nonvolatile memory Lock Technology command. locations 02h, 03h, and 0Fh. This command is used to enable or disable either the software Write Protect, A Modify Write Protect or WiperLock Technology wiper 0 WiperLock Technology, or wiper 1 WiperLock Command will only start an EEPROM write cycle (t ) wc Technology. Table7-6 shows the memory addresses, after a properly formatted Command has been the High Voltage command and the result of those received and the Stop condition occurs. commands on the nonvolatile WP, WL0, 0r WL1 bits. During an EEPROM write cycle, only serial commands to Volatile memory (addresses 00h, 01h, 04h, and 05h) are accepted. All other serial commands are ignored until the EEPROM write cycle (t ) completes. This wc allows the Host Controller to operate on the Volatile Wiper registers and the TCON register, and to Read the Status Register. The EEWA bit in the Status register indicates the status of an EEPROM Write Cycle. TABLE 7-6: ADDRESS MAP TO MODIFY WRITE PROTECT AND WIPERLOCK TECHNOLOGY Commands and Result Memory Address High Voltage Decrement Wiper High Voltage Increment Wiper 00h Wiper 0 register is incremented Wiper 0 register is incremented 01h Wiper 1 register is decremented Wiper 1 register is incremented 02h WL0 is enabled WL0 is disabled 03h WL1 is enabled WL1 is disabled 04h (1) TCON register not changed TCON register not changed 05h - 0Eh (1) Reserved Reserved 0Fh WP is enabled WP is disabled Note 1: Reserved addresses: Increment or Decrement commands are invalid for these addresses. Write bit Device Fixed Variable Memory Address Address Address Command (Increment) ADADADAD S 0 1 0 1 A2 A1 A0 0 A 0 1 X X A P 3 2 1 0 Control Byte Disable Command FIGURE 7-9: I2C Disable Command Sequence. Write bit Device Fixed Variable Memory Address Address Address Command (Decrement) ADADADAD S 0 1 0 1 A2 A1 A0 0 A 1 0 X X A P 3 2 1 0 Control Byte Enable Command FIGURE 7-10: I2C Enable Command Sequence.  2008-2013 Microchip Technology Inc. DS22107B-page 65

MCP454X/456X/464X/466X NOTES: DS22107B-page 66  2008-2013 Microchip Technology Inc.

MCP454X/456X/464X/466X 8.0 APPLICATIONS EXAMPLES 8.2 Software Reset Sequence Nonvolatile digital potentiometers have a multitude of Note: This technique is documented in AN1028. practical uses in modern electronic circuits. The most At times it may become necessary to perform a Soft- popular uses include precision calibration of set point ware Reset Sequence to ensure the MCP45XX/46XX thresholds, sensor trimming, LCD bias trimming, audio device is in a correct and known I2C Interface state. attenuation, adjustable power supplies, motor control This technique only resets the I2C state machine. overcurrent trip setting, adjustable gain amplifiers and This is useful if the MCP45XX/46XX device powers up offset trimming. The MCP454X/456X/464X/466X in an incorrect state (due to excessive bus noise, ...), or devices can be used to replace the common mechani- if the Master Device is reset during communication. cal trim pot in applications where the operating and Figure8-2 shows the communication sequence to soft- terminal voltages are within CMOS process limitations ware reset the device. (V = 2.7V to 5.5V). DD 8.1 Using Shutdown S ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ S P Figure8-1 shows a possible application circuit where Nine bits of ‘1’ the independent terminals could be used. Disconnect- ing the wiper allows the transistor input to be taken to Start bit Start bit Stop bit the Bias voltage level (disconnecting A and or B may be desired to reduce system current). Disconnecting Ter- FIGURE 8-2: Software Reset Sequence minal A modifies the transistor input by the R rheo- Format. BW stat value to the Common B. Disconnecting Terminal B The 1st Start bit will cause the device to reset from a modifies the transistor input by the R rheostat value AW state in which it is expecting to receive data from the to the Common A. The Common A and Common B Master Device. In this mode, the device is monitoring connections could be connected to V and V . DD SS the data bus in Receive mode and can detect the Start bit forces an internal Reset. The nine bits of ‘1’ are used to force a Reset of those devices that could not be reset by the previous Start bit. Common A This occurs only if the MCP45XX/46XX is driving an A bit on the I2C bus, or is in output mode (from a Read command) and is driving a data bit of ‘0’ onto the I2C Input bus. In both of these cases, the previous Start bit could A not be generated due to the MCP45XX/46XX holding the bus low. By sending out nine ‘1’ bits, it is ensured that the device will see a A bit (the Master Device does not drive the I2C bus low to acknowledge the data sent by the MCP45XX/46XX), which also forces the To base MCP45XX/46XX to reset. W of Transistor The 2nd Start bit is sent to address the rare possibility (or Amplifier) of an erroneous write. This could occur if the Master Device was reset while sending a Write command to the MCP45XX/46XX, AND then as the Master Device returns to normal operation and issues a Start condition while the MCP45XX/46XX is issuing an Acknowledge. B In this case, if the 2nd Start bit is not sent (and the Stop Input bit was sent) the MCP45XX/46XX could initiate a write cycle. Note: The potential for this erroneous write Common B ONLY occurs if the Master Device is reset while sending a Write command to the Balance Bias MCP45XX/46XX. FIGURE 8-1: Example Application Circuit The Stop bit terminates the current I2C bus activity. The using Terminal Disconnects. MCP45XX/46XX wait to detect the next Start condition. This sequence does not effect any other I2C devices which may be on the bus, as they should disregard this as an invalid command.  2008-2013 Microchip Technology Inc. DS22107B-page 67

MCP454X/456X/464X/466X 8.3 Using the General Call Command Figure8-3 shows two I2C bus configurations. In many cases, the single I2C bus configuration will be The use of the General Call Address Increment, Decre- adequate. For applications that do not want all the ment, or Write commands is analogous to the “Load” MCP45XX/46XX devices to do General Call support, or feature (LDAC pin) on some DACs (such as the have a conflict with General Call commands, the MCP4921). This allows all the devices to “Update” the multiple I2C bus configuration would be used. output level “at the same time”. For some applications, the ability to update the wiper Single I2C Bus Configuration values “at the same time” may be a requirement, since the delay from writing to one wiper value and then the next may cause application issues. A possible example Device 1 Device 3 Device n would be a “tuned” circuit that uses several MCP45XX/ Host 46XX in rheostat configuration. As the system condition Controller changes (temperature, load, ...) these devices need to Device 2 Device 4 be changed (incremented/decremented) to adjust for the system change. These changes will either be in the same direction or in opposite directions. With the Multiple I2C Bus Configuration Potentiometer device, the customer can either select the PxB terminals (same direction) or the PxA Device 1a Device 3a Device na terminal(s) (opposite direction). Host Bus a Figure8-4 shows that the update of six devices takes Controller 6*T time in “normal” operation, but only I2CDLY Device 2a Device 4a 1*T time in “General Call” operation. I2CDLY Note: The application system may need to Device 1b Device 3b Device nb partition the I2C bus into multiple busses to Bus b ensure that the MCP45XX/46XX General Call commands do not conflict with the General Call commands that the other I2C Device 2b Device 4b devices may have defined. Also, if only a portion of the MCP45XX/46XX devices are Device 1n Device 3n Device nn to require this synchronous operation, Bus n then the devices that should not receive these commands should be on the second I2C bus. Device 2n Device 4n FIGURE 8-3: Typical Application I2C Bus Configurations. Normal Operation INC INC INC INC INC INC POT01 POT02 POT03 POT04 POT05 POT06 T T T T T T I2CDLY I2CDLY I2CDLY I2CDLY I2CDLY I2CDLY General Call Operation INC INC INC INC INC INC POTs 01-06 POTs 01-06 POTs 01-06 POTs 01-06 POTs 01-06 POTs 01-06 T T T T T T I2CDLY I2CDLY I2CDLY I2CDLY I2CDLY I2CDLY T = Time from one I2C command completed to completing the next I2C command. I2CDLY FIGURE 8-4: Example Comparison of “Normal Operation” vs. “General Call Operation” wiper Updates. DS22107B-page 68  2008-2013 Microchip Technology Inc.

MCP454X/456X/464X/466X 8.4 Implementing Log Steps with a EQUATION 8-1: dB CALCULATIONS Linear Digital Potentiometer (VOLTAGE) In audio volume control applications, the use of L = 20 * log10 (VOUT / VIN) logarithmic steps is desirable, since the human ear hears in a logarithmic manner. The use of a linear dB V / V Ratio potentiometer can approximate a log potentiometer, OUT IN but with fewer steps. An 8-bit potentiometer can -3 0.70795 achieve fourteen 3dB log steps plus a 100% (0dB) -2 0.79433 and a mute setting. -1 0.89125 Figure8-5 shows a block diagram of one of the MCP45x1 resistor networks being used to attenuate an input signal. In this case, the attenuation will be ground EQUATION 8-2: dB CALCULATIONS referenced. Terminal B can be connected to a common (RESISTANCE) - CASE 1 mode voltage, but the voltages on the A, B and Wiper Terminal B connected to Ground (see Figure8-5) terminals must not exceed the MCP45x1’s V /V DD SS voltage limits. L = 20 * log (R / R ) 10 BW AB MCP45X1 EQUATION 8-3: dB CALCULATIONS (RESISTANCE) - CASE 2 P0A Terminal B through R to Ground B2GND P0W L = 20 * log ( (R + R ) / (R + R ) ) 10 BW B2GND AB B2GND P0B Table8-1 shows the codes that can be used for 8-bit digital potentiometers to implement the log attenuation. The table shows the wiper codes for -3dB, -2dB, and FIGURE 8-5: Signal Attenuation Block -1dB attenuation steps. This table also shows the Diagram - Ground Referenced. calculated attenuation based on the wiper code’s linear step. Calculated attenuation values less than the Equation8-1 shows the equation to calculate voltage desired attenuation are shown with red text. At lower dB gain ratios for the digital potentiometer, while wiper code values, the attenuation may skip a step, if Equation8-2 shows the equation to calculate this occurs the next attenuation value is colored resistance dB gain ratios. These two equations assume magenta to highlight that a skip occurred. For example, that the B terminal is connected to ground. in the -3dB column the -48dB value is highlighted If terminal B is not directly resistively connected to since the -45dB step could not be implemented (there ground, then this terminal B to ground resistance are no wiper codes between 2 and 1). (R ) must be included into the calculation. B2GND Equation8-3 shows this equation.  2008-2013 Microchip Technology Inc. DS22107B-page 69

MCP454X/456X/464X/466X TABLE 8-1: LINEAR TO LOG ATTENUATION FOR 8-BIT DIGITAL POTENTIOMETERS -3dB Steps -2dB Steps -1dB Steps # of Calculated Calculated Calculated Steps Desired Wiper Attenuation Desired Wiper Attenuation Desired Wiper Attenuation Attenuation Code Attenuation Code Attenuation Code (1) (1) (1) 0 0dB 256 0dB 0dB 256 0dB 0dB 256 0dB 1 -3dB 181 -3.011dB -2dB 203 -2.015dB -1dB 228 -1.006dB 2 -6dB 128 -6.021dB -4dB 162 -3.975dB -2dB 203 -2.015dB 3 -9dB 91 -8.984dB -6dB 128 -6.021dB -3dB 181 -3.011dB 4 -12dB 64 -12.041dB -8dB 102 -7.993dB -4dB 162 -3.975dB 5 -15dB 46 -14.910dB -10dB 81 -9.995dB -5dB 144 -4.998dB 6 -18dB 32 -18.062dB -12dB 64 -12.041dB -6dB 128 -6.021dB 7 -21dB 23 -20.930dB -14dB 51 -14.013dB -7dB 114 -7.027dB 8 -24dB 16 -24.082dB -16dB 41 -15.909dB -8dB 102 -7.993dB 9 -27dB 11 -27.337dB -18dB 32 -18.062dB -9dB 91 -8.984dB 10 -30dB 8 -30.103dB -20dB 26 -19.865dB -10dB 81 -9.995dB 11 -33dB 6 -32.602dB -22dB 20 -22.144dB -11dB 72 -11.018dB 12 -36dB 4 -36.124dB -24dB 16 -24.082dB -12dB 64 -12.041dB 13 -39dB 3 -38.622dB -26dB 13 -25.886dB -13dB 57 -13.047dB 14 -42dB 2 -42.144dB -28dB 10 -28.165dB -14dB 51 -14.013dB 15 -48dB 1 -48.165dB -30dB 8 -30.103dB -15dB 46 - 14.910dB 16 Mute 0 Mute -32dB 6 -32.602dB -16dB 41 -15.909dB 17 -34dB 5 -34.185dB -17dB 36 -17.039dB 18 -36dB 4 -36.124dB -18dB 32 -18.062dB 19 -38dB 3 -38.622dB -19dB 29 -18.917dB 20 -42dB 2 -42.144dB -20dB 26 -19.865dB 21 -48dB 1 -48.165dB -21dB 23 - 20.930dB 22 Mute 0 Mute -22dB 20 -22.144dB 23 -23dB 18 -23.059dB 24 -24dB 16 -24.082dB 25 -25dB 14 -25.242dB 26 -26dB 13 -25.886dB 27 -27dB 11 -27.337dB 28 -28dB 10 -28.165dB 29 -29dB 9 -29.080dB 30 -30dB 8 -30.103dB 31 -31dB 7 -31.263dB 32 -33dB 6 -32.602dB 33 -34dB 5 -34.185dB 34 -36dB 4 -36.124dB 35 -39dB 3 -38.622dB 36 -42dB 2 -42.144dB 37 -48dB 1 -48.165dB 38 Mute 0 Mute Note 1: Attenuation values do not include errors from Digital Potentiometer errors, such as Full Scale Error or Zero Scale Error. DS22107B-page 70  2008-2013 Microchip Technology Inc.

MCP454X/456X/464X/466X 8.5 Design Considerations 8.5.2 LAYOUT CONSIDERATIONS In the design of a system with the MCP4XXX devices, Several layout considerations may be applicable to the following considerations should be taken into your application. These may include: account: • Noise • Power Supply Considerations • Footprint Compatibility • Layout Considerations • PCB Area Requirements 8.5.1 POWER SUPPLY 8.5.2.1 Noise CONSIDERATIONS Inductively-coupled AC transients and digital switching The typical application will require a bypass capacitor noise can degrade the input and output signal integrity, in order to filter high-frequency noise, which can be potentially masking the MCP4XXX’s performance. induced onto the power supply's traces. The bypass Careful board layout minimizes these effects and capacitor helps to minimize the effect of these noise increases the Signal-to-Noise Ratio (SNR). Multi-layer sources on signal integrity. Figure8-6 illustrates an boards utilizing a low-inductance ground plane, appropriate bypass strategy. isolated inputs, isolated outputs and proper decoupling are critical to achieving the performance that the silicon In this example, the recommended bypass capacitor is capable of providing. Particularly harsh value is 0.1µF. This capacitor should be placed as environments may require shielding of critical signals. close (within 4mm) to the device power pin (V ) as DD possible. If low noise is desired, breadboards and wire-wrapped boards are not recommended. The power source supplying these devices should be as clean as possible. If the application circuit has 8.5.2.2 Footprint Compatibility separate digital and analog power supplies, V and DD V should reside on the analog plane. The specification of the MCP4XXX pinouts was done to SS allow systems to be designed to easily support the use of either the dual (MCP46XX) or quad (MCP44XX) VDD device. Figure8-7 shows how the dual pinout devices fit on the 0.1µF quad device footprint. For the Rheostat devices, the dual device is in the MSOP package, so the footprints VDD would need to be offset from each other. MCP44X1 Quad Potentiometers 0.1µF P3A 1 20 P2A er P3W 2 19 P2W oll P3B 3 18 P2B tr HVC/A0 4 17 VDD n o SCL 5 16 A1 A 56X/X croc SVDSAS 67 1145 RWEPSET MCP42X1 Pinout (1) W 54X/4X/466 SCL ®C Mi PPP111WAB 8910 111221 PPP000WBA 44 PI CP46 TSSOP B M SDA MCP44X2 Quad Rheostat P3W 1 14 P2W P3B 2 13 P2B HVC/A0 3 12 VDD VSS VSS SCL 4 11 A1 SDA 5 10 P0B MCP42X2 Pinout FIGURE 8-6: Typical Microcontroller VSS 6 9 P0W P1B 7 8 P1W Connections. TSSOP Note 1: Pin 15 (RESET) is the Address A2 (A2) pin on the MCP46x1 device. FIGURE 8-7: Quad Pinout (TSSOP Package) vs. Dual Pinout.  2008-2013 Microchip Technology Inc. DS22107B-page 71

MCP454X/456X/464X/466X Figure8-8 shows possible layout implementations for 8.5.2.3 PCB Area Requirements an application to support the quad and dual options on In some applications, PCB area is a criteria for device the same PCB. selection. Table8-2 shows the package dimensions and area for the different package options. The table Potentiometers Devices also shows the relative area factor compared to the smallest area. For space critical applications, the QFN package would be the suggested package. MCP44X1 TABLE 8-2: PACKAGE FOOTPRINT (1) MCP46X1 Package Package Footprint Pins Type Code DiXm(emnmsi)o Yns 2Area (mm) elative Area R Rheostat Devices MSOP MS 3.00 4.90 14.70 1.63 MCP46X2 8 DFN (3x3) MF 3.00 3.00 9.00 1 MCP44X2 MSOP UN 3.00 4.90 14.70 1.63 10 DFN (3x3) MF 3.00 3.00 9.00 1 14 TSSOP ST 5.10 6.40 32.64 3.62 QFN (4x4) ML 4.00 4.00 16.00 1.78 FIGURE 8-8: Layout to Support Quad and (2) TSSOP ST 6.60 6.40 42.24 3.63 Dual Devices. 16 (2) QFN (4x4) ML 4.00 4.00 16.00 1.78 Note1: Does not include recommended land pattern dimensions. 2: These packages are for the Quad output devices (MCP44x1). 8.5.3 RESISTOR TEMPCO Characterization curves of the resistor temperature coefficient (Tempco) are shown in Figure2-10, Figure2-21, Figure2-32, and Figure2-43. These curves show that the resistor network is designed to correct for the change in resistance as temperature increases. This technique reduces the end-to-end change in R resistance. AB 8.5.4 HIGH VOLTAGE TOLERANT PINS High Voltage support (V ) on the Serial Interface pins IHH supports user configuration of the Nonvolatile EEPROM, Write Protect, and WiperLock feature. Note: In many applications, the High Voltage will only be present at the manufacturing stage so as to “lock” the Nonvolatile wiper value (after calibration) and the contents of the EEPROM. This ensures that since High Voltage is not present under normal operating conditions, that these values can not be modified. DS22107B-page 72  2008-2013 Microchip Technology Inc.

MCP454X/456X/464X/466X 9.0 DEVICE OPTIONS Additional, custom devices are available. These devices have weak pull-up resistors on the SDA and SCL pins. This is useful for applications where the wiper value is programmed during manufacture and not modified by the system during normal operation. Please contact your local sales office for current infor- mation and minimum volume requirements. 9.1 Custom Options The custom device will have a “P” (for Pull-up) after the resistance version in the Product Identification System. These devices will not be available through Microchip’s online Microchip Direct nor Microchip’s Sample systems. Example part number: MCP4641-103PE/ST  2008-2013 Microchip Technology Inc. DS22107B-page 73

MCP454X/456X/464X/466X NOTES: DS22107B-page 74  2008-2013 Microchip Technology Inc.

MCP454X/456X/464X/466X 10.0 DEVELOPMENT SUPPORT 10.2 Technical Documentation Several additional technical documents are available to 10.1 Development Tools assist you in your design and development. These technical documents include Application Notes, Several development tools are available to assist in Technical Briefs, and Design Guides. Table10-2 your design and evaluation of the MCP45XX/46XX shows some of these documents. devices. The currently available tools are shown in Table10-1. These boards may be purchased directly from the Microchip web site at www.microchip.com. TABLE 10-1: DEVELOPMENT TOOLS Board Name Part # Supported Devices MCP46XX PICTail Plus Daughter Board (2) MCP46XXDM-PTPLS MCP46XX MCP46XX Evaluation Board MCP46XXEV MCP4631/41/51/61 MCP43XX Evaluation Board MCP43XXEV MCP4331/41/51/61 MCP4XXX Digital Potentiometer Daughter Board (1) MCP4XXXDM-DB MCP42XXX, MCP42XX, MCP46XX, MCP4021, and MCP4011 8-pin SOIC/MSOP/TSSOP/DIP Evaluation Board SOIC8EV Any 8-pin device in DIP, SOIC, MSOP, or TSSOP package 14-pin SOIC/MSOP/DIP Evaluation Board SOIC14EV Any 14-pin device in DIP, SOIC, or MSOP package Note1: Requires the use of a PICDEM Demo Board (see User’s Guide for details) 2: Requires the use of the PIC24 Explorer 16 Demo Board (see User’s Guide for details) 3: The desired MCP46XX device (in MSOP package) must be soldered onto the extra board. TABLE 10-2: TECHNICAL DOCUMENTATION Application Title Literature # Note Number TB3073 Implementing a 10-bit Digital Potentiometer using a Quad 8-bit Digital Potentiometer DS93073 Technical Brief AN1316 Using Digital Potentiometers for Programmable Amplifier Gain DS01316 AN1080 Understanding Digital Potentiometers Resistor Variations DS01080 AN737 Using Digital Potentiometers to Design Low Pass Adjustable Filters DS00737 AN692 Using a Digital Potentiometer to Optimize a Precision Single-Supply Photo Detect DS00692 AN691 Optimizing the Digital Potentiometer in Precision Circuits DS00691 AN219 Comparing Digital Potentiometers to Mechanical Potentiometers DS00219 — Digital Potentiometer Design Guide DS22017 — Signal Chain Design Guide DS21825  2008-2013 Microchip Technology Inc. DS22107B-page 75

MCP454X/456X/464X/466X NOTES: DS22107B-page 76  2008-2013 Microchip Technology Inc.

MCP454X/456X/464X/466X 11.0 PACKAGING INFORMATION 11.1 Package Marking Information 8-Lead DFN (3x3) Example: Part Number Code Part Number Code MCP4541-502E/MF DACJ MCP4542-502E/MF DACP XXXX DACJ XYWW MCP4541-103E/MF DACK MCP4542-103E/MF DACQ E841 NNN MCP4541-104E/MF DACM MCP4542-104E/MF DACS 256 MCP4541-503E/MF DACL MCP4542-503E/MF DACR MCP4561-502E/MF DADB MCP4562-502E/MF DADF MCP4561-103E/MF DADC MCP4562-103E/MF DADG MCP4561-104E/MF DADE MCP4562-104E/MF DADJ MCP4561-503E/MF DADD MCP4562-503E/MF DADH 8-Lead MSOP Example Part Number Code Part Number Code MCP4541-103E/MS 454113 MCP4542-103E/MS 454213 XXXXXX 454113 MCP4541-104E/MS 454114 MCP4542-104E/MS 454214 YWWNNN 841256 MCP4541-502E/MS 454152 MCP4542-502E/MS 454252 MCP4541-503E/MS 454153 MCP4542-503E/MS 454253 MCP4561-103E/MS 456113 MCP4562-103E/MS 456213 MCP4561-104E/MS 456114 MCP4562-104E/MS 456214 MCP4561-502E/MS 456152 MCP4562-502E/MS 456252 MCP4561-503E/MS 456153 MCP4562-503E/MS 456253 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2008-2013 Microchip Technology Inc. DS22107B-page 77

MCP454X/456X/464X/466X Package Marking Information (Continued) 10-Lead DFN (3x3) Example: Part Number Code Part Number Code XXXX AAFA MCP4642-502E/MF AAFA MCP4662-502E/MF AAQA YYWW 0841 NNN MCP4642-103E/MF AAGA MCP4662-103E/MF AARA 256 MCP4642-104E/MF AAJA MCP4662-104E/MF AATA MCP4642-503E/MF AAHA MCP4662-503E/MF AASA 10-Lead MSOP Example Part Number Code Part Number Code XXXXXX 463252 MCP4642-502E/UN 464252 MCP4662-502E/UN 466252 YWWNNN 841256 MCP4642-103E/UN 464213 MCP4662-103E/UN 466213 MCP4642-104E/UN 464214 MCP4662-104E/UN 466214 MCP4642-503E/UN 464253 MCP4662-503E/UN 466253 14-Lead TSSOP (MCP4641, MCP4661) Example XXXXXXXX 4641502E YYWW 0841 NNN 256 16-Lead QFN (MCP4641, MCP4661) Example XXXXX 4641 XXXXXX 502 XXXXXX E/ML^e^3 YWWNNN 841256 DS22107B-page 78  2008-2013 Microchip Technology Inc.

MCP454X/456X/464X/466X Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2008-2013 Microchip Technology Inc. DS22107B-page 79

MCP454X/456X/464X/466X Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22107B-page 80  2008-2013 Microchip Technology Inc.

MCP454X/456X/464X/466X (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:8)(cid:17)(cid:10)(cid:6)(cid:12)(cid:18)(cid:8)(cid:19)(cid:20)(cid:8)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:14)(cid:21)(cid:6)(cid:22)(cid:5)(cid:8)(cid:23)(cid:24)(cid:17)(cid:25)(cid:8)(cid:26)(cid:8)(cid:27)(cid:28)(cid:27)(cid:28)(cid:29)(cid:30)(cid:31)(cid:8) (cid:8)!(cid:20)(cid:7)"(cid:8)#(cid:15)(cid:17)(cid:19)$ (cid:19)(cid:20)(cid:12)(cid:5)% (cid:30)(cid:10)(cid:9)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2) (cid:10)!(cid:31)(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)(cid:31)(cid:2)(cid:12)(cid:28)(cid:8)#(cid:28)(cid:17)(cid:14)(cid:2)$(cid:9)(cid:28)%(cid:7)(cid:15)(cid:17)!&(cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)’(cid:28)(cid:8)#(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)((cid:7)(cid:8)(cid:28)(cid:31)(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)(cid:31)(cid:14)$(cid:2)(cid:28)(cid:31)(cid:2) (cid:11)(cid:31)(cid:31)(cid:12))**%%%(cid:20) (cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10) *(cid:12)(cid:28)(cid:8)#(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)  2008-2013 Microchip Technology Inc. DS22107B-page 81

MCP454X/456X/464X/466X Note: For the mostcurrent package drawings,please seetheMicrochip Packaging Specification located at http://www.microchip.com/packaging DS22107B-page 82  2008-2013 Microchip Technology Inc.

MCP454X/456X/464X/466X Note: For the mostcurrent package drawings,please seetheMicrochip Packaging Specification located at http://www.microchip.com/packaging  2008-2013 Microchip Technology Inc. DS22107B-page 83

MCP454X/456X/464X/466X Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22107B-page 84  2008-2013 Microchip Technology Inc.

MCP454X/456X/464X/466X Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2008-2013 Microchip Technology Inc. DS22107B-page 85

MCP454X/456X/464X/466X Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22107B-page 86  2008-2013 Microchip Technology Inc.

MCP454X/456X/464X/466X Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2008-2013 Microchip Technology Inc. DS22107B-page 87

MCP454X/456X/464X/466X UN Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22107B-page 88  2008-2013 Microchip Technology Inc.

MCP454X/456X/464X/466X UN Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2008-2013 Microchip Technology Inc. DS22107B-page 89

MCP454X/456X/464X/466X 10-Lead Plastic Micro Small Outline Package (UN) [MSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22107B-page 90  2008-2013 Microchip Technology Inc.

MCP454X/456X/464X/466X Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2008-2013 Microchip Technology Inc. DS22107B-page 91

MCP454X/456X/464X/466X Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22107B-page 92  2008-2013 Microchip Technology Inc.

MCP454X/456X/464X/466X Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2008-2013 Microchip Technology Inc. DS22107B-page 93

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DS22107B-page 94  2008-2013 Microchip Technology Inc.

MCP454X/456X/464X/466X Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2008-2013 Microchip Technology Inc. DS22107B-page 95

MCP454X/456X/464X/466X NOTES: DS22107B-page 96  2008-2013 Microchip Technology Inc.

MCP454X/456X/464X/466X APPENDIX A: REVISION HISTORY Revision B (February 2013) The following is the list of modifications: 1. Updated the DFN package pinout on page 1. 2. Updated the Absolute Maximum Ratings† page format and added Total Power Dissipation values for each package type. 3. Updated the typical thermal package resistance values for the 8L-DFN (3x3) and 8L-SOIC pack- ages in the Temperature characteristics table. 4. Added new Figure2-59 to Section2.1 “Test Circuits”. 5. Corrected values in Figure5-1. 6. Added description of wiper value on POR/BOR (Section5.2 “Wiper”). 7. Removed Section 8.1. 8. Added Section8.4 “Implementing Log Steps with a Linear Digital Potentiometer”. 9. Added Section8.5.2.2 “Footprint Compatibil- ity”. 10. Added Section8.5.2.3 “PCB Area Require- ments”. 11. Updated Table8-2. 12. Enhanced the listing of development tools and technical documentation in Section10.0 “Development support”. 13. Updated Table10-1 and Table10-2. 14. Updated Section11.0 “Packaging Informa- tion” with package available landing pattern diagrams. Revision A (November 2008) • Original Release of this Document.  2008-2012 Microchip Technology Inc. DS22107B-page 97

MCP454X/456X/464X/466X NOTES: DS22107B-page 98  2008-2012 Microchip Technology Inc.

MCP454X/456X/464X/466X PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. XXX X /XX Examples: a) MCP4541-502E/XX: 5k 8LD Device Device Resistance Temperature Package b) MCP4541-103E/XX: 10k, 8-LD Device Version Range c) MCP4541-503E/XX: 50k, 8LD Device d) MCP4541-104E/XX: 100k, 8LD Device e) MCP4541T-104E/XX: T/R, 100k, 8LD Device Device: MCP4541: Single Nonvolatile 7-bit Potentiometer a) MCP4542-502E/XX: 5k 8LD Device MCP4541T: Single Nonvolatile 7-bit Potentiometer b) MCP4542-103E/XX: 10k, 8-LD Device (Tape and Reel) c) MCP4542-503E/XX: 50k, 8LD Device MCP4542: Single Nonvolatile 7-bit Rheostat d) MCP4542-104E/XX: 100k, 8LD Device MCP4542T: Single Nonvolatile 7-bit Rheostat e) MCP4542T-104E/XX: T/R, 100k, 8LD Device (Tape and Reel) MCP4561: Single Nonvolatile 8-bit Potentiometer a) MCP4561-502E/XX: 5k 8LD Device MCP4561T: Single Nonvolatile 8-bit Potentiometer b) MCP4561-103E/XX: 10k, 8-LD Device (Tape and Reel) c) MCP4561-503E/XX: 50k, 8LD Device MCP4562: Single Nonvolatile8-bit Rheostat d) MCP4561-104E/XX: 100k, 8LD Device MCP4562T: Single Nonvolatile 8-bit Rheostat e) MCP4561T-104E/XX: T/R, 100k, 8LD Device (Tape and Reel) a) MCP4562-502E/XX: 5k 8LD Device MCP4641: Dual Nonvolatile 7-bit Potentiometer b) MCP4562-103E/XX: 10k, 8-LD Device MCP4641T: Dual Nonvolatile 7-bit Potentiometer c) MCP4562-503E/XX: 50k, 8LD Device (Tape and Reel) d) MCP4562-104E/XX: 100k, 8LD Device MCP4642: Dual Nonvolatile 7-bit Rheostat e) MCP4562T-104E/XX: T/R, 100k, 8LD Device MCP4642T: Dual Nonvolatile 7-bit Rheostat (Tape and Reel) a) MCP4641-502E/XX: 5k 8LD Device MCP4661: Dual Nonvolatile 8-bit Potentiometer b) MCP4641-103E/XX: 10k, 8-LD Device MCP4661T: Dual Nonvolatile 8-bit Potentiometer c) MCP4641-503E/XX: 50k, 8LD Device (Tape and Reel) d) MCP4641-104E/XX: 100k, 8LD Device MCP4662: Dual Nonvolatile8-bit Rheostat e) MCP4641T-104E/XX: T/R, 100k, 8LD Device MCP4662T: Dual Nonvolatile 8-bit Rheostat a) MCP4642-502E/XX: 5k 8LD Device (Tape and Reel) b) MCP4642-103E/XX: 10k, 8-LD Device c) MCP4642-503E/XX: 50k, 8LD Device Resistance Version: 502 = 5k d) MCP4642-104E/XX: 100k, 8LD Device 103 = 10k e) MCP4642T-104E/XX: T/R, 100k, 8LD Device 503 = 50k a) MCP4661-502E/XX: 5k 8LD Device 104 = 100k b) MCP4661-103E/XX: 10k, 8-LD Device c) MCP4661-503E/XX: 50k, 8LD Device d) MCP4661-104E/XX: 100k, 8LD Device Temperature Range: E = -40°C to +125°C e) MCP4661T-104E/XX: T/R, 100k, 8LD Device a) MCP4662-502E/XX: 5k 8LD Device Package: MF = Plastic Dual Flat No-lead (3x3 DFN), 8/10-lead b) MCP4662-103E/XX: 10k, 8-LD Device ML = Plastic Quad Flat No-lead (QFN), 16-lead c) MCP4662-503E/XX: 50k, 8LD Device MS = Plastic Micro Small Outline (MSOP), 8-lead d) MCP4662-104E/XX: 100k, 8LD Device ST = Plastic Thin Shrink Small Outline (TSSOP), 14-lead e) MCP4662T-104E/XX: T/R, 100k, 8LD Device UN = Plastic Micro Small Outline (MSOP), 10-lead XX = MF for 8/10-lead 3x3 DFN = ML for 16-lead QFN = MS for 8-lead MSOP = ST for 14-lead TSSOP = UN for 10-lead MSOP  2008-2013 Microchip Technology Inc. DS22107B-page 99

MCP454X/456X/464X/466X NOTES: DS22107B-page 100  2008-2013 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, ensure that your application meets with your specifications. PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash MICROCHIP MAKES NO REPRESENTATIONS OR and UNI/O are registered trademarks of Microchip Technology WARRANTIES OF ANY KIND WHETHER EXPRESS OR Incorporated in the U.S.A. and other countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MTP, SEEVAL and The Embedded Control Solutions QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Silicon Storage Technology is a registered trademark of devices in life support and/or safety applications is entirely at Microchip Technology Inc. in other countries. the buyer’s risk, and the buyer agrees to defend, indemnify and Analog-for-the-Digital Age, Application Maestro, BodyCom, hold harmless Microchip from any and all damages, claims, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, suits, or expenses resulting from such use. No licenses are dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, conveyed, implicitly or otherwise, under any Microchip ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial intellectual property rights. Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. & KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2008-2013, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-62077-032-0 QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures == ISO/TS 16949 == are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2008-2013 Microchip Technology Inc. DS22107B-page 101

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: MCP4642T-502E/MF MCP4541-503E/MS MCP4641T-502E/ML MCP4662T-503E/UN MCP4642T-104E/UN MCP4662T-103E/UN MCP4661T-103E/ML MCP4642T-502E/UN MCP4661T-503E/ML MCP4642T-104E/MF MCP4641T-103E/ST MCP4641T-503E/ST MCP4641T-502E/ST MCP4561-103E/MS MCP4561-503E/MS MCP4541T-104E/MF MCP4662T-103E/MF MCP4542-502E/MS MCP4662T-503E/MF MCP4541T-104E/MS MCP4562T-104E/MF MCP4562-103E/MS MCP4542T-502E/MS MCP4661T-103E/ST MCP4542T-104E/MS MCP4661T-502E/ML MCP4642-103E/UN MCP4661-502E/ST MCP4662T-104E/UN MCP4562-503E/MS MCP4642- 104E/UN MCP4642T-503E/MF MCP4661T-104E/ST MCP4541T-502E/MF MCP4542T-104E/MF MCP4541-104E/MS MCP4641T-503E/ML MCP4642T-103E/MF MCP4542-104E/MS MCP4561-502E/MS MCP4642-502E/UN MCP4562T-503E/MF MCP4541-502E/MS MCP4661-104E/ST MCP4641T-104E/ST MCP4662T-502E/MF MCP4662T-502E/UN MCP4662T-104E/MF MCP4642-503E/UN MCP4561T-104E/MF MCP4562-502E/MS MCP4561T-104E/MS MCP4562T-104E/MS MCP4661T-503E/ST MCP4561T-103E/MS MCP4641-503E/ST MCP4561T-503E/MS MCP4542T-502E/MF MCP4641T-103E/ML MCP4662-104E/UN MCP4561-104E/MS MCP4661-503E/ST MCP4542T-103E/MF MCP4641-502E/ST MCP4561T-103E/MF MCP4561T-503E/MF MCP4662- 503E/UN MCP4642T-103E/UN MCP4541T-502E/MS MCP4562T-103E/MF MCP4562T-503E/MS MCP4642T- 503E/UN MCP4641-103E/ST MCP4562T-103E/MS MCP4542-103E/MS MCP4662-103E/UN MCP4661T-502E/ST MCP4561T-502E/MS MCP4541T-503E/MS MCP4661-103E/ST MCP4541T-103E/MF MCP4662-502E/UN MCP4562T-502E/MF MCP4561T-502E/MF MCP4562T-502E/MS MCP4641T-104E/ML MCP4542T-503E/MS MCP4641-104E/ST MCP4542-503E/MS MCP4541-103E/MS MCP4542T-103E/MS MCP4541T-103E/MS MCP4661T-104E/ML MCP4542T-503E/MF MCP4562-104E/MS MCP4541T-503E/MF MCP4541T-103E/MSVAO MCP4541T-503E/MSVAO