MCP443X/5X 7/8-Bit Volatile Quad Digital POT 2 with I C Interface Package Types (Top View) Features • Quad Resistor Network • Potentiometer or Rheostat Configuration Options MCP44X1 Quad Potentiometers • Resistor Network Resolution: 7-bit – 128 Resistors (129 Taps) P3A 1 20 P2A P3W 2 19 P2W 8-bit – 256 Resistors (257 Taps) P3B 3 18 P2B • Four RAB Resistances options: HVC/A0 4 17 VDD SCL 5 16 A1 5k SDA 6 15 RESET 10k VSS 7 14 NC 50k P1B 8 12 P0B P1W 9 12 P0W 100k P1A 10 11 P0A • Zero-scale to Full-scale Wiper Operation TSSOP • Low Wiper Resistance – 75 typical • Low Tempco: Absolute (Rheostat) – 50ppm typical (0°-70°C) Ratiometric (Potentiometer) – 15ppm typical W A A W B • I2C Serial Interface Support: 3 3 2 2 2 P P P P P 100kHz 20 19 18 17 16 15 V 400kHz P3B 1 DD 3.4MHz 14 A1 HVC/A0 2 • Serial Protocol Allows High-Speed Read/Write to SCL 3 EP 13 RESET Wiper 21 12 NC SDA 4 • Resistor Network Terminal Disconnect Feature 11 P0B via Terminal Control (TCON) Register VSS 5 • Reset Input Pin 6 7 8 9 10 • Brown-out Reset Protection – 1.5V typical B W A A W • Serial Interface Inactive Current – 2.5uA typical P1 P1 P1 P0 P0 • High-Voltage Tolerant Digital Inputs Up to 12.5V 4x4 QFN • Supports Split Rail Applications • Internal Weak Pull-up on All Digital Inputs, except SCL and SDA • Wide Operating Voltage: MCP44X2 Quad Rheostat 2.7V to 5.5V - Device Characteristics Specified 1.8V to 5.5V - Device Operation P3W 1 14 P2W • Wide Bandwidth (-3dB) Operation – P3B 2 13 P2B 2MHz typical for 5.0k Device HVC/A0 3 12 VDD SCL 4 11 A1 • Extended Temperature Range (-40°C to +125°C) SDA 5 10 P0B • Three Package Types: VSS 6 9 P0W P1B 7 8 P1W 4x4 QFN-20 TSSOP-20 TSSOP TSSOP-14  2010 Microchip Technology Inc. DS22267A-page 1

MCP443X/5X Device Block Diagram VDD Power-up/ Resistor P0A Brown-out V Network 0 SS Control (Pot 0) P0W A1 I2C Serial Wiper 0 & TCON0 Interface HVC/A0 Register Module & P0B SCL Control SDA Logic P1A Resistor Network 1 RESET (Pot 1) P1W Wiper 1 Memory (16x9) & TCON0 Wiper0 (Vol) Register P1B Wiper1 (Vol) Wiper2 (Vol) Wiper3 (Vol) P2A Resistor TCON0 Network 2 TCON1 (Pot 2) P2W Wiper 2 & TCON1 Register P2B P3A Resistor Network 3 (Pot 3) P3W Wiper 3 & TCON1 Register P3B Device Features Device # of POTs ConWfigipuerar tion Control Memory Type WiperLock Technology POR Wiper Setting RARB eOspisttiaonncse ( k(ty)picaW-l( )iRpW)er # of Taps ORpaeVnrDgaDeti (n2)g MCP4431 4 Potentiometer (1) I2C RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 129 1.8V to 5.5V MCP4432 4 Rheostat I2C RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 129 1.8V to 5.5V MCP4441 4 Potentiometer (1) I2C EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0 75 129 2.7V to 5.5V MCP4442 4 Rheostat I2C EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0 75 129 2.7V to 5.5V MCP4451 4 Potentiometer(1) I2C RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 257 1.8V to 5.5V MCP4452 4 Rheostat I2C RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 257 1.8V to 5.5V MCP4461 4 Potentiometer(1) I2C EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0 75 257 2.7V to 5.5V MCP4462 4 Rheostat I2C EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0 75 257 2.7V to 5.5V Note 1: Floating either terminal (A or B) allows the device to be used as a Rheostat (variable resistor). 2: Analog characteristics only tested from 2.7V to 5.5V unless otherwise noted. DS22267A-page 2  2010 Microchip Technology Inc.

MCP443X/5X 1.0 ELECTRICAL † Notice: Stresses above those listed under “Maximum CHARACTERISTICS Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those Absolute Maximum Ratings † indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions Voltage on V with respect to V ..... -0.6V to +7.0V DD SS for extended periods may affect device reliability. Voltage on HVC/A0, A1, SCL, SDA, and RESET, with respect to V -0.6V to 12.5V SS ............................................... Voltage on all other pins (PxA, PxW, and PxB), with respect to V -0.3V to V + 0.3V SS ..................................... DD Input clamp current, I IK (VI < 0, VI > VDD, VI > VPP ON HV pins)...........±20mA Output clamp current, I OK (V < 0 or V > V ).......................................±20mA O O DD Maximum output current sunk by any Output pin ...........................................................................25mA Maximum output current sourced by any Output pin ...........................................................................25mA Maximum current out of V pin......................100mA SS Maximum current into V pin.........................100mA DD Maximum current into PXA, PXW & PXB pins.±2.5mA Storage temperature .........................-65°C to +150°C Ambient temperature with power applied .......................................................... -40°C to +125°C Package power dissipation (T = +50°C, T = +150°C) A J TSSOP-14.................................................1000mW TSSOP-20..................................................1110mW QFN-20 (4x4).............................................2320mW Soldering temperature of leads (10 seconds)..+300°C ESD protection on all pins 4kV (HBM), ................................................................ 300V (MM) Maximum Junction Temperature (T ) ..............+150°C J  2010 Microchip Technology Inc. DS22267A-page 3

MCP443X/5X AC/DC CHARACTERISTICS Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C  T  +125°C (extended) A DC Characteristics All parameters apply across the specified operating ranges unless noted. V = +2.7V to 5.5V, 5k, 10k, 50k, 100k devices. DD Typical specifications represent values for V = 5.5V, T = +25°C. DD A Parameters Sym Min Typ Max Units Conditions Supply Voltage V 2.7 — 5.5 V DD 1.8 — 2.7 V Serial Interface only. HVC/A0, SDA, V V — 12.5V V V  The HVC/A0 pin will be at one HV SS DD SCL, A1, RESET 4.5V of three input levels pin (V , V or V ). (Note6) V — V + V V < IL IH IHH Voltage Range SS DD DD 8.0V 4.5V V Start Voltage V — — 1.65 V RAM retention voltage (V ) < V DD BOR RAM BOR to ensure Wiper Reset V Rise Rate to V (Note9) V/ms DD DDRR ensure Power-on Reset Delay after device T — 10 20 µs BORD exits the Reset state (V > V ) DD BOR Supply Current I — — 600 µA Serial Interface Active, DD (Note10) HVC/A0 = V (or V ) (Note11) IH IL Write all 0’s to volatile Wiper 0 V = 5.5V, F @ 3.4MHz DD SCL — — 250 µA Serial Interface Active, HVC/A0 = V (or V ) (Note11) IH IL Write all 0’s to volatile Wiper 0 V = 5.5V, F @ 100kHz DD SCL — 2.5 5 µA Serial Interface Inactive, (Stop condition, SCL = SDA = V ), IH Wiper = 0 V = 5.5V, HVC/A0 = V DD IH Note 1: Resistance is defined as the resistance between terminal A to terminal B. 2: INL and DNL are measured at V with V = V and V = V . W A DD B SS 3: MCP44X1 only. 4: MCP44X2 only, includes V and V . WZSE WFSE 5: Polarity of resistor terminals A, W and B, with respect to each other, is not restricted. 6: This specification by design. 7: Non-linearity is affected by wiper resistance (R ), which changes significantly over voltage and W temperature. 8: The MCP44X1 is externally connected to match the configurations of the MCP44X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network. 11: When HVC/A0 = V , the I current is less due to current into the HVC/A0 pin. See I specification. IHH DD PU DS22267A-page 4  2010 Microchip Technology Inc.

MCP443X/5X AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C  T  +125°C (extended) A DC Characteristics All parameters apply across the specified operating ranges unless noted. V = +2.7V to 5.5V, 5k, 10k, 50k, 100k devices. DD Typical specifications represent values for V = 5.5V, T = +25°C. DD A Parameters Sym Min Typ Max Units Conditions Resistance R 4.0 5 6.0 k -502 devices(Note1) AB (± 20%) 8.0 10 12.0 k -103 devices(Note1) 40.0 50 60.0 k -503 devices(Note1) 80.0 100 120.0 k -104 devices(Note1) Resolution N 257 Taps 8-bit No Missing Codes 129 Taps 7-bit No Missing Codes Step Resistance R — R / —  8-bit Note6 S AB (256) — R / —  7-bit Note6 AB (128) Nominal (| R - — 0.2 1.50 % 5k MCP44X1 devices only ABWC Resistance Match RABMEAN |) / — 0.2 1.25 % 10k R ABMEAN — 0.2 1.0 % 50k — 0.2 1.0 % 100k (| R - — 0.25 1.75 % 5k Code = Full Scale BWWC RBWMEAN |) / — 0.25 1.50 % 10k R BWMEAN — 0.25 1.25 % 50k — 0.25 1.25 % 100k Wiper Resistance R — 75 160  V = 5.5 V, I = 2.0mA, code = 00h W DD W (Note3, Note4) — 75 300  V = 2.7 V, I = 2.0mA, code = 00h DD W Nominal R /T — 50 — ppm/°C T = -20°C to +70°C AB A Resistance — 100 — ppm/°C T = -40°C to +85°C A Tempco — 150 — ppm/°C T = -40°C to +125°C A Ratiometeric V /T — 15 — ppm/°C Code = Midscale (80h or 40h) WB Tempco Resistance RTRACK Section2.0 ppm/°C See Typical Performance Curves Tracking Note 1: Resistance is defined as the resistance between terminal A to terminal B. 2: INL and DNL are measured at V with V = V and V = V . W A DD B SS 3: MCP44X1 only. 4: MCP44X2 only, includes V and V . WZSE WFSE 5: Polarity of resistor terminals A, W and B, with respect to each other, is not restricted. 6: This specification by design. 7: Non-linearity is affected by wiper resistance (R ), which changes significantly over voltage and W temperature. 8: The MCP44X1 is externally connected to match the configurations of the MCP44X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network. 11: When HVC/A0 = V , the I current is less due to current into the HVC/A0 pin. See I specification. IHH DD PU  2010 Microchip Technology Inc. DS22267A-page 5

MCP443X/5X AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C  T  +125°C (extended) A DC Characteristics All parameters apply across the specified operating ranges unless noted. V = +2.7V to 5.5V, 5k, 10k, 50k, 100k devices. DD Typical specifications represent values for V = 5.5V, T = +25°C. DD A Parameters Sym Min Typ Max Units Conditions Resistor Terminal V V V V — V V Note5, Note6 A, W, B SS DD Input Voltage Range (Terminals A, B and W) Maximum current I — — 2.5 mA Terminal A I , W AW through A, W or B W = Full Scale (FS) (Note6) — — 2.5 mA Terminal B I , BW W = Zero Scale (ZS) — — 2.5 mA Terminal W I (W = FS) or AW I (W = ZS) BW Maximum R I — — 1.38 mA V = 0V, V = 5.5V, R = 4000 AB AB B A AB(MIN) current (IAB) — — 0.688 mA VB = 0V, VA = 5.5V, RAB(MIN) = 8000 (Note6) — — 0.138 mA V = 0V, V = 5.5V, R = 40000 B A AB(MIN) — — 0.069 mA V = 0V, V = 5.5V, R = 80000 B A AB(MIN) Leakage current I — 100 — nA MCP44X1 PxA = PxW = PxB = V WL SS into A, W or B — 100 — nA MCP44X2 PxB = PxW = V SS — 100 — nA Terminals Disconnected (R0A = R0W = R0B = 0; R1A = R1W = R1B = 0; R2A = R2W = R2B = 0; R3A = R3W = R3B = 0) Note 1: Resistance is defined as the resistance between terminal A to terminal B. 2: INL and DNL are measured at V with V = V and V = V . W A DD B SS 3: MCP44X1 only. 4: MCP44X2 only, includes V and V . WZSE WFSE 5: Polarity of resistor terminals A, W and B, with respect to each other, is not restricted. 6: This specification by design. 7: Non-linearity is affected by wiper resistance (R ), which changes significantly over voltage and W temperature. 8: The MCP44X1 is externally connected to match the configurations of the MCP44X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network. 11: When HVC/A0 = V , the I current is less due to current into the HVC/A0 pin. See I specification. IHH DD PU DS22267A-page 6  2010 Microchip Technology Inc.

MCP443X/5X AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C  T  +125°C (extended) A DC Characteristics All parameters apply across the specified operating ranges unless noted. V = +2.7V to 5.5V, 5k, 10k, 50k, 100k devices. DD Typical specifications represent values for V = 5.5V, T = +25°C. DD A Parameters Sym Min Typ Max Units Conditions Full Scale Error V -6.0 -0.1 — LSb 5k 8-bit 3.0V  V  5.5V WFSE DD (MCP44X1 only) -4.0 -0.1 — LSb 7-bit 3.0V  V  5.5V DD (8-bit code = 100h, -3.5 -0.1 — LSb 10k 8-bit 3.0V  V  5.5V 7-bit code = 80h) DD -2.0 -0.1 — LSb 7-bit 3.0V  V  5.5V DD -0.8 -0.1 — LSb 50k 8-bit 3.0V  V  5.5V DD -0.5 -0.1 — LSb 7-bit 3.0V  V  5.5V DD -0.5 -0.1 — LSb 100k 8-bit 3.0V  V  5.5V DD -0.5 -0.1 — LSb 7-bit 3.0V  V  5.5V DD Zero Scale Error V — +0.1 +6.0 LSb 5k 8-bit 3.0V  V  5.5V WZSE DD (MCP44X1 only) — +0.1 +3.0 LSb 7-bit 3.0V  V  5.5V DD (8-bit code = 00h, — +0.1 +3.5 LSb 10k 8-bit 3.0V  V  5.5V 7-bit code = 00h) DD — +0.1 +2.0 LSb 7-bit 3.0V  V  5.5V DD — +0.1 +0.8 LSb 50k 8-bit 3.0V  V  5.5V DD — +0.1 +0.5 LSb 7-bit 3.0V  V  5.5V DD — +0.1 +0.5 LSb 100k 8-bit 3.0V  V  5.5V DD — +0.1 +0.5 LSb 7-bit 3.0V  V  5.5V DD Potentiometer INL -1 ±0.5 +1 LSb 8-bit 3.0V  V  5.5V DD Integral -0.5 ±0.25 +0.5 LSb 7-bit MCP44X1 devices only Non-linearity (Note2) Potentiometer DNL -0.5 ±0.25 +0.5 LSb 8-bit 3.0V  V  5.5V DD Differential Non- -0.25 ±0.125 +0.25 LSb 7-bit MCP44X1 devices only linearity (Note2) Bandwidth -3dB BW — 2 — MHz 5k 8-bit Code = 80h (See Figure2-90, — 2 — MHz 7-bit Code = 40h load = 30pF) — 1 — MHz 10k 8-bit Code = 80h — 1 — MHz 7-bit Code = 40h — 200 — kHz 50k 8-bit Code = 80h — 200 — kHz 7-bit Code = 40h — 100 — kHz 100k 8-bit Code = 80h — 100 — kHz 7-bit Code = 40h Note 1: Resistance is defined as the resistance between terminal A to terminal B. 2: INL and DNL are measured at V with V = V and V = V . W A DD B SS 3: MCP44X1 only. 4: MCP44X2 only, includes V and V . WZSE WFSE 5: Polarity of resistor terminals A, W and B, with respect to each other, is not restricted. 6: This specification by design. 7: Non-linearity is affected by wiper resistance (R ), which changes significantly over voltage and W temperature. 8: The MCP44X1 is externally connected to match the configurations of the MCP44X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network. 11: When HVC/A0 = V , the I current is less due to current into the HVC/A0 pin. See I specification. IHH DD PU  2010 Microchip Technology Inc. DS22267A-page 7

MCP443X/5X AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C  T  +125°C (extended) A DC Characteristics All parameters apply across the specified operating ranges unless noted. V = +2.7V to 5.5V, 5k, 10k, 50k, 100k devices. DD Typical specifications represent values for V = 5.5V, T = +25°C. DD A Parameters Sym Min Typ Max Units Conditions Rheostat Integral R-INL -1.5 ±0.5 +1.5 LSb 5k 8-bit 5.5V, I = 900µA W Non-linearity -8.25 +4.5 +8.25 LSb 3.0V, I = 480µA W MCP44X1 (Note7) (Note4, Note8) Section2.0 1.8V, I = 190µA MCP44X2 devices W -1.125 ±0.5 +1.125 LSb 7-bit 5.5V, I = 900µA only (Note4) W -6.0 +4.5 +6.0 LSb 3.0V, I = 480µA W (Note7) Section2.0 1.8V, I = 190µA W -1.5 ±0.5 +1.5 LSb 10k 8-bit 5.5V, I = 450µA W -5.5 +2.5 +5.5 LSb 3.0V, I = 240µA W (Note7) Section2.0 1.8V, I = 150µA W -1.125 ±0.5 +1.125 LSb 7-bit 5.5V, I = 450µA W -4.0 +2.5 +4.0 LSb 3.0V, I = 240µA W (Note7) Section2.0 1.8V, I = 150µA W -1.5 ±0.5 +1.5 LSb 50k 8-bit 5.5V, I = 90µA W -2.0 +1 +2.0 LSb 3.0V, I = 48µA W (Note7) Section2.0 1.8V, I = 30µA W -1.125 ±0.5 +1.125 LSb 7-bit 5.5V, I = 90µA W -1.5 +1 +1.5 LSb 3.0V, I = 48µA W (Note7) Section2.0 1.8V, I = 30µA W -1.0 ±0.5 +1.0 LSb 100k 8-bit 5.5V, I = 45µA W -1.5 +0.25 +1.5 LSb 3.0V, I = 24µA W (Note7) Section2.0 1.8V, I = 15µA W -0.8 ±0.5 +0.8 LSb 7-bit 5.5V, I = 45µA W -1.125 +0.25 +1.125 LSb 3.0V, I = 24µA W (Note7) Section2.0 1.8V, I = 15µA W Note 1: Resistance is defined as the resistance between terminal A to terminal B. 2: INL and DNL are measured at V with V = V and V = V . W A DD B SS 3: MCP44X1 only. 4: MCP44X2 only, includes V and V . WZSE WFSE 5: Polarity of resistor terminals A, W and B, with respect to each other, is not restricted. 6: This specification by design. 7: Non-linearity is affected by wiper resistance (R ), which changes significantly over voltage and W temperature. 8: The MCP44X1 is externally connected to match the configurations of the MCP44X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network. 11: When HVC/A0 = V , the I current is less due to current into the HVC/A0 pin. See I specification. IHH DD PU DS22267A-page 8  2010 Microchip Technology Inc.

MCP443X/5X AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C  T  +125°C (extended) A DC Characteristics All parameters apply across the specified operating ranges unless noted. V = +2.7V to 5.5V, 5k, 10k, 50k, 100k devices. DD Typical specifications represent values for V = 5.5V, T = +25°C. DD A Parameters Sym Min Typ Max Units Conditions Rheostat R-DNL -0.5 ±0.25 +0.5 LSb 5k 8-bit 5.5V, I = 900µA W Differential Non- -1.0 +0.5 +1.0 LSb 3.0V, I = 480µA W linearity (Note7) MCP44X1 Section2.0 1.8V, I = 190µA (Note4, Note8) W -0.375 ±0.25 +0.375 LSb 7-bit 5.5V, I = 900µA MCP44X2 devices W only -0.75 +0.5 +0.75 LSb 3.0V, IW = 480µA (Note4) (Note7) Section2.0 1.8V, I = 190µA W -0.5 ±0.25 +0.5 LSb 10k 8-bit 5.5V, I = 450µA W -1.0 +0.25 +1.0 LSb 3.0V, I = 240µA W (Note7) Section2.0 1.8V, I = 150µA W -0.375 ±0.25 +0.375 LSb 7-bit 5.5V, I = 450µA W -0.75 +0.5 +0.75 LSb 3.0V, I = 240µA W (Note7) Section2.0 1.8V, I = 150µA W -0.5 ±0.25 +0.5 LSb 50k 8-bit 5.5V, I = 90µA W -0.5 ±0.25 +0.5 LSb 3.0V, I = 48µA W (Note7) Section2.0 1.8V, I = 30µA W -0.375 ±0.25 +0.375 LSb 7-bit 5.5V, I = 90µA W -0.375 ±0.25 +0.375 LSb 3.0V, I = 48µA W (Note7) Section2.0 1.8V, I = 30µA W -0.5 ±0.25 +0.5 LSb 100k 8-bit 5.5V, I = 45µA W -0.5 ±0.25 +0.5 LSb 3.0V, I = 24µA W (Note7) Section2.0 1.8V, I = 15µA W -0.375 ±0.25 +0.375 LSb 7-bit 5.5V, I = 45µA W -0.375 ±0.25 +0.375 LSb 3.0V, I = 24µA W (Note7) Section2.0 1.8V, I = 15µA W Note 1: Resistance is defined as the resistance between terminal A to terminal B. 2: INL and DNL are measured at V with V = V and V = V . W A DD B SS 3: MCP44X1 only. 4: MCP44X2 only, includes V and V . WZSE WFSE 5: Polarity of resistor terminals A, W and B, with respect to each other, is not restricted. 6: This specification by design. 7: Non-linearity is affected by wiper resistance (R ), which changes significantly over voltage and W temperature. 8: The MCP44X1 is externally connected to match the configurations of the MCP44X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network. 11: When HVC/A0 = V , the I current is less due to current into the HVC/A0 pin. See I specification. IHH DD PU  2010 Microchip Technology Inc. DS22267A-page 9

MCP443X/5X AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C  T  +125°C (extended) A DC Characteristics All parameters apply across the specified operating ranges unless noted. V = +2.7V to 5.5V, 5k, 10k, 50k, 100k devices. DD Typical specifications represent values for V = 5.5V, T = +25°C. DD A Parameters Sym Min Typ Max Units Conditions Digital Inputs/Outputs (HVC/A0, A1, SDA, SCL, RESET) Schmitt Trigger V 0.45V — — V All 2.7V  V  5.5V IH DD DD High Input Inputs (Allows 2.7V Digital V with DD Threshold except 5V Analog V ) DD 0.5V — — V SDA 1.8V  V  2.7V DD DD and SCL 0.7V — V V 100kHz DD MAX SDA 0.7V — V V 400kHz DD MAX and 0.7V — V V 1.7MHz DD MAX SCL 0.7V — V V 3.4Mhz DD MAX Schmitt Trigger V — — 0.2V V All inputs except SDA and SCL IL DD Low Input -0.5 — 0.3V V 100kHz DD Threshold SDA -0.5 — 0.3V V 400kHz DD and -0.5 — 0.3V V 1.7MHz DD SCL -0.5 — 0.3V V 3.4Mhz DD Hysteresis of V — 0.1V — V All inputs except SDA and SCL HYS DD Schmitt Trigger N.A. — — V V < 2.0V DD Inputs 100kHz N.A. — — V V  2.0V DD SDA 0.1V — — V V < 2.0V DD and 400kHz DD 0.05V — — V V  2.0V DD SCL DD 0.1V — — V 1.7MHz DD 0.1V — — V 3.4Mhz DD High Voltage Input V 9.0 — 12.5 V Threshold for WiperLock Technology IHHEN Entry Voltage (Note6) High Voltage Input V — — V + V IHHEX DD Exit Voltage 0.8V (Note6) High Voltage Limit V — — 12.5 V Pin can tolerate V or less. MAX MAX (Note6) Output Low V V — 0.2V V V < 2.0V, I = 1mA, OL SS DD DD OL Voltage (SDA) V — 0.4 V V ≥2.0V, I = 3mA SS DD OL Note 1: Resistance is defined as the resistance between terminal A to terminal B. 2: INL and DNL are measured at V with V = V and V = V . W A DD B SS 3: MCP44X1 only. 4: MCP44X2 only, includes V and V . WZSE WFSE 5: Polarity of resistor terminals A, W and B, with respect to each other, is not restricted. 6: This specification by design. 7: Non-linearity is affected by wiper resistance (R ), which changes significantly over voltage and W temperature. 8: The MCP44X1 is externally connected to match the configurations of the MCP44X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network. 11: When HVC/A0 = V , the I current is less due to current into the HVC/A0 pin. See I specification. IHH DD PU DS22267A-page 10  2010 Microchip Technology Inc.

MCP443X/5X AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C  T  +125°C (extended) A DC Characteristics All parameters apply across the specified operating ranges unless noted. V = +2.7V to 5.5V, 5k, 10k, 50k, 100k devices. DD Typical specifications represent values for V = 5.5V, T = +25°C. DD A Parameters Sym Min Typ Max Units Conditions Weak Pull-up I — — 1.75 mA Internal V pull-up, V pull-down, PU DD IHH Current V = 5.5V, V = 12.5V DD HVC — 170 — µA HVC pin, V = 5.5V, V = 3V DD HVC HVC Pull-up / R — 16 — k V = 5.5V, V = 3V HVC DD HVC Pull-down Resistance RESET Pull-up R — 16 — k V = 5.5V, V = 0V RESET DD RESET Resistance Input Leakage I -1 — 1 µA V = V (all pins) and IL IN DD Current V = V (all pins except RESET) IN SS Pin Capacitance C , C — 10 — pF f = 20MHz IN OUT C Capacitance (P ) C — 75 — pF f =1MHz, Code = Full Scale A AW Capacitance (P ) C — 120 — pF f =1MHz, Code = Full Scale w W Capacitance (P ) C — 75 — pF f =1MHz, Code = Full Scale B BW RAM (Wiper, TCON) Value Value Range N 0h — 1FFh hex 8-bit device 0h — 1FFh hex 7-bit device TCON POR/BOR 1FF hex All Terminals connected Setting Power Requirements Power Supply PSS — 0.0015 0.0035 %/% 8-bit V = 2.7V to 5.5V, DD Sensitivity V = 2.7V, Code = 80h A (MCP44X1) — 0.0015 0.0035 %/% 7-bit V = 2.7V to 5.5V, DD V = 2.7V, Code = 40h A Note 1: Resistance is defined as the resistance between terminal A to terminal B. 2: INL and DNL are measured at V with V = V and V = V . W A DD B SS 3: MCP44X1 only. 4: MCP44X2 only, includes V and V . WZSE WFSE 5: Polarity of resistor terminals A, W and B, with respect to each other, is not restricted. 6: This specification by design. 7: Non-linearity is affected by wiper resistance (R ), which changes significantly over voltage and W temperature. 8: The MCP44X1 is externally connected to match the configurations of the MCP44X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network. 11: When HVC/A0 = V , the I current is less due to current into the HVC/A0 pin. See I specification. IHH DD PU  2010 Microchip Technology Inc. DS22267A-page 11

MCP443X/5X 1.1 I2C Mode Timing Waveforms and Requirements RESET tRST tRSTD SCL V V IH IH SDA Wx FIGURE 1-1: RESET Waveforms. TABLE 1-1: RESET TIMING Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C  T  +125°C (extended) A Timing Characteristics All parameters apply across the specified operating ranges unless noted. V = +2.7V to 5.5V, 5k, 10k, 50k, 100k devices. DD Typical specifications represent values for V = 5.5V, T = +25°C. DD A Parameters Sym Min Typ Max Units Conditions RESET pulse width t 50 — — ns RST RESET rising edge t — — 20 ns RSTD normal mode (Wiper driving and I2C interface operational) DS22267A-page 12  2010 Microchip Technology Inc.

MCP443X/5X V IHH HVC/A0 VIH 94 95 VIH or VIL or V IL SCL 91 93 90 92 SDA START STOP Condition Condition FIGURE 1-2: I2C Bus Start/Stop Bits Timing Waveforms. TABLE 1-2: I2C BUS START/STOP BITS REQUIREMENTS I2C AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature –40C  TA  +125C (Extended) Operating Voltage VDD range is described in AC/DC characteristics Param. Symbol Characteristic Min Max Units Conditions No. F Standard Mode 0 100 kHz C = 400pF, 1.8V - 5.5V SCL b Fast Mode 0 400 kHz C = 400pF, 2.7V - 5.5V b High-Speed 1.7 0 1.7 MHz C = 400pF, 4.5V - 5.5V b High-Speed 3.4 0 3.4 MHz C = 100pF, 4.5V - 5.5V b D102 Cb Bus capacitive 100kHz mode — 400 pF loading 400kHz mode — 400 pF 1.7MHz mode — 400 pF 3.4MHz mode — 100 pF 90 TSU:STA START condition 100kHz mode 4700 — ns Only relevant for repeated Setup time 400kHz mode 600 — ns START condition 1.7MHz mode 160 — ns 3.4MHz mode 160 — ns 91 THD:STA START condition 100kHz mode 4000 — ns After this period the first Hold time 400kHz mode 600 — ns clock pulse is generated 1.7MHz mode 160 — ns 3.4MHz mode 160 — ns 92 TSU:STO STOP condition 100kHz mode 4000 — ns Setup time 400kHz mode 600 — ns 1.7MHz mode 160 — ns 3.4MHz mode 160 — ns 93 THD:STO STOP condition 100kHz mode 4000 — ns Hold time 400kHz mode 600 — ns 1.7MHz mode 160 — ns 3.4MHz mode 160 — ns 94 T HVC to SCL Setup time 25 — uS High Voltage Commands HVCSU 95 T SCL to HVC Hold time 25 — uS High Voltage Commands HVCHD  2010 Microchip Technology Inc. DS22267A-page 13

MCP443X/5X 103 100 102 101 SCL 90 106 91 107 92 SDA In 109 109 110 SDA Out FIGURE 1-3: I2C Bus Data Timing. T ABLE 1-3: I2C BUS DATA REQUIREMENTS (SLAVE MODE) I2C AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature –40C  TA  +125C (Extended) Operating Voltage V range is described in AC/DC characteristics DD Param. Sym Characteristic Min Max Units Conditions No. 100 THIGH Clock high time 100kHz mode 4000 — ns 1.8V-5.5V 400kHz mode 600 — ns 2.7V-5.5V 1.7MHz mode 120 ns 4.5V-5.5V 3.4MHz mode 60 — ns 4.5V-5.5V 101 TLOW Clock low time 100kHz mode 4700 — ns 1.8V-5.5V 400kHz mode 1300 — ns 2.7V-5.5V 1.7MHz mode 320 ns 4.5V-5.5V 3.4MHz mode 160 — ns 4.5V-5.5V Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (minimum 300ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 2: A fast-mode (400kHz) I2C-bus device can be used in a standard-mode (100kHz) I2C-bus system, but the requirement t 250ns must then be met. This will automatically be the case if the device does not SU;DAT stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line T max.+t =1000+250=1250ns (according to the standard-mode I2C bus specification) before R SU;DAT the SCL line is released. 3: The MCP44X1/MCP44X2 device must provide a data hold time to bridge the undefined part between V IH and V of the falling edge of the SCL signal. This specification is not a part of the I2C specification, but IL must be tested in order to ensure that the output data will meet the setup and hold specifications for the receiving device. 4: Use Cb in pF for the calculations. 5: Not Tested. 6: A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do not unintentionally create a Start or Stop condition. 7: Ensured by the T 3.4MHz specification test. AA DS22267A-page 14  2010 Microchip Technology Inc.

MCP443X/5X TABLE 1-3: I2C BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED) I2C AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature –40C  TA  +125C (Extended) Operating Voltage V range is described in AC/DC characteristics DD Param. Sym Characteristic Min Max Units Conditions No. 102A (5) TRSCL SCL rise time 100kHz mode — 1000 ns Cb is specified to be from 10 to 400pF (100pF 400kHz mode 20 + 0.1Cb 300 ns maximum for 3.4MHz 1.7MHz mode 20 80 ns mode) 1.7MHz mode 20 160 ns After a Repeated Start condition or an Acknowledge bit 3.4MHz mode 10 40 ns 3.4MHz mode 10 80 ns After a Repeated Start condition or an Acknowledge bit 102B (5) TRSDA SDA rise time 100kHz mode — 1000 ns Cb is specified to be from 10 to 400pF (100pF max 400kHz mode 20 + 0.1Cb 300 ns for 3.4MHz mode) 1.7MHz mode 20 160 ns 3.4MHz mode 10 80 ns 103A (5) TFSCL SCL fall time 100kHz mode — 300 ns Cb is specified to be from 10 to 400pF (100pF max 400kHz mode 20 + 0.1Cb 300 ns for 3.4MHz mode) 1.7MHz mode 20 80 ns 3.4MHz mode 10 40 ns 103B (5) TFSDA SDA fall time 100kHz mode — 300 ns Cb is specified to be from 400kHz mode 20 + 0.1Cb (4) 300 ns 10 to 400pF (100pF max for 3.4MHz mode) 1.7MHz mode 20 160 ns 3.4MHz mode 10 80 ns 106 T Data input hold 100kHz mode 0 — ns 1.8V-5.5V, Note6 HD:DAT time 400kHz mode 0 — ns 2.7V-5.5V, Note6 1.7MHz mode 0 — ns 4.5V-5.5V, Note6 3.4MHz mode 0 — ns 4.5V-5.5V, Note6 Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (minimum 300ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 2: A fast-mode (400kHz) I2C-bus device can be used in a standard-mode (100kHz) I2C-bus system, but the requirement t 250ns must then be met. This will automatically be the case if the device does not SU;DAT stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line T max.+t =1000+250=1250ns (according to the standard-mode I2C bus specification) before R SU;DAT the SCL line is released. 3: The MCP44X1/MCP44X2 device must provide a data hold time to bridge the undefined part between V IH and V of the falling edge of the SCL signal. This specification is not a part of the I2C specification, but IL must be tested in order to ensure that the output data will meet the setup and hold specifications for the receiving device. 4: Use Cb in pF for the calculations. 5: Not Tested. 6: A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do not unintentionally create a Start or Stop condition. 7: Ensured by the T 3.4MHz specification test. AA  2010 Microchip Technology Inc. DS22267A-page 15

MCP443X/5X TABLE 1-3: I2C BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED) I2C AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature –40C  TA  +125C (Extended) Operating Voltage V range is described in AC/DC characteristics DD Param. Sym Characteristic Min Max Units Conditions No. 107 T Data input setup 100kHz mode 250 — ns Note2 SU:DAT time 400kHz mode 100 — ns 1.7MHz mode 10 — ns 3.4MHz mode 10 — ns 109 T Output valid 100kHz mode — 3450 ns Note1 AA from clock 400kHz mode — 900 ns 1.7MHz mode — 150 ns Cb = 100pF, Note1, Note7 — 310 ns Cb = 400pF, Note1, Note5 3.4MHz mode — 150 ns Cb = 100pF, Note1 110 TBUF Bus free time 100kHz mode 4700 — ns Time the bus must be free before a new transmission 400kHz mode 1300 — ns can start 1.7MHz mode N.A. — ns 3.4MHz mode N.A. — ns T Input filter spike 100kHz mode — 50 ns NXP specification states SP suppression N.A. (SDA and SCL) 400kHz mode — 50 ns 1.7MHz mode — 10 ns Spike suppression 3.4MHz mode — 10 ns Spike suppression Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (minimum 300ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 2: A fast-mode (400kHz) I2C-bus device can be used in a standard-mode (100kHz) I2C-bus system, but the requirement t 250ns must then be met. This will automatically be the case if the device does not SU;DAT stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line T max.+t =1000+250=1250ns (according to the standard-mode I2C bus specification) before R SU;DAT the SCL line is released. 3: The MCP44X1/MCP44X2 device must provide a data hold time to bridge the undefined part between V IH and V of the falling edge of the SCL signal. This specification is not a part of the I2C specification, but IL must be tested in order to ensure that the output data will meet the setup and hold specifications for the receiving device. 4: Use Cb in pF for the calculations. 5: Not Tested. 6: A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do not unintentionally create a Start or Stop condition. 7: Ensured by the T 3.4MHz specification test. AA DS22267A-page 16  2010 Microchip Technology Inc.

MCP443X/5X TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, V =+2.7V to +5.5V, V =GND. DD SS Parameters Sym Min Typ Max Units Conditions Temperature Ranges Specified Temperature Range T -40 — +125 °C A Operating Temperature Range T -40 — +125 °C A Storage Temperature Range T -65 — +150 °C A Thermal Package Resistances Thermal Resistance, 14L-TSSOP  — 100 — °C/W JA Thermal Resistance, 20L-QFN  — 43 — °C/W JA Thermal Resistance, 20L-TSSOP  — 90 — °C/W JA  2010 Microchip Technology Inc. DS22267A-page 17

MCP443X/5X NOTES: DS22267A-page 18  2010 Microchip Technology Inc.

MCP443X/5X 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS 550 250 1000 500 800 3.4MHz, 5.5V 450 200 600 400 3.4MHz, 4.5V s) 400 I (µA)DD122335050500000 400kHz, 5.5V 11..77MMHHzz1,,0 540..k55HVVz, 5.5V R (kOhmHVC 110500 IHVC --0242000000I (µA)HVC 100 50 RHVC -600 50 400kHz, 2.7V 100kHz, 2.7V -800 0 0 -1000 -40 0 40 80 120 2 3 4 5 6 7 8 9 10 Temperature (°C) VHVC (V) FIGURE 2-1: Device Current (I ) vs. I2C FIGURE 2-3: HVC/A0 Pull-up/Pull-down DD Frequency (f ) and Ambient Temperature Resistance (R ) and Current (I ) vs. HVC/ SCL HVC HVC (V = 2.7V and 5.5V). A0 Input Voltage (V ) (V = 5.5V). DD HVC DD 3.0 12.0 ) (µA)SHDN 22..05 5.5V hold (V)180..00 5.5V Entry 2.7V Entry Current (I 11..05 2.7V A0 Thres 46..00 5.5V Exit 2.7V Exit y C/ b V d 0.5 H 2.0 n a St 0.0 0.0 -40 0 40 80 120 -40 0 40 80 120 Ambient Temperature (°C) Ambient Temperature (°C) FIGURE 2-2: Device Current (I ) and FIGURE 2-4: HVC/A0 High Input Entry/ SHDN V . (HVC/A0 = V ) vs. Ambient Temperature. Exit Threshold vs. Ambient Temperature and DD DD V . DD  2010 Microchip Technology Inc. DS22267A-page 19

MCP443X/5X Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS 120 0.3 120 1.25 -40C Rw 25C Rw 85C Rw 125C Rw -40C Rw 25C Rw 85C Rw 125C Rw -40C INL 25C INL 85C INL 125C INL -40C INL 25C INL 85C INL 125C INL R) W 100 -40C DNL 25C DNL 85C DNL 125C DNL 0.2 R) W 100 -40C DNL 25C DNL 85C DNL 125C DNL 0.75 er Resistance ((ohms)6800 DNL INL -000.1.1Error (LSb) er Resistance ((ohms)6800 INL -00.2.255Error (LSb) p p DNL Wi 40 125°C85°C -40°C 25°C RW -0.2 Wi 40 125°C85°C 25°C-40°C RW -0.75 20 -0.3 20 -1.25 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 Wiper Setting (decimal) Wiper Setting (decimal) FIGURE 2-5: 5k Pot Mode – R (), FIGURE 2-8: 5k Rheo Mode – R (), W W INL (LSb), DNL (LSb) vs. Wiper Setting and INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (V = 5.5V). Ambient Temperature (V = 5.5V). DD DD 300 300 0.3 -40C Rw 25C Rw 85C Rw 125C Rw -40C Rw 25C Rw 85C Rw 125C Rw -40C INL 25C INL 85C INL 125C INL 6 ) W 260 --4400CC DINNLL 2255CC IDNNLL 8855CC IDNNLL 112255CC IDNNLL 0.2 ) W 260 -40C DNL 25C DNL 85C DNL 125C DNL Wiper Resistance (R(ohms)11120482600000 DNL 85°C12I5N°RLCW --0000.1..21Error (LSb) Wiper Resistance (R(ohms)11126048200000 -40°C RW INL 024 Error (LSb) -40°C 25°C 125°C 85°C25°C DNL 20 -0.3 20 -2 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 Wiper Setting (decimal) Wiper Setting (decimal) FIGURE 2-6: 5k Pot Mode – R (), FIGURE 2-9: 5k Rheo Mode – R (), W W INL (LSb), DNL (LSb) vs. Wiper Setting and INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (V = 3.0V). Ambient Temperature (V = 3.0V). DD DD 0.5 -40C Rw 25C Rw 85C Rw 125C Rw 118 )W 2500 ---444000CCC RIDNwNLL 222555CCC RIDNwNLL 888555CCC RIDNwNLL 111222555CCC RIDNwNLL 0.4 )W 2500 --4400CC IDNNLL 2255CC IDNNLL 8855CC IDNNLL 112255CC IDNNLL 98 per Resistance (R(ohms)112050000000 INL -00000...123.1Error (LSb) per Resistance (R(ohms)112050000000 INL 357888 Error (LSb) Wi 500 DNL -0.2 Wi 500 RW DNL 18 RW 0 -0.3 0 -2 0 64 128 192 256 0 64 128 192 256 Wiper Setting (decimal) Wiper Setting (decimal) Note: See Appendix B: for additional Note: See Appendix B: for additional information of R resistance variation information of R resistance variation W W characteristics for V > 2.7V. characteristics for V > 2.7V. DD DD FIGURE 2-7: 5k Pot Mode – R (), FIGURE 2-10: 5k Rheo Mode – R (), W W INL (LSb), DNL (LSb) vs. Wiper Setting and INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (V = 1.8V). Ambient Temperature (V = 1.8V, I = 260 µA). DD DD W DS22267A-page 20  2010 Microchip Technology Inc.

MCP443X/5X Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS 5300 6000 R) AB 5250 5000 e ( sistanchms) 5200 2.7V ance ((cid:2))34000000 nal Re(O 5150 Resist2000 -40C mi 5100 +25C No 5.5V 1000 +85C +125C 5050 0 -40 0 40 80 120 0 32 64 96 128 160 192 224 256 Ambient Temperature (°C) Wiper Code FIGURE 2-11: 5k – Nominal Resistance FIGURE 2-12: 5k – R () vs. Wiper WB (R ) () vs. Ambient Temperature and V . Setting and Ambient Temperature AB DD (V = 5.5V, I = 190µA). DD W 6000 5000 (cid:2))4000 e ( c n3000 a st si Re2000 -40C +25C 1000 +85C +125C 0 0 32 64 96 128 160 192 224 256 Wiper Code FIGURE 2-13: 5k – R () vs. Wiper WB Setting and Ambient Temperature (V = 3.0V, I = 190µA). DD W 7000 6000 5000 (cid:2)) e (4000 c n a st3000 si Re2000 -40C +25C 1000 +85C +125C 0 0 32 64 96 128 160 192 224 256 Wiper Code Note: See Appendix B: for additional information of R resistance variation W characteristics for V > 2.7V. DD FIGURE 2-14: 5k – R () vs. Wiper WB Setting and Ambient Temperature (V = 1.8V, I = 190 µA). DD W  2010 Microchip Technology Inc. DS22267A-page 21

MCP443X/5X Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS 2.50% 54 -40C +25C 52 CH0 CH1 1.50% +85C CH2 CH3 +125C 50 Error %-00..5500%% PPM / °C4468 44 -1.50% 42 40 -2.50% 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 Wiper Code Wiper Code FIGURE 2-15: 5k – Worst Case RBW FIGURE 2-18: 5k – RWB PPM/°C vs. from Average RBW (RBW0-RBW3) Error (%) vs. Wiper Setting. (RBW(code=n, 125°C)-RBW(code=n, - Wiper Setting and Temperature 40°C) )/RBW(code = 256, 25°C)/165°C * 1,000,000) (VDD = 5.5V, IW = 190µA). (VDD = 5.5V, IW = 190µA). 2.50% 100 -40C +25C 95 CH0 CH1 1.50% +85C CH2 CH3 90 +125C 85 0.50% C or % M / ° 80 Err-0.50% PP 75 70 -1.50% 65 -2.50% 60 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 Wiper Code Wiper Code FIGURE 2-16: 5k – Worst Case RBW FIGURE 2-19: 5k – RWB PPM/°C vs. from Average RBW (RBW0-RBW3) Error (%) vs. Wiper Setting. (RBW(code=n, 125°C)-RBW(code=n, - Wiper Setting and Temperature 40°C) )/RBW(code = 256, 25°C)/165°C * 1,000,000) (VDD = 3.0V, IW = 190µA). (VDD = 3.0V, IW = 190µA). 2.00% 500 1.00% 0 0.00% -1.00% C -500 Error %--32..0000%% PPM / °-1000 -4.00% -40C -5.00% +25C -1500 CH0 CH1 -6.00% +85C CH2 CH3 +125C -7.00% -2000 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 Wiper Code Wiper Code Note: See Appendix B: for additional Note: See Appendix B: for additional information of RW resistance variation information of RW resistance variation characteristics for VDD > 2.7V. characteristics for VDD > 2.7V. FIGURE 2-17: 5k – Worst Case R FIGURE 2-20: 5k – R PPM/°C vs. BW WB from Average R (R -R ) Error (%) vs. Wiper Setting. (R -R BW BW0 BW3 BW(code=n, 125°C) BW(code=n, - Wiper Setting and Temperature )/R /165°C * 1,000,000) 40°C) BW(code = 256, 25°C) (V = 1.8V, I = 190 µA). (V = 1.8V, I = 190 µA). DD W DD W DS22267A-page 22  2010 Microchip Technology Inc.

MCP443X/5X Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS FIGURE 2-21: 5k – Low-Voltage FIGURE 2-24: 5k – Low-Voltage Decrement Wiper Settling Time (V = 2.7V) Increment Wiper Settling Time (V = 2.7V) DD DD (1µs/Div). (1µs/Div). FIGURE 2-22: 5k – Low-Voltage FIGURE 2-25: 5k – Low-Voltage Decrement Wiper Settling Time (V = 5.5V) Increment Wiper Settling Time (V = 5.5V) DD DD (1µs/Div). (1µs/Div). FIGURE 2-23: 5k – Power-Up Wiper Response Time (20ms/Div).  2010 Microchip Technology Inc. DS22267A-page 23

MCP443X/5X Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS 120 0.3 120 1 -40C Rw 25C Rw 85C Rw 125C Rw -40C Rw 25C Rw 85C Rw 125C Rw -40C INL 25C INL 85C INL 125C INL -40C INL 25C INL 85C INL 125C INL ) W 100 -40C DNL 25C DNL 85C DNL 125C DNL 0.2 ) W 100 -40C DNL 25C DNL 85C DNL 125C DNL R R 0.5 Wiper Resistance ((ohms) 468000 125°C 85D°CN2L5°C -40°C INL RW --0000.1..21Error (LSb) Wiper Resistance ((ohms)468000 125°C85°C 25°C -40°ICNL RW DNL -00.5Error (LSb) 20 -0.3 20 -1 0 25 50 75 100125150175200225250 0 32 64 96 128 160 192 224 256 Wiper Setting (decimal) Wiper Setting (decimal) FIGURE 2-26: 10k Pot Mode – R (), FIGURE 2-29: 10k Rheo Mode – R (), W W INL (LSb), DNL (LSb) vs. Wiper Setting and INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (V = 5.5V). Ambient Temperature (V = 5.5V). DD DD 300 4 300 0.3 -40C Rw 25C Rw 85C Rw 125C Rw -40C Rw 25C Rw 85C Rw 125C Rw -40C INL 25C INL 85C INL 125C INL ) W 260 --4400CC DINNLL 2255CC IDNNLL 8855CC IDNNLL 112255CC IDNNLL 0.2 ) W 260 -40C DNL 25C DNL 85C DNL 125C DNL 3 R R INL Wiper Resistance ((ohms)11120482600000 DNL -40°C IRNWL --0000.1..21Error (LSb) Wiper Resistance ((ohms)11120482600000 -40°C DNL RW -0121 Error (LSb) 125°C 85°C 25°C 125°C 85°C 25°C 20 -0.3 20 -2 0 32 64 96 128 160 192 224 256 0 25 50 75 100125150175200225250 Wiper Setting (decimal) Wiper Setting (decimal) FIGURE 2-27: 10k Pot Mode – R (), FIGURE 2-30: 10k Rheo Mode – R (), W W INL (LSb), DNL (LSb) vs. Wiper Setting and INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (V = 3.0V). Ambient Temperature (V = 3.0V). DD DD 0.6 98 4000 -40C Rw 25C Rw 85C Rw 125C Rw 4000 -40C Rw 25C Rw 85C Rw -40C INL 25C INL 85C INL 125C INL 0.5 18255CC I NRLw -14205CC IINNLL 2-450CC I NDLNL 88 e 3500 -40C DNL 25C DNL 85C DNL 125C DNL 0.4 R)W 3500 25C DNL 85C DNL 125C DNL 78 Wiper Resistanc(R)(ohms)W11223050500000000000 DNL INL -00000...123.1Error (LSb) per Resistance ((ohms) 11223050500000000000 INL 2345688888 Error (LSb) 500 RW -0.2 Wi 500 RW DNL 818 0 -0.3 0 -2 0 64 128 192 256 0 64 128 192 256 Wiper Setting (decimal) Wiper Setting (decimal) Note: See Appendix B: for additional Note: See Appendix B: for additional information of RW resistance variation information of RW resistance variation characteristics for VDD > 2.7V. characteristics for VDD > 2.7V. FIGURE 2-28: 10k Pot Mode – R (), FIGURE 2-31: 10k Rheo Mode – R (), W W INL (LSb), DNL (LSb) vs. Wiper Setting and INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (V = 1.8V). Ambient Temperature (V = 1.8V, I = 125 µA). DD DD W DS22267A-page 24  2010 Microchip Technology Inc.

MCP443X/5X Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS 10250 12000 ) B RA 10200 10000 al Resistance ((Ohms) 1100110500 2.7V esistance ((cid:2)) 468000000000 -40C n 5.5V R mi 10050 +25C o 2000 +85C N +125C 10000 0 -40 0 40 80 120 0 32 64 96 128 160 192 224 256 Ambient Temperature (°C) Wiper Code FIGURE 2-32: 10k – Nominal Resistance FIGURE 2-33: 10k – R () vs. Wiper WB (R ) () vs. Ambient Temperature and V . Setting and Ambient Temperature AB DD (V = 5.5V, I = 150µA). DD W 12000 10000 (cid:2)) 8000 e ( c n 6000 a st Resi 4000 -40C +25C 2000 +85C +125C 0 0 32 64 96 128 160 192 224 256 Wiper Code FIGURE 2-34: 10k – R () vs. Wiper WB Setting and Ambient Temperature (V = 3.0V, I = 150µA). DD W 12000 10000 (cid:2)) 8000 e ( c n 6000 a st esi 4000 -40C R +25C 2000 +85C +125C 0 0 32 64 96 128 160 192 224 256 Wiper Code Note: See Appendix B: for additional information of R resistance variation W characteristics for V > 2.7V. DD FIGURE 2-35: 10k – R () vs. Wiper WB Setting and Ambient Temperature (V = 1.8V, I = 150 µA). DD W  2010 Microchip Technology Inc. DS22267A-page 25

MCP443X/5X Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS 1.50% 50 -40C +25C 1.00% +85C +125C 45 40 0.50% C35 or % 0.00% M / °30 Err PP25 -0.50% 20 CH0 CH1 -1.00% 15 CH2 CH3 -1.50% 10 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 Wiper Code Wiper Code FIGURE 2-36: 10k – Worst Case RBW FIGURE 2-39: 10k – RWB PPM/°C vs. from Average RBW (RBW0-RBW3) Error (%) vs. Wiper Setting. (RBW(code=n, 125°C)-RBW(code=n, - Wiper Setting and Temperature 40°C) )/RBW(code = 256, 25°C)/165°C * 1,000,000) (VDD = 5.5V, IW = 150µA). (VDD = 5.5V, IW = 150µA). 1.50% 60 -40C +25C 55 1.00% +85C +125C 50 0.50% C45 or % 0.00% M / °40 Err PP35 -0.50% 30 CH0 CH1 -1.00% 25 CH2 CH3 20 -1.50% 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 Wiper Code Wiper Code FIGURE 2-37: 10k – Worst Case RBW FIGURE 2-40: 10k – RWB PPM/°C vs. from Average RBW (RBW0-RBW3) Error (%) vs. Wiper Setting. (RBW(code=n, 125°C)-RBW(code=n, - Wiper Setting and Temperature 40°C) )/RBW(code = 256, 25°C)/165°C * 1,000,000) (VDD = 3.0V, IW = 150µA). (VDD = 3.0V, IW = 150µA). 1.50% 200 -40C +25C 0 1.00% +85C +125C -200 0.50% C -400 or % 0.00% M / ° -600 Err PP -800 -0.50% -1000 CH0 CH1 -1.00% -1200 CH2 CH3 -1400 -1.50% 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 Wiper Code Wiper Code Note: See Appendix B: for additional Note: See Appendix B: for additional information of RW resistance variation information of RW resistance variation characteristics for VDD > 2.7V. characteristics for VDD > 2.7V. FIGURE 2-38: 10k – Worst Case RBW FIGURE 2-41: 10k – RWB PPM/°C vs. from Average RBW (RBW0-RBW3) Error (%) vs. Wiper Setting. (RBW(code=n, 125°C)-RBW(code=n, - Wiper Setting and Temperature 40°C) )/RBW(code = 256, 25°C)/165°C * 1,000,000) (VDD = 1.8V, IW = 150 µA). (VDD = 1.8V, IW = 150 µA). DS22267A-page 26  2010 Microchip Technology Inc.

MCP443X/5X Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS FIGURE 2-42: 10k – Low-Voltage FIGURE 2-44: 10k – Low-Voltage Decrement Wiper Settling Time (V = 2.7V) Increment Wiper Settling Time (V = 2.7V) DD DD (1µs/Div). (1µs/Div). FIGURE 2-43: 10k – Low-Voltage FIGURE 2-45: 10k – Low-Voltage Decrement Wiper Settling Time (V = 5.5V) Increment Wiper Settling Time (V = 5.5V) DD DD (1µs/Div). (1µs/Div).  2010 Microchip Technology Inc. DS22267A-page 27

MCP443X/5X Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS 120 0.3 120 0.3 -40C Rw 25C Rw 85C Rw 125C Rw -40C Rw 25C Rw 85C Rw 125C Rw -40C INL 25C INL 85C INL 125C INL -40C INL 25C INL 85C INL 125C INL )W 100 -40C DNL 25C DNL 85C DNL 125C DNL 0.2 )W 100 -40C DNL 25C DNL 85C DNL 125C DNL 0.2 R R INL er Resistance ((ohms)6800 DNL INL -000.1.1Error (LSb) er Resistance ((ohms)6800 DNL -000.1.1Error (LSb) Wip 40 25°C -40°C RW -0.2 Wip 40 125°C 85°C 25°C -40°C RW -0.2 125°C 85°C 20 -0.3 20 -0.3 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 Wiper Setting (decimal) Wiper Setting (decimal) FIGURE 2-46: 50k Pot Mode – R (), FIGURE 2-49: 50k Rheo Mode – R (), W W INL (LSb), DNL (LSb) vs. Wiper Setting and INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (V = 5.5V). Ambient Temperature (V = 5.5V). DD DD 300 1 300 0.3 -40C Rw 25C Rw 85C Rw 125C Rw per Resistance (R)W(ohms)111220482600000 ---444000CCC D DRINNNwLLL 222555CCC RIDNwNLL 888IRN555CCCWL RIDNwNLL 111222555CCC RIDNwNLL -0000..12.1Error (LSb) Wiper Resistance (R) W(ohms)111220482600000 --4400CCD IDNNNLLL 2255CC IDNNILNLL 88R55CCW IDNNLL 112255CC DINNLL --000000...257..52555 Error (LSb) Wi 60 -40°C -0.2 60 -40°C -0.75 125°C 85°C 25°C 125°C 85°C 25°C 20 -0.3 20 -1 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 Wiper Setting (decimal) Wiper Setting (decimal) FIGURE 2-47: 50k Pot Mode – R (), FIGURE 2-50: 50k Rheo Mode – R (), W W INL (LSb), DNL (LSb) vs. Wiper Setting and INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (V = 3.0V). Ambient Temperature (V = 3.0V). DD DD 1145000000 -40C Rw 25C Rw 85C Rw 125C Rw 0.5 1145000000 --4400CC RINwL 2255CC RINwL 8855CC RINwL 112255CC RINwL 7738..55 Wiper Resistance (R)W(ohms)111134567890123000000000000000000000000000000000 --4400CC IDNNLL DN2255LCCI NIDNNLLL 8855CC IDNNLL 112255CC IDNNLL ---00000000....1234...321Error (LSb) Wiper Resistance (Rw) (ohms)111101233456789000000000000000000000000000000000 -40C DNL 25C DNL 85C DNLIRNWL125C DNL 112233445566383838383838............555555555555 Error (LSb) 12000000 RW -0.4 12000000 DNL 38..55 0 -0.5 0 -1.5 0 64 128 192 256 0 64 128 192 256 Wiper Setting (decimal) Wiper Setting (decimal) Note: See Appendix B: for additional Note: See Appendix B: for additional information of R resistance variation information of R resistance variation W W characteristics for V > 2.7V. characteristics for V > 2.7V. DD DD FIGURE 2-48: 50k Pot Mode – RW (), FIGURE 2-51: 50k Rheo Mode – RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 1.8V). Ambient Temperature (VDD = 1.8V, IW = 25 µA). DS22267A-page 28  2010 Microchip Technology Inc.

MCP443X/5X Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS 50800 60000 ) B 50600 RA 50000 e ( 50400 nc (cid:2))40000 nal Resista(Ohms) 455900802000000 5.5V 2.7V Resistance (2300000000 -40C mi +25C o 49600 10000 +85C N +125C 49400 0 -40 0 40 80 120 0 32 64 96 128 160 192 224 256 Ambient Temperature (°C) Wiper Code FIGURE 2-52: 50k – Nominal Resistance FIGURE 2-53: 50k – R () vs. Wiper WB (RAB) () vs. Ambient Temperature and VDD. Setting and Ambient Temperature (V = 5.5V, I = 90µA). DD W 60000 50000 (cid:2))40000 e ( c n30000 a st esi20000 -40C R +25C 10000 +85C +125C 0 0 32 64 96 128 160 192 224 256 Wiper Code FIGURE 2-54: 50k – R () vs. Wiper WB Setting and Ambient Temperature (V = 3.0V, I = 48µA). DD W 60000 50000 (cid:2))40000 e ( c n30000 a st esi20000 -40C R +25C 10000 +85C +125C 0 0 32 64 96 128 160 192 224 256 Wiper Code Note: See Appendix B: for additional information of R resistance variation W characteristics for V > 2.7V. DD FIGURE 2-55: 50k – R () vs. Wiper WB Setting and Ambient Temperature (V = 1.8V, I = 30 µA). DD W  2010 Microchip Technology Inc. DS22267A-page 29

MCP443X/5X Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS 7.00% 7 -40C +25C 6 6.00% +85C +125C 5 5.00% 4 4.00% C 3 or % 3.00% M / ° 2 Err 2.00% PP 1 0 1.00% -1 CH0 CH1 0.00% -2 CH2 CH3 -1.00% -3 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 Wiper Code Wiper Code FIGURE 2-56: 50k – Worst Case RBW FIGURE 2-59: 50k – RWB PPM/°C vs. from Average RBW (RBW0-RBW3) Error (%) vs. Wiper Setting. (RBW(code=n, 125°C)-RBW(code=n, - Wiper Setting and Temperature 40°C) )/RBW(code = 256, 25°C)/165°C * 1,000,000) (VDD = 5.5V, IW = 90µA). (VDD = 5.5V, IW = 90µA). 4.00% 12 -40C +25C 10 3.00% +85C +125C 8 2.00% C Error % 1.00% PPM / ° 46 0.00% 2 CH0 CH1 -1.00% 0 CH2 CH3 -2 -2.00% 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 Wiper Code Wiper Code FIGURE 2-57: 50k – Worst Case RBW FIGURE 2-60: 50k – RWB PPM/°C vs. from Average RBW (RBW0-RBW3) Error (%) vs. Wiper Setting. (RBW(code=n, 125°C)-RBW(code=n, - Wiper Setting and Temperature 40°C) )/RBW(code = 256, 25°C)/165°C * 1,000,000) (VDD = 3.0V, IW = 48µA). (VDD = 3.0V, IW = 48µA). 3.50% 200 -40C +25C 0 +85C +125C 2.50% -200 C -400 or % 1.50% M / ° -600 Err 0.50% PP -800 -1000 -0.50% CH0 CH1 -1200 CH2 CH3 -1400 -1.50% 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 Wiper Code Wiper Code Note: See Appendix B: for additional Note: See Appendix B: for additional information of RW resistance variation information of RW resistance variation characteristics for VDD > 2.7V. characteristics for VDD > 2.7V. FIGURE 2-58: 50k – Worst Case RBW FIGURE 2-61: 50k – RWB PPM/°C vs. from Average RBW (RBW0-RBW3) Error (%) vs. Wiper Setting. (RBW(code=n, 125°C)-RBW(code=n, - Wiper Setting and Temperature 40°C) )/RBW(code = 256, 25°C)/165°C * 1,000,000) (VDD = 1.8V, IW = 30 µA). (VDD = 1.8V, IW = 30 µA). DS22267A-page 30  2010 Microchip Technology Inc.

MCP443X/5X Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS FIGURE 2-62: 50k – Low-Voltage FIGURE 2-64: 50k – Low-Voltage Decrement Wiper Settling Time (V = 2.7V) Increment Wiper Settling Time (V = 2.7V) DD DD (1µs/Div). (1µs/Div). FIGURE 2-63: 50k – Low-Voltage FIGURE 2-65: 50k – Low-Voltage Decrement Wiper Settling Time (V = 5.5V) Increment Wiper Settling Time (V = 5.5V) DD DD (1µs/Div). (1µs/Div).  2010 Microchip Technology Inc. DS22267A-page 31

MCP443X/5X Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS 120 0.2 120 0.3 -40C Rw 25C Rw 85C Rw 125C Rw -40C Rw 25C Rw 85C Rw 125C Rw -40C INL 25C INL 85C INL 125C INL -40C INL 25C INL 85C INL 125C INL ) W 100 -40C DNL 25C DNL 85C DNL 125C DNL ) W 100 -40C DNL 25C DNL 85C DNL 125C DNL 0.2 R 0.1 R INL per Resistance ((ohms)6800 DNL INL -00.1Error (LSb) per Resistance ((ohms)6800 DNL -000.1.1Error (LSb) Wi 40 25°C -40°C RW Wi 40 125°C 85°C 25°C-40°C RW -0.2 125°C 85°C 20 -0.2 20 -0.3 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 Wiper Setting (decimal) Wiper Setting (decimal) FIGURE 2-66: 100k Pot Mode – R (), FIGURE 2-69: 100k Rheo Mode – R W W INL (LSb), DNL (LSb) vs. Wiper Setting and (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (V = 5.5V). Ambient Temperature (V = 5.5V). DD DD 300 0.6 300 0.2 -40C Rw 25C Rw 85C Rw 125C Rw -40C Rw 25C Rw 85C Rw 125C Rw -40C INL 25C INL 85C INL 125C INL per Resistance (R) W(ohms)111220482600000 --4400CC IDDNNLNLL 2255CC IDNNLL I88RN55CCWL IDNNLL 112255CC DINNLL --000000...011..10555Error (LSb) per Resistance (Rw) (ohms)111220482600000 -4D0NC LDNL 25C DNINLL 85CR DWNL 125C DNL -0000..24.2 Error (LSb) Wi 60 -40°C -0.15 Wi 60 -40°C -0.4 125°C85°C 25°C 125°C 85°C 25°C 20 -0.2 20 -0.6 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 Wiper Setting (decimal) Wiper Setting (decimal) FIGURE 2-67: 100k Pot Mode – R (), FIGURE 2-70: 100k Rheo Mode – R W W INL (LSb), DNL (LSb) vs. Wiper Setting and (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (V = 3.0V). Ambient Temperature (V = 3.0V). DD DD 0.35 -40C Rw 25C Rw 85C Rw 125C Rw 59 -40C Rw 25C Rw 85C Rw 125C Rw -40C INL 25C INL 85C INL 125C INL 54 )W 25000 --4400CC IDNNLL 2255CC IDNNLL 8855CC IDNNLL 112255CC IDNNLL 0.25 )W 25000 -40C DNL 25C DNL 85C DNL 125C DNL 49 per Resistance (R(ohms)112050000000000 DNL --0000..01..105555Error (LSb) per Resistance (R(ohms)112050000000000 RINWL 11223344949494 Error (LSb) Wi 5000 INL -0.25 Wi 5000 9 RW DNL 4 0 -0.35 0 -1 0 64 128 192 256 0 64 128 192 256 Wiper Setting (decimal) Wiper Setting (decimal) Note: See Appendix B: for additional Note: See Appendix B: for additional information of R resistance variation information of R resistance variation W W characteristics for V > 2.7V. characteristics for V > 2.7V. DD DD FIGURE 2-68: 100k Pot Mode – R (), FIGURE 2-71: 100k Rheo Mode – R W W INL (LSb), DNL (LSb) vs. Wiper Setting and (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (V = 1.8V). Ambient Temperature (V = 1.8V, I = 10 µA). DD DD W DS22267A-page 32  2010 Microchip Technology Inc.

MCP443X/5X Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS 101500 120000 ) B RA 101000 100000 e ( al Resistanc(Ohms) 110000050000 2.7V esistance ((cid:2)) 468000000000000 -40C min 99500 5.5V R +25C o 20000 +85C N +125C 99000 0 -40 0 40 80 120 0 32 64 96 128 160 192 224 256 Ambient Temperature (°C) Wiper Code FIGURE 2-72: 100k – Nominal FIGURE 2-73: 100k – R () vs. Wiper WB Resistance (RAB) () vs. Ambient Temperature Setting and Ambient Temperature and VDD. (VDD = 5.5V, IW = 45µA). 120000 100000 (cid:2)) 80000 e ( c n 60000 a st esi 40000 -40C R +25C 20000 +85C +125C 0 0 32 64 96 128 160 192 224 256 Wiper Code FIGURE 2-74: 100k – R () vs. Wiper WB Setting and Ambient Temperature (V = 3.0V, I = 24µA). DD W 120000 100000 (cid:2)) 80000 e ( c n 60000 a st esi 40000 -40C R +25C 20000 +85C +125C 0 0 32 64 96 128 160 192 224 256 Wiper Code Note: See Appendix B: for additional information of R resistance variation W characteristics for V > 2.7V. DD FIGURE 2-75: 100k – R () vs. Wiper WB Setting and Ambient Temperature (V = 1.8V, I = 15 µA). DD W  2010 Microchip Technology Inc. DS22267A-page 33

MCP443X/5X Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS 14.00% 16 13.00% -40C +25C 12.00% +85C +125C 14 11.00% 10.00% 12 89..0000%% C10 Error % 567...000000%%% PPM / ° 68 4.00% 3.00% 4 CH0 CH1 2.00% 1.00% 2 CH2 CH3 0.00% 0 -1.00% 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 Wiper Code Wiper Code FIGURE 2-76: 100k – Worst Case RBW FIGURE 2-79: 100k – RWB PPM/°C vs. from Average RBW (RBW0-RBW3) Error (%) vs. Wiper Setting. (RBW(code=n, 125°C)-RBW(code=n, - Wiper Setting and Temperature 40°C) )/RBW(code = 256, 25°C)/165°C * 1,000,000) (VDD = 5.5V, IW = 45µA). (VDD = 5.5V, IW = 45µA). 7.00% 18 -40C +25C 16 6.00% +85C +125C 14 5.00% 12 4.00% C Error % 23..0000%% PPM / °1680 1.00% 4 CH0 CH1 0.00% 2 CH2 CH3 -1.00% 0 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 Wiper Code Wiper Code FIGURE 2-77: 100k – Worst Case RBW FIGURE 2-80: 100k – RWB PPM/°C vs. from Average RBW (RBW0-RBW3) Error (%) vs. Wiper Setting. (RBW(code=n, 125°C)-RBW(code=n, - Wiper Setting and Temperature 40°C) )/RBW(code = 256, 25°C)/165°C * 1,000,000) (VDD = 3.0V, IW = 24µA). (VDD = 3.0V, IW = 24µA). 6.00% 200 -40C +25C 5.00% +85C +125C 0 4.00% -200 C Error % 23..0000%% PPM / ° --640000 -800 1.00% CH0 CH1 -1000 0.00% CH2 CH3 -1200 -1.00% 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 Wiper Code Wiper Code Note: See Appendix B: for additional Note: See Appendix B: for additional information of RW resistance variation information of RW resistance variation characteristics for VDD > 2.7V. characteristics for VDD > 2.7V. FIGURE 2-78: 100k – Worst Case RBW FIGURE 2-81: 100k – RWB PPM/°C vs. from Average RBW (RBW0-RBW3) Error (%) vs. Wiper Setting. (RBW(code=n, 125°C)-RBW(code=n, - Wiper Setting and Temperature 40°C) )/RBW(code = 256, 25°C)/165°C * 1,000,000) (VDD = 1.8V, IW = 15 µA). (VDD = 1.8V, IW = 15 µA). DS22267A-page 34  2010 Microchip Technology Inc.

MCP443X/5X Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS FIGURE 2-82: 100k – Low-Voltage FIGURE 2-84: 100k – Low-Voltage Decrement Wiper Settling Time (V = 2.7V) Increment Wiper Settling Time (V = 2.7V) DD DD (1µs/Div). (1µs/Div). FIGURE 2-83: 100k – Low-Voltage FIGURE 2-85: 100k – Low-Voltage Decrement Wiper Settling Time (V = 5.5V) Increment Wiper Settling Time (V = 5.5V) DD DD (1µs/Div). (1µs/Div).  2010 Microchip Technology Inc. DS22267A-page 35

MCP443X/5X Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS 4 230 3.5 210 2.7V 5.5V 190 3 170 V) mV) 150 V (IH 2.5 (OL 130 5.5V 2 V 110 2.7V 90 1.5 70 1 50 -40 0 40 80 120 -40 0 40 80 120 Temperature (°C) Temperature (°C) FIGURE 2-86: V (SDA, SCL) vs. V and FIGURE 2-88: V (SDA) vs. V and IH DD OL DD Temperature. Temperature (I = 3mA). OL 2 5.5V V) V (IL 1.5 2.7V 1 -40 0 40 80 120 Temperature (°C) FIGURE 2-87: V (SDA, SCL) vs. V and IL DD Temperature. DS22267A-page 36  2010 Microchip Technology Inc.

MCP443X/5X Note: Unless otherwise indicated, T = +25°C, V =5V, V = 0V. A DD SS 2.1 Test Circuits 1.6 1.4 1.2 +5V 1.0 V) A V (DD 00..68 VIN W + VOUT 0.4 B - Offset 0.2 GND 0.0 -40 0 40 80 120 2.5V DC Temperature (°C) FIGURE 2-89: POR/BOR Trip point vs. V DD and Temperature. FIGURE 2-90: -3db Gain vs. Frequency Test. floating V A A V W W I W R = V /I BW W W B R = (V -V )/I V W W A W B FIGURE 2-91: R and R Measurement. BW W  2010 Microchip Technology Inc. DS22267A-page 37

MCP443X/5X NOTES: DS22267A-page 38  2010 Microchip Technology Inc.

MCP443X/5X 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table3-1. Additional descriptions of the device pins follows. TABLE 3-1: PINOUT DESCRIPTION FOR THE MCP443X/5X Pin Weak Pull-up/ TSSOP QFN Standard Function Buffer down Symbol I/O 14L 20L 20L Type (Note1) — 1 19 P3A A Analog No Potentiometer 3 Terminal A 1 2 20 P3W A Analog No Potentiometer 3 Wiper Terminal 2 3 1 P3B A Analog No Potentiometer 3 Terminal B 3 4 2 HVC/A0 I HV w/ST “smart” High Voltage Command / I2C Address 0 4 5 3 SCL I HV w/ST No I2C Clock Input 5 6 4 SDA I HV w/ST No I2C Serial Data I/O. Open Drain output 6 7 5 VSS — P — Ground 7 8 6 P1B A Analog No Potentiometer 1 Terminal B 8 9 7 P1W A Analog No Potentiometer 1 Wiper Terminal — 10 8 P1A A Analog No Potentiometer 1 Terminal A — 11 9 P0A A Analog No Potentiometer 0 Terminal A 9 12 10 P0W A Analog No Potentiometer 0 Wiper Terminal 10 13 11 P0B A Analog No Potentiometer 0 Terminal B — 14 12 NC I — — No Connect — 15 13 RESET I HV w/ST Yes Hardware Reset Pin 11 16 14 A1 I HV w/ST “smart” I2C Address 1 12 17 15 VDD — P — Positive Power Supply Input 13 18 16 P2B A Analog No Potentiometer 2 Terminal B 14 19 17 P2W A Analog No Potentiometer 2 Wiper Terminal — 20 18 P2A A Analog No Potentiometer 2 Terminal A — — 21 EP — — — Exposed Pad. (Note2) Legend: HV w/ST = High Voltage tolerant input (with Schmidtt trigger input) A = Analog pins (Potentiometer terminals) I = digital input (high Z) O = digital output I/O = Input / Output P = Power Note 1: The pin’s “smart” pull-up shuts off while the pin is forced low. This is done to reduce the standby and shut-down current. 2: The QFN package has a contact on the bottom of the package. This contact is conductively connected to the die substrate, and therefore should be unconnected or connected to the same ground as the device’s V pin. SS  2010 Microchip Technology Inc. DS22267A-page 39

MCP443X/5X 3.1 High Voltage Command / 3.7 Potentiometer Terminal A Address 0 (HVC/A0) The terminal A pin is available on the MCP44X1 The HVC/A0 pin is the Address 0 input for the I2C devices, and is connected to the internal interface as well as the High Voltage Command pin. At potentiometer’s terminal A. the device’s POR/BOR the value of the A0 address bit The potentiometer’s terminal A is the fixed connection is latched. This input along with the A1 pin completes to the Full Scale wiper value of the digital the device address. This allows up to 4 MCP44XX potentiometer. This corresponds to a wiper value of devices to be on a single I2C bus. 0x100 for 8-bit devices or 0x80 for 7-bit devices. During normal operation, the voltage on this pin The terminal A pin does not have a polarity relative to determines whether the I2C command is a normal the terminal W or B pins. The terminal A pin can command or a High Voltage command (when HVC/A0 support both positive and negative current. The voltage = VIHH). on terminal A must be between VSS and VDD. The terminal A pin is not available on the MCP44X2 3.2 Serial Clock (SCL) devices, and the internally terminal A signal is floating. The SCL pin is the serial interfaces Serial Clock pin. MCP44X1 devices have four terminal A pins, one for This pin is connected to the Host Controllers SCL pin. each resistor network. Terminal A is not available on The MCP44XX is a slave device, so its SCL pin accepts the MCP44X2 devices. only external clock signals. 3.8 Not Connected (NC) 3.3 Serial Data (SDA) The NC pin is not used. The SDA pin is the serial interfaces Serial Data pin. This pin is connected to the Host Controllers SDA pin. 3.9 Reset (RESET) The SDA pin is an open-drain N-channel driver. The RESET pin is used to force the device into the 3.4 Ground (V ) POR/BOR state. SS The VSS pin is the device ground reference. 3.10 Address 1 (A1) 3.5 Potentiometer Terminal B The A1 pin is the I2C interface’s Address 1 pin. Along with the A0 pins, up to 4 MCP44XX devices can be on The terminal B pin is connected to the internal a single I2C bus. potentiometer’s terminal B. The potentiometer’s terminal B is the fixed connection 3.11 Positive Power Supply Input (VDD) to the Zero Scale wiper value of the digital The V pin is the device’s positive power supply input. potentiometer. This corresponds to a wiper value of DD The input power supply is relative to V . 0x00 for both 7-bit and 8-bit devices. SS While the device V < V (2.7V), the electrical The terminal B pin does not have a polarity relative to DD min performance of the device may not meet the data sheet the terminal W or A pins. The terminal B pin can specifications. support both positive and negative current. The voltage on terminal B must be between V and V . SS DD 3.12 No Connect (NC) MCP44XX devices have four terminal B pins, one for each resistor network. These pins should be either connected to V or V . DD SS 3.6 Potentiometer Wiper (W) Terminal 3.13 Exposed Pad (EP) The terminal W pin is connected to the internal This pad is conductively connected to the device's potentiometer’s terminal W (the wiper). The wiper substrate. This pad should be tied to the same potential terminal is the adjustable terminal of the digital as the V pin (or left unconnected). This pad could be SS potentiometer. The terminal W pin does not have a used to assist as a heat sink for the device when polarity relative to terminals A or B pins. The terminal connected to a PCB heat sink. W pin can support both positive and negative current. The voltage on terminal W must be between V and SS V . DD MCP44XX devices have four terminal W pins, one for each resistor network. DS22267A-page 40  2010 Microchip Technology Inc.

MCP443X/5X 4.0 FUNCTIONAL OVERVIEW 4.1.2 BROWN-OUT RESET When the device powers down, device V will cross This data sheet covers a family of four volatile Digital DD V /V voltage. Potentiometer and Rheostat devices that will be POR BOR referred to as MCP44XX. The MCP44X1 devices are When V voltage decreases below V /V DD POR BOR the Potentiometer configuration, while the MCP44X2 voltage, the serial Interface is disabled. devices are the Rheostat configuration. If the V voltage decreases below V voltage, the DD RAM As the Device Block Diagram shows, there are four following events may occur: main functional blocks. These are: • Volatile wiper registers could become corrupted • POR/BOR and RESET Operation • TCON registers could become corrupted • Memory Map As the voltage recovers above the V /V voltage, POR BOR • Resistor Network the operation is the same as Power-on Reset, as dis- • Serial Interface (I2C) cussed in the previous subsection. The POR/BOR operation and the Memory Map are Serial commands that are not completed because of a discussed in this section and the Resistor Network and brown-out condition could cause the memory location I2C operation are described in their own sections. The to become corrupted. Device Commands commands are discussed in Section7.0. 4.1.3 RESET PIN The RESET pin can be used to force the device into 4.1 POR/BOR and RESET Operation the POR/BOR state of the device. When the RESET pin is forced Low, the device is forced into the Reset The Power-on Reset is the case where the device is state. This means that the TCON registers are forced having power applied to it from V . The Brown-out SS to their default values and the volatile wiper registers Reset occurs when a device had power applied to it, are loaded with the default value. Also the I2C inter- and that power (voltage) drops below the specified face is disabled. range. This feature allows a hardware method for all registers The devices RAM retention voltage (V ) is lower RAM to be updated at the same time. than the POR/BOR voltage trip point (V /V ). The POR BOR maximum VPOR/VBOR voltage is less then 1.8V. 4.1.4 INTERACTION OF RESET PIN AND When V /V < V < 2.7V, the electrical perfor- BOR/POR CIRCUITRY POR BOR DD mance may not meet the data sheet specifications. In Figure4-1 shows how the RESET pin signal and the this region, the device is capable of incrementing, dec- POR/BOR signal interact to control the hardware Reset rementing, reading and writing to its volatile memory if state of the device. the proper serial command is executed. When V < V /V or the RESET pin is Low, the DD POR BOR pin weak pull-ups are enabled. RESET (from pin) Device Reset 4.1.1 POWER-ON RESET POR/BOR signal When the device powers up, the device V crosses DD FIGURE 4-1: POR/BOR Signal and the V /V voltage. POR BOR RESET Pin Interaction. When the V voltage crosses the V /V voltage, DD POR BOR the following events occur: • Volatile wiper register is loaded with the default value • TCON registers are loaded with their default value • Device is capable of digital operation  2010 Microchip Technology Inc. DS22267A-page 41

MCP443X/5X 4.2 Memory Map The volatile memory starts functioning at the RAM retention voltage (V ). The POR/BOR Wiper code is RAM The device memory supports 16 locations that are 9-bit shown in Table4-1. wide (16x9 bits). This memory space contains only volatile locations (see Table4-2). TABLE 4-1: STANDARD SETTINGS 4.2.1 VOLATILE MEMORY (RAM) Wiper Default Resistance Typical Code There are six Volatile Memory locations. These are: POR Wiper Code R Value AB Setting • Volatile Wiper 0 8-bit 7-bit • Volatile Wiper 1 -502 5.0k Mid scale 80h 40h • Volatile Wiper 2 -103 10.0k Mid scale 80h 40h • Volatile Wiper 3 -503 50.0k Mid scale 80h 40h • Terminal Control (TCON0) Register 0 -104 100.0k Mid scale 80h 40h • Terminal Control (TCON)1 Register 1 TABLE 4-2: MEMORY MAP AND THE SUPPORTED COMMANDS Memory Factory Address Function Allowed Commands Disallowed Commands (1) Type Initialization 00h Volatile Wiper 0 RAM Read, Write, — 8-bit 80h Increment, Decrement 7-bit 40h 01h Volatile Wiper 1 RAM Read, Write, — 8-bit 80h Increment, Decrement 7-bit 40h 02h Reserved — None All — 03h Reserved — None All — 04h Volatile RAM Read, Write Increment, Decrement 1FFh TCON0 Register 05h Reserved — None All — 06h Volatile Wiper 2 RAM Read, Write, — 8-bit 80h Increment, Decrement 7-bit 40h 07h Volatile Wiper 3 RAM Read, Write, — 8-bit 80h Increment, Decrement 7-bit 40h 08h Reserved — None All — 09h Reserved — None All — 0Ah Volatile RAM Read, Write Increment, Decrement 1FFh TCON1 Register 0Bh - 0Fh Reserved — None All — Note 1: This command on this address will generate an error condition. To exit the error condition, the user must take the HVC pin to the V level and then back to the active state (V or V ). IH IL IHH DS22267A-page 42  2010 Microchip Technology Inc.

MCP443X/5X 4.2.1.1 Terminal Control (TCON) Registers The value that is written to the specified TCON register There are two Terminal Control (TCON) Registers. will appear on the appropriate resistor network These are called TCON0 and TCON1. Each register terminals when the serial command has completed. contains 8 control bits, four bits for each Wiper. On a POR/BOR these registers are loaded with Register4-1 describes each bit of the TCON0 register, 1FFh(9-bit), for all terminals connected. The Host while Register4-2 describes each bit of the TCON1 Controller needs to detect the POR/BOR event and register. then update the Volatile TCON register values. The state of each resistor network terminal connection is individually controlled. That is, each terminal connection (A, B and W) can be individually connected/ disconnected from the resistor network. This allows the system to minimize the currents through the digital potentiometer. R E GISTER 4-1: TCON0 BITS (1) R-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 D8 R1HW R1A R1W R1B R0HW R0A R0W R0B bit 8 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 8 D8: Reserved. Forced to ‘1’ bit 7 R1HW: Resistor 1 Hardware Configuration Control bit This bit forces Resistor 1 into the “shutdown” configuration of the Hardware pin 1 = Resistor 1 is NOT forced to the hardware pin “shutdown” configuration 0 = Resistor 1 is forced to the hardware pin “shutdown” configuration bit 6 R1A: Resistor 1 Terminal A (P1A pin) Connect Control bit This bit connects/disconnects the Resistor 1 Terminal A to the Resistor 1 Network 1 = P1A pin is connected to the Resistor 1 Network 0 = P1A pin is disconnected from the Resistor 1 Network bit 5 R1W: Resistor 1 Wiper (P1W pin) Connect Control bit This bit connects/disconnects the Resistor 1 Wiper to the Resistor 1 Network 1 = P1W pin is connected to the Resistor 1 Network 0 = P1W pin is disconnected from the Resistor 1 Network bit 4 R1B: Resistor 1 Terminal B (P1B pin) Connect Control bit This bit connects/disconnects the Resistor 1 Terminal B to the Resistor 1 Network 1 = P1B pin is connected to the Resistor 1 Network 0 = P1B pin is disconnected from the Resistor 1 Network bit 3 R0HW: Resistor 0 Hardware Configuration Control bit This bit forces Resistor 0 into the “shutdown” configuration of the Hardware pin 1 = Resistor 0 is NOT forced to the hardware pin “shutdown” configuration 0 = Resistor 0 is forced to the hardware pin “shutdown” configuration bit 2 R0A: Resistor 0 Terminal A (P0A pin) Connect Control bit This bit connects/disconnects the Resistor 0 Terminal A to the Resistor 0 Network 1 = P0A pin is connected to the Resistor 0 Network 0 = P0A pin is disconnected from the Resistor 0 Network bit 1 R0W: Resistor 0 Wiper (P0W pin) Connect Control bit This bit connects/disconnects the Resistor 0 Wiper to the Resistor 0 Network 1 = P0W pin is connected to the Resistor 0 Network 0 = P0W pin is disconnected from the Resistor 0 Network bit 0 R0B: Resistor 0 Terminal B (P0B pin) Connect Control bit This bit connects/disconnects the Resistor 0 Terminal B to the Resistor 0 Network 1 = P0B pin is connected to the Resistor 0 Network 0 = P0B pin is disconnected from the Resistor 0 Network Note 1: These bits do not affect the wiper register values.  2010 Microchip Technology Inc. DS22267A-page 43

MCP443X/5X R EGISTER 4-2: TCON1 BITS (1) R-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 D8 R3HW R3A R3W R3B R2HW R2A R2W R2B bit 8 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 8 D8: Reserved. Forced to ‘1’ bit 7 R3HW: Resistor 3 Hardware Configuration Control bit This bit forces Resistor 3 into the “shutdown” configuration of the Hardware pin 1 = Resistor 3 is NOT forced to the hardware pin “shutdown” configuration 0 = Resistor 3 is forced to the hardware pin “shutdown” configuration bit 6 R3A: Resistor 3 Terminal A (P3A pin) Connect Control bit This bit connects/disconnects the Resistor 3 Terminal A to the Resistor 3 Network 1 = P3A pin is connected to the Resistor 3 Network 0 = P3A pin is disconnected from the Resistor 3 Network bit 5 R3W: Resistor 3 Wiper (P3W pin) Connect Control bit This bit connects/disconnects the Resistor 3 Wiper to the Resistor 3 Network 1 = P3W pin is connected to the Resistor 3 Network 0 = P3W pin is disconnected from the Resistor 3 Network bit 4 R3B: Resistor 3 Terminal B (P3B pin) Connect Control bit This bit connects/disconnects the Resistor 3 Terminal B to the Resistor 3 Network 1 = P3B pin is connected to the Resistor 3 Network 0 = P3B pin is disconnected from the Resistor 3 Network bit 3 R2HW: Resistor 2 Hardware Configuration Control bit This bit forces Resistor 2 into the “shutdown” configuration of the Hardware pin 1 = Resistor 2 is NOT forced to the hardware pin “shutdown” configuration 0 = Resistor 2 is forced to the hardware pin “shutdown” configuration bit 2 R2A: Resistor 2 Terminal A (P0A pin) Connect Control bit This bit connects/disconnects the Resistor 2 Terminal A to the Resistor 2 Network 1 = P2A pin is connected to the Resistor 2 Network 0 = P2A pin is disconnected from the Resistor 2 Network bit 1 R2W: Resistor 2 Wiper (P0W pin) Connect Control bit This bit connects/disconnects the Resistor 2 Wiper to the Resistor 2 Network 1 = P2W pin is connected to the Resistor 2 Network 0 = P2W pin is disconnected from the Resistor 2 Network bit 0 R2B: Resistor 2 Terminal B (P2B pin) Connect Control bit This bit connects/disconnects the Resistor 2 Terminal B to the Resistor 2 Network 1 = P2B pin is connected to the Resistor 2 Network 0 = P2B pin is disconnected from the Resistor 2 Network Note 1: These bits do not affect the wiper register values. DS22267A-page 44  2010 Microchip Technology Inc.

MCP443X/5X 5.0 RESISTOR NETWORK 5.1 Resistor Ladder Module The Resistor Network has either 7-bit or 8-bit The resistor ladder is a series of equal value resistors resolution. Each Resistor Network allows zero scale to (RS) with a connection point (tap) between the two full scale connections. Figure5-1 shows a block resistors. The total number of resistors in the series diagram for the resistive network of a device. (ladder) determines the RAB resistance (see Figure5- 1). The end points of the resistor ladder are connected The Resistor Network is made up of several parts. to analog switches which are connected to the device These include: Terminal A and Terminal B pins. The R (and R ) AB S • Resistor Ladder resistance has small variations over voltage and • Wiper temperature. • Shutdown (Terminal Connections) For an 8-bit device, there are 256 resistors in a string Devices have four resistor networks. These are between terminal A and terminal B. The wiper can be referred to as Pot 0, Pot 1 Pot 2, and Pot 3. set to tap onto any of these 256 resistors, thus providing 257 possible settings (including terminal A A and terminal B). For a 7-bit device, there are 128 resistors in a string 8-Bit 7-Bit between terminal A and terminal B. The wiper can be N = N = 256 128 set to tap onto any of these 128 resistors, thus (100h) (80h) providing 129 possible settings (including terminal A R (1) R W and terminal B). S Equation5-1 shows the calculation for the step 255 127 resistance. RS RW (1) (FFh) (7Fh) EQUATION 5-1: R CALCULATION 254 126 S (FEh) (7Eh) R (1) R RABRS W RS = ---2---5-A---6B---- 8-bit Device W R R = -------A---B----- 7-bit Device 1 1 S 128 (01h) (01h) R (1) R W S 0 0 (00h) (00h) R (1) W Analog Mux B Note1:The wiper resistance is dependent on several factors including, wiper code, device V , Terminal voltages (on A, B, DD and W), and temperature. Also for the same conditions, each tap selection resistance has a small variation. This R variation has greater effects on W some specifications (such as INL) for the smaller resistance devices (5.0k) compared to larger resistance devices (100.0k). FIGURE 5-1: Resistor Block Diagram.  2010 Microchip Technology Inc. DS22267A-page 45

MCP443X/5X 5.2 Wiper 5.3 Shutdown Shutdown is used to minimize the device’s current Each tap point (between the R resistors) is a S consumption. The MCP44XX has one method to connection point for an analog switch. The opposite achieve this. This is: side of the analog switch is connected to a common signal which is connected to the Terminal W (Wiper) • Terminal Control Register (TCON) pin. This is different from the MCP42XXX devices in that the Hardware Shutdown Pin (SHDN) has been replaced by A value in the volatile wiper register selects which a RESET pin. The Hardware Shutdown Pin function is analog switch to close, connecting the W terminal to still available via software commands to the TCON the selected node of the resistor ladder. register. The wiper can connect directly to Terminal B or to 5.3.1 TERMINAL CONTROL REGISTER Terminal A. A zero scale connections, connects the Terminal W (wiper) to Terminal B (wiper setting of (TCON) 000h). A full scale connection, connects the Terminal W The Terminal Control (TCON) register is a volatile (wiper) to Terminal A (wiper setting of 100h or 80h). In register used to configure the connection of each these configurations, the only resistance between the resistor network terminal pin (A, B, and W) to the Terminal W and the other Terminal (A or B) is that of the Resistor Network. These registers are shown in analog switches. Register4-1 and Register4-2. A wiper setting value greater than full scale (wiper The RxHW bits forces the selected resistor network setting of 100h for 8-bit device or 80h for 7-bit devices) into the same state as the MCP42X1’s SHDN pin. will also be a Full Scale setting (Terminal W (wiper) Alternate low power configurations may be achieved connected to Terminal A). Table5-1 illustrates the full with the RxA, RxW, and RxB bits. wiper setting map. When the RxHW bit is ‘0’: • The P0A, P1A, P2A, and P3A terminals are Equation5-2 illustrates the calculation used to disconnected determine the resistance between the wiper and • The P0W, P1W, P2W, and P3W terminals are terminal B. simultaneously connect to the P0B, P1B, P2B, and P3B terminals, respectively (see Figure5-2) EQUATION 5-2: R CALCULATION WB R N Note: When the RxHW bit forces the resistor R = -----A---B------+R 8-bit Device network into the hardware SHDN state, WB 256 W the state of the TCON0 or TCON1 N = 0 to 256 (decimal) register’s RxA, RxW, and RxB bits is overridden (ignored). When the state of R N R = -----A---B------+R 7-bit Device the RxHW bit no longer forces the resistor WB 128 W network into the hardware SHDN state, N = 0 to 128 (decimal) the TCON0 or TCON1 register’s RxA, RxW, and RxB bits return to controlling the terminal connection state. In other words, TABLE 5-1: VOLATILE WIPER VALUE VS. the RxHW bit does not corrupt the state of WIPER POSITION MAP the RxA, RxW, and RxB bits. Wiper Setting The RxHW bit does NOT corrupt the values in the Properties Volatile Wiper Registers nor the TCON register. When 7-bit 8-bit the Shutdown mode is exited (RxHW bit = 1): 3FFh – 3FFh – Reserved (Full Scale (W = A)), • The device returns to the Wiper setting specified 081h 101h Increment and Decrement by the Volatile Wiper value commands ignored • The TCON register bits return to controlling the 080h 100h Full Scale (W = A), terminal connection state Increment commands ignored A 07Fh – 0FFh – W = N k 041h 081h or 040h 080h W = N (Mid Scale) w W et 03Fh – 07Fh – W = N N 001h 001h or st 000h 000h Zero Scale (W = B) si e Decrement command ignored R B FIGURE 5-2: Resistor Network Shutdown State (RxHW = ‘0’). DS22267A-page 46  2010 Microchip Technology Inc.

MCP443X/5X 6.0 SERIAL INTERFACE (I2C) 6.1 Signal Descriptions The MCP44XX devices support the I2C serial protocol. The I2C interface uses up to four pins (signals). These The MCP44XX I2C’s module operates in Slave mode are: (does not generate the serial clock). • SDA (Serial Data) Figure6-1 shows a typical I2C Interface connection. All • SCL (Serial Clock) I2C interface signals are high-voltage tolerant. • A0 (Address 0 bit) The MCP44XX devices use the two-wire I2C serial • A1 (Address 1 bit) interface. This interface can operate in standard, fast or 6.1.1 SERIAL DATA (SDA) High-Speed mode. A device that sends data onto the bus is defined as transmitter, and a device receiving The Serial Data (SDA) signal is the data signal of the data as receiver. The bus has to be controlled by a device. The value on this pin is latched on the rising master device which generates the serial clock (SCL), edge of the SCL signal when the signal is an input. controls the bus access and generates the START and With the exception of the START and STOP conditions, STOP conditions. The MCP44XX device works as the high or low state of the SDA pin can only change slave. Both master and slave can operate as when the clock signal on the SCL pin is low. During the transmitter or receiver, but the master device high period of the clock, the SDA pin’s value (high or determines which mode is activated. Communication is low) must be stable. Changes in the SDA pin’s value initiated by the master (microcontroller) which sends while the SCL pin is HIGH will be interpreted as a the START bit, followed by the slave address byte. The START or a STOP condition. first byte transmitted is always the slave address byte, which contains the device code, the address bits, and 6.1.2 SERIAL CLOCK (SCL) the R/W bit. The Serial Clock (SCL) signal is the clock signal of the Refer to the NXP I2C document for more details of the device. The rising edge of the SCL signal latches the I2C specifications. value on the SDA pin. The MCP44XX supports three I2C interface clock modes: Typical I2C Interface Connections • Standard Mode: clock rates up to 100kHz • Fast Mode: clock rates up to 400kHz Host MCP4XXX • High-Speed Mode (HS mode): clock rates up to Controller 3.4MHz SCL SCL The MCP44XX will not stretch the clock signal (SCL) SDA SDA since memory read access occur fast enough. I/O (1) HVC/A0 (2) Depending on the clock rate mode, the interface will display different characteristics. A1 (2, 3) 6.1.3 THE ADDRESS BITS (A1:A0) Note1: If High voltage commands are desired, There are up to two hardware pins used to specify the some type of external circuitry needs to device address. The number of address pins is be implemented. determined by the part number. 2: These pins have internal pull-ups. If Address 0 is multiplexed with the High Voltage faster rise times are required, then Command (HVC) function. So the state of A0 is latched external pull-ups should be added. on the MCP4XXX’s POR/BOR event. 3: This pin could be tied high, low, or The state of the A1 pin should be static, that is they connected to an I/O pin of the Host should be tied high or tied low. Controller. 6.1.3.1 The High Voltage Command (HVC) FIGURE 6-1: Typical I2C Interface Block Signal Diagram. The High Voltage Command (HVC) signal is multiplexed with Address 0 (A0) and is used to indicate that the command, or sequence of commands, are in the High Voltage mode. High Voltage commands are supported for compatibility with non-volatile devices. The HVC pin has an internal resistor connection to the MCP44XXs internal V signal. DD  2010 Microchip Technology Inc. DS22267A-page 47

MCP443X/5X 6.2 I2C Operation 6.2.1.3 Acknowledge (A) Bit The MCP44XX’s I2C module is compatible with the The A bit (see Figure6-4) is typically a response from NXP I2C specification. The following lists some of the the receiving device to the transmitting device. modules features: Depending on the context of the transfer sequence, the A bit may indicate different things. Typically the Slave • 7-bit slave addressing device will supply an A response after the Start bit and • Supports three clock rate modes: 8 “data” bits have been received. an A bit has the SDA - Standard mode, clock rates up to 100kHz signal low. - Fast mode, clock rates up to 400kHz - High-speed mode (HS mode), clock rates up to 3.4MHz SDA D0 A • Support Multi-Master Applications • General call addressing SCL 8 9 • Internal weak pull-ups on interface signals The I2C 10-bit addressing mode is not supported. FIGURE 6-4: Acknowledge Waveform. The NXP I2C specification only defines the field types, field lengths, timings, etc. of a frame. The frame con- Not A (A) Response tent defines the behavior of the device. The frame con- tent for the MCP44XX is defined in Section7.0. The A bit has the SDA signal high. Table6-1 shows some of the conditions where the Slave Device will 6.2.1 I2C BIT STATES AND SEQUENCE issue a Not A (A). Figure6-8 shows the I2C transfer sequence. The serial If an error condition occurs (such as an A instead of A), clock is generated by the master. The following defini- then an START bit must be issued to reset the tions are used for the bit states: command state machine. • Start bit (S) • Data bit TABLE 6-1: MCP45XX/MCP46XX A / A • Acknowledge (A) bit (driven low) / RESPONSES No Acknowledge (A) bit (not driven low) Acknowledge • Repeated Start bit (Sr) Event Comment Bit Response • Stop bit (P) General Call A Only if GCEN bit is 6.2.1.1 Start Bit set The Start bit (see Figure6-2) indicates the beginning of Slave Address A a data transfer sequence. The Start bit is defined as the valid SDA signal falling when the SCL signal is “High”. Slave Address A not valid 1st Bit 2nd Bit Device Memory A After device has SDA Address and received address specified and command SCL command S (AD3:AD0 and FIGURE 6-2: Start Bit. C1:C0) are an invalid 6.2.1.2 Data Bit combination The SDA signal may change state while the SCL signal Communica- A After device has is Low. While the SCL signal is High, the SDA signal tion during received address MUST be stable (see Figure6-5). EEPROM write and command, cycle and valid conditions for SDA 1st Bit 2nd Bit EEPROM write Bus Collision N.A. I2C Module SCL Resets, or a “Don’t Data Bit Care” if the FIGURE 6-3: Data Bit. collision occurs on the Master’s “Start bit” DS22267A-page 48  2010 Microchip Technology Inc.

MCP443X/5X 6.2.1.4 Repeated Start Bit 6.2.1.5 Stop Bit The Repeated Start bit (see Figure6-5) indicates the The Stop bit (see Figure6-6) Indicates the end of the current Master Device wishes to continue communicat- I2C Data Transfer Sequence. The Stop bit is defined as ing with the current Slave Device without releasing the the SDA signal rising when the SCL signal is “High”. I2C bus. The Repeated Start condition is the same as A Stop bit resets the I2C interface of all MCP44XX the Start condition, except that the Repeated Start bit devices. follows a Start bit (with the Data bits + A bit) and not a Stop bit. The Start bit is the beginning of a data transfer SDA A / A sequence and is defined as the SDA signal falling when the SCL signal is “High”. SCL Note1: A bus collision during the Repeated Start P condition occurs if: FIGURE 6-6: Stop Condition Receive or Transmit Mode. •SDA is sampled low when SCL goes from low to high. 6.2.2 CLOCK STRETCHING •SCL goes low before SDA is asserted “Clock Stretching” is something that the receiving low. This may indicate that another Device can do, to allow additional time to “respond” to master is attempting to transmit a the “data” that has been received. data‘1’. The MCP44XX will not stretch the clock signal (SCL) since memory read access occur fast enough. SDA 1st Bit 6.2.3 ABORTING A TRANSMISSION If any part of the I2C transmission does not meet the command format, it is aborted. This can be intentionally accomplished with a START or STOP condition. This is SCL done so that noisy transmissions (usually an extra START or STOP condition) are aborted before they Sr = Repeated Start corrupt the device. FIGURE 6-5: Repeat Start Condition Waveform. SDA SCL S 1st Bit 2nd Bit 3rd Bit 4th Bit 5th Bit 6th Bit 7th Bit 8th Bit A / A P FIGURE 6-7: Typical 8-Bit I2C Waveform Format. SDA SCL START Data allowed Data or STOP Condition to change A valid Condition FIGURE 6-8: I2C Data States and Bit Sequence.  2010 Microchip Technology Inc. DS22267A-page 49

MCP443X/5X 6.2.4 ADDRESSING Slave Address The address byte is the first byte received following the START condition from the master device. The address S A6 A5 A4 A3 A2 A1 A0 R/W A/A contains four (or more) fixed bits and (up to) three user ‘0’‘1’ ‘0’‘1’ ‘1’ defined hardware address bits (pins A1 and A0). These See Table6-2 7-bits address the desired I2C device. The A6:A2 Start R/W bit address bits are fixed to ‘01011’ and the device bit R/W = 0 = write appends the value of following two address pins (A1 R/W = 1 = read and A0). A bit (controlled by slave device) Since there are address bits controlled by hardware A = 0 = Slave Device Acknowledges byte pins, there may be up to four MCP44XX devices on the A = 1 = Slave Device does not Acknowledge byte same I2C bus. FIGURE 6-9: Slave Address Bits in the Figure6-9 shows the slave address byte format, which I2C Control Byte. contains the seven address bits. There is also a read/ write (R/W) bit. Table6-2 shows the fixed address for TABLE 6-2: DEVICE SLAVE ADDRESSES device. Device Address Comment MCP44XX ‘0101 1’b + A1:A0 Supports up to 4 Hardware Address Pins devices. (Note1) The hardware address bits (A1, and A0) correspond to Note 1: A0 is used for High-Voltage commands the logic level on the associated address pins. This (HVC/A0) and the value is latched at allows up to eight devices on the bus. POR/BOR. These pins have a weak pull-up enabled when the V DD 6.2.5 SLOPE CONTROL < V . The weak pull-up utilizes the “smart” pull-up BOR technology and exhibits the same characteristics as the The MCP44XX implements slope control on the SDA High-voltage tolerant I/O structure. output. The state of the A0 address pin is latch on POR/BOR. As the device transitions from HS mode to FS mode, This is required since High Voltage commands force the slope control parameter will change from the HS this pin (HVC/A0) to the V level. specification to the FS specification. IHH For Fast (FS) and High-Speed (HS) modes, the device has a spike suppression and a Schmidt trigger at SDA and SCL inputs. DS22267A-page 50  2010 Microchip Technology Inc.

MCP443X/5X 6.2.6 HS MODE After switching to the High-Speed mode, the next The I2C specification requires that a high-speed mode transferred byte is the I2C control byte, which specifies the device to communicate with, and any number of device must be ‘activated’ to operate in high-speed data bytes plus acknowledgements. The Master (3.4Mbit/s) mode. This is done by the Master sending Device can then either issue a Repeated Start bit to a special address byte following the START bit. This address a different device (at High-Speed) or a Stop bit byte is referred to as the high-speed Master Mode to return to Fast/Standard bus speed. After the Stop bit, Code (HSMMC). any other Master Device (in a Multi-Master system) can The MCP44XX device does not acknowledge this byte. arbitrate for the I2C bus. However, upon receiving this command, the device See Figure6-10 for illustration of HS mode command switches to HS mode. The device can now sequence. communicate at up to 3.4Mbit/s on SDA and SCL lines. The device will switch out of the HS mode on the For more information on the HS mode, or other I2C next STOP condition. modes, please refer to the I2C specification. The master code is sent as follows: 6.2.6.1 Slope Control 1. START condition (S) The slope control on the SDA output is different 2. High-Speed Master Mode Code (0000 1XXX), between the Fast/Standard Speed and the High-Speed The XXX bits are unique to the high-speed (HS) clock modes of the interface. mode Master. 3. No Acknowledge (A) 6.2.6.2 Pulse Gobbler The pulse gobbler on the SCL pin is automatically adjusted to suppress spikes < 10ns during HS mode. F/S-mode HS-mode P F/S-mode S ‘0 0 0 0 1 X X X’b A Sr‘Slave Address’R/W A “Data” A/A HS-mode continues Sr‘Slave Address’R/W A HS Select Byte Control Byte Command/Data Byte(s) S = Start bit Control Byte Sr = Repeated Start bit A = Acknowledge bit A = Not Acknowledge bit R/W = Read/Write bit P = Stop bit (Stop condition terminates HS Mode) FIGURE 6-10: HS Mode Sequence.  2010 Microchip Technology Inc. DS22267A-page 51

MCP443X/5X 6.2.7 GENERAL CALL TABLE 6-3: GENERAL CALL COMMANDS The General Call is a method by which the “Master” 7-bit device can communicate with all other “Slave” devices. Command Comment In a Multi-Master application, the other Master devices (1, 2, 3) are operating in Slave mode. The General Call address has two documented formats. These are shown in ‘1000 00d’b Write Next Byte (Third Byte) to Volatile Figure6-11. We have added a MCP44XX format in this Wiper 0 Register figure as well. ‘1001 00d’b Write Next Byte (Third Byte) to Volatile This will allow customers to have multiple I2C Digital Wiper 1 Register Potentiometers on the bus and have them operate in a ‘1100 00d’b Write Next Byte (Third Byte) to TCON synchronous fashion (analogous to the DAC Sync pin Register functionality). If these MCP44XX 7-bit commands ‘1000 010’b Increment Wiper 0 Register conflict with other I2C devices on the bus, then the or customer will need two I2C busses and ensure that the ‘1000 011’b devices are on the correct bus for their desired application functionality. ‘1001 010’b Increment Wiper 1 Register or Dual Pot devices can not update both Pot0 and Pot1 ‘1001 011’b from a single command. To address this, there are General Call commands for the Wiper 0, Wiper 1, and ‘1000 100’b Decrement Wiper 0 Register the TCON registers. or ‘1000 101’b Table6-3 shows the General Call Commands. Three commands are specified by the I2C specification and ‘1001 100’b Decrement Wiper 1 Register are not applicable to the MCP44XX (so command is or Not Acknowledged). The MCP44XX General Call ‘1001 101’b Commands are Acknowledged. Any other command is Note 1: Any other code is Not Acknowledged. Not Acknowledged. These codes may be used by other devices on the I2C bus. Note: Only one General Call command per issue 2: The 7-bit command always appends a ‘0’ of the General Call control byte. Any to form 8-bits. additional General Call commands are 3: “d” is the D8 bit for the 9-bit write value. ignored and Not Acknowledged. DS22267A-page 52  2010 Microchip Technology Inc.

MCP443X/5X Second Byte S 0 0 0 0 0 0 0 0 A X X X X X X X 0 A P General Call Address “7-bit Command” Reserved 7-bit Commands (by I2C Specification - NXP UM10204_3, Version 03 19, June 2007) ‘0000 011’b - Reset and write programmable part of slave address by hardware. ‘0000 010’b - Write programmable part of slave address by hardware. ‘0000 000’b - NOT Allowed MCP44XX 7-bit Commands ‘1000 01x’b - Increment Wiper 0 Register. ‘1001 01x’b - Increment Wiper 1 Register. ‘1000 10x’b - Decrement Wiper 0 Register. ‘1001 10x’b - Decrement Wiper 1 Register. The Following is a Microchip Extension to this General Call Format Second Byte Third Byte S 0 0 0 0 0 0 0 0 A X X X X X X d 0 A d d d d d d d d A P General Call Address “7-bit Command” ‘0’ for General Call Command MCP44XX 7-bit Commands ‘1000 00d’b - Write Next Byte (Third Byte) to Volatile Wiper 0 Register. ‘1001 00d’b - Write Next Byte (Third Byte) to Volatile Wiper 1 Register. ‘1100 00d’b - Write Next Byte (Third Byte) to TCON Register. The Following is a “Hardware General Call” Format Second Byte n occurrences of (Data + A) S 0 0 0 0 0 0 0 0 A X X X X X X X 1 A X X X X X X X X A P General Call Address “7-bit Command” This indicates a “Hardware General Call” MCP44XX will ignore this byte and all following bytes (and A), until a Stop bit (P) is encountered. FIGURE 6-11: General Call Formats.  2010 Microchip Technology Inc. DS22267A-page 53

MCP443X/5X NOTES: DS22267A-page 54  2010 Microchip Technology Inc.

MCP443X/5X 7.0 DEVICE COMMANDS 7.1 Command Byte The MCP44XX’s I2C command formats are specified in The MCP44XX’s Command Byte has three fields: the this section. The I2C protocol does not specify how Address, the Command Operation, and 2 Data bits commands are formatted. (see Figure7-1). Currently only one of the data bits is defined (D8). The MCP44XX supports four basic commands. The location accessed determines the commands that are The device memory is accessed when the Master supported. sends a proper Command Byte to select the desired operation. The memory location getting accessed is For the Volatile Wiper Registers, these commands are: contained in the Command Byte’s AD3:AD0 bits. The • Write Data action desired is contained in the Command Byte’s • Read Data C1:C0 bits, see Figure7-1. C1:C0 determines if the • Increment Data desired memory location will be read, written, • Decrement Data Incremented (wiper setting +1) or Decremented (wiper For the TCON Register, these commands are: setting -1). The Increment and Decrement commands are only valid on the volatile wiper registers, and in • Write Data High Voltage commands to enable/disable WiperLock • Read Data Technology and Software Write Protect. These commands have formats for both a single If the Address bits and Command bits are not a valid command or continuous commands. These commands combination, then the MCP44XX will generate a Not are shown in Table7-1. Acknowledge pulse to indicate the invalid combination. Each command has two operational states. These The I2C Master device must then force a Start operational states are referred to as: Condition to reset the MCP44XX’s I2C module. • Normal Serial Commands D9 and D8 are the most significant bits for the digital • High-Voltage Serial Commands potentiometer’s wiper setting. The 8-bit devices utilize Note: High Voltage commands are supported for D8 as their MSb while the 7-bit devices utilize D7 (from compatibility with Non-Volatile devices in the data byte) as their MSb. the family. COMMAND BYTE TABLE 7-1: I2C COMMANDS A A A A A C C D D A Command # of Bit Clocks D D D D 1 0 9 8 Operation Mode (1) 3 2 1 0 Write Data Single 29 MCP4XXX MSbits (Data) Continuous 18n + 11 Memory Address Read Data Single 29 Command Operation bits Random 48 00 = Write Data 01 = Increment Continuous 18n + 11 10 = Decrement Increment Single 20 11 = Read Data Continuous 9n + 11 FIGURE 7-1: Command Byte Format. Decrement Single 20 Continuous 9n + 11 Note 1: “n” indicates the number of times the command operation is to be repeated. Normal serial commands are those where the HVC pin is driven to V or V . With High-Voltage Serial IH IL Commands, the HVC pin is driven to V . In each IHH mode, there are four possible commands. Table7-2 shows the supported commands for each memory location. Table7-3 shows an overview of all the device commands and their interaction with other device features.  2010 Microchip Technology Inc. DS22267A-page 55

MCP443X/5X TABLE 7-2: MEMORY MAP AND THE SUPPORTED COMMANDS Address Data Value Function Command (10-bits) (1) Comment 00h Volatile Wiper 0 Write Data nn nnnn nnnn Read Data (3) nn nnnn nnnn Increment Wiper — Decrement Wiper — 01h Volatile Wiper 1 Write Data nn nnnn nnnn Read Data (3) nn nnnn nnnn Increment Wiper — Decrement Wiper — 02h Reserved — — 03h Reserved — — 04h (2) Volatile Write Data nn nnnn nnnn TCON 0 Register Read Data (3) nn nnnn nnnn 05h (2) — Read Data (3) — Maps to Non-Volatile MCP444x/6x device’s STATUS Register 06h Volatile Wiper 2 Write Data nn nnnn nnnn Read Data (3) nn nnnn nnnn Increment Wiper — Decrement Wiper — 07h Volatile Wiper 3 Write Data nn nnnn nnnn Read Data (3) nn nnnn nnnn Increment Wiper — Decrement Wiper — 08h Reserved — — 09h Reserved — — 0Ah (2) Volatile Write Data nn nnnn nnnn TCON 1 Register Read Data (3) nn nnnn nnnn 0Bh - 0Fh Reserved — — Note 1: The Data Memory is only 9-bits wide, so the MSb is ignored by the device. 2: Increment or Decrement commands are invalid for these addresses. 3: I2C read operation will read 2 bytes, of which the 10-bits of data are contained within. DS22267A-page 56  2010 Microchip Technology Inc.

MCP443X/5X 7.2 Data Byte 7.3 Error Condition Only the Read Command and the Write Command If the four address bits received (AD3:AD0), and the have Data Byte(s). two command bits received (C1:C0), are a valid combination, the MCP44XX will Acknowledge the I2C The Write command concatenates the 8 bits of the bus. Data Byte with the one data bit (D8) contained in the Command Byte to form 9 bits of data (D8:D0). The If the address bits and command bits are an invalid Command Byte format supports up to 9 bits of data so combination, then the MCP44XX will Not Acknowledge that the 8-bit resistor network can be set to Full-Scale the I2C bus. (100h or greater). This allows wiper connections to When an error condition has occurred, any commands Terminal A and to TerminalB. The D9 bit is currently that follow are ignored until the I2C bus is reset with a unused. Start Condition. 7.3.1 ABORTING A TRANSMISSION A Restart or Stop condition in the expected data bit position will abort the current command sequence and data will not be written to the MCP44XX. TABLE 7-3: COMMANDS High Voltage Command Name # of Bits (V ) on IHH HVC pin? Write Data 29 — Read Data 29 — Increment Wiper 20 — Decrement Wiper 20 — High Voltage Write Data 29 Yes High Voltage Read Data 29 Yes High Voltage Increment Wiper 20 Yes High Voltage Decrement Wiper 20 Yes  2010 Microchip Technology Inc. DS22267A-page 57

MCP443X/5X 7.4 Write Data 7.4.2 CONTINUOUS WRITES TO Normal and High Voltage VOLATILE MEMORY A continuous write mode of operation is possible when The Write Command format, see Figure7-2, includes the I2C Control Byte, an A bit, the MCP44XX Command writing to the volatile memory registers (address 00h, 01h, 04h, 06h, 07h, and 0Ah). This continuous write Byte, an A bit, the MCP44XX Data Byte, an A bit, and mode allows writes without a Stop or Restart condition a Stop (or Restart) condition. The MCP44XX generates or repeated transmissions of the I2C Control Byte. the A/A bits. Figure7-3 shows the sequence for three continuous A Write command to a Volatile memory location writes. The writes do not need to be to the same volatile changes that location after a properly formatted Write memory address. The sequence ends with the master Command and the A/A clock have been received. sending a STOP or RESTART condition. 7.4.1 SINGLE WRITE TO VOLATILE 7.4.3 THE HIGH VOLTAGE COMMAND MEMORY (HVC) SIGNAL For volatile memory locations, data is written to the The High Voltage Command (HVC) signal is MCP44XX after every byte transfer (during the multiplexed with Address 0 (A0) and is used to indicate Acknowledge). If a Stop or Restart condition is that the command, or sequence of commands, are in generated during a data transfer (before the A), the the High Voltage operational state. data will not be written to the MCP44XX. After the A bit, The HVC pin has an internal resistor connection to the the master can initiate the next sequence with a Stop or MCP44XXs internal V signal. Restart condition. DD Refer to Figure7-2 for the byte write sequence. DS22267A-page 58  2010 Microchip Technology Inc.

MCP443X/5X Write bit Device Fixed Variable Memory Address Address Address Command Write “Data” bits ADADADAD S 0 1 0 1 1 A1 A0 0 A 3 2 1 0 0 0 x D8 A D7 D6D5 D4 D3 D2 D1D0 A P Control Byte WRITE Command Write Data bits FIGURE 7-2: I2C Write Sequence. Write bit Device Fixed Variable Memory Address Address Address Command Write “Data” bits ADADADAD S 0 1 0 1 1 A1 A0 0 A 0 0 x D8 AD7 D6D5 D4 D3 D2 D1D0 A 3 2 1 0 Control Byte WRITE Command Write Data bits ADADADAD 0 0 x D8 A D7 D6 D5 D4 D3 D2D1D0 A 3 2 1 0 WRITE Command Write Data bits STOP bit ADADADAD 0 0 x D8 A D7 D6D5 D4 D3 D2 D1D0 A P 3 2 1 0 WRITE Command Write Data bits Note: Only functions when writing the volatile wiper registers (AD3:AD0 = 00h, 01h, 06h, and 07h) or the TCON registers (AD3:AD0 = 04h and 0Ah) FIGURE 7-3: I2C Continuous Volatile Wiper Write.  2010 Microchip Technology Inc. DS22267A-page 59

MCP443X/5X 7.5 Read Data 7.5.1 SINGLE READ Normal and High Voltage Figure7-4 show the waveforms for a single read. The Read Command format (see Figure7-4), includes For single reads the master sends a STOP or the Start condition, I2C Control Byte (with R/W bit set to RESTART condition after the data byte is sent from the ‘0’), A bit, MCP44XX Command Byte, A bit, followed by slave. a Repeated Start bit, I2C Control Byte (with R/W bit set 7.5.1.1 Random Read to ‘1’), and the MCP44XX transmitting the requested Data High Byte, and A bit, the Data Low Byte, the Figure7-5 shows the sequence for a Random Reads. Master generating the A, and Stop condition. Refer to Figure7-5 for the random byte read The I2C Control Byte requires the R/W bit equal to a sequence. logic one (R/W = 1) to generate a read sequence. The memory location read will be the last address 7.5.2 CONTINUOUS READS contained in a valid write MCP44XX Command Byte or Continuous reads allows the devices memory to be address 00h if no write operations have occurred since read quickly. Continuous reads are possible to all the device was reset (Power-on Reset or Brown-out memory locations. Reset). Figure7-6 shows the sequence for three continuous Read operations initially include the same address byte reads. sequence as the write sequence (shown in Figure6-9). This sequence is followed by another control byte For continuous reads, instead of transmitting a Stop (including the Start condition and Acknowledge) with or Restart condition after the data transfer, the master the R/W bit equal to a logic one (R/W = 1) to indicate a reads the next data byte. The sequence ends with the read. The MCP44XX will then transmit the data master Not Acknowledging and then sending a Stop or contained in the addressed register. This is followed by Restart. the master generating an A bit in preparation for more 7.5.3 THE HIGH VOLTAGE COMMAND data, or an A bit followed by a Stop. The sequence is (HVC) SIGNAL ended with the master generating a Stop or Restart condition. The High Voltage Command (HVC) signal is The internal address pointer is maintained. multiplexed with Address 0 (A0) and is used to indicate that the command, or sequence of commands, are in the High Voltage mode. The HVC pin has an internal resistor connection to the MCP44XX’s internal V signal. DD 7.5.4 IGNORING AN I2C TRANSMISSION AND “FALLING OFF” THE BUS The MCP44XX expects to receive complete, valid I2C commands and will assume any command not defined as a valid command is due to a bus corruption and will enter a passive high condition on the SDA signal. All signals will be ignored until the next valid Start condition and Control Byte are received. DS22267A-page 60  2010 Microchip Technology Inc.

MCP443X/5X Read bit STOP bit Fixed Variable Address Address Read Data bits S 0 1 0 1 1 A1 A0 1 A 0 0 0 0 0 0 0 D8 A1D7 D6 D5 D4D3 D2 D1D0 A2 P Control Byte Read bits Note1: Master Device is responsible for A / A signal. If a A signal occurs, the MCP44XX will abort this transfer and release the bus. 2: The Master Device will Not Acknowledge, and the MCP44XX will release the bus so the Master Device can generate a Stop or Repeated Start condition. 3: The MCP44XX retains the last “Device Memory Address” that it has received. This is the MCP44XX does not “corrupt” the “Device Memory Address” after Repeated Start or Stop conditions. 4: The Device Memory Address pointer defaults to 00h on POR and BOR conditions. FIGURE 7-4: I2C Read (Last Memory Address Accessed). Write bit Repeated Start bit Device Fixed Variable Memory Address Address Address Command ADADADAD S 0 1 0 1 1 A1 A0 0 A 1 1 x X A Sr 3 2 1 0 Control Byte READ Command STOP bit Read bit Read Data bits 0 1 0 1 1 A1 A0 1 A 0 0 0 0 0 0 0 D8 A1 D7 D6D5 D4 D3 D2 D1D0 A2 P Control Byte Read bits Note1: Master Device is responsible for A / A signal. If a A signal occurs, the MCP44XX will abort this transfer and release the bus. 2: The Master Device will Not Acknowledge, and the MCP44XX will release the bus so the Mas- ter Device can generate a Stop or Repeated Start condition. 3: The MCP44XX retains the last “Device Memory Address” that it has received. This is the MCP44XX does not “corrupt” the “Device Memory Address” after Repeated Start or Stop conditions. FIGURE 7-5: I2C Random Read.  2010 Microchip Technology Inc. DS22267A-page 61

MCP443X/5X Read bit Fixed Variable Address Address Read Data bits S 0 1 0 1 1 A1 A0 1 A 0 0 0 0 0 0 0 D8 A1D7D6 D5 D4 D3 D2D1D0 A1 Control Byte Read bits Read Data bits 0 0 0 0 0 0 0 D8 A1D7D6 D5 D4 D3 D2D1D0 A1 STOP bit Read Data bits 0 0 0 0 0 0 0 D8 A1 D7 D6 D5 D4D3 D2 D1D0 A2 P Note1: Master Device is responsible for A / A signal. If a A signal occurs, the MCP44XX will abort this transfer and release the bus. 2: The Master Device will Not Acknowledge, and the MCP44XX will release the bus so the Master Device can generate a Stop or Repeated Start condition. FIGURE 7-6: I2C Continuous Reads. DS22267A-page 62  2010 Microchip Technology Inc.

MCP443X/5X 7.6 Increment Wiper TABLE 7-4: INCREMENT OPERATION VS. Normal and High Voltage VOLATILE WIPER VALUE The Increment Command provides a quick and easy Current Wiper method to modify the potentiometer’s wiper by +1 with Setting Wiper (W) Increment Command minimal overhead. The Increment Command will only Properties 7-bit 8-bit Operates? function on the volatile wiper setting memory locations Pot Pot 00h, 01h, 06h and 07h. 3FFh 3FFh Reserved No Note: Table7-4 shows the valid addresses for 081h 101h (Full-Scale (W = A)) the Increment Wiper command. Other 080h 100h Full-Scale (W = A) No addresses are invalid. 07Fh 0FFh W = N When executing an Increment Command, the volatile 041h 081 wiper setting will be altered from n to n+1 for each 040h 080h W = N (Mid-Scale) Yes Increment Command received. The value will 03Fh 07Fh W = N increment up to 100h max on 8-bit devices and 80h on 001h 001 7-bit devices. If multiple Increment Commands are received after the value has reached 100h (or 80h), the 000h 000h Zero Scale (W = B) Yes value will not be incremented further. Table7-4 shows the Increment Command versus the current volatile 7.6.1 THE HIGH VOLTAGE COMMAND wiper value. (HVC) SIGNAL The Increment Command will most commonly be The High Voltage Command (HVC) signal is performed on the Volatile Wiper locations until a multiplexed with Address 0 (A0) and is used to indicate desired condition is met. The MCP44XX is responsible that the command, or sequence of commands, are in for generating the A bits. the High Voltage mode. Signals > V (~8.5V) on the IHH HVC/A0 pin puts MCP44XX devices into High Voltage Refer to Figure7-7 for the Increment Command mode. sequence. The sequence is terminated by the Stop condition. So when executing a continuous command Note: There is a required delay after the HVC pin string, the Increment command can be followed by any is driven to the V level to the 1st edge other valid command. This means that writes do not IHH of the SCL pin. need to be to the same volatile memory address. The HVC pin has an internal resistor connection to the Note: The command sequence can go from an MCP44XX’s internal VDD signal. increment to any other valid command for the specified address. The advantage of using an Increment Command instead of a read-modify-write series of commands is speed and simplicity. The wiper will transition after each Command Acknowledge when accessing the volatile wiper registers. Write bit Device Fixed Variable Memory Address Address Address Command ADADADAD ADADADAD S 0 1 0 1 1 A1 A0 0 A 3 2 1 0 0 1 x X A 4 3 2 1 0 1 x X A P (2) Control Byte INCR Command (n+1) INCR Command (n+2) Note1: Increment Command (INCR) only functions when accessing the volatile wiper registers (AD3:AD0 = 00h, 01h, 06h, and 07h). 2: This command sequence does not need to terminate (using the Stop bit) and can change to any other desired command sequence (Increment, Read, or Write). FIGURE 7-7: I2C Increment Command Sequence.  2010 Microchip Technology Inc. DS22267A-page 63

MCP443X/5X 7.7 Decrement Wiper TABLE 7-5: DECREMENT OPERATION VS. Normal and High Voltage VOLATILE WIPER VALUE The Decrement Command provides a quick and easy Current Wiper method to modify the potentiometer’s wiper by -1 with Setting Wiper (W) Decrement Command minimal overhead. The Decrement Command will only Properties 7-bit 8-bit Operates? function on the volatile wiper setting memory locations Pot Pot 00h and 01h. 3FFh 3FFh Reserved No Note: Table7-5 shows the valid addresses for 081h 101h (Full-Scale (W = A)) the Decrement Wiper command. Other 080h 100h Full-Scale (W = A) Yes addresses are invalid. 07Fh 0FFh W = N When executing a Decrement Command, the volatile 041h 081 wiper setting will be altered from n to n-1 for each 040h 080h W = N (Mid-Scale) Yes Decrement Command received. The value will 03Fh 07Fh W = N decrement down to 000h min. If multiple Decrement 001h 001 Commands are received after the value has reached 000h, the value will not be decremented further. 000h 000h Zero Scale (W = B) No Table7-5 shows the Increment Command versus the current volatile wiper value. 7.7.1 THE HIGH VOLTAGE COMMAND (HVC) SIGNAL The Decrement Command will most commonly be performed on the Volatile Wiper locations until a The High Voltage Command (HVC) signal is desired condition is met. The MCP44XX is responsible multiplexed with Address 0 (A0) and is used to indicate for generating the A bits. that the command, or sequence of commands, are in the High Voltage mode. Signals > V (~8.5V) on the Refer to Figure7-8 for the Decrement Command IHH HVC/A0 pin puts MCP44XX devices into High Voltage sequence. The sequence is terminated by the Stop mode. condition. So when executing a continuous command string, the Increment command can be followed by any Note: There is a required delay after the HVC pin other valid command. This means that writes do not is driven to the V level to the 1st edge need to be to the same volatile memory address. IHH of the SCL pin. Note: The command sequence can go from an The HVC pin has an internal resistor connection to the increment to any other valid command for MCP44XX’s internal VDD signal. the specified address. The advantage of using a Decrement Command instead of a read-modify-write series of commands is speed and simplicity. The wiper will transition after each Command Acknowledge when accessing the volatile wiper registers. Write bit Device Fixed Variable Memory Address Address Address Command ADADADAD ADADADAD S 0 1 0 1 1 A1 A0 0 A 1 0 X X A 1 0 X X A P (2) 3 2 1 0 4 3 2 1 Control Byte DECR Command (n-1) DECR Command (n-2) Note1: Decrement Command (DECR) only functions when accessing the volatile wiper registers (AD3:AD0 = 00h, 01h, 06h, and 07h). 2: This command sequence does not need to terminate (using the Stop bit) and can change to any other desired command sequence (INCR, Read, or Write). FIGURE 7-8: I2C Decrement Command Sequence. DS22267A-page 64  2010 Microchip Technology Inc.

MCP443X/5X 8.0 APPLICATIONS EXAMPLES The circuit in Figure8-2 shows the method used on the MCP402X Nonvolatile Digital Potentiometer Evaluation Nonvolatile digital potentiometers have a multitude of Board (Part Number: MCP402XEV). This method practical uses in modern electronic circuits. The most requires that the system voltage be approximately 5V. popular uses include precision calibration of set point This ensures that when the PIC10F206 enters a brown- thresholds, sensor trimming, LCD bias trimming, audio out condition, there is an insufficient voltage level on attenuation, adjustable power supplies, motor control the HVC/A0 pin to change the stored value of the wiper. overcurrent trip setting, adjustable gain amplifiers and The MCP402X Nonvolatile Digital Potentiometer Eval- offset trimming. The MCP44XX devices can be used to uation Board User’s Guide (DS51546) contains a replace the common mechanical trim pot in complete schematic. applications where the operating and terminal voltages GP0 is a general purpose I/O pin, while GP2 can either are within CMOS process limitations (V = 2.7V to DD be a general purpose I/O pin or it can output the internal 5.5V). clock. 8.1 Techniques to Force the HVC/A0 For the serial commands, configure the GP2 pin as an input (high impedance). The output state of the GP0 pin Pin to V IHH will determine the voltage on the HVC/A0 pin (V or IL The circuit in Figure8-1 shows a method using the VIH). TC1240A doubling charge pump. When the SHDN pin For high-voltage serial commands, force the GP0 is high, the TC1240A is off, and the level on the HVC/ output pin to output a high level (V ) and configure the OH A0 pin is controlled by the PIC® microcontrollers GP2 pin to output the internal clock. This will form a (MCUs) IO2 pin. charge pump and increase the voltage on the CS pin When the SHDN pin is low, the TC1240A is on and the (when the system voltage is approximately 5V). V voltage is 2 * V . The resistor R allows the OUT DD 1 HVC/A0 pin to go higher than the voltage such that the PIC MCU’s IO2 pin “clamps” at approximately V . DD PIC10F206 R 1 GP0 TC1240A MCP4XXX PIC MCU VIN C+ C1 SHDN C- GP2 HVC/A0 V IO1 OUT C1 C2 MCP4XXX R 1 HVC/A0 IO2 FIGURE 8-2: MCP4XXX Nonvolatile C 2 Digital Potentiometer Evaluation Board (MCP402XEV) implementation to generate the V voltage. IHH FIGURE 8-1: Using the TC1240A to Generate the V Voltage. IHH  2010 Microchip Technology Inc. DS22267A-page 65

MCP443X/5X 8.2 Using Shutdown Modes 8.3 Software Reset Sequence Figure8-3 shows a possible application circuit where Note: This technique is documented in AN1028. the independent terminals could be used. Disconnecting the wiper allows the transistor input to At times, it may become necessary to perform a be taken to the Bias voltage level (disconnecting A and Software Reset Sequence to ensure the MCP44XX or B may be desired to reduce system current). device is in a correct and known I2C Interface state. Disconnecting Terminal A modifies the transistor input This technique only resets the I2C state machine. by the RBW rheostat value to the Common B. This is useful if the MCP44XX device powers up in an Disconnecting Terminal B modifies the transistor input incorrect state (due to excessive bus noise, etc), or if by the RAW rheostat value to the Common A. The the Master Device is reset during communication. Common A and Common B connections could be Figure8-4 shows the communication sequence to connected to VDD and VSS. software reset the device. S ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ S P Common A Nine bits of ‘1’ Start bit Input Start A bit Stop bit FIGURE 8-4: Software Reset Sequence Format. The 1st Start bit will cause the device to reset from a To base W state in which it is expecting to receive data from the of Transistor Master Device. In this mode, the device is monitoring (or Amplifier) the data bus in Receive mode and can detect the Start bit forces an internal Reset. The nine bits of ‘1’ are used to force a Reset of those devices that could not be reset by the previous Start bit. B This occurs only if the MCP44XX is driving an A bit on the I2C bus, or is in output mode (from a Read Input command) and is driving a data bit of ‘0’ onto the I2C bus. In both of these cases, the previous Start bit could not be generated due to the MCP44XX holding the bus Common B low. By sending out nine ‘1’ bits, it is ensured that the device will see a A bit (the Master Device does not drive Balance Bias the I2C bus low to acknowledge the data sent by the MCP44XX), which also forces the MCP44XX to Reset. FIGURE 8-3: Example Application Circuit The 2nd Start bit is sent to address the rare possibility using Terminal Disconnects. of an erroneous write. This could occur if the Master Device was reset while sending a Write command to the MCP44XX, AND then as the Master Device returns to normal operation and issues a Start condition while the MCP44XX is issuing an Acknowledge. In this case, if the 2nd Start bit is not sent (and the Stop bit was sent) the MCP44XX could initiate a write cycle. Note: The potential for this erroneous write ONLY occurs if the Master Device is reset while sending a Write command to the MCP44XX. The Stop bit terminates the current I2C bus activity. The MCP44XX waits to detect the next Start condition. This sequence does not effect any other I2C devices which may be on the bus, as they should disregard this as an invalid command. DS22267A-page 66  2010 Microchip Technology Inc.

MCP443X/5X 8.4 Using the General Call Command Figure8-5 shows two I2C bus configurations. In many cases, the single I2C bus configuration will be The use of the General Call Address Increment, adequate. For applications that do not want all the Decrement, or Write commands is analogous to the MCP44XX devices to do General Call support or have “Load” feature (LDAC pin) on some DACs (such as the a conflict with General Call commands, the multiple I2C MCP4921). This allows all the devices to “Update” the bus configuration would be used. output level “at the same time”. For some applications, the ability to update the wiper Single I2C Bus Configuration values “at the same time” may be a requirement, since they delay from writing to one wiper value and then the next may cause application issues. A possible example Device 1 Device 3 Device n would be a “tuned” circuit that uses several MCP44XX Host in rheostat configuration. As the system condition Controller changes (temperature, load, etc.) these devices need Device 2 Device 4 to be changed (incremented/decremented) to adjust for the system change. These changes will either be in the same direction or in opposite directions. With the Multiple I2C Bus Configuration Potentiometer device, the customer can either select the PxB terminals (same direction) or the PxA Device 1a Device 3a Device na terminal(s) (opposite direction). Host Bus a Figure8-6 shows that the update of six devices takes Controller 6*T time in “normal” operation, but only I2CDLY Device 2a Device 4a 1*T time in “General Call” operation. I2CDLY Note: The application system may need to Device 1b Device 3b Device nb partition the I2C bus into multiple busses to Bus b ensure that the MCP44XX General Call commands do not conflict with the General Call commands that the other I2C devices Device 2b Device 4b may have defined. Also if only a portion of the MCP44XX devices are to require this Device 1n Device 3n Device nn synchronous operation, then the devices Bus n that should not receive these commands should be on the second I2C bus. Device 2n Device 4n FIGURE 8-5: Typical Application I2C Bus Configurations. Normal Operation INC INC INC INC INC INC POT01 POT02 POT03 POT04 POT05 POT06 T T T T T T I2CDLY I2CDLY I2CDLY I2CDLY I2CDLY I2CDLY General Call Operation INC INC INC INC INC INC POTs 01-06 POTs 01-06 POTs 01-06 POTs 01-06 POTs 01-06 POTs 01-06 T T T T T T I2CDLY I2CDLY I2CDLY I2CDLY I2CDLY I2CDLY T = Time from one I2C command completed to completing the next I2C command. I2CDLY FIGURE 8-6: Example Comparison of “Normal Operation” vs. “General Call Operation” Wiper Updates.  2010 Microchip Technology Inc. DS22267A-page 67

MCP443X/5X 8.5 Implementing Log Steps with a EQUATION 8-1: dB CALCULATIONS Linear Digital Potentiometer (VOLTAGE) In audio volume control applications, the use of L = 20 * log10 (VOUT / VIN) logarithmic steps is desirable since the human ear hears in a logarithmic manner. The use of a linear dB V / V Ratio potentiometer can approximate a log potentiometer, OUT IN but with fewer steps. An 8-bit potentiometer can -3 0.70795 achieve fourteen 3dB log steps plus a 100% (0dB) -2 0.79433 and a mute setting. -1 0.89125 Figure8-7 shows a block diagram of one of the MCP44x1 resistor networks being used to attenuate an input signal. In this case, the attenuation will be ground EQUATION 8-2: dB CALCULATIONS referenced. Terminal B can be connected to a common (RESISTANCE) - CASE 1 mode voltage, but the voltages on the A, B and Wiper Terminal B connected to Ground (see Figure8-7) terminals must not exceed the MCP44x1’s V /V DD SS voltage limits. L = 20 * log (R / R ) 10 BW AB MCP44X1 EQUATION 8-3: dB CALCULATIONS (RESISTANCE) - CASE 2 P0A Terminal B through R to Ground B2GND P0W L = 20 * log ( (R + R ) / (R + R ) ) 10 BW B2GND AB B2GND P0B Table8-1 shows the codes that can be used for 8-bit digital potentiometers to implement the log attenuation. The table shows the wiper codes for -3dB, -2dB, and FIGURE 8-7: Signal Attenuation Block -1dB attenuation steps. This table also shows the Diagram - Ground Referenced. calculated attenuation based on the wiper code’s linear step. Calculated attenuation values less than the Equation8-1 shows the equation to calculate voltage desired attenuation are shown with red text. At lower dB gain ratios for the digital potentiometer, while wiper code values, the attenuation may skip a step, if Equation8-2 shows the equation to calculate this occurs the next attenuation value is colored resistance dB gain ratios. These two equations assume magenta to highlight that a skip occurred. For example, that the B terminal is connected to ground. in the -3dB column the -48dB value is highlighted If terminal B is not directly resistively connected to since the -45dB step could not be implemented (there ground, then this terminal B to ground resistance are no wiper codes between 2 and 1). (R ) must be included into the calculation. B2GND Equation8-3 shows this equation. DS22267A-page 68  2010 Microchip Technology Inc.

MCP443X/5X TABLE 8-1: LINEAR TO LOG ATTENUATION FOR 8-BIT DIGITAL POTENTIOMETERS -3dB Steps -2dB Steps -1dB Steps # of Calculated Calculated Calculated Steps Desired Wiper Attenuation Desired Wiper Attenuation Desired Wiper Attenuation Attenuation Code Attenuation Code Attenuation Code (1) (1) (1) 0 0dB 256 0dB 0dB 256 0dB 0dB 256 0dB 1 -3dB 181 -3.011dB -2dB 203 -2.015dB -1dB 228 -1.006dB 2 -6dB 128 -6.021dB -4dB 162 -3.975dB -2dB 203 -2.015dB 3 -9dB 91 -8.984dB -6dB 128 -6.021dB -3dB 181 -3.011dB 4 -12dB 64 -12.041dB -8dB 102 -7.993dB -4dB 162 -3.975dB 5 -15dB 46 -14.910dB -10dB 81 -9.995dB -5dB 144 -4.998dB 6 -18dB 32 -18.062dB -12dB 64 -12.041dB -6dB 128 -6.021dB 7 -21dB 23 -20.930dB -14dB 51 -14.013dB -7dB 114 -7.027dB 8 -24dB 16 -24.082dB -16dB 41 -15.909dB -8dB 102 -7.993dB 9 -27dB 11 -27.337dB -18dB 32 -18.062dB -9dB 91 -8.984dB 10 -30dB 8 -30.103dB -20dB 26 -19.865dB -10dB 81 -9.995dB 11 -33dB 6 -32.602dB -22dB 20 -22.144dB -11dB 72 -11.018dB 12 -36dB 4 -36.124dB -24dB 16 -24.082dB -12dB 64 -12.041dB 13 -39dB 3 -38.622dB -26dB 13 -25.886dB -13dB 57 -13.047dB 14 -42dB 2 -42.144dB -28dB 10 -28.165dB -14dB 51 -14.013dB 15 -48dB 1 -48.165dB -30dB 8 -30.103dB -15dB 46 - 14.910dB 16 Mute 0 Mute -32dB 6 -32.602dB -16dB 41 -15.909dB 17 -34dB 5 -34.185dB -17dB 36 -17.039dB 18 -36dB 4 -36.124dB -18dB 32 -18.062dB 19 -38dB 3 -38.622dB -19dB 29 -18.917dB 20 -42dB 2 -42.144dB -20dB 26 -19.865dB 21 -48dB 1 -48.165dB -21dB 23 - 20.930dB 22 Mute 0 Mute -22dB 20 -22.144dB 23 -23dB 18 -23.059dB 24 -24dB 16 -24.082dB 25 -25dB 14 -25.242dB 26 -26dB 13 -25.886dB 27 -27dB 11 -27.337dB 28 -28dB 10 -28.165dB 29 -29dB 9 -29.080dB 30 -30dB 8 -30.103dB 31 -31dB 7 -31.263dB 32 -33dB 6 -32.602dB 33 -34dB 5 -34.185dB 34 -36dB 4 -36.124dB 35 -39dB 3 -38.622dB 36 -42dB 2 -42.144dB 37 -48dB 1 -48.165dB 38 Mute 0 Mute Note 1: Attenuation values do not include errors from Digital Potentiometer errors, such as Full Scale Error or Zero Scale Error.  2010 Microchip Technology Inc. DS22267A-page 69

MCP443X/5X 8.6 Design Considerations 8.6.2 LAYOUT CONSIDERATIONS In the design of a system with the MCP44XX devices, Several layout considerations may be applicable to the following considerations should be taken into your application. These may include: account: • Noise • Power Supply Considerations • Footprint Compatibility • Layout Considerations • PCB Area Requirements 8.6.1 POWER SUPPLY 8.6.2.1 Noise CONSIDERATIONS Inductively-coupled AC transients and digital switching The typical application will require a bypass capacitor noise can degrade the input and output signal integrity, in order to filter high-frequency noise, which can be potentially masking the MCP44XX’s performance. induced onto the power supply's traces. The bypass Careful board layout minimizes these effects and capacitor helps to minimize the effect of these noise increases the Signal-to-Noise Ratio (SNR). Multi-layer sources on signal integrity. Figure8-8 illustrates an boards utilizing a low-inductance ground plane, appropriate bypass strategy. isolated inputs, isolated outputs and proper decoupling are critical to achieving the performance that the silicon In this example, the recommended bypass capacitor is capable of providing. Particularly harsh value is 0.1µF. This capacitor should be placed as environments may require shielding of critical signals. close (within 4mm) to the device power pin (V ) as DD possible. If low noise is desired, breadboards and wire-wrapped boards are not recommended. The power source supplying these devices should be as clean as possible. If the application circuit has 8.6.2.2 Footprint Compatibility separate digital and analog power supplies, V and DD V should reside on the analog plane. The specification of the MCP44XX pinouts was done to SS allow systems to be designed to easily support the use of either the dual (MCP46XX) or quad (MCP44XX) V device. DD Figure8-9 shows how the dual pinout devices fit on the quad device footprint. For the Rheostat devices, the 0.1µF dual device is in the MSOP package, so the footprints V would need to be offset from each other. DD MCP44X1 Quad Potentiometers 0.1µF P3A 1 20 P2A r e P3W 2 19 P2W oll P3B 3 18 P2B r nt HVC/A0 4 17 VDD SCL o SCL 5 16 A1 c A X/5X HVCS/DAA0 Micro SPVD1SABS 678 111452 RWP0EPBSET MCP42X1 Pinout (1) W 3 A1 M P1W 9 12 P0W 4 T 4 C P1A 10 11 P0A P PI C TSSOP M B MCP44X2 Quad Rheostat P3W 1 14 P2W P3B 2 13 P2B HVC/A0 3 12 VDD VSS VSS SCL 4 11 A1 SDA 5 10 P0B MCP42X2 Pinout FIGURE 8-8: Typical Microcontroller VSS 6 9 P0W Connections. P1B 7 8 P1W TSSOP Note 1: Pin 15 (RESET) is the Address A2 (A2) pin on the MCP46x1 device. FIGURE 8-9: Quad Pinout (TSSOP Package) vs. Dual Pinout. DS22267A-page 70  2010 Microchip Technology Inc.

MCP443X/5X Figure8-10 shows possible layout implementations for 8.6.2.3 PCB Area Requirements an application to support the quad and dual options on In some applications, PCB area is a criteria for device the same PCB. selection. Table8-2 shows the package dimensions and area for the different package options. The table Potentiometers Devices also shows the relative area factor compared to the smallest area. For space critical applications, the QFN package would be the suggested package. MCP44X1 TABLE 8-2: PACKAGE FOOTPRINT (1) MCP46X1 Package Package Footprint Dim(emnmsi)o ns 2m) Area ns Type Code m e Pi X Y ea ( ativ Ar el R Rheostat Devices 14 TSSOP ST 5.10 6.40 32.64 2.04 MCP46X2 QFN ML 4.00 4.00 16.00 1 20 MCP44X2 TSSOP ST 6.60 6.40 42.24 2.64 Note1: Does not include recommended land pattern dimensions. 8.6.3 RESISTOR TEMPCO Characterization curves of the resistor temperature coefficient (Tempco) are shown in Figure2-11, FIGURE 8-10: Layout to Support Quad and Figure2-32, Figure2-52, and Figure2-72. Dual Devices. These curves show that the resistor network is designed to correct for the change in resistance as temperature increases. This technique reduces the end to end change is R resistance. AB 8.6.4 HIGH VOLTAGE TOLERANT PINS High Voltage support (V ) on the Serial Interface pins IHH is for compatibility with the non-volatile devices.  2010 Microchip Technology Inc. DS22267A-page 71

MCP443X/5X NOTES: DS22267A-page 72  2010 Microchip Technology Inc.

MCP443X/5X 9.0 DEVELOPMENT SUPPORT 9.2 Technical Documentation Several additional technical documents are available to 9.1 Development Tools assist you in your design and development. These technical documents include Application Notes, Several development tools are available to assist in Technical Briefs, and Design Guides. Table9-2 shows your design and evaluation of the MCP44XX devices. some of these documents. The currently available tools are shown in Table9-1. These boards may be purchased directly from the Microchip web site at www.microchip.com. TABLE 9-1: DEVELOPMENT TOOLS Board Name Part # Supported Devices 20-pin TSSOP and SSOP Evaluation Board TSSOP20EV MCP44XX MCP46XX Digital Potentiometer PICtail Plus Demo MCP46XXDM-PTPLS MCP46XX Board (1, 2) MCP46XX Digital Potentiometer Evaluation Board (2) MCP46XXEV MCP46X1 Note1: Requires a PICDEM Demo board. See the User’s Guide for additional information and requirements. 2: Requires a PICkit Serial Analyzer. See the User’s Guide for additional information and requirements. TABLE 9-2: TECHNICAL DOCUMENTATION Application Title Literature # Note Number AN1316 Using Digital Potentiometers for Programmable Amplifier Gain DS01316 AN1080 Understanding Digital Potentiometers Resistor Variations DS01080 AN737 Using Digital Potentiometers to Design Low-Pass Adjustable Filters DS00737 AN692 Using a Digital Potentiometer to Optimize a Precision Single Supply Photo Detect DS00692 AN691 Optimizing the Digital Potentiometer in Precision Circuits DS00691 AN219 Comparing Digital Potentiometers to Mechanical Potentiometers DS00219 — Digital Potentiometer Design Guide DS22017 — Signal Chain Design Guide DS21825  2010 Microchip Technology Inc. DS22267A-page 73

MCP443X/5X NOTES: DS22267A-page 74  2010 Microchip Technology Inc.

MCP443X/5X 10.0 PACKAGING INFORMATION 10.1 Package Marking Information 14-Lead TSSOP Example XXXXXXXX 4452502E YYWW 1035 NNN 256 20-Lead QFN (4x4) Example XXXXX 4451 XXXXXX 502EML XXXXXX e^3^1035 YYWWNNN 256 20-Lead TSSOP Example XXXXXXXX 4451502 XXXXX NNN EST ^e^3256 YYWW 1035 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2010 Microchip Technology Inc. DS22267A-page 75

MCP443X/5X Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22267A-page 76  2010 Microchip Technology Inc.

MCP443X/5X Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2010 Microchip Technology Inc. DS22267A-page 77

MCP443X/5X Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22267A-page 78  2010 Microchip Technology Inc.

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(cid:25)5 (cid:4)(cid:20)(cid:3)(cid:4)(cid:2)(cid:26)6> H(cid:31)(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)N(cid:7)#&(cid:11) 6 (cid:23)(cid:20)(cid:4)(cid:4)(cid:2);(cid:22)< 6$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:30)(cid:28)#(cid:2)N(cid:7)#&(cid:11) 6(cid:3) (cid:3)(cid:20)O(cid:4) (cid:3)(cid:20)(cid:5)(cid:4) (cid:3)(cid:20)L(cid:4) H(cid:31)(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)A(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:23)(cid:20)(cid:4)(cid:4)(cid:2);(cid:22)< 6$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:30)(cid:28)#(cid:2)A(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21)(cid:3) (cid:3)(cid:20)O(cid:4) (cid:3)(cid:20)(cid:5)(cid:4) (cid:3)(cid:20)L(cid:4) <(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)N(cid:7)#&(cid:11) ) (cid:4)(cid:20)(cid:29)L (cid:4)(cid:20)(cid:3)8 (cid:4)(cid:20)5(cid:4) <(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)A(cid:14)(cid:15)(cid:17)&(cid:11) A (cid:4)(cid:20)5(cid:4) (cid:4)(cid:20)(cid:23)(cid:4) (cid:4)(cid:20)8(cid:4) <(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:27)&(cid:10)(cid:27)6$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:30)(cid:28)# Q (cid:4)(cid:20)(cid:3)(cid:4) R R (cid:20)(cid:21)(cid:13)(cid:6)(cid:12)% (cid:29)(cid:20) (cid:30)(cid:7)(cid:15)(cid:2)(cid:29)(cid:2)(cid:31)(cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2)(cid:31)(cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) (cid:30)(cid:28)(cid:8)+(cid:28)(cid:17)(cid:14)(cid:2)(cid:7)!(cid:2)!(cid:28)*(cid:2)!(cid:7)(cid:15)(cid:17)"(cid:16)(cid:28)&(cid:14)#(cid:20) 5(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6)6(cid:2)7(cid:29)(cid:23)(cid:20)8(cid:6)(cid:20) ;(cid:22)<= ;(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2)(cid:31)(cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26)6>= (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)<(cid:4)(cid:23)(cid:27)(cid:29)(cid:3)O;  2010 Microchip Technology Inc. DS22267A-page 79

MCP443X/5X (cid:20)(cid:21)(cid:13)(cid:6)% >(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)+(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:30)(cid:28)(cid:8)+(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)=??***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’?(cid:12)(cid:28)(cid:8)+(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) DS22267A-page 80  2010 Microchip Technology Inc.

MCP443X/5X (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)&’(cid:14)((cid:9))’*(cid:14)((cid:22)(cid:9)) (cid:7)(cid:11)(cid:11)(cid:9)+(cid:17)(cid:13)(cid:11)(cid:14)((cid:6)(cid:9)(cid:24))&(cid:26)(cid:9)(cid:27)(cid:9)(cid:28)(cid:30)(cid:28)(cid:9) (cid:9)!(cid:21)(cid:8)"(cid:9)#&))+(cid:10)$ (cid:20)(cid:21)(cid:13)(cid:6)% >(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)+(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:30)(cid:28)(cid:8)+(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)=??***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’?(cid:12)(cid:28)(cid:8)+(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D N E E1 NOTE1 1 2 b e c φ A A2 A1 L1 L @(cid:15)(cid:7)&! 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(cid:25)(cid:3) (cid:4)(cid:20)L(cid:4) (cid:29)(cid:20)(cid:4)(cid:4) (cid:29)(cid:20)(cid:4)8 (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2) (cid:25)(cid:29) (cid:4)(cid:20)(cid:4)8 R (cid:4)(cid:20)(cid:29)8 H(cid:31)(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)N(cid:7)#&(cid:11) 6 O(cid:20)(cid:23)(cid:4)(cid:2);(cid:22)< (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:30)(cid:28)(cid:8)+(cid:28)(cid:17)(cid:14)(cid:2)N(cid:7)#&(cid:11) 6(cid:29) (cid:23)(cid:20)5(cid:4) (cid:23)(cid:20)(cid:23)(cid:4) (cid:23)(cid:20)8(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:30)(cid:28)(cid:8)+(cid:28)(cid:17)(cid:14)(cid:2)A(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) O(cid:20)(cid:23)(cid:4) O(cid:20)8(cid:4) O(cid:20)O(cid:4) >(cid:10)(cid:10)&(cid:2)A(cid:14)(cid:15)(cid:17)&(cid:11) A (cid:4)(cid:20)(cid:23)8 (cid:4)(cid:20)O(cid:4) (cid:4)(cid:20)(cid:5)8 >(cid:10)(cid:10)&(cid:12)(cid:9)(cid:7)(cid:15)& A(cid:29) (cid:29)(cid:20)(cid:4)(cid:4)(cid:2)(cid:26)6> >(cid:10)(cid:10)&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)U R LU A(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)+(cid:15)(cid:14)!! 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DS22267A-page 81

MCP443X/5X Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22267A-page 82  2010 Microchip Technology Inc.

MCP443X/5X APPENDIX A: REVISION HISTORY Revision A (November 2010) • Original release of this document.  2010 Microchip Technology Inc. DS22267A-page 83

MCP443X/5X NOTES: DS22267A-page 84  2010 Microchip Technology Inc.

MCP443X/5X APPENDIX B: CHARACTERIZATION B.1 Low-Voltage Operation DATA ANALYSIS This appendix gives an overview of CMOS semiconductor characteristics at lower voltages. This is Some designers may want to understand the device important so that the 1.8V resistor network operational characteristics outside of the specified characterization graphs of the MCP443X/5X devices operating conditions of the device. can be better understood. Applications where the knowledge of the resistor For this discussion, we will use the 5k device data. network characteristics could be useful include battery This data was chosen since the variations of wiper powered devices and applications that experience resistance have much greater implications for devices brown-out conditions. with smaller R resistances. AB In battery applications, the application voltage decays FigureB-1 shows the worst case R error from the over time until new batteries are installed. As the BW average R as a percentage, while FigureB-2 shows voltage decays, the system will continue to operate. At BW the R resistance versus the wiper code graph. some voltage level, the application will be below its BW Non-linear behavior occurs at approximately wiper specified operating voltage range. This is dependent code 160. This is better shown in FigureB-2, where the on the individual components used in the design. It is R resistance changes from a linear slope. This still useful to understand the device characteristics to BW change is due to the change in the wiper resistance. expect when this low-voltage range is encountered. Unlike a microcontroller, which can use an external supervisor device to force the controller into the Reset 2.00% state, a digital potentiometer’s resistance characteristic 1.00% is not specified. But understanding the operational 0.00% characteristics can be important in the design of the -1.00% applications circuit for this low-voltage condition. or %-2.00% Other application system scenarios where Err-3.00% understanding the low-voltage characteristics of the -4.00% -40C resistor network could be important is for system brown -5.00% +25C out conditions. -6.00% +85C +125C -7.00% For the MCP443X/5X devices, the analog operation is 0 32 64 96 128 160 192 224 256 specified at a minimum of 2.7V. Device testing has Ter- Wiper Code minal A connected to the device V (for the DD potentiometer configuration only) and Terminal B FIGURE B-1: 1.8V Worst Case RBW Error connected to VSS. from Average RBW (RBW0-RBW3) vs. Wiper Code and Temperature (V = 1.8V, I = 190µA). DD W 7000 6000 5000 (cid:2)) ce (4000 n a st3000 si e R2000 -40C +25C 1000 +85C +125C 0 0 32 64 96 128 160 192 224 256 Wiper Code FIGURE B-2: R vs. Wiper Code And BW Temperature (V = 1.8V, I = 190µA). DD W  2010 Microchip Technology Inc. DS22267A-page 85

MCP443X/5X FigureB-3 and FigureB-4 show the wiper resistance The method in which the data was collected is for V voltages of 5.5, 3.0, 1.8 Volts. These graphs important to understand. FigureB-5 shows the DD show that as the resistor ladder wiper node voltage technique that was used to measure the R and R BW W (V ) approaches the V /2 voltage, the wiper resistance. In this technique, Terminal A is floating and WCn DD resistance increases. These graphs also show the Terminal B is connected to ground. A fixed current is different resistance characteristics of the NMOS and then forced into the wiper (I ) and the corresponding W PMOS transistors that make up the wiper switch. This wiper voltage (V ) is measured. Forcing a known W is demonstrated by the wiper code resistance curve, current through R (I ) and then measuring the BW W which does not mirror itself around the mid-scale code voltage difference between the wiper (V ) and W (wiper code = 128). Terminal A (V ), the wiper resistance (R ) can be A W calculated, see FigureB-5. Changes in I current will So why are the R graphs showing the maximum W W change the wiper voltage (V ). This may affect the resistance at about mid-scale (wiper code = 128) and W device’s wiper resistance (R ). the R graphs showing the issue at code 160? W BW This requires understanding low-voltage transistor floating characteristics as well as how the data was measured. V A A V W 220 W 200 -40C @ 3.0V +25C @ 3.0V +85C @ 3.0V +125C @ 3.0V -40C @5.5V +25C @ 5.5V +85C @ 5.5V +125C @ 5.5V 180 I W R = V /I (cid:2))160 BW W W ance (112400 B VB RW = (VW-VA)/IW sist100 e R 80 FIGURE B-5: R and R Measurement. BW W 60 40 FigureB-6 shows a block diagram of the resistor 20 network where the RAB resistor is a series of 256 RS 0 64 128 192 256 resistors. These resistors are polysilicon devices. Each Wiper Code wiper switch is an analog switch made up of an NMOS and PMOS transistor. A more detailed figure of the FIGURE B-3: Wiper Resistance (R ) vs. W wiper switch is shown in FigureB-7. The wiper Wiper Code and Temperature resistance is influenced by the voltage on the wiper (V = 5.5V, I = 900µA; V = 3.0V, DD W DD switches nodes (V , V and V ). Temperature also G W WCn IW = 480µA). influences the characteristics of the wiper switch, see FigureB-4. The NMOS transistor and PMOS transistor have 2020 -40C @ 1.8V different characteristics. These characteristics, as well +25C @ 1.8V as the wiper switch node voltages, determine the R +85C @ 1.8V W (cid:2))1520 +125C @ 1.8V resistance at each wiper code. The variation of each e ( wiper switch’s characteristics in the resistor network is c n sta1020 greater then the variation of the RS resistors. si Re The voltage on the resistor network node (VWCn) is 520 dependent upon the wiper code selected and the voltages applied to V , V and V . The wiper switch V A B W G 20 voltage to V or V voltage determines how strongly W WCn 0 64 128 192 256 the transistor is turned on. When the transistor is Wiper Code weakly turned on, the wiper resistance R will be high. W FIGURE B-4: Wiper Resistance (R ) vs. When the transistor is strongly turned on, the wiper W resistance (R ) will be in the typical range. Wiper Code and Temperature W (V = 1.8V, I = 260µA). DD W DS22267A-page 86  2010 Microchip Technology Inc.

MCP443X/5X So looking at the wiper voltage (V ) for the W A 3.0Vand1.8V data gives the graphs in FigureB-8 and VA FigureB-9. In the 1.8V graph, as the VW approaches 0.8V, the voltage increases nonlinearly. Since V=I*R, and the current (I ) is constant, it means that the W N n device resistance increased nonlinearly at around R RW (1) wiper code 160. S N RnS-1 RW (1) DVG 1.2 1.0 Nn-2 VWC(n-2) NPMMOOSS e (V) 0.8 RABRS oltag 0.6 Nn-3 RW (1) er V 0.4 -40C W p Wi +25C VW 0.2 +85C +125C N 0.0 1 R (1) 0 32 64 96 128 160 192 224 256 RS W Wiper Code FIGURE B-8: Wiper Voltage (V ) vs. N W 0 R (1) Wiper Code (VDD = 3.0V, IW = 190µA). W VB 1.4 B 1.2 Note1: The wiper resistance is dependent on V)1.0 several factors including, wiper code, e ( danedvi cWe) ,V aDnDd, tTeemrmpeinraatlu rveo.l tages (on A, B Voltag00..68 er -40C FIGURE B-6: Resistor Network Block Wip0.4 +25C Diagram. 0.2 +85C +125C The characteristics of the wiper are determined by the 0.0 0 32 64 96 128 160 192 224 256 characteristics of the wiper switch at each of the Wiper Code resistor networks tap points. FigureB-7 shows an example of a wiper switch. As the device operational FIGURE B-9: Wiper Voltage (V ) vs. W voltage becomes lower, the characteristics of the wiper Wiper Code (V = 1.8V, I = 190µA). DD W switch change due to a lower voltage on the V signal. G FigureB-7 shows an implementation of a wiper switch. When the transistor is turned off, the switch resistance is in the Giga s. When the transistor is turned on, the switch resistance is dependent on the V , V and G W V voltages. This resistance is referred to as R . WCn W R (1) W V (V /V ) G DD SS “gate” NMOS NWC Wiper VWCn PMOS VW “gate” Note1: Wiper Resistance (R ) depends on the W voltages at the wiper switch nodes (V , V and V ). G W WCn FIGURE B-7: Wiper Switch.  2010 Microchip Technology Inc. DS22267A-page 87

MCP443X/5X Using the simulation models of the NMOS and PMOS devices for the MCP44XX analog switch (FigureB-10), 7.00E+09 160 we plot the device resistance when the devices are RNMOS trVsdvrueeioeImrsNslvntii apssievcgttlodyeaael snntt ah cco(geeenRfoe s.pW r bia so Fer= ftaiic gh nltoRluehcemNrr elee M eraNeNBsOssM M-Sei1sv OdO1|te|a. S SrRnTya c hPanelaeMnad d odOr wg n SFieP p)Pti .gheM M(ueBrGO r OerNeeiSlgSoMsB awi dsO-o1 tedhatS2hvemn ieavccs seinetc)hhsd. e (or RsPeaIw,nsWsM h )Otttto hhhh liSdeeees OS and PMOS Resistance ((cid:2))23456.....0000000000EEEEE+++++0000099999 RPMOS PTRhMeWOs Sh olNTdhMeOsSho ld 468111000024000 Wiper Resistance ((cid:2)) transistors active region, the resistance is much lower. NM 1.00E+09 20 For these graphs, the resistances are on different 0.00E+00 0 scales. FigureB-13 and FigureB-14 only plot the 0.0 0.6 1.2 1.8 2.4 3.0 VIN Voltage NMOS and PMOS device resistance for their active region and the resulting wiper resistance. For these FIGURE B-12: NMOS and PMOS graphs, all resistances are on the same scale. Transistor Resistance (RNMOS, RPMOS) and Wiper Resistance (R ) VS. V W IN (V = 1.8V). R DD W V (V /V ) G DD SS “gate” 300 NMOS VIN VOUT 250 PMOS “gate” e ((cid:2)) 200 RNMOS RPMOS nc 150 a FIGURE B-10: Analog Switch. esist 100 R RW 50 3.00E+10 2500 RW RNMOS 0 PMOS Resistance ((cid:2))122...505000EEE+++111000 RPMOS 112050000000 Resistance ((cid:2)) FTWrIaGipnUesrRi sREtoe0 .rBs0 Ri-s1eta3sn:i0sc.t6ea n(RcNe 1M().V2R IVNO NVSSoMl.t a OaVg1Sen.8,d R PPMM2OO.4SS) an3d.0 NMOS and 51..0000EE++0190 PThMeOsSh old NThMeOsSho ld 500 Wiper ( VDD = 3.0V). W IN 0.00E+00 0 5000 0.0 0.3 0.6 0.9 1.2 1.5 1.8 VIN Voltage 4500 4000 FIGURE B-11: NMOS and PMOS 3500 TWraipnesri sRtoers Risetasnisctea n(RceW ()R VNSM. OVSIN, RPMOS) and ance ((cid:2))23500000 RNMOS RPMOS (VDD = 3.0V). Resist12500000 RW 1000 500 0 0.0 0.3 0.6 0.9 1.2 1.5 1.8 VIN Voltage FIGURE B-14: NMOS and PMOS Transistor Resistance (R , R ) and NMOS PMOS Wiper Resistance (R ) VS. V W IN (V = 1.8V). DD DS22267A-page 88  2010 Microchip Technology Inc.

MCP443X/5X B.2 Optimizing Circuit Design for Low-Voltage Characteristics R1 The low-voltage nonlinear characteristics can be V A minimized by application design. The section will show A V W two application circuits that can be used to control a W programmable reference voltage (VOUT). VOUT Minimizing the low-voltage nonlinear characteristics is done by keeping the voltages on the wiper switch B nodes at a voltage where either the NMOS or PMOS V B transistor is turned on. R2 An example of this is if we are using a digital potentiometer for a voltage reference (V ). Let’s say OUT that we want V to range from 0.5 * V to 0.6 * V . FIGURE B-15: Example Implementation #1. OUT DD DD In example implementation #1 (FigureB-15), we TABLE B-1: EXAMPLE #1 VOLTAGE window the digital potentiometer using resistors R1 and CALCULATIONS R2. When the wiper code is at full scale, the V OUT voltage will be  0.6 * VDD, and when the wiper code is Variation at zero scale the V voltage will be  0.5 * V . OUT DD Remember that the digital potentiometers R variation Min Typ Max AB must be included. TableB-1 shows that the VOUT R1 12,000 12,000 12,000 voltage can be selected to be between 0.455 * V and DD R2 20,000 20,000 20,000 0.727 * V , which includes the desired range. With DD respect to the voltages on the resistor network node, at RAB 8,000 10,000 12,000 1.8V the VA voltage would range from 1.29V to 1.31V VOUT (@ FS) 0.714 VDD 0.70 VDD 0.727 VDD while the V voltage would range from 0.82V to 0.86V. B V (@ ZS) 0.476 V 0.50 V 0.455 V OUT DD DD DD These voltages cause the wiper resistance to be in the V 0.714 V 0.70 V 0.727 V nonlinear region (seeFigureB-12).In Potentiometer A DD DD DD mode, the variation of the wiper resistance is typically VB 0.476 VDD 0.50 VDD 0.455 VDD not an issue, as shown by the INL/DNL graph Legend: FS – Full Scale, ZS – Zero Scale (Figure2-6). In example implementation #2 (FigureB-16) we use the digital potentiometer in Rheostat mode. The resistor ladder uses resistors R1 and R2 with R at BW the bottom of the ladder. When the wiper code is at full scale, the V voltage will be  0.6 * V and when OUT DD the wiper code is at full scale the V voltage will be OUT  0.5 * V . Remember that the digital potentiometers DD R variation must be included. TableB-2 shows that AB the V voltage can be selected to be between 0.50 * OUT V and 0.687 * V , which includes the desired DD DD range. With respect to the voltages on the resistor network node, at 1.8V the V voltage would range from W 0.29V to 0.38V. These voltages cause the wiper resistance to be in the linear region (see FigureB-12).  2010 Microchip Technology Inc. DS22267A-page 89

MCP443X/5X R1 V OUT R2 V A A W V W B V B FIGURE B-16: Example Implementation #2. TABLE B-2: EXAMPLE #2 VOLTAGE CALCULATIONS Variation Min Typ Max R1 10,000 10,000 10,000 R2 10,000 10,000 10,000 R (max) 8,000 10,000 12,000 BW V (@ FS) 0.667 V 0.643 V 0.687 V OUT DD DD DD V (@ ZS) 0.50 V 0.50 V 0.50 V OUT DD DD DD V (@ FS) 0.333 V 0.286 V 0.375 V W DD DD DD V (@ ZS) V V V W SS SS SS Legend: FS – Full Scale, ZS – Zero Scale DS22267A-page 90  2010 Microchip Technology Inc.

MCP443X/5X PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. -XXX X /XX Examples: a) MCP4431-502E/XX: 5k 20-LD Device Device Resistance Temperature Package b) MCP4431T-502E/XX: T/R, 5k20-LD Device Version Range c) MCP4431-103E/XX: 10k, 20-LD Device d) MCP4431T-103E/XX: T/R, 10k, 20-LD Device e) MCP4431-503E/XX: 50k, 20-LD Device Device MCP4431: Quad Volatile 7-bit Potentiometer f) MCP4431T-503E/XX: T/R, 50k, 20-LD Device MCP4431T: Quad Volatile 7-bit Potentiometer g) MCP4431-104E/XX: 100k, 20-LD Device (Tape and Reel) h) MCP4431T-104E/XX: T/R, 100k, MCP4432: Quad Volatile 7-bit Rheostat 20-LD Device MCP4432T: Quad Volatile 7-bit Rheostat a) MCP4432-502E/XX: 5k 14-LD Device (Tape and Reel) MCP4451: Quad Volatile 8-bit Potentiometer b) MCP4432T-502E/XX: T/R, 5k14-LD Device MCP4451T: Quad Volatile 8-bit Potentiometer c) MCP4432-103E/XX: 10k, 14-LD Device (Tape and Reel) d) MCP4432T-103E/XX: T/R, 10k, 14-LD Device MCP4452: Quad Volatile 8-bit Rheostat e) MCP4432-503E/XX: 50k, 8LD Device MCP4452T: Quad Volatile 8-bit Rheostat f) MCP4432T-503E/XX: T/R, 50k, 14-LD Device (Tape and Reel) g) MCP4432-104E/XX: 100k, 14-LD Device h) MCP4432T-104E/XX: T/R, 100k, 14-LD Device Resistance Version: 502 = 5k a) MCP4451-502E/XX: 5k 20-LD Device 103 = 10k b) MCP4451T-502E/XX: T/R, 5k20-LD Device 503 = 50k c) MCP4451-103E/XX: 10k, 20-LD Device 104 = 100k d) MCP4451T-103E/XX: T/R, 10k, 20-LD Device e) MCP4451-503E/XX: 50k, 20-LD Device f) MCP4451T-503E/XX: T/R, 50k, 20-LD Device Temperature Range E = -40C to +125C (Extended) g) MCP4451-104E/XX: 100k, 20-LD Device h) MCP4451T-104E/XX: T/R, 100k, 20-LD Device Package ST = Plastic Thin Shrink Small Outline (TSSOP), 14/20-lead a) MCP4452-502E/XX: 5k 14-LD Device ML = Plastic Quad Flat No-lead (4x4 QFN), 20-lead b) MCP4452T-502E/XX: T/R, 5k14-LD Device c) MCP4452-103E/XX: 10k, 14-LD Device d) MCP4452T-103E/XX: T/R, 10k, 14-LD Device e) MCP4452-503E/XX: 50k, 14-LD Device f) MCP4452T-503E/XX: T/R, 50k, 14-LD Device g) MCP4452-104E/XX: 100k, 14-LD Device h) MCP4452T-104E/XX: T/R, 100k, 14-LD Device XX = ST for 14/20-lead TSSOP = ML for 20-lead QFN  2010 Microchip Technology Inc. DS22267A-page 91

MCP443X/5X NOTES: DS22267A-page 92  2010 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. PIC32 logo, rfPIC and UNI/O are registered trademarks of MICROCHIP MAKES NO REPRESENTATIONS OR Microchip Technology Incorporated in the U.S.A. and other WARRANTIES OF ANY KIND WHETHER EXPRESS OR countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MXDEV, MXLAB, SEEVAL and The Embedded Control QUALITY, PERFORMANCE, MERCHANTABILITY OR Solutions Company are registered trademarks of Microchip FITNESS FOR PURPOSE. Microchip disclaims all liability Technology Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, CodeGuard, devices in life support and/or safety applications is entirely at dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, the buyer’s risk, and the buyer agrees to defend, indemnify and ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial hold harmless Microchip from any and all damages, claims, Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified suits, or expenses resulting from such use. No licenses are logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code conveyed, implicitly or otherwise, under any Microchip Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, intellectual property rights. PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2010, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-60932-533-6 Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2010 Microchip Technology Inc. DS22267A-page 93

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: MCP4431-103E/ML MCP4431-103E/ST MCP4431-104E/ML MCP4431-104E/ST MCP4431-502E/ML MCP4431- 502E/ST MCP4431-503E/ML MCP4431-503E/ST MCP4432-103E/ST MCP4432-104E/ST MCP4432-502E/ST MCP4432-503E/ST MCP4451-103E/ML MCP4451-103E/ST MCP4451-104E/ML MCP4451-104E/ST MCP4451- 502E/ML MCP4451-502E/ST MCP4451-503E/ML MCP4451-503E/ST MCP4452-103E/ST MCP4452-104E/ST MCP4452-502E/ST MCP4452-503E/ST MCP4432T-503E/ST MCP4432T-502E/ST MCP4431T-103E/ST MCP4431T- 502E/ST MCP4431T-104E/ML MCP4432T-104E/ST MCP4431T-503E/ML MCP4432T-103E/ST MCP4431T-502E/ML MCP4431T-103E/ML MCP4431T-104E/ST MCP4431T-503E/ST