MCP433X/435X 7/8-Bit Quad SPI Digital POT with Volatile Memory Package Types (Top View) Features • Quad Resistor Network MCP43X1 Quad Potentiometers • Potentiometer or Rheostat Configuration Options TSSOP • Resistor Network Resolution: P3A 1 20 P2A P3W 2 19 P2W - 7-bit: 128 Resistors (129 Taps) P3B 3 18 P2B - 8-bit: 256 Resistors (257 Taps) CS 4 17 VDD • R Resistances Options of: SCK 5 16 SDO AB SDI 6 15 RESET - 5k VSS 7 14 NC - 10k P1B 8 13 P0B P1W 9 12 P0W - 50k P1A 10 11 P0A - 100k • Zero Scale to Full Scale Wiper Operation MCP43X1 Quad Potentiometers • Low Wiper Resistance: 75 (typical) 4x4QFN* • Low Tempco: - Absolute (Rheostat): 50ppm typical W A A W B 3 3 2 2 2 P P P P P (0°C to 70°C) - Ratiometric (Potentiometer): 15ppm typical 20 19 18 17 16 15 V P3B 1 DD • SPI Serial Interface (10MHz, Modes 0,0 and 1,1): 14 SDO CS 2 - High-Speed Read/Writes to wiper registers EP 13 RESET • Resistor Network Terminal Disconnect Feature SCK 3 21 12 NC via Terminal Control (TCON) Register SDI 4 11 P0B • Reset Input Pin VSS 5 • Brown-out Reset Protection (1.5V typical) 6 7 8 9 10 • Serial Interface Inactive Current (2.5µA typical) B W A A W • High-Voltage Tolerant Digital Inputs: Up to 12.5V P1 P1 P1 P0 P0 • Supports Split Rail Applications • Internal Weak Pull-up on all Digital Inputs MCP43X2 Quad Rheostat • Wide Operating Voltage: TSSOP - 2.7V to 5.5V – Device Characteristics P3W 1 14 P2W Specified P3B 2 13 P2B - 1.8V to 5.5V – Device Operation CS 3 12 VDD • Wide Bandwidth (-3dB) Operation: SCK 4 11 SDO SDI 5 10 P0B - 2MHz (typical) for 5.0k device VSS 6 9 P0W • Extended Temperature Range (-40°C to +125°C) P1B 7 8 P1W *Includes Exposed Thermal Pad (EP); see Table3-1.  2010 Microchip Technology Inc. DS22242A-page 1

MCP433X/435X Device Block Diagram VDD Power-up/ Resistor P0A V Brown-out Network 0 SS Control (Pot 0) P0W CS SPI Serial Wiper 0 and TCON0 SCK Interface Register Module and SDI P0B Control SDO Logic RESET Resistor P1A Network 1 (Pot 1) Memory (16x9) P1W Wiper0 (V) Wiper 1 Wiper1 (V) and TCON0 Wiper2 (V) Register P1B Wiper3 (V) TCON0 P2A TCON1 Resistor Network 2 (Pot 2) P2W Wiper 2 and TCON1 Register P2B P3A Resistor Network 3 (Pot 3) P3W Wiper 3 and TCON1 Register P3B Device Features Device # of POTs ConWfigipuerar tion Control Interface Memory Type WiperLock Technology POR Wiper Setting RARB eOspisttioanncse ( k(ty)picaW-l( )iRpW)er # of Taps ORpaeVnrgDaDeti n(2g) MCP4331 4 Potentiometer (1) SPI RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 129 1.8V to 5.5V MCP4332 4 Rheostat SPI RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 129 1.8V to 5.5V MCP4341 4 Potentiometer (1) SPI EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0 75 129 2.7V to 5.5V MCP4342 4 Rheostat SPI EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0 75 129 2.7V to 5.5V MCP4351 4 Potentiometer (1) SPI RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 257 1.8V to 5.5V MCP4352 4 Rheostat SPI RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 257 1.8V to 5.5V MCP4361 4 Potentiometer (1) SPI EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0 75 257 2.7V to 5.5V MCP4362 4 Rheostat SPI EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0 75 257 2.7V to 5.5V Note 1: Floating either terminal (A or B) allows the device to be used as a Rheostat (variable resistor). 2: Analog characteristics only tested from 2.7V to 5.5V unless otherwise noted. DS22242A-page 2  2010 Microchip Technology Inc.

MCP433X/435X 1.0 ELECTRICAL † Notice: Stresses above those listed under “Maximum CHARACTERISTICS Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those Absolute Maximum Ratings † indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions Voltage on V with respect to V ..... -0.6V to +7.0V DD SS for extended periods may affect device reliability. Voltage on CS, SCK, SDI, SDI/SDO, and RESET with respect to V -0.6V to 12.5V SS ..................... Voltage on all other pins (PxA, PxW, PxB and SDO) with respect to V -0.3V to V + 0.3V SS ............... DD Input clamp current, I IK (VI < 0, VI > VDD, VI > VPP ON HV pins)...........±20mA Output clamp current, I OK (V < 0 or V > V ).......................................±20mA O O DD Maximum output current sunk by any Output pin ...........................................................................25mA Maximum output current sourced by any Output pin ...........................................................................25mA Maximum current out of V pin......................100mA SS Maximum current into V pin.........................100mA DD Maximum current into PXA, PXW and PXB pins ±2.5mA Storage temperature ...........-65°C to +150°C Ambient temperature with power applied ..........................................................-40°C to +125°C Package power dissipation (T = +50°C, T = +150°C) TSSOP-14.........1000mW A J TSSOP-20......................................................1110mW QFN-20 (4x4)................................................2320mW Soldering temperature of leads (10 seconds)....................................................+300°C ESD protection on all pins 4kV (HBM), ................................................................ 300V (MM) Maximum Junction Temperature (T ) ..............+150°C J  2010 Microchip Technology Inc. DS22242A-page 3

MCP433X/435X AC/DC CHARACTERISTICS Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C  T  +125°C (extended) A DC Characteristics All parameters apply across the specified operating ranges unless noted. V = +2.7V to 5.5V, 5k, 10k, 50k, 100k devices. DD Typical specifications represent values for V = 5.5V, T = +25°C. DD A Parameters Sym Min Typ Max Units Conditions Supply Voltage V 2.7 — 5.5 V DD 1.8 — 2.7 V Serial Interface only. CS, SDI, SDO, V V — 12.5V V V  4.5V The CS pin will be at one HV SS DD SCK, RESET pin of three input levels V — V + V V < 4.5V SS DD DD Voltage Range (V , V or V ). (Note6) 8.0V IL IH IHH V Start Voltage V — — 1.65 V RAM retention voltage (V ) < V DD BOR RAM BOR to ensure Wiper Reset V Rise Rate to V (Note9) V/ms DD DDRR ensure Power-on Reset Delay after device T — 10 20 µs BORD exits the Reset state (V > V ) DD BOR Supply Current I — — 450 µA Serial Interface Active, DD (Note10) V = 5.5V, CS = V , SCK @ 5MHz, DD IL write all 0’s to volatile Wiper 0 (address 0h) — 2.5 5 µA Serial Interface Inactive, CS = V , V = 5.5V IH DD — 0.55 1 mA Serial Interface Active, V = 5.5V, CS = V , DD IHH SCK @ 5MHz, decrement volatile Wiper 0 (address 0h) Note 1: Resistance is defined as the resistance between terminal A to terminal B. 2: INL and DNL are measured at V with V = V and V = V . W A DD B SS 3: MCP43X1 only. 4: MCP43X2 only, includes V and V . WZSE WFSE 5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted. 6: This specification by design. 7: Non-linearity is affected by wiper resistance (R ), which changes significantly over voltage and W temperature. 8: The MCP43X1 is externally connected to match the configurations of the MCP43X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network. DS22242A-page 4  2010 Microchip Technology Inc.

MCP433X/435X AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C  T  +125°C (extended) A DC Characteristics All parameters apply across the specified operating ranges unless noted. V = +2.7V to 5.5V, 5k, 10k, 50k, 100k devices. DD Typical specifications represent values for V = 5.5V, T = +25°C. DD A Parameters Sym Min Typ Max Units Conditions Resistance R 4.0 5 6.0 k -502 devices(Note1) AB (± 20%) 8.0 10 12.0 k -103 devices(Note1) 40.0 50 60.0 k -503 devices(Note1) 80.0 100 120.0 k -104 devices(Note1) Resolution N 257 Taps 8-bit No Missing Codes 129 Taps 7-bit No Missing Codes Step Resistance R — R / —  8-bit Note6 S AB (256) — R / —  7-bit Note6 AB (128) Nominal (| R - — 0.2 1.50 % 5k MCP43X1 devices only ABWC Resistance Match R |)/ ABMEAN — 0.2 1.25 % 10k R ABMEAN — 0.2 1.0 % 50k — 0.2 1.0 % 100k (| R - — 0.25 1.75 % 5k Code = Full Scale BWWC R |)/ BWMEAN — 0.25 1.50 % 10k R BWMEAN — 0.25 1.25 % 50k — 0.25 1.25 % 100k Wiper Resistance R — 75 160  V = 5.5 V, I = 2.0mA, code = 00h W DD W (Note3, Note4) — 75 300  V = 2.7 V, I = 2.0mA, code = 00h DD W Nominal R /T — 50 — ppm/°C T = -20°C to +70°C AB A Resistance — 100 — ppm/°C T = -40°C to +85°C A Tempco — 150 — ppm/°C T = -40°C to +125°C A Ratiometeric V /T — 15 — ppm/°C Code = Mid-scale (80h or 40h) WB Tempco Resistance R Section2.0 ppm/°C See Section2.0 “Typical Performance TRACK Tracking Curves” Note 1: Resistance is defined as the resistance between terminal A to terminal B. 2: INL and DNL are measured at V with V = V and V = V . W A DD B SS 3: MCP43X1 only. 4: MCP43X2 only, includes V and V . WZSE WFSE 5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted. 6: This specification by design. 7: Non-linearity is affected by wiper resistance (R ), which changes significantly over voltage and W temperature. 8: The MCP43X1 is externally connected to match the configurations of the MCP43X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network.  2010 Microchip Technology Inc. DS22242A-page 5

MCP433X/435X AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C  T  +125°C (extended) A DC Characteristics All parameters apply across the specified operating ranges unless noted. V = +2.7V to 5.5V, 5k, 10k, 50k, 100k devices. DD Typical specifications represent values for V = 5.5V, T = +25°C. DD A Parameters Sym Min Typ Max Units Conditions Resistor Terminal V V V Vss — V V Note5, Note6 A, W, B DD Input Voltage Range (Terminals A, B and W) Maximum current I — — 2.5 mA Worst case current through wiper when W through A, W or B wiper is either Full Scale or Zero Scale. (Note6) Leakage current I — 100 — nA MCP43X1 PxA = PxW = PxB = V WL SS into A, W or B — 100 — nA MCP43X2 PxB = PxW = V SS Note 1: Resistance is defined as the resistance between terminal A to terminal B. 2: INL and DNL are measured at V with V = V and V = V . W A DD B SS 3: MCP43X1 only. 4: MCP43X2 only, includes V and V . WZSE WFSE 5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted. 6: This specification by design. 7: Non-linearity is affected by wiper resistance (R ), which changes significantly over voltage and W temperature. 8: The MCP43X1 is externally connected to match the configurations of the MCP43X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network. DS22242A-page 6  2010 Microchip Technology Inc.

MCP433X/435X AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C  T  +125°C (extended) A DC Characteristics All parameters apply across the specified operating ranges unless noted. V = +2.7V to 5.5V, 5k, 10k, 50k, 100k devices. DD Typical specifications represent values for V = 5.5V, T = +25°C. DD A Parameters Sym Min Typ Max Units Conditions Full Scale Error V -6.0 -0.1 — LSb 5k 8-bit 3.0V  V  5.5V WFSE DD (MCP43X1 only) -4.0 -0.1 — LSb 7-bit 3.0V  V  5.5V DD (8-bit code = 100h, -3.5 -0.1 — LSb 10k 8-bit 3.0V  V  5.5V 7-bit code = 80h) DD -2.0 -0.1 — LSb 7-bit 3.0V  V  5.5V DD -0.8 -0.1 — LSb 50k 8-bit 3.0V  V  5.5V DD -0.5 -0.1 — LSb 7-bit 3.0V  V  5.5V DD -0.5 -0.1 — LSb 100k 8-bit 3.0V  V  5.5V DD -0.5 -0.1 — LSb 7-bit 3.0V  V  5.5V DD Zero Scale Error V — +0.1 +6.0 LSb 5k 8-bit 3.0V  V  5.5V WZSE DD (MCP43X1 only) — +0.1 +3.0 LSb 7-bit 3.0V  V  5.5V DD (8-bit code = 00h, — +0.1 +3.5 LSb 10k 8-bit 3.0V  V  5.5V 7-bit code = 00h) DD — +0.1 +2.0 LSb 7-bit 3.0V  V  5.5V DD — +0.1 +0.8 LSb 50k 8-bit 3.0V  V  5.5V DD — +0.1 +0.5 LSb 7-bit 3.0V  V  5.5V DD — +0.1 +0.5 LSb 100k 8-bit 3.0V  V  5.5V DD — +0.1 +0.5 LSb 7-bit 3.0V  V  5.5V DD Potentiometer INL -1 ±0.5 +1 LSb 8-bit 3.0V  V  5.5V DD Integral MCP43X1 devices only -0.5 ±0.25 +0.5 LSb 7-bit Non-linearity (Note2) Potentiometer DNL -0.5 ±0.25 +0.5 LSb 8-bit 3.0V  V  5.5V DD Differential MCP43X1 devices only -0.25 ±0.125 +0.25 LSb 7-bit Non-linearity (Note2) Bandwidth -3dB BW — 2 — MHz 5k 8-bit Code = 80h (See Figure2-92, — 2 — MHz 7-bit Code = 40h load = 30pF) — 1 — MHz 10k 8-bit Code = 80h — 1 — MHz 7-bit Code = 40h — 200 — kHz 50k 8-bit Code = 80h — 200 — kHz 7-bit Code = 40h — 100 — kHz 100k 8-bit Code = 80h — 100 — kHz 7-bit Code = 40h Note 1: Resistance is defined as the resistance between terminal A to terminal B. 2: INL and DNL are measured at V with V = V and V = V . W A DD B SS 3: MCP43X1 only. 4: MCP43X2 only, includes V and V . WZSE WFSE 5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted. 6: This specification by design. 7: Non-linearity is affected by wiper resistance (R ), which changes significantly over voltage and W temperature. 8: The MCP43X1 is externally connected to match the configurations of the MCP43X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network.  2010 Microchip Technology Inc. DS22242A-page 7

MCP433X/435X AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C  T  +125°C (extended) A DC Characteristics All parameters apply across the specified operating ranges unless noted. V = +2.7V to 5.5V, 5k, 10k, 50k, 100k devices. DD Typical specifications represent values for V = 5.5V, T = +25°C. DD A Parameters Sym Min Typ Max Units Conditions Rheostat Integral R-INL -1.5 ±0.5 +1.5 LSb 5k 8-bit 5.5V, I = 900µA W Non-linearity -8.25 +4.5 +8.25 LSb 3.0V, I = 480µA W MCP43X1 (Note7) (Note4, Note8) Section2.0 1.8V, I = 190µA MCP43X2 devices W only (Note4) -1.125 ±0.5 +1.125 LSb 7-bit 5.5V, IW = 900µA -6.0 +4.5 +6.0 LSb 3.0V, I = 480µA W (Note7) Section2.0 1.8V, I = 190µA W -1.5 ±0.5 +1.5 LSb 10k 8-bit 5.5V, I = 450µA W -5.5 +2.5 +5.5 LSb 3.0V, I = 240µA W (Note7) Section2.0 1.8V, I = 150µA W -1.125 ±0.5 +1.125 LSb 7-bit 5.5V, I = 450µA W -4.0 +2.5 +4.0 LSb 3.0V, I = 240µA W (Note7) Section2.0 1.8V, I = 150µA W -1.5 ±0.5 +1.5 LSb 50k 8-bit 5.5V, I = 90µA W -2.0 +1 +2.0 LSb 3.0V, I = 48µA W (Note7) Section2.0 1.8V, I = 30µA W -1.125 ±0.5 +1.125 LSb 7-bit 5.5V, I = 90µA W -1.5 +1 +1.5 LSb 3.0V, I = 48µA W (Note7) Section2.0 1.8V, I = 30µA W -1.0 ±0.5 +1.0 LSb 100k 8-bit 5.5V, I = 45µA W -1.5 +0.25 +1.5 LSb 3.0V, I = 24µA W (Note7) Section2.0 1.8V, I = 15µA W -0.8 ±0.5 +0.8 LSb 7-bit 5.5V, I = 45µA W -1.125 +0.25 +1.125 LSb 3.0V, I = 24µA W (Note7) Section2.0 1.8V, I = 15µA W Note 1: Resistance is defined as the resistance between terminal A to terminal B. 2: INL and DNL are measured at V with V = V and V = V . W A DD B SS 3: MCP43X1 only. 4: MCP43X2 only, includes V and V . WZSE WFSE 5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted. 6: This specification by design. 7: Non-linearity is affected by wiper resistance (R ), which changes significantly over voltage and W temperature. 8: The MCP43X1 is externally connected to match the configurations of the MCP43X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network. DS22242A-page 8  2010 Microchip Technology Inc.

MCP433X/435X AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C  T  +125°C (extended) A DC Characteristics All parameters apply across the specified operating ranges unless noted. V = +2.7V to 5.5V, 5k, 10k, 50k, 100k devices. DD Typical specifications represent values for V = 5.5V, T = +25°C. DD A Parameters Sym Min Typ Max Units Conditions Rheostat R-DNL -0.5 ±0.25 +0.5 LSb 5k 8-bit 5.5V, I = 900µA W Differential -1.0 +0.5 +1.0 LSb 3.0V, I = 480µA W Non-linearity (Note7) MCP43X1 Section2.0 1.8V, I = 190µA (Note4, Note8) W MCP43X2 devices -0.375 ±0.25 +0.375 LSb 7-bit 5.5V, IW = 900µA only -0.75 +0.5 +0.75 LSb 3.0V, I = 480µA W (Note4) (Note7) Section2.0 1.8V, I = 190µA W -0.5 ±0.25 +0.5 LSb 10k 8-bit 5.5V, I = 450µA W -1.0 +0.25 +1.0 LSb 3.0V, I = 240µA W (Note7) Section2.0 1.8V, I = 150µA W -0.375 ±0.25 +0.375 LSb 7-bit 5.5V, I = 450µA W -0.75 +0.5 +0.75 LSb 3.0V, I = 240µA W (Note7) Section2.0 1.8V, I = 150µA W -0.5 ±0.25 +0.5 LSb 50k 8-bit 5.5V, I = 90µA W -0.5 ±0.25 +0.5 LSb 3.0V, I = 48µA W (Note7) Section2.0 1.8V, I = 30µA W -0.375 ±0.25 +0.375 LSb 7-bit 5.5V, I = 90µA W -0.375 ±0.25 +0.375 LSb 3.0V, I = 48µA W (Note7) Section2.0 1.8V, I = 30µA W -0.5 ±0.25 +0.5 LSb 100k 8-bit 5.5V, I = 45µA W -0.5 ±0.25 +0.5 LSb 3.0V, I = 24µA W (Note7) Section2.0 1.8V, I = 15µA W -0.375 ±0.25 +0.375 LSb 7-bit 5.5V, I = 45µA W -0.375 ±0.25 +0.375 LSb 3.0V, I = 24µA W (Note7) Section2.0 1.8V, I = 30µA W Note 1: Resistance is defined as the resistance between terminal A to terminal B. 2: INL and DNL are measured at V with V = V and V = V . W A DD B SS 3: MCP43X1 only. 4: MCP43X2 only, includes V and V . WZSE WFSE 5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted. 6: This specification by design. 7: Non-linearity is affected by wiper resistance (R ), which changes significantly over voltage and W temperature. 8: The MCP43X1 is externally connected to match the configurations of the MCP43X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network.  2010 Microchip Technology Inc. DS22242A-page 9

MCP433X/435X AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C  T  +125°C (extended) A DC Characteristics All parameters apply across the specified operating ranges unless noted. V = +2.7V to 5.5V, 5k, 10k, 50k, 100k devices. DD Typical specifications represent values for V = 5.5V, T = +25°C. DD A Parameters Sym Min Typ Max Units Conditions Capacitance (P ) C — 75 — pF f =1MHz, Code = Full Scale A AW Capacitance (P ) C — 120 — pF f =1MHz, Code = Full Scale w W Capacitance (P ) C — 75 — pF f =1MHz, Code = Full Scale B BW Digital Inputs/Outputs (CS, SDI, SDO, SCK, WP, RESET) Schmitt Trigger V 0.45V — — V 2.7V  V  5.5V IH D DD High Input (Allows 2.7V Digital V with D DD Threshold 5V Analog V ) DD 0.5V — — V 1.8V  V  2.7V DD DD Schmitt Trigger V — — 0.2V V IL DD Low Input Threshold Hysteresis of V — 0.1V — V HYS DD Schmitt Trigger Inputs High Voltage Input V 8.5 — 12.5 (6) V IHH Entry Voltage High Voltage Input V — — V + V IHH DD Exit Voltage 0.8V High Voltage Limit V — — 12.5 (6) V Pin can tolerate V or less. MAX MAX Output Low V V — 0.3V V I = 5mA, V = 5.5V OL SS DD OL DD Voltage (SDO) V — 0.3V V I = 1mA, V = 1.8V SS DD OL DD Output High V 0.7V — V V I = -2.5mA, V = 5.5V OH DD DD OH DD Voltage (SDO) 0.7V — V V I = -1mA, V = 1.8V DD DD OL DD Note 1: Resistance is defined as the resistance between terminal A to terminal B. 2: INL and DNL are measured at V with V = V and V = V . W A DD B SS 3: MCP43X1 only. 4: MCP43X2 only, includes V and V . WZSE WFSE 5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted. 6: This specification by design. 7: Non-linearity is affected by wiper resistance (R ), which changes significantly over voltage and W temperature. 8: The MCP43X1 is externally connected to match the configurations of the MCP43X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network. DS22242A-page 10  2010 Microchip Technology Inc.

MCP433X/435X AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C  T  +125°C (extended) A DC Characteristics All parameters apply across the specified operating ranges unless noted. V = +2.7V to 5.5V, 5k, 10k, 50k, 100k devices. DD Typical specifications represent values for V = 5.5V, T = +25°C. DD A Parameters Sym Min Typ Max Units Conditions Weak Pull-up I — — 1.75 mA Internal V pull-up, V pull-down, PU DD IHH Current V = 5.5V, V = 12.5V DD CS — 170 — µA CS pin, V = 5.5V, V = 3V DD CS CS Pull-up/ R — 16 — k V = 5.5V, V = 3V CS DD CS Pull-down Resistance RESET Pull-up R — 16 — k V = 5.5V, V = 0V RESET DD RESET Resistance Input Leakage I -1 — 1 µA V = V (all pins) and IL IN DD Current V = V (all pins except RESET) IN SS Pin Capacitance C , C — 10 — pF f = 20MHz IN OUT C RAM (Wiper, TCON) Value Value Range N 0h — 1FFh hex 8-bit device 0h — 1FFh hex 7-bit device TCON POR/BOR 1FF hex All terminals connected Setting Wiper POR/BOR N 080h hex 8-bit Setting 040h hex 7-bit Power Requirements Power Supply PSS — 0.0015 0.0035 %/% 8-bit V = 2.7V to 5.5V, DD Sensitivity V = 2.7V, Code = 80h A (MCP43X1) — 0.0015 0.0035 %/% 7-bit V = 2.7V to 5.5V, DD V = 2.7V, Code = 40h A Note 1: Resistance is defined as the resistance between terminal A to terminal B. 2: INL and DNL are measured at V with V = V and V = V . W A DD B SS 3: MCP43X1 only. 4: MCP43X2 only, includes V and V . WZSE WFSE 5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted. 6: This specification by design. 7: Non-linearity is affected by wiper resistance (R ), which changes significantly over voltage and W temperature. 8: The MCP43X1 is externally connected to match the configurations of the MCP43X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network.  2010 Microchip Technology Inc. DS22242A-page 11

MCP433X/435X 1.1 SPI Mode Timing Waveforms and Requirements RESET tRST tRSTD SCK Wx FIGURE 1-1: Reset Waveforms. TABLE 1-1: RESET TIMING Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C  T  +125°C (extended) A Timing Characteristics All parameters apply across the specified operating ranges unless noted. V = +2.7V to 5.5V, 5k, 10k, 50k, 100k devices. DD Typical specifications represent values for V = 5.5V, T = +25°C. DD A Parameters Sym Min Typ Max Units Conditions RESET pulse width tRST 50 — — ns RESET rising edge t — — 20 ns RSTD normal mode (Wiper driving and SPI interface operational) DS22242A-page 12  2010 Microchip Technology Inc.

MCP433X/435X V IHH VIH VIH CS V IL 84 70 72 SCK 83 71 79 78 80 SDO MSb BIT6 - - - - - -1 LSb 75, 76 77 SSDDII MSb IN BIT6 - - - -1 LSb IN 74 73 FIGURE 1-2: SPI Timing Waveform (Mode= 11). TABLE 1-2: SPI REQUIREMENTS (MODE= 11) # Characteristic Symbol Min Max Units Conditions SCK Input Frequency F — 10 MHz V = 2.7V to 5.5V SCK DD — 1 MHz V = 1.8V to 2.7V DD 70 CS Active (V or V ) to SCK input TcsA2scH 60 — ns IL IHH 71 SCK input high time TscH 45 — ns V = 2.7V to 5.5V DD 500 — ns V = 1.8V to 2.7V DD 72 SCK input low time TscL 45 — ns V = 2.7V to 5.5V DD 500 — ns V = 1.8V to 2.7V DD 73 Setup time of SDI input to SCK edge TDIV2scH 10 — ns VDD = 2.7V to 5.5V 20 — ns V = 1.8V to 2.7V DD 74 Hold time of SDI input from SCK edge TscH2DIL 20 — ns 77 CS Inactive (VIH) to SDO output high-impedance TcsH2DOZ — 50 ns Note1 80 SDO data output valid after SCK edge TscL2DOV — 70 ns VDD = 2.7V to 5.5V 170 ns V = 1.8V to 2.7V DD 83 CS Inactive (V ) after SCK edge TscH2csI 100 — ns V = 2.7V to 5.5V IH DD 1 ms V = 1.8V to 2.7V DD 84 Hold time of CS Inactive (V ) to TcsA2csI 50 — ns IH CS Active (V or V ) IL IHH Note 1: This specification by design.  2010 Microchip Technology Inc. DS22242A-page 13

MCP433X/435X V IHH VIH VIH 82 CS V IL 84 70 SCK 83 80 71 72 SDO MSb BIT6 - - - - - -1 LSb 75, 76 77 73 SSDDII MSb IN BIT6 - - - -1 LSb IN 74 FIGURE 1-3: SPI Timing Waveform (Mode= 00). TABLE 1-3: SPI REQUIREMENTS (MODE= 00) # Characteristic Symbol Min Max Units Conditions SCK Input Frequency F — 10 MHz V = 2.7V to 5.5V SCK DD — 1 MHz V = 1.8V to 2.7V DD 70 CS Active (V or V ) to SCK input TcsA2scH 60 — ns IL IHH 71 SCK input high time TscH 45 — ns V = 2.7V to 5.5V DD 500 — ns V = 1.8V to 2.7V DD 72 SCK input low time TscL 45 — ns V = 2.7V to 5.5V DD 500 — ns V = 1.8V to 2.7V DD 73 Setup time of SDI input to SCK edge TDIV2scH 10 — ns VDD = 2.7V to 5.5V 20 — ns V = 1.8V to 2.7V DD 74 Hold time of SDI input from SCK edge TscH2DIL 20 — ns 77 CS Inactive (VIH) to SDO output high-impedance TcsH2DOZ — 50 ns Note1 80 SDO data output valid after SCK edge TscL2DOV — 70 ns VDD = 2.7V to 5.5V 170 ns V = 1.8V to 2.7V DD 82 SDO data output valid after TssL2doV — 85 ns CS Active (V or V ) IL IHH 83 CS Inactive (V ) after SCK edge TscH2csI 100 — ns V = 2.7V to 5.5V IH DD 1 ms V = 1.8V to 2.7V DD 84 Hold time of CS Inactive (V ) to TcsA2csI 50 — ns IH CS Active (V or V ) IL IHH Note 1: This specification by design. DS22242A-page 14  2010 Microchip Technology Inc.

MCP433X/435X TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, V =+2.7V to +5.5V, V =GND. DD SS Parameters Sym Min Typ Max Units Conditions Temperature Ranges Specified Temperature Range T -40 — +125 °C A Operating Temperature Range T -40 — +125 °C A Storage Temperature Range T -65 — +150 °C A Thermal Package Resistances Thermal Resistance, 14L-TSSOP  — 100 — °C/W JA Thermal Resistance, 20L-QFN  — 43 — °C/W JA Thermal Resistance, 20L-TSSOP  — 90 — °C/W JA  2010 Microchip Technology Inc. DS22242A-page 15

MCP433X/435X NOTES: DS22242A-page 16  2010 Microchip Technology Inc.

MCP433X/435X 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS 700 250 1000 ating Current (I) (μA)DD 122334455665050505050500000000000 22225555........77775555VVVVVVVV -281-2814455255200°°5°°5°°CCCC°°CCCC R (kOhms)CS11250500000 ICS ---0246864200000000000000 I (μA)CS per 100 -800 O 50 RCS 0 0 -1000 0.00 2.00 4.00 6.00 8.00 10.00 12.00 2 3 4 5 6 7 8 9 10 fSCK (MHz) VCS (V) FIGURE 2-1: Device Current (I ) vs. SPI FIGURE 2-3: CS Pull-up/Pull-down DD Frequency (f ) and Ambient Temperature Resistance (R ) and Current (I ) vs. CS Input SCK CS CS (V = 2.7V and 5.5V). Voltage (V ) (V = 5.5V). DD CS DD 3.0 12 A) μ 2.5 10 stby) ( 2.0 5.5V old (V) 8 5.5V Entry 2.7V Entry nt (I 1.5 esh 6 5.5V Exit Curre 1.0 ThrPP 4 ndby 0.5 2.7V CS V 2 2.7V Exit a St 0.0 0 -40 25 85 125 -40 -20 0 20 40 60 80 100 120 Ambient Temperature (°C) Ambient Temperature (°C) FIGURE 2-2: Device Current (I ) and FIGURE 2-4: CS High Input Entry/Exit SHDN V . (CS = V ) vs. Ambient Temperature. Threshold vs. Ambient Temperature and V . DD DD DD  2010 Microchip Technology Inc. DS22242A-page 17

MCP433X/435X Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS 120 0.3 120 1.25 -40C Rw 25C Rw 85C Rw 125C Rw -40C Rw 25C Rw 85C Rw 125C Rw -40C INL 25C INL 85C INL 125C INL -40C INL 25C INL 85C INL 125C INL R)W 100 -40C DNL 25C DNL 85C DNL 125C DNL 0.2 R)W 100 -40C DNL 25C DNL 85C DNL 125C DNL 0.75 er Resistance ((ohms)6800 DNL INL -000.1.1Error (LSb) er Resistance ((ohms)6800 INL -00.2.255Error (LSb) p p DNL Wi 40 125°C85°C -40°C 25°C RW -0.2 Wi 40 125°C85°C 25°C-40°C RW -0.75 20 -0.3 20 -1.25 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 Wiper Setting (decimal) Wiper Setting (decimal) FIGURE 2-5: 5k Pot Mode – R (), FIGURE 2-8: 5k Rheo Mode – R (), W W INL (LSb), DNL (LSb) vs. Wiper Setting and INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (V = 5.5V). Ambient Temperature (V = 5.5V, I = 900 µA). DD DD W 300 300 0.3 -40C Rw 25C Rw 85C Rw 125C Rw -40C Rw 25C Rw 85C Rw 125C Rw -40C INL 25C INL 85C INL 125C INL 6 Wiper Resistance (R)W(ohms)11122604826000000 --4400CCD IDNNNLLL 2255CC 8IDN5NL°LC12I5N88°R55LCCCW IDNNLL 112255CC IDNNLL --00000..12..21Error (LSb) Wiper Resistance (R)W(ohms)11122604826000000 -40C DNL 25C D-N40L°C 85CR DWNL 1I2N5CL DNL 024 Error (LSb) -40°C 25°C 125°C 85°C25°C DNL 20 -0.3 20 -2 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 Wiper Setting (decimal) Wiper Setting (decimal) FIGURE 2-6: 5k Pot Mode – R (), FIGURE 2-9: 5k Rheo Mode – R (), W W INL (LSb), DNL (LSb) vs. Wiper Setting and INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (V = 3.0V). Ambient Temperature (V = 3.0V, I = 480 µA). DD DD W 0.5 -40C Rw 25C Rw 85C Rw 125C Rw 118 )W 2500 ---444000CCC RIDNwNLL 222555CCC RIDNwNLL 888555CCC RIDNwNLL 111222555CCC RIDNwNLL 0.4 )W 2500 --4400CC IDNNLL 2255CC IDNNLL 8855CC IDNNLL 112255CC IDNNLL 98 per Resistance (R(ohms)112050000000 INL -00000...123.1Error (LSb) per Resistance (R(ohms)112050000000 INL 357888 Error (LSb) Wi 500 DNL -0.2 Wi 500 RW DNL 18 RW 0 -0.3 0 -2 0 64 128 192 256 0 64 128 192 256 Wiper Setting (decimal) Wiper Setting (decimal) Note: See Appendix B: for additional infor- Note: See Appendix B: for additional infor- mation of R resistance variation char- mation of R resistance variation char- W W acteristics for V > 2.7V. acteristics for V > 2.7V. DD DD FIGURE 2-7: 5k Pot Mode – R (), FIGURE 2-10: 5k Rheo Mode – R (), W W INL (LSb), DNL (LSb) vs. Wiper Setting and INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (V = 1.8V). Ambient Temperature (V = 1.8V, I = 260 µA). DD DD W DS22242A-page 18  2010 Microchip Technology Inc.

MCP433X/435X Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS 5300 6000 )B RA 5250 5000 e ( nal Resistanc(Ohms) 55125000 5.5V 2.7V Resistance ((cid:2))234000000000 -40C mi 5100 1.8V +25C No 1000 +85C +125C 5050 0 -40 0 40 80 120 0 32 64 96 128 160 192 224 256 Ambient Temperature (°C) Wiper Code FIGURE 2-11: 5k – Nominal Resistance FIGURE 2-12: 5k – R () vs. Wiper WB (RAB) () vs. Ambient Temperature and VDD. Setting and Ambient Temperature (V = 5.5V, I = 190 µA). DD W 6000 5000 (cid:2))4000 e ( c n3000 a st si Re2000 -40C +25C 1000 +85C +125C 0 0 32 64 96 128 160 192 224 256 Wiper Code FIGURE 2-13: 5k – R () vs. Wiper WB Setting and Ambient Temperature (V = 3.0V, I = 190 µA). DD W 7000 6000 5000 (cid:2)) e (4000 c n a st3000 si Re2000 -40C +25C 1000 +85C +125C 0 0 32 64 96 128 160 192 224 256 Wiper Code Note: See Appendix B: for additional infor- mation of R resistance variation char- W acteristics for V > 2.7V. DD FIGURE 2-14: 5k – R () vs. Wiper WB Setting and Ambient Temperature (V = 1.8V, I = 190 µA). DD W  2010 Microchip Technology Inc. DS22242A-page 19

MCP433X/435X Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS 2.50% 54 -40C +25C 52 CH0 CH1 1.50% +85C CH2 CH3 +125C 50 Error %-00..5500%% PPM / °C4468 44 -1.50% 42 40 -2.50% 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 Wiper Code Wiper Code FIGURE 2-15: 5k – Worst Case RBW FIGURE 2-18: 5k – RWB PPM/°C vs. from Average RBW (RBW0-RBW3) Error (%) vs. Wiper Setting. (RBW(code=n, 125°C)-RBW(code=n, Wiper Setting and Temperature -40°C) )/RBW(code = 256, 25°C)/165°C * 1,000,000) (VDD = 5.5V, IW = 190 µA). (VDD = 5.5V, IW = 190 µA). 2.50% 100 -40C +25C 95 CH0 CH1 1.50% +85C CH2 CH3 90 +125C 85 0.50% C or % M / ° 80 Err-0.50% PP 75 70 -1.50% 65 -2.50% 60 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 Wiper Code Wiper Code FIGURE 2-16: 5k – Worst Case RBW FIGURE 2-19: 5k – RWB PPM/°C vs. from Average RBW (RBW0-RBW3) Error (%) vs. Wiper Setting. (RBW(code=n, 125°C)-RBW(code=n, Wiper Setting and Temperature -40°C) )/RBW(code = 256, 25°C)/165°C * 1,000,000) (VDD = 3.0V, IW = 190 µA). (VDD = 3.0V, IW = 190 µA). 2.00% 500 1.00% 0 0.00% -1.00% C -500 Error %--32..0000%% PPM / °-1000 -4.00% -40C -5.00% +25C -1500 CH0 CH1 -6.00% +85C CH2 CH3 +125C -7.00% -2000 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 Wiper Code Wiper Code Note: See Appendix B: for additional infor- Note: See Appendix B: for additional infor- mation of RW resistance variation char- mation of RW resistance variation char- acteristics for VDD > 2.7V. acteristics for VDD > 2.7V. FIGURE 2-17: 5k – Worst Case R FIGURE 2-20: 5k – R PPM/°C vs. BW WB from Average R (R -R ) Error (%) vs. Wiper Setting. (R -R BW BW0 BW3 BW(code=n, 125°C) BW(code=n, Wiper Setting and Temperature )/R /165°C * 1,000,000) -40°C) BW(code = 256, 25°C) (V = 1.8V, I = 190 µA). (V = 1.8V, I = 190 µA). DD W DD W DS22242A-page 20  2010 Microchip Technology Inc.

MCP433X/435X Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS FIGURE 2-21: 5k – Low-Voltage FIGURE 2-24: 5k – Low-Voltage Decrement Wiper Settling Time (V = 5.5V) Increment Wiper Settling Time (V = 5.5V) DD DD (1µs/Div). (1µs/Div). FIGURE 2-22: 5k – Low-Voltage FIGURE 2-25: 5k – Low-Voltage Decrement Wiper Settling Time (V = 2.7V) Increment Wiper Settling Time (V = 2.7V) DD DD (1µs/Div). (1µs/Div). FIGURE 2-23: 5k – Power-Up Wiper Response Time (20ms/Div).  2010 Microchip Technology Inc. DS22242A-page 21

MCP433X/435X Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS 120 0.3 120 1 -40C Rw 25C Rw 85C Rw 125C Rw -40C Rw 25C Rw 85C Rw 125C Rw -40C INL 25C INL 85C INL 125C INL -40C INL 25C INL 85C INL 125C INL )W 100 -40C DNL 25C DNL 85C DNL 125C DNL 0.2 )W 100 -40C DNL 25C DNL 85C DNL 125C DNL R R 0.5 Wiper Resistance ((ohms) 468000 125°C 85D°CN2L5°C -40°C INL RW --0000.1..21Error (LSb) Wiper Resistance ((ohms)468000 125°C85°C 25°C -40°ICNL RW DNL -00.5Error (LSb) 20 -0.3 20 -1 0 64 128 192 256 0 32 64 96 128 160 192 224 256 Wiper Setting (decimal) Wiper Setting (decimal) FIGURE 2-26: 10k Pot Mode – R (), FIGURE 2-29: 10k Rheo Mode – R (), W W INL (LSb), DNL (LSb) vs. Wiper Setting and INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (V = 5.5V). Ambient Temperature (V = 5.5V, I = 450 µA). DD DD W 300 4 300 0.3 -40C Rw 25C Rw 85C Rw 125C Rw -40C Rw 25C Rw 85C Rw 125C Rw -40C INL 25C INL 85C INL 125C INL R)W 260 --4400CC IDNNLL 2255CC IDNNLL 8855CC IDNNLL 112255CC IDNNLL 0.2 R)W 260 -40C DNL 25C DNL 85C DNL 12I5NCL DNL 3 Wiper Resistance ((ohms)11126048200000 DNL -40°C IRNWL --0000.1..21Error (LSb) Wiper Resistance ((ohms)11126048200000 -40°C DNL RW -0121 Error (LSb) 125°C 85°C 25°C 125°C 85°C 25°C 20 -0.3 20 -2 0 32 64 96 128 160 192 224 256 0 64 128 192 256 Wiper Setting (decimal) Wiper Setting (decimal) FIGURE 2-27: 10k Pot Mode – R (), FIGURE 2-30: 10k Rheo Mode – R (), W W INL (LSb), DNL (LSb) vs. Wiper Setting and INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (V = 3.0V). Ambient Temperature (V = 3.0V, I = 240 µA). DD DD W 0.6 98 4000 -40C Rw 25C Rw 85C Rw 125C Rw 4000 -40C Rw 25C Rw 85C Rw -40C INL 25C INL 85C INL 125C INL 0.5 18255CC I NRLw -14205CC IINNLL 2-450CC I NDLNL 88 e 3500 -40C DNL 25C DNL 85C DNL 125C DNL 0.4 R)W 3500 25C DNL 85C DNL 125C DNL 78 Wiper Resistanc(R)(ohms)W11223050500000000000 DNL INL -00000...123.1Error (LSb) per Resistance ((ohms) 11223050500000000000 INL 2345688888 Error (LSb) 500 RW -0.2 Wi 500 RW DNL 818 0 -0.3 0 -2 0 64 128 192 256 0 64 128 192 256 Wiper Setting (decimal) Wiper Setting (decimal) Note: See Appendix B: for additional infor- Note: See Appendix B: for additional infor- mation of RW resistance variation char- mation of RW resistance variation char- acteristics for VDD > 2.7V. acteristics for VDD > 2.7V. FIGURE 2-28: 10k Pot Mode – R (), FIGURE 2-31: 10k Rheo Mode – R (), W W INL (LSb), DNL (LSb) vs. Wiper Setting and INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (V = 1.8V). Ambient Temperature (V = 1.8V, I = 125 µA). DD DD W DS22242A-page 22  2010 Microchip Technology Inc.

MCP433X/435X Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS 10300 12000 )B 10250 RA 10200 10000 nal Resistance ((Ohms) 11110000001105050000 5.52V.7V Resistance ((cid:2)) 468000000000 -40C mi 9950 1.8V +25C No 9900 2000 +85C +125C 9850 0 -40 0 40 80 120 0 32 64 96 128 160 192 224 256 Ambient Temperature (°C) Wiper Code FIGURE 2-32: 10k – Nominal Resistance FIGURE 2-33: 10k – R () vs. Wiper WB (R ) () vs. Ambient Temperature and V . Setting and Ambient Temperature AB DD (V = 5.5V, I = 150 µA). DD W 12000 10000 (cid:2)) 8000 e ( c n 6000 a st Resi 4000 -40C +25C 2000 +85C +125C 0 0 32 64 96 128 160 192 224 256 Wiper Code FIGURE 2-34: 10k – R () vs. Wiper WB Setting and Ambient Temperature (V = 3.0V, I = 150 µA). DD W 12000 10000 (cid:2)) 8000 e ( c n 6000 a st esi 4000 -40C R +25C 2000 +85C +125C 0 0 32 64 96 128 160 192 224 256 Wiper Code Note: See Appendix B: for additional infor- mation of R resistance variation char- W acteristics for V > 2.7V. DD FIGURE 2-35: 10k – R () vs. Wiper WB Setting and Ambient Temperature (V = 1.8V, I = 150 µA). DD W  2010 Microchip Technology Inc. DS22242A-page 23

MCP433X/435X Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS 1.50% 50 -40C +25C 1.00% +85C +125C 45 40 0.50% C35 or % 0.00% M / °30 Err PP25 -0.50% 20 CH0 CH1 -1.00% 15 CH2 CH3 -1.50% 10 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 Wiper Code Wiper Code FIGURE 2-36: 10k – Worst Case RBW FIGURE 2-39: 10k – RWB PPM/°C vs. from Average RBW (RBW0-RBW3) Error (%) vs. Wiper Setting. (RBW(code=n, 125°C)-RBW(code=n, Wiper Setting and Temperature -40°C) )/RBW(code = 256, 25°C)/165°C * 1,000,000) (VDD = 5.5V, IW = 150 µA). (VDD = 5.5V, IW = 150 µA). 1.50% 60 -40C +25C 55 1.00% +85C +125C 50 0.50% C45 or % 0.00% M / °40 Err PP35 -0.50% 30 CH0 CH1 -1.00% 25 CH2 CH3 20 -1.50% 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 Wiper Code Wiper Code FIGURE 2-37: 10k – Worst Case RBW FIGURE 2-40: 10k – RWB PPM/°C vs. from Average RBW (RBW0-RBW3) Error (%) vs. Wiper Setting. (RBW(code=n, 125°C)-RBW(code=n, Wiper Setting and Temperature -40°C) )/RBW(code = 256, 25°C)/165°C * 1,000,000) (VDD = 3.0V, IW = 150 µA). (VDD = 3.0V, IW = 150 µA). 1.50% 200 -40C +25C 0 1.00% +85C +125C -200 0.50% C -400 or % 0.00% M / ° -600 Err PP -800 -0.50% -1000 CH0 CH1 -1.00% -1200 CH2 CH3 -1400 -1.50% 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 Wiper Code Wiper Code Note: See Appendix B: for additional infor- Note: See Appendix B: for additional infor- mation of RW resistance variation char- mation of RW resistance variation char- acteristics for VDD > 2.7V. acteristics for VDD > 2.7V. FIGURE 2-38: 10k – Worst Case RBW FIGURE 2-41: 10k – RWB PPM/°C vs. from Average RBW (RBW0-RBW3) Error (%) vs. Wiper Setting. (RBW(code=n, 125°C)-RBW(code=n, Wiper Setting and Temperature -40°C) )/RBW(code = 256, 25°C)/165°C * 1,000,000) (VDD = 1.8V, IW = 150 µA). (VDD = 1.8V, IW = 150 µA). DS22242A-page 24  2010 Microchip Technology Inc.

MCP433X/435X Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS FIGURE 2-42: 10k – Low-Voltage FIGURE 2-44: 10k – Low-Voltage Decrement Wiper Settling Time (V = 5.5V) Increment Wiper Settling Time (V = 5.5V) DD DD (1µs/Div). (1µs/Div). FIGURE 2-43: 10k – Low-Voltage FIGURE 2-45: 10k – Low-Voltage Decrement Wiper Settling Time (V = 2.7V) Increment Wiper Settling Time (V = 2.7V) DD DD (1µs/Div). (1µs/Div).  2010 Microchip Technology Inc. DS22242A-page 25

MCP433X/435X Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS 120 0.3 120 0.3 -40C Rw 25C Rw 85C Rw 125C Rw -40C Rw 25C Rw 85C Rw 125C Rw -40C INL 25C INL 85C INL 125C INL -40C INL 25C INL 85C INL 125C INL )W 100 -40C DNL 25C DNL 85C DNL 125C DNL 0.2 )W 100 -40C DNL 25C DNL 85C DNL 125C DNL 0.2 R R INL er Resistance ((ohms)6800 DNL INL -000.1.1Error (LSb) er Resistance ((ohms)6800 DNL -000.1.1Error (LSb) Wip 40 25°C -40°C RW -0.2 Wip 40 125°C 85°C 25°C -40°C RW -0.2 125°C 85°C 20 -0.3 20 -0.3 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 Wiper Setting (decimal) Wiper Setting (decimal) FIGURE 2-46: 50k Pot Mode – R (), FIGURE 2-49: 50k Rheo Mode – R (), W W INL (LSb), DNL (LSb) vs. Wiper Setting and INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (V = 5.5V). Ambient Temperature (V = 5.5V, I = 90 µA). DD DD W 300 1 300 0.3 -40C Rw 25C Rw 85C Rw 125C Rw per Resistance (R)W(ohms)111220482600000 ---444000CCCD RIDNNwNLLL 222555CCC RIDNwNLL 888IRN555CCCWL RIDNwNLL 111222555CCC RIDNwNLL -0000..12.1Error (LSb) Wiper Resistance (R)W(ohms)111220482600000 --4400CCD IDNNNLLL 2255CC IDNNILNLL 88R55CCW IDNNLL 112255CC IDNNLL --000000...257..52555 Error (LSb) Wi 60 -40°C -0.2 60 -40°C -0.75 125°C 85°C 25°C 125°C 85°C 25°C 20 -0.3 20 -1 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 Wiper Setting (decimal) Wiper Setting (decimal) FIGURE 2-47: 50k Pot Mode – R (), FIGURE 2-50: 50k Rheo Mode – R (), W W INL (LSb), DNL (LSb) vs. Wiper Setting and INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (V = 3.0V). Ambient Temperature (V = 3.0V, I = 48 µA). DD DD W 1145000000 -40C Rw 25C Rw 85C Rw 125C Rw 0.5 1145000000 --4400CC RINwL 2255CC RINwL 8855CC RINwL 112255CC RINwL 7738..55 Wiper Resistance (R)W(ohms)111134567890123000000000000000000000000000000000 --4400CC IDNNLL DN2255LCCI NIDNNLLL 8855CC IDNNLL 112255CC IDNNLL ---00000000....1234...321Error (LSb) Wiper Resistance (Rw) (ohms)111101233456789000000000000000000000000000000000 -40C DNL 25C DNL 85C DNLIRNWL125C DNL 112233445566383838383838............555555555555 Error (LSb) 12000000 RW -0.4 12000000 DNL 38..55 0 -0.5 0 -1.5 0 64 128 192 256 0 64 128 192 256 Wiper Setting (decimal) Wiper Setting (decimal) Note: See Appendix B: for additional infor- Note: See Appendix B: for additional infor- mation of R resistance variation char- mation of R resistance variation char- W W acteristics for V > 2.7V. acteristics for V > 2.7V. DD DD FIGURE 2-48: 50k Pot Mode – RW (), FIGURE 2-51: 50k Rheo Mode – RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 1.8V). Ambient Temperature (VDD = 1.8V, IW = 25 µA). DS22242A-page 26  2010 Microchip Technology Inc.

MCP433X/435X Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS 52500 60000 )B 52000 RA 50000 e ( 51500 1.8V nc (cid:2))40000 nal Resista(Ohms) 555001050000000 2.7V Resistance (2300000000 -40C mi +25C o 49500 10000 +85C N 5.5V +125C 49000 0 -40 0 40 80 120 0 32 64 96 128 160 192 224 256 Ambient Temperature (°C) Wiper Code FIGURE 2-52: 50k – Nominal Resistance FIGURE 2-53: 50k – R () vs. Wiper WB (RAB) () vs. Ambient Temperature and VDD. Setting and Ambient Temperature (V = 5.5V, I = 90 µA). DD W 60000 50000 (cid:2))40000 e ( c n30000 a st esi20000 -40C R +25C 10000 +85C +125C 0 0 32 64 96 128 160 192 224 256 Wiper Code FIGURE 2-54: 50k – R () vs. Wiper WB Setting and Ambient Temperature (V = 3.0V, I = 48 µA). DD W 60000 50000 (cid:2))40000 e ( c n30000 a st esi20000 -40C R +25C 10000 +85C +125C 0 0 32 64 96 128 160 192 224 256 Wiper Code Note: See Appendix B: for additional infor- mation of R resistance variation char- W acteristics for V > 2.7V. DD FIGURE 2-55: 50k – R () vs. Wiper WB Setting and Ambient Temperature (V = 1.8V, I = 30 µA). DD W  2010 Microchip Technology Inc. DS22242A-page 27

MCP433X/435X Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS 7.00% 7 -40C +25C 6 6.00% +85C +125C 5 5.00% 4 4.00% C 3 or % 3.00% M / ° 2 Err 2.00% PP 1 0 1.00% -1 CH0 CH1 0.00% -2 CH2 CH3 -1.00% -3 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 Wiper Code Wiper Code FIGURE 2-56: 50k – Worst Case RBW FIGURE 2-59: 50k – RWB PPM/°C vs. from Average RBW (RBW0-RBW3) Error (%) vs. Wiper Setting. (RBW(code=n, 125°C)-RBW(code=n, Wiper Setting and Temperature -40°C) )/RBW(code = 256, 25°C)/165°C * 1,000,000) (VDD = 5.5V, IW = 90 µA). (VDD = 5.5V, IW = 90 µA). 4.00% 12 -40C +25C 10 3.00% +85C +125C 8 2.00% C Error % 1.00% PPM / ° 46 0.00% 2 CH0 CH1 -1.00% 0 CH2 CH3 -2 -2.00% 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 Wiper Code Wiper Code FIGURE 2-57: 50k – Worst Case RBW FIGURE 2-60: 50k – RWB PPM/°C vs. from Average RBW (RBW0-RBW3) Error (%) vs. Wiper Setting. (RBW(code=n, 125°C)-RBW(code=n, Wiper Setting and Temperature -40°C) )/RBW(code = 256, 25°C)/165°C * 1,000,000) (VDD = 3.0V, IW = 48 µA). (VDD = 3.0V, IW = 48 µA). 3.50% 200 -40C +25C 0 +85C +125C 2.50% -200 C -400 or % 1.50% M / ° -600 Err 0.50% PP -800 -1000 -0.50% CH0 CH1 -1200 CH2 CH3 -1400 -1.50% 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 Wiper Code Wiper Code Note: See Appendix B: for additional infor- Note: See Appendix B: for additional infor- mation of RW resistance variation char- mation of RW resistance variation char- acteristics for VDD > 2.7V. acteristics for VDD > 2.7V. FIGURE 2-58: 50k – Worst Case RBW FIGURE 2-61: 50k – RWB PPM/°C vs. from Average RBW (RBW0-RBW3) Error (%) vs. Wiper Setting. (RBW(code=n, 125°C)-RBW(code=n, Wiper Setting and Temperature -40°C) )/RBW(code = 256, 25°C)/165°C * 1,000,000) (VDD = 1.8V, IW = 30 µA). (VDD = 1.8V, IW = 30 µA). DS22242A-page 28  2010 Microchip Technology Inc.

MCP433X/435X Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS FIGURE 2-62: 50k – Low-Voltage FIGURE 2-64: 50k – Low-Voltage Decrement Wiper Settling Time (V = 5.5V) Increment Wiper Settling Time (V = 5.5V) DD DD (1µs/Div). (1µs/Div). FIGURE 2-63: 50k – Low-Voltage FIGURE 2-65: 50k – Low-Voltage Decrement Wiper Settling Time (V = 2.7V) Increment Wiper Settling Time (V = 2.7V) DD DD (1µs/Div). (1µs/Div).  2010 Microchip Technology Inc. DS22242A-page 29

MCP433X/435X Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS 120 0.2 120 0.3 -40C Rw 25C Rw 85C Rw 125C Rw -40C Rw 25C Rw 85C Rw 125C Rw -40C INL 25C INL 85C INL 125C INL -40C INL 25C INL 85C INL 125C INL )W 100 -40C DNL 25C DNL 85C DNL 125C DNL )W 100 -40C DNL 25C DNL 85C DNL 125C DNL 0.2 R 0.1 R INL per Resistance ((ohms)6800 DNL INL -00.1Error (LSb) per Resistance ((ohms)6800 DNL -000.1.1Error (LSb) Wi 40 25°C -40°C RW Wi 40 125°C 85°C 25°C-40°C RW -0.2 125°C 85°C 20 -0.2 20 -0.3 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 Wiper Setting (decimal) Wiper Setting (decimal) FIGURE 2-66: 100k Pot Mode – R (), FIGURE 2-69: 100k Rheo Mode – R W W INL (LSb), DNL (LSb) vs. Wiper Setting and (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (V = 5.5V). Ambient Temperature (V = 5.5V, I = 45 µA). DD DD W 300 0.6 300 0.2 -40C Rw 25C Rw 85C Rw 125C Rw -40C Rw 25C Rw 85C Rw 125C Rw -40C INL 25C INL 85C INL 125C INL per Resistance (R)W(ohms)111220482600000 --4400CC IDDNNLNLL 2255CC IDNNLL I88RN55CCWL IDNNLL 112255CC IDNNLL --000000...011..10555Error (LSb) per Resistance (Rw) (ohms)111220482600000 -4D0NC LDNL 25C DNINLL 85CR DWNL 125C DNL -0000..24.2 Error (LSb) Wi 60 -40°C -0.15 Wi 60 -40°C -0.4 125°C85°C 25°C 125°C 85°C 25°C 20 -0.2 20 -0.6 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 Wiper Setting (decimal) Wiper Setting (decimal) FIGURE 2-67: 100k Pot Mode – R (), FIGURE 2-70: 100k Rheo Mode – R W W INL (LSb), DNL (LSb) vs. Wiper Setting and (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (V = 3.0V). Ambient Temperature (V = 3.0V, I = 24 µA). DD DD W 0.35 -40C Rw 25C Rw 85C Rw 125C Rw 59 -40C Rw 25C Rw 85C Rw 125C Rw -40C INL 25C INL 85C INL 125C INL 54 )W 25000 --4400CC IDNNLL 2255CC IDNNLL 8855CC IDNNLL 112255CC IDNNLL 0.25 )W 25000 -40C DNL 25C DNL 85C DNL 125C DNL 49 per Resistance (R(ohms)112050000000000 DNL --0000..01..105555Error (LSb) per Resistance (R(ohms)112050000000000 RINWL 11223344949494 Error (LSb) Wi 5000 INL -0.25 Wi 5000 9 RW DNL 4 0 -0.35 0 -1 0 64 128 192 256 0 64 128 192 256 Wiper Setting (decimal) Wiper Setting (decimal) Note: See Appendix B: for additional infor- Note: See Appendix B: for additional infor- mation of R resistance variation char- mation of R resistance variation char- W W acteristics for V > 2.7V. acteristics for V > 2.7V. DD DD FIGURE 2-68: 100k Pot Mode – R (), FIGURE 2-71: 100k Rheo Mode – R W W INL (LSb), DNL (LSb) vs. Wiper Setting and (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (V = 1.8V). Ambient Temperature (V = 1.8V, I = 10 µA). DD DD W DS22242A-page 30  2010 Microchip Technology Inc.

MCP433X/435X Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS 103500 120000 )B 103000 RA 102500 100000 e ( 102000 minal Resistanc(Ohms) 11119000090011505050000000000 2.71V.8V Resistance ((cid:2)) 468000000000000 -+4205CC o 20000 +85C N 99000 5.5V +125C 98500 0 -40 0 40 80 120 0 32 64 96 128 160 192 224 256 Ambient Temperature (°C) Wiper Code FIGURE 2-72: 100k – Nominal FIGURE 2-73: 100k – R () vs. Wiper WB Resistance (RAB) () vs. Ambient Temperature Setting and Ambient Temperature and VDD. (VDD = 5.5V, IW = 45 µA). 120000 100000 (cid:2)) 80000 e ( c n 60000 a st esi 40000 -40C R +25C 20000 +85C +125C 0 0 32 64 96 128 160 192 224 256 Wiper Code FIGURE 2-74: 100k – R () vs. Wiper WB Setting and Ambient Temperature (V = 3.0V, I = 24 µA). DD W 120000 100000 (cid:2)) 80000 e ( c n 60000 a st esi 40000 -40C R +25C 20000 +85C +125C 0 0 32 64 96 128 160 192 224 256 Wiper Code Note: See Appendix B: for additional infor- mation of R resistance variation char- W acteristics for V > 2.7V. DD FIGURE 2-75: 100k – R () vs. Wiper WB Setting and Ambient Temperature (V = 1.8V, I = 15 µA). DD W  2010 Microchip Technology Inc. DS22242A-page 31

MCP433X/435X Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS 14.00% 16 13.00% -40C +25C 12.00% +85C +125C 14 11.00% 10.00% 12 89..0000%% C10 Error % 567...000000%%% PPM / ° 68 4.00% 3.00% 4 CH0 CH1 2.00% 1.00% 2 CH2 CH3 0.00% 0 -1.00% 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 Wiper Code Wiper Code FIGURE 2-76: 100k – Worst Case RBW FIGURE 2-79: 100k – RWB PPM/°C vs. from Average RBW (RBW0-RBW3) Error (%) vs. Wiper Setting. (RBW(code=n, 125°C)-RBW(code=n, Wiper Setting and Temperature -40°C) )/RBW(code = 256, 25°C)/165°C * 1,000,000) (VDD = 5.5V, IW = 45 µA). (VDD = 5.5V, IW = 45 µA). 7.00% 18 -40C +25C 16 6.00% +85C +125C 14 5.00% 12 4.00% C Error % 23..0000%% PPM / °1068 1.00% 4 CH0 CH1 0.00% 2 CH2 CH3 -1.00% 0 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 Wiper Code Wiper Code FIGURE 2-77: 100k – Worst Case RBW FIGURE 2-80: 100k – RWB PPM/°C vs. from Average RBW (RBW0-RBW3) Error (%) vs. Wiper Setting. (RBW(code=n, 125°C)-RBW(code=n, Wiper Setting and Temperature -40°C) )/RBW(code = 256, 25°C)/165°C * 1,000,000) (VDD = 3.0V, IW = 24 µA). (VDD = 3.0V, IW = 24 µA). 6.00% 200 -40C +25C 5.00% +85C +125C 0 4.00% -200 C Error % 23..0000%% PPM / ° --640000 -800 1.00% CH0 CH1 -1000 0.00% CH2 CH3 -1200 -1.00% 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 Wiper Code Wiper Code Note: See Appendix B: for additional infor- Note: See Appendix B: for additional infor- mation of RW resistance variation char- mation of RW resistance variation char- acteristics for VDD > 2.7V. acteristics for VDD > 2.7V. FIGURE 2-78: 100k – Worst Case RBW FIGURE 2-81: 100k – RWB PPM/°C vs. from Average RBW (RBW0-RBW3) Error (%) vs. Wiper Setting. (RBW(code=n, 125°C)-RBW(code=n, Wiper Setting and Temperature -40°C) )/RBW(code = 256, 25°C)/165°C * 1,000,000) (VDD = 1.8V, IW = 15 µA). (VDD = 1.8V, IW = 15 µA). DS22242A-page 32  2010 Microchip Technology Inc.

MCP433X/435X Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS FIGURE 2-82: 100k – Low-Voltage FIGURE 2-84: 100k – Low-Voltage Decrement Wiper Settling Time (V = 5.5V) Increment Wiper Settling Time (V = 5.5V) DD DD (1µs/Div). (1µs/Div). FIGURE 2-83: 100k – Low-Voltage FIGURE 2-85: 100k – Low-Voltage Decrement Wiper Settling Time (V = 2.7V) Increment Wiper Settling Time (V = 2.7V) DD DD (1µs/Div). (1µs/Div).  2010 Microchip Technology Inc. DS22242A-page 33

MCP433X/435X Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS 2.4 0 -5 2.2 5.5V -10 2 -15 2.7V V (V)IH 11..68 (mA)OH --2250 5.5V I -30 1.4 2.7V -35 1.2 -40 1 -45 -40 0 40 80 120 -40 0 40 80 120 Temperature (°C) Temperature (°C) FIGURE 2-86: V (SDI, SCK, CS, and FIGURE 2-88: I (SDO) vs. V and IH OH DD RESET) vs. V and Temperature. Temperature. DD 1.4 50 1.3 45 5.5V 5.5V 40 1.2 35 V (V)IL 01..191 I (mA)OL 223050 2.7V 15 0.8 2.7V 10 0.7 5 0.6 0 -40 0 40 80 120 -40 0 40 80 120 Temperature (°C) Temperature (°C) FIGURE 2-87: V (SDI, SCK, CS, and FIGURE 2-89: I (SDO) vs. V and IL OL DD RESET) vs. V and Temperature. Temperature. DD DS22242A-page 34  2010 Microchip Technology Inc.

MCP433X/435X Note: Unless otherwise indicated, T = +25°C, 2.1 Test Circuits A V =5V, V = 0V. DD SS +5V 2 A 1.6 VIN W + VOUT V (V)DD 01..82 Offset B - GND 0.4 2.5V DC 0 -40 0 40 80 120 Temperature (°C) FIGURE 2-92: -3db Gain vs. Frequency FIGURE 2-90: POR/BOR Trip point vs. V DD Measurement. and Temperature. floating 14.2 V A 14.1 A 5.5V VW 14.0 W z) 13.9 H ck (M 1133..78 2.7V IW RBW = VW / IW fs 13.6 B V RW = (VW - VA) / IW B 13.5 13.4 FIGURE 2-93: R and R Measurement. -40 0 40 80 120 BW W Temperature (°C) FIGURE 2-91: SCK Input Frequency vs. Voltage and Temperature.  2010 Microchip Technology Inc. DS22242A-page 35

MCP433X/435X NOTES: DS22242A-page 36  2010 Microchip Technology Inc.

MCP433X/435X 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table3-1. Additional descriptions of the device pins follows. TABLE 3-1: PINOUT DESCRIPTION FOR THE MCP433X/435X Pin Weak Pull-up/ TSSOP QFN Standard Function Buffer down Symbol I/O 14L 20L 20L Type (Note1) — 1 19 P3A A Analog No Potentiometer 3 Terminal A 1 2 20 P3W A Analog No Potentiometer 3 Wiper Terminal 2 3 1 P3B A Analog No Potentiometer 3 Terminal B 3 4 2 CS I HV w/ST “smart” SPI Chip Select Input 4 5 3 SCK I HV w/ST “smart” SPI Clock Input 5 6 4 SDI I HV w/ST “smart” SPI Serial Data Input 6 7 5 VSS — P — Ground 7 8 6 P1B A Analog No Potentiometer 1 Terminal B 8 9 7 P1W A Analog No Potentiometer 1 Wiper Terminal — 10 8 P1A A Analog No Potentiometer 1 Terminal A — 11 9 P0A A Analog No Potentiometer 0 Terminal A 9 12 10 P0W A Analog No Potentiometer 0 Wiper Terminal 10 13 11 P0B A Analog No Potentiometer 0 Terminal B — 14 12 NC I I — No Connect — 15 13 RESET I HV w/ST Yes Hardware Reset Pin 11 16 14 SDO O O No SPI Serial Data Output 12 17 15 VDD — P — Positive Power Supply Input 13 18 16 P2B A Analog No Potentiometer 2 Terminal B 14 19 17 P2W A Analog No Potentiometer 2 Wiper Terminal — 20 18 P2A A Analog No Potentiometer 2 Terminal A — — 21 EP — — — Exposed Pad. (Note2) Legend: HV w/ST = High Voltage tolerant input (with Schmitt trigger input) A = Analog pins (Potentiometer terminals) I = digital input (high Z) O = digital output I/O = Input / Output P = Power Note 1: The pin’s “smart” pull-up shuts off while the pin is forced low. This is done to reduce the standby and shutdown current. 2: The QFN package has a contact on the bottom of the package. This contact is conductively connected to the die substrate, and therefore should be unconnected or connected to the same ground as the device’s V pin. SS  2010 Microchip Technology Inc. DS22242A-page 37

MCP433X/435X 3.1 Chip Select (CS) 3.7 Potentiometer Terminal A The CS pin is the serial interface’s chip select input. The terminal A pin is available on the MCP43X1 Forcing the CS pin to V enables the serial commands. devices, and is connected to the internal IL Forcing the CS pin to V enables the high-voltage potentiometer’s terminal A. IHH serial commands. The potentiometer’s terminal A is the fixed connection to the full scale wiper value of the digital potentiometer. 3.2 Serial Clock (SCK) This corresponds to a wiper value of 0x100 for 8-bit devices or 0x80 for 7-bit devices. The SCK pin is the serial interface's Serial Clock pin. This pin is connected to the host controllers SCK pin. The terminal A pin does not have a polarity relative to The MCP43XX is an SPI slave device, so it’s SCK pin the terminal W or B pins. The terminal A pin can is an input only pin. support both positive and negative current. The voltage on terminal A must be between V and V . SS DD 3.3 Serial Data In (SDI) The terminal A pin is not available on the MCP43X2 devices, and the internally terminal A signal is floating. The SDI pin is the serial interfaces Serial Data In pin. This pin is connected to the host controllers SDO pin. MCP43X1 devices have four terminal A pins, one for each resistor network. 3.4 Ground (V ) SS 3.8 Not Connected (NC) The V pin is the device ground reference. SS The NC pin is not used. 3.5 Potentiometer Terminal B 3.9 Reset (RESET) The terminal B pin is connected to the internal potentiometer’s terminal B. The RESET pin is used to force the device into the POR/BOR state. The potentiometer’s terminal B is the fixed connection to the zero scale wiper value of the digital 3.10 Serial Data Out (SDO) potentiometer. This corresponds to a wiper value of 0x00 for both 7-bit and 8-bit devices. The SDO pin is the serial interfaces Serial Data Out pin. The terminal B pin does not have a polarity relative to This pin is connected to the host controllers SDI pin. the terminal W or A pins. The terminal B pin can This pin allows the host controller to read the digital support both positive and negative current. The voltage potentiometers registers, or monitor the state of the on terminal B must be between VSS and VDD. command error bit. MCP43XX devices have four terminal B pins, one for each resistor network. 3.11 Positive Power Supply Input (V ) DD The V pin is the device’s positive power supply input. 3.6 Potentiometer Wiper (W) Terminal DD The input power supply is relative to V . SS The terminal W pin is connected to the internal While the devices V is less than V (2.7V), the DD min potentiometer’s terminal W (the wiper). The wiper electrical performance of the device may not meet the terminal is the adjustable terminal of the digital data sheet specifications. potentiometer. The terminal W pin does not have a polarity relative to terminals A or B pins. The terminal 3.12 Exposed Pad (EP) W pin can support both positive and negative current. The voltage on terminal W must be between VSS and This pad is conductively connected to the device's VDD. substrate. This pad should be tied to the same potential MCP43XX devices have four terminal W pins, one for as the VSS pin (or left unconnected). This pad could be each resistor network. used to assist as a heat sink for the device when connected to a PCB heat sink. DS22242A-page 38  2010 Microchip Technology Inc.

MCP433X/435X 4.0 FUNCTIONAL OVERVIEW 4.1.2 BROWN-OUT RESET When the device powers down, the device V will This data sheet covers a family of four volatile Digital DD cross the V /V voltage. Potentiometer and Rheostat devices that will be POR BOR referred to as MCP43XX. The MCP43X1 devices are Once the V voltage decreases below the V /V DD POR BOR the Potentiometer configuration, while the MCP43X2 voltage the following happens: devices are the Rheostat configuration. • Serial Interface is disabled As the Device Block Diagram shows, there are four If the V voltage decreases below the V voltage, DD RAM main functional blocks. These are: the following happens: • POR/BOR and Reset Operation • Volatile wiper registers may become corrupted • Memory Map • TCON registers may become corrupted • Resistor Network As the voltage recovers above the V /V voltage, POR BOR • Serial Interface (SPI) the operation is the same as Power-on Reset (see The POR/BOR operation and the Memory Map are Section4.1.1 “Power-on Reset”). discussed in this section and the Resistor Network and Serial commands not completed due to a brown-out SPI operation are described in their own sections. The condition may cause the memory location to become Device Commands are discussed in Section7.0. corrupted. 4.1 POR/BOR and Reset Operation 4.1.3 RESET PIN The Power-on Reset is the case where the device is The RESET pin can be used to force the device into having power applied to it from V . The Brown-out the POR/BOR state of the device. When the RESET SS Reset occurs when a device had power applied to it, pin is forced Low, the device is forced into the Reset and that power (voltage) drops below the specified state. This means that the TCON registers are forced range. to their default values and the volatile wiper registers are loaded with the default value. Also the SPI The devices RAM retention voltage (V ) is lower RAM interface is disabled. than the POR/BOR voltage trip point (V /V ). The POR BOR maximum V /V voltage is less than 1.8V. This feature allows a hardware method for all registers POR BOR to be updated to the default value at the same time. When V /V < V < 2.7V, the analog electrical POR BOR DD performance may not meet the data sheet 4.1.4 INTERACTION OF RESET PIN AND BOR/ specifications. In this region, the device is capable of POR CIRCUITRY incrementing, decrementing, reading and writing to its volatile memory, if the proper serial command is Figure4-1 shows how the RESET pin signal and the POR/BOR signal interact to control the hardware Reset executed. state of the device. When V < V /V or the RESET pin is Low, the DD POR BOR pin weak pull-ups are enabled. RESET (from pin) 4.1.1 POWER-ON RESET Device Reset When the device powers up, the device V will cross POR/BOR signal DD the V /V voltage. Once the V voltage crosses POR BOR DD the V /V voltage, the following happens: FIGURE 4-1: POR/BOR Signal and POR BOR RESET Pin Interaction. • Volatile wiper register is loaded with the default value • The TCON registers are loaded with their default value • The device is capable of digital operation  2010 Microchip Technology Inc. DS22242A-page 39

MCP433X/435X 4.2 Memory Map The volatile memory starts functioning at the RAM retention voltage (V ). The POR/BOR Wiper code is RAM The device memory supports 16 locations that are shown in Table4-1. 9-bits wide (16x9bits). This memory space contains only volatile locations (see Table4-2). TABLE 4-1: STANDARD SETTINGS 4.2.1 VOLATILE MEMORY (RAM) Default Wiper Resistance Typical Code POR Wiper There are six volatile memory locations. These are: Code R Value AB Setting 8-bit 7-bit • Volatile Wiper 0 • Volatile Wiper 1 -502 5.0k Mid scale 80h 40h • Volatile Wiper 2 -103 10.0k Mid scale 80h 40h • Volatile Wiper 3 -503 50.0k Mid scale 80h 40h • Terminal Control (TCON0) Register 0 -104 100.0k Mid scale 80h 40h • Terminal Control (TCON)1 Register 1 TABLE 4-2: MEMORY MAP AND THE SUPPORTED COMMANDS Memory Factory Address Function Allowed Commands Disallowed Commands (1) Type Initialization 00h Volatile Wiper 0 RAM Read, Write, — 7-bit 040h Increment, Decrement 8-bit 080h 01h Volatile Wiper 1 RAM Read, Write, — 7-bit 040h Increment, Decrement 8-bit 080h 02h Reserved — None All — 03h Reserved — None All — 04h Volatile RAM Read, Write Increment, Decrement 1FFh TCON0 Register 05h Reserved — None All — 06h Volatile Wiper 2 RAM Read, Write, — 7-bit 040h Increment, Decrement 8-bit 080h 07h Volatile Wiper 3 RAM Read, Write, — 7-bit 040h Increment, Decrement 8-bit 080h 08h Reserved — None All — 09h Reserved — None All — 0Ah Volatile RAM Read, Write Increment, Decrement 1FFh TCON1 Register 0Bh-0Fh Reserved — None All — Note 1: This command on this address will generate an error condition. To exit the error condition, the user must take the CS pin to the V level and then back to the active state (V or V ). IH IL IHH DS22242A-page 40  2010 Microchip Technology Inc.

MCP433X/435X 4.2.1.1 Terminal Control (TCON) Registers disconnected from the resistor network. This allows the system to minimize the currents through the digital There are two Terminal Control (TCON) Registers. potentiometer. These are called TCON0 and TCON1. Each register contains 8 control bits. Four bits for each Wiper. The value that is written to the specified TCON register Register4-1 describes each bit of the TCON0 register, will appear on the appropriate resistor network while Register4-2 describes each bit of the TCON1 terminals when the serial command has completed. register. On a POR/BOR these registers are loaded with The state of each resistor network terminal connection 1FFh(9-bits), for all terminals connected. The host is individually controlled. That is, each terminal controller needs to detect the POR/BOR event and connection (A, B and W) can be individually connected/ then update the volatile TCON register values. R E GISTER 4-1: TCON0 BITS (1) R-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 D8 R1HW R1A R1W R1B R0HW R0A R0W R0B bit 8 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 8 D8: Reserved. Forced to “1” bit 7 R1HW: Resistor 1 Hardware Configuration Control bit This bit forces Resistor 1 into the “shutdown” configuration of the Hardware pin 1 = Resistor 1 is NOT forced to the hardware pin “shutdown” configuration 0 = Resistor 1 is forced to the hardware pin “shutdown” configuration bit 6 R1A: Resistor 1 Terminal A (P1A pin) Connect Control bit This bit connects/disconnects the Resistor 1 Terminal A to the Resistor 1 Network 1 = P1A pin is connected to the Resistor 1 Network 0 = P1A pin is disconnected from the Resistor 1 Network bit 5 R1W: Resistor 1 Wiper (P1W pin) Connect Control bit This bit connects/disconnects the Resistor 1 Wiper to the Resistor 1 Network 1 = P1W pin is connected to the Resistor 1 Network 0 = P1W pin is disconnected from the Resistor 1 Network bit 4 R1B: Resistor 1 Terminal B (P1B pin) Connect Control bit This bit connects/disconnects the Resistor 1 Terminal B to the Resistor 1 Network 1 = P1B pin is connected to the Resistor 1 Network 0 = P1B pin is disconnected from the Resistor 1 Network bit 3 R0HW: Resistor 0 Hardware Configuration Control bit This bit forces Resistor 0 into the “shutdown” configuration of the Hardware pin 1 = Resistor 0 is NOT forced to the hardware pin “shutdown” configuration 0 = Resistor 0 is forced to the hardware pin “shutdown” configuration bit 2 R0A: Resistor 0 Terminal A (P0A pin) Connect Control bit This bit connects/disconnects the Resistor 0 Terminal A to the Resistor 0 Network 1 = P0A pin is connected to the Resistor 0 Network 0 = P0A pin is disconnected from the Resistor 0 Network bit 1 R0W: Resistor 0 Wiper (P0W pin) Connect Control bit This bit connects/disconnects the Resistor 0 Wiper to the Resistor 0 Network 1 = P0W pin is connected to the Resistor 0 Network 0 = P0W pin is disconnected from the Resistor 0 Network bit 0 R0B: Resistor 0 Terminal B (P0B pin) Connect Control bit This bit connects/disconnects the Resistor 0 Terminal B to the Resistor 0 Network 1 = P0B pin is connected to the Resistor 0 Network 0 = P0B pin is disconnected from the Resistor 0 Network Note 1: These bits do not affect the wiper register values.  2010 Microchip Technology Inc. DS22242A-page 41

MCP433X/435X R EGISTER 4-2: TCON1 BITS (1) R-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 D8 R3HW R3A R3W R3B R2HW R2A R2W R2B bit 8 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 8 D8: Reserved. Forced to “1” bit 7 R3HW: Resistor 3 Hardware Configuration Control bit This bit forces Resistor 3 into the “shutdown” configuration of the Hardware pin 1 = Resistor 3 is NOT forced to the hardware pin “shutdown” configuration 0 = Resistor 3 is forced to the hardware pin “shutdown” configuration bit 6 R3A: Resistor 3 Terminal A (P3A pin) Connect Control bit This bit connects/disconnects the Resistor 3 Terminal A to the Resistor 3 Network 1 = P3A pin is connected to the Resistor 3 Network 0 = P3A pin is disconnected from the Resistor 3 Network bit 5 R3W: Resistor 3 Wiper (P3W pin) Connect Control bit This bit connects/disconnects the Resistor 3 Wiper to the Resistor 3 Network 1 = P3W pin is connected to the Resistor 3 Network 0 = P3W pin is disconnected from the Resistor 3 Network bit 4 R3B: Resistor 3 Terminal B (P3B pin) Connect Control bit This bit connects/disconnects the Resistor 3 Terminal B to the Resistor 3 Network 1 = P3B pin is connected to the Resistor 3 Network 0 = P3B pin is disconnected from the Resistor 3 Network bit 3 R2HW: Resistor 2 Hardware Configuration Control bit This bit forces Resistor 2 into the “shutdown” configuration of the Hardware pin 1 = Resistor 2 is NOT forced to the hardware pin “shutdown” configuration 0 = Resistor 2 is forced to the hardware pin “shutdown” configuration bit 2 R2A: Resistor 2 Terminal A (P0A pin) Connect Control bit This bit connects/disconnects the Resistor 2 Terminal A to the Resistor 2 Network 1 = P2A pin is connected to the Resistor 2 Network 0 = P2A pin is disconnected from the Resistor 2 Network bit 1 R2W: Resistor 2 Wiper (P0W pin) Connect Control bit This bit connects/disconnects the Resistor 2 Wiper to the Resistor 2 Network 1 = P2W pin is connected to the Resistor 2 Network 0 = P2W pin is disconnected from the Resistor 2 Network bit 0 R2B: Resistor 2 Terminal B (P2B pin) Connect Control bit This bit connects/disconnects the Resistor 2 Terminal B to the Resistor 2 Network 1 = P2B pin is connected to the Resistor 2 Network 0 = P2B pin is disconnected from the Resistor 2 Network Note 1: These bits do not affect the wiper register values. DS22242A-page 42  2010 Microchip Technology Inc.

MCP433X/435X 5.0 RESISTOR NETWORK 5.1 Resistor Ladder Module The Resistor Network has either 7-bit or 8-bit The resistor ladder is a series of equal value resistors resolution. Each Resistor Network allows zero scale to (RS) with a connection point (tap) between the two full scale connections. Figure5-1 shows a block resistors. The total number of resistors in the series diagram for the resistive network of a device. (ladder) determines the RAB resistance (see Figure5-1). The end points of the resistor ladder are The Resistor Network is made up of several parts. connected to analog switches which are connected to These include: the device terminal A and terminal B pins. The R AB • Resistor Ladder (and R ) resistance has small variations over voltage S • Wiper and temperature. • Shutdown (Terminal Connections) For an 8-bit device, there are 256 resistors in a string Devices have either four resistor networks. These are between terminal A and terminal B. The wiper can be referred to as Pot 0, Pot 1, Pot 2 and Pot 3. set to tap onto any of these 256 resistors thus providing 257 possible settings (including terminal A and A terminalB). For a 7-bit device, there are 128 resistors in a string 8-Bit 7-Bit between terminal A and terminal B. The wiper can be N = N = 257 128 set to tap onto any of these 128 resistors thus providing (100h) (80h) 129 possible settings (including terminal A and R (1) R W terminalB). S Equation5-1 shows the calculation for the step 256 127 resistance. RS RW (1) (FFh) (7Fh) EQUATION 5-1: R CALCULATION 255 126 S (FEh) (7Eh) R (1) R RABRS W RS = ---2---5A---6-B--- 8-bit Device W R R = -------A---B---- 7-bit Device 1 1 S 128 (01h) (01h) R (1) R W S 0 0 (00h) (00h) R (1) W Analog Mux B Note1: The wiper resistance is dependent on several factors including, wiper code, device V , Terminal voltages (on A, B DD and W), and temperature. Also for the same conditions, each tap selection resistance has a small variation. This R variation has greater effects on W some specifications (such as INL) for the smaller resistance devices (5.0k) compared to larger resistance devices (100.0k). FIGURE 5-1: Resistor Block Diagram.  2010 Microchip Technology Inc. DS22242A-page 43

MCP433X/435X 5.2 Wiper TABLE 5-1: VOLATILE WIPER VALUE VS. WIPER POSITION MAP Each tap point (between the R resistors) is a S connection point for an analog switch. The opposite Wiper Setting side of the analog switch is connected to a common Properties signal which is connected to the Terminal W (Wiper) 7-bit 8-bit pin. 3FFh- 3FFh- Reserved (Full Scale (W = A)), A value in the volatile wiper register selects which 081h 101h Increment and Decrement analog switch to close, connecting the W terminal to commands ignored the selected node of the resistor ladder. 080h 100h Full Scale (W = A), The wiper can connect directly to Terminal B or to Increment commands ignored Terminal A. A zero scale connection, connects the 07Fh- 0FFh- W = N Terminal W (wiper) to Terminal B (wiper setting of 041h 081h 000h). A full scale connection, connects the Terminal W 040h 080h W = N (Mid Scale) (wiper) to Terminal A (wiper setting of 100h or 80h). In 03Fh- 07Fh- W = N these configurations the only resistance between the 001h 001h Terminal W and the other Terminal (A or B) is that of the analog switches. 000h 000h Zero Scale (W = B) Decrement command ignored A wiper setting value greater than full scale (wiper setting of 100h for 8-bit device or 80h for 7-bit devices) will also be a full scale setting (Terminal W (wiper) con- nected to Terminal A). Table5-1 illustrates the full wiper setting map. Equation5-2 illustrates the calculation used to determine the resistance between the wiper and terminal B. EQUATION 5-2: R CALCULATION WB R N R = ----A----B------+R 8-bit Device WB 256 W N = 0 to 256 (decimal) R N R = ----A----B------+R 7-bit Device WB 128 W N = 0 to 128 (decimal) DS22242A-page 44  2010 Microchip Technology Inc.

MCP433X/435X 5.3 Shutdown The RxHW bit does NOT corrupt the values in the Volatile Wiper Registers nor the TCON register. When Shutdown is used to minimize the device’s current the Shutdown mode is exited (RxHW bit = 1): consumption. The MCP43XX has one method to • The device returns to the Wiper setting specified achieve this: by the Volatile Wiper value • Terminal Control Register (TCON) • The TCON register bits return to controlling the This is different from the MCP42XXX devices in that the terminal connection state Hardware Shutdown pin (SHDN) has been replaced by a RESET pin. The Hardware Shutdown pin function is A still available via software commands to the TCON k r register. o w W et 5.3.1 TERMINAL CONTROL REGISTER N r (TCON) o st si The Terminal Control (TCON) register is a volatile e R register used to configure the connection of each B resistor network terminal pin (A, B and W) to the FIGURE 5-2: Resistor Network Shutdown Resistor Network. These registers are shown in State (RxHW = 0). Register4-1 and Register4-2. The RxHW bit forces the selected resistor network into the same state as the MCP42X1’s SHDN pin. Alternate low-power configurations may be achieved with the RxA, RxW and RxB bits. When the RxHW bit is “0”: • The P0A, P1A, P2A and P3A terminals are disconnected • The P0W, P1W, P2W and P3W terminals are simultaneously connect to the P0B, P1B, P2B and P3B terminals, respectively (see Figure5-2) Note: When the RxHW bit forces the resistor network into the hardware SHDN state, the state of the TCON0 or TCON1 register’s RxA, RxW and RxB bits is overridden (ignored). When the state of the RxHW bit no longer forces the resistor network into the hardware SHDN state, the TCON0 or TCON1 register’s RxA, RxW and RxB bits return to controlling the terminal connection state. In other words, the RxHW bit does not corrupt the state of the RxA, RxW and RxB bits.  2010 Microchip Technology Inc. DS22242A-page 45

MCP433X/435X NOTES: DS22242A-page 46  2010 Microchip Technology Inc.

MCP433X/435X 6.0 SERIAL INTERFACE (SPI) Typical SPI Interface is shown in Figure6-1. In the SPI interface, the Master’s Output pin is connected to the The MCP43XX devices support the SPI serial protocol. Slave’s Input pin and the Master’s Input pin is This SPI operates in the Slave mode (does not connected to the Slave’s Output pin. generate the serial clock). The MCP4XXX SPI’s module supports two (of the four) The SPI interface uses up to four pins. These are: standard SPI modes. These are Mode 0,0 and 1,1. The • CS – Chip Select SPI mode is determined by the state of the SCK pin • SCK – Serial Clock (VIH or VIL) on the when the CS pin transitions from • SDI – Serial Data In inactive (VIH) to active (VIL or VIHH). • SDO – Serial Data Out All SPI interface signals are high-voltage tolerant. Typical SPI Interface Connections Host MCP4XXX Controller SDO (Master Out – Slave In (MOSI)) SDI SDI (Master In – Slave Out (MISO)) SDO SCK SCK I/O (1) CS Note1: If high voltage commands are desired, some type of external circuitry needs to be implemented. FIGURE 6-1: Typical SPI Interface Block Diagram.  2010 Microchip Technology Inc. DS22242A-page 47

MCP433X/435X 6.1 SDI, SDO, SCK, and CS Operation 6.1.4 THE CS SIGNAL The operation of the four SPI interface pins are The Chip Select (CS) signal is used to select the device discussed in this section. These pins are: and frame a command sequence. To start a command, or sequence of commands, the CS signal must • SDI (Serial Data In) transition from the inactive state (V ) to an active state IH • SDO (Serial Data Out) (V or V ). IL IHH • SCK (Serial Clock) After the CS signal has gone active, the SDO pin is • CS (Chip Select) driven and the clock bit counter is reset. The serial interface works on either 8-bit or 16-bit boundaries depending on the selected command. The Note: There is a required delay after the CS pin Chip Select (CS) pin frames the SPI commands. goes active to the 1st edge of the SCK pin. 6.1.1 SERIAL DATA IN (SDI) If an error condition occurs for an SPI command, then the command byte’s Command Error (CMDERR) bit The Serial Data In (SDI) signal is the data signal into (on the SDO pin) will be driven low (V ). To exit the IL the device. The value on this pin is latched on the rising error condition, the user must take the CS pin to the V IH edge of the SCK signal. level. 6.1.2 SERIAL DATA OUT (SDO) When the CS pin returns to the inactive state (VIH) the SPI module resets (including the Address Pointer). The Serial Data Out (SDO) signal is the data signal out While the CS pin is in the inactive state (V ), the serial IH of the device. The value on this pin is driven on the interface is ignored. This allows the host controller to falling edge of the SCK signal. interface to other SPI devices using the same SDI, Once the CS pin is forced to the active level (V or SDO and SCK signals. IL V ), the SDO pin will be driven. The state of the SDO IHH The CS pin has an internal pull-up resistor. The resistor pin is determined by the serial bit’s position in the is disabled when the voltage on the CS pin is at the V IL command, the command selected, and if there is a level. This means that when the CS pin is not driven, command error state (CMDERR). the internal pull-up resistor will pull this signal to the V IH level. When the CS pin is driven low (V ), the 6.1.3 SERIAL CLOCK (SCK) IL resistance becomes very large to reduce the device (SPI FREQUENCY OF OPERATION) current consumption. The SPI interface is specified to operate up to 10MHz. The high voltage capability of the CS pin allows High The actual clock rate depends on the configuration of Voltage commands. Support of High Voltage the system and the serial command used. Table6-1 commands allows circuit compatibility with the shows the SCK frequency. corresponding nonvolatile device. TABLE 6-1: SCK FREQUENCY (1) Command Memory Type Access Write, Read Increment, Decrement Volatile SDI, SDO 10MHz 10MHz Memory Note 1: This is the maximum clock frequency without an external pull-up resistor. DS22242A-page 48  2010 Microchip Technology Inc.

MCP433X/435X 6.2 The SPI Modes 6.2.2 MODE 1,1 The SPI module supports two (of the four) standard SPI In Mode 1,1: SCK Idle state = high (VIH), data is modes. These are Mode 0,0 and 1,1. The mode is clocked in on the SDI pin on the rising edge of SCK and determined by the state of the SDI pin on the rising clocked out on the SDO pin on the falling edge of SCK. edge of the 1st clock bit (of the 8-bit byte). 6.3 SPI Waveforms 6.2.1 MODE 0,0 Figure6-2 through Figure6-5 show the different SPI In Mode 0,0: SCK Idle state = low (VIL), data is clocked command waveforms. Figure6-2 and Figure6-3 are in on the SDI pin on the rising edge of SCK and clocked read and write commands. Figure6-4 and Figure6-5 out on the SDO pin on the falling edge of SCK. are Increment and Decrement commands. Support of High Voltage commands allows circuit compatibility with the corresponding nonvolatile device. VIH VIHH CS VIL SCK Write to SSPBUF CMDERR bit SDO bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 AD3 AD2 AD1 AD0 X D8 D7 D6 D5 D4 D3 D2 D1 D0 SDI bit15 bit14 bit13 bit12 C1 C0 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Input Sample FIGURE 6-2: 16-Bit Commands (Write, Read) – SPI Waveform (Mode 1,1). VIH VIHH CS VIL SCK Write to SSPBUF CMDERR bit SDO bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 AD3 AD2 AD1 AD0 X D8 D7 D6 D5 D4 D3 D2 D1 D0 SDI bit15 bit14 bit13 bit12 C1 C0 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Input Sample FIGURE 6-3: 16-Bit Commands (Write, Read) – SPI Waveform (Mode 0,0).  2010 Microchip Technology Inc. DS22242A-page 49

MCP433X/435X CS VIH VIHH VIL SCK Write to SSPBUF CMDERR bit “1” = Valid Command “0” = Invalid Command SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SDI AD3 AD2 AD1 AD0 C1 C0 X X bit7 bit0 Input Sample FIGURE 6-4: 8-Bit Commands (Increment, Decrement) – SPI Waveform with PIC MCU (Mode 1,1). VIH VIHH CS VIL SCK Write to SSPBUF CMDERR bit “1” = Valid Command “0” = Invalid Command SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SDI AD3 AD2 AD1 AD0 C1 C0 X X bit7 bit0 Input Sample FIGURE 6-5: 8-Bit Commands (Increment, Decrement) – SPI Waveform with PIC MCU (Mode 0,0). DS22242A-page 50  2010 Microchip Technology Inc.

MCP433X/435X 7.0 DEVICE COMMANDS 7.1 Command Byte The MCP43XX’s SPI command format supports The command byte has three fields, the address, the 16memory address locations and four commands. command, and 2 data bits, see Figure7-1. Currently Each command has two modes: only one of the data bits is defined (D8). This is for the Write command. • Normal Serial Commands • High-Voltage Serial Commands The device memory is accessed when the master sends a proper command byte to select the desired Normal serial commands are those where the CS pin is operation. The memory location getting accessed is driven to V . With high-voltage serial commands, the IL contained in the command byte’s AD3:AD0 bits. The CS pin is driven to V . In each mode, there are four IHH action desired is contained in the command byte’s possible commands. These commands are shown in C1:C0 bits, see Table7-1. C1:C0 determines if the Table7-1. desired memory location will be read, written, The 8-bit commands (Increment Wiper and incremented (wiper setting +1) or decremented (wiper Decrement Wiper commands) contain a command setting -1). The Increment and Decrement commands byte, see Figure7-1, while 16-bit commands (Read are only valid on the volatile wiper registers. Data and Write Data commands) contain a command As the command byte is being loaded into the device byte and a data byte. The command byte contains two (on the SDI pin), the device’s SDO pin is driving. The data bits, see Figure7-1. SDO pin will output high bits for the first six bits of that Table7-2 shows the supported commands for each command. On the 7th bit, the SDO pin will output the memory location and the corresponding values on the CMDERR bit state (see Section7.3 “Error SDI and SDO pins. Condition”). The 8th bit state depends on the command selected. Table7-3 shows an overview of all the SPI commands and their interaction with other device features. TABLE 7-1: COMMAND BIT OVERVIEW Operates on C1:C0 # of Volatile/ Bit Command Bits Nonvolatile States memory 11 Read Data 16-Bits Both 00 Write Data 16-Bits Both 01 Increment 8-Bits Volatile Only 10 Decrement 8-Bits Volatile Only 8-bit Command 16-bit Command Command Byte Command Byte Data Byte A A A A C C D D A A A A C C D D D D D D D D D D Command D D D D 1 0 9 8 D D D D 1 0 9 8 7 6 5 4 3 2 1 0 Bits 3 2 1 0 3 2 1 0 C C 1 0 Memory Data Memory Data 0 0 = Write Data Address Bits Address Bits 0 1 = INCR Command Command 1 0 = DECR Bits Bits 1 1 = Read Data FIGURE 7-1: General SPI Command Formats.  2010 Microchip Technology Inc. DS22242A-page 51

MCP433X/435X TABLE 7-2: MEMORY MAP AND THE SUPPORTED COMMANDS Address Data SPI String (Binary) Command Value Function (10-bits) (1) MOSI (SDI pin) MISO (SDO pin) (2) 00h Volatile Wiper 0 Write Data nn nnnn nnnn 0000 00nn nnnn nnnn 1111 1111 1111 1111 Read Data nn nnnn nnnn 0000 11nn nnnn nnnn 1111 111n nnnn nnnn Increment Wiper — 0000 0100 1111 1111 Decrement Wiper — 0000 1000 1111 1111 01h Volatile Wiper 1 Write Data nn nnnn nnnn 0001 00nn nnnn nnnn 1111 1111 1111 1111 Read Data nn nnnn nnnn 0001 11nn nnnn nnnn 1111 111n nnnn nnnn Increment Wiper — 0001 0100 1111 1111 Decrement Wiper — 0001 1000 1111 1111 02h Reserved None — — — 03h Reserved None — — — 04h (3) Volatile Write Data nn nnnn nnnn 0100 00nn nnnn nnnn 1111 1111 1111 1111 TCON 0 Register Read Data nn nnnn nnnn 0100 11nn nnnn nnnn 1111 111n nnnn nnnn 05h Reserved None — — — 06h Volatile Wiper 2 Write Data nn nnnn nnnn 0110 00nn nnnn nnnn 1111 1111 1111 1111 Read Data nn nnnn nnnn 0110 11nn nnnn nnnn 1111 111n nnnn nnnn Increment Wiper — 0110 0100 1111 1111 Decrement Wiper — 0110 1000 1111 1111 07h Volatile Wiper 3 Write Data nn nnnn nnnn 0111 00nn nnnn nnnn 1111 1111 1111 1111 Read Data nn nnnn nnnn 0111 11nn nnnn nnnn 1111 111n nnnn nnnn Increment Wiper — 0111 0100 1111 1111 Decrement Wiper — 0111 1000 1111 1111 08h Reserved None — — — 09h Reserved None — — — 0Ah (3) Volatile Write Data nn nnnn nnnn 1010 00nn nnnn nnnn 1111 1111 1111 1111 TCON 1 Register Read Data nn nnnn nnnn 1010 11nn nnnn nnnn 1111 111n nnnn nnnn 0Bh-0Fh Reserved None — — — Note 1: The data memory is only 9-bits wide, so the MSb is ignored by the device. 2: All these address/command combinations are valid, so the CMDERR bit is set. Any other address/command combina- tion is a command error state and the CMDERR bit will be clear. 3: Increment or Decrement commands are invalid for these addresses. DS22242A-page 52  2010 Microchip Technology Inc.

MCP433X/435X 7.2 Data Byte 7.3.1 ABORTING A TRANSMISSION Only the Read command and the Write command use All SPI transmissions must have the correct number of the data byte, see Figure7-1. These commands SCK pulses to be executed. The command is not concatenate the 8 bits of the data byte with the one executed until the complete number of clocks have data bit (D8) contained in the command byte to form been received. Some commands also require the CS 9-bits of data (D8:D0). The command byte format pin to be forced inactive (VIH). If the CS pin is forced to the inactive state (V ) the serial interface is reset. supports up to 9-bits of data so that the 8-bit resistor IH Partial commands are not executed. network can be set to full scale (100h or greater). This allows wiper connections to Terminal A and to SPI is more susceptible to noise than other bus TerminalB. protocols. The most likely case is that this noise corrupts the value of the data being clocked into the The D9 bit is currently unused, and corresponds to the MCP43XX or the SCK pin is injected with extra clock position on the SDO data of the CMDERR bit. pulses. This may cause data to be corrupted in the device, or a command error to occur, since the address 7.3 Error Condition and command bits were not a valid combination. The The CMDERR bit indicates if the four address bits extra SCK pulse will also cause the SPI data (SDI) and received (AD3:AD0) and the two command bits clock (SCK) to be out of sync. Forcing the CS pin to the received (C1:C0) are a valid combination (see inactive state (VIH) resets the serial interface. The SPI Table4-2). The CMDERR bit is high if the combination interface will ignore activity on the SDI and SCK pins is valid and low if the combination is invalid. until the CS pin transition to the active state is detected (V to V or V to V ). The command error bit will also be low if a write to a IH IL IH IHH nonvolatile address has been specified and another Note1: When data is not being received by the SPI command occurs before the CS pin is driven MCP43XX, It is recommended that the inactive (V ). IH CS pin be forced to the inactive level (V ) IL SPI commands that do not have a multiple of 8 clocks 2: It is also recommended that long are ignored. continuous command strings should be Once an error condition has occurred, any following broken down into single commands or commands are ignored. All following SDO bits will be shorter continuous command strings. low until the CMDERR condition is cleared by forcing This reduces the probability of noise on the CS pin to the inactive state (VIH). the SCK pin corrupting the desired SPI commands.  2010 Microchip Technology Inc. DS22242A-page 53

MCP433X/435X 7.4 Continuous Commands Note1: It is recommended that while the CS pin is The device supports the ability to execute commands active, only one type of command should continuously. While the CS pin is in the active state (VIL be issued. When changing commands, it or VIHH). Any sequence of valid commands may be is recommended to take the CS pin received. inactive then force it back to the active The following example is a valid sequence of events: state. 1. CS pin driven active (V or V ). 2: It is also recommended that long IL IHH command strings should be broken down 2. Read Command. into shorter command strings. This 3. Increment Command (Wiper 0). reduces the probability of noise on the 4. Increment Command (Wiper 0). SCK pin corrupting the desired SPI 5. Decrement Command (Wiper 1). command string. 6. Write Command (volatile memory). 7. CS pin driven inactive (V ). IH TABLE 7-3: COMMANDS High # of Voltage Command Name Bits (V ) on IHH CS pin? Write Data 16-Bits — Read Data 16-Bits — Increment Wiper 8-Bits — Decrement Wiper 8-Bits — High-Voltage Write Data 16-Bits Yes High-Voltage Read Data 16-Bits Yes High-Voltage Increment Wiper 8-Bits Yes High-Voltage Decrement Wiper 8-Bits Yes DS22242A-page 54  2010 Microchip Technology Inc.

MCP433X/435X 7.5 Write Data 7.5.1 SINGLE WRITE TO VOLATILE Normal and High Voltage MEMORY The write operation requires that the CS pin be in the The Write command is a 16-bit command. The format active state (V or V ). Typically, the CS pin will be in of the command is shown in Figure7-2. IL IHH the inactive state (V ) and is driven to the active state IH A Write command to a volatile memory location (V ). The 16-bit Write command (command byte and IL changes that location after a properly formatted Write data byte) is then clocked in on the SCK and SDI pins. command (16-clock) have been received. Once all 16 bits have been received, the specified volatile address is updated. A write will not occur if the write command isn’t exactly 16 clocks pulses. This protects against system issues from corrupting the nonvolatile memory locations. Figure6-2 and Figure6-3 show possible waveforms for a single write. COMMAND BYTE DATA BYTE A A A A 0 0 D D D D D D D D D D SDI D D D D 9 8 7 6 5 4 3 2 1 0 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Valid Address/Command combination SDO 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Invalid Address/Command combination (1) Note1: If an Error Condition occurs (CMDERR = L), all following SDO bits will be low until the CMDERR condition is cleared (the CS pin is forced to the inactive state). FIGURE 7-2: Write Command – SDI and SDO States.  2010 Microchip Technology Inc. DS22242A-page 55

MCP433X/435X 7.5.2 CONTINUOUS WRITES TO VOLATILE MEMORY Continuous writes are possible only when writing to the volatile memory registers (address 00h, 01h and 04h). Figure7-3 shows the sequence for three continuous writes. The writes do not need to be to the same volatile memory address. COMMAND BYTE DATA BYTE A A A A 0 0 D9 D D D D D D D D D SDI D D D D 8 7 6 5 4 3 2 1 0 3 2 1 0 SDO 1 1 1 1 1 1 1* 1 1 1 1 1 1 1 1 1 A A A A 0 0 D9 D D D D D D D D D D D D D 8 7 6 5 4 3 2 1 0 3 2 1 0 1 1 1 1 1 1 1* 1 1 1 1 1 1 1 1 1 A A A A 0 0 D9 D D D D D D D D D D D D D 8 7 6 5 4 3 2 1 0 3 2 1 0 1 1 1 1 1 1 1* 1 1 1 1 1 1 1 1 1 Note1: If a Command Error (CMDERR) occurs at this bit location (*), then all following SDO bits will be driven low until the CS pin is driven inactive (V ). IH FIGURE 7-3: Continuous Write Sequence. DS22242A-page 56  2010 Microchip Technology Inc.

MCP433X/435X 7.6 Read Data 7.6.1 SINGLE READ Normal and High Voltage The read operation requires that the CS pin be in the active state (V or V ). Typically, the CS pin will be in The Read command is a 16-bit command. The format IL IHH the inactive state (V ) and is driven to the active state of the command is shown in Figure7-4. IH (V or V ). The 16-bit Read command (command IL IHH The first 6 bits of the Read command determine the byte and data byte) is then clocked in on the SCK and address and the command. The 7th clock will output SDI pins. The SDO pin starts driving data on the 7th bit the CMDERR bit on the SDO pin. The remaining (CMDERR bit) and the addressed data comes out on 9-clocks the device will transmit the 9 data bits (D8:D0) the 8th through 16th clocks. Figure6-2 through of the specified address (AD3:AD0). Figure6-3 show possible waveforms for a single read. Figure7-4 shows the SDI and SDO information for a Read command. COMMAND BYTE DATA BYTE A A A A 1 1 X X X X X X X X X X SDI D D D D 3 2 1 0 SDO 1 1 1 1 1 1 1 D D D D D D D D D Valid Address/Command combination 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Attempted Memory Read of Reserved Memory location READ DATA FIGURE 7-4: Read Command – SDI and SDO States.  2010 Microchip Technology Inc. DS22242A-page 57

MCP433X/435X 7.6.2 CONTINUOUS READS Figure7-5 shows the sequence for three continuous reads. The reads do not need to be to the same Continuous reads allow the devices memory to be read memory address. quickly. Continuous reads are possible to all memory locations. COMMAND BYTE DATA BYTE A A A A 1 1 X X X X X X X X X X SDI D D D D 3 2 1 0 SDO 1 1 1 1 1 1 1* D D D D D D D D D 8 7 6 5 4 3 2 1 0 A A A A 1 1 X X X X X X X X X X D D D D 3 2 1 0 1 1 1 1 1 1 1* D D D D D D D D D 8 7 6 5 4 3 2 1 0 A A A A 1 1 X X X X X X X X X X D D D D 3 2 1 0 1 1 1 1 1 1 1* D D D D D D D D D 8 7 6 5 4 3 2 1 0 Note1: If a Command Error (CMDERR) occurs at this bit location (*), then all following SDO bits will be driven low until the CS pin is driven inactive (V ). IH FIGURE 7-5: Continuous Read Sequence. DS22242A-page 58  2010 Microchip Technology Inc.

MCP433X/435X 7.7 Increment Wiper 7.7.1 SINGLE INCREMENT Normal and High Voltage Typically, the CS pin starts at the inactive state (V ), IH but may already be in the active state due to the The Increment command is an 8-bit command. The completion of another command. Increment command can only be issued to volatile memory locations. The format of the command is Figure6-4 through Figure6-5 show possible shown in Figure7-6. waveforms for a single increment. The increment operation requires that the CS pin be in the active state An Increment command to the volatile memory location (V or V ). Typically, the CS pin will be in the inactive changes that location after a properly formatted com- IL IHH state (V ) and is driven to the active state (V or V ). mand (8-clocks) have been received. IH IL IHH The 8-bit Increment command (command byte) is then Increment commands provide a quick and easy clocked in on the SDI pin by the SCK pins. The SDO pin method to modify the value of the volatile wiper location drives the CMDERR bit on the 7th clock. by +1 with minimal overhead. The wiper value will increment up to 100h on 8-bit devices and 80h on 7-bit devices. After the wiper value COMMAND BYTE has reached full scale (8-bit = 100h, 7-bit = 80h), the wiper value will not be incremented further. If the wiper (INCR COMMAND (n+1)) register has a value between 101h and 1FFh, the A A A A 0 1 X X Increment command is disabled. See Table7-4 for SDI D D D D additional information on the Increment command 3 2 1 0 versus the current volatile wiper value. 1 1 1 1 1 1 1* 1 Note1, 2 The increment operations only require the Increment SDO 1 1 1 1 1 1 0 0 Note1,3 command byte while the CS pin is active (VILor VIHH) for a single increment. Note1: Only functions when writing the volatile After the wiper is incremented to the desired position, wiper registers (AD3:AD0) 0h and 1h. the CS pin should be forced to V to ensure that IH 2: Valid Address/Command combination. unexpected transitions on the SCK pin do not cause 3: Invalid Address/Command combination the wiper setting to change. Driving the CS pin to VIH all following SDO bits will be low until the should occur as soon as possible (within device CMDERR condition is cleared. (the CS specifications) after the last desired increment occurs. pin is forced to the inactive state). TABLE 7-4: INCREMENT OPERATION VS. 4: If a Command Error (CMDERR) occurs VOLATILE WIPER VALUE at this bit location (*), then all following SDO bits will be driven low until the CS Current Wiper Setting Increment pin is driven inactive (VIH). Wiper (W) Command Properties 7-bit 8-bit Operates? FIGURE 7-6: Increment Command – Pot Pot SDI and SDO States. 3FFh 3FFh Reserved No 081h 101h (Full Scale (W = A)) Note: Table7-2 shows the valid addresses for 080h 100h Full Scale (W = A) No the Increment Wiper command. Other 07Fh 0FFh W = N addresses are invalid. 041h 081 040h 080h W = N (Mid-scale) Yes 03Fh 07Fh W = N 001h 001 000h 000h Zero Scale (W = B) Yes  2010 Microchip Technology Inc. DS22242A-page 59

MCP433X/435X 7.7.2 CONTINUOUS INCREMENTS Increment commands can be sent repeatedly without raising CS until a desired condition is met. Continuous increments are possible only when writing to the volatile memory registers (address 00h, 01h, 06h When executing a continuous command string, the and 07h). Increment command can be followed by any other valid command. Figure7-7 shows a continuous increment sequence for three continuous writes. The writes do not need to be The wiper terminal will move after the command has to the same volatile memory address. been received (8th clock). When executing an continuous Increment commands, After the wiper is incremented to the desired position, the selected wiper will be altered from n to n+1 for each the CS pin should be forced to VIH to ensure that Increment command received. The wiper value will unexpected transitions (on the SCK pin do not cause increment up to 100h on 8-bit devices and 80h on 7-bit the wiper setting to change). Driving the CS pin to VIH devices. After the wiper value has reached full scale should occur as soon as possible (within device (8-bit = 100h, 7-bit = 80h), the wiper value will not be specifications) after the last desired increment occurs. incremented further. If the wiper register has a value between 101h and 1FFh, the Increment command is disabled. COMMAND BYTE COMMAND BYTE COMMAND BYTE (INCR COMMAND (n+1)) (INCR COMMAND (n+2)) (INCR COMMAND (n+3)) A A A A 0 1 X X A A A A 0 1 X X A A A A 0 1 X X SDI D D D D D D D D D D D D 3 2 1 0 3 2 1 0 3 2 1 0 1 1 1 1 1 1 1* 1 1 1 1 1 1 1 1* 1 1 1 1 1 1 1 1* 1 Note1, 2 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note3, 4 SDO 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Note3, 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 Note3, 4 Note1: Only functions when writing the volatile wiper registers (AD3:AD0) 0h and 1h. 2: Valid Address/Command combination. 3: Invalid Address/Command combination. 4: If an Error Condition occurs (CMDERR = L), all following SDO bits will be low until the CMDERR condition is cleared (the CS pin is forced to the inactive state). FIGURE 7-7: Continuous Increment Command – SDI and SDO States. DS22242A-page 60  2010 Microchip Technology Inc.

MCP433X/435X 7.8 Decrement Wiper 7.8.1 SINGLE DECREMENT Normal and High Voltage Typically, the CS pin starts at the inactive state (V ), IH but may already be in the active state due to the The Decrement command is an 8-bit command. The completion of another command. Decrement command can only be issued to volatile memory locations. The format of the command is Figure6-4 through Figure6-5 show possible shown in Figure7-6. waveforms for a single decrement. The decrement operation requires that the CS pin be in the active state A Decrement command to the volatile memory location (V or V ). Typically, the CS pin will be in the inactive changes that location after a properly formatted IL IHH state (V ) and is driven to the active state (V or V ). command (8 clocks) have been received. IH IL IHH Then the 8-bit Decrement command (command byte) is Decrement commands provide a quick and easy clocked in on the SDI pin by the SCK pins. The SDO pin method to modify the value of the volatile wiper location drives the CMDERR bit on the 7th clock. by -1 with minimal overhead. The wiper value will decrement from the wiper’s full scale value (100h on 8-bit devices and 80h on 7-bit COMMAND BYTE devices). Above the wiper’s full scale value (8-bit= (DECR COMMAND (n+1)) 101h to 1FFh, 7-bit = 81h to FFh), the Decrement com- mand is disabled. If the wiper register has a zero scale A A A A 1 0 X X value (000h), then the wiper value will not decrement. SDI D D D D See Table7-5 for additional information on the Decre- 3 2 1 0 ment command vs. the current volatile wiper value. 1 1 1 1 1 1 1* 1 Note1, 2 The Decrement commands only require the Decrement SDO 1 1 1 1 1 1 0 0 Note1, 3 command byte, while the CS pin is active (V or V ) IL IHH for a single decrement. Note1: Only functions when writing the volatile After the wiper is decremented to the desired position, wiper registers (AD3:AD0) 0h and 1h. the CS pin should be forced to V to ensure that IH 2: Valid Address/Command combination. unexpected transitions on the SCK pin do not cause the wiper setting to change. Driving the CS pin to V 3: Invalid Address/Command combination IH should occur as soon as possible (within device all following SDO bits will be low until the specifications) after the last desired decrement occurs. CMDERR condition is cleared. (the CS pin is forced to the inactive TABLE 7-5: DECREMENT OPERATION VS. state). VOLATILE WIPER VALUE 4: If a Command Error (CMDERR) occurs Current Wiper at this bit location (*), then all following Setting Decrement SDO bits will be driven low until the CS Wiper (W) Command pin is driven inactive (VIH). 7-bit 8-bit Properties Operates? Pot Pot FIGURE 7-8: Decrement Command – SDI and SDO States. 3FFh 3FFh Reserved No 081h 101h (Full Scale (W = A)) Note: Table7-2 shows the valid addresses for 080h 100h Full Scale (W = A) Yes the Decrement Wiper command. Other 07Fh 0FFh W = N addresses are invalid. 041h 081 040h 080h W = N (Mid-scale) Yes 03Fh 07Fh W = N 001h 001 000h 000h Zero Scale (W = B) No  2010 Microchip Technology Inc. DS22242A-page 61

MCP433X/435X 7.8.2 CONTINUOUS DECREMENTS Decrement commands can be sent repeatedly without raising CS until a desired condition is met. Continuous decrements are possible only when writing to the volatile memory registers (address 00h, 01h, and When executing a continuous command string, the 04h). Decrement command can be followed by any other valid command. Figure7-9 shows a continuous decrement sequence for three continuous writes. The writes do not need to The wiper terminal will move after the command has be to the same volatile memory address. been received (8th clock). When executing continuous Decrement commands, After the wiper is decremented to the desired position, the selected wiper will be altered from n to n-1 for each the CS pin should be forced to VIH to ensure that Decrement command received. The wiper value will “unexpected” transitions (on the SCK pin do not cause decrement from the wiper’s full scale value (100h on the wiper setting to change). Driving the CS pin to VIH 8-bit devices and 80h on 7-bit devices). Above the should occur as soon as possible (within device wiper’s full scale value (8-bit = 101h to 1FFh, specifications) after the last desired decrement occurs. 7-bit=81h to FFh), the Decrement command is disabled. If the Wiper register has a zero scale value (000h), then the wiper value will not decrement. See Table7-5 for additional information on the Decrement command vs. the current volatile wiper value. COMMAND BYTE COMMAND BYTE COMMAND BYTE (DECR COMMAND (n-1)) (DECR COMMAND (n-1)) (DECR COMMAND (n-1)) A A A A 1 0 X X A A A A 1 0 X X A A A A 1 0 X X SDI D D D D D D D D D D D D 3 2 1 0 3 2 1 0 3 2 1 0 1 1 1 1 1 1 1* 1 1 1 1 1 1 1 1* 1 1 1 1 1 1 1 1* 1 Note1, 2 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note3, 4 SDO 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Note3, 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 Note3, 4 Note1: Only functions when writing the volatile wiper registers (AD3:AD0) 0h and 1h. 2: Valid Address/Command combination. 3: Invalid Address/Command combination. 4: If an Error Condition occurs (CMDERR = L), all following SDO bits will be low until the CMDERR condition is cleared (the CS pin is forced to the inactive state). FIGURE 7-9: Continuous Decrement Command – SDI and SDO States. DS22242A-page 62  2010 Microchip Technology Inc.

MCP433X/435X 8.0 APPLICATIONS EXAMPLES 5V Voltage 3V Digital potentiometers have a multitude of practical Regulator uses in modern electronic circuits. The most popular uses include precision calibration of set point thresh- olds, sensor trimming, LCD bias trimming, audio atten- PIC® MCU MCP4XXX uation, adjustable power supplies, motor control SDI SDI overcurrent trip setting, adjustable gain amplifiers and offset trimming. The MCP433X/435X devices can be CS CS SCK SCK used to replace the common mechanical trim pot in applications where the operating and terminal voltages I/O RESET are within CMOS process limitations (V = 2.7V to DD 5.5V). SDO SDO 8.1 Split Rail Applications FIGURE 8-1: Example Split Rail System1. All inputs that would be used to interface to a host controller support high voltage on their input pin. This allows the MCP43XX device to be used in split power Voltage 5V rail applications. Regulator An example of this is a battery application where the 3V PIC® MCU is directly powered by the battery supply PIC® MCU MCP4XXX (4.8V) and the MCP43XX device is powered by the 3.3V regulated voltage. SDI SDI CS CS For SPI applications, these inputs are: SCK SCK • CS I/O RESET • SCK • SDI (or SDI/SDO) SDO SDO • RESET FIGURE 8-2: Example Split Rail Figure8-1 through Figure8-2 show three example split System2. rail systems. In this system, the MCP43XX interface input signals need to be able to support the PIC MCU TABLE 8-1: V – V COMPARISONS OH IH output high voltage (V ). OH PIC® MCU (1) MCP4XXX (2) In Example #1 (Figure8-1), the MCP43XX interface Comment input signals need to be able to support the PIC MCU V V V V V V DD IH OH DD IH OH output high voltage (V ). If the split rail voltage delta OH 5.5 4.4 4.4 2.7 1.215 — (3) becomes too large, then the customer may be required to do some level shifting due to MCP43XX V levels 5.0 4.0 4.0 3.0 1.35 — (3) OH related to host controller VIH levels. 4.5 3.6 3.6 3.3 1.485 — (3) In Example #2 (Figure8-2), the MCP43XX interface 3.3 2.64 2.64 4.5 2.025 — (3) input signals need to be able to support the lower 3.0 2.4 2.4 5.0 2.25 — (3) voltage of the PIC MCU output high voltage level (V ). OH 2.7 2.16 2.16 5.5 2.475 — (3) Table8-1 shows an example PIC microcontroller I/O Note 1: V minimum = 0.8 * V ; voltage specifications and the MCP43XX OH DD V maximum = 0.6V specifications. So this PIC MCU operating at 3.3V will OL V minimum = 0.8 * V ; drive a V at 2.64V, and for the MCP43XX operating IH DD OH V maximum = 0.2 * V ; at 5.5V, the V is 2.47V. Therefore, the interface IL DD IH 2: V minimum (SDA only) =; signals meet specifications. OH V maximum = 0.2 * V OL DD V minimum = 0.45 * V ; IH DD V maximum = 0.2 * V IL DD 3: The only MCP4XXX output pin is SDO, which is open-drain (or open-drain with internal pull-up) with high voltage support  2010 Microchip Technology Inc. DS22242A-page 63

MCP433X/435X 8.2 Techniques to Force the CS Pin to VIHH PIC10F206 R 1 The circuit in Figure8-3 shows a method using the GP0 TC1240A doubling charge pump. When the SHDN pin MCP4XXX is high, the TC1240A is off, and the level on the CS pin is controlled by the PIC® microcontrollers (MCUs) IO2 pin. GP2 CS When the SHDN pin is low, the TC1240A is on and the C1 C2 V voltage is 2 * V . The resistor R allows the CS OUT DD 1 pin to go higher than the voltage such that the PIC MCU’s IO2 pin “clamps” at approximately V . FIGURE 8-4: MCP4XXX Nonvolatile DD Digital Potentiometer Evaluation Board (MCP402XEV) implementation to generate the TC1240A V voltage. IHH PIC® MCU VIN C+ C1 SHDN C- 8.3 Using Shutdown Modes V IO1 OUT Figure8-5 shows a possible application circuit where the independent terminals could be used. MCP4XXX Disconnecting the wiper allows the transistor input to R 1 CS be taken to the bias voltage level (disconnecting A and IO2 or B may be desired to reduce system current). C 2 Disconnecting Terminal A modifies the transistor input by the R rheostat value to the Common B. BW Disconnecting Terminal B modifies the transistor input FIGURE 8-3: Using the TC1240A to by the RAW rheostat value to the Common A. The Generate the V Voltage. Common A and Common B connections could be IHH connected to V and V . DD SS The circuit in Figure8-4 shows the method used on the MCP402X Nonvolatile Digital Potentiometer Evaluation Board (Part Number: MCP402XEV). This method requires that the system voltage be approximately 5V. Common A This ensures that when the PIC10F206 enters a brown-out condition, there is an insufficient voltage level on the CS pin to change the stored value of the Input wiper. The “MCP402X Nonvolatile Digital A Potentiometer Evaluation Board User’s Guide” (DS51546) contains a complete schematic. GP0 is a general purpose I/O pin, while GP2 can either be a general purpose I/O pin or it can output the internal clock. To base W For the serial commands, configure the GP2 pin as an of Transistor (or Amplifier) input (high-impedance). The output state of the GP0 pin will determine the voltage on the CS pin (V or V ). IL IH For high-voltage serial commands, force the GP0 output pin to output a high level (V ) and configure the OH GP2 pin to output the internal clock. This will form a B charge pump and increase the voltage on the CS pin Input (when the system voltage is approximately 5V). Common B Balance Bias FIGURE 8-5: Example Application Circuit using Terminal Disconnects. DS22242A-page 64  2010 Microchip Technology Inc.

MCP433X/435X 8.4 Design Considerations 8.4.2 LAYOUT CONSIDERATIONS In the design of a system with the MCP43XX devices, Several layout considerations may be applicable to the following considerations should be taken into your application. These may include: account: • Noise • Power Supply Considerations • Footprint Compatibility • Layout Considerations • PCB Area Requirements 8.4.1 POWER SUPPLY 8.4.2.1 Noise CONSIDERATIONS Inductively-coupled AC transients and digital switching The typical application will require a bypass capacitor noise can degrade the input and output signal integrity, in order to filter high-frequency noise, which can be potentially masking the MCP43XX’s performance. induced onto the power supply’s traces. The bypass Careful board layout minimizes these effects and capacitor helps to minimize the effect of these noise increases the Signal-to-Noise Ratio (SNR). Multi-layer sources on signal integrity. Figure8-6 illustrates an boards utilizing a low-inductance ground plane, appropriate bypass strategy. isolated inputs, isolated outputs and proper decoupling are critical to achieving the performance that the In this example, the recommended bypass capacitor siliconis capable of providing. Particularly harsh value is 0.1µF. This capacitor should be placed as environments may require shielding of critical signals. close (within 4mm) to the device power pin (V ) as DD possible. If low noise is desired, breadboards and wire-wrapped boards are not recommended. The power source supplying these devices should be as clean as possible. If the application circuit has 8.4.2.2 Footprint Compatibility separate digital and analog power supplies, V and DD V should reside on the analog plane. The specification of the MCP43XX pinouts was done to SS allow systems to be designed to easily support the use of either the dual (MCP42XX) or quad (MCP43XX) V device. DD Figure8-7 shows how the dual pinout devices fit on the quad device footprint. For the Rheostat devices, the 0.1µF dual device is in the MSOP package, so the footprints V would need to be offset from each other. DD MCP43X1 Quad Potentiometers 0.1µF P3A 1 20 P2A r P3W 2 19 P2W e oll P3B 3 18 P2B tr CS 4 17 VDD on SCK 5 16 SDO A 35X croc VSSDSI 67 1145 RWEPSET MCP42X1 Pinout (1) W 3X/4 U/D ® Mi PP11WB 89 1122 PP00WB 3 C P1A 10 11 P0A 4 PI P TSSOP C B M CS MCP43X2 Quad Rheostat P3W 1 14 P2W P3B 2 13 P2B CS 3 12 VDD VSS VSS SCK 4 11 SDO SDI 5 10 P0B MCP42X2 Pinout FIGURE 8-6: Typical Microcontroller VSS 6 9 P0W P1B 7 8 P1W Connections. TSSOP Note1: Pin 15 (RESET) is the Shutdown (SHDN) pin on the MCP42x1 device. FIGURE 8-7: Quad Pinout (TSSOP Package) vs. Dual Pinout.  2010 Microchip Technology Inc. DS22242A-page 65

MCP433X/435X Figure8-8 shows possible layout implementations for 8.4.2.3 PCB Area Requirements an application to support the quad and dual options on In some applications, PCB area is a criteria for device the same PCB. selection. Table8-2 shows the package dimensions and area for the different package options. The table Potentiometers Devices also shows the relative area factor compared to the smallest area. For space critical applications, the QFN package would be the suggested package. MCP43X1 TABLE 8-2: PACKAGE FOOTPRINT (1) MCP42X1 Package Package Footprint Dim(emnmsi)o ns 2m) Area Pins Type Code X Y ea (m ative Ar el R Rheostat Devices 14 TSSOP ST 5.10 6.40 32.64 2.04 MCP42X2 QFN ML 4.00 4.00 16.00 1 20 MCP43X2 TSSOP ST 6.60 6.40 42.24 2.64 Note1: Does not include recommended land pattern dimensions. 8.4.3 RESISTOR TEMPCO Characterization curves of the resistor temperature coefficient (Tempco) are shown in Figure2-11, FIGURE 8-8: Layout to support Quad and Figure2-32, Figure2-52, and Figure2-72. Dual Devices. These curves show that the resistor network is designed to correct for the change in resistance as temperature increases. This technique reduces the end to end change is R resistance. AB 8.4.4 HIGH VOLTAGE TOLERANT PINS High voltage support (V ) on the Serial Interface pins IHH supports in-circuit accommodation of split rail applications and power supply sync issues. DS22242A-page 66  2010 Microchip Technology Inc.

MCP433X/435X 9.0 DEVELOPMENT SUPPORT 9.2 Technical Documentation Several additional technical documents are available to 9.1 Development Tools assist you in your design and development. These technical documents include Application Notes, Several development tools are available to assist in Technical Briefs, and Design Guides. Table9-2 shows your design and evaluation of the MCP43XX devices. some of these documents. The currently available tools are shown in Table9-1. These boards may be purchased directly from the Microchip web site at www.microchip.com. TABLE 9-1: DEVELOPMENT TOOLS Board Name Part # Supported Devices 20-pin TSSOP and SSOP Evaluation Board TSSOP20EV MCP43XX MCP4361 Evaluation Board (1) MCP43XXEV MCP4361 MCP42XX Digital Potentiometer PICtail™ Plus Demo MCP42XXDM-PTPLS MCP42XX Board MCP4XXX Digital Potentiometer Daughter Board (2) MCP4XXXDM-DB MCP42XXX, MCP42XX, MCP4021 and MCP4011 Note1: This Evaluation Board is planned to be available by March 2010. This board uses the TSSOP20EV PCB and requires the PICkit™ Serial Analyzer (see User’s Guide for details). This kit also includes 1 blank TSSOP20EV PCB. 2: Requires the use of a PICDEM™ Demo board (see User’s Guide for details). TABLE 9-2: TECHNICAL DOCUMENTATION Application Title Literature # Note Number AN1080 Understanding Digital Potentiometers Resistor Variations DS01080 AN737 Using Digital Potentiometers to Design Low-Pass Adjustable Filters DS00737 AN692 Using a Digital Potentiometer to Optimize a Precision Single Supply Photo Detect DS00692 AN691 Optimizing the Digital Potentiometer in Precision Circuits DS00691 AN219 Comparing Digital Potentiometers to Mechanical Potentiometers DS00219 — Digital Potentiometer Design Guide DS22017 — Signal Chain Design Guide DS21825  2010 Microchip Technology Inc. DS22242A-page 67

MCP433X/435X NOTES: DS22242A-page 68  2010 Microchip Technology Inc.

MCP433X/435X 10.0 PACKAGING INFORMATION 10.1 Package Marking Information 14-Lead TSSOP Example XXXXXXXX 4352502E YYWW 1004 NNN 256 20-Lead QFN (4x4) Example XXXXX 4351 XXXXXX 502EML XXXXXX ^e^31004 YYWWNNN 256 20-Lead TSSOP Example XXXXXXXX 4351502 XXXXX NNN EST^e^3256 YYWW 1004 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2010 Microchip Technology Inc. DS22242A-page 69

MCP433X/435X (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:14)(cid:18)(cid:9)(cid:19)(cid:17)(cid:20)(cid:14)(cid:18)(cid:21)(cid:9)(cid:19)(cid:22)(cid:7)(cid:11)(cid:11)(cid:9)(cid:23)(cid:24)(cid:13)(cid:11)(cid:14)(cid:18)(cid:6)(cid:9)(cid:25)(cid:19)(cid:16)(cid:26)(cid:9)(cid:27)(cid:9)(cid:3)(cid:28)(cid:3)(cid:9)(cid:22)(cid:22)(cid:9)(cid:29)(cid:30)(cid:8)(cid:31)(cid:9) (cid:16)(cid:19)(cid:19)(cid:23)(cid:10)! "(cid:30)(cid:13)(cid:6)# 2(cid:23)(cid:22)(cid:14)&(cid:24)(cid:13)(cid:14)’(cid:23)!&(cid:14)(cid:21)"(cid:22)(cid:22)(cid:13)(cid:26)&(cid:14)(cid:10)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:13)(cid:14)#(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)!((cid:14)(cid:10)(cid:27)(cid:13)(cid:11)!(cid:13)(cid:14)!(cid:13)(cid:13)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:14)(cid:31)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:20)(cid:26)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:21)(cid:20)%(cid:20)(cid:21)(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)(cid:11)&(cid:14) (cid:24)&&(cid:10)144***(cid:30)’(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:30)(cid:21)(cid:23)’4(cid:10)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:20)(cid:26)(cid:12) D N E E1 NOTE1 1 2 e b c φ A A2 A1 L1 L 5(cid:26)(cid:20)&! (cid:19)(cid:29)66(cid:29)(cid:19)+(cid:25)+(cid:8)(cid:3) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:14)6(cid:20)’(cid:20)&! (cid:19)(cid:29)7 78(cid:19) (cid:19)(cid:7)9 7"’)(cid:13)(cid:22)(cid:14)(cid:23)%(cid:14)(cid:31)(cid:20)(cid:26)! 7 (cid:15)(cid:5) (cid:31)(cid:20)&(cid:21)(cid:24) (cid:13) (cid:4)(cid:30):,(cid:14)/(cid:3)0 8 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14);(cid:13)(cid:20)(cid:12)(cid:24)& (cid:7) < < (cid:15)(cid:30)(cid:17)(cid:4) (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:13)(cid:14)(cid:25)(cid:24)(cid:20)(cid:21)3(cid:26)(cid:13)!! (cid:7)(cid:17) (cid:4)(cid:30)(cid:16)(cid:4) (cid:15)(cid:30)(cid:4)(cid:4) (cid:15)(cid:30)(cid:4), (cid:3)&(cid:11)(cid:26)#(cid:23)%%(cid:14) (cid:7)(cid:15) (cid:4)(cid:30)(cid:4), < (cid:4)(cid:30)(cid:15), 8 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)=(cid:20)#&(cid:24) + :(cid:30)(cid:5)(cid:4)(cid:14)/(cid:3)0 (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:13)(cid:14)=(cid:20)#&(cid:24) +(cid:15) (cid:5)(cid:30)-(cid:4) (cid:5)(cid:30)(cid:5)(cid:4) (cid:5)(cid:30),(cid:4) (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:13)(cid:14)6(cid:13)(cid:26)(cid:12)&(cid:24) (cid:2) (cid:5)(cid:30)(cid:6)(cid:4) ,(cid:30)(cid:4)(cid:4) ,(cid:30)(cid:15)(cid:4) 2(cid:23)(cid:23)&(cid:14)6(cid:13)(cid:26)(cid:12)&(cid:24) 6 (cid:4)(cid:30)(cid:5), (cid:4)(cid:30):(cid:4) (cid:4)(cid:30)(cid:18), 2(cid:23)(cid:23)&(cid:10)(cid:22)(cid:20)(cid:26)& 6(cid:15) (cid:15)(cid:30)(cid:4)(cid:4)(cid:14)(cid:8)+2 2(cid:23)(cid:23)&(cid:14)(cid:7)(cid:26)(cid:12)(cid:27)(cid:13) (cid:3) (cid:4)> < (cid:16)> 6(cid:13)(cid:11)#(cid:14)(cid:25)(cid:24)(cid:20)(cid:21)3(cid:26)(cid:13)!! (cid:21) (cid:4)(cid:30)(cid:4)(cid:6) < (cid:4)(cid:30)(cid:17)(cid:4) 6(cid:13)(cid:11)#(cid:14)=(cid:20)#&(cid:24) ) (cid:4)(cid:30)(cid:15)(cid:6) < (cid:4)(cid:30)-(cid:4) "(cid:30)(cid:13)(cid:6)(cid:12)# (cid:15)(cid:30) (cid:31)(cid:20)(cid:26)(cid:14)(cid:15)(cid:14) (cid:20)!"(cid:11)(cid:27)(cid:14)(cid:20)(cid:26)#(cid:13)$(cid:14)%(cid:13)(cid:11)&"(cid:22)(cid:13)(cid:14)’(cid:11)(cid:28)(cid:14) (cid:11)(cid:22)(cid:28)((cid:14))"&(cid:14)’"!&(cid:14))(cid:13)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)*(cid:20)&(cid:24)(cid:20)(cid:26)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:24)(cid:11)&(cid:21)(cid:24)(cid:13)#(cid:14)(cid:11)(cid:22)(cid:13)(cid:11)(cid:30) (cid:17)(cid:30) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)!(cid:14)(cid:2)(cid:14)(cid:11)(cid:26)#(cid:14)+(cid:15)(cid:14)#(cid:23)(cid:14)(cid:26)(cid:23)&(cid:14)(cid:20)(cid:26)(cid:21)(cid:27)"#(cid:13)(cid:14)’(cid:23)(cid:27)#(cid:14)%(cid:27)(cid:11)!(cid:24)(cid:14)(cid:23)(cid:22)(cid:14)(cid:10)(cid:22)(cid:23)&(cid:22)"!(cid:20)(cid:23)(cid:26)!(cid:30)(cid:14)(cid:19)(cid:23)(cid:27)#(cid:14)%(cid:27)(cid:11)!(cid:24)(cid:14)(cid:23)(cid:22)(cid:14)(cid:10)(cid:22)(cid:23)&(cid:22)"!(cid:20)(cid:23)(cid:26)!(cid:14)!(cid:24)(cid:11)(cid:27)(cid:27)(cid:14)(cid:26)(cid:23)&(cid:14)(cid:13)$(cid:21)(cid:13)(cid:13)#(cid:14)(cid:4)(cid:30)(cid:15),(cid:14)’’(cid:14)(cid:10)(cid:13)(cid:22)(cid:14)!(cid:20)#(cid:13)(cid:30) -(cid:30) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:20)(cid:26)(cid:12)(cid:14)(cid:11)(cid:26)#(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:20)(cid:26)(cid:12)(cid:14)(cid:10)(cid:13)(cid:22)(cid:14)(cid:7)(cid:3)(cid:19)+(cid:14).(cid:15)(cid:5)(cid:30),(cid:19)(cid:30) /(cid:3)01 /(cid:11)!(cid:20)(cid:21)(cid:14)(cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:30)(cid:14)(cid:25)(cid:24)(cid:13)(cid:23)(cid:22)(cid:13)&(cid:20)(cid:21)(cid:11)(cid:27)(cid:27)(cid:28)(cid:14)(cid:13)$(cid:11)(cid:21)&(cid:14) (cid:11)(cid:27)"(cid:13)(cid:14)!(cid:24)(cid:23)*(cid:26)(cid:14)*(cid:20)&(cid:24)(cid:23)"&(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:13)!(cid:30) (cid:8)+21 (cid:8)(cid:13)%(cid:13)(cid:22)(cid:13)(cid:26)(cid:21)(cid:13)(cid:14)(cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)((cid:14)"!"(cid:11)(cid:27)(cid:27)(cid:28)(cid:14)*(cid:20)&(cid:24)(cid:23)"&(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:13)((cid:14)%(cid:23)(cid:22)(cid:14)(cid:20)(cid:26)%(cid:23)(cid:22)’(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:10)"(cid:22)(cid:10)(cid:23)!(cid:13)!(cid:14)(cid:23)(cid:26)(cid:27)(cid:28)(cid:30) (cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:25)(cid:13)(cid:21)(cid:24)(cid:26)(cid:23)(cid:27)(cid:23)(cid:12)(cid:28)(cid:2)(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)0(cid:4)(cid:5)(cid:9)(cid:4)(cid:16)(cid:18)/ DS22242A-page 70  2010 Microchip Technology Inc.

MCP433X/435X Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2010 Microchip Technology Inc. DS22242A-page 71

MCP433X/435X $%(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)&(cid:24)(cid:7)(cid:8)(cid:9)’(cid:11)(cid:7)(cid:13)((cid:9)"(cid:30)(cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:7)(cid:15)(cid:21)(cid:7))(cid:6)(cid:9)(cid:25)*(cid:5)(cid:26)(cid:9)(cid:27)(cid:9)(cid:3)+(cid:3)+%(cid:28),(cid:9)(cid:22)(cid:22)(cid:9)(cid:29)(cid:30)(cid:8)(cid:31)(cid:9) &’"! "(cid:30)(cid:13)(cid:6)# 2(cid:23)(cid:22)(cid:14)&(cid:24)(cid:13)(cid:14)’(cid:23)!&(cid:14)(cid:21)"(cid:22)(cid:22)(cid:13)(cid:26)&(cid:14)(cid:10)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:13)(cid:14)#(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)!((cid:14)(cid:10)(cid:27)(cid:13)(cid:11)!(cid:13)(cid:14)!(cid:13)(cid:13)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:14)(cid:31)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:20)(cid:26)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:21)(cid:20)%(cid:20)(cid:21)(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)(cid:11)&(cid:14) (cid:24)&&(cid:10)144***(cid:30)’(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:30)(cid:21)(cid:23)’4(cid:10)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:20)(cid:26)(cid:12) (cid:14) D D2 EXPOSED PAD e E2 E 2 2 b 1 1 K N N NOTE1 L TOPVIEW BOTTOMVIEW A A3 A1 5(cid:26)(cid:20)&! (cid:19)(cid:29)66(cid:29)(cid:19)+(cid:25)+(cid:8)(cid:3) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:14)6(cid:20)’(cid:20)&! (cid:19)(cid:29)7 78(cid:19) (cid:19)(cid:7)9 7"’)(cid:13)(cid:22)(cid:14)(cid:23)%(cid:14)(cid:31)(cid:20)(cid:26)! 7 (cid:17)(cid:4) (cid:31)(cid:20)&(cid:21)(cid:24) (cid:13) (cid:4)(cid:30),(cid:4)(cid:14)/(cid:3)0 8 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14);(cid:13)(cid:20)(cid:12)(cid:24)& (cid:7) (cid:4)(cid:30)(cid:16)(cid:4) (cid:4)(cid:30)(cid:6)(cid:4) (cid:15)(cid:30)(cid:4)(cid:4) (cid:3)&(cid:11)(cid:26)#(cid:23)%%(cid:14) (cid:7)(cid:15) (cid:4)(cid:30)(cid:4)(cid:4) (cid:4)(cid:30)(cid:4)(cid:17) (cid:4)(cid:30)(cid:4), 0(cid:23)(cid:26)&(cid:11)(cid:21)&(cid:14)(cid:25)(cid:24)(cid:20)(cid:21)3(cid:26)(cid:13)!! (cid:7)- (cid:4)(cid:30)(cid:17)(cid:4)(cid:14)(cid:8)+2 8 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)=(cid:20)#&(cid:24) + (cid:5)(cid:30)(cid:4)(cid:4)(cid:14)/(cid:3)0 +$(cid:10)(cid:23)!(cid:13)#(cid:14)(cid:31)(cid:11)#(cid:14)=(cid:20)#&(cid:24) +(cid:17) (cid:17)(cid:30):(cid:4) (cid:17)(cid:30)(cid:18)(cid:4) (cid:17)(cid:30)(cid:16)(cid:4) 8 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)6(cid:13)(cid:26)(cid:12)&(cid:24) (cid:2) (cid:5)(cid:30)(cid:4)(cid:4)(cid:14)/(cid:3)0 +$(cid:10)(cid:23)!(cid:13)#(cid:14)(cid:31)(cid:11)#(cid:14)6(cid:13)(cid:26)(cid:12)&(cid:24) (cid:2)(cid:17) (cid:17)(cid:30):(cid:4) (cid:17)(cid:30)(cid:18)(cid:4) (cid:17)(cid:30)(cid:16)(cid:4) 0(cid:23)(cid:26)&(cid:11)(cid:21)&(cid:14)=(cid:20)#&(cid:24) ) (cid:4)(cid:30)(cid:15)(cid:16) (cid:4)(cid:30)(cid:17), (cid:4)(cid:30)-(cid:4) 0(cid:23)(cid:26)&(cid:11)(cid:21)&(cid:14)6(cid:13)(cid:26)(cid:12)&(cid:24) 6 (cid:4)(cid:30)-(cid:4) (cid:4)(cid:30)(cid:5)(cid:4) (cid:4)(cid:30),(cid:4) 0(cid:23)(cid:26)&(cid:11)(cid:21)&(cid:9)&(cid:23)(cid:9)+$(cid:10)(cid:23)!(cid:13)#(cid:14)(cid:31)(cid:11)# ? (cid:4)(cid:30)(cid:17)(cid:4) < < "(cid:30)(cid:13)(cid:6)(cid:12)# (cid:15)(cid:30) (cid:31)(cid:20)(cid:26)(cid:14)(cid:15)(cid:14) (cid:20)!"(cid:11)(cid:27)(cid:14)(cid:20)(cid:26)#(cid:13)$(cid:14)%(cid:13)(cid:11)&"(cid:22)(cid:13)(cid:14)’(cid:11)(cid:28)(cid:14) (cid:11)(cid:22)(cid:28)((cid:14))"&(cid:14)’"!&(cid:14))(cid:13)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)*(cid:20)&(cid:24)(cid:20)(cid:26)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:24)(cid:11)&(cid:21)(cid:24)(cid:13)#(cid:14)(cid:11)(cid:22)(cid:13)(cid:11)(cid:30) (cid:17)(cid:30) (cid:31)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:13)(cid:14)(cid:20)!(cid:14)!(cid:11)*(cid:14)!(cid:20)(cid:26)(cid:12)"(cid:27)(cid:11)&(cid:13)#(cid:30) -(cid:30) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:20)(cid:26)(cid:12)(cid:14)(cid:11)(cid:26)#(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:20)(cid:26)(cid:12)(cid:14)(cid:10)(cid:13)(cid:22)(cid:14)(cid:7)(cid:3)(cid:19)+(cid:14).(cid:15)(cid:5)(cid:30),(cid:19)(cid:30) /(cid:3)01 /(cid:11)!(cid:20)(cid:21)(cid:14)(cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:30)(cid:14)(cid:25)(cid:24)(cid:13)(cid:23)(cid:22)(cid:13)&(cid:20)(cid:21)(cid:11)(cid:27)(cid:27)(cid:28)(cid:14)(cid:13)$(cid:11)(cid:21)&(cid:14) (cid:11)(cid:27)"(cid:13)(cid:14)!(cid:24)(cid:23)*(cid:26)(cid:14)*(cid:20)&(cid:24)(cid:23)"&(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:13)!(cid:30) (cid:8)+21 (cid:8)(cid:13)%(cid:13)(cid:22)(cid:13)(cid:26)(cid:21)(cid:13)(cid:14)(cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)((cid:14)"!"(cid:11)(cid:27)(cid:27)(cid:28)(cid:14)*(cid:20)&(cid:24)(cid:23)"&(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:13)((cid:14)%(cid:23)(cid:22)(cid:14)(cid:20)(cid:26)%(cid:23)(cid:22)’(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:10)"(cid:22)(cid:10)(cid:23)!(cid:13)!(cid:14)(cid:23)(cid:26)(cid:27)(cid:28)(cid:30) (cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:25)(cid:13)(cid:21)(cid:24)(cid:26)(cid:23)(cid:27)(cid:23)(cid:12)(cid:28)(cid:2)(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)0(cid:4)(cid:5)(cid:9)(cid:15)(cid:17):/ DS22242A-page 72  2010 Microchip Technology Inc.

MCP433X/435X "(cid:30)(cid:13)(cid:6)# 2(cid:23)(cid:22)(cid:14)&(cid:24)(cid:13)(cid:14)’(cid:23)!&(cid:14)(cid:21)"(cid:22)(cid:22)(cid:13)(cid:26)&(cid:14)(cid:10)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:13)(cid:14)#(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)!((cid:14)(cid:10)(cid:27)(cid:13)(cid:11)!(cid:13)(cid:14)!(cid:13)(cid:13)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:14)(cid:31)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:20)(cid:26)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:21)(cid:20)%(cid:20)(cid:21)(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)(cid:11)&(cid:14) (cid:24)&&(cid:10)144***(cid:30)’(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:30)(cid:21)(cid:23)’4(cid:10)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:20)(cid:26)(cid:12)  2010 Microchip Technology Inc. DS22242A-page 73

MCP433X/435X $%(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:14)(cid:18)(cid:9)(cid:19)(cid:17)(cid:20)(cid:14)(cid:18)(cid:21)(cid:9)(cid:19)(cid:22)(cid:7)(cid:11)(cid:11)(cid:9)(cid:23)(cid:24)(cid:13)(cid:11)(cid:14)(cid:18)(cid:6)(cid:9)(cid:25)(cid:19)(cid:16)(cid:26)(cid:9)(cid:27)(cid:9)(cid:3)(cid:28)(cid:3)(cid:9)(cid:22)(cid:22)(cid:9)(cid:29)(cid:30)(cid:8)(cid:31)(cid:9) (cid:16)(cid:19)(cid:19)(cid:23)(cid:10)! "(cid:30)(cid:13)(cid:6)# 2(cid:23)(cid:22)(cid:14)&(cid:24)(cid:13)(cid:14)’(cid:23)!&(cid:14)(cid:21)"(cid:22)(cid:22)(cid:13)(cid:26)&(cid:14)(cid:10)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:13)(cid:14)#(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)!((cid:14)(cid:10)(cid:27)(cid:13)(cid:11)!(cid:13)(cid:14)!(cid:13)(cid:13)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:14)(cid:31)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:20)(cid:26)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:21)(cid:20)%(cid:20)(cid:21)(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)(cid:11)&(cid:14) (cid:24)&&(cid:10)144***(cid:30)’(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:30)(cid:21)(cid:23)’4(cid:10)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:20)(cid:26)(cid:12) D N E E1 NOTE1 1 2 b e c φ A A2 A1 L1 L 5(cid:26)(cid:20)&! (cid:19)(cid:29)66(cid:29)(cid:19)+(cid:25)+(cid:8)(cid:3) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:14)6(cid:20)’(cid:20)&! (cid:19)(cid:29)7 78(cid:19) (cid:19)(cid:7)9 7"’)(cid:13)(cid:22)(cid:14)(cid:23)%(cid:14)(cid:31)(cid:20)(cid:26)! 7 (cid:17)(cid:4) (cid:31)(cid:20)&(cid:21)(cid:24) (cid:13) (cid:4)(cid:30):,(cid:14)/(cid:3)0 8 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14);(cid:13)(cid:20)(cid:12)(cid:24)& (cid:7) < < (cid:15)(cid:30)(cid:17)(cid:4) (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:13)(cid:14)(cid:25)(cid:24)(cid:20)(cid:21)3(cid:26)(cid:13)!! (cid:7)(cid:17) (cid:4)(cid:30)(cid:16)(cid:4) (cid:15)(cid:30)(cid:4)(cid:4) (cid:15)(cid:30)(cid:4), (cid:3)&(cid:11)(cid:26)#(cid:23)%%(cid:14) (cid:7)(cid:15) (cid:4)(cid:30)(cid:4), < (cid:4)(cid:30)(cid:15), 8 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)=(cid:20)#&(cid:24) + :(cid:30)(cid:5)(cid:4)(cid:14)/(cid:3)0 (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:13)(cid:14)=(cid:20)#&(cid:24) +(cid:15) (cid:5)(cid:30)-(cid:4) (cid:5)(cid:30)(cid:5)(cid:4) (cid:5)(cid:30),(cid:4) (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:13)(cid:14)6(cid:13)(cid:26)(cid:12)&(cid:24) (cid:2) :(cid:30)(cid:5)(cid:4) :(cid:30),(cid:4) :(cid:30):(cid:4) 2(cid:23)(cid:23)&(cid:14)6(cid:13)(cid:26)(cid:12)&(cid:24) 6 (cid:4)(cid:30)(cid:5), (cid:4)(cid:30):(cid:4) (cid:4)(cid:30)(cid:18), 2(cid:23)(cid:23)&(cid:10)(cid:22)(cid:20)(cid:26)& 6(cid:15) (cid:15)(cid:30)(cid:4)(cid:4)(cid:14)(cid:8)+2 2(cid:23)(cid:23)&(cid:14)(cid:7)(cid:26)(cid:12)(cid:27)(cid:13) (cid:3) (cid:4)> < (cid:16)> 6(cid:13)(cid:11)#(cid:14)(cid:25)(cid:24)(cid:20)(cid:21)3(cid:26)(cid:13)!! (cid:21) (cid:4)(cid:30)(cid:4)(cid:6) < (cid:4)(cid:30)(cid:17)(cid:4) 6(cid:13)(cid:11)#(cid:14)=(cid:20)#&(cid:24) ) (cid:4)(cid:30)(cid:15)(cid:6) < (cid:4)(cid:30)-(cid:4) "(cid:30)(cid:13)(cid:6)(cid:12)# (cid:15)(cid:30) (cid:31)(cid:20)(cid:26)(cid:14)(cid:15)(cid:14) (cid:20)!"(cid:11)(cid:27)(cid:14)(cid:20)(cid:26)#(cid:13)$(cid:14)%(cid:13)(cid:11)&"(cid:22)(cid:13)(cid:14)’(cid:11)(cid:28)(cid:14) (cid:11)(cid:22)(cid:28)((cid:14))"&(cid:14)’"!&(cid:14))(cid:13)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)*(cid:20)&(cid:24)(cid:20)(cid:26)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:24)(cid:11)&(cid:21)(cid:24)(cid:13)#(cid:14)(cid:11)(cid:22)(cid:13)(cid:11)(cid:30) (cid:17)(cid:30) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)!(cid:14)(cid:2)(cid:14)(cid:11)(cid:26)#(cid:14)+(cid:15)(cid:14)#(cid:23)(cid:14)(cid:26)(cid:23)&(cid:14)(cid:20)(cid:26)(cid:21)(cid:27)"#(cid:13)(cid:14)’(cid:23)(cid:27)#(cid:14)%(cid:27)(cid:11)!(cid:24)(cid:14)(cid:23)(cid:22)(cid:14)(cid:10)(cid:22)(cid:23)&(cid:22)"!(cid:20)(cid:23)(cid:26)!(cid:30)(cid:14)(cid:19)(cid:23)(cid:27)#(cid:14)%(cid:27)(cid:11)!(cid:24)(cid:14)(cid:23)(cid:22)(cid:14)(cid:10)(cid:22)(cid:23)&(cid:22)"!(cid:20)(cid:23)(cid:26)!(cid:14)!(cid:24)(cid:11)(cid:27)(cid:27)(cid:14)(cid:26)(cid:23)&(cid:14)(cid:13)$(cid:21)(cid:13)(cid:13)#(cid:14)(cid:4)(cid:30)(cid:15),(cid:14)’’(cid:14)(cid:10)(cid:13)(cid:22)(cid:14)!(cid:20)#(cid:13)(cid:30) -(cid:30) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:20)(cid:26)(cid:12)(cid:14)(cid:11)(cid:26)#(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:20)(cid:26)(cid:12)(cid:14)(cid:10)(cid:13)(cid:22)(cid:14)(cid:7)(cid:3)(cid:19)+(cid:14).(cid:15)(cid:5)(cid:30),(cid:19)(cid:30) /(cid:3)01 /(cid:11)!(cid:20)(cid:21)(cid:14)(cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:30)(cid:14)(cid:25)(cid:24)(cid:13)(cid:23)(cid:22)(cid:13)&(cid:20)(cid:21)(cid:11)(cid:27)(cid:27)(cid:28)(cid:14)(cid:13)$(cid:11)(cid:21)&(cid:14) (cid:11)(cid:27)"(cid:13)(cid:14)!(cid:24)(cid:23)*(cid:26)(cid:14)*(cid:20)&(cid:24)(cid:23)"&(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:13)!(cid:30) (cid:8)+21 (cid:8)(cid:13)%(cid:13)(cid:22)(cid:13)(cid:26)(cid:21)(cid:13)(cid:14)(cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)((cid:14)"!"(cid:11)(cid:27)(cid:27)(cid:28)(cid:14)*(cid:20)&(cid:24)(cid:23)"&(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:13)((cid:14)%(cid:23)(cid:22)(cid:14)(cid:20)(cid:26)%(cid:23)(cid:22)’(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:10)"(cid:22)(cid:10)(cid:23)!(cid:13)!(cid:14)(cid:23)(cid:26)(cid:27)(cid:28)(cid:30) (cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:25)(cid:13)(cid:21)(cid:24)(cid:26)(cid:23)(cid:27)(cid:23)(cid:12)(cid:28)(cid:2)(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)0(cid:4)(cid:5)(cid:9)(cid:4)(cid:16)(cid:16)/ DS22242A-page 74  2010 Microchip Technology Inc.

MCP433X/435X Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2010 Microchip Technology Inc. DS22242A-page 75

MCP433X/435X NOTES: DS22242A-page 76  2010 Microchip Technology Inc.

MCP433X/435X APPENDIX A: REVISION HISTORY Revision A (March 2010) • Original Release of this Document. Note: Original TSSOP-20 device samples used the example marking shown in Figure A-1. Future device samples will usE the part marking shown in Section 10. Figure A-1: Old example TSSOP-20 device marking. Example MCP4351 EST^e^3256 1004  2010 Microchip Technology Inc. DS22242A-page 77

MCP433X/435X NOTES: DS22242A-page 78  2010 Microchip Technology Inc.

MCP433X/435X APPENDIX B: CHARACTERIZATION B.1 Low-Voltage Operation DATA ANALYSIS This appendix gives an overview of CMOS semiconductor characteristics at lower voltages. This is Some designers may desire to understand the device important so that the 1.8V resistor network operational characteristics outside of the specified characterization graphs of the MCP433X/435X devices operating conditions of the device. can be better understood. Applications where the knowledge of the resistor For this discussion, we will use the 5k device data. network characteristics could be useful include battery This data was chosen since the variations of wiper powered devices and applications that experience resistance has much greater implications for devices brown-out conditions. with smaller R resistances. AB In battery applications the application voltage decays FigureB-1 shows the worst case R error from the over time until new batteries are installed. As the BW average R as a percentage, while FigureB-2 shows voltage decays, the system will continue to operate. At BW the R resistance verse wiper code graph. Nonlinear some voltage level, the application will be below its BW behavior occurs at approximately wiper code 160. This specified operating voltage range. This is dependent is better shown in FigureB-2, where the R on the individual components used in the design. It is BW resistance changes from a linear slope. This change is still useful to understand the device characteristics to due to the change in the wiper resistance. expect when this low-voltage range is encountered. Unlike a microcontroller which can use an external supervisor device to force the controller into the Reset 2.00% state, a digital potentiometer’s resistance characteristic 1.00% is not specified. But understanding the operational 0.00% characteristics can be important in the design of the -1.00% applications circuit for this low-voltage condition. %-2.00% or Other application system scenarios where understand- Err-3.00% ing the low-voltage characteristics of the resistor net- -4.00% -40C work could be important is for system brown out -5.00% +25C +85C conditions. -6.00% +125C -7.00% For the MCP433X/435X devices, the analog operation 0 32 64 96 128 160 192 224 256 is specified at a minimum of 2.7V. Device testing has Wiper Code Terminal A connected to the device V (for DD potentiometer configuration only) and Terminal B FIGURE B-1: 1.8V Worst Case RBW Error connected to VSS. from Average RBW (RBW0-RBW3) vs. Wiper Code and Temperature (V = 1.8V, I = 190 µA). DD W 7000 6000 5000 (cid:2)) e (4000 c n a st3000 si Re2000 -40C +25C 1000 +85C +125C 0 0 32 64 96 128 160 192 224 256 Wiper Code FIGURE B-2: R vs. Wiper Code And BW Temperature (V = 1.8V, I = 190µA). DD W  2010 Microchip Technology Inc. DS22242A-page 79

MCP433X/435X FigureB-3 and FigureB-4 show the wiper resistance The method in which the data was collected is for V voltages of 5.5, 3.0, 1.8 Volts. These graphs important to understand. FigureB-5 shows the DD show that as the resistor ladder wiper node voltage technique that was used to measure the R and R BW W (V ) approaches the V /2 voltage, the wiper resistance. In this technique Terminal A is floating and WCn DD resistance increases. These graphs also show the Terminal B is connected to ground. A fixed current is different resistance characteristics of the NMOS and then forced into the wiper (I ) and the corresponding W PMOS transistors that make up the wiper switch. This wiper voltage (V ) is measured. Forcing a known W is demonstrated by the wiper code resistance curve, current through R (I ) and then measuring the BW W which does not mirror itself around the mid-scale code voltage difference between the wiper (V ) and W (wiper code = 128). Terminal A (V ), the wiper resistance (R ) can be A W calculated, see FigureB-5. Changes in I current will So why is the R graphs showing the maximum W W change the wiper voltage (V ). This may effect the resistance at about mid-scale (wiper code = 128) and W device’s wiper resistance (R ). the R graphs showing the issue at code 160? W BW This requires understanding low-voltage transistor floating characteristics as well as how the data was measured. V A A V W 220 W 200 -40C @ 3.0V +25C @ 3.0V +85C @ 3.0V +125C @ 3.0V -40C @5.5V +25C @ 5.5V +85C @ 5.5V +125C @ 5.5V 180 I (cid:2))160 W RBW = VW/IW nce (112400 B VB RW = (VW-VA)/IW a sist100 Re 80 FIGURE B-5: R and R Measurement. BW W 60 40 FigureB-6 shows a block diagram of the resistor 20 network where the R resistor is a series of 256 R AB S 0 64 128 192 256 resistors. These resistors are polysilicon devices. Each Wiper Code wiper switch is an analog switch made up of an NMOS and PMOS transistor. A more detailed figure of the FIGURE B-3: Wiper Resistance (R ) vs. W wiper switch is shown in FigureB-7. The wiper Wiper Code and Temperature resistance is influenced by the voltage on the wiper (V = 5.5V, I = 900 UA; V = 3.0V, DD W DD switches nodes (V , V and V ). Temperature also G W WCn IW = 480 µA). influences the characteristics of the wiper switch, see FigureB-4. The NMOS transistor and PMOS transistor have 2020 -40C @ 1.8V different characteristics. These characteristics as well +25C @ 1.8V as the wiper switch node voltages determine the R +85C @ 1.8V W (cid:2))1520 +125C @ 1.8V resistance at each wiper code. The variation of each e ( wiper switch’s characteristics in the resistor network is c n sta1020 greater then the variation of the RS resistors. si Re The voltage on the resistor network node (VWCn) is 520 dependent upon the wiper code selected and the voltages applied to V , V and V . The wiper switch V A B W G 20 voltage to V or V voltage determines how strongly W WCn 0 64 128 192 256 the transistor is turned on. When the transistor is Wiper Code weakly turned on the wiper resistance R will be high. W FIGURE B-4: Wiper Resistance (R ) vs. When the transistor is strongly turned on, the wiper W resistance (R ) will be in the typical range. Wiper Code and Temperature W (V = 1.8V, I = 260 µA). DD W DS22242A-page 80  2010 Microchip Technology Inc.

MCP433X/435X So looking at the wiper voltage (V ) for the W A 3.0Vand1.8V data gives the graphs in FigureB-8 and VA FigureB-9. In the 1.8V graph, as the VW approaches 0.8V, the voltage increases nonlinearly. Since V=I*R, and the current (I ) is constant, it means that the W N n device resistance increased nonlinearly at around R RW (1) wiper code 160. S N n-1 DV 1.2 RS RW (1) G 1.0 Nn-2 VWC(n-2) NPMMOOSS e (V) 0.8 RABRS oltag 0.6 Nn-3 RW (1) er V 0.4 -40C W Wip +25C V 0.2 W +85C +125C 0.0 N 1 R (1) 0 32 64 96 128 160 192 224 256 RS W Wiper Code FIGURE B-8: Wiper Voltage (V ) vs. N W 0 R (1) Wiper Code (VDD = 3.0V, IW = 190 µA). W V 1.4 B B 1.2 Note1: The wiper resistance is dependent on V)1.0 sdaeenvdvei cWrea) l, V afDanDcd,t otTeresmr mpieninrcaalutlu drvieno.gl t,a gwesip e(or n cAo,d eB, Voltage (00..68 FIGURE B-6: Resistor Network Block Wiper 0.4 -+4205CC Diagram. 0.2 +85C +125C 0.0 The characteristics of the wiper is determined by the 0 32 64 96 128 160 192 224 256 characteristics of the wiper switch at each of the Wiper Code resistor networks tap points. FigureB-7 shows an example of a wiper switch. As the device operational FIGURE B-9: Wiper Voltage (V ) vs. W voltage becomes lower, the characteristics of the wiper Wiper Code (V = 1.8V, I = 190 µA). DD W switch change due to a lower voltage on the V signal. G FigureB-7 shows an implementation of a wiper switch. When the transistor is turned off, the switch resistance is in the Giga s. When the transistor is turned on, the switch resistance is dependent on the V , V and G W V voltages. This resistance is referred to as R . WCn W R (1) W V (V /V ) G DD SS “gate” NMOS NWC Wiper VWCn PMOS VW “gate” Note1: Wiper Resistance (R ) depends on the W voltages at the wiper switch nodes (V , V and V ). G W WCn FIGURE B-7: Wiper Switch.  2010 Microchip Technology Inc. DS22242A-page 81

MCP433X/435X Using the simulation models of the NMOS and PMOS devices for the MCP43XX analog switch (FigureB-10), 7.00E+09 160 we plot the device resistance when the devices are RNMOS trVsdvrueeioeImrsNslvntii apssievcglttodyeaael snntt ah cco(geeenRfoe s .pW r bia so Fer= ftaii cgh nltRoluehcemNrr elee M reaNeNBOsssMM -Sei1s vOdO1|te|a. S SrRnTya chP aneaeMndl ad odO wr n gSFiP p)ePti.gheM MeuBr(O r GOerNeeSlSioMsgB wi adsO-1 tedatS2hven ieacvcs seine)tch.hsd e (or RsPeIawn,sWsM h )Otttto hhhh liSdeeees MOS and PMOS Resistance ((cid:2))123456......000000000000EEEEEE++++++000000999999 RPMOS PTRhMeWOs Sh olNTdhMeOsSho ld 24681110000024000 Wiper Resistance ((cid:2)) transistors active region, the resistance is much lower. N For these graphs, the resistances are on different 0.00E+00 0 0.0 0.6 1.2 1.8 2.4 3.0 scales. FigureB-13 and FigureB-14 only plots the VIN Voltage NMOS and PMOS device resistance for their active region and the resulting wiper resistance. For these FIGURE B-12: NMOS and PMOS graphs, all resistances are on the same scale. Transistor Resistance (RNMOS, RPMOS) and Wiper Resistance (R ) VS. V W IN (V = 1.8V). R DD W V (V /V ) G DD SS “gate” 300 NMOS VIN VOUT 250 PMOS 200 “gate” e ((cid:2)) RNMOS RPMOS c 150 n a FIGURE B-10: Analog Switch. esist 100 R RW 50 3.00E+10 2500 RW RNMOS 0 e 2.50E+10 0.0 0.6 1.2 1.8 2.4 3.0 c 2000 PMOS Resistan((cid:2))12..5000EE++1100 RPMOS 11050000 Resistance ((cid:2)) WFTrIaGipnUesrRi sREtoe rBs Ri-s1eta3sn:isctea n(RcNe M()VR IVNO NVSSoMl.t a OaVgSen,d R PPMMOOSS) and S and 1.00E+10 PMOS NMOS 500 Wiper (VDD = 3.0V). W IN O 5.00E+09 Theshold NM Theshold 0.00E+00 0 5000 0.0 0.3 0.6 0.9 1.2 1.5 1.8 4500 VIN Voltage 4000 FIGURE B-11: NMOS and PMOS 3500 Transistor Resistance (R , R ) and (cid:2))3000 Wiper Resistance (RW) VNSM. OVSIN PMOS ance (2500 RNMOS RPMOS (VDD = 3.0V). Resist12500000 RW 1000 500 0 0.0 0.3 0.6 0.9 1.2 1.5 1.8 VIN Voltage FIGURE B-14: NMOS and PMOS Transistor Resistance (R , R ) and NMOS PMOS Wiper Resistance (R ) VS. V W IN (V = 1.8V). DD DS22242A-page 82  2010 Microchip Technology Inc.

MCP433X/435X B.2 Optimizing Circuit Design for Low- Voltage Characteristics R1 The low-voltage nonlinear characteristics can be V A minimized by application design. The section will show A V W two application circuits that can be used to control a W programmable reference voltage (VOUT). VOUT Minimizing the low-voltage nonlinear characteristics is done by keeping the voltages on the wiper switch B nodes at a voltage where either the NMOS or PMOS V B transistor is turned on. R2 An example of this is if we are using a digital potentiom- eter for a voltage reference (V ). Lets say that we OUT want V to range from 0.5 * V to 0.6 * V . FIGURE B-15: Example Implementation #1. OUT DD DD In example implementation #1 (FigureB-15) we TABLE B-1: EXAMPLE #1 VOLTAGE window the digital potentiometer using resistors R1 and CALCULATIONS R2. When the wiper code is at full scale the V OUT voltage will be  0.6 * VDD, and when the wiper code is Variation at zero scale the V voltage will be  0.5 * V . OUT DD Remember that the digital potentiometers R variation Min Typ Max AB must be included. TableB-1 shows that the VOUT volt- R1 12,000 12,000 12,000 age can be selected to be between 0.455 * V and DD R2 20,000 20,000 20,000 0.727 * V , which includes the desired range. With DD respect to the voltages on the resistor network node, at RAB 8,000 10,000 12,000 1.8V the VA voltage would range from 1.29V to 1.31V VOUT (@ FS) 0.714 VDD 0.70 VDD 0.727 VDD while the V voltage would range from 0.82V to 0.86V. B V (@ ZS) 0.476 V 0.50 V 0.455 V OUT DD DD DD These voltages cause the wiper resistance to be in the V 0.714 V 0.70 V 0.727 V nonlinear region (seeFigureB-12).In Potentiometer A DD DD DD mode, the variation of the wiper resistance is typically VB 0.476 VDD 0.50 VDD 0.455 VDD not an issue, as shown by the INL/DNL graph Legend: FS – Full Scale, ZS – Zero Scale (Figure2-7). In example implementation #2 (FigureB-16) we use the digital potentiometer in Rheostat mode. The resis- tor ladder uses resistors R1 and R2 with R at the BW bottom of the ladder. When the wiper code is at full scale, the V voltage will be  0.6 * V and when OUT DD the wiper code is at full scale the V voltage will be OUT  0.5 * V . Remember that the digital potentiometers DD R variation must be included. TableB-2 shows that AB the V voltage can be selected to be between 0.50 * OUT V and 0.687 * V , which includes the desired DD DD range. With respect to the voltages on the resistor net- work node, at 1.8V the V voltage would range from W 0.29V to 0.38V. These voltages cause the wiper resistance to be in the linear region (see FigureB-12).  2010 Microchip Technology Inc. DS22242A-page 83

MCP433X/435X R1 V OUT R2 V A A W V W B V B FIGURE B-16: Example Implementation #2. TABLE B-2: EXAMPLE #2 VOLTAGE CALCULATIONS Variation Min Typ Max R1 10,000 10,000 10,000 R2 10,000 10,000 10,000 R (max) 8,000 10,000 12,000 BW V (@ FS) 0.667 V 0.643 V 0.687 V OUT DD DD DD V (@ ZS) 0.50 V 0.50 V 0.50 V OUT DD DD DD V (@ FS) 0.333 V 0.286 V 0.375 V W DD DD DD V (@ ZS) V V V W SS SS SS Legend: FS – Full Scale, ZS – Zero Scale DS22242A-page 84  2010 Microchip Technology Inc.

MCP433X/435X PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. -XXX X /XX Examples: a) MCP4331-502E/XX: 5k 20-LD Device Device Resistance Temperature Package b) MCP4331T-502E/XX: T/R, 5k20-LD Device Version Range c) MCP4331-103E/XX: 10k, 20-LD Device d) MCP4331T-103E/XX: T/R, 10k, 20-LD Device e) MCP4331-503E/XX: 50k, 20-LD Device Device: MCP4331: Quad Volatile 7-bit Potentiometer f) MCP4331T-503E/XX: T/R, 50k, 20-LD Device MCP4331T: Quad Volatile 7-bit Potentiometer g) MCP4331-104E/XX: 100k, 20-LD Device (Tape and Reel) h) MCP4331T-104E/XX: T/R, 100k, MCP4332: Quad Volatile 7-bit Rheostat 20-LD Device MCP4332T: Quad Volatile 7-bit Rheostat a) MCP4332-502E/XX: 5k 14-LD Device (Tape and Reel) MCP4351: Quad Volatile 8-bit Potentiometer b) MCP4332T-502E/XX: T/R, 5k14-LD Device MCP4351T: Quad Volatile 8-bit Potentiometer c) MCP4332-103E/XX: 10k, 14-LD Device (Tape and Reel) d) MCP4332T-103E/XX: T/R, 10k, 14-LD Device MCP4352: Quad Volatile 8-bit Rheostat e) MCP4332-503E/XX: 50k, 8LD Device MCP4352T: Quad Volatile 8-bit Rheostat f) MCP4332T-503E/XX: T/R, 50k, 14-LD Device (Tape and Reel) g) MCP4332-104E/XX: 100k, 14-LD Device h) MCP4332T-104E/XX: T/R, 100k, 14-LD Device Resistance 502 = 5k a) MCP4351-502E/XX: 5k 20-LD Device Version: 103 = 10k b) MCP4351T-502E/XX: T/R, 5k20-LD Device 503 = 50k c) MCP4351-103E/XX: 10k, 20-LD Device 104 = 100k d) MCP4351T-103E/XX: T/R, 10k, 20-LD Device e) MCP4351-503E/XX: 50k, 20-LD Device f) MCP4351T-503E/XX: T/R, 50k, 20-LD Device Temperature E = -40C to +125C (Extended) g) MCP4351-104E/XX: 100k, 20-LD Device Range: h) MCP4351T-104E/XX: T/R, 100k, 20-LD Device Package: ST = Plastic Thin Shrink Small Outline (TSSOP), a) MCP4352-502E/XX: 5k 14-LD Device 14/20-lead b) MCP4352T-502E/XX: T/R, 5k14-LD Device ML = Plastic Quad Flat No-lead (4x4 QFN), 20-lead c) MCP4352-103E/XX: 10k, 14-LD Device d) MCP4352T-103E/XX: T/R, 10k, 14-LD Device e) MCP4352-503E/XX: 50k, 14-LD Device f) MCP4352T-503E/XX: T/R, 50k, 14-LD Device g) MCP4352-104E/XX: 100k, 14-LD Device h) MCP4352T-104E/XX: T/R, 100k, 14-LD Device XX = ST for 14/20-lead TSSOP = ML for 20-lead QFN  2010 Microchip Technology Inc. DS22242A-page 85

MCP433X/435X NOTES: DS22242A-page 86  2010 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. PIC32 logo, rfPIC and UNI/O are registered trademarks of MICROCHIP MAKES NO REPRESENTATIONS OR Microchip Technology Incorporated in the U.S.A. and other WARRANTIES OF ANY KIND WHETHER EXPRESS OR countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MXDEV, MXLAB, SEEVAL and The Embedded Control QUALITY, PERFORMANCE, MERCHANTABILITY OR Solutions Company are registered trademarks of Microchip FITNESS FOR PURPOSE. Microchip disclaims all liability Technology Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, CodeGuard, devices in life support and/or safety applications is entirely at dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, the buyer’s risk, and the buyer agrees to defend, indemnify and ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial hold harmless Microchip from any and all damages, claims, Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified suits, or expenses resulting from such use. No licenses are logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code conveyed, implicitly or otherwise, under any Microchip Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, intellectual property rights. PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2010, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-60932-061-4 Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2010 Microchip Technology Inc. DS22242A-page 87

WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office Asia Pacific Office India - Bangalore Austria - Wels 2355 West Chandler Blvd. Suites 3707-14, 37th Floor Tel: 91-80-3090-4444 Tel: 43-7242-2244-39 Chandler, AZ 85224-6199 Tower 6, The Gateway Fax: 91-80-3090-4123 Fax: 43-7242-2244-393 Tel: 480-792-7200 Harbour City, Kowloon India - New Delhi Denmark - Copenhagen Fax: 480-792-7277 Hong Kong Tel: 91-11-4160-8631 Tel: 45-4450-2828 Technical Support: Tel: 852-2401-1200 Fax: 91-11-4160-8632 Fax: 45-4485-2829 http://support.microchip.com Web Address: Fax: 852-2401-3431 India - Pune France - Paris www.microchip.com Australia - Sydney Tel: 91-20-2566-1512 Tel: 33-1-69-53-63-20 Tel: 61-2-9868-6733 Fax: 91-20-2566-1513 Fax: 33-1-69-30-90-79 ADtullaunthta, GA Fax: 61-2-9868-6755 Japan - Yokohama Germany - Munich Tel: 678-957-9614 China - Beijing Tel: 81-45-471- 6166 Tel: 49-89-627-144-0 Tel: 86-10-8528-2100 Fax: 49-89-627-144-44 Fax: 678-957-1455 Fax: 81-45-471-6122 Fax: 86-10-8528-2104 Italy - Milan Boston Korea - Daegu Westborough, MA China - Chengdu Tel: 82-53-744-4301 Tel: 39-0331-742611 Tel: 774-760-0087 Tel: 86-28-8665-5511 Fax: 82-53-744-4302 Fax: 39-0331-466781 Fax: 774-760-0088 Fax: 86-28-8665-7889 Korea - Seoul Netherlands - Drunen Chicago China - Chongqing Tel: 82-2-554-7200 Tel: 31-416-690399 Itasca, IL Tel: 86-23-8980-9588 Fax: 82-2-558-5932 or Fax: 31-416-690340 Tel: 630-285-0071 Fax: 86-23-8980-9500 82-2-558-5934 Spain - Madrid Fax: 630-285-0075 China - Hong Kong SAR Malaysia - Kuala Lumpur Tel: 34-91-708-08-90 Cleveland Tel: 852-2401-1200 Tel: 60-3-6201-9857 Fax: 34-91-708-08-91 Independence, OH Fax: 852-2401-3431 Fax: 60-3-6201-9859 UK - Wokingham Tel: 216-447-0464 China - Nanjing Malaysia - Penang Tel: 44-118-921-5869 Fax: 216-447-0643 Tel: 86-25-8473-2460 Tel: 60-4-227-8870 Fax: 44-118-921-5820 Dallas Fax: 86-25-8473-2470 Fax: 60-4-227-4068 Addison, TX China - Qingdao Philippines - Manila Tel: 972-818-7423 Tel: 86-532-8502-7355 Tel: 63-2-634-9065 Fax: 972-818-2924 Fax: 86-532-8502-7205 Fax: 63-2-634-9069 Detroit China - Shanghai Singapore Farmington Hills, MI Tel: 86-21-5407-5533 Tel: 65-6334-8870 Tel: 248-538-2250 Fax: 86-21-5407-5066 Fax: 65-6334-8850 Fax: 248-538-2260 China - Shenyang Taiwan - Hsin Chu Kokomo Tel: 86-24-2334-2829 Tel: 886-3-6578-300 Kokomo, IN Fax: 86-24-2334-2393 Fax: 886-3-6578-370 Tel: 765-864-8360 Fax: 765-864-8387 China - Shenzhen Taiwan - Kaohsiung Tel: 86-755-8203-2660 Tel: 886-7-536-4818 Los Angeles Fax: 86-755-8203-1760 Fax: 886-7-536-4803 Mission Viejo, CA Tel: 949-462-9523 China - Wuhan Taiwan - Taipei Tel: 86-27-5980-5300 Tel: 886-2-2500-6610 Fax: 949-462-9608 Fax: 86-27-5980-5118 Fax: 886-2-2508-0102 Santa Clara China - Xian Thailand - Bangkok Santa Clara, CA Tel: 408-961-6444 Tel: 86-29-8833-7252 Tel: 66-2-694-1351 Fax: 408-961-6445 Fax: 86-29-8833-7256 Fax: 66-2-694-1350 China - Xiamen Toronto Mississauga, Ontario, Tel: 86-592-2388138 Canada Fax: 86-592-2388130 Tel: 905-673-0699 China - Zhuhai Fax: 905-673-6509 Tel: 86-756-3210040 Fax: 86-756-3210049 01/05/10 DS22242A-page 88  2010 Microchip Technology Inc.

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: MCP4331-103E/ML MCP4331-103E/ST MCP4331-104E/ML MCP4331-104E/ST MCP4331-502E/ML MCP4331- 502E/ST MCP4331-503E/ML MCP4331-503E/ST MCP4331T-103E/ML MCP4331T-103E/ST MCP4331T-104E/ML MCP4331T-104E/ST MCP4331T-502E/ML MCP4331T-502E/ST MCP4331T-503E/ML MCP4331T-503E/ST MCP4351-103E/ML MCP4351-103E/ST MCP4351-104E/ML MCP4351-104E/ST MCP4351-502E/ML MCP4351- 502E/ST MCP4351-503E/ML MCP4351-503E/ST MCP4351T-103E/ML MCP4351T-103E/ST MCP4351T-104E/ML MCP4351T-104E/ST MCP4351T-502E/ML MCP4351T-502E/ST MCP4351T-503E/ML MCP4351T-503E/ST MCP4332-103E/ST MCP4332-104E/ST MCP4332-502E/ST MCP4332-503E/ST MCP4332T-103E/ST MCP4332T- 104E/ST MCP4332T-502E/ST MCP4332T-503E/ST MCP4352-103E/ST MCP4352-104E/ST MCP4352-502E/ST MCP4352-503E/ST MCP4352T-103E/ST MCP4352T-104E/ST MCP4352T-502E/ST MCP4352T-503E/ST