M MCP41XXX/42XXX ™ Single/Dual Digital Potentiometer with SPI Interface Features Description • 256 taps for each potentiometer The MCP41XXX and MCP42XXX devices are 256- • Potentiometer values for 10kΩ, 50kΩ and position, digital potentiometers available in 10kΩ, 100kΩ 50kΩ and 100kΩ resistance versions. The MCP41XXX is a single-channel device and is offered in • Single and dual versions an 8-pin PDIP or SOIC package. The MCP42XXX con- • SPI™ serial interface (mode 0,0 and 1,1) tains two independent channels in a 14-pin PDIP, SOIC • ±1LSB max INL & DNL or TSSOP package. The wiper position of the • Low power CMOS technology MCP41XXX/42XXX varies linearly and is controlled via • 1µA maximum supply current in static operation an industry-standard SPI interface. The devices con- sume <1µA during static operation. A software shut- • Multiple devices can be daisy-chained together down feature is provided that disconnects the “A” (MCP42XXX only) terminal from the resistor stack and simultaneously con- • Shutdown feature open circuits of all resistors for nects the wiper to the “B” terminal. In addition, the dual maximum power savings MCP42XXX has a SHDN pin that performs the same • Hardware shutdown pin available on MCP42XXX function in hardware. During shutdown mode, the con- only tents of the wiper register can be changed and the • Single supply operation (2.7V - 5.5V) potentiometer returns from shutdown to the new value. • Industrial temperature range: -40°C to +85°C The wiper is reset to the mid-scale position (80h) upon • Extended temperature range: -40°C to +125°C power-up. The RS (reset) pin implements a hardware reset and also returns the wiper to mid-scale. The Block Diagram MCP42XXX SPI interface includes both the SI and SO pins, allowing daisy-chaining of multiple devices. Chan- RS SHDN nel-to-channel resistance matching on the MCP42XXX varies by less than 1%. These devices operate from a V DD single 2.7 - 5.5V supply and are specified over the V PB0 SS extended and industrial temperature ranges. Wiper Resistor C Loongtricol Register Array 0 Package Types PA0 PW0 PDIP/SOIC PB1 CS 16-Bit Wiper Resistor PA1 CS 1 M 8 VDD SI Shift Register Array 1* PW1 SCK 2 CP 7 PB0 Register SI 3 41 6 PW0 SCK X V 4 X 5 PA0 S0 SS X *Potentiometer P1 is only available on the dual PDIP/SOIC/TSSOP MCP42XXX version. CS 1 14 V DD SCK 2 13 SO M SI 3 C 12 SHDN P V 4 4 11 RS SS 2 X PB1 5 10 PB0 X X PW1 6 9 PW0 PA1 7 8 PA0  2003 Microchip Technology Inc. DS11195C-page 1

MCP41XXX/42XXX 1.0 ELECTRICAL CHARACTERISTICS DC CHARACTERISTICS: 10 kΩ VERSION Electrical Characteristics: Unless otherwise indicated, VDD = +2.7V to 5.5V, TA = -40°C to +85°C (TSSOP devices are only specified at +25°C and +85°C). Typical specifications represent values for VDD = 5V, VSS = 0V, VB = 0V, TA = +25°C. Parameters Sym Min Typ Max Units Conditions Rheostat Mode Nominal Resistance R 8 10 12 kΩ TA = +25°C (Note1) Rheostat Differential Non Linearity R-DNL -1 ±1/4 +1 LSB Note2 Rheostat Integral Non Linearity R-INL -1 ±1/4 +1 LSB Note2 Rheostat Tempco ∆RAB/∆T — 800 — ppm/°C Wiper Resistance RW — 52 100 Ω VDD = 5.5V, IW = 1mA, code 00h RW — 73 125 Ω VDD = 2.7V, IW = 1mA, code 00h Wiper Current IW -1 — +1 mA Nominal Resistance Match ∆R/R — 0.2 1 % MCP42010 only, P0 to P1; TA = +25°C Potentiometer Divider Resolution N 8 — — Bits Monotonicity N 8 — — Bits Differential Non-Linearity DNL -1 ±1/4 +1 LSB Note3 Integral Non-Linearity INL -1 ±1/4 +1 LSB Note3 Voltage Divider Tempco ∆VW/∆T — 1 — ppm/°C Code 80h Full Scale Error VWFSE -2 -0.7 0 LSB Code FFh, VDD = 5V, see Figure2-25 VWFSE -2 -0.7 0 LSB Code FFh, VDD = 3V, see Figure2-25 Zero Scale Error VWZSE 0 +0.7 +2 LSB Code 00h, VDD = 5V, see Figure2-25 VWZSE 0 +0.7 +2 LSB Code 00h, VDD = 3V, see Figure2-25 Resistor Terminals Voltage Range VA,B,W 0 — VDD Note4 Capacitance (CA or CB) — 15 — pF f = 1MHz, Code = 80h, see Figure2-30 Capacitance C — 5.6 — pF f = 1MHz, Code = 80h, see Figure2-30 W Dynamic Characteristics (All dynamic characteristics use VDD = 5V) Bandwidth -3dB BW — 1 — MHz VB = 0V, Measured at Code 80h, Output Load = 30PF Settling Time tS — 2 — µS VA = VDD,VB = 0V, ±1% Error Band, Transition from Code 00h to Code 80h, Output Load = 30pF Resistor Noise Voltage eNWB — 9 — nV/√Hz VA = Open, Code 80h, f =1kHz Crosstalk CT — -95 — dB VA = VDD, VB = 0V (Note5) Digital Inputs/Outputs (CS, SCK, SI, SO) See Figure2-12 for RS and SHDN pin operation Schmitt Trigger High-Level Input Voltage VIH 0.7VDD — — V Schmitt Trigger Low-Level Input Voltage VIL — — 0.3VDD V Hysteresis of Schmitt Trigger Inputs VHYS — 0.05VDD — Low-Level Output Voltage VOL — — 0.40 V IOL = 2.1mA, VDD = 5V High-Level Output Voltage VOH VDD - 0.5 — — V IOH = -400µA, VDD = 5V Input Leakage Current ILI -1 — +1 µA CS = VDD, VIN = VSS or VDD, includes VA SHDN=0 Pin Capacitance (All inputs/outputs) CIN, COUT — 10 — pF VDD = 5.0V, TA = +25°C, fc = 1MHz Power Requirements Operating Voltage Range VDD 2.7 — 5.5 V Supply Current, Active IDDA — 340 500 µA VDD = 5.5V, CS = VSS, fSCK = 10MHz, SO = Open, Code FFh (Note6) Supply Current, Static IDDS — 0.01 1 µA CS, SHDN, RS = VDD = 5.5V, SO = Open (Note6) Power Supply Sensitivity PSS — 0.0015 0.0035 %/% VDD = 4.5V - 5.5V, VA = 4.5V, Code 80h PSS — 0.0015 0.0035 %/% VDD = 2.7V - 3.3V, VA = 2.7V, Code 80h Note 1: VAB = VDD, no connection on wiper. 2: Rheostat position non-linearity R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from the ideal between successive tap positions. IW = 50µA for VDD = 3V and IW = 400µA for VDD = 5V for 10kΩ version. See Figure2-26 for test circuit. 3: INL and DNL are measured at VW with the device configured in the voltage divider or potentiometer mode. VA = VDD and VB = 0V. DNL specification limits of ±1LSB max are specified monotonic operating conditions. See Figure2-25 for test circuit. 4: Resistor terminals A,B and W have no restrictions on polarity with respect to each other. Full-scale and zero-scale error were measured using Figure2-25. 5: Measured at VW pin where the voltage on the adjacent VW pin is swinging full-scale. 6: Supply current is independent of current through the potentiometers. DS11195C-page 2  2003 Microchip Technology Inc.

MCP41XXX/42XXX DC CHARACTERISTICS: 50 kΩ VERSION Electrical Characteristics: Unless otherwise indicated, VDD = +2.7V to 5.5V, TA = -40°C to +85°C (TSSOP devices are only specified at +25°C and +85°C). Typical specifications represent values for VDD = 5V, VSS = 0V, VB = 0V, TA = +25°C. Parameters Sym Min Typ Max Units Conditions Rheostat Mode Nominal Resistance R 35 50 65 kΩ TA = +25°C (Note1) Rheostat Differential Non-Linearity R-DNL -1 ±1/4 +1 LSB Note2 Rheostat Integral Non-Linearity R-INL -1 ±1/4 +1 LSB Note2 Rheostat Tempco ∆RAB/∆T — 800 — ppm/°C Wiper Resistance RW — 125 175 Ω VDD = 5.5V, IW = 1mA, code 00h RW — 175 250 Ω VDD = 2.7V, IW = 1mA, code 00h Wiper Current IW -1 — +1 mA Nominal Resistance Match ∆R/R — 0.2 1 % MCP42050 only, P0 to P1;TA = +25°C Potentiometer Divider Resolution N 8 — — Bits Monotonicity N 8 — — Bits Differential Non-Linearity DNL -1 ±1/4 +1 LSB Note3 Integral Non-Linearity INL -1 ±1/4 +1 LSB Note3 Voltage Divider Tempco ∆VW/∆T — 1 — ppm/°C Code 80h Full-Scale Error VWFSE -1 -0.25 0 LSB Code FFh, VDD = 5V, see Figure2-25 VWFSE -1 -0.35 0 LSB Code FFh, VDD = 3V, see Figure2-25 Zero-Scale Error VWZSE 0 +0.25 +1 LSB Code 00h, VDD = 5V, see Figure2-25 VWZSE 0 +0.35 +1 LSB Code 00h, VDD = 3V, see Figure2-25 Resistor Terminals Voltage Range VA,B,W 0 — VDD Note4 Capacitance (CA or CB) — 11 — pF f =1MHz, Code = 80h, see Figure2-30 Capacitance CW — 5.6 — pF f =1MHz, Code = 80h, see Figure2-30 Dynamic Characteristics (All dynamic characteristics use VDD = 5V) Bandwidth -3dB BW — 280 — MHz VB = 0V, Measured at Code 80h, Output Load = 30PF Settling Time tS — 8 — µS VA = VDD,VB = 0V, ±1% Error Band, Transition from Code 00h to Code 80h, Output Load = 30pF Resistor Noise Voltage eNWB — 20 — nV/√Hz VA = Open, Code 80h, f =1kHz Crosstalk CT — -95 — dB VA = VDD, VB = 0V (Note5) Digital Inputs/Outputs (CS, SCK, SI, SO) See Figure2-12 for RS and SHDN pin operation. Schmitt Trigger High-Level Input Voltage VIH 0.7VDD — — V Schmitt Trigger Low-Level Input Voltage VIL — — 0.3VDD V Hysteresis of Schmitt Trigger Inputs VHYS — 0.05VDD — Low-Level Output Voltage VOL — — 0.40 V IOL = 2.1mA, VDD = 5V High-Level Output Voltage VOH VDD - 0.5 — — V IOH = -400µA, VDD = 5V Input Leakage Current ILI -1 — +1 µA CS = VDD, VIN = VSS or VDD, includes VA SHDN=0 Pin Capacitance (All inputs/outputs) CIN, COUT — 10 — pF VDD = 5.0V, TA = +25°C, fc = 1MHz Power Requirements Operating Voltage Range VDD 2.7 — 5.5 V Supply Current, Active IDDA — 340 500 µA VDD = 5.5V, CS = VSS, fSCK = 10MHz, SO = Open, Code FFh (Note6) Supply Current, Static IDDS — 0.01 1 µA CS, SHDN, RS = VDD = 5.5V, SO = Open (Note6) Power Supply Sensitivity PSS — 0.0015 0.0035 %/% VDD = 4.5V - 5.5V, VA = 4.5V, Code 80h PSS — 0.0015 0.0035 %/% VDD = 2.7V - 3.3V, VA = 2.7V, Code 80h Note 1: VAB = VDD, no connection on wiper. 2: Rheostat position non-linearity R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from the ideal between successive tap positions. IW = VDD/R for +3V or +5V for 50kΩ version. See Figure2-26 for test circuit. 3: INL and DNL are measured at VW with the device configured in the voltage divider or potentiometer mode. VA = VDD and VB = 0V. DNL specification limits of ±1LSB max are specified monotonic operating conditions. See Figure2-25 for test circuit. 4: Resistor terminals A,B and W have no restrictions on polarity with respect to each other. Full-scale and zero-scale error were measured using Figure2-25. 5: Measured at VW pin where the voltage on the adjacent VW pin is swinging full scale. 6: Supply current is independent of current through the potentiometers.  2003 Microchip Technology Inc. DS11195C-page 3

MCP41XXX/42XXX DC CHARACTERISTICS: 100 kΩ VERSION Electrical Characteristics: Unless otherwise indicated, VDD = +2.7V to 5.5V, TA = -40°C to +85°C (TSSOP devices are only specified at +25°C and +85°C). Typical specifications represent values for VDD = 5V, VSS = 0V, VB = 0V, TA = +25°C. Parameters Sym Min Typ Max Units Conditions Rheostat Mode Nominal Resistance R 70 100 130 kΩ TA = +25°C (Note1) Rheostat Differential Non-Linearity R-DNL -1 ±1/4 +1 LSB Note2 Rheostat Integral Non-Linearity R-INL -1 ±1/4 +1 LSB Note2 Rheostat Tempco ∆RAB/∆T — 800 — ppm/°C Wiper Resistance RW — 125 175 Ω VDD = 5.5V, IW = 1mA, code 00h RW — 175 250 Ω VDD = 2.7V, IW = 1mA, code 00h Wiper Current IW -1 — +1 mA Nominal Resistance Match ∆R/R — 0.2 1 % MCP42010 only, P0 to P1;TA = +25°C Potentiometer Divider Resolution N 8 — — Bits Monotonicity N 8 — — Bits Differential Non-Linearity DNL -1 ±1/4 +1 LSB Note3 Integral Non-Linearity INL -1 ±1/4 +1 LSB Note3 Voltage Divider Tempco ∆VW/∆T — 1 — ppm/°C Code 80h Full-Scale Error VWFSE -1 -0.25 0 LSB Code FFh, VDD = 5V, see Figure2-25 VWFSE -1 -0.35 0 LSB Code FFh, VDD = 3V, see Figure2-25 Zero-Scale Error VWZSE 0 +0.25 +1 LSB Code 00h, VDD = 5V, see Figure2-25 VWZSE 0 +0.35 +1 LSB Code 00h, VDD = 3V, see Figure2-25 Resistor Terminals Voltage Range VA,B,W 0 — VDD Note4 Capacitance (CA or CB) — 11 — pF f =1MHz, Code = 80h, see Figure2-30 Capacitance CW — 5.6 — pF f =1MHz, Code = 80h, see Figure2-30 Dynamic Characteristics (All dynamic characteristics use VDD = 5V.) Bandwidth -3dB BW — 145 — MHz VB = 0V, Measured at Code 80h, Output Load = 30PF Settling Time tS — 18 — µS VA = VDD,VB = 0V, ±1% Error Band, Transition from Code 00h to Code 80h, Output Load = 30pF Resistor Noise Voltage eNWB — 29 — nV/√Hz VA = Open, Code 80h, f =1kHz Crosstalk CT — -95 — dB VA = VDD, VB = 0V (Note5) Digital Inputs/Outputs (CS, SCK, SI, SO) See Figure2-12 for RS and SHDN pin operation. Schmitt Trigger High-Level Input Voltage VIH 0.7VDD — — V Schmitt Trigger Low-Level Input Voltage VIL — — 0.3VDD V Hysteresis of Schmitt Trigger Inputs VHYS — 0.05VDD — Low-Level Output Voltage VOL — — 0.40 V IOL = 2.1mA, VDD = 5V High-Level Output Voltage VOH VDD - 0.5 — — V IOH = -400µA, VDD = 5V Input Leakage Current ILI -1 — +1 µA CS = VDD, VIN = VSS or VDD, includes VA SHDN=0 Pin Capacitance (All inputs/outputs) CIN, COUT — 10 — pF VDD = 5.0V, TA = +25°C, fc = 1MHz Power Requirements Operating Voltage Range VDD 2.7 — 5.5 V Supply Current, Active IDDA — 340 500 µA VDD = 5.5V, CS = VSS, fSCK = 10MHz, SO = Open, Code FFh (Note6) Supply Current, Static IDDS — 0.01 1 µA CS, SHDN, RS = VDD = 5.5V, SO = Open (Note6) Power Supply Sensitivity PSS — 0.0015 0.0035 %/% VDD = 4.5V - 5.5V, VA = 4.5V, Code 80h PSS — 0.0015 0.0035 %/% VDD = 2.7V - 3.3V, VA = 2.7V, Code 80h Note 1: VAB = VDD, no connection on wiper. 2: Rheostat position non-linearity R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from the ideal between successive tap positions. IW = 50µA for VDD = 3V and IW = 400µA for VDD = 5V for 10kΩ version. See Figure2-26 for test circuit. 3: INL and DNL are measured at VW with the device configured in the voltage divider or potentiometer mode. VA = VDD and VB = 0V. DNL specification limits of ±1LSB max are specified monotonic operating conditions. See Figure2-25 for test circuit. 4: Resistor terminals A,B and W have no restrictions on polarity with respect to each other. Full-scale and zero-scale error were measured using Figure2-25. 5: Measured at VW pin where the voltage on the adjacent VW pin is swinging full-scale. 6: Supply current is independent of current through the potentiometers. DS11195C-page 4  2003 Microchip Technology Inc.

MCP41XXX/42XXX Absolute Maximum Ratings † V ...................................................................................7.0V † Notice: Stresses above those listed under “maximum rat- DD All inputs and outputs w.r.t. V ...............-0.6V to V +1.0V ings” may cause permanent damage to the device. This is a SS DD stress rating only and functional operation of the device at Storage temperature.....................................-60°C to +150°C those or any other conditions above those indicated in the Ambient temp. with power applied................-60°C to +125°C operational listings of this specification is not implied. Expo- ESD protection on all pins..................................................≥ 2kV sure to maximum rating conditions for extended periods may affect device reliability. AC TIMING CHARACTERISTICS Electrical Characteristics: Unless otherwise indicated, VDD = +2.7V to 5.5V, TA = -40°C to +85°C. Parameter Sym Min. Typ. Max. Units Conditions Clock Frequency FCLK — — 10 MHz VDD = 5V (Note1) Clock High Time tHI 40 — — ns Clock Low Time tLO 40 — — ns CS Fall to First Rising CLK Edge tCSSR 40 — — ns Data Input Setup Time tSU 40 — — ns Data Input Hold Time tHD 10 — — ns SCK Fall to SO Valid Propagation Delay tDO — 80 ns CL = 30pF (Note2) SCK Rise to CS Rise Hold Time tCHS 30 — — ns SCK Rise to CS Fall Delay tCS0 10 — — ns CS Rise to CLK Rise Hold tCS1 100 — — ns CS High Time tCSH 40 — — ns Reset Pulse Width tRS 150 — — ns Note2 RS Rising to CS Falling Delay Time tRSCS 150 — — ns Note2 CS rising to RS or SHDN falling delay time tSE 40 — — ns Note3 CS low time tCSL 100 — — ns Note3 Shutdown Pulse Width tSH 150 — — ns Note3 Note 1: When using the device in the daisy-chain configuration, maximum clock frequency is determined by a combination of propagation delay time (tDO) and data input setup time (tSU). Max. clock frequency is therefore ~ 5.8MHz based on SCK rise and fall times of 5ns, tHI = 40ns, tDO = 80ns and tSU = 40ns. 2: Applies only to the MCP42XXX devices. 3: Applies only when using hardware pins to exit software shutdown mode, MCP42XXX only.  2003 Microchip Technology Inc. DS11195C-page 5

MCP41XXX/42XXX t CSH CS tCSSR 1/FCLK tCHS tCSO tHI tLO tCS1 SCK t SU t HD SI msb in t DO SO (First 16 bits out are always zeros) tS ±1% ±1% Error Band V OUT FIGURE 1-1: Detailed Serial interface Timing. Wiper position is changed to Code 80h is latched mid-scale (80h) if RS is held on rising edge of RS low for 150ns CS t RSCS t RS RS t S ±1% ±1% Error Band V OUT FIGURE 1-2: Reset Timing. t CSL CS t SE t RS RS t SE t SH SHDN FIGURE 1-3: Software Shutdown Exit Timing. DS11195C-page 6  2003 Microchip Technology Inc.

MCP41XXX/42XXX 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, curve represents 10kΩ, 50kΩ and 100kΩ devices, V = 5V, V = 0V, T = +25°C, DD SS A V = 0V. B 1 14 Ωe () 0.8 VDD = +3V to +5V Ωk)12 RAB nc e (10 a c ormalized Resist 000...246 RWB RWA Nominal Resistan 2468 CodReW =B 80h N MCP41010, MCP42010 (10 kΩ potentiometers) 0 0 0 32 64 96 128 160 192 224 256 -40 -25 -10 5 20 35 50 65 80 95 110125 Code (Decimal) Temperature (°C) FIGURE 2-1: Normalized Wiper to End FIGURE 2-4: Nominal Resistance 10kΩ Terminal Resistance vs. Code. vs. Temperature. LSB) 00..45 TRAe f=e r- 4to0 °FCig tuor e+ 825-2°C5 Ω) 6700 Error ( 00..23 nce (k 50 RAB NL 0.1 sta 40 otentiometer I ----0000....43210 Nominal Resi 123000 MCP41050, MCP42050 (50 kΩ potentiometers)C odReW =B 80h P -0.5 0 0 32 64 96 128 160 192 224 256 -40 -25 -10 5 20 35 50 65 80 95 110 125 Code (Decimal) Temperature (°C) FIGURE 2-2: Potentiometer INL Error vs. FIGURE 2-5: Nominal Resistance 50kΩ Code. vs. Temperature. Co 70 TA = -40°C to +85°C 140 mp 60 VA = 3V Ωk) 120 Te 50 e ( 100 RAB otentiometer Mode (ppm / °C) 123400000 Nominal Resistanc 24680000 MCP41100, MCP42100 (100 kΩ potentiometersC)odReW =B 80h P -10 0 0 32 64 96 128 160 192 224 256 -40 -25 -10 5 20 35 50 65 80 95 110 125 Code (Decimal) Temperature (°C) FIGURE 2-3: Potentiometer Mode FIGURE 2-6: Nominal Resistance 100kΩ Tempco vs. Code. vs. Temperature.  2003 Microchip Technology Inc. DS11195C-page 7

MCP41XXX/42XXX Note: Unless otherwise indicated, curve represents 10kΩ, 50kΩ and 100kΩ devices, V = 5V, V = 0V, T = +25°C, DD SS A V = 0V. B 0.5 280 B) 0.4 Refer to Figure 2-27 µA) Error (LS 000...123 TA = +85°C Current ( 128300 VDD = 5V FCCoLdKe = = 3 F MFHhz Rheostat INL ----0000....04321 TA = -40°C TA = +25°C Active Supply 13800 VDD = 3V 30 -0.5 -40 -25 -10 5 20 35 50 65 80 95 110125 0 32 64 96 128 160 192 224 256 Code (Decimal) Temperature (°C) FIGURE 2-7: Rheostat INL Error vs. FIGURE 2-10: Active Supply Current vs. Code. Temperature. 3000 1000 empCo 22050000 TVRAAW =B= m-n4oe0 a°cCsou ntrone ed+c8t5, °C, ent (mA) 789000000 ABCD ---- VVVVDDDDDDDD ==== 5533....5533VVVV,,,, CCCCooooddddeeee ==== AFFAFFAAhhhh B stat Mode T(ppm / °C) 11050000 Supply Curr 345600000000 A C Rheo 500 ctive 200 0 A 100 D 0 32 64 96 128 160 192 224 256 0 1k 10k 100k 1M 10M Code (Decimal) Clock Frequency (Hz) FIGURE 2-8: Rheostat Mode Tempco vs. FIGURE 2-11: Active Supply Current vs. Code. Clock Frequency. 1000 A) 1 VDD = 5.5V m 0 A) nt ( -1 nt (n 100 urre -2 urre k C -3 C n c 10 Si -4 ati N St HD -5 S 1-40 -25 -10 5 20 35 50 65 80 95 11 12 RS & --76 0 5 0 2 4 6 Temperature (°C) RS & SHDN Pin Voltage (V) FIGURE 2-9: Static Current vs. FIGURE 2-12: Reset & Shutdown Pins Temperature. Current vs. Voltage. DS11195C-page 8  2003 Microchip Technology Inc.

MCP41XXX/42XXX Note: Unless otherwise indicated, curve represents 10kΩ, 50kΩ and 100kΩ devices, V = 5V, V = 0V, T = +25°C, DD SS A V = 0V. B 180 MCP41010,MCP42010 C = 27pF s160 Code = 00h, L ce140 Sample Size = 400 urren120 VOUT FFh cc100 O of 80 er 60 00h b m 40 u N 20 CS 0 47 48 49 50 51 52 53 54 55 56 57 58 59 Wiper Resistance (Ω) FIGURE 2-13: 10kΩ Device Wiper FIGURE 2-16: Full-Scale Settling Time. Resistance Histogram. 140 MCP41050, MCP41100, CL = 27pF ces120 MCoCdPe4 2=0 0500h, ,MCP42100 Code = 80h en100 Sample Size = 796 ccurr 80 VOUT O of 60 ber 40 m Nu 20 CS 0 115 117 119 121 123 125 127 129 131 133 Wiper Resistance (Ω) FIGURE 2-14: 50kΩ, 100kΩ Device Wiper FIGURE 2-17: Digital Feed through vs. Resistance Histogram. Time. 6 CL = 17pF 0 Code = FFh Code = 80h -6 Code = 40h -12 Code = 20h -18 VOUT Code = 7Fh Code = 80h dB) -24 Code = 10h Gain ( -30 CCooddee == 0084hh -36 Code = 02h -42 Code = 01h CS -48 -54 CMLC =P 43100p1F0, ,R MefCePr 4to2 0F1ig0u (r1e0 2k-Ω29 potentiometers) -60 100 1k 10k 100k 1M 10M Frequency (Hz) FIGURE 2-15: One Position Settling Time. FIGURE 2-18: Gain vs. Frequency for 10kΩ Potentiometer.  2003 Microchip Technology Inc. DS11195C-page 9

MCP41XXX/42XXX Note: Unless otherwise indicated, curve represents 10kΩ, 50kΩ and 100kΩ devices, V = 5V, V = 0V, T = +25°C, DD SS A V = 0V. B 6 40 -60 CCooddee == F80Fhh 35 10 kΩ Potentiometer VCCDLo Dd= =e 2 4=7. 58pV0Fh ,t ,o 5.5V, -12 Code = 40h 30 VRAe f=e r4 Vto Figure 2-28 Code = 20h Gain (dB) ----33216048 CCCooodddeee === 100084hhh PSRR (dB) 122505 50 kΩ Potentiometer Code = 02h -42 10 100 kΩ Potentiometer -48 Code = 01h -54 CL = 30pF, Refer to Figure 2-29 5 MCP41050, MCP42050 (50kΩ potentiometers) -60100 1k 10k 100k 1M 10M 01k 10k 100k 1M 10M Frequency (Hz) Frequency (Hz) FIGURE 2-19: Gain vs. Frequency for FIGURE 2-22: Power Supply Rejection 50kΩ Potentiometer. Ratio vs. Frequency. 6 700 Code = FFh MCP41010, MCP42010 0 -6 Code = 80h Ω) 600 IRwe f=e r1 tmo AF,i gCuorde e2 -=2 700h, -12 Code = 40h e ( 500 VDD = 2.7V ain (dB) ---321048 CCCooodddeee === 210008hhh Resistanc 340000 G -36 Code = 04h er 200 -42 CCooddee == 0021hh Wip 100 VDD = 5V -48 -54 CL = 30pF, Refer to Figure 2-29 0 MCP41100, MCP42100 (100kΩ potentiometers) -60 0 1 2 3 4 5 100 1k 10k 100k 1M Frequency (Hz) Terminal B Voltage (V) FIGURE 2-20: Gain vs. Frequency for FIGURE 2-23: 10kΩ Wiper Resistance vs. 100kΩ Potentiometer. Voltage. 0 450 Code = 00h 400 Refer to Figure 2-27 -6 Ω) 350 dB) -12 145 k2H7z9 kHz 1.06 MHz stance ( 235000 VDD = 2.7V Gain ( --2148 10 kΩ per Resi 112050000 VDD = 5V 50 kΩ Wi 50 -30 CL = 30 pF, Code = 80h 100 kΩ 0 Refer to Figure 2-29 -36 0 1 2 3 4 5 1k 10k 100k 1M 10M Frequency (Hz) Terminal B Voltage (V) FIGURE 2-21: -3 dB Bandwidths. FIGURE 2-24: 50kΩ & 100kΩ Wiper Resistance vs. Voltage. DS11195C-page 10  2003 Microchip Technology Inc.

MCP41XXX/42XXX 2.1 Parametric Test Circuits V A V+ = V DD 1LSB = V+/256 A V A DD V+ V+ W W B B + DUT - VMEAS* DUT +- VMEAS* *Assume infinite input impedance V+ = V ± 10% DD FIGURE 2-25: Potentiometer Divider Non- ∆V PSRR (dB) = 20LOG( DD ) Linearity Error Test Circuit (DNL, INL). ∆V MEAS PSS (%/%) = ∆V DD ∆V MEAS No Connection *Assume infinite input impedance FIGURE 2-28: Power Supply Sensitivity A IW Test Circuit (PSS, PSRR). W B DUT + A V * - MEAS +5V W VIN ~ + VOUT *Assume infinite input impedance OFFSET DUT - GND B FIGURE 2-26: Resistor Position Non- Linearity Error Test Circuit (Rheostat operation 2.5V DC DNL, INL). Rsw = 0.1V FIGURE 2-29: Gain vs. Frequency Test Isw Circuit. A Code = 00h W DUT B ISW + 0.1V A DUT B - +5V V = 0 to V SS DD V - OUT V ~ + IN MCP601 2.5V DC FIGURE 2-27: Wiper Resistance Test Offset Circuit. FIGURE 2-30: Capacitance Test Circuit.  2003 Microchip Technology Inc. DS11195C-page 11

MCP41XXX/42XXX 3.0 PIN DESCRIPTIONS 3.9 Shutdown (SHDN) (MCP42XXX devices only) 3.1 PA0, PA1 The Shutdown pin has a Schmitt Trigger input. Pulling Potentiometer Terminal A Connection. this pin low will put the device in a power-saving mode where A terminal is opened and the B and W terminals 3.2 PB0, PB1 are connected for all potentiometers. This pin should not be toggled low when the CS pin is low. In order to Potentiometer Terminal B Connection. minimize power consumption, this pin has an active pull-up circuit. The performance of this circuit is shown 3.3 PW0, PW1 in Figure2-12. This pin will draw negligible current at logic level ‘0’ and logic level ‘1’. Do not leave this pin Potentiometer Wiper Connection. floating. 3.4 Chip Select (CS) TABLE 3-1: MCP41XXX Pins This is the SPI port chip select pin and is used to exe- Pin # Name Function cute a new command after it has been loaded into the shift register. This pin has a Schmitt Trigger input. 1 CS Chip Select 2 SCK Serial Clock 3.5 Serial Clock (SCK) 3 SI Serial Data Input This is the SPI port clock pin and is used to clock-in 4 V Ground new register data. Data is clocked into the SI pin on the SS rising edge of the clock and out the SO pin on the falling 5 PA0 Terminal A Connection For Pot 0 edge of the clock. This pin is gated to the CS pin (i.e., 6 PW0 Wiper Connection For Pot 0 the device will not draw any more current if the SCK pin is toggling when the CS pin is high). This pin has a 7 PB0 Terminal B Connection For Pot 0 Schmitt Trigger input. 8 V Power DD 3.6 Serial Data Input (SI) TABLE 3-2: MCP42XXX Pins This is the SPI port serial data input pin. The command Pin # Name Function and data bytes are clocked into the shift register using this pin. This pin is gated to the CS pin (i.e., the device 1 CS Chip Select will not draw any more current if the SI pin is toggling 2 SCK Serial Clock when the CS pin is high). This pin has a Schmitt Trigger input. 3 SI Serial Data Input 4 V Ground SS 3.7 Serial Data Output (SO) 5 PB1 Terminal B Connection For Pot 1 (MCP42XXX devices only) 6 PW1 Wiper Connection For Pot 1 This is the SPI port serial data output pin used for 7 PA1 Terminal A Connection For Pot 1 daisy-chaining more than one device. Data is clocked out of the SO pin on the falling edge of clock. This is a 8 PA0 Terminal A Connection For Pot 0 push-pull output and does not go to a high-impedance 9 PW0 Wiper Connection For Pot 0 state when CS is high. It will drive a logic-low when CS is high. 10 PB0 Terminal B Connection For Pot 0 11 RS Reset Input 3.8 Reset (RS) (MCP42XXX devices only) 12 SHDN Shutdown Input 13 SO Data Out for Daisy-Chaining The Reset pin will set all potentiometers to mid-scale (Code 80h) if this pin is brought low for at least 150ns. 14 V Power DD This pin should not be toggled low when the CS pin is low. It is possible to toggle this pin when the SHDN pin is low. In order to minimize power consumption, this pin has an active pull-up circuit. The performance of this circuit is shown in Figure2-12. This pin will draw negli- gible current at logic level ‘0’ and logic level ‘1’. Do not leave this pin floating. DS11195C-page 12  2003 Microchip Technology Inc.

MCP41XXX/42XXX 4.0 APPLICATIONS INFORMATION The MCP41XXX/42XXX devices are 256 position power-up, all data registers will automatically be loaded single and dual digital potentiometers that can be used with the mid-scale value (80h). The serial interface pro- in place of standard mechanical pots. Resistance val- vides the means for loading data into the shift register, ues of 10kΩ, 50kΩ and 100kΩ are available. As which is then transferred to the data registers. The shown in Figure4-1, each potentiometer is made up of serial interface also provides the means to place indi- a variable resistor and an 8-bit (256 position) data reg- vidual potentiometers in the shutdown mode for maxi- ister that determines the wiper position. There is a mum power savings. The SHDN pin can also be used nominal wiper resistance of 52Ω for the 10kΩ version, to put all potentiometers in shutdown mode and the RS 125Ω for the 50kΩ and 100kΩ versions. For the dual pin is provided to set all potentiometers to mid-scale devices, the channel-to-channel matching variation is (80h). less than 1%. The resistance between the wiper and either of the resistor endpoints varies linearly according to the value stored in the data register. Code 00h effectively connects the wiper to the B terminal. At PW0 PW1 PA0 PB0 PA1 PB1 RDAC1 RDAC2 Data Register 0 Data Register 1 D7 D0 D7 D0 RS Decode Logic D7 D0 CS 16-bit Shift Register SCK SI SO SHDN FIGURE 4-1: Block diagram showing the MCP42XXX dual digital potentiometer. Data register 0 and data register 1 are 8-bit registers allowing 256 positions for each wiper. Standard SPI pins are used with the addition of the Shutdown (SHDN) and Reset (RS) pins. As shown, reset affects the data register and wipers, bringing them to mid-scale. Shutdown disconnects the A terminal and connects the wiper to B, without changing the state of the data registers. When laying out the circuit for your digital potentiome- V DD V ter, bypass capacitors should be used. These capaci- DD tors should be placed as close as possible to the device 0.1uF pin. A bypass capacitor value of 0.1µF is recom- 0.1uF mended. Digital and analog traces should be separated X X as much as possible on the board, with no traces run- X B ning underneath the device or the bypass capacitor. µC X 4 W Extra precautions should be taken to keep traces with Data Lines P C A high-frequency signals (such as clock lines) as far as M possible from analog traces. Use of an analog ground plane is recommended in order to keep the ground To Application potential the same for all devices on the board. Circuit  2003 Microchip Technology Inc. DS11195C-page 13

MCP41XXX/42XXX 4.1 Modes of Operation 4.1.2 POTENTIOMETER MODE Digital potentiometer applications can be divided into In the potentiometer mode, all three terminals of the two categories: rheostat mode and potentiometer, or device are tied to different nodes in the circuit. This voltage divider, mode. allows the potentiometer to output a voltage propor- tional to the input voltage. This mode is sometimes 4.1.1 RHEOSTAT MODE called voltage divider mode. The potentiometer is used to provide a variable voltage by adjusting the wiper In the rheostat mode, the potentiometer is used as a position between the two endpoints as shown in two-terminal resistive element. The unused terminal Figure4-3. Note that reversing the polarity of the A and should be tied to the wiper, as shown in Figure4-2. B terminals will not affect operation. Note that reversing the polarity of the A and B terminals will not affect operation. V 1 A A V W 2 W B B MCP4XXXX MCP4XXXX Resistor FIGURE 4-3: Three terminal or voltage divider mode. FIGURE 4-2: Two-terminal or rheostat configuration for the digital potentiometer. Acting In this configuration, the ratio of the internal resistance defines the temperature coefficient of the device. The as a resistive element in the circuit, resistance is resistor matching of the R resistor to the R resistor controlled by changing the wiper setting. WB AB performs with a typical temperature coefficient of Using the device in this mode allows control of the total 1ppm/°C (measured at code 80h). At lower codes, the resistance between the two nodes. The total measured wiper resistance temperature coefficient will dominate. resistance would be the least at code 00h, where the Figure2-3 shows the effect of the wiper. Above the wiper is tied to the B terminal. The resistance at this lower codes, this figure shows that 70% of the states code is equal to the wiper resistance, typically 52Ω for will typically have a temperature coefficient of less than the 10kΩ MCP4X010 devices, 125Ω for the 50kΩ 5ppm/°C. 30% of the states will typically have a (MCP4X050), and 100kΩ (MCP4X100) devices. For ppm/°C of less than 1. the 10kΩ device, the LSB size would be 39.0625Ω (assuming 10kΩ total resistance). The resistance would then increase with this LSB size until the total measured resistance at code FFh would be 9985.94Ω. The wiper will never directly connect to the A terminal of the resistor stack. In the 00h state, the total resistance is the wiper resis- tance. To avoid damage to the internal wiper circuitry in this configuration, care should be taken to ensure the current flow never exceeds 1mA. For dual devices, the variation of channel-to-channel matching of the total resistance from A to B is less than 1%. The device-to-device matching, however, can vary up to 30%. In the rheostat mode, the resistance has a positive temperature coefficient. The change in wiper- to-end terminal resistance over temperature is shown in Figure2-8. The most variation over temperature will occur in the first 6% of codes (code 00h to 0Fh) due to the wiper resistance coefficient affecting the total resis- tance. The remaining codes are dominated by the total resistance tempco R , typically 800ppm/°C. AB DS11195C-page 14  2003 Microchip Technology Inc.

MCP41XXX/42XXX 4.2 Typical Applications In order for these circuits to work properly, care must be taken in a few areas. For linear operation, the analog 4.2.1 PROGRAMMABLE SINGLE-ENDED input and output signals must be in the range of V to SS AMPLIFIERS VDD for the potentiometer and input and output rails of the op-amp. The circuit in Figure4-4 requires a virtual Potentiometers are often used to adjust system refer- ground or reference input to the non-inverting input of ence levels or gain. Programmable gain circuits using the amplifier. Refer to Application Note 682, “Using digital potentiometers can be realized in a number of Single-Supply Operational Amplifiers in Embedded different ways. An example of a single-supply, inverting Systems” (DS00682), for more details. At power-up or gain amplifier is shown in Figure4-4. Due to the high reset (RS), the resistance is set to mid-scale, with R input impedance of the amplifier, the wiper resistance A and R matching. Based on the transfer function for the is not included in the transfer function. For a single-sup- B circuit, the gain is -1V/V. As the code is increased and ply, non-inverting gain configuration, the circuit in the wiper moves towards the A terminal, the gain Figure4-5 can be used. increases. Conversely, when the wiper is moved . towards the B terminal, the gain decreases. Figure4-6 MCP41010 shows this relationship. Notice the pseudo-logarithmic A B gain around decimal code 128. As the wiper V IN approaches either terminal, the step size in the gain W VDD calculation increases dramatically. Due to the - -IN mismatched ratio of RA and RB at the extreme high and low codes, small increments in wiper position can MCP606 V OUT dramatically affect the gain. As shown in Figure4-3, +IN V + recommended gains lie between 0.1 and 10V/V. REF V SS 10 VOUT = –VINRR-----B--+VREF1+RR-----B-- V) A A V/ Where: n ( ai RA = R-----A----B---(--2-2---5-5--6-6----–----D-----n---)- RB = R-----2A---5-B--6-D-----n- olute G 1 s RAB = Total Resistance of pot Ab D = Wiper setting forD =0 to 255 n n 0.1 0 64 128 192 256 FIGURE 4-4: Single-supply, Decimal code (0-255) programmable, inverting gain amplifier using a FIGURE 4-6: Gain vs. Code for inverting digital potentiometer. and differential amplifier circuits. V DD 4.2.2 PROGRAMMABLE DIFFERENTIAL VIN +IN + AMPLIFIER MCP606 VOUT An example of a differential input amplifier using digital -IN potentiometers is shown in Figure4-7. For the transfer - V function to hold, both pots must be programmed to the SS same code. The resistor-matching from channel-to- W RA RB channel within a dual device can be used as an advan- tage in this circuit. This circuit will also show stable MCP41010 operation over temperature due to the low potentiome- VOUT = VIN1+RR-----B-- ter temperature coefficient. Figure4-6 also shows the Where: A relationship between gain and code for this circuit. As the wiper approaches either terminal, the step size in R (256–D ) R D R = -----A----B--------------------------n---- R = -----A----B--------n- the gain calculation increases dramatically. This circuit A 256 B 256 is recommended for gains between 0.1 and 10V/V. R = Total Resistance of pot AB D = Wiper setting forD =0 to 255 n n FIGURE 4-5: Single-supply, programmable, non-inverting gain amplifier.  2003 Microchip Technology Inc. DS11195C-page 15

MCP41XXX/42XXX 4.3 Calculating Resistances 1/2 MCP42010 When programming the digital potentiometer settings, VB A B the following equations can be used to calculate the resistances. Programming code 00h effectively brings (SIG -) VDD the wiper to the B terminal, leaving only the wiper resis- + -IN tance. Programming higher codes will bring the wiper V A A MCP601 VOUT closer to the A terminal of the potentiometer. The equa- (SIG +) 0 +IN tions in Figure4-9 can be used to calculate the terminal 1 - 1/2P420 B VSS ruessinisgta an c1e0sk. ΩF igpuorteen4ti-o1m0 estheor.ws an example calculation C M R V = (V –V )-----B-- PA OUT A B R V A PW REF Where: PB R (256–D ) R D R = -----A----B--------------------------n---- R = -----A----B--------n- A 256 B 256 (R )(256–D ) R (D ) = -------A----B-----------------------------n----+R R = Total Resistance of pot WA n 256 W AB D = Wiper setting forD =0 to 255 n n (R )(D ) R (D ) = -------A----B-------------n----+R NOTE: Potentiometer values must be equal WB n 256 W Where: FIGURE 4-7: Single Supply PA is the A terminal programmable differential amplifier using digital PB is the B terminal PW is the wiper terminal potentiometers. RWA is resistance between Terminal A and wiper RWB is resistance between Terminal B and Wiper 4.2.3 PROGRAMMABLE OFFSET TRIM RAB is overall resistance for pot (10kΩ, 50kΩ or 100kΩ) RW is wiper resistance For applications requiring only a programmable voltage Dn is 8-bit value in data register for pot number n reference, the circuit in Figure4-8 can be used. This FIGURE 4-9: Potentiometer resistances circuit shows the device used in the potentiometer mode along with two resistors and a buffered output. are a function of code. It should be noted that, This creates a circuit with a linear relationship between when using these equations for most feedback voltage-out and programmed code. Resistors R and amplifier circuits (see Figure4-4 and Figure4-5), 1 R2 can be used to increase or decrease the output volt- the wiper resistance can be omitted due to the age step size. The potentiometer in this mode is stable high impedance input of the amplifier. over temperature. The operation of this circuit over temperature is shown in Figure2-3. The worst perfor- Example: mance over temperature will occur at the lower codes PA R = 10kΩ due to the dominating wiper resistance. R1 and R2 can 10kΩ PW Code = C0h = 192d also be used to affect the boundary voltages, thereby eliminating the use of these lower codes. PB (R )(256–D ) R (D ) = -------A----B-----------------------------n----+R VDD WA n 256 W R VDD R (C0h) = (---1---0----k---Ω-----)---(--2---5----6-----–----1---9----2----)-+52Ω 1 - WA 256 0 -IN R (C0h) = 2552Ω 01 A MCP606 WA CP41 B +IN+ VSS OUT RWB(Dn) = (---R----A---2-B--5--)-6-(--D-----n---)-+RW M 0.1uF R (C0h) = (---1---0----k---Ω-----)---(--1----9---2----)-+52Ω R WB 256 2 VSS RWB(C0h) = 7552Ω FIGURE 4-8: By changing the values of Note: All values shown are typical and R and R , the voltage output resolution of this actual results will vary. 1 2 programmable voltage reference circuit is FIGURE 4-10: Example Resistance affected. calculations. DS11195C-page 16  2003 Microchip Technology Inc.

MCP41XXX/42XXX 5.0 SERIAL INTERFACE 5.3 Using The Shutdown Command Communications from the controller to the The shutdown command allows the user to put the MCP41XXX/42XXX digital potentiometers is accom- application circuit into a power-saving mode. In this plished using the SPI serial interface. This interface mode, the A terminal is open-circuited and the B and W allows three commands: terminals are shorted together. The command select 1. Write a new value to the potentiometer data bits C1, C0 are set to 1,0. The potentiometer selection register(s). bits P1 and P0 allow each potentiometer to be shut- down independently. If either P1 or P0 are high, the 2. Cause a channel to enter low power shutdown respective potentiometer will enter shutdown mode. A mode. ‘0’ for P1 or P0 will have no effect. The eight data bits 3. NOP (No Operation) command. following the command byte still need to be transmitted Executing any command is accomplished by setting for the shutdown command, but they are ‘don’t care’ CS low and then clocking-in a command byte followed bits. See Figure5-2 for command format summary. by a data byte into the 16-bit shift register. The com- Once a particular potentiometer has entered the shut- mand is executed when CS is raised. Data is clocked- down mode, it will remain in this mode until: in on the rising edge of clock and out the SO pin on the • A new value is written to the potentiometer data falling edge of the clock (see Figure5-1). The device register, provided that the SHDN pin is high. The will track the number of clocks (rising edges) while CS device will remain in the shutdown mode until the is low and will abort all commands if the number of rising edge of the CS is detected, at which time clocks is not a multiple of 16. the device will come out of shutdown mode and the new value will be written to the data regis- 5.1 Command Byte ter(s). If the SHDN pin is low when the new value The first byte sent is always the command byte, fol- is received, the registers will still be set to the new lowed by the data byte. The command byte contains value, but the device will remain in shutdown two command select bits and two potentiometer select mode. This scenario assumes that a valid com- bits. Unused bits are ‘don’t care’ bits. The command mand was received. If an invalid command was select bits are summarized in Figure5-2. The com- received, the command will be ignored and the mand select bits C1 and C0 (bits 4:5) of the command device will remain in the shutdown mode. byte determine which command will be executed. If the It is also possible to use the hardware shutdown pin command bits are both 0’s or 1’s, then a NOP com- and reset pin to remove a device from software shut- mand will be executed once all 16 bits have been down. To do this, a low pulse on the chip select line loaded. This command is useful when using the daisy- must first be sent. For multiple devices, sharing a single chain configuration. When the command bits are 0,1, a SHDN or RESET line allows you to pick an individual write command will be executed with the 8 bits sent in device on that chain to remove from software shutdown the data byte. The data will be written to the potentiom- mode. See Figure1-3 for timing. With a preceding chip eter(s) determined by the potentiometer select bits. If select pulse, either of these situations will also remove the command bits are 1,0, then a shutdown command a device from software shutdown: will be executed on the potentiometers determined by • A falling edge is seen on the RS pin and held low the potentiometer select bits. for at least 150ns, provided that the SHDN pin is For the MCP42XXX devices, the potentiometer select high. If the SHDN pin is low, the registers will still bits P1 and P0 (bits 0:1) determine which potentiome- be set to mid-scale, but the device will remain in ters are to be acted upon by the command. A corre- shutdown mode. This condition assumes that CS sponding ‘1’ in the position signifies that the command is high, as bringing the RS pin low while CS is low for that potentiometer will get executed, while a ‘0’ sig- is an invalid state and results are indeterminate. nifies that the command will not effect that • A rising edge on the SHDN pin is seen after being potentiometer (see Figure5-2). low for at least 100ns, provided that the CS pin is 5.2 Writing Data Into Data Registers high. Toggling the SHDN pin low while CS is low is an invalid state and results are indeterminate. When new data is written into one or more of the poten- • The device is powered-down and back up. tiometer data registers, the write command is followed by the data byte for the new value. The command Note: The hardware SHDN pin will always put select bits C1, C0 are set to 0,1. The potentiometer the device in shutdown regardless of selection bits P1 and P0 allow new values to be written whether a potentiometer has already been to potentiometer 0, potentiometer 1 (or both) with a sin- put in the shutdown mode using the gle command. A ‘1’ for either P1 or P0 will cause the software command. data to be written to the respective data register and a ‘0’ for P1 or P0 will cause no change. See Figure5-2 for the command format summary.  2003 Microchip Technology Inc. DS11195C-page 17

MCP41XXX/42XXX Data is always latched Data is always clocked out in on the rising edge of the SO pin after the of SCK. falling edge of SCK. CS† Data Registers are loaded on rising edge of CS. Shift 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 register is loaded with zeros at this time. SCK COMMAND Byte Data Byte Don’t Don’t Channel Care Command Care Select New Register Data Bits Bits Bits Bits SI X X C1 C0 X X P1* P0 D7 D6 D5 D4 D3 D2 D1 D0 SO pin will always drive low when CS First 16 bits shifted out will always be zeros goes high. SO‡ X † There must always be multiples of 16 clocks while CS is low or commands will abort. ‡ The serial data out pin (SO) is only available on the MCP42XXX device. * P1 is a ‘don’t care’ bit for the MCP41XXX. FIGURE 5-1: Timing Diagram for Writing Instructions or Data to a Digital Potentiometer. COMMAND BYTE X X C1 C0 X X P1*P0 Command Potentiometer Selection Selection Bits Bits C1 C0 Command Command Summary P1* P0 Potentiometer Selections 0 0 None No Command will be executed. 0 0 Dummy Code: Neither Potentiometer affected. 0 1 Write Data Write the data contained in Data Byte to the potentiometer(s) determined by the potenti- 0 1 Command executed on ometer selection bits. Potentiometer 0. 1 0 Shutdown Potentiometer(s) determined by potentiome- 1 0 Command executed on ter selection bits will enter Shutdown Mode. Potentiometer 1. Data bits for this command are ‘don’t cares’. 1 1 Command executed on both 1 1 None No Command will be executed. Potentiometers. FIGURE 5-2: Command Byte Format. DS11195C-page 18  2003 Microchip Technology Inc.

MCP41XXX/42XXX 5.4 Daisy-Chain Configuration When using the daisy-chain configuration, keep in mind that the shift register of each device is automatically Multiple MCP42XXX devices can be connected in a loaded with zeros whenever a command is executed daisy-chain configuration, as shown in Figure5-4, by (CS = high). Because of this, the first 16 bits that come connecting the SO pin from one device to the SI pin on out of the SO pin once the CS line goes low will always the next device. The data on the SO pin is the output of be zeros. This means that when the first command is the 16-bit shift register. The daisy-chain configuration being loaded into a device, it will always shift a NOP allows the system designer to communicate with sev- command into the next device on the chain because eral devices without using a separate CS line for each the command bits (and all the other bits) will be zeros. device. The example shows a daisy-chain configura- This feature makes it necessary only to send command tion with three devices, although any number of and data bytes to the device farthest down the chain devices (with or without the same resistor values) can that needs a new command. For example, if there were be configured this way. While it is not possible to use a three devices on the chain and it was desired to send a MCP41XXX at the beginning or middle of a daisy-chain command to the device in the middle, only 32 bytes of (because it does not provide the serial data out (SO) data need to be transmitted. The last device on the pin), it is possible to use the device at the end of a chain will have a NOP loaded from the previous device chain. As shown in the timing diagram in Figure5-3, so no registers will be affected when the CS pin is data will be clocked-out of the SO pin on the falling raised to execute the command. The user must edge of the clock. The SO pin has a CMOS push-pull always ensure that multiples of 16 clocks are output and will drive low when CS goes high. SO will always provided (while CS is low), as all commands not go to a high-impedance state when CS is held high. will abort if the number of clocks provided is not a When using the daisy-chain configuration, the maxi- multiple of 16. mum clock speed possible is reduced to ~5.8MHz, because of the propagation delay of the data coming out of the SO pin. Data Registers for all devices are loaded on Rising Edge of CS CS 1 2 3 4 5 6 7 8 910111213141516 1 2 3 4 5 6 7 8 910111213141516 1 2 3 4 5 6 7 8 910111213141516 SCK Command Byte Data Byte Command Byte Data Byte Command Byte Data Byte for Device 3 for Device 3 for Device 2 for Device 2 for Device 1 for Device 1 SI X XCC X X P PD DD DDDD D X XCC X X P PDDD DDDD D X XCC X X P PDDD DDDD D Command and Data for Device 3 Command and Data for Device 2 First 16 bits shifted out start shifting out after the first 16 clocks start shifting out after the first 32 clocks will always be zeros SO X XC C X X P PDDD DDDD D X XC C X X P PDDD DDDD D † There must always be multiples of 16 clocks while CS is low or commands will abort. ‡ The serial data out pin (SO) is only available on the MCP42XXX device. FIGURE 5-3: Timing Diagram for Daisy-Chain Configuration.  2003 Microchip Technology Inc. DS11195C-page 19

MCP41XXX/42XXX CS SCK SO Microcontroller CS SCK CS SI SO SCK Device 1 CS SI SO SCK EXAMPLE: Device 2 SI If you want to load the following Device 3* command/data into each part in the chain. Device 1 XX10XX1111001100 Device 2 XX01XX1011110000 Device 3 XX10XX0010101010 (cid:99) After 16 clocks, Device 2 and Device 3 will both have all zeros clocked in from the Start by setting CS low and previous part’s shift register. clocking in the command and data that will end up in Device Device 1 XX10XX0010101010 Device 2 3 (16 clocks). 0000000000000000 Device 3 0000000000000000 (cid:100) After 32 clocks, Device 2 has the data previously loaded Clock-In the command and into Device 1 and Device 3 data for Device 2 (16 more gets 16 more zeros. clocks). The data that was pre- Device 1 viously loaded gets shifted to XX01XX1011110000 Device 2 the next device on the chain. XX10XX0010101010 Device 3 0000000000000000 (cid:101) After 48 clocks, all 3 devices Clock-In the data for Device 1 have the proper command/ (16 more clocks). The data that data loaded into their shift was previously loaded into registers. Device 1 gets shifted into Device 1 Device 2 and Device 3 contains XX10XX1111001100 Device 2 the first byte loaded. Raise the XX01XX1011110000 Device 3 XX10XX0010101010 CS line to execute the com- mands for all 3 devices at the same time. * Last device on a daisy-chain may be a single channel MCP41XXX device. FIGURE 5-4: Daisy-Chain Configuration. DS11195C-page 20  2003 Microchip Technology Inc.

MCP41XXX/42XXX 5.5 Reset (RS) Pin Operation TABLE 5-1: TRUTH TABLE FOR LOGIC INPUTS The Reset pin (RS) will automatically set all potentiom- eter data latches to mid-scale (Code 80h) when pulled SCK CS RS SHDN Action low (provided that the pin is held low at least 150ns and CS is high). The reset will execute regardless of X Ø H H Communication is initiated with the position of the SCK, SHDN and SI pins. It is possi- device. Device comes out of ble to toggle RS low and back high while SHDN is low. standby mode. In this case, the potentiometer registers will reset to L L H H No action. Device is waiting for mid-scale, but the potentiometer will remain in data to be clocked into shift shutdown mode until the SHDN pin is raised. register or CS to go high to execute command. Note: Bringing the RS pin low while the CS pin is ¦ L H X Shift one bit into shift register. low constitutes an invalid operating state The shift register can be loaded and will result in indeterminate results while the SHDN pin is low. when RS and/or CS are brought high. Ø L H X Shift one bit out of shift register on the SO pin. The SO pin is 5.6 Shutdown (SHDN) Pin Operation active while the SHDN pin is low. When held low, the shutdown pin causes the applica- X ¦ H H Based on command bits, either tion circuit to go into a power-saving mode by open-cir- load data from shift register into cuiting the A terminal and shorting the B and W data latches or execute shut- terminals for all potentiometers. Data register contents down command. Neither com- are not affected by entering shutdown mode (i.e., when mand executed unless multiples of 16 clocks have the SHDN pin is raised, the data register contents are been entered while CS is low. the same as before the shutdown mode was entered). SO pin goes to a logic low. While in shutdown mode, it is still possible to clock in X H H H Static Operation. new values for the data registers, as well as toggling X H Ø H All data registers set and the RS pin to cause all data registers to go to mid-scale. latched to code 80h. The new values will take affect when the SHDN pin is X H Ø L All data registers set and raised. latched to code 80h. Device is If the device is powered-up with the SHDN pin held low, in hardware shutdown mode it will power-up in the shutdown mode with the data reg- and will remain in this mode. isters set to mid-scale. X H H Ø All potentiometers put into hardware shutdown mode; Note: Bringing the SHDN pin low while the CS terminal A is open and W is pin is low constitutes an invalid operating shorted to B. state and will result in indeterminate X H H ¦ All potentiometers exit hard- results when SHDN and/or CS are brought ware shutdown mode. Potenti- high. ometers will also exit software shutdown mode if this rising 5.7 Power-up Considerations edge occurs after a low pulse on CS. Contents of data When the device is powered on, the data registers will latches are restored. be set to mid-scale (80h). A power-on reset circuit is utilized to ensure that the device powers up in this known state.  2003 Microchip Technology Inc. DS11195C-page 21

MCP41XXX/42XXX 5.8 Using the MCP41XXX/42XXX in SPI Mode 1,1 It is possible to operate the devices in SPI modes 0,0 and 1,1. The only difference between these two modes is that, when using mode 1,1, the clock idles in the high state, while in mode 0,0, the clock idles in the low state. In both modes, data is clocked into the devices on the rising edge of SCK and data is clocked out the SO pin once the falling edge of SCK. Operations using mode 0,0 are shown in Figure5-1. The example in Figure5-5 shows mode 1,1. Data is always latched in Data is always clocked out the SO Data Registers are on the rising edge of SCK. pin after the falling edge of SCK. loaded on rising CS† edge of CS. Shift register is loaded with zeros at this time. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SCK COMMAND BYTE DATA BYTE Don’t Don’t Channel Care Command Care Select New Register Data Bits Bits Bits Bits SI X X C1 C0 X X P1* P0 D7 D6 D5 D4 D3 D2 D1 D0 SO pin will always drive low when CS First 16 bits Shifted out will always be zeros goes high. SO‡ X † There must always be multiples of 16 clocks while CS is low or commands will abort. ‡ The serial data out pin (SO) is only available on the MCP42XXX device. FIGURE 5-5: Timing Diagram for SPI Mode 1,1 Operation. DS11195C-page 22  2003 Microchip Technology Inc.

MCP41XXX/42XXX 6.0 PACKAGING INFORMATION 6.1 Package Marking Information 8-Lead PDIP (300 mil) Example: XXXXXXXX MCP41010 XXXXXNNN I/P256 YYWW 0313 8-Lead SOIC (150 mil) Example: XXXXXXXX MCP41050 XXXXYYWW I/SN0313 NNN 256 14-Lead PDIP (300 mil) Example: XXXXXXXXXXXXXX MCP42010 XXXXXXXXXXXXXX I/P YYWWNNN 0313256 14-Lead SOIC (150 mil) Example: XXXXXXXXXXX 42050ISL XXXXXXXXXXX XXXXXXXXXXX YYWWNNN 0313256 14-Lead TSSOP (4.4mm) * Example: XXXXXXXX 42100I YYWW 0313 NNN 256 Legend: XX...X Customer specific information* YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard marking consists of Microchip part number, year code, week code, facility code, mask rev#, and assembly code.  2003 Microchip Technology Inc. DS11195C-page 23

MCP41XXX/42XXX 8-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n 1 α E A A2 L c A1 β B1 p eB B Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch p .100 2.54 Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32 Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26 Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60 Overall Length D .360 .373 .385 9.14 9.46 9.78 Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43 Lead Thickness c .008 .012 .015 0.20 0.29 0.38 Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78 Lower Lead Width B .014 .018 .022 0.36 0.46 0.56 Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92 Mold Draft Angle Top α 5 10 15 5 10 15 Mold Draft Angle Bottom β 5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018 DS11195C-page 24  2003 Microchip Technology Inc.

MCP41XXX/42XXX 8-Lead Plastic Small Outline (SN) –Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 h α 45° c A A2 φ β L A1 Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch p .050 1.27 Overall Height A .053 .061 .069 1.35 1.55 1.75 Molded Package Thickness A2 .052 .056 .061 1.32 1.42 1.55 Standoff § A1 .004 .007 .010 0.10 0.18 0.25 Overall Width E .228 .237 .244 5.79 6.02 6.20 Molded Package Width E1 .146 .154 .157 3.71 3.91 3.99 Overall Length D .189 .193 .197 4.80 4.90 5.00 Chamfer Distance h .010 .015 .020 0.25 0.38 0.51 Foot Length L .019 .025 .030 0.48 0.62 0.76 Foot Angle φ 0 4 8 0 4 8 Lead Thickness c .008 .009 .010 0.20 0.23 0.25 Lead Width B .013 .017 .020 0.33 0.42 0.51 Mold Draft Angle Top α 0 12 15 0 12 15 Mold Draft Angle Bottom β 0 12 15 0 12 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057  2003 Microchip Technology Inc. DS11195C-page 25

MCP41XXX/42XXX 14-Lead Plastic Dual In-line (P) –300 mil (PDIP) E1 D 2 n 1 α E A A2 c L A1 β B1 eB B p Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 14 14 Pitch p .100 2.54 Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32 Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26 Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60 Overall Length D .740 .750 .760 18.80 19.05 19.30 Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43 Lead Thickness c .008 .012 .015 0.20 0.29 0.38 Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78 Lower Lead Width B .014 .018 .022 0.36 0.46 0.56 Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92 Mold Draft Angle Top α 5 10 15 5 10 15 Mold Draft Angle Bottom β 5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-005 DS11195C-page 26  2003 Microchip Technology Inc.

MCP41XXX/42XXX 14-Lead Plastic Small Outline (SL) –Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 α h 45° c A A2 φ A1 L β Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 14 14 Pitch p .050 1.27 Overall Height A .053 .061 .069 1.35 1.55 1.75 Molded Package Thickness A2 .052 .056 .061 1.32 1.42 1.55 Standoff § A1 .004 .007 .010 0.10 0.18 0.25 Overall Width E .228 .236 .244 5.79 5.99 6.20 Molded Package Width E1 .150 .154 .157 3.81 3.90 3.99 Overall Length D .337 .342 .347 8.56 8.69 8.81 Chamfer Distance h .010 .015 .020 0.25 0.38 0.51 Foot Length L .016 .033 .050 0.41 0.84 1.27 Foot Angle φ 0 4 8 0 4 8 Lead Thickness c .008 .009 .010 0.20 0.23 0.25 Lead Width B .014 .017 .020 0.36 0.42 0.51 Mold Draft Angle Top α 0 12 15 0 12 15 Mold Draft Angle Bottom β 0 12 15 0 12 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-065  2003 Microchip Technology Inc. DS11195C-page 27

MCP41XXX/42XXX 14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP) E E1 p D 2 n 1 B α A c φ β A1 A2 L Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 14 14 Pitch p .026 0.65 Overall Height A .043 1.10 Molded Package Thickness A2 .033 .035 .037 0.85 0.90 0.95 Standoff § A1 .002 .004 .006 0.05 0.10 0.15 Overall Width E .246 .251 .256 6.25 6.38 6.50 Molded Package Width E1 .169 .173 .177 4.30 4.40 4.50 Molded Package Length D .193 .197 .201 4.90 5.00 5.10 Foot Length L .020 .024 .028 0.50 0.60 0.70 Foot Angle φ 0 4 8 0 4 8 Lead Thickness c .004 .006 .008 0.09 0.15 0.20 Lead Width B .007 .010 .012 0.19 0.25 0.30 Mold Draft Angle Top α 0 5 10 0 5 10 Mold Draft Angle Bottom β 0 5 10 0 5 10 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005” (0.127mm) per side. JEDEC Equivalent: MO-153 Drawing No. C04-087 DS11195C-page 28  2003 Microchip Technology Inc.

MCP41XXX/42XXX PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX Examples: a) MCP41010-I/SN: I-Temp., 8LD SOIC pkg. Device Temperature Package b) MCP41010-E/P: E-Temp., 8LD PDIP pkg. Range c) MCP41010T-I/SN: Tape and Reel, I-Temp., 8LD SOIC pkg. d) MCP41050-E/SN: E-Temp., 8LD SOIC pkg. Device: MCP41010: Single Digital Potentiometer (10kΩ) e) MCP41050-I/P: I-Temp., 8LD PDIP pkg. MCP41010T:Single Digital Potentiometer (10kΩ) f) MCP41050-E/SN: E-Temp., 8LD SOIC pkg. (Tape and Reel) g) MCP41100-I/SN: I-Temp., 8LD SOIC MCP41050: Single Digital Potentiometer (50kΩ) package. (Tape and Reel) h) MCP41100-E/P: E-Temp., 8LD PDIP pkg. MCP41050T:Single Digital Potentiometer (50kΩ) i) MCP41100T-I/SN: I-Temp., 8LD SOIC pkg. MCP41100: Single Digital Potentiometer (100kΩ) (Tape and Reel) a) MCP42010-E/P: E-Temp., 14LD PDIP pkg. MCP41100T: Single Digital Potentiometer (100kΩ) b) MCP42010-I/SL: I-Temp., 14LD SOIC pkg. c) MCP42010-E/ST: E-Temp., 14LD TSSOP MCP42010: Dual Digital Potentiometer (10kΩ) pkg. MCP42010T:Dual Digital Potentiometer (10kΩ) d) MCP42010T-I/ST: Tape and Reel, I-Temp., (Tape and Reel) 14LD TSSOP pkg. MCP42050: Dual Digital Potentiometer (50kΩ) MCP42050T:Dual Digital Potentiometer (50kΩ) e) MCP42050-E/P: E-Temp., 14LD PDIP pkg. (Tape and Reel) f) MCP42050T-I/SL: Tape and Reel, I-Temp., MCP42100: Dual Digital Potentiometer (100kΩ) 14LD SOIC pkg. MCP42100T:Dual Digital Potentiometer (100kΩ) g) MCP42050-E/SL: E-Temp., 14LD SOIC pkg. (Tape and Reel) h) MCP42050-I/ST: I-Temp., 14LD TSSOP pkg. i) MCP42050T-I/SL: Tape and Reel, I-Temp., Temperature Range: I = -40°C to +85°C 14LD SOIC pkg. E = -40°C to +125°C j) MCP42050T-I/ST: Tape and Reel, I-Temp., 14LD TSSOP pkg. k) MCP42100-E/P: E-Temp., 14LD PDIP pkg. Package: P = Plastic DIP (300 mil Body), 8-lead, 14-lead l) MCP42100-I/SL: I-Temp., 14LD SOIC pkg. SN = Plastic SOIC (150 mil Body), 8-lead m) MCP42100-E/ST: E-Temp., 14LD TSSOP SL = Plastic SOIC (150 mil Body), 14-lead pkg. ST = TSSOP (4.4mm Body), 14-lead n) MCP42100T-I/SL: Tape and Reel, I-Temp., 14LD SOIC pkg. o) MCP42100T-I/ST: Tape and Reel, I-Temp., 14LD TSSOP pkg. Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office 2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 3. The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.  2003 Microchip Technology Inc. DS11195C-page 29

MCP41XXX/42XXX NOTES: DS11195C-page 30  2003 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to The Microchip name and logo, the Microchip logo, dsPIC, ensure that your application meets with your specifications. KEELOQ, MPLAB, PIC, PICmicro, PICSTART, PRO MATE and No representation or warranty is given and no liability is PowerSmart are registered trademarks of Microchip assumed by Microchip Technology Incorporated with respect Technology Incorporated in the U.S.A. and other countries. to the accuracy or use of such information, or infringement of FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL patents or other intellectual property rights arising from such and The Embedded Control Solutions Company are use or otherwise. Use of Microchip’s products as critical registered trademarks of Microchip Technology Incorporated components in life support systems is not authorized except in the U.S.A. with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual Accuron, Application Maestro, dsPICDEM, dsPICDEM.net, property rights. ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In- Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICC, PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPIC, Select Mode, SmartSensor, SmartShunt, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2003, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified.  2003 Microchip Technology Inc. DS11195C-page 31

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: MCP42100-I/SL MCP42100-I/P MCP42100-I/ST MCP42050-I/SL MCP42050-I/ST MCP42010-I/ST MCP42010- I/SL MCP42100-E/P MCP41100-E/P MCP41100-I/P MCP41010-I/P MCP42010-I/P MCP41050-E/P MCP42050-E/P MCP41100-E/SN MCP41050-E/SN MCP41010-E/SN MCP41010-E/P MCP42100T-E/ST MCP42010T-E/SL MCP41050T-I/SN MCP41100T-I/SN MCP42010T-E/ST MCP42050T-E/SL MCP41010T-I/SN MCP42050T-E/ST MCP42100T-E/SL MCP41050T-E/SN MCP42050T-I/ST MCP41010T-E/SN MCP42050T-I/SL MCP42010T-I/SL MCP42010T-I/ST MCP41050-I/P MCP42050-I/P MCP42010-E/P MCP42100-E/SL MCP42010-E/ST MCP42050- E/SL MCP42100-E/ST MCP42010-E/SL MCP42050-E/ST MCP41050-I/SN MCP41010-I/SN MCP41100-I/SN MCP42100T-I/ST MCP42100T-I/SL MCP41100T-E/SN MCP4241T-502E/ML MCP4241-104E/P MCP4241-502E/P MCP4241-503E/P MCP4241T-103E/ML MCP4241T-104E/ML MCP4241T-503E/ML