MCP40D17/18/19 2 7-Bit Single I C™ (with Command Code) Digital POT with Volatile Memory in SC70 Package Types Features • Potentiometer or Rheostat configuration options Potentiometer Rheostat • 7-bit: Resistor Network Resolution MCP40D18 MCP40D17 SC70-6 - 127Resistors (128Steps) SC70-6 • Zero Scale to Full Scale Wiper operation VDD 1 A 6 A VDD 1 W 6 W A • RAB Resistances: 5kΩ, 10kΩ, 50kΩ, or 100kΩ VSS 2 5 W VSS 2 B 5 B B W • Low Wiper Resistance: 100Ω (typical) SCL 3 4 SDA SCL 3 4 SDA • Low Tempco: MCP40D19 - Absolute (Rheostat): 50ppm typical SC70-5 (0°C to 70°C) - Ratiometric (Potentiometer): 15ppm typical VDD 1 W 5 W • I2C Protocol VSS 2 B A SCL 3 4 SDA - Supports SMBus 2.0 Write Byte/Word Protocol Formats - Supports SMBus 2.0 Read Byte/Word Applications Protocol Formats • Standard I2C Device Addresses: • PC Servers (I2C Protocol with Command Code) • Amplifier Gain Control and Offset Adjustment - All devices offered with address “0101110” - MCP40D18 also offered with address • Sensor Calibration (Pressure, Temperature, “0111110” Position, Optical and Chemical) • Brown-out reset protection (1.5V typical) • Set point or offset trimming • Power-on Default Wiper Setting (Mid-scale) • Cost-sensitive mechanical trim pot replacement • Low-Power Operation: • RF Amplifier Biasing - 2.5µA Static Current (typical) • LCD Brightnes and Contract Adjustment • Wide Operating Voltage Range: - 2.7V to 5.5V - Device Characteristics Specified - 1.8V to 5.5V - Device Operation • Wide Bandwidth (-3dB) Operation: - 2MHz (typical) for 5.0kΩ device • Extended temperature range (-40°C to +125°C) • Very small package (SC70) • Lead free (Pb-free) package Device Features s Resistance (typical) Device Control Interface # of Step ConWfigipuerar tion Memory Type Options (kΩ) W(iΩp)er ORpaneVrgDaeDt i (n1g) Package MCP40D17 I2C 128 Rheostat RAM 5.0, 10.0, 50.0, 100.0 75 1.8V to 5.5V SC70-6 MCP40D18 I2C 128 Potentiometer RAM 5.0, 10.0, 50.0, 100.0 75 1.8V to 5.5V SC70-6 MCP40D19 I2C 128 Rheostat RAM 5.0, 10.0, 50.0, 100.0 75 1.8V to 5.5V SC70-5 Note 1: Analog characteristics only tested from 2.7V to 5.5V © 2009 Microchip Technology Inc. DS22152B-page 1

MCP40D17/18/19 Device Block Diagram VDD Power-up/ A (2) Brown-out V SS Control W I2C Serial SCL Interface Resistor SDA Module, Network 0 B (1, 2) Control (Pot 0) Logic, & Note1: Some configurations will have this Memory signal internally connected to Note 1 ground. 2: In some configurations, this signal may not be connected externally (internally floating or grounded). Comparison of Similar Microchip Devices (1) Device Control Interface # of Steps ConWfigipuerar tion Memory Type ResOisptatinocnes ((tkyΩpi)cal) OpReVarnDaDgti eng HV Interface WiperLock Technology Package MCP40D17 (2) I2C 128 Rheostat RAM 5.0, 10.0, 50.0, 100.0 1.8V to 5.5V No No SC70-6 MCP4017 (2,4) I2C 128 Rheostat RAM 5.0, 10.0, 50.0, 100.0 1.8V to 5.5V No No SC70-6 MCP4012 (2) U/D 64 Rheostat RAM 2.1, 5.0, 10.0, 50.0 1.8V to 5.5V Yes No SOT-23-6 MCP4022 (2) U/D 64 Rheostat EE 2.1, 5.0, 10.0, 50.0 2.7V to 5.5V Yes Yes SOT-23-6 MCP4132 (3) SPI 129 Rheostat RAM 5.0, 10.0, 50.0, 100.0 1.8V to 5.5V Yes No PDIP-8, MCP4142 (3) SPI 129 Rheostat EE 5.0, 10.0, 50.0, 100.0 2.7V to 5.5V Yes Yes SOIC-8, MSOP-8, MCP4152 (3) SPI 257 Rheostat RAM 5.0, 10.0, 50.0, 100.0 1.8V to 5.5V Yes No DFN-8 MCP4162 (3) SPI 257 Rheostat EE 5.0, 10.0, 50.0, 100.0 2.7V to 5.5V Yes Yes MCP4532 (3) I2C 129 Rheostat RAM 5.0, 10.0, 50.0, 100.0 1.8V to 5.5V Yes No MSOP-8, MCP4542 (3) I2C 129 Rheostat EE 5.0, 10.0, 50.0, 100.0 2.7V to 5.5V Yes Yes DFN-8 MCP4552 (3) I2C 257 Rheostat RAM 5.0, 10.0, 50.0, 100.0 1.8V to 5.5V Yes No MCP4562 (3) I2C 257 Rheostat EE 5.0, 10.0, 50.0, 100.0 2.7V to 5.5V Yes Yes MCP40D18 (2) I2C 128 Potentiometer RAM 5.0, 10.0, 50.0, 100.0 1.8V to 5.5V No No SC70-6 MCP4018 (2,4) I2C 128 Potentiometer RAM 5.0, 10.0, 50.0, 100.0 1.8V to 5.5V No No SC70-6 MCP4013 (2) U/D 64 Potentiometer RAM 2.1, 5.0, 10.0, 50.0 1.8V to 5.5V Yes No SOT-23-6 MCP4023 (2) U/D 64 Potentiometer EE 2.1, 5.0, 10.0, 50.0 2.7V to 5.5V Yes Yes SOT-23-6 MCP40D19 (2) I2C 128 Rheostat RAM 5.0, 10.0, 50.0, 100.0 1.8V to 5.5V No No SC70-5 MCP4019 (2,4) I2C 128 Rheostat RAM 5.0, 10.0, 50.0, 100.0 1.8V to 5.5V No No SC70-5 MCP4014 (2) U/D 64 Rheostat RAM 2.1, 5.0, 10.0, 50.0 1.8V to 5.5V Yes No SOT-23-5 MCP4024 (2) U/D 64 Rheostat EE 2.1, 5.0, 10.0, 50.0 2.7V to 5.5V Yes Yes SOT-23-5 Note 1: This table is broken into three groups by a thick line (and color coding). The unshaded devices in this table are the devices described in this data sheet, while the shaded devices offer a comparable resistor network configuration. 2: Analog characteristics only tested from 2.7V to 5.5V. 3: Analog characteristics only tested from 3.0V to 5.5V. 4: These devices have a simplified I2C command format, which allows higher data throughput. DS22152B-page 2 © 2009 Microchip Technology Inc.

MCP40D17/18/19 1.0 ELECTRICAL † Notice: Stresses above those listed under “Maximum CHARACTERISTICS Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those Absolute Maximum Ratings † indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions Voltage on V with respect to V ..... -0.6V to +7.0V DD SS for extended periods may affect device reliability. Voltage on SCL, and SDA with respect to V SS -0.6V to 12.5V ............................................................................. Voltage on all other pins (A, W, and B) with respect to V -0.3V to V + 0.3V SS............................ DD Input clamp current, I IK (VI < 0, VI > VDD, VI > VPP ON HV pins)...........±20mA Output clamp current, I OK (V < 0 or V > V ).......................................±20mA O O DD Maximum output current sunk by any Output pin ...........................................................................25mA Maximum output current sourced by any Output pin ...........................................................................25mA Maximum current out of V pin......................100mA SS Maximum current into V pin.........................100mA DD Maximum current into A, W and B pins...........±2.5mA Package power dissipation (T = +50°C, T = +150°C) A J SC70-5............................................................302mW SC70-6............................................................483mW Storage temperature..........................-65°C to +150°C Ambient temperature with power applied ...........................................................-40°C to +125°C ESD protection on all pins ........................≥ 4kV (HBM) ........................................................................≥ 400V (MM) Maximum Junction Temperature (T ) ..............+150°C J © 2009 Microchip Technology Inc. DS22152B-page 3

MCP40D17/18/19 AC/DC CHARACTERISTICS Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C ≤ T ≤ +125°C (extended) A DC Characteristics All parameters apply across the specified operating ranges unless noted. V = +2.7V to 5.5V, 5kΩ, 10kΩ, 50kΩ, 100kΩ devices. DD Typical specifications represent values for V = 5.5V, T = +25°C. DD A Parameters Sym Min Typ Max Units Conditions Supply Voltage V 2.7 — 5.5 V Analog Characteristics specified DD 1.8 — 5.5 V Digital Characteristics specified V Start Voltage V — — 1.65 V RAM retention voltage (V ) < V DD BOR RAM BOR to ensure Wiper Reset V Rise Rate to V (Note7) V/ms DD DDRR ensure Power-on Reset Delay after device T — 10 20 µS BORD exits the reset state (V > V ) DD BOR Supply Current I — 45 80 µA Serial Interface Active, DD (Note8) Write all 0’s to Volatile Wiper V = 5.5V, F = 400kHz DD SCL — 2.5 5 µA Serial Interface Inactive, (Stop condition, SCL = SDA = V ), IH Wiper = 0, V = 5.5V DD Note 1: Resistance is defined as the resistance between terminal A to terminal B. 2: INL and DNL are measured at V with V = V and V = V . W A DD B SS 3: MCP40D18 device only, includes V and V . WZSE WFSE 4: Resistor terminals A, W and B’s polarity with respect to each other is not restricted. 5: This specification by design. 6: Non-linearity is affected by wiper resistance (R ), which changes significantly over voltage and W temperature. 7: POR/BOR is not rate dependent. 8: Supply current is independent of current through the resistor network DS22152B-page 4 © 2009 Microchip Technology Inc.

MCP40D17/18/19 AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C ≤ T ≤ +125°C (extended) A DC Characteristics All parameters apply across the specified operating ranges unless noted. V = +2.7V to 5.5V, 5kΩ, 10kΩ, 50kΩ, 100kΩ devices. DD Typical specifications represent values for V = 5.5V, T = +25°C. DD A Parameters Sym Min Typ Max Units Conditions Resistance R 4.0 5 6.0 kΩ -502 devices (Note1) AB (± 20%) 8.0 10 12.0 kΩ -103 devices (Note1) 40.0 50 60.0 kΩ -503 devices (Note1) 80.0 100 120.0 kΩ -104 devices (Note1) Resolution N 128 Taps No Missing Codes Step Resistance R — R / — Ω Note5 S AB (127) Wiper Resistance R — 100 170 Ω V = 5.5 V, I = 2.0mA, code = 00h W DD W — 155 325 Ω V = 2.7 V, I = 2.0mA, code = 00h DD W Nominal ΔR /ΔT — 50 — ppm/°C T = -20°C to +70°C AB A Resistance — 100 — ppm/°C T = -40°C to +85°C A Tempco — 150 — ppm/°C T = -40°C to +125°C A Ratiometeric ΔV /ΔT — 15 — ppm/°C Code = Midscale (3Fh) WB Tempco Resistor Terminal V V V Vss — V V Note4, Note5 A, W, B DD Input Voltage Range (Terminals A, B and W) Maximum current I — — 2.5 mA Terminal A I , W = Full Scale (FS) T AW through Terminal — — 2.5 mA Terminal B I , W = Zero Scale (ZS) BW (A, W or B) — — 2.5 mA Terminal W I or I , W = FS or ZS Note5 AW BW — — 1.38 mA I , V = 0V, V = 5.5V, AB B A R = 4000 AB(MIN) — — 0.688 mA I , V = 0V, V = 5.5V, Terminal A AB B A R = 8000 and AB(MIN) — — 0.138 mA I , V = 0V, V = 5.5V, Terminal B AB B A R = 40000 AB(MIN) — — 0.069 mA I , V = 0V, V = 5.5V, AB B A R = 80000 AB(MIN) Note 1: Resistance is defined as the resistance between terminal A to terminal B. 2: INL and DNL are measured at V with V = V and V = V . W A DD B SS 3: MCP40D18 device only, includes V and V . WZSE WFSE 4: Resistor terminals A, W and B’s polarity with respect to each other is not restricted. 5: This specification by design. 6: Non-linearity is affected by wiper resistance (R ), which changes significantly over voltage and W temperature. 7: POR/BOR is not rate dependent. 8: Supply current is independent of current through the resistor network © 2009 Microchip Technology Inc. DS22152B-page 5

MCP40D17/18/19 AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C ≤ T ≤ +125°C (extended) A DC Characteristics All parameters apply across the specified operating ranges unless noted. V = +2.7V to 5.5V, 5kΩ, 10kΩ, 50kΩ, 100kΩ devices. DD Typical specifications represent values for V = 5.5V, T = +25°C. DD A Parameters Sym Min Typ Max Units Conditions Full Scale Error V -3.0 -0.1 — LSb 5kΩ 2.7V ≤ V ≤ 5.5V WFSE DD (MCP40D18 only) -2.0 -0.1 — LSb 10kΩ 2.7V ≤ V ≤ 5.5V DD (code = 7Fh) -0.5 -0.1 — LSb 50kΩ 2.7V ≤ V ≤ 5.5V DD -0.5 -0.1 — LSb 100kΩ 2.7V ≤ V ≤ 5.5V DD Zero Scale Error V — +0.1 +3.0 LSb 5kΩ 2.7V ≤ V ≤ 5.5V WZSE DD (MCP40D18 only) — +0.1 +2.0 LSb 10kΩ 2.7V ≤ V ≤ 5.5V DD (code = 00h) — +0.1 +0.5 LSb 50kΩ 2.7V ≤ V ≤ 5.5V DD — +0.1 +0.5 LSb 100kΩ 2.7V ≤ V ≤ 5.5V DD Potentiometer INL -0.5 ±0.25 +0.5 LSb 2.7V ≤ V ≤ 5.5V DD Integral MCP40D18 device only (Note2) Non-linearity Potentiometer DNL -0.25 ±0.125 +0.25 LSb 2.7V ≤ V ≤ 5.5V DD Differential Non- MCP40D18 device only (Note2) linearity Bandwidth -3dB BW — 2 — MHz 5kΩ Code = 3Fh (See Figure2-83, — 1 — MHz 10kΩ Code = 3Fh load = 30pF) — 260 — kHz 50kΩ Code = 3Fh — 100 — kHz 100kΩ Code = 3Fh Note 1: Resistance is defined as the resistance between terminal A to terminal B. 2: INL and DNL are measured at V with V = V and V = V . W A DD B SS 3: MCP40D18 device only, includes V and V . WZSE WFSE 4: Resistor terminals A, W and B’s polarity with respect to each other is not restricted. 5: This specification by design. 6: Non-linearity is affected by wiper resistance (R ), which changes significantly over voltage and W temperature. 7: POR/BOR is not rate dependent. 8: Supply current is independent of current through the resistor network DS22152B-page 6 © 2009 Microchip Technology Inc.

MCP40D17/18/19 AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C ≤ T ≤ +125°C (extended) A DC Characteristics All parameters apply across the specified operating ranges unless noted. V = +2.7V to 5.5V, 5kΩ, 10kΩ, 50kΩ, 100kΩ devices. DD Typical specifications represent values for V = 5.5V, T = +25°C. DD A Parameters Sym Min Typ Max Units Conditions Rheostat Integral R-INL -2.0 ±0.5 +2.0 LSb 5kΩ 5.5V, I = 900µA W Non-linearity -5.0 +3.5 +5.0 LSb 2.7V, I = 430µA (Note6) W MCP40D18 See Section2.0 LSb 1.8V (Note6) (Note3) MCP40D17 and -2.0 ±0.5 +2.0 LSb 10kΩ 5.5V, IW = 450µA MCP40D19 -4.0 +2.5 +4.0 LSb 2.7V, I = 215µA (Note6) W devices only See Section2.0 LSb 1.8V (Note6) (Note3) -1.125 ±0.5 +1.125 LSb 50kΩ 5.5V, I = 90µA W -1.5 +1 +1.5 LSb 2.7V, I = 43µA (Note6) W See Section2.0 LSb 1.8V (Note6) -0.8 ±0.5 +0.8 LSb 100kΩ 5.5V, I = 45µA W -1.125 +0.25 +1.125 LSb 2.7V, I = 21.5µA (Note6) W See Section2.0 LSb 1.8V (Note6) Rheostat R-DNL -0.5 ±0.25 +0.5 LSb 5kΩ 5.5V, I = 900mA W Differential -0.75 +0.5 +0.75 LSb 2.7V, I = 430µA (Note6) W Non-linearity See Section2.0 LSb 1.8V (Note6) MCP40D18 (Note3) -0.5 ±0.25 +0.5 LSb 10kΩ 5.5V, IW = 450µA MCP40D17 and -0.75 +0.5 +0.75 LSb 2.7V, I = 215µA (Note6) W MCP40D19 See Section2.0 LSb 1.8V (Note6) devices only (Note3) -0.375 ±0.25 +0.375 LSb 50kΩ 5.5V, IW = 90µA -0.375 ±0.25 +0.375 LSb 2.7V, I = 43µA (Note6) W See Section2.0 LSb 1.8V (Note6) -0.375 ±0.25 +0.375 LSb 100kΩ 5.5V, I = 45µA W -0.375 ±0.25 +0.375 LSb 2.7V, I = 21.5µA (Note6) W See Section2.0 LSb 1.8V (Note6) Capacitance (P ) C — 75 — pF f =1MHz, Code = Full Scale A AW Capacitance (P ) C — 120 — pF f =1MHz, Code = Full Scale w W Capacitance (P ) C — 75 — pF f =1MHz, Code = Full Scale B BW Note 1: Resistance is defined as the resistance between terminal A to terminal B. 2: INL and DNL are measured at V with V = V and V = V . W A DD B SS 3: MCP40D18 device only, includes V and V . WZSE WFSE 4: Resistor terminals A, W and B’s polarity with respect to each other is not restricted. 5: This specification by design. 6: Non-linearity is affected by wiper resistance (R ), which changes significantly over voltage and W temperature. 7: POR/BOR is not rate dependent. 8: Supply current is independent of current through the resistor network © 2009 Microchip Technology Inc. DS22152B-page 7

MCP40D17/18/19 AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C ≤ T ≤ +125°C (extended) A DC Characteristics All parameters apply across the specified operating ranges unless noted. V = +2.7V to 5.5V, 5kΩ, 10kΩ, 50kΩ, 100kΩ devices. DD Typical specifications represent values for V = 5.5V, T = +25°C. DD A Parameters Sym Min Typ Max Units Conditions Digital Inputs/Outputs (SDA, SCK) Schmitt Trigger V 0.7V — — V 1.8V ≤ V ≤ 5.5V IH DD DD High Input Threshold Schmitt Trigger V -0.5 — 0.3V V IL DD Low Input Threshold Hysteresis of V — 0.1V — V All inputs except SDA and SCL HYS DD Schmitt Trigger N.A. — — V V < 2.0V DD Inputs (Note5) SDA 100kHz N.A. — — V V ≥ 2.0V DD and 0.1V — — V V < 2.0V DD SCL DD 400kHz 0.05V — — V V ≥ 2.0V DD DD Output Low V V — 0.2V V V < 2.0V, I = 1mA OL SS DD DD OL Voltage (SDA) V — 0.4 V V ≥ 2.0V, I = 3mA SS DD OL Input Leakage I -1 — 1 µA V = V and V = V IL IN DD IN SS Current Pin Capacitance C , C — 10 — pF f = 400kHz IN OUT C RAM (Wiper) Value Value Range N 0h — 7Fh hex Wiper POR/BOR N 3Fh hex POR/BOR Value Power Requirements Power Supply PSS — 0.0005 0.0035 %/% V = 2.7V to 5.5V, DD Sensitivity V = 2.7V, Code = 3Fh A (MCP40D18 only) Note 1: Resistance is defined as the resistance between terminal A to terminal B. 2: INL and DNL are measured at V with V = V and V = V . W A DD B SS 3: MCP40D18 device only, includes V and V . WZSE WFSE 4: Resistor terminals A, W and B’s polarity with respect to each other is not restricted. 5: This specification by design. 6: Non-linearity is affected by wiper resistance (R ), which changes significantly over voltage and W temperature. 7: POR/BOR is not rate dependent. 8: Supply current is independent of current through the resistor network DS22152B-page 8 © 2009 Microchip Technology Inc.

MCP40D17/18/19 1.1 I2C Mode Timing Waveforms and Requirements SCL 91 93 90 92 SDA START STOP Condition Condition FIGURE 1-1: I2C Bus Start/Stop Bits Timing Waveforms. TABLE 1-1: I2C BUS START/STOP BITS REQUIREMENTS I2C AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C ≤ TA ≤ +125°C (Extended) Operating Voltage V range is described in Section2.0 “Typical DD Performance Curves” Param. Symbol Characteristic Min Max Units Conditions No. F Standard Mode 0 100 kHz C = 400pF, 1.8V - 5.5V SCL b Fast Mode 0 400 kHz C = 400pF, 2.7V - 5.5V b D102 Cb Bus capacitive 100kHz mode — 400 pF loading 400kHz mode — 400 pF 90 TSU:STA START condition 100kHz mode 4700 — ns Only relevant for repeated Setup time 400kHz mode 600 — ns START condition 91 THD:STA START condition 100kHz mode 4000 — ns After this period the first Hold time 400kHz mode 600 — ns clock pulse is generated 92 TSU:STO STOP condition 100kHz mode 4000 — ns Setup time 400kHz mode 600 — ns 93 THD:STO STOP condition 100kHz mode 4000 — ns Hold time 400kHz mode 600 — ns 103 100 102 101 SCL 90 106 91 107 92 SDA In 109 109 110 SDA Out Note1: Refer to specification D102 (Cb) for load conditions. FIGURE 1-2: I2C Bus Data Timing. © 2009 Microchip Technology Inc. DS22152B-page 9

MCP40D17/18/19 TABLE 1-2: I2C BUS DATA REQUIREMENTS (SLAVE MODE) I2C AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C ≤ T ≤ +125°C (Extended) A Operating Voltage VDD range is described in AC/DC characteristics Parame- Sym Characteristic Min Max Units Conditions ter No. 100 T Clock high time 100kHz mode 4000 — ns 1.8V-5.5V HIGH 400kHz mode 600 — ns 2.7V-5.5V 101 TLOW Clock low time 100kHz mode 4700 — ns 1.8V-5.5V 400kHz mode 1300 — ns 2.7V-5.5V 102A (5) TRSCL SCL rise time 100kHz mode — 1000 ns Cb is specified to be from 400kHz mode 20 + 0.1Cb 300 ns 10 to 400pF 102B (5) TRSDA SDA rise time 100kHz mode — 1000 ns Cb is specified to be from 400kHz mode 20 + 0.1Cb 300 ns 10 to 400pF 103A (5) TFSCL SCL fall time 100kHz mode — 300 ns Cb is specified to be from 400kHz mode 20 + 0.1Cb 40 ns 10 to 400pF 103B (5) TFSDA SDA fall time 100kHz mode — 300 ns Cb is specified to be from 400kHz mode 20 + 0.1Cb 300 ns 10 to 400pF (4) 106 THD:DAT Data input hold 100kHz mode 0 — ns 1.8V-5.5V, Note 6 time 400kHz mode 0 — ns 2.7V-5.5V, Note 6 107 TSU:DAT Data input 100kHz mode 250 — ns (2) setup time 400kHz mode 100 — ns 109 TAA Output valid 100kHz mode — 3450 ns (1) from clock 400kHz mode — 900 ns 110 T Bus free time 100kHz mode 4700 — ns Time the bus must be free BUF before a new transmission 400kHz mode 1300 — ns can start T Input filter spike 100kHz mode — 50 ns Philips Spec states N.A. SP suppression 400kHz mode — 50 ns (SDA and SCL) Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 2: A fast-mode (400kHz) I2C-bus device can be used in a standard-mode (100kHz) I2C-bus system, but the requirement tsu; DAT≥250ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line TR max.+tsu;DAT=1000+250=1250ns (according to the standard-mode I2C bus specification) before the SCL line is released. 3: The MCP40D18/MCP40D19 device must provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCL signal. This specification is not a part of the I2C specification, but must be tested in order to guarantee that the output data will meet the setup and hold specifications for the receiving device. 4: Use C in pF for the calculations. b 5: Not Tested. 6: A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do not unintentionally create a Start or Stop condition. DS22152B-page 10 © 2009 Microchip Technology Inc.

MCP40D17/18/19 TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, V =+1.8V to +5.5V, V =GND. DD SS Parameters Sym Min Typ Max Units Conditions Temperature Ranges Specified Temperature Range T -40 — +125 °C A Operating Temperature Range T -40 — +125 °C A Storage Temperature Range T -65 — +150 °C A Thermal Package Resistances Thermal Resistance, 5L-SC70 θ — 331 — °C/W Note1 JA Thermal Resistance, 6L-SC70 θ — 207 — °C/W JA Note 1: Package Power Dissipation (P ) is calculated as follows: DIS P = (T - T ) / θ , DIS J A JA where: T = Junction Temperature, T = Ambient Temperature. J A © 2009 Microchip Technology Inc. DS22152B-page 11

MCP40D17/18/19 NOTES: DS22152B-page 12 © 2009 Microchip Technology Inc.

MCP40D17/18/19 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS 60 2 A) 1.8 50 e (µ 1.6 5.5V v 1.4 A) 40 400 kHz, 5.5V nacti 1.2 (µD 30 ce I 0.81 D a I 1200 400 kHz, 2.7V 10100 k0H kzH, z5,. 52V.7V I InterfDD 000...246 2.7V 0 0 -40 0 40 80 120 -40 0 40 80 120 Temperature (°C) Temperature (°C) FIGURE 2-1: Interface Active Current FIGURE 2-2: Interface Inactive Current (I ) vs. SCL Frequency (f ) and Temperature (I ) vs. Temperature and V . DD SCL SHDN DD (V = 1.8V, 2.7V and 5.5V). (V = 1.8V, 2.7V and 5.5V). DD DD © 2009 Microchip Technology Inc. DS22152B-page 13

MCP40D17/18/19 Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS 120 0.3 120 0.3 -40C Rw 25C Rw 85C Rw 125C Rw -40C Rw 25C Rw 85C Rw 125C Rw -40C INL 25C INL 85C INL 125C INL -40C INL 25C INL 85C INL 125C INL ) W 100 -40C DNL 25C DNL 85C DNL 125C DNL 0.2 ) W 100 -40C DNL 25C DNL 85C DNL 125C DNL 0.2 Wiper Resistance (R(ohms)468000 -I4N0L°C 25°C85°C 125°C DNL RW --0000.1..21Error (LSb) Wiper Resistance (R(ohms)468000 -40°C RW 85°C 2152°5C°C DNL --0000.1..21Error (LSb) INL 20 -0.3 20 -0.3 0 32 64 96 0 32 64 96 Wiper Setting (decimal) Wiper Setting (decimal) FIGURE 2-3: 5.0kΩ : Pot Mode – R (Ω), FIGURE 2-6: 5.0kΩ : Rheo Mode – R W W INL (LSb), DNL (LSb) vs. Wiper Setting and (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (V = 5.5V). (A = V , B = V ). Temperature (V = 5.5V).(I = 1.4mA, B = V ) DD DD SS DD W SS 300 3 300 0.3 -40C Rw 25C Rw 85C Rw 125C Rw -40C Rw 25C Rw 85C Rw 125C Rw -40C INL 25C INL 85C INL 125C INL Wiper Resistance (R) W(ohms)11122048266000000 -40--°44C00CC 82IDN55NL°°LC1252255°CCC IDNNLLDNL8855CC IDNNLL 1122R55CCWI IDNNNLLL --00000..12..21Error (LSb) Wiper Resistance (R) W(ohms)11122048266000000 25°8-C450°CC DN1L25°C25C DNLDNL85C DNL RW12I5NCL DNL 012 Error (LSb) -40°C 20 -0.3 20 -1 0 32 64 96 0 32 64 96 Wiper Setting (decimal) Wiper Setting (decimal) FIGURE 2-4: 5.0kΩ : Pot Mode – R (Ω), FIGURE 2-7: 5.0kΩ : Rheo Mode – R W W INL (LSb), DNL (LSb) vs. Wiper Setting and (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (V = 2.7V). (A = V , B = V ) Temperature (V = 2.7V).(I = 450µA, B = V ) DD DD SS DD W SS 2500 0.35 2500 -40C Rw 25C Rw 85C Rw 125C Rw 44 -40C Rw 25C Rw 85C Rw 125C Rw -40C INL 25C INL 85C INL 125C INL Wiper Resistance (R) W(ohms)112050500000000 --R4400WCC IDNNLL 2255CCIN IDNLNLL 8855CC IDNDNLNLL 112255CC IDNNLL ---000000...012...210555555Error (LSb) Wiper Resistance (R) W(ohms)112050500000000 -40C DNLDNL2R5CW DNL 85C DNLINL125C DNL 9112233494949 Error (LSb) 4 0 -0.35 0 -1 0 32 64 96 0 32 64 96 Wiper Setting (decimal) Wiper Setting (decimal) Note: Refer to AN1080 for additional informa- Note: Refer to AN1080 for additional informa- tion on the characteristics of the wiper tion on the characteristics of the wiper resistance (R ) with respect to device resistance (R ) with respect to device W W voltage and wiper setting value. voltage and wiper setting value. FIGURE 2-5: 5.0kΩ : Pot Mode – R (Ω), FIGURE 2-8: 5.0kΩ : Rheo Mode – R W W INL (LSb), DNL (LSb) vs. Wiper Setting and (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (V = 1.8V). (A = V , B = V ) Temperature (V = 1.8V). (I =260µA, B = V ) DD DD SS DD W SS DS22152B-page 14 © 2009 Microchip Technology Inc.

MCP40D17/18/19 Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS 0.0 200 Sb) -0.2 180 ull-Scale Error (FSE) (L -------1111000.......6420864 1.8V 2.75.5V R Tempco (PPM)BW 11110246246800000000 2.7V 5.5V F -1.8 0 -40 0 40 80 120 0 32 64 96 Ambient Temperature (°C) Wiper Setting (decimal) FIGURE 2-9: 5.0kΩ : Full Scale Error FIGURE 2-12: 5.0kΩ : R Tempco BW (FSE) vs. Temperature (V = 5.5V, 2.7V, 1.8V). ΔR / ΔT vs. Code. DD WB 1.8 b) 1.6 S L E) ( 1.4 S 1.2 Z or ( 1.0 1.8V Err 0.8 2.7 ale 0.6 c S 0.4 o- 5.5V er 0.2 Z 0.0 -40 0 40 80 120 Ambient Temperature (°C) FIGURE 2-10: 5.0kΩ : Zero Scale Error FIGURE 2-13: 5.0kΩ : Power-Up Wiper (ZSE) vs. Temperature (V = 5.5V, 2.7V, 1.8V). Response Time. DD 5200 ) B 5180 RA 5160 e ( 5140 c al Resistan(Ohms) 5555001168020000 2.7V 1.8V WVipDeDr n mi 5040 o N 5020 5.5V 5000 -40 0 40 80 120 Ambient Temperature (°C) FIGURE 2-11: 5.0kΩ : Nominal Resistance FIGURE 2-14: 5.0kΩ : Digital Feedthrough (Ω) vs. Temperature and V . (SCL signal coupling to Wiper pin). DD © 2009 Microchip Technology Inc. DS22152B-page 15

MCP40D17/18/19 Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS FIGURE 2-15: 5.0kΩ : Write Wiper FIGURE 2-18: 5.0kΩ : Write Wiper (40h → 3Fh) Settling Time (V =5.5V). (FFh → 00h) Settling Time (V =5.5V). DD DD FIGURE 2-16: 5.0kΩ : Write Wiper FIGURE 2-19: 5.0kΩ : Write Wiper (40h → 3Fh) Settling Time (V =2.7V). (FFh → 00h) Settling Time (V =2.7V). DD DD FIGURE 2-17: 5.0kΩ : Write Wiper FIGURE 2-20: 5.0kΩ : Write Wiper (40h → 3Fh) Settling Time (V =1.8V). (FFh → 00h) Settling Time (V =1.8V). DD DD DS22152B-page 16 © 2009 Microchip Technology Inc.

MCP40D17/18/19 Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS 120 0.3 120 0.3 -40C Rw 25C Rw 85C Rw 125C Rw -40C Rw 25C Rw 85C Rw 125C Rw -40C INL 25C INL 85C INL 125C INL -40C INL 25C INL 85C INL 125C INL ) W 100 -40C DNL 25C DNL 85C DNL 125C DNL 0.2 ) W 100 -40C DNL 25C DNL 85C DNL 125C DNL 0.2 Wiper Resistance (R(ohms)468000 -40°C DNL 8255°°CC 12IN5°LC RW --0000.1..21Error (LSb) Wiper Resistance (R(ohms)468000 -40°C 8255°°CC 125IN°CL DNL RW --0000.1..21Error (LSb) 20 -0.3 20 -0.3 0 32 64 96 0 32 64 96 Wiper Setting (decimal) Wiper Setting (decimal) FIGURE 2-21: 10kΩ Pot Mode : R (Ω), FIGURE 2-24: 10kΩ Rheo Mode : R (Ω), W W INL (LSb), DNL (LSb) vs. Wiper Setting and INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (V = 5.5V). (A = V , B = V ). Temperature (V = 5.5V).(I = 450µA, B = V ). DD DD SS DD W SS 300 3 300 0.3 -40C Rw 25C Rw 85C Rw 125C Rw -40C Rw 25C Rw 85C Rw 125C Rw -40C INL 25C INL 85C INL 125C INL Wiper Resistance (R) W(ohms)11122048266000000 -40--°44C00CC IDNNL2LI5N°LC2255CC IDNNLLDN8L588°55CC IDNNLL 11122255RCC5W °IDNCNLL --00000..12..21Error (LSb) Wiper Resistance (R) W(ohms)11122048266000000 -402°5C-°4C0C DN8L5°C25C DDNNL1L25°C85C DNINLL 125C DRNWL 012 Error (LSb) 20 -0.3 20 -1 0 32 64 96 0 32 64 96 Wiper Setting (decimal) Wiper Setting (decimal) FIGURE 2-22: 10kΩ Pot Mode : R (Ω), FIGURE 2-25: 10kΩ Rheo Mode : R (Ω), W W INL (LSb), DNL (LSb) vs. Wiper Setting and INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (V = 2.7V). (A = V , B = V ). Temperature (V = 2.7V).(I = 210µA, B = V ). DD DD SS DD W SS 0.35 -40C Rw 25C Rw 85C Rw 125C Rw 39 -40C Rw 25C Rw 85C Rw 125C Rw -40C INL 25C INL 85C INL 125C INL ) W 3000 --4400CC IDNNLL 2255CC IDNNLL 8855CC IDNNLL 112255CC IDNNLL 0.25 ) W 3000 -40C DNL 25C DNL 85C DNL 125C DNL 34 Wiper Resistance (R(ohms)12000000 RW DNL INL ---00000..01...21055555Error (LSb) Wiper Resistance (R(ohms)12000000 RW DNL INL 4911224949 Error (LSb) 0 -0.35 0 -1 0 32 64 96 0 32 64 96 Wiper Setting (decimal) Wiper Setting (decimal) Note: Refer to AN1080 for additional informa- Note: Refer to AN1080 for additional informa- tion on the characteristics of the wiper tion on the characteristics of the wiper resistance (RW) with respect to device resistance (RW) with respect to device voltage and wiper setting value. voltage and wiper setting value. FIGURE 2-23: 10kΩ Pot Mode : R (Ω), FIGURE 2-26: 10kΩ Rheo Mode : R (Ω), W W INL (LSb), DNL (LSb) vs. Wiper Setting and INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (V = 1.8V). (A = V , B = V ). Temperature (V = 1.8V). (I =260µA, B = V ). DD DD SS DD W SS © 2009 Microchip Technology Inc. DS22152B-page 17

MCP40D17/18/19 Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS 0.0 100 b) -0.1 S E) (L --00..32 PM) 80 2.7V S P e Error (F ---000...654 2.7 5.5V Tempco ( 4600 al -0.7 W 5.5V c B ull-S --00..98 1.8V R 20 F -1.0 0 -40 0 40 80 120 0 32 64 96 Ambient Temperature (°C) Wiper Setting (decimal) FIGURE 2-27: 10kΩ : Full Scale Error FIGURE 2-30: 10kΩ : RBW Tempco (FSE) vs. Temperature (VDD = 5.5V, 2.7V, 1.8V). ΔRWB / ΔT vs. Code. 0.9 b) 0.8 S L E) ( 0.7 S 0.6 Z 1.8V or ( 0.5 2.7 Err 0.4 ale 0.3 c S 0.2 5.5V o- er 0.1 Z 0.0 -40 0 40 80 120 Ambient Temperature (°C) FIGURE 2-28: 10kΩ : Zero Scale Error FIGURE 2-31: 10kΩ : Power-Up Wiper (ZSE) vs. Temperature (V = 5.5V, 2.7V, 1.8V). Response Time. DD 10200 ) AB 10150 R nce ( 10100 Wiper esistaOhms) 10050 1.8V VDD al R( 10000 n mi 2.7 o 9950 N 5.5V 9900 -40 0 40 80 120 Ambient Temperature (°C) FIGURE 2-29: 10kΩ : Nominal Resistance FIGURE 2-32: 10kΩ : Digital Feedthrough (Ω) vs. Temperature and V . (SCL signal coupling to Wiper pin). DD DS22152B-page 18 © 2009 Microchip Technology Inc.

MCP40D17/18/19 Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS FIGURE 2-33: 10kΩ : Write Wiper FIGURE 2-36: 10kΩ : Write Wiper (40h → 3Fh) Settling Time (V =5.5V). (FFh → 00h) Settling Time (V =5.5V). DD DD FIGURE 2-34: 10kΩ : Write Wiper FIGURE 2-37: 10kΩ : Write Wiper (40h → 3Fh) Settling Time (V =2.7V). (FFh → 00h) Settling Time (V =2.7V). DD DD FIGURE 2-35: 10kΩ : Write Wiper FIGURE 2-38: 10kΩ : Write Wiper (40h → 3Fh) Settling Time (V =1.8V). (FFh → 00h) Settling Time (V =1.8V). DD DD © 2009 Microchip Technology Inc. DS22152B-page 19

MCP40D17/18/19 Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS 120 0.3 120 0.3 -40C Rw 25C Rw 85C Rw 125C Rw -40C Rw 25C Rw 85C Rw 125C Rw -40C INL 25C INL 85C INL 125C INL -40C INL 25C INL 85C INL 125C INL ) W 100 -40C DNL 25C DNL 85C DNL 125C DNL 0.2 ) W 100 -40C DNL 25C DNL 85C DNL 125C DNL 0.2 Wiper Resistance (R(ohms)468000 -40°C IN8L5°C DN12L5°C25°C RW --0000.1..21Error (LSb) Wiper Resistance (R(ohms)468000 -40°C 2855°°CC DNL125°ICNL RW --0000.1..21Error (LSb) 20 -0.3 20 -0.3 0 32 64 96 0 32 64 96 Wiper Setting (decimal) Wiper Setting (decimal) FIGURE 2-39: 50kΩ Pot Mode : R (Ω), FIGURE 2-42: 50kΩ Rheo Mode : R (Ω), W W INL (LSb), DNL (LSb) vs. Wiper Setting and INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (V = 5.5V). Temperature (V = 5.5V).(I = 90µA, B = V ) DD DD W SS 300 0.3 300 0.3 -40C Rw 25C Rw 85C Rw 125C Rw -40C Rw 25C Rw 85C Rw 125C Rw -40C INL 25C INL 85C INL 125C INL Wiper Resistance (R) W(ohms)11122048266000000 --4400CC IDN2NL5L°C822555°CC IDNNLL DN88L55CC IDNINLNLL 11122255R5CC° WIDCNNLL --00000..12..21Error (LSb) Wiper Resistance (R) W(ohms)11122048266000000 25-°84C05C°C DNL 2152C5 D°NCLDNL85C DNL R1W25CIN DLNL --00000..12..21 Error (LSb) -40°C -40°C 20 -0.3 20 -0.3 0 32 64 96 0 32 64 96 Wiper Setting (decimal) Wiper Setting (decimal) FIGURE 2-40: 50kΩ Pot Mode : R (Ω), FIGURE 2-43: 50kΩ Rheo Mode : R (Ω), W W INL (LSb), DNL (LSb) vs. Wiper Setting and INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (V = 2.7V). Temperature (V = 2.7V).(I = 45µA, B = V ). DD DD W SS 10000 23 10000 0.35 -40C Rw 25C Rw 85C Rw 125C Rw -40C Rw 25C Rw 85C Rw 125C Rw -40C INL 25C INL 85C INL 125C INL 21 R) W 8000 --4400CC DINNLL 2255CC IDNNLL 8855CC IDNNLL 112255CC IDNNLL 0.25 R) W 8000 -40C DNL 25C DNL 85C DNL 125C DNL 1179 Wiper Resistance ((ohms) 246000000000 DINNLL RW ---00000..01...21055555Error (LSb) Wiper Resistance ((ohms) 246000000000 DNL RW INL 3579111135 Error (LSb) 1 0 -0.35 0 -1 0 32 64 96 0 32 64 96 Wiper Setting (decimal) Wiper Setting (decimal) Note: Refer to AN1080 for additional informa- Note: Refer to AN1080 for additional informa- tion on the characteristics of the wiper tion on the characteristics of the wiper resistance (RW) with respect to device resistance (RW) with respect to device voltage and wiper setting value. voltage and wiper setting value. FIGURE 2-41: 50kΩ Pot Mode : R (Ω), FIGURE 2-44: 50kΩ Rheo Mode : R (Ω), W W INL (LSb), DNL (LSb) vs. Wiper Setting and INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (V = 1.8V). Temperature (V = 1.8V). (I =260µA, B = V ). DD DD W SS DS22152B-page 20 © 2009 Microchip Technology Inc.

MCP40D17/18/19 Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS 0.00 100 b) S L ull-Scale Error (FSE) ( ---000...100284 21..78V 5.5V R Tempco (PPM)BW 24680000 2.7V 5.5V F -0.16 0 -40 0 40 80 120 0 32 64 96 Ambient Temperature (°C) Wiper Setting (decimal) FIGURE 2-45: 50kΩ : Full Scale Error FIGURE 2-48: 50kΩ : R Tempco BW (FSE) vs. Temperature (V = 5.5V, 2.7V, 1.8V). ΔR / ΔT vs. Code. DD WB 0.20 b) S E) (L 0.16 S 1.8V or (Z 0.12 Err 0.08 2.7 e al c S 0.04 ero- 5.5V Z 0.00 -40 0 40 80 120 Ambient Temperature (°C) FIGURE 2-46: 50kΩ : Zero Scale Error FIGURE 2-49: 50kΩ : Power-Up Wiper (ZSE) vs. Temperature (V = 5.5V, 2.7V, 1.8V). Response Time. DD 49800 ) B RA 49600 e ( stancms) 49400 Wiper al Resi(Oh 49200 1.8V VDD n mi 49000 2.7V o N 5.5V 48800 -40 0 40 80 120 Ambient Temperature (°C) FIGURE 2-47: 50kΩ : Nominal Resistance FIGURE 2-50: 50kΩ : Digital Feedthrough (Ω) vs. Temperature and V . (SCL signal coupling to Wiper pin). DD © 2009 Microchip Technology Inc. DS22152B-page 21

MCP40D17/18/19 Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS FIGURE 2-51: 50kΩ : Write Wiper FIGURE 2-54: 50kΩ : Write Wiper (40h → 3Fh) Settling Time (V =5.5V). (FFh → 00h) Settling Time (V =5.5V). DD DD FIGURE 2-52: 50kΩ : Write Wiper FIGURE 2-55: 50kΩ : Write Wiper (40h → 3Fh) Settling Time (V =2.7V). (FFh → 00h) Settling Time (V =2.7V). DD DD FIGURE 2-53: 50kΩ : Write Wiper FIGURE 2-56: 50kΩ : Write Wiper (40h → 3Fh) Settling Time (V =1.8V). (FFh → 00h) Settling Time (V =1.8V). DD DD DS22152B-page 22 © 2009 Microchip Technology Inc.

MCP40D17/18/19 Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS 120 0.3 120 0.3 -40C Rw 25C Rw 85C Rw 125C Rw -40C Rw 25C Rw 85C Rw 125C Rw -40C INL 25C INL 85C INL 125C INL -40C INL 25C INL 85C INL 125C INL R) W 100 -40C DNL85°C25C1 D2N5L°C 85DC NDNLL 125C DNL 0.2 R) W 100 -40C DNL85°C25C DNL125°8C5C DNDLNL 125C DNL 0.2 er Resistance ((ohms)6800 INL -000.1.1Error (LSb) er Resistance ((ohms)6800 -000.1.1Error (LSb) Wip 40 -40°C 25°C RW -0.2 Wip 40 -40°C 25°C INL RW -0.2 20 -0.3 20 -0.3 0 32 64 96 0 32 64 96 Wiper Setting (decimal) Wiper Setting (decimal) FIGURE 2-57: 100kΩ Pot Mode : R (Ω), FIGURE 2-60: 100kΩ Rheo Mode : R W W INL (LSb), DNL (LSb) vs. Wiper Setting and (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (V = 5.5V). Temperature (V = 5.5V). (I = 45µA, B = V ). DD DD W SS 300 0.3 300 0.3 -40C Rw 25C Rw 85C Rw 125C Rw -40C Rw 25C Rw 85C Rw 125C Rw -40C INL 25C INL 85C INL 125C INL Wiper Resistance (R) W(ohms)11122048266000000 DN--44L00CC IDNNL2L5°C2255CC8 5IDN°NLL 1288555CC° CIDINNNLLL 1122R55CCW IDNNLL --00000..12..21Error (LSb) Wiper Resistance (R) W(ohms)11122048266000000 -40CIN DLNL25°C25C DNLDN8L5°8C5C DN1L25°CR1W25C DNL --00000..12..21 Error (LSb) -40°C -40°C 20 -0.3 20 -0.3 0 32 64 96 0 32 64 96 Wiper Setting (decimal) Wiper Setting (decimal) FIGURE 2-58: 100kΩ Pot Mode : R (Ω), FIGURE 2-61: 100kΩ Rheo Mode : R W W INL (LSb), DNL (LSb) vs. Wiper Setting and (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (V = 2.7V). Temperature (V = 2.7V). (I = 21µA, B = V ). DD DD W SS 15000 15000 0.35 -40C Rw 25C Rw 85C Rw 125C Rw 19 -40C Rw 25C Rw 85C Rw 125C Rw -40C INL 25C INL 85C INL 125C INL ) W 12500 --4400CC DINNLL 2255CC IDNNLL 8855CC IDNNLL 112255CC IDNNLL 0.25 ) W 12500 -40C DNL 25C DNL 85C DNL 125C DNL 17 Wiper Resistance (R(ohms)10257050500000000 DNL INL ---00000..01...21055555Error (LSb) Wiper Resistance (R(ohms)10257050500000000 DNL RW INL 3579111135 Error (LSb) RW 1 0 -0.35 0 -1 0 32 64 96 0 32 64 96 Wiper Setting (decimal) Wiper Setting (decimal) Note: Refer to AN1080 for additional informa- Note: Refer to AN1080 for additional informa- tion on the characteristics of the wiper tion on the characteristics of the wiper resistance (R ) with respect to device resistance (R ) with respect to device W W voltage and wiper setting value. voltage and wiper setting value. FIGURE 2-59: 100kΩ Pot Mode : R (Ω), FIGURE 2-62: 100kΩ Rheo Mode : R (Ω), W W INL (LSb), DNL (LSb) vs. Wiper Setting and INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (V = 1.8V). Temperature (V = 1.8V). (I =260µA, B = V ). DD DD W SS © 2009 Microchip Technology Inc. DS22152B-page 23

MCP40D17/18/19 Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS 0.00 100 b) S L Full-Scale Error (FSE) ( ---000...000642 1.8V 2.57.5V R Tempco (PPM)BW 24680000 2.7V 5.5V -0.08 0 -40 0 40 80 120 0 32 64 96 Ambient Temperature (°C) Wiper Setting (decimal) FIGURE 2-63: 100kΩ : Full Scale Error FIGURE 2-66: 100kΩ : R Tempco BW (FSE) vs. Temperature (V = 5.5V, 2.7V, 1.8V). ΔR / ΔT vs. Code. DD WB 0.12 b) S L E) ( S 0.08 Z or ( 1.8V Err ale 0.04 2.7 c S o- er 5.5V Z 0.00 -40 0 40 80 120 Ambient Temperature (°C) FIGURE 2-64: 100kΩ : Zero Scale Error FIGURE 2-67: 100kΩ : Power-Up Wiper (ZSE) vs. Temperature (V = 5.5V, 2.7V, 1.8V). Response Time. DD 99800 ) B 99600 RA 99400 e ( 99200 c al Resistan(Ohms) 99998889468000000000 2.7V1.8V WVipDeDr n mi 98200 o N 98000 5.5V 97800 -40 0 40 80 120 Ambient Temperature (°C) FIGURE 2-65: 100kΩ : Nominal FIGURE 2-68: 100kΩ : Digital Resistance (Ω) vs. Temperature and V . Feedthrough (SCL signal coupling to Wiper pin). DD DS22152B-page 24 © 2009 Microchip Technology Inc.

MCP40D17/18/19 Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS FIGURE 2-69: 100kΩ : Write Wiper FIGURE 2-72: 100kΩ : Write Wiper (40h → 3Fh) Settling Time (V = 5.5V). (FFh → 00h) Settling Time (V = 5.5V). DD DD FIGURE 2-70: 100kΩ : Write Wiper FIGURE 2-73: 100kΩ : Write Wiper (40h → 3Fh) Settling Time (V = 2.7V). (FFh → 00h) Settling Time (V = 2.7V). DD DD FIGURE 2-71: 100kΩ : Write Wiper FIGURE 2-74: 100kΩ : Write Wiper (40h → 3Fh) Settling Time (V = 1.8V). (FFh → 00h) Settling Time (V = 1.8V). DD DD © 2009 Microchip Technology Inc. DS22152B-page 25

MCP40D17/18/19 Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS 4 0.3 3.5 5.5V 0.25 3 2.7V (@ 3mA) 0.2 V) 2.5 2.7V mV) V (IH 1.52 V (OL 0.15 5.5V (@ 3mA) 0.1 1 1.8V (@ 1mA) 0.05 0.5 1.8V 0 0 -40 0 40 80 120 -40 0 40 80 120 Temperature (°C) Temperature (°C) FIGURE 2-75: V (SCL, SDA) vs. V and FIGURE 2-77: V (SDA) vs. V and IH DD OL DD Temperature. Temperature. 2 1.2 1 5.5 5.5V 1.5 V 2.7V 0.8 V (V)IL 1 V (V)DD 0.6 2.7V 0.4 0.5 1.8V 0.2 0 0 -40 0 40 80 120 -40 0 40 80 120 Temperature (°C) Temperature (°C) FIGURE 2-76: V (SCL, SDA) vs. V and FIGURE 2-78: POR/BOR Trip point vs. V IL DD DD Temperature. and Temperature. DS22152B-page 26 © 2009 Microchip Technology Inc.

MCP40D17/18/19 Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V. A DD SS 10 10 Code = 7Fh Code = 7Fh 0 0 Code = 3Fh -10 Code = 3Fh -10 Code = 1Fh -20 B -20 B Code = 0Fh d d Code = 0Fh Code = 1Fh -30 -30 Code = 01h Code = 01h -40 -40 -50 -50 -60 100 1,000 10,000 100 1,000 10,000 Frequency (kHz) Frequency (kHz) FIGURE 2-79: 5kΩ – Gain vs. Frequency FIGURE 2-82: 100kΩ – Gain vs. (-3dB). Frequency (-3dB). 2.1 Test Circuits 10 Code = 7Fh 0 Code = 3Fh +5V -10 +5V -20 dB -30 CoCdoed e= =0 10hFh Code = 1Fh VIN A W + VOUT -40 B - -50 -60 100 1,000 10,000 Frequency (kHz) FIGURE 2-80: 10kΩ – Gain vs. Frequency (-3dB). FIGURE 2-83: Gain vs. Frequency Test (-3dB). 10 Code = 7Fh 0 -10 Code = 3Fh -20 Code = 1Fh B d Code = 0Fh -30 Code = 01h -40 -50 -60 100 1,000 10,000 Frequency (kHz) FIGURE 2-81: 50kΩ – Gain vs. Frequency (-3dB). © 2009 Microchip Technology Inc. DS22152B-page 27

MCP40D17/18/19 NOTES: DS22152B-page 28 © 2009 Microchip Technology Inc.

MCP40D17/18/19 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table3-1. Additional descriptions of the device pins follow. TABLE 3-1: PINOUT DESCRIPTION FOR THE MCP40D17/18/19 Pin Number Pin Pin Buffer Function Name MCP40D17 MCP40D18 MCP40D19 Type Type (SC70-6) (SC70-6) (SC70-5) V 1 1 1 P — Positive Power Supply Input DD V 2 2 2 P — Ground SS SCL 3 3 3 I/O ST (OD) I2C Serial Clock pin SDA 4 4 4 I/O ST (OD) I2C Serial Data pin B 5 — — I/O A Potentiometer Terminal B W 6 5 5 I/O A Potentiometer Wiper Terminal A — 6 — I/O A Potentiometer Terminal A Legend: A = Analog input ST (OD) = Schmitt Trigger with Open Drain I = Input O = Output I/O = Input/Output P = Power © 2009 Microchip Technology Inc. DS22152B-page 29

MCP40D17/18/19 3.1 Positive Power Supply Input (V ) 3.6 Potentiometer Wiper (W) Terminal DD The V pin is the device’s positive power supply input. The terminal Wpin is connected to the internal DD The input power supply is relative to V and can range potentiometer’s terminal W(the wiper). The wiper SS from 1.8V to 5.5V. A de-coupling capacitor on V terminal is the adjustable terminal of the digital DD (toV ) is recommended to achieve maximum potentiometer. The terminal Wpin does not have a SS performance. polarity relative to terminals A or B pins. The terminal Wpin can support both positive and negative current. While the device’s voltage is in the range of The voltage on terminal W must be between V and 1.8V≤V <2.7V, the Resistor Network’s electrical SS DD V . performance of the device may not meet the data sheet DD specifications. 3.7 Potentiometer Terminal A 3.2 Ground (V ) SS The terminal Apin (available on some devices) is connected to the internal potentiometer’s terminalA. The V pin is the device ground reference. SS The potentiometer’s terminalA is the fixed connection 3.3 I2C Serial Clock (SCL) to the Full Scale (0x7F tap) wiper value of the digital potentiometer. The SCL pin is the serial clock pin of the I2C interface. The terminal Apin is available on the MCP40D18 The MCP40D17/18/19 acts only as a slave and the devices. The terminal A pin does not have a polarity SCL pin accepts only external serial clocks. The SCL relative to the terminal Wpin. The terminal A pin can pin is an open-drain output. Refer to Section5.0 “Serial Interface - I2C Module” for more details of I2C support both positive and negative current. The voltage on terminalA must be between V and V . Serial Interface communication. SS DD The terminal A pin is not available on the MCP40D17 3.4 I2C Serial Data (SDA) and MCP40D19 devices. For these devices, the potentiometer’s terminal A is internally floating. The SDA pin is the serial data pin of the I2C interface. The SDA pin has a Schmitt trigger input and an open-drain output. Refer to Section5.0 “Serial Interface - I2C Module” for more details of I2C Serial Interface communication. 3.5 Potentiometer Terminal B The terminal B pin (available on some devices) is connected to the internal potentiometer’s terminal B. The potentiometer’s terminal B is the fixed connection to the Zero Scale (0x00 tap) wiper value of the digital potentiometer. The terminal B pin is available on the MCP40D17 device. The terminal Bpin does not have a polarity relative to the terminal Wpin. The terminal Bpin can support both positive and negative current. The voltage on terminal B must be between V and V . SS DD The terminal Bpin is not available on the MCP40D18 and MCP40D19 devices. For these devices, the potentiometer’s terminal B is internally connected to V . SS DS22152B-page 30 © 2009 Microchip Technology Inc.

MCP40D17/18/19 4.0 GENERAL OVERVIEW 4.1.1 POWER-ON RESET When the device powers up, the device V will cross The MCP40D17/18/19 devices are general purpose DD the V /V voltage. Once the V voltage crosses digital potentiometers intended to be used in POR BOR DD the V /V voltage, the following happens: applications where a programmable resistance with POR BOR moderate bandwidth is desired. • Volatile wiper register is loaded with the default wiper value (3Fh) This Data Sheet covers a family of three Digital Potentiometer and Rheostat devices. The MCP40D18 • The device is capable of digital operation device is the Potentiometer configuration, while the 4.1.2 BROWN-OUT RESET MCP40D17 and MCP40D19 devices are the Rheostat configuration. When the device powers down, the device V will DD cross the V /V voltage. Once the V voltage Applications generally suited for the MCP40D17/18/19 POR BOR DD decreases below the V /V voltage the following devices include: POR BOR happens: • Computer Servers • Serial Interface is disabled • Set point or offset trimming If the V voltage decreases below the V voltage • Sensor calibration DD RAM the following happens: • Selectable gain and offset amplifier designs • Volatile wiper registers may become corrupted • Cost-sensitive mechanical trim pot replacement As the voltage recovers above the V /V voltage As the Device Block Diagram shows, there are four POR BOR see Section4.1.1 “Power-on Reset”. main functional blocks. These are: Serial commands not completed due to a Brown-out • POR/BOR Operation • Serial Interface - I2C Module condition may cause the memory location to become corrupted. • Resistor Network The POR/BOR operation and the Memory Map are 4.1.3 WIPER REGISTER (RAM) discussed in this section and the I2C and Resistor The Wiper Register is volatile memory that starts Network operation are described in their own sections. functioning at the RAM retention voltage (V ). The RAM The Serial Commands commands are discussed in Wiper Register will be loaded with the default wiper Section5.4. value when V will rise above the V /V voltage. DD POR BOR 4.1 POR/BOR Operation 4.1.4 DEVICE CURRENTS The Power-on Reset is the case where the device is The current of the device can be classified into two having power applied to it from V . The Brown-out modes of the device operation. These are: SS Reset occurs when a device had power applied to it, • Serial Interface Inactive (Static Operation) and that power (voltage) drops below the specified • Serial Interface Active range. Static Operation occurs when a Stop condition is The devices RAM retention voltage (VRAM) is lower received. Static Operation is exited when a Start than the POR/BOR voltage trip point (V /V ). The POR BOR condition is received. maximum V /V voltage is less than 1.8V. POR BOR When V /V < V < 2.7V, the Resistor Network’s POR BOR DD electrical performance may not meet the data sheet specifications. In this region, the device is capable of reading and writing to its volatile memory if the proper serial command is executed. Table4-1 shows the digital pot’s level of functionality across the entire V range, while Figure4-1 illustrates DD the Power-up and Brown-out functionality. © 2009 Microchip Technology Inc. DS22152B-page 31

MCP40D17/18/19 TABLE 4-1: DEVICE FUNCTIONALITY AT EACH V REGION (NOTE1) DD Serial Potentiometer V Level Wiper Setting Comment DD Interface Terminals V < V < 1.8V Ignored “unknown” Unknown DD BOR V ≤ V < 1.8V “Unknown” Operational with Wiper Register loaded BOR DD reduced electrical with POR/BOR value specs 1.8V ≤ V < 2.7V Accepted Operational with Wiper Register Electrical performance may not DD reduced electrical determines Wiper meet the data sheet specifications. specs Setting 2.7V ≤ V ≤ 5.5V Accepted Operational Wiper Register Meets the data sheet specifications DD determines Wiper Setting Note 1: For system voltages below the minimum operating voltage, the customer will be recommended to use a voltage supervisor to hold the system in reset. This will ensure that MCP4017/18/19 commands are not attempted out of the operating range of the device. Normal Operation Range Normal Operation Range V Outside Specified DD AC/DC Range 2.7V 1.8V V POR/BOR V RAM V SS Analog Analog Characteristics Characteristics not specified not specified Device’s Serial Interface is VBOR Delay “Not Operational” Wiper Forced to Default POR/BOR setting FIGURE 4-1: Power-up and Brown-out. DS22152B-page 32 © 2009 Microchip Technology Inc.

MCP40D17/18/19 5.0 SERIAL INTERFACE - 5.1 I2C I/O Considerations I2C MODULE I2C specifications require active low, passive high A 2-wire I2C serial protocol is used to write or read the functionality on devices interfacing to the bus. Since digital potentiometer’s wiper register. The I2C protocol devices may be operating on separate power supply sources, ESD clamping diodes are not permitted. The utilizes the SCL input pin and SDA input/output pin. specification recommends using open drain transistors The I2C serial interface supports the following features: tied to V (common) with a pull-up resistor. The SS • Slave mode of operation specification makes some general recommendations on the size of this pull-up, but does not specify the • 7-bit addressing exact value since bus speeds and bus capacitance • The following clock rate modes are supported: impacts the pull-up value for optimum system - Standard mode, bit rates up to 100kb/s performance. - Fast mode, bit rates up to 400kb/s Common pull-up values range from 1kΩ to a maximum • Support Multi-Master Applications of ~10kΩ. Power sensitive applications tend to choose The serial clock is generated by the Master. higher values to minimize current losses during The I2C Module is compatible with the Phillips I2C communication but these applications also typically utilize lower V . specification. Philips only defines the field types, field DD lengths, timings, etc. of a frame. The frame content The SDA and SCL float (are not driving) when the defines the behavior of the device. The frame content device is powered down. for the MCP40D17, MCP40D18, and MCP40D19 A "glitch" filter is on the SCL and SDA pins when the pin devices are defined in this section of the data sheet. is an input. When these pins are an output, there is a Figure5-1 shows a typical I2C bus configurations. slew rate control of the pin that is independent of device frequency. Single I2C Bus Configuration 5.1.1 SLOPE CONTROL The device implements slope control on the SDA Device 1 Device 3 Device n output. The slope control is defined by the fast mode Host specifications. Controller For Fast (FS) mode, the device has spike suppression and Schmidt trigger inputs on the SDA and SCL pins. Device 2 Device 4 FIGURE 5-1: Typical Application I2C Bus Configurations. Refer to Section2.0 “Typical Performance Curves”, AC/DC Electrical Characteristics table for detailed input threshold and timing specifications. © 2009 Microchip Technology Inc. DS22152B-page 33

MCP40D17/18/19 5.2 I2C Bit Definitions If the Slave Address is not valid, the Slave Device will issue a Not A (A). The A bit will have the SDA signal I2C bit definitions include: high. • Start Bit If an error condition occurs (such as an A instead of A) • Data Bit then a START bit must be issued to reset the command • Acknowledge (A) Bit state machine. • Repeated Start Bit TABLE 5-1: MCP40D17/18/19 A / A • Stop Bit RESPONSES • Clock Stretching Figure5-8 shows the waveform for these states. Acknowledge Event Comment Bit Response 5.2.1 START BIT General Call A The Start bit (see Figure5-2) indicates the beginning of Slave Address A a data transfer sequence. The Start bit is defined as the valid SDA signal falling when the SCL signal is “High”. Slave Address A not valid SDA 1st Bit 2nd Bit Bus Collision N.A. I2C Module Resets, or a “Don’t Care” if the collision occurs SCL S on the Masters “Start bit”. FIGURE 5-2: Start Bit. 5.2.4 REPEATED START BIT 5.2.2 DATA BIT The Repeated Start bit (see Figure5-5) indicates The SDA signal may change state while the SCL signal thecurrent Master Device wishes to continue is Low. While the SCL signal is High, the SDA signal communicating with the current Slave Device without MUST be stable (see Figure5-3). releasing the I2C bus. The Repeated Start condition is the same as the Start condition, except that the Repeated Start bit follows a Start bit (with the Data bits 1st Bit 2nd Bit +Abit) and not a Stop bit. SDA The Start bit is the beginning of a data transfer SCL sequence and is defined as the SDA signal falling when S the SCL signal is “High”. FIGURE 5-3: Data Bit. Note1: A bus collision during the Repeated Start condition occurs if: 5.2.3 ACKNOWLEDGE (A) BIT • SDA is sampled low when SCL goes The Abit (see Figure5-4) is a response from the Slave from low to high. device to the Master device. Depending on the context • SCL goes low before SDA is of the transfer sequence, the Abit may indicate asserted low. This may indicate that different things. Typically the Slave device will supply another master is attempting to an A response after the Start bit and 8 “data” bits have transmit a data "1". been received. The A bit will have the SDA signal low. SDA D0 A SDA 1st Bit SCL 8 9 FIGURE 5-4: Acknowledge Waveform. SCL Sr = Repeated Start FIGURE 5-5: Repeat Start Condition Waveform. DS22152B-page 34 © 2009 Microchip Technology Inc.

MCP40D17/18/19 5.2.5 STOP BIT 5.2.7 ABORTING A TRANSMISSION The Stop bit (see Figure5-6) Indicates the end of the If any part of the I2C transmission does not meet the I2C Data Transfer Sequence. The Stop bit is defined as command format, it is aborted. This can be intentionally the SDA signal rising when the SCL signal is “High”. accomplished with a START or STOP condition. This is A Stop bit resets the I2C interface of the other devices. done so that noisy transmissions (usually an extra START or STOP condition) are aborted before they corrupt the device. SDA A / A 5.2.8 IGNORING AN I2C TRANSMISSION AND “FALLING OFF” THE BUS SCL The MCP40D17/18/19 expects to receive entire, valid P I2C commands and will assume any command not defined as a valid command is due to a bus corruption FIGURE 5-6: Stop Condition Receive or and will enter a passive high condition on the SDA Transmit Mode. signal. All signals will be ignored until the next valid START condition and CONTROL BYTE are received. 5.2.6 CLOCK STRETCHING “Clock Stretching” is something that the Secondary Device can do, to allow additional time to “respond” to the “data” that has been received. The MCP40D17/18/19 will not strech the clock signal (SCL) since memory read accesses occur fast enough. SDA SCL S 1st 2nd 3rd 4th 5th 6th 7th 8th A/A 1st 2nd 3rd 4th 5th 6th 7th 8th A/A P Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit FIGURE 5-7: Typical 16-bit I2C Waveform Format. SDA SCL START Data allowed Data or STOP Condition to change A valid Condition FIGURE 5-8: I2C Data States and Bit Sequence. © 2009 Microchip Technology Inc. DS22152B-page 35

MCP40D17/18/19 5.2.9 I2C COMMAND PROTOCOL TABLE 5-2: DEVICE I2C ADDRESS The MCP40D17/18/19 is a slave I2C device which Device I2C Address Comment supports 7-bit slave addressing. The slave address MCP40D17 ‘0101110’ contains seven fixed bits. Figure5-9 shows the control ‘0101110’ MCP40D18-xxxE/LT byte format. MCP40D18 ‘0111110’ MCP40D18-xxxAE/LT 5.2.9.1 Control Byte (Slave Address) MCP40D19 ‘0101110’ The Control Byte is always preceded by a START 5.2.9.2 Hardware Address Pins condition. The Control Byte contains the slave address consisting of seven fixed bits and the R/W bit. Figure5- The MCP40D17/MCP40D18/MCP40D19 does not 9shows the control byte format and Table5-2 shows support hardware address bits. the I2C address for the devices. 5.2.10 GENERAL CALL All devices are offered with the I2C slave address of “0101110”, while the MCP40D18 also offers a second The General Call is a method that the Master device standard I2C slave address of “0111110”. can communicate with all other Slave devices. The MCP40D17/18/19 devices do not respond to Slave Address General Call address and commands, and therefore the communications are Not Acknowledged. S A6 A5 A4 A3 A2 A1 A0 R/W A/A “0”“1” “0”“1” “1” “1”“0” Start R/W bit bit R/W = 0 = write R/W = 1 = read A bit (controlled by slave device) A = 0 = Slave Device Acknowledges byte A = 1 = Slave Device does not Acknowledge byte FIGURE 5-9: Slave Address Bits in the I2C Control Byte (Slave Address = “0101110”). Second Byte S 0 0 0 0 0 0 0 0 A X X X X X X X 0 A P General Call Address “7-bit Command” Reserved 7-bit Commands (By I2C Specification - Philips # 9398 393 40011, Ver. 2.1 January 2000) “0000 011”b - Reset and write programmable part of slave address by hardware “0000 010”b - Write programmable part of slave address by hardware “0000 000”b - NOT Allowed The Following is a “Hardware General Call” Format Second Byte n occurrences of (Data + A / A) S 0 0 0 0 0 0 0 0 A X X X X X X X 1 A X X X X X X X X A P General Call Address “7-bit Command” This indicates a “Hardware General Call” MCP40D17/18/19 will ignore this byte and all following bytes (and A), until a Stop bit (P) is encountered. FIGURE 5-10: General Call Formats. DS22152B-page 36 © 2009 Microchip Technology Inc.

MCP40D17/18/19 5.3 Software Reset Sequence The Stop bit terminates the current I2C bus activity. TheMCP40D17/18/19 wait to detect the next Start Note: This technique should be supported by condition. any I2C compliant device. The 24XXXX I2C Serial EEPROM devices support this This sequence does not effect any other I2C devices which may be on the bus, as they should disregard this technique, which is documented in as an invalid command. AN1028. At times it may become necessary to perform a 5.4 Serial Commands Software Reset Sequence to ensure the MCP40D17/ 18/19 device is in a correct and known I2C Interface The MCP40D17/18/19 devices support 2 serial state. This only resets the I2C state machine. commands. These commands are: This is useful if the MCP40D17/18/19 device powers up • Write Operation in an incorrect state (due to excessive bus noise, etc), • Read Operations or if the Master Device is reset during communication. The I2C command formats have been defined so to Figure5-11 shows the communication sequence to support the SMBus version 2.0 Write Byte/Word software reset the device. Protocol formats and Read Byte/Word Protocol formats. The SMBus specification defines this operation is Section 5 of the Version 2.0 document S ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ S P (August 3, 2000). This protocol format may be convienient for customers using library routines for the I2C bus, where all they Nine bits of ‘1’ need to do is specify the command (read, write, ...) with Start bit Start the Device Address, the Register Address, and the bit Stop bit Data. If higher data throughput is desired, please look at the FIGURE 5-11: Software Reset Sequence MCP4017/18/19 devices which have a simplier I2C Format. command format. The 1st Start bit will cause the device to reset from a state in which it is expecting to receive data from the Master Device. In this mode, the device is monitoring the data bus in Receive mode and can detect the Start bit forces an internal Reset. The nine bits of ‘1’ are used to force a Reset of those devices that could not be reset by the previous Start bit. This occurs only if the MCP40D17/18/19 is driving an A on the I2C bus, or is in output mode (from a Read command) and is driving a data bit of ‘0’ onto the I2C bus. In both of these cases, the previous Start bit could not be generated due to the MCP40D17/18/19 holding the bus low. By sending out nine ‘1’ bits, it is ensured that the device will see a A (the Master Device does not drive the I2C bus low to acknowledge the data sent by the MCP40D17/18/19), which also forces the MCP40D17/18/19 to reset. The 2nd Start bit is sent to address the rare possibility of an erroneous write. This could occur if the Master Device was reset while sending a Write command to the MCP40D17/18/19, AND then as the Master Device returns to normal operation and issues a Start condition while the MCP40D17/18/19 is issuing an A. In this case if the 2nd Start bit is not sent (and the Stop bit was sent) the MCP40D17/18/19 could initiate a write cycle. Note: The potential for this erroneous write ONLY occurs if the Master Device is reset while sending a Write command to the MCP40D17/18/19. © 2009 Microchip Technology Inc. DS22152B-page 37

MCP40D17/18/19 5.4.1 WRITE OPERATION 5.4.2 READ OPERATIONS The write operation requires the START condition, The read operation requires the START condition, Control Byte, Acknowledge, Command Code, Control Byte, Acknowledge, Command Code, Acknowledge, Data Byte, Acknowledge and STOP (or Acknowledge, Restart Condition, Control Byte, RESTART) condition. The Control (Slave Address) Acknowledge, Data Byte, the master generating the Byte requires the R/W bit equal to a logic zero (R/W = Aand STOP (or RESTART) condition. The first Control “0”) to generate a write sequence. The MCP40D17/ Byte requires the R/W bit equal to a logic zero (R/W = 18/19 is responsible for generating the Acknowledge “0”) to write the Command Code, while the second (A) bits. Control Byte requires the R/W bit equal to a logic one (R/W = “1”) to generate a read sequence. The Data is written to the MCP40D17/18/19 after every byte MCP40D17/18/19 will A the Slave Address Byte and A transfer (during the A bit). If a STOP or RESTART all the Data Bytes. The I2C Master will A the Slave condition is generated during a data transfer (before Address Byte and the last Data Byte. If there are the A bit), the data will not be written to MCP40D17/18/ multiple Data Bytes, the I2C Master will A all Data Bytes 19. except the last Data Byte (which it will A). Data bytes may be written after each Acknowledge. The MCP40D17/18/19 maintains control of the SDA The command is terminated once a Stop (P) condition signal until all data bits have been clocked out. occurs. Refer to Figure5-12 for the single byte write sequence and Figure5-13 for the generic (multi-byte) The command is terminated once a Stop (P) or Restart (S) condition occurs. Refer to Figure5-15 for the read write sequence. For a single byte write, the master command sequence. For a single read, the master sends a STOP or RESTART condition after the 1st data sends a STOP or RESTART condition after the 1st data byte is sent. byte (and A bit) is sent from the slave. The MSb of each Data Byte is a don’t care, since the wiper register is only 7-bits wide. Figure5-16 shows the I2C read communication behavior of the Master Device and the MCP40D17/18/ The command is terminated once a Stop (P) or Restart 19 device and the resultant I2C bus values. (S) condition occurs. Figure5-14 shows the I2C write communication Note: A command code with a non-zero value behavior of the Master Device and the MCP40D17/18/ will cause the data not to be read from the 19 device and the resultant I2C bus values. wiper register Note: A command code with a non-zero value will cause the data not to be written to the wiper register Fixed Address Read/Write bit (“0” = Write) STOP bit S 0 1 0 1 1 1 0 0 A 0 0 0 0 0 0 0 0 A X D6D5 D4 D3 D2 D1D0 A P Slave Address Byte Command Code Data Byte Legend S = Start Condition P = Stop Condition A = Acknowledge X = Don’t Care R/W = Read/Write bit D6:D0 = Data bits FIGURE 5-12: I2C Single Byte Write Command Format (Slave Address = “0101110”). DS22152B-page 38 © 2009 Microchip Technology Inc.

MCP40D17/18/19 Fixed Read/Write bit (“0” = Write) Address S 0 1 0 1 1 1 1 0 A 0 0 0 0 0 0 0 0 A X D6D5 D4D3 D2 D1D0 A Slave Address Byte Command Code Data Byte STOP bit X D6 D5D4D3D2 D1D0 A X D6 D5D4 D3 D2D1D0 A P Data Byte Data Byte Legend S = Start Condition P = Stop Condition A = Acknowledge X = Don’t Care R/W = Read/Write bit D6:D0 = Data bits FIGURE 5-13: I2C Write Command Format (Slave Address = “0101110”). Write 1 Byte with Command Code = 00h R A A A / C C C S Slave Address W K Command Code K Data Byte K P Master S 0 1 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 1 0 d d d d d d d 1 P MCP40D17/18/19 0 0 0 I2C Bus S 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 d d d d d d d 0 P Write 2 Byte with Command Code = 00h R A A A / C C C S Slave Address WK Command Code K Data Byte K Master S 0 1 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 1 0 d d d d d d d 1 MCP40D17/18/19 0 0 0 I2C Bus S 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 d d d d d d d 0 A C Data Byte K P Master 0 d d d d d d d 1 P MCP40D17/18/19 0 I2C Bus 0 d d d d d d d 0 P FIGURE 5-14: I2C Write Communication Behavior (Slave Address = “0101110”). © 2009 Microchip Technology Inc. DS22152B-page 39

MCP40D17/18/19 Read/Write bit (“0” = Write) S 0 1 0 1 1 1 0 0 A 0 0 0 0 0 0 0 0 A Legend S = Start Condition Slave Address Byte Command Code P = Stop Condition STOP bit A = Acknowledge Read/Write bit (“1” = Read) X = Don’t Care S 0 1 0 1 1 1 0 1 A 0 D6 D5D4D3 D2D1D0 A(2)P R/W = Read/Write bit D6:D0 = Data bits Slave Address Byte Data Byte Note1: Master Device is responsible for ACK / NACK signal. If a NACK signal occurs, the MCP40D17/18/19 will abort this transfer and release the bus. 2: The Master Device will Not ACK, and the MCP40D17/18/19 will release the bus so the Master Device can generate a Stop or Repeated Start condition. FIGURE 5-15: I2C Read Command Format (Slave Address = “0101110”). Read 1 Byte with Command Code = 00h R A A R A / C C R / C S Slave Address WK Command Code K S Slave Address WK Master S 0 1 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 1 S 0 1 0 1 1 1 0 1 1 MCP40D17/18/19 0 0 0 I2C Bus S 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 S 0 1 0 1 1 1 0 1 0 A C Data Byte K P Master 1 P MCP40D17/18/19 0 d d d d d d d 1 I2C Bus 0 d d d d d d d 1 P Read 2 Byte with Command Code = 00h R A A R A / C C R / C S Slave Address WK Command Code K S Slave Address WK Master S 0 1 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 1 S 0 1 0 1 1 1 0 1 1 MCP40D17/18/19 0 0 0 I2C Bus S 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 S 0 1 0 1 1 1 0 1 0 A A C C Data Byte K Data Byte K P Master 0 1 P MCP40D17/18/19 0 d d d d d d d 1 0 d d d d d d d 1 I2C Bus 0 d d d d d d d 0 0 d d d d d d d 1 P FIGURE 5-16: I2C Read Communication Behavior (Slave Address = “0101110”). DS22152B-page 40 © 2009 Microchip Technology Inc.

MCP40D17/18/19 6.0 RESISTOR NETWORK A The Resistor Network is made up of two parts. These N = 127 7Fh are: RW (1) • Resistor Ladder R S • Wiper N = 126 7Eh Figure6-1 shows a block diagram for the resistive network. RS RW (1) Digital potentiometer applications can be divided into N = 125 7Dh two resistor network categories: RW (1) R • Rheostat configuration S • Potentiometer (or voltage divider) configuration The MCP40D17 is a true rheostat, with terminal B and W the wiper (W) of the variable resistor available on pins. N = 1 01h The MCP40D18 device offers a voltage divider (potentiometer) with terminal B internally connected to R RW (1) S ground. N = 0 00h The MCP40D19 device is a Rheostat device with terminal A of the resistor floating, terminal B internally RW (1) B connected to ground, and the wiper (W) available on Analog pin. Mux Note1: The wiper resistance is tap dependent. 6.1 Resistor Ladder Module That is, each tap selection resistance has a small variation. This variation has The resistor ladder is a series of equal value resistors more effect on devices with smaller R (R ) with a connection point (tap) between the two AB S resistance (5.0kΩ). resistors. The total number of resistors in the series(ladder) determines the R resistance AB FIGURE 6-1: Resistor Network Block (seeFigure6-1). The end points of the resistor ladder Diagram. are connected to the device Terminal A and Terminal B pins. The R (and R ) resistance has small variations AB S TABLE 6-1: WIPER SETTING MAP over voltage and temperature. The Resistor Network has 127 resistors in a string Wiper Setting Properties between terminal A and terminal B. This gives 7-bits of 07Fh Full Scale (W = A) resolution. 07Eh - 040h W = N The wiper can be set to tap onto any of these 127 03Fh W = N (Mid Scale) resistors thus providing 128 possible settings 03Eh - 001h W = N (including terminal A and terminal B). This allows zero 000h Zero Scale (W = B) scale to full scale connections. A wiper setting of 00h connects the Terminal W (wiper) to Terminal B (Zero Scale). A wiper setting of 3Fh is the Mid scale setting. A wiper setting of 7Fh connects theTerminal W (wiper) to Terminal A (Full Scale). Table6-1 illustrates the full wiper setting map. Terminal A and B as well as the wiper W do not have a polarity. These terminals can support both positive and negative current. © 2009 Microchip Technology Inc. DS22152B-page 41

MCP40D17/18/19 Step resistance (R ) is the resistance from one tap A POR/BOR event will load the Volatile Wiper register S setting to the next. This value will be dependent on the value with the default value. Table6-3 shows the R value that has been selected. Equation6-1 shows default values offered. AB the calculation for the step resistance while Table6-2 shows the typical step resistances for each device. TABLE 6-3: DEFAULT FACTORY SETTINGS SELECTION EQUATION 6-1: R CALCULATION S Default POR Wiper Resistance Typical R R = ----A----B- Code RAB Value Setting Code (1) S 127 -502 5.0kΩ Mid-scale 3Fh Equation6-2 illustrates the calculation used to -103 10.0kΩ Mid-scale 3Fh determine the resistance between the wiper and -503 50.0kΩ Mid-scale 3Fh terminal B. -104 100.0kΩ Mid-scale 3Fh EQUATION 6-2: R CALCULATION Note 1: Custom POR/BOR Wiper Setting options WB are available, contact the local Microchip R N R = ----A----B------+R Sales Office for additional information. WB 127 W Custom options have minimum volume N = 0 to 127 (decimal) requirements. The digital potentiometer is available in four nominal resistances (R ) where the nominal resistance is AB defined as the resistance between terminal A and terminal B. The four nominal resistances are 5kΩ, 10kΩ, 50kΩ, and 100kΩ. The total resistance of the device has minimal variation due to operating voltage (see Figure2-11, Figure2-29, Figure2-47, or Figure2-65). TABLE 6-2: STEP RESISTANCES Resistance (Ω) Part Number Total Case Step (R ) (R ) S AB Minimum 4000 31.496 MCP40D17/18/19- Typical 5000 39.370 502 Maximum 6000 47.244 Minimum 8000 62.992 MCP40D17/18/19- Typical 10000 78.740 103 Maximum 12000 94.488 Minimum 40000 314.961 MCP40D17/18/19- Typical 50000 393.701 503 Maximum 60000 472.441 Minimum 80000 629.921 MCP40D17/18/19- Typical 100000 787.402 104 Maximum 120000 944.882 DS22152B-page 42 © 2009 Microchip Technology Inc.

MCP40D17/18/19 6.2 Resistor Configurations 6.2.2 POTENTIOMETER CONFIGURATION 6.2.1 RHEOSTAT CONFIGURATION When used as a potentiometer, all three terminals of When used as a rheostat, two of the three digital the device are tied to different nodes in the circuit. This potentiometer’s terminals are used as a resistive allows the potentiometer to output a voltage element in the circuit. With terminal W (wiper) and proportional to the input voltage. This configuration is either terminal A or terminal B, a variable resistor is sometimes called voltage divider mode. The created. The resistance will depend on the tap setting potentiometer is used to provide a variable voltage by of the wiper (and the wiper’s resistance). The adjusting the wiper position between the two endpoints resistance is controlled by changing the wiper setting as shown in Figure6-3. Reversing the polarity of the A The unused terminal (B or A) should be left floating. and B terminals will not affect operation. Figure6-2 shows the two possible resistors that can be used. Reversing the polarity of the A and B terminals V will not affect operation. 1 A V A W 3 B W RAW or RBW V 2 B FIGURE 6-3: Potentiometer Configuration. Resistor The temperature coefficient of the R resistors is AB FIGURE 6-2: Rheostat Configuration. minimal by design. In this configuration, the resistors all change uniformly, so minimal variation should be seen. This allows the control of the total resistance between the two nodes. The total resistance depends on the The Wiper resistor temperature coefficient is different “starting” terminal to the Wiper terminal. So at the code to the RAB temperature coefficient. The voltage at node 00h, the RBW resistance is minimal (RW), but the RAW V3 (Figure6-3) is not dependent on this Wiper resistance in maximized (RAB + RW). Conversely, at the resistance, just the ratio of the RAB resistors, so this code 3Fh, the R resistance is minimal (R ), but the temperature coefficient in most cases can be ignored. AW W R resistance in maximized (R + R ). BW AB W Note: To avoid damage to the internal wiper The resistance Step size (R ) equates to one LSb of S circuitry in this configuration, care should the resistor. be taken to insure the current flow never exceeds 2.5mA. Note: To avoid damage to the internal wiper circuitry in this configuration, care should be taken to insure the current flow never exceeds 2.5mA. The pinout for the rheostat devices is such that as the wiper register is incremented, the resistance of the resistor will increase (as measured from TerminalB to the W Terminal). © 2009 Microchip Technology Inc. DS22152B-page 43

MCP40D17/18/19 6.3 Wiper Resistance In a potentiometer configuration, the wiper resistance variation does not effect the output voltage seen on the Wiper resistance is the series resistance of the analog W pin. switch that connects the selected resistor ladder node The slope of the resistance has a linear area (at the to the Wiper Terminal common signal (see Figure6-1). higher voltages) and a non-linear area (at the lower A value in the volatile wiper register selects which voltages). In where resistance increases faster than the analog switch to close, connecting the W terminal to voltage drop (at low voltages). the selected node of the resistor ladder. The resistance is dependent on the voltages on the analog switch source, gate, and drain nodes, as well as the device’s wiper code, temperature, and the current through the switch. As the device voltage decreases, the wiper resistance increases (see Figure6-4 and R W Table6-4). The wiper can connect directly to TerminalB or to TerminalA. A zero scale connections, connects the TerminalW (wiper) to TerminalB (wiper setting of 000h). A full scale connections, connects the V TerminalW (wiper) to TerminalA (wiper setting of 7Fh). DD In these configurations the only resistance between the Note: The slope of the resistance has a linear TerminalW and the other Terminal (A or B) is thaΩt of area (at the higher voltages) and a non- the analog switches. linear area (at the lower voltages). The wiper resistance is typically measured when the FIGURE 6-4: Relationship of Wiper wiper is positioned at either zero scale (00h) or full Resistance (R ) to Voltage. W scale (3Fh). Since there is minimal variation of the total device The wiper resistance in potentiometer-generated resistance over voltage, at a constant temperature (see voltage divider applications is not a significant source Figure2-11, Figure2-29, Figure2-47, or Figure2-65), of error. the change in wiper resistance over voltage can have a The wiper resistance in rheostat applications can significant impact on the INL and DNL error. create significant nonlinearity as the wiper is moved toward zero scale (00h). The lower the nominal resistance, the greater the possible error. In a rheostat configuration, this change in voltage needs to be taken into account. Particularly for the lower resistance devices. For the 5.0kΩ device the maximum wiper resistance at 5.5V is approximately 3.2% of the total resistance, while at 2.7V it is approximately 6.5% of the total resistance. TABLE 6-4: TYPICAL STEP RESISTANCES AND RELATIONSHIP TO WIPER RESISTANCE Resistance (?) R / R (%) (1) R / R (%) (2) W S W AB Typical Wiper (R ) W R = R = Max R = Max R = R = Max R = Max W W W W W W Total Step Max @ Max @ Typical @ 5.5V @ 2.7V Typical @ 5.5V @ 2.7V Typical (R ) (R ) 5.5V 2.7V AB S 5000 39.37 100 170 325 254.00% 431.80% 825.5% 2.00% 3.40% 6.50% 10000 78.74 100 170 325 127.00% 215.90% 412.75% 1.00% 1.70% 3.25% 50000 393.70 100 170 325 25.40% 43.18% 82.55% 0.20% 0.34% 0.65% 100000 787.40 100 170 325 12.70% 21.59% 41.28% 0.10% 0.17% 0.325% Note 1: R is the typical value. The variation of this resistance is minimal over voltage. S 2: R is the typical value. The variation of this resistance is minimal over voltage. AB DS22152B-page 44 © 2009 Microchip Technology Inc.

MCP40D17/18/19 6.4 Operational Characteristics 6.4.1.2 Differential Non-linearity (DNL) Understanding the operational characteristics of the DNL error is the measure of variations in code widths device’s resistor components is important to the system from the ideal code width. A DNL error of zero would design. imply that every code is exactly 1LSb wide. 6.4.1 ACCURACY 6.4.1.1 Integral Non-linearity (INL) 111 INL error for these devices is the maximum deviation 110 Actual between an actual code transition point and its transfer corresponding ideal transition point after offset and 101 function gain errors have been removed. These endpoints are Digital 100 from 0x00 to 0x7F. Refer to Figure6-5. Input Ideal transfer function Positive INL means higher resistance than ideal. Code 011 Negative INL means lower resistance than ideal. 010 Wide code, > 1 LSb 001 INL < 0 000 111 Narrow code < 1 LSb Actual 110 transfer function Digital Pot Output 101 FIGURE 6-6: DNL Accuracy. Digital 100 Input 6.4.1.3 Ratiometric temperature coefficient Code 011 Ideal transfer The ratiometric temperature coefficient quantifies the function error in the ratio RAW/RWB due to temperature drift. 010 This is typically the critical error when using a potentiometer device (MCP40D18) in a voltage divider 001 configuration. 000 6.4.1.4 Absolute temperature coefficient INL < 0 The absolute temperature coefficient quantifies the Digital Pot Output error in the end-to-end resistance (Nominal resistance R ) due to temperature drift. This is typically the AB FIGURE 6-5: INL Accuracy. critical error when using a rheostat device (MCP40D17 and MCP40D19) in an adjustable resistor configuration. © 2009 Microchip Technology Inc. DS22152B-page 45

MCP40D17/18/19 6.4.2 MONOTONIC OPERATION Monotonic operation means that the device’s resistance increases with every step change (from terminal A to terminal B or terminal B to terminal A). The wiper resistances difference at each tap location. When changing from one tap position to the next (either increasing or decreasing), the ΔR is less than the W ΔR . When this change occurs, the device voltage and S temperature are “the same” for the two tap positions. R S63 0x3F R S62 0x3E e d 0x3D o C ut p n R al I 0x03 S3 git R Di 0x02 S1 R S0 0x01 0x00 R W n = ? (@ tap) R = R + R BW Sn W(@ Tap n) n = 0 Resistance (R ) BW FIGURE 6-7: R . BW DS22152B-page 46 © 2009 Microchip Technology Inc.

MCP40D17/18/19 7.0 DESIGN CONSIDERATIONS 7.2 Layout Considerations In the design of a system with the MCP40D17/18/19 Inductively-coupled AC transients and digital switching devices, the following considerations should be taken noise can degrade the input and output signal integrity, into account. These are: potentially masking the MCP40D17/18/19’s performance. Careful board layout will minimize these • The Power Supply effects and increase the Signal-to-Noise Ratio (SNR). • The Layout Bench testing has shown that a multi-layer board In the design of a system with the MCP40D17/18/19 utilizing a low-inductance ground plane, isolated inputs, devices, the following considerations should be taken isolated outputs and proper decoupling are critical to into account: achieving the performance that the silicon is capable of providing. Particularly harsh environments may require • Power Supply Considerations shielding of critical signals. • Layout Considerations If low noise is desired, breadboards and wire-wrapped 7.1 Power Supply Considerations boards are not recommended. The typical application will require a bypass capacitor 7.2.1 RESISTOR TEMPCO in order to filter high-frequency noise, which can be Characterization curves of the resistor temperature induced onto the power supply's traces. The bypass coefficient (Tempco) are shown in Figure2-11, capacitor helps to minimize the effect of these noise Figure2-29, Figure2-47, and Figure2-65. sources on signal integrity. Figure7-1 illustrates an These curves show that the resistor network is appropriate bypass strategy. designed to correct for the change in resistance as In this example, the recommended bypass capacitor temperature increases. This technique reduces the value is 0.1µF. This capacitor should be placed as end to end change is R resistance. AB close to the device power pin (V ) as possible (within DD 4mm). The power source supplying these devices should be as clean as possible. If the application circuit has separate digital and analog power supplies, V and DD V should reside on the analog plane. SS V DD 0.1µF V DD 0.1µF er oll ntr o 9 c A 18/1 Micro W 17/ SCL ®o D cr 0 mi 4 P C B MC SDA PI V V SS SS FIGURE 7-1: Typical Microcontroller Connections. © 2009 Microchip Technology Inc. DS22152B-page 47

MCP40D17/18/19 NOTES: DS22152B-page 48 © 2009 Microchip Technology Inc.

MCP40D17/18/19 8.0 APPLICATIONS EXAMPLES V Digital potentiometers have a multitude of practical DD uses in modern electronic circuits. The most popular uses include precision calibration of set point R1 thresholds, sensor trimming, LCD bias trimming, audio MCP40D18 A attenuation, adjustable power supplies, motor control overcurrent trip setting, adjustable gain amplifiers and SDA W V offset trimming. The MCP40D17/18/19 devices can be SCL OUT used to replace the common mechanical trim pot in B applications where the operating and terminal voltages are within CMOS process limitations (V = 2.7V to DD 5.5V). FIGURE 8-1: Using the Digital 8.1 Set Point Threshold Trimming Potentiometer to Set a Precise Output Voltage. Applications that need accurate detection of an input 8.1.1 TRIMMING A THRESHOLD FOR AN threshold event often need several sources of error OPTICAL SENSOR eliminated. Use of comparators and operational amplifiers (op amps) with low offset and gain error can If the application has to calibrate the threshold of a help achieve the desired accuracy, but in many diode, transistor or resistor, a variation range of 0.1V is applications, the input source variation is beyond the common. Often, the desired resolution of 2mV or designer’s control. If the entire system can be better is adequate to accurately detect the presence of calibrated after assembly in a controlled environment a precise signal. A “windowed” voltage divider, utilizing (like factory test), these sources of error are minimized the MCP40D18, would be a potential solution. if not entirely eliminated. Figure8-2 illustrates this example application. Figure8-1 illustrates a common digital potentiometer configuration. This configuration is often referred to as V DD a “windowed voltage divider”. Note that R is not 1 necessary to create the voltage divider, but its presence is useful when the desired threshold has limited range. It is “windowed” because R can narrow 1 the adjustable range of V to a value much less than TRIP V V – V . If the output range is reduced, the DD V DD SS CC+ R magnitude of each output step is reduced. This sense effectively increases the trimming resolution for a fixed R1 digital potentiometer resolution. This technique may MCP40D18 A Comparator allow a lower-cost digital potentiometer to be utilized V (64 steps instead of 256 steps). SDA W TRIP SCL MCP6021 The MCP40D18’s low DNL performance is critical to B V meeting calibration accuracy in production without 0.1µF CC- having to use a higher precision digital potentiometer. EQUATION 8-1: CALCULATING THE WIPER SETTING FROM FIGURE 8-2: Set Point or Threshold THE DESIRED V Calibration. TRIP R V = V ⎛---------W----B------⎞ TRIP DD⎝R +R ⎠ 1 2 R = R AB Nominal D R = R • WB AB 127 V D = T R IP • (R + R ) • 127 V 1 AB DD D = Digital Potentiometer Wiper Setting (0-127) © 2009 Microchip Technology Inc. DS22152B-page 49

MCP40D17/18/19 8.2 Operational Amplifier Applications MCP40D18 R 4 B A Figure8-3 and Figure8-4 illustrate typical amplifier circuits that could replace fixed resistors with the W MCP40D17/18/19 to achieve digitally-adjustable analog solutions. VDD ‚ Op Amp R MCP6291 1 V VIN + VIN + OUT MCP6021 V Op Amp A DD W ‚ VOUT B fc = 2----π----⋅----R--1---------⋅---C--- R1 MCP40D18 Eq A R3 W B Thevenin R = (R +R –R )||(R +R )+R MCP40D18 MCP40D17 Equivalent Eq 1 AB WB 2 WB w FIGURE 8-4: Programmable Filter. FIGURE 8-3: Trimming Offset and Gain in a Non-Inverting Amplifier. DS22152B-page 50 © 2009 Microchip Technology Inc.

MCP40D17/18/19 8.3 Temperature Sensor Applications The circuit illustrated by Figure8-6 utilizes a digital potentiometer for trimming the offset error. This Thermistors are resistors with very predictable solution removes R from the trimming equation along W variation with temperature. Thermistors are a popular with the error associated with R . R is not required, W 2 sensor choice when a low-cost temperature-sensing but can be utilized to reduce the trimming “window” and solution is desired. Unfortunately, thermistors have reduce variation due to the digital pot’s R part-to-part AB non-linear characteristics that are undesirable, typically variability. requiring trimming in an application to achieve greater accuracy. There are several common solutions to trim and linearize thermistors. Figure8-5 and Figure8-6 VDD are simple methods for linearizing a 3-terminal NTC thermistor. Both are simple voltage dividers using a Positive Temperature Coefficient (PTC) resistor (R1) R1 with a transfer function capable of compensating for the NTC linearity error in the Negative Temperature Coefficient Thermistor (NTC) thermistor. The circuit, illustrated by Figure8-5, utilizes a digital rheostat for trimming the offset error caused by the thermistor’s part-to-part variation. This solution puts the V digital potentiometer’s R into the voltage divider OUT W MCP40D18 calculation. The MCP40D17/18/19’s R temperature AB coefficient is a low 50ppm (-20°C to +70°C). R ’s error W is substantially greater than R ’s error because R AB W varies with V , wiper setting and temperature. For the DD FIGURE 8-6: Thermistor Calibration using 50kΩ devices, the error introduced by R is, in most W cases, insignificant as long as the wiper setting is > 6. a Digital Potentiometer in a Potentiometer For the 2kΩ devices, the error introduced by R is Configuration. W significant because it is a higher percentage of R . WB For these reasons, the circuit illustrated in Figure8-5 is not the most optimum method for “exciting” and linearizing a thermistor. V DD R 1 NTC Thermistor V OUT R 2 MCP40D17 FIGURE 8-5: Thermistor Calibration using a Digital Potentiometer in a Rheostat Configuration. © 2009 Microchip Technology Inc. DS22152B-page 51

MCP40D17/18/19 8.4 Wheatstone Bridge Trimming Another common configuration to “excite” a sensor (such as a strain gauge, pressure sensor or thermistor) is the wheatstone bridge configuration. The wheatstone bridge provides a differential output instead of a single-ended output. Figure8-7 illustrates a wheatstone bridge utilizing one to three digital potentiometers. The digital potentiometers in this example are used to trim the offset and gain of the wheatstone bridge. V DD 5kΩ MCP40D17 V OUT MCP40D17 MCP40D17 50kΩ 50kΩ FIGURE 8-7: Wheatstone Bridge Trimming. DS22152B-page 52 © 2009 Microchip Technology Inc.

MCP40D17/18/19 9.0 DEVELOPMENT SUPPORT 9.2 Technical Documentation Several additional technical documents are available to 9.1 Development Tools assist you in your design and development. These technical documents include Application Notes, The MCP40D17/18/19 devices can be evaluated with Technical Briefs, and Design Guides. Table9-1 shows the MCP4XXXDM-PGA board, but it will require the some of these documents. removal of the MCP4017 device and the installation of the MCP40D17 device. Please check the Microchip web site for the release of this board. The board part number is tentatively MCP4XXXDM-PGA, and is expected to be available in the fall of 2009. Note: The MCP40D17 device is identical to the MCP4017 device with the exception of the I2C interface protocol format. TABLE 9-1: TECHNICAL DOCUMENTATION Application Title Literature # Note Number AN1080 Understanding Digital Potentiometers Resistor Variations DS01080 AN737 Using Digital Potentiometers to Design Low-Pass Adjustable Filters DS00737 AN692 Using a Digital Potentiometer to Optimize a Precision Single Supply Photo Detect DS00692 AN691 Optimizing the Digital Potentiometer in Precision Circuits DS00691 AN219 Comparing Digital Potentiometers to Mechanical Potentiometers DS00219 — Digital Potentiometer Design Guide DS22017 — Signal Chain Design Guide DS21825 © 2009 Microchip Technology Inc. DS22152B-page 53

MCP40D17/18/19 NOTES: DS22152B-page 54 © 2009 Microchip Technology Inc.

MCP40D17/18/19 10.0 PACKAGING INFORMATION 10.1 Package Marking Information 5-Lead SC70 Example: Part Number Code MCP40D19T-502E/LT BTNN XXNN ATNN MCP40D19T-103E/LT BUNN MCP40D19T-503E/LT BVNN 1 1 MCP40D19T-104E/LT BWNN 6-Lead SC70 Example: Part Number Code Part Number Code MCP40D17T-502E/LT AJNN MCP40D18T-502E/LT APNN XXNN AJNN MCP40D17T-103E/LT AKNN MCP40D18T-502AE/LT ATNN MCP40D17T-503E/LT ALNN MCP40D18T-103E/LT AQNN 1 1 MCP40D17T-104E/LT AMNN MCP40D18T-103AE/LT AUNN MCP40D18T-503E/LT ARNN MCP40D18T-503AE/LT AVNN MCP40D18T-104E/LT ASNN MCP40D18T-104AE/LT AWNN Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2009 Microchip Technology Inc. DS22152B-page 55

MCP40D17/18/19 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:10)(cid:8)(cid:17)(cid:18)(cid:12)(cid:10)(cid:13)(cid:19)(cid:5)(cid:8)(cid:20)(cid:21)(cid:6)(cid:19)(cid:11)(cid:13)(cid:11)(cid:12)(cid:22)(cid:21)(cid:8)(cid:23)(cid:4)(cid:20)(cid:24)(cid:8)(cid:25)(cid:15)(cid:26)(cid:27)(cid:28)(cid:29) (cid:30)(cid:22)(cid:12)(cid:5)(cid:31) .(cid:10)(cid:9)(cid:2)#(cid:11)(cid:14)(cid:2)(cid:31)(cid:10) #(cid:2)(cid:8)$(cid:9)(cid:9)(cid:14)(cid:15)#(cid:2)(cid:12)(cid:28)(cid:8)/(cid:28)(cid:17)(cid:14)(cid:2)!(cid:9)(cid:28)-(cid:7)(cid:15)(cid:17) 0(cid:2)(cid:12)(cid:16)(cid:14)(cid:28) (cid:14)(cid:2) (cid:14)(cid:14)(cid:2)#(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)1(cid:28)(cid:8)/(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)#(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)#(cid:14)!(cid:2)(cid:28)#(cid:2) (cid:11)##(cid:12)+22---(cid:20)(cid:31)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)(cid:31)2(cid:12)(cid:28)(cid:8)/(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D b 3 2 1 E1 E 4 5 e e A A2 c A1 L 3(cid:15)(cid:7)# (cid:6)(cid:19)44(cid:19)(cid:6)"(cid:13)"(cid:26)(cid:22) (cid:21)(cid:7)(cid:31)(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:2)4(cid:7)(cid:31)(cid:7)# (cid:6)(cid:19)5 56(cid:6) (cid:6)(cid:25)7 5$(cid:31)8(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)1(cid:7)(cid:15) 5 ( 1(cid:7)#(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)9((cid:2))(cid:22)* 6,(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2):(cid:14)(cid:7)(cid:17)(cid:11)# (cid:25) (cid:4)(cid:20);(cid:4) < (cid:30)(cid:20)(cid:30)(cid:4) (cid:6)(cid:10)(cid:16)!(cid:14)!(cid:2)1(cid:28)(cid:8)/(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)/(cid:15)(cid:14) (cid:25)(cid:3) (cid:4)(cid:20);(cid:4) < (cid:30)(cid:20)(cid:4)(cid:4) (cid:22)#(cid:28)(cid:15)!(cid:10)%% (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:4) < (cid:4)(cid:20)(cid:30)(cid:4) 6,(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)=(cid:7)!#(cid:11) " (cid:30)(cid:20);(cid:4) (cid:3)(cid:20)(cid:30)(cid:4) (cid:3)(cid:20)(cid:23)(cid:4) (cid:6)(cid:10)(cid:16)!(cid:14)!(cid:2)1(cid:28)(cid:8)/(cid:28)(cid:17)(cid:14)(cid:2)=(cid:7)!#(cid:11) "(cid:30) (cid:30)(cid:20)(cid:30)( (cid:30)(cid:20)(cid:3)( (cid:30)(cid:20)(cid:29)( 6,(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)4(cid:14)(cid:15)(cid:17)#(cid:11) (cid:21) (cid:30)(cid:20);(cid:4) (cid:3)(cid:20)(cid:4)(cid:4) (cid:3)(cid:20)(cid:3)( .(cid:10)(cid:10)#(cid:2)4(cid:14)(cid:15)(cid:17)#(cid:11) 4 (cid:4)(cid:20)(cid:30)(cid:4) (cid:4)(cid:20)(cid:3)(cid:4) (cid:4)(cid:20)(cid:23)9 4(cid:14)(cid:28)!(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)/(cid:15)(cid:14) (cid:8) (cid:4)(cid:20)(cid:4); < (cid:4)(cid:20)(cid:3)9 4(cid:14)(cid:28)!(cid:2)=(cid:7)!#(cid:11) 8 (cid:4)(cid:20)(cid:30)( < (cid:4)(cid:20)(cid:23)(cid:4) (cid:30)(cid:22)(cid:12)(cid:5)(cid:11)(cid:31) (cid:30)(cid:20) (cid:21)(cid:7)(cid:31)(cid:14)(cid:15) (cid:7)(cid:10)(cid:15) (cid:2)(cid:21)(cid:2)(cid:28)(cid:15)!(cid:2)"(cid:30)(cid:2)!(cid:10)(cid:2)(cid:15)(cid:10)#(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)$!(cid:14)(cid:2)(cid:31)(cid:10)(cid:16)!(cid:2)%(cid:16)(cid:28) (cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)#(cid:9)$ (cid:7)(cid:10)(cid:15) (cid:20)(cid:2)(cid:6)(cid:10)(cid:16)!(cid:2)%(cid:16)(cid:28) (cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)#(cid:9)$ (cid:7)(cid:10)(cid:15) (cid:2) (cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)#(cid:2)(cid:14)&(cid:8)(cid:14)(cid:14)!(cid:2)(cid:4)(cid:20)(cid:30)(cid:3)(cid:5)(cid:2)(cid:31)(cid:31)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2) (cid:7)!(cid:14)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7)(cid:31)(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)!(cid:2)#(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6)"(cid:2)’(cid:30)(cid:23)(cid:20)((cid:6)(cid:20) )(cid:22)*+ )(cid:28) (cid:7)(cid:8)(cid:2)(cid:21)(cid:7)(cid:31)(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)#(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)&(cid:28)(cid:8)#(cid:2),(cid:28)(cid:16)$(cid:14)(cid:2) (cid:11)(cid:10)-(cid:15)(cid:2)-(cid:7)#(cid:11)(cid:10)$#(cid:2)#(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14) (cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)-(cid:7)(cid:15)(cid:17)*(cid:4)(cid:23)(cid:27)(cid:4)9(cid:30)) DS22152B-page 56 © 2009 Microchip Technology Inc.

MCP40D17/18/19 (cid:30)(cid:22)(cid:12)(cid:5)(cid:31) .(cid:10)(cid:9)(cid:2)#(cid:11)(cid:14)(cid:2)(cid:31)(cid:10) #(cid:2)(cid:8)$(cid:9)(cid:9)(cid:14)(cid:15)#(cid:2)(cid:12)(cid:28)(cid:8)/(cid:28)(cid:17)(cid:14)(cid:2)!(cid:9)(cid:28)-(cid:7)(cid:15)(cid:17) 0(cid:2)(cid:12)(cid:16)(cid:14)(cid:28) (cid:14)(cid:2) (cid:14)(cid:14)(cid:2)#(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)1(cid:28)(cid:8)/(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)#(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)#(cid:14)!(cid:2)(cid:28)#(cid:2) (cid:11)##(cid:12)+22---(cid:20)(cid:31)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)(cid:31)2(cid:12)(cid:28)(cid:8)/(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) © 2009 Microchip Technology Inc. DS22152B-page 57

MCP40D17/18/19 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22152B-page 58 © 2009 Microchip Technology Inc.

MCP40D17/18/19 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2009 Microchip Technology Inc. DS22152B-page 59

MCP40D17/18/19 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22152B-page 60 © 2009 Microchip Technology Inc.

MCP40D17/18/19 APPENDIX A: REVISION HISTORY Revision B (August 2009) the following is the List of Modifications: 1. Document updated to include the new standard I2C slave address (“0111110“) for the MCP40D18 device. 2. Section10.0 “Packaging Information”: Cor- rected the Marking codes for 5-lead SC70 Codes shown were for the 6-lead SC70. Updated Package Outline Drawings. Revision A (May 2009) • Original Release of this Document. © 2009 Microchip Technology Inc. DS22152B-page 61

MCP40D17/18/19 NOTES: DS22152B-page 62 © 2009 Microchip Technology Inc.

MCP40D17/18/19 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. XXX X X /XX Examples: Device Resistance I2C Device Temperature Package a) MCP40D17T-502E/LT: 5kΩ, Version Address Range 6-LD SC70 b) MCP40D17T-103E/LT: 10kΩ, Device: MCP40D17: Single Rheostat with I2C interface 6-LD SC70 MCP40D17T:Single Rheostat with I2C interface c) MCP40D17T-503E/LT: 50kΩ, 6-LD SC70 (Tape and Reel) d) MCP40D17T-104E/LT: 100kΩ, MCP40D18: Single Potentiometer to GND with I2C Interface 6-LD SC70 MCP40D18T:Single Potentiometer to GND with a) MCP40D18T-502E/LT: 5kΩ, I2C Interface (Tape and Reel) 6-LD SC70 MCP40D19: Single Rheostat to GND with b) MCP40D18T-103E/LT: 10kΩ, I2C Interface 6-LD SC70 MCP40D19T:Single Rheostat to GND with c) MCP40D18T-503E/LT: 50kΩ, I2C Interface (Tape and Reel) 6-LD SC70 d) MCP40D18T-104E/LT: 100kΩ, Resistance 502 = 5kΩ 6-LD SC70 Version: 103 = 10kΩ a) MCP40D18T-502AE/LT: 5kΩ, 503 = 50kΩ 6-LD SC70 104 = 100kΩ b) MCP40D18T-103AE/LT: 10kΩ, 6-LD SC70 I2C Device blank= ‘0101110’ c) MCP40D18T-503AE/LT: 50kΩ, Address A = ‘0111110’ (1) 6-LD SC70 Version: d) MCP40D18T-104AE/LT: 100kΩ, 6-LD SC70 Temperature E = -40°C to +125°C a) MCP40D19T-502E/LT: 5kΩ, Range: 5-LD SC70 b) MCP40D19T-103E/LT: 10kΩ, 5-LD SC70 Package: LT = Plastic Small Outline Transistor (SC70), c) MCP40D19T-503E/LT: 50kΩ, 5-lead, 6-lead 5-LD SC70 Note 1: This address is a standard option on the MCP40D18 d) MCP40D19T-104E/LT: 100kΩ, device only. It is a custom device on the MCP40D17 5-LD SC70 and MCP40D19 devices. © 2009 Microchip Technology Inc. DS22152B-page 63

MCP40D17/18/19 NOTES: DS22152B-page 64 © 2009 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. rfPIC and UNI/O are registered trademarks of Microchip MICROCHIP MAKES NO REPRESENTATIONS OR Technology Incorporated in the U.S.A. and other countries. WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, OTHERWISE, RELATED TO THE INFORMATION, MXDEV, MXLAB, SEEVAL and The Embedded Control INCLUDING BUT NOT LIMITED TO ITS CONDITION, Solutions Company are registered trademarks of Microchip QUALITY, PERFORMANCE, MERCHANTABILITY OR Technology Incorporated in the U.S.A. FITNESS FOR PURPOSE. Microchip disclaims all liability Analog-for-the-Digital Age, Application Maestro, CodeGuard, arising from this information and its use. Use of Microchip dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, devices in life support and/or safety applications is entirely at ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial the buyer’s risk, and the buyer agrees to defend, indemnify and Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified hold harmless Microchip from any and all damages, claims, logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code suits, or expenses resulting from such use. No licenses are Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, conveyed, implicitly or otherwise, under any Microchip PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total intellectual property rights. Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2009 Microchip Technology Inc. DS22152B-page 65

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