MCP3550/1/3 Low-Power, Single-Channel 22-Bit Delta-Sigma ADCs Features Description • 22-bit ADC in Small 8-pin MSOP Package with The Microchip Technology Inc. MCP3550/1/3 devices Automatic Internal Offset and Gain Calibration are 2.7V to 5.5V low-power, 22-bit Delta-Sigma Ana- (cid:129) Low-Output Noise of 2.5µV with Effective log-to-Digital Converters (ADCs). The devices offer RMS Resolution of 21.9 bits (MCP3550/1) output noise as low as 2.5µVRMS, with a total unadjusted error of 10ppm. The family exhibits 6ppm (cid:129) 3µV Typical Offset Error Integral Non-Linearity (INL) error, 3µV offset error and (cid:129) 2ppm Typical Full-Scale Error less than 2ppm full-scale error. The MCP3550/1/3 (cid:129) 6ppm Maximum INL Error devices provide high accuracy and low noise (cid:129) Total Unadjusted Error Less Than 10ppm performance for applications where sensor (cid:129) No Digital Filter Settling Time, Single-Command measurements (such as pressure, temperature and Conversions through 3-wire SPI Interface humidity) are performed. With the internal oscillator (cid:129) Ultra-Low Conversion Current (MCP3550/1): and high oversampling rate, minimal external components are required for high-accuracy - 100µA typical (V = 2.7V) DD applications. - 120µA typical (V = 5.0V) DD This product line has fully differential analog inputs, (cid:129) Differential Input with V to V Common Mode SS DD making it compatible with a wide variety of sensor, Range industrial control or process control applications. (cid:129) 2.7V to 5.5V Single-Supply Operation The MCP3550/1/3 devices operate from -40°C to (cid:129) Extended Temperature Range: +125°C and are available in the space-saving 8-pin - -40°C to +125°C MSOP and SOIC packages. Applications Package Types: (cid:129) Weigh Scales MCP3550/1/3 (cid:129) Direct Temperature Measurement SOIC, MSOP (cid:129) 6-digit DVMs (cid:129) Instrumentation VREF 1 8 VDD (cid:129) Data Acquisition V + 2 7 CS IN (cid:129) Strain Gauge Measurement V – 3 6 SDO/RDY IN Block Diagram VSS 4 5 SCK VREF VSSVDD Device Selection Table Sample Effective 50/60Hz VVININ+- 3DMwCr/aSod Il d-inAbOutrDelraadrCtnteioo arrnl 4SINC al Interface SSRCDDKOY MMPaCCrPPt 33N55u55m00--b56e00r 112R5.5astspepss R22e11s..o99l ubbtiiittossn Re56j00ecHHtizzo n eri CS MCP3551 13.75sps 21.9 bits 50/60Hz S Internal VDD (simultaneous) Oscillator MCP3553 60sps 20.6 bits N/A POR © 2007 Microchip Technology Inc. DS21950D-page 1

MCP3550/1/3 1.0 ELECTRICAL † Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is CHARACTERISTICS a stress rating only and functional operation of the device at those or any other conditions above those indicated in the 1.1 Maximum Ratings* operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect V ...................................................................................7.0V DD device reliability. All inputs and outputs w.r.t V .............. -0.3V to V + 0.3V SS DD Difference Input Voltage .......................................|V - V | DD SS Output Short Circuit Current .................................Continuous Current at Input Pins ....................................................±2mA Current at Output and Supply Pins ............................±10mA Storage Temperature.....................................-65°C to +150°C Ambient temp. with power applied................-55°C to +125°C ESD protection on all pins (HBM, MM) ............≥ 6kV, ≥ 400V Maximum Junction Temperature (T )..........................+150°C J DC CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, all parameters apply at -40°C ≤ T ≤ +85°C, V = 2.7V or 5.0V. A DD V = 2.5V. V + = V - = V = V /2. All ppm units use 2*V as full-scale range. Unless otherwise noted, specification REF IN IN CM REF REF applies to entire MCP3550/1/3 family. Parameters Sym Min Typ Max Units Conditions Noise Performance (MCP3550/1) No Missing Codes NMC 22 — — bits At DC (Note5) Output Noise e — 2.5 — µV N RMS Effective Resolution ER — 21.9 — bits RMS V = 5V REF Noise Performance (MCP3553) No Missing Codes NMC 20 — — bits At DC (Note5) Output Noise e — 6 — µV N RMS Effective Resolution ER — 20.6 — bits RMS V = 5V REF Conversion Times MCP3550-50 t -1.0% 80 +1.0% ms CONV MCP3550-60 t -1.0% 66.67 +1.0% ms CONV MCP3551 t -1.0% 72.73 +1.0% ms CONV MCP3553 t -1.0% 16.67 +1.0% ms CONV Accuracy Integral Non-Linearity INL — ±2 6 ppm T = +25°C only (Note2) A Offset Error V -12 ±3 +12 µV T = +25°C OS A — ±4 — µV T = +85°C A — ±6 — µV T = +125°C A Positive Full-Scale Error V -10 ±2 +10 ppm T = +25°C only FS,P A Negative Full-Scale Error V -10 ±2 +10 ppm T = +25°C only FS,N A Offset Drift — 0.040 — ppm/°C Positive/Negative Full-Scale Error — 0.028 — ppm/°C Drift Note 1: This parameter is established by characterization and not 100% tested. 2: INL is the difference between the endpoints line and the measured code at the center of the quantization band. 3: This current is due to the leakage current and the current due to the offset voltage between V + and V -. IN IN 4: Input impedance is inversely proportional to clock frequency; typical values are for the MCP3550/1 device. V =5V. REF 5: Characterized by design, but not tested. 6: Rejection performance depends on internal oscillator accuracy; see Section4.0 “Device Overview” for more informa- tion on oscillator and digital filter design. MCP3550/1 device rejection specifications characterized from 49 to 61Hz. DS21950D-page 2 © 2007 Microchip Technology Inc.

MCP3550/1/3 DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply at -40°C ≤ T ≤ +85°C, V = 2.7V or 5.0V. A DD V = 2.5V. V + = V - = V = V /2. All ppm units use 2*V as full-scale range. Unless otherwise noted, specification REF IN IN CM REF REF applies to entire MCP3550/1/3 family. Parameters Sym Min Typ Max Units Conditions Rejection Performance(1,6) Common Mode DC Rejection — -135 — dB V range from 0 to V CM DD Power Supply DC Rejection — -115 — dB Common Mode 50/60Hz Rejection CMRR — -135 — dB V varies from 0V to V CM DD Power Supply 50/60Hz Rejection PSRR — -85 — dB MCP3551 only, V varies from DD 4.5V to 5.5V Power Supply 50/60Hz Rejection PSRR — -120 — dB MCP3550-50 or MCP3550-60 only at 50 or 60Hz respectively, V DD varies from 4.5V to 5.5V Normal Mode 50 and 60Hz NMRR — -85 — dB MCP3551 only, Rejection 0 < V < V , CM DD -V < V = (V + -V -) < +V REF IN IN IN REF Normal Mode 50 or 60Hz NMRR — -120 — dB MCP3550-50 or MCP3550-60 only Rejection at 50 or 60Hz respectively, 0 < V < V , CM DD -V < V = (V + -V -) < +V REF IN IN IN REF Analog Inputs Differential Input Range V − V -V — +V V IN+ IN- REF REF Absolute/Common Mode Voltages V - 0.3 — V + 0.3 V SS DD Analog Input Sampling Capacitor — 10 — pF Note5 Differential Input Impedance — 2.4 — MΩ Shutdown Mode Leakage Current — 1 — nA V + = V - = V ; CS = V IN IN DD DD (Note3) Reference Input Voltage Range 0.1 — V V DD Reference Input Sampling — 15 — pF Note5 Capacitor Reference Input Impedance — 2.4 — MΩ Note4 Shutdown Mode Reference — 1 — nA V + = V - = V ; CS = V IN IN SS DD Leakage Current Power Requirements Power Supply Voltage Range V 2.7 — 5.5 V DD MCP3550-50, MCP3551 Supply I — 120 170 µA V = 5V DD DD Current — 100 — µA V = 2.7V DD MCP3550-60, MCP3553 Supply I — 140 185 µA V = 5V DD DD Current — 120 — µA V = 2.7V DD Supply Current, Sleep Mode I — 10 µA DDSL Supply Current, Shutdown Mode I — — 1 µA CS = SCK = V DDS DD Serial Interface Voltage Input High (CS, SCK) V 0.7V — — V IH DD Voltage Input Low (CS, SCK) V — — 0.4 V IL Voltage Output High (SDO/RDY) V V - 0.5 — — V V = 1mA, V = 5.0V OH DD OH DD Note 1: This parameter is established by characterization and not 100% tested. 2: INL is the difference between the endpoints line and the measured code at the center of the quantization band. 3: This current is due to the leakage current and the current due to the offset voltage between V + and V -. IN IN 4: Input impedance is inversely proportional to clock frequency; typical values are for the MCP3550/1 device. V =5V. REF 5: Characterized by design, but not tested. 6: Rejection performance depends on internal oscillator accuracy; see Section4.0 “Device Overview” for more informa- tion on oscillator and digital filter design. MCP3550/1 device rejection specifications characterized from 49 to 61Hz. © 2007 Microchip Technology Inc. DS21950D-page 3

MCP3550/1/3 DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply at -40°C ≤ T ≤ +85°C, V = 2.7V or 5.0V. A DD V = 2.5V. V + = V - = V = V /2. All ppm units use 2*V as full-scale range. Unless otherwise noted, specification REF IN IN CM REF REF applies to entire MCP3550/1/3 family. Parameters Sym Min Typ Max Units Conditions Voltage Output Low (SDO/RDY) V — — 0.4 V V = -1mA, V = 5.0V OL OH DD Input leakage Current I -1 — 1 µA LI (CS, SCK) Internal Pin Capacitance C — 5 — pF Note1 INT (CS, SCK, SDO/RDY) Note 1: This parameter is established by characterization and not 100% tested. 2: INL is the difference between the endpoints line and the measured code at the center of the quantization band. 3: This current is due to the leakage current and the current due to the offset voltage between V + and V -. IN IN 4: Input impedance is inversely proportional to clock frequency; typical values are for the MCP3550/1 device. V =5V. REF 5: Characterized by design, but not tested. 6: Rejection performance depends on internal oscillator accuracy; see Section4.0 “Device Overview” for more informa- tion on oscillator and digital filter design. MCP3550/1 device rejection specifications characterized from 49 to 61Hz. TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated Parameters Sym Min Typ Max Units Conditions Temperature Ranges Specified Temperature Range T -40 — +85 °C A Operating Temperature Range T -40 — +125 °C A Thermal Package Resistances Thermal Resistance, 8L-MSOP θ — 206 — °C/W JA Thermal Resistance, 8L-SOIC θ — 163 — °C/W JA SERIAL TIMINGS Electrical Specifications: Unless otherwise indicated, all parameters apply at -40°C ≤ T ≤ +85°C, A V = 3.3V or 5.0V, SDO load = 50pF. DD Parameters Sym Min Typ Max Units Conditions CLK Frequency f — — 5 MHz SCK CLK High t 90 — — ns HI CLK Low t 90 — — ns LO CLK fall to output data valid t 0 — 90 ns DO CS low to indicate RDY state t 0 — 50 ns RDY CS minimum low time t 50 — — ns CSL RDY flag setup time t 20 — — ns SU CS rise to output disable t 20 — — ns DIS CS disable time t 90 — — ns CSD Power-up to CS LOW t — 10 — µs PUCSL CS High to Shutdown Mode t — 10 — µs CSHSD DS21950D-page 4 © 2007 Microchip Technology Inc.

MCP3550/1/3 t RDY t CSHSD t CSD CS tCSL t DIS SDO /RDY tDO fSCK t t HI LO t SCK SU FIGURE 1-1: Serial Timing. t V PUCSL DD CS FIGURE 1-2: Power-up Timing. © 2007 Microchip Technology Inc. DS21950D-page 5

MCP3550/1/3 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise specified, T = +25°C, V = 5V, V = 2.5V, V = 0V, V = V /2, V + = V -. A DD REF SS CM REF IN IN All ppm units use 2*V as full-scale range.Unless otherwise noted, graphs apply to entire MCP3550/1/3 family. REF 5 10 4 +125 C 3 8 2 +85 C m) m) 1 pp 6 NL (pp -10 -40 C Error ( 4 I -2 +25 C NL -3 I 2 -4 -5 0 -2.5 -1.5 -0.5 0.5 1.5 2.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 V (V) V (V) IN REF FIGURE 2-1: INL Error vs. Input Voltage FIGURE 2-4: Maximum INL Error vs. (V = 2.7V). V . DD REF 5 10 4 +125 C 9 3 +85 C 8 2 m) 7 INL (ppm) --2101 +25 C- 40 C Max INL (pp 3456 -3 2 -4 1 -5 0 -2.5 -1.5 -0.5 0.5 1.5 2.5 -50 -25 0 25 50 75 100 125 VIN (V) Temperature (°C) FIGURE 2-2: INL Error vs. Input Voltage FIGURE 2-5: Maximum INL Error vs. (V = 5.0V). Temperature. DD 10 10 8 L (ppm) -20246 ++18255 C C oise (µV)RMS 56789 MCP3553 N +25 C N 4 I -4 -40 C ut 3 MCP3550/1 -6 p -8 Out 12 -10 0 -5 -4 -3 -2 -1 0 1 2 3 4 5 -2.5 -1.5 -0.5 0.5 1.5 2.5 VIN (V) VIN (Volts) FIGURE 2-3: INL Error vs. Input Voltage FIGURE 2-6: Output Noise vs. Input (V = 5.0V, V = 5V). Voltage (V = 2.7V). DD REF DD DS21950D-page 6 © 2007 Microchip Technology Inc.

MCP3550/1/3 Note: Unless otherwise specified, T = +25°C, V = 5V, V = 2.5V, V = 0V, V = V /2, V + = V -. A DD REF SS CM REF IN IN All ppm units use 2*V as full-scale range. Unless otherwise noted, graphs apply to entire MCP3550/1/3 family. REF 15 10 )S 9 RM )MS 8 µV 10 VR 7 se ( MCP3553 e (µ 6 MCP3553 put Noi 5 MCP3550/1 put Nois 345 MCP3550/1 ut ut 2 O O 1 0 0 -2.5 -1.5 -0.5 0.5 1.5 2.5 -50 -25 0 25 50 75 100 125 VIN (V) Temperature (°C) FIGURE 2-7: Output Noise vs. Input FIGURE 2-10: Output Noise vs. Voltage (V = 5.0V). Temperature. DD u 10.0 5 9.0 )MS 8.0 4 R V 7.0 ut Noise (µ 3456....0000 MCP3553 MCP3550/1 Offset (µV) 23 p ut 2.0 1 O 1.0 0.0 0 0.0 1.0 2.0 3.0 4.0 5.0 2.5 3 3.5 4 4.5 5 5.5 V (V) V (V) REF DD FIGURE 2-8: Output Noise vs. V . FIGURE 2-11: Offset Error vs V REF DD (V =0V). CM 7 10 )S 9 6 RM 8 5 oise (µV 567 MCP3553 set (µV) 34 put N 34 MCP3550/1 Off 2 ut 2 1 O 1 0 0 -50 -25 0 25 50 75 100 125 2.5 3 3.5 4 4.5 5 5.5 VDD (V) Temperature (°C) FIGURE 2-9: Output Noise vs.V . FIGURE 2-12: Offset Error vs. DD Temperature (V = 5.0V). REF © 2007 Microchip Technology Inc. DS21950D-page 7

MCP3550/1/3 Note: Unless otherwise specified, T = +25°C, V = 5V, V = 2.5V, V = 0V, V = V /2, V + = V -. A DD REF SS CM REF IN IN All ppm units are ratioed against 2*V Unless otherwise noted, graphs apply to entire MCP3550/1/3 family. REF . 5 4000 pm) 34 Positive Full-Scale nces 33050000 VVVDRCDEMF == = 51 2V.2.55VV Error (p 012 Occurre 22050000 V1Tc6oAIN 3n= =8s 24e05 cVCutive Full-Scale ----4321 Negative Full-Scale Number of 11505000000 readings -5 0 2.5 3 3.5 4 4.5 5 5.5 -15 -10 -5 0 5 10 15 VDD (V) Output Code (LSB) FIGURE 2-13: Full-Scale Error vs. V . FIGURE 2-16: MCP3550/1 Output Noise DD Histogram. 10 1800 m) 68 es1600 VVDRDEF = = 5 2V.5V or (pp 24 Positive Full-Scale urrenc11240000 VVTACIN M= = = 20 51V°.2C5V ale Err -20 of Occ1800000 1re6a3d8i4n gcosnsecutive ull-Sc --64 Negative Full-Scale mber 460000 F -8 Nu 200 -10 0 -50 -25 0 25 50 75 100 125 -15 -10 -5 0 5 10 15 Temperature (°C) Output Code (LSB) FIGURE 2-14: Full-Scale Error vs. FIGURE 2-17: MCP3553 Output Noise Temperature. Histogram. 5.0 10 4.0 8 m) 6 3.0 or (pp 24 Positive Full-Scale pm) 12..00 Scale Err --420 Negative Full-Scale TUE (p --210...000 Full- --86 --43..00 -10 -5.0 -50 -25 0 25 50 75 100 125 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 Temperature (°C) V (V) IN FIGURE 2-15: Full-Scale Error vs. FIGURE 2-18: Total Unadjusted Error Temperature (V = 5.0V). (TUE) vs. Input Voltage (V = 2.7V). REF DD DS21950D-page 8 © 2007 Microchip Technology Inc.

MCP3550/1/3 Note: Unless otherwise specified, T = +25°C, V = 5V, V = 2.5V, V = 0V, V = V /2, V + = V -. A DD REF SS CM REF IN IN All ppm units use 2*V as full-scale range.Unless otherwise noted, graphs apply to entire MCP3550/1/3 family. REF 5 6 4 3 m) 5 p m) 12 E (p 4 p U E (p 0 m T 3 TU -1 mu 2 -2 xi -3 Ma 1 -4 0 -5 -50 -25 0 25 50 75 100 125 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 VIN (V) Temperature (°C) FIGURE 2-19: Total Unadjusted Error FIGURE 2-22: Maximum TUE vs. (TUE) vs. Input Voltage. Temperature. 10 5 8 4.5 6 4 TUE (ppm) --42024 TUE (ppm) 123...52535 -6 1 -8 0.5 -10 0 -5 -4 -3 -2 -1 0 1 2 3 4 5 2.5 2.7 3 3.3 4 5 5.5 V (V) V (V) IN DD FIGURE 2-20: Total Unadjusted Error FIGURE 2-23: Maximum TUE vs. V . DD (TUE) vs. Input Voltage (V = 5.0V). REF 10 0.6 9 m) 8 0.5 pp 7 0.4 MCP3550/1 UE ( 6 A) 0.3 um T 45 (µDDS 0.2 MCP3553 m 3 I 0.1 xi Ma 2 0 1 0 -0.1 0 1 2 3 4 5 -50 -25 0 25 50 75 100 125 V (V) Temperature (°C) REF FIGURE 2-21: Maximum TUE vs. V . FIGURE 2-24: I vs. Temperature. REF DDS © 2007 Microchip Technology Inc. DS21950D-page 9

MCP3550/1/3 Note: Unless otherwise specified, T = +25°C, V = 5V, V = 2.5V, V = 0V, V = V /2, V + = V -. A DD REF SS CM REF IN IN All ppm units use 2*V as full-scale range.Unless otherwise noted, graphs apply to entire MCP3550/1/3 family. REF 200 160 180 140 MCP3550-60, MCP3553 160 MCP3550-50, MCP3550/1 140 MCP3550-60, MCP3553 120 A) 120 A) 100 I (µDD 18000 MCP3550-50, MCP3550/1 I (µDD 6800 60 40 40 20 20 0 0 2.5 3 3.5 4 4.5 5 5.5 -50 -25 0 25 50 75 100 125 VDD (V) Temperature (°C) FIGURE 2-25: I vs. V . FIGURE 2-26: I vs. Temperature. DD DD DD DS21950D-page 10 © 2007 Microchip Technology Inc.

MCP3550/1/3 3.0 PIN DESCRIPTIONS TABLE 3-1: PIN FUNCTION TABLE Pin No. Symbol I/O/P Function 1 V I Reference Voltage Analog Input Pin REF 2 V + I Non-inverting Analog Input Pin IN 3 V - I Inverting Analog Input Pin IN 4 V P Ground Pin SS 5 SCK I Serial Clock Digital Input Pin 6 SDO/RDY O Data/Ready Digital Output Pin 7 CS I Chip Select Digital Input Pin 8 V P Positive Supply Voltage Pin DD Type Identification: I = Input; O = Output; P = Power 3.1 Voltage Reference (V ) this pin should be maintained in the 2.7V to 5.5V range REF for specified operation. V is the ground pin and the SS The MCP3550/1/3 devices accept single-ended refer- current return path for both analog and digital circuitry ence voltages from 0.1V to VDD. Since the converter of the MCP3550/1/3. If an analog ground plane is output noise is dominated by thermal noise, which is available, it is recommended that this device be tied to independent of the reference voltage, the output noise the analog ground plane of the Printed Circuit Board is not significantly improved by diminishing the refer- (PCB). ence voltage at the V input pin. A reduced voltage REF reference will significantly improve the INL perfor- 3.4 Serial Clock (SCK) mance (see Figure2-4); the INL max error is proportional to VREF2. SCK synchronizes data communication with the device. The device operates in both SPI mode 1,1 and 3.2 Analog Inputs (V +, V -) SPI mode 0,0. Data is shifted out of the device on the IN IN falling edge of SCK. Data is latched in on the rising The MCP3550/1/3 devices accept a fully differential edge of SCK. During CS high times, the SCK pin can analog input voltage to be connected on the VIN+ and idle either high or low. V - input pins. The differential voltage that is con- IN verted is defined by V = V + – V -. The differential IN IN IN 3.5 Data Output (SDO/RDY) voltage range specified for ensured accuracy is from -VREF to +VREF. However, the converter will still output SDO/RDY is the output data pin for the device. Once a valid and usable codes with the inputs overranged by conversion is complete, this pin will go active-low, up to 12% (see Section5.0 “Serial Interface”) at acting as a ready flag. Subsequent falling clock edges room temperature. This overrange is clearly specified will then place the 24-bit data word (two overflow bits by two overload bits in the output code. and 22 bits of data, see Section5.0 “Serial Inter- face”) on the SPI bus through the SDO pin. Data is The absolute voltage range on these input pins extends from V – 0.3V to V + 0.3V. Any voltage above or clocked out on the falling edge of SCK. SS DD below this range will create leakage currents through the Electrostatic Discharge (ESD) diodes. This current 3.6 Chip Select (CS) will increase exponentially, degrading the accuracy and CS gates all communication to the device and can be noise performance of the device. The common mode of used to select multiple devices that share the same the analog inputs should be chosen such that both the SCK and SDO/RDY pins. This pin is also used to differential analog input range and the absolute voltage control the internal conversions, which begin on the range on each pin are within the specified operating falling edge of CS. Raising CS before the first internal range defined in Section1.0 “Electrical Characteris- conversion is complete places the device in Single tics”. Conversion mode. Leaving CS low will place the device in Continuous Conversion mode (i.e., additional 3.3 Supply Voltage (V , V ) DD SS internal conversions will automatically occur). CS may V is the power supply pin for the analog and digital be tied permanently low for two-wire Continuous DD circuitry within the MCP3550/1/3. This pin requires an Conversion mode operation. SDO/RDY enters a high- appropriate bypass capacitor of 0.1µF. The voltage on impedance state with CS high. © 2007 Microchip Technology Inc. DS21950D-page 11

MCP3550/1/3 4.0 DEVICE OVERVIEW The MCP3550/1/3 devices communicate with a simple 3-wire SPI interface. The interface controls the The MCP3550/1/3 devices are 22-bit delta-sigma conversion start event, with an added feature of an ADCs that include fully differential analog inputs, a auto-conversion at system power-up by tying the CS third-order delta-sigma modulator, a fourth-order pin to logic-low. The device can communicate with bus modified SINC decimation filter, an on-chip, low-noise speeds of up to 5MHz, with 50pF capacitive loading. internal oscillator, a power supply monitoring circuit and The interface offers two conversion modes: Single an SPI 3-wire digital interface. These devices can be Conversion mode for multiplexed applications and a easily used to measure low-frequency, low-level Continuous Conversion mode for multiple conversions signals such as those found in pressure transducers, in series. Every conversion is independent of each temperature, strain gauge, industrial control or process other. That is, all internal registers are flushed between control applications. The power supply range for this conversions. When the device is not converting, it auto- product family is 2.7V to 5.5V; the temperature range is matically goes into Shutdown mode and, while in this -40°C to +125°C. The functional block diagram for the mode, consumes less than 1µA. MCP3550/1/3 devices is shown in Figure4-1. A Power-On Reset (POR) monitoring circuit is included to ensure proper power supply voltages during the conversion process. The clock source for the part is internally generated to ±0.5% over the full-power supply voltage range and industrial temperature range. This stable clock source allows for superior conversion repeatability and minimal drift across conversions. The MCP3550/1/3 devices employ a delta-sigma conversion technique to realize up to 22 bits of no missing code performance with 21.9 Effective Number of Bits (ENOB). These devices provide single-cycle conversions with no digital filter settling time. Every conversion includes an internal offset and gain auto- calibration to reduce device error. These calibrations are transparent to the user and are done in real-time during the conversion. Therefore, these devices do not require any additional time or conversion to proceed, allowing easy usage of the devices for multiplexed applications. The MCP3550/1/3 devices incorporate a fourth-order digital decimation filter in order to allow superior averaging performance, as well as excellent line frequency rejection capabilities. The oversampling frequency also reduces any external anti-aliasing filter requirements. Reference Input Differential Charge Conversion Output Bit Analog Input GOaifnfs aentd Transfer ThirdΔ-ΣOrder Stream DeDciimgitaatlion Code SPI 3-wire Code Interface Calibration Modulator Filter (SINC4) Clock Internal Oscillator FIGURE 4-1: MCP3550/1/3 Functional Block Diagram. DS21950D-page 12 © 2007 Microchip Technology Inc.

MCP3550/1/3 4.1 MCP3550/1/3 Delta-Sigma 4.2 Digital Filter Modulator with Internal Offset and The MCP3550/1/3 devices include a digital decimation Gain Calibration filter, which is a fourth-order modified SINC filter. This filter averages the incoming bit stream from the modu- The converter core of the MCP3550/1/3 devices is a lator and outputs a 22-bit conversion word in binary third-order delta-sigma modulator with automatic gain two's complement. When all bits have been processed and offset error calibrations. The modulator uses a 1-bit by the filter, the output code is ready for SPI communi- DAC structure. The delta-sigma modulator processes cation, the RDY flag is set on the SDO/RDY pin and all the sampled charges through switched capacitor the internal registers are reset in order to process the structures controlled by a very low drift oscillator for next conversion. reduced clock jitter. Like the commonly used SINC filter, the modified SINC During the conversion process, the modulator outputs filter in the MCP3550/1/3 family has the main notch a bit stream with the bit frequency equivalent to the frequency located at f /(OSR*L), where f is the bit f /4 (see Table4-1). The high oversampling S S OSC stream sample frequency. OSR is the Oversampling implemented in the modulator ensures very high Ratio and L is the order of the filter. resolution and high averaging factor to achieve low- noise specifications. The bit stream output of the mod- The MCP3550-50 device has the main filter notch ulator is then processed by the digital decimation filter located at 50Hz. For the MCP3550-60 device, the in order to provide a 22-bit output code at a data rate of notch is located at 60Hz. The MCP3551 device has its 12.5Hz for the MCP3550-50, 15Hz for the MCP3550- notch located at 55Hz, and for the MCP3553 device, 60, 13.75Hz for the MCP3551 and 60Hz for the the main notch is located at 240Hz, with an OSR of MCP3553. Since the oversampling ratio is lower with 128. (see Table4-1 for rejection performance). the MCP3553 device, a much higher output data rate is The digital decimation SINC filter has been modified in achieved while still achieving 20 bits No Missing Codes order to offer staggered zeros in its transfer function. (NMC) and 20.6 ENOB. This modification is intended to widen the main notch in A self-calibration of offset and gain occurs at the onset order to be less sensitive to oscillator deviation or line- of every conversion. The conversion data available at frequency drift. The MCP3551 filter has staggered the output of the device is always calibrated for offset zeros spread in order to reject both 50Hz and 60Hz and gain through this process. This offset and gain line frequencies simultaneously (see Figure4-2). auto-calibration is performed internally and has no impact on the speed of the converter since the offset and gain errors are calibrated in real-time during the conversion. The real-time offset and gain calibration schemes do not affect the conversion process. TABLE 4-1: DATA RATE, OUTPUT NOISE AND DIGITAL FILTER SPECIFICATIONS BY DEVICE Output Data Output Primary Sample Internal Device Rate (t ) Noise Notch Frequency Clock 50/60Hz Rejection CONV (Note) (µV ) (Hz) (f ) f RMS S OSC MCP3550-50 80.00ms 2.5 50 25600Hz 102.4kHz -120dB min. at 50Hz MCP3550-60 66.67ms 2.5 60 30720Hz 122.88kHz -120dB min. at 60Hz MCP3551 72.73ms 2.5 55 28160Hz 112.64kHz -82dB min. from 48Hz to 63Hz. - 82dB at 50Hz and -88dB at 60Hz MCP3553 16.67ms 6 240 30720Hz 122.88 kHz Not Applicable Note: For the first conversion after exiting Shutdown, t must include an additional 144f periods before CONV OSC the conversion is complete and the RDY (Ready) flag appears on SDO/RDY. © 2007 Microchip Technology Inc. DS21950D-page 13

MCP3550/1/3 : 0 0 -20 B) -20 enuation (dB) ---864000 Mode Rejection (d ---864000 Att-100 ormal -100 N -120 -120 0 50 100 150 200 -140 0 28160 56320 84480 112640140800168960197120225280253440 Frequency (Hz) Frequency (Hz) FIGURE 4-2: SINC Filter Response, FIGURE 4-5: SINC Filter Response at MCP3550-50 Device. Integer Multiples of the Sampling Frequency (f ). s : 4.3 Internal Oscillator 0 The MCP3550/1/3 devices include a highly stable and -20 B) accurate internal oscillator that provides clock signals n (d -40 to the delta-sigma ADC with minimum jitter. The oscil- atio -60 lator is a specialized structure with a low temperature u coefficient across the full range of specified operation. Atten -80 See Table4-1 for oscillator frequencies. -100 The conversion time is an integer multiple of the inter- -120 nal clock period and, therefore, has the same accuracy 0 60 120 180 240 as the internal clock frequency. The internal oscillator Frequency (Hz) frequency is 102.4kHz ±1% for the MCP3550-50, 112.64kHz ±1% for the MCP3551, and 122.88kHz FIGURE 4-3: SINC Filter Response, ±1% for the MCP3550-60 and MCP3553 devices, MCP3550-60 Device. across the full power supply voltage and specified temperature ranges. : The notch of the digital filter is proportional to the 0 internal oscillator frequency, with the exact notch -10 -20 frequency equivalent to the oscillator accuracy (< 1% B) -30 deviation). This high accuracy, combined with wide d -40 n ( -50 notches, will ensure that the MCP3551 will have simul- o uati --7600 taneous 50Hz and 60Hz line frequency rejection and en -80 the MCP3550-50 or MCP3550-60 devices will have Att -90 greater than 120dB rejection (at either 50 or 60Hz) by -100 the digital filtering, even when jitter is present. -110 -120 The internal oscillator is held in the reset condition 0 10 20 30 40 50 60 70 80 90 100110 when the part is in Shutdown mode to ensure very low Frequency (Hz) power consumption (< 1µA in Shutdown mode). The internal oscillator is independent of all serial digital FIGURE 4-4: SINC Filter Response, interface edges (i.e., state machine processing the MCP3551 Device, Simultaneous 50/60Hz digital SPI interface is asynchronous with respect to the Rejection. internal clock edges). DS21950D-page 14 © 2007 Microchip Technology Inc.

MCP3550/1/3 4.4 Differential Analog Inputs 4.5 Voltage Reference Input Pin The MCP3550/1/3 devices accept a fully differential The MCP3550/1/3 devices accept a single-ended analog input voltage to be connected to the VIN+ and external reference voltage, to be connected on the VIN- input pins. The differential voltage that is converted VREF input pin. Internally, the reference voltage for the is defined by VIN = VIN+ – VIN-. The differential voltage ADC is a differential voltage with the non-inverting input range specified for ensured accuracy is from -VREF to connected to the VREF pin and the inverting input +VREF. connected to the VSS pin. The value of the reference The converter will output valid and usable codes from - voltage is VREF - VSS and the common mode of the 112% to 112% of output range (see Section5.0 reference is always (VREF - VSS)/2. “Serial Interface”) at room temperature. The ±12% The MCP3550/1/3 devices accept a single-ended overrange is clearly specified by two overload bits in reference voltage from 0.1V to V The converter DD. the output code: OVH and OVL. This feature allows for output noise is dominated by thermal noise that is system calibration of a positive gain error. independent of the reference voltage. Therefore, the The absolute voltage range on these input pins extends output noise is not significantly improved by lowering from VSS - 0.3V to VDD + 0.3V. If the input voltages are the reference voltage at the VREF input pin. However, a above or below this range, the leakage currents of the reduced reference voltage will significantly improve the ESD diodes will increase exponentially, degrading the INL performance since the INL max error is accuracy and noise performance of the converter. The proportional to VREF2 (see Figure2-4). common mode of the analog inputs should be chosen The charge and discharge of the input capacitor create such that both the differential analog input range and dynamic input currents at the V input pin inversely REF absolute voltage range on each pin are within the proportional to the sampling capacitor, which is a func- specified operating range defined in Section1.0 tion of the input reference voltage. The typical value of “Electrical Characteristics”. the single-ended input impedance is 2.4MΩ, with Both the analog differential inputs and the reference VDD=VREF=5V. The DC leakage current caused by input have switched-capacitor input structures. The the ESD input diodes, though on the order of 1nA input capacitors are charged and discharged alterna- typically, can cause additional gain error proportional to tively with the input and the reference in order to the source resistance at the VREF pin. process a conversion. The charge and discharge of the input capacitors create dynamic input currents at the 4.6 Power-On Reset (POR) V + and V - input pins inversely proportional to the IN IN The MCP3550/1/3 devices contain an internal Power- sampling capacitor. This current is a function of the On Reset (POR) circuit that monitors power supply differential input voltages and their respective common voltage V during operation. This circuit ensures modes. The typical value of the differential input imped- DD ance is 2.4MΩ, with V = 2.5V, V = V = 5V. The correct device start-up at system power-up and power- CM DD REF down events. The POR has built-in hysteresis and a DC leakage current caused by the ESD input diodes, timer to give a high degree of immunity to potential even though on the order of 1nA, can cause additional ripple and noise on the power supplies, as well as to offset errors proportional to the source resistance at the allow proper settling of the power supply during power- V + and V - input pins. IN IN up. A 0.1µF decoupling capacitor should be mounted From a transient response standpoint and as a first- as close as possible to the V pin, providing additional DD order approximation, these input structures form a transient immunity. simple RC filtering circuit with the source impedance in The threshold voltage is set at 2.2V, with a tolerance of series with the R (switched resistance when closed) ON approximately ±5%. If the supply voltage falls below of the input switch and the sampling capacitor. In order this threshold, the MCP3550/1/3 devices will be held in to ensure the accuracy of the sampled charge, proper a reset condition or in Shutdown mode. When the part settling time of the input circuit has to be considered. is in Shutdown mode, the power consumption is less Slow settling of the input circuit will create additional than 1µA. The typical hysteresis value is around gain error. As a rule of thumb, in order to obtain 1ppm 200mV in order to prevent reset during brown-out or absolute measurement accuracy, the sampling period other glitches on the power supply. must be 14 times greater than the input circuit RC time constant. © 2007 Microchip Technology Inc. DS21950D-page 15

MCP3550/1/3 Once a power-up event has occurred, the device must 4.8 Sleep Mode require additional time before a conversion can take place. During this time, all internal analog circuitry must During Sleep mode, the device is not converting and is settle before the first conversion can occur. An internal awaiting data retrieval; the internal analog circuitry is timer counts 32 internal clock periods before the still running and the device typically consumes 10µA. internal oscillator can provide clock to the conversion In order to restart a conversion while in Sleep mode, process. This allows all internal analog circuitry to toggling CS to a logic-high (placing the part in Shut- down mode) and then back to a logic-low will restart the settle to their proper operating point. This timing is typically less than 300µs, which is negligible compared conversion. Sleep can only be entered in Single Conversion mode. Once a conversion is complete in to one conversion time (e.g. 72.7ms for the Single Conversion mode, the device automatically MCP3551). Figure4-6 illustrates the conditions for a enters Sleep mode. power-up and power-down event under typical start-up conditions. V DD 2.2V 2.0V 300µs 0V Time Normal Reset Start-up Reset Operation FIGURE 4-6: Power-On Reset Operation. 4.7 Shutdown Mode When not internally converting, the two modes of operation for the MCP3550/1/3 devices are the Shutdown and Sleep modes. During Shutdown mode, all internal analog circuitry, including the POR, is turned off and the device consumes less than 1µA. When exiting Shutdown mode, the device must require addi- tional time before a conversion can take place. During this time, all internal analog circuitry must settle before the first conversion can occur. An internal timer counts 32 internal clock periods before the internal oscillator can provide clock to the conversion process. This allows all internal analog circuitry to settle to their proper operating point. This timing is typically less than 300µs, which is negligible compared to one conversion time (72.7ms for MCP3551). DS21950D-page 16 © 2007 Microchip Technology Inc.

MCP3550/1/3 5.0 SERIAL INTERFACE Bit 21 to bit 0 represents the output code in 22-bit binary two's complement. Bit 21 is the sign bit and is logic ‘0’ when the differential analog input is positive 5.1 Overview and logic ‘1’ when the differential analog input is Serial communication between the microcontroller and negative. From Bit 20 to bit 0, the output code is given the MCP3550/1/3 devices is achieved using CS, SCK MSb first (MSb is bit 20 and LSB is Bit 0). When the and SDO/RDY. There are two modes of operation: analog input value is comprised between -VREF and Single Conversion and Continuous Conversion. CS VREF–1LSB, the two overflow bits are set to logic ‘0’. controls the conversion start. There are 24 bits in the The relationship between input voltage and output data word: 22 bits of conversion data and two overflow code is shown in Figure5-1. bits. The conversion process takes place via the inter- The delta-sigma modulator saturation point for the nal oscillator and the status of this conversion must be differential analog input is located at around ±112% of detected. The typical method of communication is V (at room temperature), meaning that the modula- REF shown in Figure5-1. The status of the internal conver- tor will still give accurate output codes with an over- sion is the SDO/RDY pin and is available with CS low. range of 12% below or above the reference voltage. A High state on SDO/RDY means the device is busy Unlike the usual 22-bit device, the 22-bit output code converting, while a Low state means the conversion is will not lock at 0x1FFFFF for positive sign inputs or finished and data is ready for transfer using SCK. 0x200000 for negative sign inputs in order to take SDO/RDY remains in a high-impedance state when advantage of the overrange capabilities of the device. CS is held high. CS must be low when clocking out the This can be practical for closed-loop operations, for data using SCK and SDO/RDY. instance. In case of an overflow, the output code Bit 22 is Overflow High (OVH) when V > V – 1LSB, becomes a 23-bit two's complement output code, IN REF OVH toggles to logic ‘1’, detecting an overflow high in where the sign bit will be the OVL bit. If an overflow high the analog input voltage. or low is detected, OVL (bit 23) becomes the sign bit (instead of bit 21), the MSb is then bit 21 and the con- Bit 23 is Overflow Low (OVL) when V < -V , OVL IN REF verter can be used as a 23-bit two's complement code toggles to logic ‘1’, detecting an overflow low in the converter, with output code from bits B21 to B0, and analog input voltage. The state OVH=OVL = ‘1’ is not OVL as the sign bit. Figure5-1 summarizes the output defined and should be considered as an interrupt for coding data format with or without overflow high and the SPI interface meaning erroneous communication. low. CS SCK SDO/RDY D O O 2120191817 16 1514131211 10 9 8 7 6 5 4 3 2 1 0 HI-Z READY R L H FIGURE 5-1: Typical Serial Device Communication and Example Digital Output Codes for Specific Analog Input Voltages. © 2007 Microchip Technology Inc. DS21950D-page 17

MCP3550/1/3 5.2 Controlling Internal Conversions In Continuous Conversion mode, a consecutive and the Internal Oscillator conversion will be automatic. In this mode, the device is continuously converting, independent of the serial During Shutdown mode, on the falling edge of CS, the interface. The most recent conversion data will always conversion process begins. During this process, the be available in the Output register. internal oscillator clocks the delta-sigma modulator and When the device exits Shutdown, there is an internal the SINC filter until a conversion is complete. This power-up delay that must be observed. conversion time is t and the timing is shown in CONV Figure5-2. At the end of t , the digital filter has CONV settled completely and there is no latency involved with the digital SINC filter of the MCP3550/1/3. The two modes of conversion for the MCP3550/1/3 devices are Single Conversion and Continuous Conversion. In Single Conversion mode, a consecutive conversion will not automatically begin. Instead, after a single conversion is complete and all four filters have settled, the device puts the data into the output register and enters shutdown. CS Int. Osc t Sleep Shutdown CONV SCK (opt) x24 Hi-Z Hi-Z SDO/RDY FIGURE 5-2: Single Conversion Mode. CS Shutdown Int. Osc tCONV tCONV tCONV SCK (opt) x24 SDO/RDY Hi-Z FIGURE 5-3: Continuous Conversion Mode. DS21950D-page 18 © 2007 Microchip Technology Inc.

MCP3550/1/3 5.3 Single Conversion Mode 5.4 Continuous Conversion Mode If a rising edge of Chip Select (CS) occurs during t , If no rising edge of CS occurs during any given conver- CONV a subsequent conversion will not take place and the sion per Figure5-2, a subsequent conversion will take device will enter low-power Shutdown mode after place and the contents of the previous conversion will t completes. This is referred to as Single be overwritten. This operation is demonstrated in CONV Conversion mode. This operation is demonstrated in Figure5-5. Once conversion output data has started to Figure5-3. Note that a falling edge of CS during the be clocked out, the output buffer is not refreshed until same conversion that detected a rising edge, as in all 24 bits have been clocked. A complete read must Figure5-2, will not initiate a new conversion. Once a occur in order to read the next conversion in this mode. rising edge is seen, the device will enter Sleep, then The subsequent conversion data to be read will then be Shutdown mode. Once the device has been put into the most recent conversion. The conversion time is Single Conversion mode, the data must be clocked out fixed and cannot be shortened by the rising edge of CS. in order for a new conversion to take place. A This rising edge will place the part in Shutdown mode subsequent falling edge on CS during Shutdown mode and all conversion data will be lost. will not initiate a new conversion, unless the prior The transfer of data from the SINC filter to the output conversion data has been clocked out of the device. buffer is demonstrated in Figure5-5. If the previous After the final data bit has been clocked out on the 25th conversion data is not clocked out of the device, it will clock, the SDO/RDY pin will go active-high. be lost and replaced by the new conversion. When the device is in Continuous Conversion mode, the most 5.3.1 READY FUNCTION OF SDO/RDY recent conversion data is always present at the output PIN, SINGLE CONVERSION MODE register for data retrieval. At every falling edge of CS during the internal conver- sion, the state of the internal conversion is latched on the SDO/RDY pin to give ready or busy information. A CS High state means the device is currently performing an internal conversion and data cannot be clocked out. A Int. Osc Low state means the device has finished its conversion and the data is ready for retrieval on the falling edge of tCONVA tCONVB tCONV C SCK. This operation is demonstrated in Figure5-4. Note that the device has been put into Single SCK & SDO/RDY Conversion mode with the first rising edge of CS. Conversion B data is clocked Note: The Ready state is latched on each falling out of the device here. edge of CS and will not dynamically FIGURE 5-5: Most Current Continuous update if CS is held low. CS must be Conversion Mode Data. toggled high through low. If a conversion is in process, it cannot be terminated with the rising edge of CS. SDO/RDY must first CS transition to a Low state, which will indicate the end of conversion. Int. Osc 5.4.1 READY FUNCTION OF SDO/RDY PIN IN CONTINUOUS CONVERSION t CONV MODE Hi-Z The device enters Continuous Conversion mode if no SDO/RDY rising edge of CS is seen during t and consecu- CONV tive conversions ensue. SDO/RDY will be high, FIGURE 5-4: RDY Functionality in Single indicating that a conversion is in process. When a Conversion Mode. conversion is complete, SDO/RDY will change to a Low state. With the Low state of SDO/RDY after this first conversion, the conversion data can be accessed with the combination of SCK and SDO/RDY. If the data ready event happens during the clocking out of the data, the data ready bit will be displayed after the complete 24-bit word communication (i.e., the data ready event will not interrupt a data transfer). © 2007 Microchip Technology Inc. DS21950D-page 19

MCP3550/1/3 If 24 bits of data are required from this conversion, they must be accessed during this communication. You can terminate data transition by bringing CS high, but the remaining data will be lost and the converter will go into Shutdown mode. Once the data has been transmitted by the converter, the SDO/RDY pin will remain in the LSB state until the 25th falling edge of SCK. At this point, SDO/RDY is released from the Data Acquisition mode and changed to the RDY state. Note: The RDY state is not latched to CS in this mode; the RDY flag dynamically updates on the SDO/RDY pin and remains in this state until data is clocked out using the SCK pin. 5.4.2 2-WIRE CONTINUOUS CONVERSION OPERATION, (CS TIED PERMANENTLY LOW) It is possible to use only two wires to communicate with the MCP3550/1/3 devices. In this state, the device is always in Continuous Conversion mode, with internal conversions continuously occurring. This mode can be entered by having CS low during power-up or changing it to a low position after power-up. If CS is low at power- up, the first conversion of the converter is initiated approximately 300µs after the power supply has stabilized. DS21950D-page 20 © 2007 Microchip Technology Inc.

MCP3550/1/3 5.5 Using The MCP3550/1/3 with In SPI mode 1,1, data is read using only 24 clocks or Microcontroller (MCU) SPI Ports three byte transfers. The data ready bit must be read by testing the SDO/RDY line prior to a falling edge of It is required that the microcontroller SPI port be config- the clock. ured to clock out data on the falling edge of clock and In SPI mode 0,0, data is read using 25 clocks or four latch data in on the rising edge. Figure5-6 depicts the byte transfers. Please note that the data ready bit is operation shown in SPI mode 1,1, which requires that included in the transfer as the first bit in this mode. the SCK from the MCU idles in the High state, while Figure5-7 shows the similar case of SPI Mode 0,0, where the clock idles in the Low state. The waveforms in the figures are examples of an MCU operating the SPI port in 8-bit mode, and the MCP3550/1/3 devices do not require data in 8-bit groups. CS SCK D O O SDO/RDY R H L 2120191817 16 151413121110 9 8 7 6 5 4 3 2 1 0 MCU Receive OLOH21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Buffer Data stored into MCU receive Data stored into MCU receive Data stored into MCU receive register after transmission of register after transmission of register after transmission of first byte second byte third byte FIGURE 5-6: SPI Communication – Mode 1,1. CS SCK O O SDO/RDY DR H L2120191817 16 151413121110 9 8 7 6 5 4 3 2 1 0 MCU Receive DROHOL21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Buffer Data stored into MCU receive Data stored into MCU receive Data stored into MCU receive Data stored into MCU receive register after transmission of register after transmission of register after transmission of register after transmission of first byte second byte third byte fourth byte FIGURE 5-7: SPI Communication – Mode 0,0. © 2007 Microchip Technology Inc. DS21950D-page 21

MCP3550/1/3 6.0 PACKAGING INFORMATION 6.1 Package Marking Information 8-Lead MSOP Example: XXXXXX 3553E e3 YWWNNN 715256 8-Lead SOIC (150 mil) Examples: XXXXXXXX MCP3551E XXXXYYWW SN^e^30715 NNN 256 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. DS21950D-page 22 © 2007 Microchip Technology Inc.

MCP3550/1/3 8-Lead Plastic Micro Small Outline Package (MS) [MSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 e b c A A2 φ A1 L1 L Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e 0.65 BSC Overall Height A – – 1.10 Molded Package Thickness A2 0.75 0.85 0.95 Standoff A1 0.00 – 0.15 Overall Width E 4.90 BSC Molded Package Width E1 3.00 BSC Overall Length D 3.00 BSC Foot Length L 0.40 0.60 0.80 Footprint L1 0.95 REF Foot Angle φ 0° – 8° Lead Thickness c 0.08 – 0.23 Lead Width b 0.22 – 0.40 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. MicrochipTechnologyDrawingC04-111B © 2007 Microchip Technology Inc. DS21950D-page 23

MCP3550/1/3 8-Lead Plastic Small Outline (SN) – Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D e N E E1 NOTE 1 1 2 3 b h α h c A A2 φ A1 L L1 β Units MILLMETERS Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e 1.27 BSC Overall Height A – – 1.75 Molded Package Thickness A2 1.25 – – Standoff § A1 0.10 – 0.25 Overall Width E 6.00 BSC Molded Package Width E1 3.90 BSC Overall Length D 4.90 BSC Chamfer (optional) h 0.25 – 0.50 Foot Length L 0.40 – 1.27 Footprint L1 1.04 REF Foot Angle φ 0° – 8° Lead Thickness c 0.17 – 0.25 Lead Width b 0.31 – 0.51 Mold Draft Angle Top α 5° – 15° Mold Draft Angle Bottom β 5° – 15° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. MicrochipTechnologyDrawingC04-057B DS21950D-page 24 © 2007 Microchip Technology Inc.

MCP3550/1/3 APPENDIX A: REVISION HISTORY Revision A (September 2005) (cid:129) Original Release of this Document. Revision B (October 2005) (cid:129) Changed LSb refefences to LSB. Revision C (December 2005) (cid:129) Added MCP3550-50, MCP3550-60 references throughout this document. Revision D (January 2007) (cid:129) This update includes revisions to the packaging diagrams. © 2007 Microchip Technology Inc. DS21950D-page 25

MCP3550/1/3 NOTES: DS21950D-page 26 © 2007 Microchip Technology Inc.

MCP3550/1/3 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. –X /XX Examples: a) MCP3550-50-E/MS: Extended Temp., Device Temperature Package 8LD MSOP. Range b) MCP3550/1T-50E/MS:Tape and Reel, Extended Temp., 8LD MSOP. Device: MCP3550-50: Single Channel 22-Bit Delta-Sigma ADC MCP3550T-50: Single Channel 22-Bit Delta-Sigma ADC c) MCP3550-60-E/SN: Extended Temp., (Tape and Reel) 8LD SOIC. MCP3550-60: Single Channel 22-Bit Delta-Sigma ADC d) MCP3550/1T-60E/SN:Tape and Reel, MCP3550T-60: Single Channel 22-Bit Delta-Sigma ADC Extended Temp., (Tape and Reel) MCP3551: Single Channel 22-Bit Delta-Sigma ADC 8LD SOIC. MCP3551T: Single Channel 22-Bit Delta-Sigma ADC (Tape and Reel) a) MCP3551-E/MS: Extended Temp., MCP3553: Single Channel 22-Bit Delta-Sigma ADC 8LD MSOP. MCP3553T: Single Channel 22-Bit Delta-Sigma ADC b) MCP3551T-E/MS: Tape and Reel, (Tape and Reel) Extended Temp., 8LD MSOP. Temperature Range: E = -40°C to +125°C c) MCP3553-E/SN: Extended Temp., 8LD SOIC. d) MCP3553T-E/SN: Tape and Reel, Package: MS = Plastic MSOP, 8-lead Extended Temp., SN = Plastic SOIC (150 mil Body), 8-lead 8LD SOIC. © 2007 Microchip Technology Inc. DS21950D-page 27

MCP3550/1/3 NOTES: DS21950D-page 28 © 2007 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: (cid:129) Microchip products meet the specification contained in their particular Microchip Data Sheet. (cid:129) Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. (cid:129) There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. (cid:129) Microchip is willing to work with the customer who is concerned about the integrity of their code. (cid:129) Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, Accuron, and may be superseded by updates. It is your responsibility to dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. PROMATE, PowerSmart, rfPIC, and SmartShunt are MICROCHIP MAKES NO REPRESENTATIONS OR registered trademarks of Microchip Technology Incorporated WARRANTIES OF ANY KIND WHETHER EXPRESS OR in the U.S.A. and other countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, INCLUDING BUT NOT LIMITED TO ITS CONDITION, SEEVAL, SmartSensor and The Embedded Control Solutions QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, CodeGuard, devices in life support and/or safety applications is entirely at dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, the buyer’s risk, and the buyer agrees to defend, indemnify and ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, hold harmless Microchip from any and all damages, claims, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active suits, or expenses resulting from such use. No licenses are Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit, conveyed, implicitly or otherwise, under any Microchip PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, intellectual property rights. PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2007, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2007 Microchip Technology Inc. DS21950D-page 29

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: MCP3550-50E/MS MCP3550-50E/SN MCP3550-60E/MS MCP3550-60E/SN MCP3550T-50E/MS MCP3550T- 50E/SN MCP3550T-60E/MS MCP3550T-60E/SN MCP3551-E/MS MCP3551-E/SN MCP3551T-E/MS MCP3551T- E/SN MCP3553-E/MS MCP3553-E/SN MCP3553T-E/MS MCP3553T-E/SN MCP3550-50E/SNVAO MCP3550- 60E/SNVAO