MCP3422/3/4 18-Bit, Multi-Channel ΔΣ Analog-to-Digital Converter with 2 I C™ Interface and On-Board Reference Features Description • 18-bit ΔΣ ADC with Differential Inputs: The MCP3422, MCP3423 and MCP3424 devices - 2 channels: MCP3422 and MCP3423 (MCP3422/3/4) are the low noise and high accuracy 18-Bit delta-sigma analog-to-digital (ΔΣ A/D) converter - 4 channels: MCP3424 family members of the MCP342X series from Microchip • Differential Input Full Scale Range: -V to REF Technology Inc. These devices can convert analog +V REF inputs to digital codes with up to 18 bits of resolution. • Self Calibration of Internal Offset and Gain per The on-board 2.048V reference voltage enables an Each Conversion input range of ±2.048V differentially (full scale • On-Board Voltage Reference (V ): REF range=4.096V/PGA). - Accuracy: 2.048V±0.05% These devices can output analog-to-digital conversion - Drift: 15ppm/°C results at rates of 3.75, 15, 60, or 240 samples per • On-Board Programmable Gain Amplifier (PGA): second depending on the user controllable - Gains of 1, 2, 4 or 8 configuration bit settings using the two-wire I2C serial • INL: 10ppm of Full Scale Range interface. During each conversion, the device calibrates offset and gain errors automatically. This • Programmable Data Rate Options: provides accurate conversion results from conversion - 3.75SPS (18bits) to conversion over variations in temperature and power - 15SPS (16bits) supply fluctuation. - 60SPS (14bits) The user can select the PGA gain of x1, x2, x4, or x8 - 240SPS (12bits) before the analog-to-digital conversion takes place. • One-Shot or Continuous Conversion Options This allows the MCP3422/3/4 devices to convert a very • Low Current Consumption: weak input signal with high resolution. - 135µA typical The MCP3422/3/4 devices have two conversion (VDD= 3V, Continuous Conversion) modes: (a) One-Shot Conversion mode and (b) - 36µA typical Continuous Conversion mode. In One-Shot conversion (V = 3V, One-Shot Conversion with 1SPS) mode, the device performs a single conversion and DD • On-Board Oscillator enters a low current standby mode automatically until it • I2C™ Interface: receives another conversion command. This reduces current consumption greatly during idle periods. In - Standard, Fast and High Speed Modes Continuous conversion mode, the conversion takes - User configurable two external address pins place continuously at the set conversion speed. The for MCP3423 and MCP3424 device updates its output buffer with the most recent • Single Supply Operation: 2.7V to 5.5V conversion data. • Extended Temperature Range: -40°C to +125°C The devices operate from a single 2.7V to 5.5V power supply and have a two-wire I2C compatible serial Typical Applications interface for a standard (100kHz), fast (400kHz), or high-speed (3.4MHz) mode. • Portable Instrumentation and Consumer Goods The I2C address bits for the MCP3423 and MCP3424 • Temperature Sensing with RTD, Thermistor, and are selected by using two external I2C address Thermocouple selection pins (Adr0 and Adr1). The user can configure • Bridge Sensing for Pressure, Strain, and Force the device to one of eight available addresses by • Weigh Scales connecting these two address selection pins to V , DD • Battery Fuel Gauges V or float. The I2C address bits of the MCP3422 are SS • Factory Automation Equipment programmed at the factory during production. © 2009 Microchip Technology Inc. DS22088C-page 1

MCP3422/3/4 The MCP3422 and MCP3423 devices have two The MCP3422 is available in 8-pin SOIC, DFN, and differential input channels and the MCP3424 has four- MSOP packages. The MCP3423 is available in 10-pin differential input channels. All electrical properties of DFN, and MSOP packages. The MCP3424 is available these three devices are the same except the in 14-pin SOIC and TSSOP packages. differences in the number of input channels and I2C address bit selection options. Package Types MCP3422 MCP3423 MCP3424 MSOP, SOIC MSOP SOIC, TSSOP CH1+ 1 8 CH2- CH1+ 1 10 Adr1 CH1+ 1 14 CH4- M CH1- 2 CP 7 CH2+ CH1- 2 MC 9 Adr0 CH1- 2 13 CH4+ VSDDDA 34 3422 56 VSSCSL CVHSS2+ 34 P342 78 SSCDLA CCHH22+- 34 MCP 1112 CCHH33-+ CH2- 5 3 6 VDD VSS 5 3424 10 Adr1 MCP3422 MCP3423 VDD 6 9 Adr0 SDA 7 8 SCL 2x3DFN* 3x3DFN* CH1+ 1 8 CH2- CH1+ 1 10 Adr1 CH1- 2 EP 7 CH2+ CH1- 2 9 Adr0 9 EP VDD 3 6 VSS VSS 3 11 8 SCL SDA 4 5 SCL CH2+ 4 7 SDA CH2- 5 6 VDD * Includes Exposed Thermal Pad (EP); see Table3-1. Functional Block Diagram VSS VDD MCP3422 Voltage Reference (2.048V) V REF CH1+ SCL X ΔΣ ADC I2C CH1- U PGA M Converter Interface SDA CH2+ CH2- Gain = 1,2,4, or 8 Clock Oscillator DS22088C-page 2 © 2009 Microchip Technology Inc.

MCP3422/3/4 Functional Block Diagram VSS VDD MCP3423 Voltage Reference Adr1 (2.048V) Adr0 V REF CH1+ SCL CH1- UX PGA ΔΣ ADC I2C M Converter Interface SDA CH2+ CH2- Gain = 1,2,4, or 8 Clock Oscillator Functional Block Diagram VSS VDD MCP3424 CH1+ Voltage Reference Adr1 (2.048V) CH1- Adr0 V REF CH2+ SCL CH2- X ΔΣ ADC I2C U PGA M Converter Interface SDA CH3+ CH3- Gain = 1,2,4, or 8 Clock CH4+ Oscillator CH4- © 2009 Microchip Technology Inc. DS22088C-page 3

MCP3422/3/4 NOTES: DS22088C-page 4 © 2009 Microchip Technology Inc.

MCP3422/3/4 1.0 ELECTRICAL †Notice: Stresses above those listed under “Maximum Rat- CHARACTERISTICS ings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the Absolute Maximum Ratings† operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods V ...................................................................................7.0V DD may affect device reliability. All inputs and outputs .......................V –0.4V to V +0.4V SS DD Differential Input Voltage ......................................|V - V | DD SS Output Short Circuit Current ................................Continuous Current at Input Pins ....................................................±2mA Current at Output and Supply Pins ............................±10mA Storage Temperature....................................-65°C to +150°C Ambient Temp. with power applied...............-55°C to +125°C ESD protection on all pins ................≥ 6kV HBM, ≥ 400VMM Maximum Junction Temperature (T )..........................+150°C J ELECTRICAL CHARACTERISTICS Electrical Specifications: Unless otherwise specified, all parameters apply for T = -40°C to +85°C, V = +5.0V, V = 0V, A DD SS CHn+ = CHn- = V /2, V = V /2. All ppm units use 2*V as differential full scale range. REF INCOM REF REF Parameters Sym Min Typ Max Units Conditions Analog Inputs Differential Full Scale Input FSR — ±2.048/PGA — V V = [CHn+ - CHn-] IN Voltage Range Maximum Input Voltage Range V -0.3 — V +0.3 V (Note1) SS DD Differential Input Impedance Z (f) — 2.25/PGA — MΩ During normal mode operation IND (Note2) Common Mode input Z (f) — 25 — MΩ PGA = 1, 2, 4, 8 INC Impedance System Performance Resolution and No Missing 12 — — Bits DR = 240SPS Codes 14 — — Bits DR = 60SPS (Effective Number of Bits) 16 — — Bits DR = 15SPS (Note3) 18 — — Bits DR = 3.75SPS Data Rate DR 176 240 328 SPS 12 bits mode (Note4) 44 60 82 SPS 14 bits mode 11 15 20.5 SPS 16 bits mode 2.75 3.75 5.1 SPS 18 bits mode Output Noise — 1.5 — µV T = +25°C, DR = 3.75SPS, RMS A PGA = 1, V + = V - = GND IN IN Integral Non-Linearity INL — 10 35 ppm of DR = 3.75SPS, FSR = Full FSR Scale Range (Note5) Internal Reference Voltage V — 2.048 — V REF Gain Error (Note6) — 0.05 0.35 % PGA = 1, DR = 3.75SPS Note 1: Any input voltage below or greater than this voltage causes leakage current through the ESD diodes at the input pins. This parameter is ensured by characterization and not 100% tested. 2: This input impedance is due to 3.2pF internal input sampling capacitor. 3: This parameter is ensured by design and not 100% tested. 4: The total conversion speed includes auto-calibration of offset and gain. 5: INL is the difference between the endpoints line and the measured code at the center of the quantization band. 6: Includes all errors from on-board PGA and V . REF 7: This parameter is ensured by characterization and not 100% tested. 8: MCP3423 and MCP3424 only. 9: Addr_Float voltage is applied at address pin. 10: No voltage is applied at address pin (left “floating”). © 2009 Microchip Technology Inc. DS22088C-page 5

MCP3422/3/4 ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise specified, all parameters apply for T = -40°C to +85°C, V = +5.0V, V = 0V, A DD SS CHn+ = CHn- = V /2, V = V /2. All ppm units use 2*V as differential full scale range. REF INCOM REF REF Parameters Sym Min Typ Max Units Conditions PGA Gain Error Match (Note6) — 0.1 — % Between any 2 PGA settings Gain Error Drift (Note6) — 15 — ppm/°C PGA=1, DR=3.75SPS Offset Error V — 15 55 µV Tested at PGA = 1 OS DR = 3.75SPS Offset Drift vs. Temperature — 50 — nV/°C Common-Mode Rejection — 105 — dB at DC and PGA =1, — 110 — dB at DC and PGA =8, T = +25°C A Gain vs. V — 5 — ppm/V T = +25°C, V = 2.7V to 5.5V, DD A DD PGA = 1 Power Supply Rejection at DC — 100 — dB T = +25°C, V = 2.7V to 5.5V, A DD Input PGA = 1 Power Requirements Voltage Range V 2.7 — 5.5 V DD Supply Current during I — 145 180 µA V = 5.0V DDA DD Conversion — 135 — µA V = 3.0V DD Supply Current during Standby I — 0.3 1 µA V = 5.0V DDS DD Mode I2C Digital Inputs and Digital Outputs High level input voltage V 0.7V — V V at SDA and SCL pins IH DD DD Low level input voltage V — — 0.3V V at SDA and SCL pins IL DD Low level output voltage V — — 0.4 V I = 3mA OL OL Hysteresis of Schmidt Trigger V 0.05V — — V f = 100kHz HYST DD SCL for inputs (Note7) Supply Current when I2C bus I — — 10 µA Device is in standby mode while DDB line is active I2C bus is active Input Leakage Current I — — 1 µA V = 5.5V ILH IH I -1 — — µA V = GND ILL IL Logic Status of I2C Address Pins (Note8) Adr0 and Adr1 Pins Addr_Low V — 0.2V V The device reads logic low. SS DD Adr0 and Adr1 Pins Addr_High 0.75V — V V The device reads logic high. DD DD Adr0 and Adr1 Pins Addr_Float 0.35V — 0.6V V Read pin voltage if voltage is DD DD applied to the address pin. (Note9) — V /2 — Device outputs float output DD voltage (V /2) on the address DD pin, if left “floating”. (Note10) Pin Capacitance and I2C Bus Capacitance Pin capacitance C — 4 10 pF PIN I2C Bus Capacitance C — — 400 pF b Note 1: Any input voltage below or greater than this voltage causes leakage current through the ESD diodes at the input pins. This parameter is ensured by characterization and not 100% tested. 2: This input impedance is due to 3.2pF internal input sampling capacitor. 3: This parameter is ensured by design and not 100% tested. 4: The total conversion speed includes auto-calibration of offset and gain. 5: INL is the difference between the endpoints line and the measured code at the center of the quantization band. 6: Includes all errors from on-board PGA and V . REF 7: This parameter is ensured by characterization and not 100% tested. 8: MCP3423 and MCP3424 only. 9: Addr_Float voltage is applied at address pin. 10: No voltage is applied at address pin (left “floating”). DS22088C-page 6 © 2009 Microchip Technology Inc.

MCP3422/3/4 TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, T = -40°C to +125°C, V = +5.0V, V = 0V. A DD SS Parameters Sym Min Typ Max Units Conditions Temperature Ranges Specified Temperature Range T -40 — +85 °C A Operating Temperature Range T -40 — +125 °C A Storage Temperature Range T -65 — +150 °C A Thermal Package Resistances Thermal Resistance, 8L-DFN (2x3) θ — 68 — °C/W JA Thermal Resistance, 8L-MSOP θ — 211 — °C/W JA Thermal Resistance, 8L-SOIC θ — 149.5 — °C/W JA Thermal Resistance, 10L-DFN (3x3) θ — 53.3 — °C/W JA Thermal Resistance, 10L-MSOP θ — 202 — °C/W JA Thermal Resistance, 14L-SOIC θ — 95.3 — °C/W JA Thermal Resistance, 14L-TSSOP θ — 100 — °C/W JA © 2009 Microchip Technology Inc. DS22088C-page 7

MCP3422/3/4 NOTES: DS22088C-page 8 © 2009 Microchip Technology Inc.

MCP3422/3/4 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, T = -40°C to +85°C, V = +5.0V, V = 0V, CHn+ = CHn- = V /2, A DD SS REF V = V /2. INCOM REF 0.0035 8 n-LinearityFSR)0.000..000200523 TA= +25°C e (µV,rms) 567 PGA = P8GA = 4 PGA = 1PGTAA = = + 225°C Integral No(% of 00..000.000010551 PGA = 8 PGA = 4 PGA = 2 PGA = 1 OutPut Nois 1234 0 0 2.5 3 3.5 4 4.5 5 5.5 -100 -75 -50 -25 0 25 50 75 100 V (V) DD Input Signal (% of FSR) FIGURE 2-1: INL vs. Supply Voltage FIGURE 2-4: Output Noise vs. Input (V ). Voltage. DD 0.0035 2 earity 00.0.002053 PGA = 1 V) 1.15 PPGGAA = =1 8 TA= +25°C ntegral Non-Lin(% of FSR)0000..00..000001005512 2.7V 5V Total Error (m-00-..1505 PGA = 4 PGA = 2 I 5.5V -1.5 0 -2 -60 -40 -20 0 20 40 60 80 100 120 140 -100 -75 -50 -25 0 25 50 75 100 Temperature (oC) Input Voltage (% of Full-Scale) FIGURE 2-2: INL vs. Temperature. FIGURE 2-5: Total Error vs. Input Voltage. 20 0.2 15 R) 0.1 Offset Error (µV) -11-00505 PPGGAA = = 2 4 PGA = 8 ain Error (% of FS----0000....43210 PGA = 8 PGA = 2 PGA = 1 -15 PGA = 1 G-0.5 PGA = 4 -20 -0.6 -60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) Temperature (°C) FIGURE 2-3: Offset Error vs. FIGURE 2-6: Gain Error vs. Temperature. Temperature. © 2009 Microchip Technology Inc. DS22088C-page 9

MCP3422/3/4 Note: Unless otherwise indicated, T = -40°C to +85°C, V = +5.0V, V = 0V, CHn+ = CHn- = V /2, A DD SS REF V = V /2. INCOM REF 200 3 Data Rate = 3.75 SPS 180 VDD = 5.5V %) 2 I(µA)DDA 111102460000 VDD = 2.7V cillator Drift ( 01 VDD = 5.0V Os-1 80 60 -2 -60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) Temperature (°C) FIGURE 2-7: I vs. Temperature. FIGURE 2-10: Oscillator Drift vs. DDA Temperature. 1 0 0.9 -10 Data Rate = 3.75 SPS 0.8 -20 µA) 00..67 VDD = 5.5V e (dB) ---543000 I (DDS 000...345 VDD = 5.0V agnitud ---876000 0.2 M -90 0.1 VDD = 2.7V -100 -110 0 -120 -60 -40 -20 0 20 40 60 80 100 120 140 00..11 11 1010 101000 11k000 1010k000 Temperature (°C) Input Signal Frequency (Hz) FIGURE 2-8: I vs. Temperature. FIGURE 2-11: Frequency Response. DDS 14 12 VDD = 5.0V VDD = 5.5V 10 A) 8 µ (DB 6 VDD = 4.5V D I 4 2 VDD = 2.7V 0 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) FIGURE 2-9: I vs. Temperature. DDB DS22088C-page 10 © 2009 Microchip Technology Inc.

MCP3422/3/4 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table3-1. TABLE 3-1: PIN FUNCTION TABLE MCP3422 MCP3423 MCP3424 Sym Description MSOP, SOIC, DFN DFN MSOP SOIC TSSOP 1 1 1 1 1 CH1+ Positive Differential Analog Input Pin of Channel 1 2 2 2 2 2 CH1- Negative Differential Analog Input Pin of Channel 1 7 7 4 4 3 CH2+ Positive Differential Analog Input Pin of Channel 2 8 8 5 5 4 CH2- Negative Differential Analog Input Pin of Channel 2 6 6 3 3 5 V Ground Pin SS 3 3 6 6 6 V Positive Supply Voltage Pin DD 4 4 7 7 7 SDA Bidirectional Serial Data Pin of the I2C Interface 5 5 8 8 8 SCL Serial Clock Pin of the I2C Interface — — 9 9 9 Adr0 I2C Address Selection Pin. See Section5.3.2. — — 10 10 10 Adr1 I2C Address Selection Pin. See Section5.3.2. — — — — 11 CH3+ Positive Differential Analog Input Pin of Channel 3 — — — — 12 CH3- Negative Differential Analog Input Pin of Channel 3 — — — — 13 CH4+ Positive Differential Analog Input Pin of Channel 4 — — — — 14 CH4- Negative Differential Analog Input Pin of Channel 4 9 — 11 — — EP Exposed Thermal Pad (EP); must be connected to V . SS 3.1 Analog Inputs (CHn+, CHn-) 3.2 Supply Voltage (VDD, VSS) CHn+ and CHn- are differential input pins for V is the power supply pin for the device. This pin DD channeln. The user can also connect CHn- pin to V requires an appropriate bypass ceramic capacitor of SS for a single-ended operation. See Figure6-4 for about 0.1µF to ground to attenuate high frequency differential and single-ended connection examples. noise presented in application circuit board. An additional 10µF capacitor (tantalum) in parallel is also The maximum voltage range on each differential input recommended to further attenuate current spike pin is from V -0.3V to V +0.3V. Any voltage below or SS DD noises. The supply voltage (V ) must be maintained above this range will cause leakage currents through DD in the 2.7V to 5.5V range for specified operation. the Electrostatic Discharge (ESD) diodes at the input pins. V is the ground pin and the current return path of the SS device. The user must connect the V pin to a ground This ESD current can cause unexpected performance SS plane through a low impedance connection. If an of the device. The input voltage at the input pins should analog ground path is available in the application PCB be within the specified operating range defined in (printed circuit board), it is highly recommended that Section1.0 “Electrical Characteristics” and the V pin be tied to the analog ground path or Section4.0 “Description of Device Operation”. SS isolated within an analog ground plane of the circuit See Section4.5 “Input Voltage Range” for more board. details of the input voltage range. Figure3-1 shows the input structure of the device. The device uses a switched capacitor input stage at the front end. C is the package pin capacitance and PIN typically about 4pF. D and D are the ESD diodes. 1 2 C is the differential input sampling capacitor. SAMPLE © 2009 Microchip Technology Inc. DS22088C-page 11

MCP3422/3/4 V DD Sampling Switch D1 VT = 0.6V RSS CHn SS RS V 4CPpIFN D2 VT = 0.6V I(L~E ±A1KAnGAE) C(3S.2AMpPFL)E V SS LEGEND V = Signal Source I = Leakage Current at Analog Pin LEAKEAGE R = Source Impedance SS = Sampling Switch SS CHn = Analog Input Pin R = Sampling Switch Resistor S C = Input Pin Capacitance C = Sample Capacitance PIN SAMPLE V = Threshold Voltage D , D = ESD Protection Diode T 1 2 FIGURE 3-1: Equivalent Analog Input Circuit. 3.3 Serial Clock Pin (SCL) 3.4 Serial Data Pin (SDA) SCL is the serial clock pin of the I2C interface. The SDA is the serial data pin of the I2C interface. The SDA device act only as a slave and the SCL pin accepts pin is used for input and output data. In read mode, the only external serial clocks. The input data from the conversion result is read from the SDA pin (output). In Master device is shifted into the SDA pin on the rising write mode, the device configuration bits are written edges of the SCL clock and output from the slave (input) though the SDA pin. The SDA pin is an open- device occurs at the falling edges of the SCL clock. drain N-channel driver. Therefore, it needs a pull-up The SCL pin is an open-drain N-channel driver. resistor from the V line to the SDA pin. Except for DD Therefore, it needs a pull-up resistor from the V line start and stop conditions, the data on the SDA pin must DD to the SCL pin. Refer to Section5.3 “I2C Serial Com- be stable during the high period of the clock. The high munications” for more details of I2C Serial Interface or low state of the SDA pin can only change when the communication. clock signal on the SCL pin is low. Refer to Section5.3 “I2C Serial Communications” for more details of I2C Serial Interface communication. Typical range of the pull-up resistor value for SCL and SDA is from 5kΩ to 10kΩ for standard (100kHz) and fast (400kHz) modes, and less than 1kΩ for high speed mode (3.4MHz). 3.5 Exposed Thermal Pad (EP) There is an internal electrical connection between the Exposed Thermal Pad (EP) and the V pin; they must SS be connected to the same potential on the Printed Circuit Board (PCB). DS22088C-page 12 © 2009 Microchip Technology Inc.

MCP3422/3/4 4.0 DESCRIPTION OF DEVICE The threshold voltage is set at 2.2V with a tolerance of OPERATION approximately ±5%. If the supply voltage falls below this threshold, the device will be held in a reset condition. The typical hysteresis value is approximately 4.1 General Overview 200mV. The MCP3422/3/4 devices are differential multi- The POR circuit is shut-down during the low-power channel low-power, 18-Bit Delta-Sigma A/D converters standby mode. Once a power-up event has occurred, with an I2C serial interface. The devices contain an the device requires additional delay time input channel selection multiplexer (mux), a (approximately 300µs) before a conversion takes programmable gain amplifier (PGA), an on-board place. During this time, all internal analog circuitries are voltage reference (2.048V), and an internal oscillator. settled before the first conversion occurs. Figure4-1 illustrates the conditions for power-up and power-down When the device powers up (POR is set), it events under typical start-up conditions. automatically resets the configuration bits to default settings. V DD Device default settings are: 2.2V • Conversion bit resolution: 12bits (240sps) 2.0V • Input channel: Channel1 300µS • PGA gain setting: x1 • Continuous conversion Time Once the device is powered-up, the user can Reset Start-up Normal Operation Reset reprogram the configuration bits using I2C serial FIGURE 4-1: POR Operation. interface any time. The configuration bits are stored in volatile memory. 4.3 Internal Voltage Reference User selectable options are: The device contains an on-board 2.048V voltage • Conversion bit resolution: 12, 14, 16, or 18 bits reference. This reference voltage is for internal use only and not directly measurable. The specification of • Input channel selection: CH1, CH2, CH3, or CH4. the reference voltage is part of the device’s gain and • PGA Gain selection: x1, x2, x4, or x8 drift specifications. Therefore, there is no separate • Continuous or one-shot conversion specification for the on-board reference. In the Continuous Conversion mode, the device converts the inputs continuously. While in the One-Shot 4.4 Analog Input Channels Conversion mode, the device converts the input one The user can select the input channel using the time and stays in the low-power standby mode until it configuration register bits. Each channel can be used receives another command for a new conversion. for differential or single-ended input. During the standby mode, the device consumes less than 1µA maximum. Each input channel has a switched capacitor input structure. The internal sampling capacitor (3.2pF for 4.2 Power-On-Reset (POR) PGA = 1) is charged and discharged to process a conversion. The charging and discharging of the input The device contains an internal Power-On-Reset sampling capacitor creates dynamic input currents at (POR) circuit that monitors power supply voltage (VDD) each input pin. The current is a function of the during operation. This circuit ensures correct device differential input voltages, and inversely proportional to start-up at system power-up and power-down events. the internal sampling capacitance, sampling frequency, The device resets all configuration register bits to and PGA setting. default settings as soon as the POR is set. The POR has built-in hysteresis and a timer to give a high degree of immunity to potential ripples and noises on the power supply. A 0.1µF decoupling capacitor should be mounted as close as possible to the V pin DD for additional transient immunity. © 2009 Microchip Technology Inc. DS22088C-page 13

MCP3422/3/4 4.5 Input Voltage Range 4.6 Input Impedance The differential (V ) and common mode voltage The device uses a switched-capacitor input stage using IN (V ) at the input pins without considering PGA a 3.2pF sampling capacitor. This capacitor is switched INCOM setting are defined by: (charged and discharged) at a rate of the sampling frequency that is generated by on-board clock. The VIN = (CHn+)–(CHn-) differential input impedance varies with the PGA settings. The typical differential input impedance during (CHn+)+(CHn-) V = ----------------------------------------------- a normal mode operation is given by: INCOM 2 Where: Z (f) = 2.25 MΩ/PGA n = nth input channel (n=1, 2, 3, or 4) IN The input signal levels are amplified by the internal Since the sampling capacitor is only switching to the programmable gain amplifier (PGA) at the front end of input pins during a conversion process, the above input the ΔΣ modulator. impedance is only valid during conversion periods. In a low power standby mode, the above impedance is not The user needs to consider two conditions for the input presented at the input pins. Therefore, only a leakage voltage range: (a) Differential input voltage range and current due to ESD diode is presented at the input pins. (b) Absolute maximum input voltage range. The conversion accuracy can be affected by the input 4.5.1 DIFFERENTIAL INPUT VOLTAGE signal source impedance when any external circuit is RANGE connected to the input pins. The source impedance adds to the internal impedance and directly affects the The device performs conversions using its internal time required to charge the internal sampling capacitor. reference voltage (V =2.048V). Therefore, the REF Therefore, a large input source impedance connected absolute value of the differential input voltage (V ), IN to the input pins can degrade the system performance, with PGA setting is included, needs to be less than the such as offset, gain, and Integral Non-Linearity (INL) internal reference voltage. The device will output satu- errors. Ideally, the input source impedance should be rated output codes (all 0s or all 1s except sign bit) if the zero. This can be achievable by using an operational absolute value of the input voltage (V ), with PGA IN amplifier with a closed-loop output impedance of tens setting is included, is greater than the internal of ohms. reference voltage (V =2.048V). The input full scale REF voltage range is given by: 4.7 Aliasing and Anti-aliasing Filter EQUATION 4-1: Aliasing occurs when the input signal contains time- –V ≤(V •PGA)≤(V –1LSB) REF IN REF varying signal components with frequency greater than Where: half the sample rate. In the aliasing conditions, the device can output unexpected output codes. For V = CHn+ - CHn- IN applications that are operating in electrical noise VREF = 2.048V environments, the time-varying signal noise or high frequency interference components can be easily If the input voltage level is greater than the above limit, added to the input signals and cause aliasing. Although the user can use a voltage divider and bring down the the device has an internal first order sinc filter, the filter input level within the full scale range. See Figure6-7 for response (Figure2-11) may not give enough more details of the input voltage divider circuit. attenuation to all aliasing signal components. To avoid the aliasing, an external anti-aliasing filter, which can 4.5.2 ABSOLUTE MAXIMUM INPUT be accomplished with a simple RC low-pass filter, is VOLTAGE RANGE typically used at the input pins. The low-pass filter cuts The input voltage at each input pin must be less than off the high frequency noise components and provides the following absolute maximum input voltage limits: a band-limited input signal to the input pins. • Input voltage < V +0.3V DD 4.8 Self-Calibration • Input voltage > V -0.3V SS The device performs a self-calibration of offset and Any input voltage outside this range can turn on the gain for each conversion. This provides reliable input ESD protection diodes, and result in input conversion results from conversion-to-conversion over leakage current, causing conversion errors, or variations in temperature as well as power supply permanently damage the device. fluctuations. Care must be taken in setting the input voltage ranges so that the input voltage does not exceed the absolute maximum input voltage range. DS22088C-page 14 © 2009 Microchip Technology Inc.

MCP3422/3/4 4.9 Digital Output Codes and Table4-1 shows the LSB size of each conversion rate Conversion to Real Values setting. The measured unknown input voltage is obtained by multiplying the output codes with LSB. See 4.9.1 DIGITAL OUTPUT CODE FROM the following section for the input voltage calculation DEVICE using the output codes. The digital output code is proportional to the input TABLE 4-1: RESOLUTION SETTINGS VS. voltage and PGA settings. The output data format is a LSB binary two’s complement. With this code scheme, the MSB can be considered a sign indicator. When the Resolution Setting LSB MSB is a logic ‘0’, the input is positive. When the MSB 12 bits 1mV is a logic ‘1’, the input is negative. The following is an 14 bits 250µV example of the output code: 16 bits 62.5µV a. for a negative full scale input voltage: 100...000 18 bits 15.625µV Example: (CHn+-CHn-) •PGA = -2.048V b. for a zero differential input voltage: 000...000 TABLE 4-2: EXAMPLE OF OUTPUT CODE Example: (CHn+-CHn-) = 0 FOR 18 BITS (NOTE1, NOTE2) c. for a positive full scale input voltage: 011...111 Input Voltage: Digital Output Code Example: (CHn+-CHn-) • PGA = 2.048V [CHn+-CHn-] • PGA The MSB (sign bit) is always transmitted first through ≥VREF 011111111111111111 the I2C serial data line. The resolution for each VREF - 1LSB 011111111111111111 conversion is 18, 16, 14, or 12 bits depending on the 2LSB 000000000000000010 conversion rate selection bit settings by the user. 1LSB 000000000000000001 The output codes will not roll-over even if the input voltage exceeds the maximum input range. In this 0 000000000000000000 case, the code will be locked at 0111...11 for all -1LSB 111111111111111111 voltages greater than (VREF - 1 LSB)/PGA and -2LSB 111111111111111110 1Ta0b0l0e.4.-2. 0s0ho wfos ra nv eoxltaamgepsle olfe osus tputht acno de-sV oRfE vFa/PriGouAs. - VREF 100000000000000000 input levels for 18 bit conversion mode. Table4-3 < -VREF 100000000000000000 shows an example of minimum and maximum output Note 1: MSB is a sign indicator: codes for each conversion rate option. 0: Positive input (CHn+ > CHn-) 1: Negative input (CHn+ < CHn-) The number of output code is given by: 2: Output data format is binary two’s EQUATION 4-2: complement. Number of Output Code = (CHn+–CHn-) TABLE 4-3: MINIMUM AND MAXIMUM = (Maximum Code+1)×PGA×----------------------------------------- 2.048V OUTPUT CODES (NOTE) Where: Resolution Minimum Maximum Data Rate See Table4-3 for Maximum Code Setting Code Code 12 240SPS -2048 2047 The LSB of the data conversion is given by: 14 60SPS -8192 8191 16 15SPS -32768 32767 EQUATION 4-3: 18 3.75SPS -131072 131071 LSB = 2-----×-----V----R---E---F-- = -2----×-----2---.-0---4---8----V-- Note: Maximum n-bit code = 2N-1 - 1 2N 2N Minimum n-bit code = -1 x 2N-1 Where: N = Resolution, which is programmed in the Configuration Register. © 2009 Microchip Technology Inc. DS22088C-page 15

MCP3422/3/4 4.9.2 CONVERTING THE DEVICE EQUATION 4-4: CONVERTING OUTPUT OUTPUT CODE TO INPUT SIGNAL CODES TO INPUT VOLTAGE VOLTAGE When the user gets the digital output codes from the If MSB = 0 (Positive Output Code): device as described in Section4.9.1 “Digital output LSB Input Voltage = (Output Code)•------------ code from device”, the next step is converting the PGA digital output codes to a measured input voltage. Equation4-4 shows an example of converting the If MSB = 1 (Negative Output Code): output codes to its corresponding input voltage. Input Voltage = (2′s complement of Output Code) •-L----S----B--- PGA If the sign indicator bit (MSB) is ‘0’, the input voltage Where: is obtained by multiplying the output code with the LSB and divided by the PGA setting. LSB = See Table4-1 If the sign indicator bit (MSB) is ‘1’, the output code 2’s complement = 1’s complement + 1 needs to be converted to two’s complement before multiplied by LSB and divided by the PGA setting. Table4-4 shows an example of converting the device output codes to input voltage. TABLE 4-4: EXAMPLE OF CONVERTING OUTPUT CODE TO VOLTAGE (WITH 18 BIT SETTING) Input Voltage Digital Output Code MSB Example of Converting Output Codes to Input Voltage [CHn+-CHn-] • PGA] ≥VREF 011111111111111111 0 (216+215+214+213+212+211+210+29+28+27+26+25+24+23+22+21+20) x LSB(15.625μV)/PGA = 2.048 (V) for PGA = 1 VREF - 1LSB 011111111111111111 0 (216+215+214+213+212+211+210+29+28+27+26+25+24+23+22+21+20) x LSB(15.625μV)/PGA = 2.048 (V) for PGA = 1 2LSB 000000000000000010 0 (0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+21+0)x LSB(15.625μV)/PGA = 31.25 (μV) for PGA = 1 1LSB 000000000000000001 0 (0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+20)x LSB(15.625μV)/PGA = 15.625 (μV)for PGA = 1 0 000000000000000000 0 (0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0)x LSB(15.625μV)/PGA = 0 V (V) for PGA = 1 -1LSB 111111111111111111 1 -(0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+20)x LSB(15.625μV)/PGA = - 15.625 (μV)for PGA = 1 -2LSB 111111111111111110 1 -(0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+21+0)x LSB(15.625μV)/PGA = - 31.25 (μV)for PGA = 1 - VREF 100000000000000000 1 -(217+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0) x LSB(15.625μV)/PGA = - 2.048 (V) for PGA = 1 ≤ -VREF 100000000000000000 1 -(217+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0) x LSB(15.625μV)/PGA = - 2.048 (V) for PGA = 1 DS22088C-page 16 © 2009 Microchip Technology Inc.

MCP3422/3/4 5.0 USING THE DEVICES 5.1.2 ONE-SHOT CONVERSION MODE (O/C BIT = 0) 5.1 Operating Modes Once the One-Shot Conversion Mode (single conver- sion) is selected, the device performs only one The user operates the device by setting up the device conversion, updates the output data register, clears the configuration register using a write command data ready flag (RDY = 0), and then enters a low power (seeFigure5-3) and reads the conversion data using a standby mode. A new One-Shot Conversion is started read command (see Figure5-4 and Figure5-5). again when the device receives a new write command Thedevice operates in two modes: (a) Continuous with RDY = 1. Conversion Mode or (b) One-Shot Conversion Mode (single conversion). This mode selection is made by • When writing configuration register: setting the O/C bit in the Configuration Register. Refer - The RDY bit needs to be set to begin a new to Section5.2 “Configuration Register” for more conversion in one-shot mode information. • When reading conversion data: - RDY bit = 0 means the latest conversion 5.1.1 CONTINUOUS CONVERSION result is ready MODE (O/C BIT = 1) - RDY bit = 1 means the conversion result is The device performs a Continuous Conversion if the O/ not updated since the last reading. A new C bit is set to logic “high”. Once the conversion is conversion is under processing and the RDY completed, RDY bit is toggled to ‘0’ and the result is bit will be cleared when the new conversion is placed at the output data register. The device done immediately begins another conversion and overwrites This One-Shot Conversion Mode is highly the output data register with the most recent result. The recommended for low power operating applications device clears the data ready flag (RDY bit=0) when where the conversion result is needed by request on the conversion is completed. The device sets the ready demand. During the low current standby mode, the flag bit (RDY bit =1), if the latest conversion result has device consumes less than 1µA maximum (or 300nA been read by the Master. typical). For example, if the user collects 18bit • When writing configuration register: conversion data once a second in One-Shot - Setting RDY bit in continuous mode does not Conversion mode, the device draws only about one affect anything fourth of its total operating current. In this example, the • When reading conversion data: device consumes approximately 36µA (135µA / 3.75SPS = 36µA), if the device performs only one - RDY bit = 0 means the latest conversion conversion per second (1SPS) in 18-bit conversion result is ready mode with 3V power supply. - RDY bit = 1 means the conversion result is not updated since the last reading. A new conversion is under processing and the RDY bit will be cleared when the new conversion result is ready © 2009 Microchip Technology Inc. DS22088C-page 17

MCP3422/3/4 5.2 Configuration Register The user can rewrite the configuration byte any time during the device operation. Register5-1 shows the The device has an 8-bit wide configuration register to configuration register bits. select for: input channel, conversion mode, conversion rate, and PGA gain. This register allows the user to change the operating condition of the device and check the status of the device operation. REGISTER 5-1: CONFIGURATION REGISTER R/W-1 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 RDY C1 C0 O/C S1 S0 G1 G0 1 * 0 * 0 * 1 * 0 * 0 * 0 * 0 * bit 7 bit 0 * Default Configuration after Power-On Reset Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RDY: Ready Bit This bit is the data ready flag. In read mode, this bit indicates if the output register has been updated with a latest conversion result. In One-Shot Conversion mode, writing this bit to “1” initiates a new conversion. Reading RDY bit with the read command: 1 = Output register has not been updated 0 = Output register has been updated with the latest conversion result Writing RDY bit with the write command: Continuous Conversion mode: No effect One-Shot Conversion mode: 1 = Initiate a new conversion 0 = No effect bit 6-5 C1-C0: Channel Selection Bits 00 = Select Channel 1 (Default) 01 = Select Channel 2 10 = Select Channel 3 (MCP3424 only, treated as “00” by the MCP3422/MCP3423) 11 = Select Channel 4 (MCP3424 only, treated as “01” by the MCP3422/MCP3423) bit 4 O/C: Conversion Mode Bit 1 = Continuous Conversion Mode (Default). The device performs data conversions continuously 0 = One-Shot Conversion Mode. The device performs a single conversion and enters a low power standby mode until it receives another write or read command bit 3-2 S1-S0: Sample Rate Selection Bit 00 = 240SPS (12 bits) (Default) 01 = 60SPS (14 bits) 10 = 15SPS (16 bits) 11 = 3.75SPS (18 bits) bit 1-0 G1-G0: PGA Gain Selection Bits 00 = x1 (Default) 01 = x2 10 = x4 11 = x8 DS22088C-page 18 © 2009 Microchip Technology Inc.

MCP3422/3/4 If the configuration byte is read repeatedly by clocking 5.3 I2C Serial Communications continuously after reading the data bytes (i.e., after the 5th byte in the 18-bit conversion mode), the state of the The device communicates with Master RDY bit indicates whether the device is ready with new (microcontroller) through a serial I2C (Inter-Integrated conversion result. When the Master finds the RDY bit is Circuit) interface and support standard (100kbits/sec), cleared, it can send a not-acknowledge (NAK) bit and fast (400kbits/sec) and high-speed (3.4Mbits/sec) a stop bit to exit the current read operation and send a modes. The serial I2C is a bidirectional 2-wire data bus new read command for the latest conversion data. communication protocol using open-drain SCL and SDA lines. Once the conversion data has been read, the ready bit toggles to ‘1’ until the next new conversion data is The device can only be addressed as a slave. Once ready. The conversion data in the output register is addressed, it can receive configuration bits with a write overwritten every time a new conversion is completed. command or transmit the latest conversion results with Figure5-4 and Figure5-5 show the examples of a read command. The serial clock pin (SCL) is an input reading the conversion data. The user can rewrite the only and the serial data pin (SDA) is bidirectional. The configuration byte any time for a new setting. Table5-1 Master starts communication by sending a START bit and terminates the communication by sending a STOP and Table5-2 show the examples of the configuration bit. In read mode, the device releases the SDA line bit operation. after receiving NAK and STOP bits. TABLE 5-1: WRITE CONFIGURATION BITS An example of a hardware connection diagram is R/W O/C RDY Operation shown in Figure6-1. More details of the I2C bus characteristic is described in Section5.6 “I2C Bus 0 0 0 No effect if all other bits remain Characteristics”. the same - operation continues with the previous settings. 5.3.1 I2C DEVICE ADDRESSING 0 0 1 Initiate One-Shot Conversion. The first byte after the START bit is always the address 0 1 0 Initiate Continuous Conversion. byte of the device, which includes the device code (4bits), address bits (3bits), and R/W bit. The device 0 1 1 Initiate Continuous Conversion. code for the devices is 1101, which is programmed at the factory. The I2C address bits (A2, A1, A0 bits) for TABLE 5-2: READ CONFIGURATION BITS the MCP3423 and MCP3424 are user configurable and R/W O/C RDY Operation determined by the logic status of the two external address selection pins on the user’s application board 1 0 0 New conversion result in (Adr0 and Adr1 pins). The Master must know the Adr0 One-Shot conversion mode has and Adr1 pin conditions before sending read or write just been read. The RDY bit command. Figure5-1 shows the details of the address remains low until set by a new byte. write command. The three I2C address bits allow up to eight devices on 1 0 1 One-Shot Conversion is in the same I2C bus line. The (R/W) bit determines if the progress. The conversion result Master device wants to read the conversion data or is not updated yet. The RDY bit write to the Configuration register. If the (R/W) bit is set stays high until the current (read mode), the device outputs the conversion data in conversion is completed. the following clocks. If the (R/W) bit is cleared (write 1 1 0 New conversion result in mode), the device expects a configuration byte in the Continuous Conversion mode following clocks. When the device receives the correct has just been read. The RDY bit address byte, it outputs an acknowledge bit after the R/ changes to high after reading the W bit. conversion data. Figure5-1 shows the address byte. Figure5-3 through 1 1 1 The conversion result in Figure5-5 show how to write the configuration register Continuous Conversion mode bits and read the conversion results. was already read. The next new conversion data is not ready. The RDY bit stays high until a new conversion is completed. © 2009 Microchip Technology Inc. DS22088C-page 19

MCP3422/3/4 It is recommended to issue a General Call Reset or Acknowledge bit General Call Latch command once after the device has powered up. This will ensure that the device reads Start bit Read/Write bit the address pins in a stable condition, and avoid latching the address bits while the power supply is Address R/W ACK ramping up. This might cause inaccurate address pin detection. Address Byte When the address pin is left “floating”: Address Byte: Device Code Address Bits (Note 1) When the address pin is left “floating”, the address pin momentarily outputs a short pulse with an amplitude of about V /2 during the latch event. The device also DD 1 1 0 1 A2 A1 A0 latches this pin voltage at the same time. If the “floating” pin is connected to a large parasitic Note 1: MCP3423 and MCP3424: Configured by capacitance (>20pF) or to a long PCB trace, this short the user. See Table5-3 for address bit floating voltage output can be altered. As a result, the configurations. device may not latch the pin correctly. 2: MCP3422: Programmed at the factory It is strongly recommended to keep the “floating” pin during production. pad as short as possible in the customer application FIGURE 5-1: Address Byte. PCB and minimize the parasitic capacitance to the pin as small as possible (< 20pF). 5.3.2 DEVICE ADDRESS BITS (A2, A1, A0) Figure5-2 shows an example of the Latch voltage AND ADDRESS SELECTION PINS output at the address pin when the address pin is left (MCP3423 AND MCP3424) “floating”. The waveform at the Adr0 pin is captured by using an oscilloscope probe with 15pF of capacitance. The MCP3423 and MCP3424 have two external The device latches the floating condition immediately device address pins (Adr1, Adr0). These pins can be after the General Call Latch command. set to a logic high (or tied to V ), low (or tied to V ), DD SS or left floating (not connected to anything, or tied to V /2), These combinations of logic level using the DD two pins allow eight possible addresses. Table5-3 shows the device address depending on the logic Float waveform (output) status of the address selection pins. at address pin The device samples the logic status of the Adr0 and Adr1 pins in the following events: SCL a. Device power-up. b. General Call Reset SDA (See Section5.4 “General Call”). c. General Call Latch (See Section5.4 “General Call”). The device samples the logic status (address pins) FIGURE 5-2: General Call Latch during the above events, and latches the values until a Command and Voltage Output at Address Pin new latch event occurs. During normal operation (after Left “Floating” (MCP3423 and MCP3424). the address pins are latched), the address pins are internally disabled from the rests of the internal circuit. DS22088C-page 20 © 2009 Microchip Technology Inc.

MCP3422/3/4 TABLE 5-3: ADDRESS BITS VS. ADDRESS 5.3.3 WRITING A CONFIGURATION BYTE SELECTION PINS FOR TO THE DEVICE (MCP3423 AND MCP3424 When the Master sends an address byte with the R/W ONLY) (NOTES1,2,3) bit low (R/W = 0), the device expects one configuration byte following the address. Any byte sent after this I2C Device Logic Status of Address second byte will be ignored. The user can change the Address Bits Selection Pins operating mode of the device by writing the configuration register bits. A2 A1 A0 Adr0 Pin Adr1 Pin If the device receives a write command with a new 0 0 0 0 (Addr_Low) 0 (Addr_Low) configuration setting, the device immediately begins a 0 0 1 0 (Addr_Low) Float new conversion and updates the conversion data. 0 1 0 0 (Addr_Low) 1 (Addr_High) 1 0 0 1 (Addr_High) 0 (Addr_Low) 1 0 1 1 (Addr_High) Float 1 1 0 1 (Addr_High) 1 (Addr_High) 0 1 1 Float 0 (Addr_Low) 1 1 1 Float 1 (Addr_High) 0 0 0 Float Float Note 1: Float: (a) Leave pin without connecting to anything (left floating), or (b) apply Addr_Float voltage. 2: The user can tie the pins to V or V : SS DD - Tie to V for Addr_Low SS - Tie to V for Addr_High DD 3: See Addr_Low, Addr_High, and Addr_Float parameters in Electrical Characteristics Table. 1 9 1 9 SCL SDA 1 1 0 1 A2 A1 A0 C1 C0 S1 S0 G1 G0 Start Bit by R/W ACK by O/C ACK by Stop Bit by Master MCP3422/3/4 MCP3422/3/4 Master RDY (a) One-Shot Mode: 1 (b) Continuous Mode: not effected 1st Byte: Address Byte 2nd Byte: with Write command Configuration Byte Note: – Stop bit can be issued any time during writing. – MCP3422/3/4 device code is 1101 (programmed at the factory). – See Figure5-1 for details in Address Byte. FIGURE 5-3: Timing Diagram For Writing To The MCP3422/3/4. © 2009 Microchip Technology Inc. DS22088C-page 21

MCP3422/3/4 5.3.4 READING OUTPUT CODES AND The configuration byte follows the output data bytes. CONFIGURATION BYTE FROM THE The device repeatedly outputs the configuration byte DEVICE only if the Master sends clocks repeatedly after the data bytes. When the Master sends a read command (R/W = 1), the device outputs both the conversion data and The device terminates the current outputs when it configuration bytes. Each byte consists of 8 bits with receives a Not-Acknowledge (NAK), a repeated start or one acknowledge (ACK) bit. The ACK bit after the a stop bit at any time during the output bit stream. It is address byte is issued by the device and the ACK bits not required to read the configuration byte. However, after each conversion data bytes are issued by the the Master may read the configuration byte to check Master. the RDY bit condition.The Master may continuously send clock (SCL) to repeatedly read the configuration When the device is configured for 18-bit conversion byte (to check the RDY bit status). mode, it outputs three data bytes followed by a Figures5-4 and5-5 show the timing diagrams of the configuration byte. The first 6 data bits in the first data reading. byte are repeated MSB (= sign bit) of the conversion data. The user can ignore the first 6 data bits, and take the 7th data bit (D17) as the MSB of the conversion data. The LSB of the 3rd data byte is the LSB of the conversion data (D0). If the device is configured for 12, 14, or 16 bit-mode, the device outputs two data bytes followed by a configuration byte. In 16 bit-conversion mode, the MSB (=sign bit) of the first data byte is D15. In 14-bit conversion mode, the first two bits in the first data byte are repeated MSB bits and can be ignored, and the 3rd bit (D13) is the MSB (=sign bit) of the conversion data. In12-bit conversion mode, the first four bits are repeated MSB bits and can be ignored. The 5th bit (D11) of the byte represents the MSB (= sign bit) of the conversion data. Table5-3 summarizes the conversion data output of each conversion mode. TABLE 5-3: OUTPUT CODES OF EACH RESOLUTION OPTION Conversion Digital Output Codes Option 18-bits MMMMMMD17D16 (1st data byte) - D15 ~ D8 (2nd data byte) - D7 ~ D0 (3rd data byte) - Configuration byte. (Note1) 16-bits D15 ~ D8 (1st data byte) - D7 ~ D0 (2nd data byte) - Configuration byte. (Note2) 14-bits MMD13D ~ D8 (1st data byte) - D7 ~ D0 (2nd data byte) - Configuration byte. (Note3) 12-bits MMMMD11 ~ D8 (1st data byte) - D7 ~ D0 (2nd data byte) - Configuration byte. (Note4) Note 1: D17 is MSB (= sign bit), M is repeated MSB of the data byte. 2: D15 is MSB (= sign bit). 3: D13 is MSB (= sign bit), M is repeated MSB of the data byte. 4: D11 is MSB (= sign bit), M is repeated MSB of the data byte. DS22088C-page 22 © 2009 Microchip Technology Inc.

MCP3422/3/4 er 9 y MastMaster G0 K bby SSG101 O/C 5th Byteguration Byte Optional) To continue: ACTo end: NAK C0 nfi ( Y o D C C1 R 1 9 D0 ACK byMaster op Bit byMaster DDDD4321 4th Byteer Data Byte 9 GG01 NAK byStMaster w e:e D5 Lo S0 BytByt 19 DDD876 ACK byMaster CS01 O/C Nth Repeated Configuration (Optional) d. e DDDD1211109 3rd Bytedle Data Byte 1 C1 RDY an be ignore 5th byte. 1991 Repeat of D17 (MSB)DDDDDA2A1A01716151413 ACK byACK byMCP3422/3/4MasterR/W Byte2nd ByteAddress ByteMidUpper Data Byte (Data on Clocks 1-6thcan be ignored) 3/4 device code is 1101.5-1 for details in Address Byte.NAK bit can be issued any time during reading. n clocks 1 - 6th in 2nd byte are repeated MSB and con byte repeats as long as clock is provided after th 1 1101 1st MCP3422/3/4 – MCP3422/– See Figure– Stop bit or – Data bits o– Configurati y b CL DA Start Bit Master Note: S S FIGURE 5-4: Timing Diagram For Reading From The MCP3422/3/4 With 18-Bit Mode. © 2009 Microchip Technology Inc. DS22088C-page 23

MCP3422/3/4 er 9 y MastMaster G0 K bby SSG101 O/C 4th Byteonfiguration Byte (Optional) To continue: ACTo end: NAK C C0 Y y C1 RD Bit bster 1 byer Stop Ma 9 ACK Mast 9 byer D0 G0 NAK Mast D1 G1 e:e DDDD5432 3rd ByteLower Data Byte CSS010 O/C Nth Repeated BytConfiguration Byt (Optional) 1 DD76 C1 RDY d. byte. 19919 DDDDDDDD1101A2A1A015141312111098 ACK byACK byMasterR/WMCP3422/3/4 1st Byte2nd ByteAddress ByteUpper Data ByteMCP3422/3/4 1 MCP3422/3/4 device code is .1101See Figure5-1 for details in Address Byte.Stop bit or NAK bit can be issued any time during reading. n 14 - bit mode: D15 and D14 are repeated MSB and can be ignoren 12 - bit mode: D15 - D12 are repeated MSB and can be ignored. Configuration byte repeats as long as clock is provided after the 4th – – – – I– I– y b CL DA Start Bit Master Note: S S FIGURE 5-5: Timing Diagram For Reading From The MCP3422/3/4 With 12-Bit to 16-Bit Modes. DS22088C-page 24 © 2009 Microchip Technology Inc.

MCP3422/3/4 5.4 General Call 5.5 High-Speed (HS) Mode The device acknowledges the general call address The I2C specification requires that a high-speed mode (0x00 in the first byte). The meaning of the general call device must be ‘activated’ to operate in high-speed address is always specified in the second byte. Refer mode. This is done by sending a special address byte to Figure5-6. The device supports the following three of “00001XXX” following the START bit. The “XXX” bits general calls. are unique to the High-Speed (HS) mode Master. This For more information on the general call, or other I2C byte is referred to as the High-Speed (HS) Master modes, please refer to the Phillips I2C specification. Mode Code (HSMMC). The MCP3422/3/4 devices do not acknowledge this byte. However, upon receiving 5.4.1 GENERAL CALL RESET this code, the device switches on its HS mode filters and communicates up to 3.4MHz on SDA and SCL The general call reset occurs if the second byte is bus lines. The device will switch out of the HS mode on ‘00000110’ (06h). At the acknowledgement of this the next STOP condition. byte, the device will abort current conversion and perform the following tasks: For more information on the HS mode, or other I2C modes, please refer to the Philips I2C specification. (a) Internal reset similar to a Power-On-Reset (POR). All configuration and data register bits are reset to 5.6 I2C Bus Characteristics default values. (b) Latch the logic status of external address selection The I2C specification defines the following bus pins (Adr0 and Adr1 pins). protocol: • Data transfer may be initiated only when the bus 5.4.2 GENERAL CALL LATCH (MCP3423 is not busy AND MCP3424) • During data transfer, the data line must remain The general call latch occurs if the second byte is stable whenever the clock line is HIGH. Changes ‘00000100’ (04h). The device will latch the logic in the data line while the clock line is HIGH will be status of the external address selection pins (Adr0 and interpreted as a START or STOP condition Adr1 pins), but will not perform a reset. Accordingly, the following bus conditions have been defined using Figure5-7. 5.4.3 GENERAL CALL CONVERSION The general call conversion occurs if the second byte 5.6.1 BUS NOT BUSY (A) is ‘00001000’ (08h). All devices on the bus initiate a Both data and clock lines remain HIGH. conversion simultaneously. When the device receives this command, the configuration will be set to the One- 5.6.2 START DATA TRANSFER (B) Shot Conversion mode and a single conversion will be A HIGH to LOW transition of the SDA line while the performed. The PGA and data rate settings are clock (SCL) is HIGH determines a START condition. All unchanged with this general call. commands must be preceded by a START condition. START LSB STOP 5.6.3 STOP DATA TRANSFER (C) A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All S 0 0 0 0 0 0 0 0 A X X X X X X X X A S operations can be ended with a STOP condition. 5.6.4 DATA VALID (D) First Byte ACK Second Byte ACK (General Call Address) The state of the data line represents valid data when, after a START condition, the data line is stable for the Note: The I2C specification does not allow duration of the HIGH period of the clock signal. ‘00000000’ (00h) in the second byte. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per FIGURE 5-6: General Call Address bit of data. Format. Each data transfer is initiated with a START condition and terminated with a STOP condition. © 2009 Microchip Technology Inc. DS22088C-page 25

MCP3422/3/4 5.6.5 ACKNOWLEDGE AND NON- During reads, the Master (microcontroller) can ACKNOWLEDGE terminate the current read operation by not providing an acknowledge bit (not Acknowledge (NAK)) on the The Master (microcontroller) and the slave (MCP3422/ last byte. In this case, the MCP3422/3/4 devices 3/4) use an acknowledge pulse as a hand shake of release the SDA line to allow the Master communication for each byte. The ninth clock pulse of (microcontroller) to generate a STOP or repeated each byte is used for the acknowledgement. The clock START condition. pulse is always provided by the Master (microcontroller) and the acknowledgement is issued The non-acknowledgement (NAK) is issued by by the receiving device of the byte (Note: The providing the SDA line to “HIGH” during the 9th clock transmitting device must release the SDA line during pulse. the acknowledge pulse.). The acknowledgement is achieved by pulling-down the SDA line “LOW” during the 9th clock pulse by the receiving device. (A) (B) (D) (D) (C) (A) SCL SDA START ADDRESS OR DATA STOP CONDITION ACKNOWLEDGE ALLOWED CONDITION VALID TO CHANGE FIGURE 5-7: Data Transfer Sequence on I2C Serial Bus. DS22088C-page 26 © 2009 Microchip Technology Inc.

MCP3422/3/4 TABLE 5-4: I2C SERIAL TIMING SPECIFICATIONS Electrical Specifications: Unless otherwise specified, all limits are specified for T = -40 to +85°C, V = +2.7V to +5.0V, A DD V = 0V, CHn+ = CHn- = V /2. SS REF Parameters Sym Min Typ Max Units Conditions Standard Mode (100kHz) Clock frequency f 0 — 100 kHz SCL Clock high time THIGH 4000 — — ns Clock low time TLOW 4700 — — ns SDA and SCL rise time TR — — 1000 ns From VIL to VIH (Note1) SDA and SCL fall time TF — — 300 ns From VIH to VIL (Note1) START condition hold time THD:STA 4000 — — ns After this period, the first clock pulse is generated. START (Repeated) condition TSU:STA 4700 — — ns setup time Data hold time THD:DAT 0 — 3450 ns (Note3) Data input setup time TSU:DAT 250 — — ns STOP condition setup time TSU:STO 4000 — — ns Output valid from clock TAA 0 — 3750 ns (Note2, Note3) Bus free time TBUF 4700 — — ns Time between START and STOP conditions. Fast Mode (400kHz) Clock frequency TSCL 0 — 400 kHz Clock high time THIGH 600 — — ns Clock low time TLOW 1300 — — ns SDA and SCL rise time TR 20 + 0.1Cb — 300 ns From VIL to VIH (Note1) SDA and SCL fall time TF 20 + 0.1Cb — 300 ns From VIH to VIL (Note1) START condition hold time THD:STA 600 — — ns After this period, the first clock pulse is generated START (Repeated) condition TSU:STA 600 — — ns setup time Data hold time THD:DAT 0 — 900 ns (Note4) Data input setup time TSU:DAT 100 — — ns STOP condition setup time TSU:STO 600 — — ns Output valid from clock TAA 0 — 1200 ns (Note2, Note3) Bus free time TBUF 1300 — — ns Time between START and STOP conditions. Note 1: This parameter is ensured by characterization and not 100% tested. 2: This specification is not a part of the I2C specification. This specification is equivalent to the Data Hold Time (THD:DAT) plus SDA Fall (or rise) time: TAA = THD:DAT + TF (OR TR). 3: If this parameter is too short, it can create an unintended Start or Stop condition to other devices on the bus line. If this parameter is too long, Clock Low time (T ) can be affected. LOW 4: For Data Input: If this parameter is too long, the Data Input Setup (T ) or Clock Low time (T ) can be affected. SU:DAT LOW For Data Output: This parameter is characterized, and tested indirectly by testing T parameter. AA © 2009 Microchip Technology Inc. DS22088C-page 27

MCP3422/3/4 TABLE 5-4: I2C SERIAL TIMING SPECIFICATIONS (CONTINUED) Electrical Specifications: Unless otherwise specified, all limits are specified for T = -40 to +85°C, V = +2.7V to +5.0V, A DD V = 0V, CHn+ = CHn- = V /2. SS REF Parameters Sym Min Typ Max Units Conditions High Speed Mode (3.4MHz) Clock frequency f 0 — 3.4 MHz C = 100pF SCL b 0 — 1.7 MHz C = 400pF b Clock high time THIGH 60 — — ns Cb = 100pF, fSCL = 3.4MHz 120 — — ns C = 400pF, f = 1.7MHz b SCL Clock low time TLOW 160 — — ns Cb = 100pF, fSCL = 3.4MHz 320 — — ns C = 400pF, f = 1.7MHz b SCL SCL rise time TR — — 40 ns From VIL to VIH, (Note1) C = 100pF, f = 3.4MHz b SCL — — 80 ns From V to V , IL IH C = 400pF, f = 1.7MHz b SCL SCL fall time TF — — 40 ns From VIH to VIL, (Note1) C = 100pF, f = 3.4MHz b SCL — — 80 ns From V to V , IH IL C = 400pF, f = 1.7MHz b SCL SDA rise time TR: DAT — — 80 ns From VIL to VIH, (Note1) C = 100pF, f = 3.4MHz b SCL — — 160 ns From V to V , IL IH C = 400pF, f = 1.7MHz b SCL SDA fall time TF: DATA — — 80 ns From VIH to VIL, (Note1) C = 100pF, f = 3.4MHz b SCL — — 160 ns From V to V , IH IL C = 400pF, f = 1.7MHz b SCL Data hold time THD:DAT 0 — 70 ns Cb = 100pF, fSCL = 3.4MHz (Note4) 0 — 150 ns C = 400pF, f = 1.7MHz b SCL Output valid from clock TAA — — 150 ns Cb = 100pF, fSCL = 3.4MHz (Notes2 and3) — — 310 ns C = 400pF, f = 1.7MHz b SCL START condition hold time THD:STA 160 — — ns After this period, the first clock pulse is generated START (Repeated) condition T 160 — — ns SU:STA setup time Data input setup time TSU:DAT 10 — — ns STOP condition setup time TSU:STO 160 — — ns Note 1: This parameter is ensured by characterization and not 100% tested. 2: This specification is not a part of the I2C specification. This specification is equivalent to the Data Hold Time (THD:DAT) plus SDA Fall (or rise) time: TAA = THD:DAT + TF (OR TR). 3: If this parameter is too short, it can create an unintended Start or Stop condition to other devices on the bus line. If this parameter is too long, Clock Low time (T ) can be affected. LOW 4: For Data Input: If this parameter is too long, the Data Input Setup (T ) or Clock Low time (T ) can be affected. SU:DAT LOW For Data Output: This parameter is characterized, and tested indirectly by testing T parameter. AA DS22088C-page 28 © 2009 Microchip Technology Inc.

MCP3422/3/4 TF THIGH TR T SCL SU:STA T SU:STO TLOW THD:DAT TSU:DAT TBUF SDA TSP THD:STA 0.7VDD 0.3V DD T AA FIGURE 5-8: I2C Bus Timing Data. © 2009 Microchip Technology Inc. DS22088C-page 29

MCP3422/3/4 NOTES: DS22088C-page 30 © 2009 Microchip Technology Inc.

MCP3422/3/4 6.0 BASIC APPLICATION 6.1.3 I2C ADDRESS SELECTION PINS CONFIGURATION (MCP3423 AND MCP3424) The user can tie the Adr0 and Adr1 pins to V , V , The MCP3422/3/4 devices can be used for various SS DD or left floating. See more details in Section5.3.2 precision analog-to-digital converter applications. “Device Address Bits (A2, A1, A0) and Address These devices operate with very simple connections to Selection Pins (MCP3423 and MCP3424)”. the application circuit. The following sections discuss the examples of the device connections and applications. MCP3424 Input Input 1 CH1+ CH4- 14 6.1 Connecting to the Application Signal 1 2 CH1- CH4+ 13 Signal 4 Circuits Input 3 CH2+ CH3- 12 Input Signal 2 4 CH2- CH3+ 11 Signal 3 6.1.1 BYPASS CAPACITORS ON VDD PIN 5 VSS Adr1 10 I2C Address For an accurate measurement, the application circuit 6 VDD Adr0 9 Selection needs a clean supply voltage and must block any noise C1 7 SDA SCL 8 Pins signal to the MCP3422/3/4 devices. Figure6-1 shows an example of using two bypass capacitors (a 10µF tantalum capacitor and a 0.1µF ceramic capacitor) on C2 TO MCU the V line of the MCP3424. These capacitors are (MASTER) DD helpful to filter out any high frequency noises on the V line and also provide the momentary bursts of exDtDra currents when the device needs from the supply. RP RP VDD These capacitors should be placed as close to the V DD pin as possible (within one inch). If the application Rp is the pull-up resistor: circuit has separate digital and analog power supplies, 5kΩ - 10kΩ for f = 100kHz to 400kHz the V and V of the MCP3422/3/4 devices should SCL DD SS reside on the analog plane. ~700Ω for fSCL = 3.45MHz C1: 0.1µF, Ceramic capacitor 6.1.2 CONNECTING TO I2C BUS USING C2: 10µF, Tantalum capacitor PULL-UP RESISTORS The SCL and SDA pins of the MCP3422/3/4 are open- FIGURE 6-1: Typical Connection. drain configurations. These pins require a pull-up Figure6-2 shows an example of multiple device resistor as shown in Figure6-1. The value of these connections. The I2C bus loading capacitance pull-up resistors depends on the operating speed increases as the number of device connected to the I2C (standard, fast, and high speed) and loading bus line increases. The bus loading capacitance affects capacitance of the I2C bus line. Higher value of pull-up on the bus operating speed. For example, the highest resistor consumes less power, but increases the signal bus operating speed for the 400pF bus capacitance is transition time (higher RC time constant) on the bus. 1.7MHz, and 3.4MHz for 100pF. Therefore, the user Therefore, it can limit the bus operating speed. The needs to consider the relationship between the lower value of resistor, on the other hand, consumes maximum operation speed versus. the number of I2C higher power, but allows higher operating speed. If the devices that are connected to the I2C bus line. bus line has higher capacitance due to long bus line or high number of devices connected to the bus, a smaller SDA SCL pull-up resistor is needed to compensate the long RC time constant. The pull-up resistor is typically chosen Microcontroller between 5kΩ and 10kΩ ranges for standard and fast (PIC16F876) MCP3422 modes, and less than 1kΩ for high speed mode depending on the presence of bus loading capacitance. MCP3423 MCP3424 MCP4725 FIGURE 6-2: Example of Multiple Device Connection on I2C Bus. © 2009 Microchip Technology Inc. DS22088C-page 31

MCP3422/3/4 6.1.4 DEVICE CONNECTION TEST 6.1.5 DIFFERENTIAL AND SINGLE- ENDED CONFIGURATION The user can test the presence of the MCP3422/3/4 on the I2C bus line without performing an input data Figure6-4 shows typical connection examples for conversion. This test can be achieved by checking an differential and single-ended inputs. Differential input acknowledge response from the MCP3422/3/4 after signals can be connected to the CHn+ and CHn- input sending a read or write command. Here is an example pins, where n = the channel number (1, 2, 3, or 4). For using Figure6-3: the single-ended input, the input signal is applied to one a. Set the R/W bit “HIGH” in the address byte. of the input pins (typically connected to the CHn+ pin) while the other input pin (typically CHn- pin) is b. Check the ACK pulse after sending the address grounded. All device characteristics hold for the single- byte. ended configuration, but this configuration loses one bit If the device acknowledges (ACK = 0), then the resolution because the input can only stand in positive device is connected, otherwise it is not half scale. Refer to Section1.0 “Electrical Character- connected. istics”. c. Send STOP or START bit. (a) Differential Input Signal Connection: Address Byte Excitation Sensor SCL 1 2 3 4 5 6 7 8 9 CHn+ Input Signal K CHn- 1 1 0 1 A2 A1 A0 1 C SDA A MCP342X Start Stop Bit Device bits Address bits Bit R/W (b) Single-ended Input Signal Connection: MCP342X Excitation Response R 1 FIGURE 6-3: I2C Bus Connection Test. CHn+ Input Signal Sensor R 2 CHn- MCP342X FIGURE 6-4: Differential and Single- Ended Input Connections. DS22088C-page 32 © 2009 Microchip Technology Inc.

MCP3422/3/4 6.2 Application Examples For the current measurement, the device measure the voltage across the current sensor, and converts it by The MCP3422/3/4 devices can be used for broad dividing the measured voltage by a known resistance ranges of sensor and data acquisition applications. value. The voltage drops across the sensor is waste. Figure6-5 shows a circuit example measuring both the Therefore, the current measurement often prefers to battery voltage and current using the MCP3422 device. use a current sensor with smaller resistance value, Channels 1 and 2 are measuring the voltage and the which, in turn, requires high resolution ADC device. current, respectively. The device can measure the input voltage as low as When the input voltage is greater than the internal ref- 2µV range (or current in ~ µA range) with 18 bit erence voltage (V = 2.048V), it needs a voltage resolution and PGA = 8 settings. REF divider circuit to prevent the output code from being The MSB (= sign bit) of the output code determines the saturated. In the example, R and R form a voltage 1 2 direction of the current, which identifies the charging or divider. The R and R are set to yield V to be less 1 2 IN the discharging current. than the internal reference voltage (V = 2.048V). REF Discharging Current To Load Current Sensor Charging To Battery Current R 1 Battery MCP3422 V (Rechargeable) BAT VIN 1 CH1+ CH2-8 2 CH1- CH2+7 3 VDD VSS6 R 0.1µF 4 SDA SCL5 2 SCL To MCU 10µF SDA (MASTER) R V = -----------2-------×V IN R +R BAT 5kΩ 1 2 5kΩ R and R = Voltage Divider V 1 2 DD FIGURE 6-5: Battery Voltage and Charging/Discharging Current Measurement. © 2009 Microchip Technology Inc. DS22088C-page 33

MCP3422/3/4 Figure6-6, shows an example of using the MCP3424for four-channel thermocouple temperature measurement applications. Thermocouple Sensor Isothermal Block Isothermal Block MCP3424 MCP9800 MCP9800 1 CH1+ CH4- 14 SDA SCL 2 CH1- CH4+ 13 SDA 3 CH2+ CH3- 12 SCL 4 CH2- CH3+ 11 0.1µF 5 VSS Adr1 10 VDD 6 VDD Adr0 9 7 SDA SCL 8 MCP9800 MCP9800 10µF SDA Heat SCL SCL SCL SDA TO MCU SDA (MASTER) 5kΩ 5kΩ V DD FIGURE 6-6: Four-Channel Thermocouple Applications. With Type K thermocouple, it can measure EQUATION 6-1: temperature from 0°C to 1250°C degrees. The full Detectable Input Signal Level = 15.625μV/PGA scale output range of the Type K thermocouple is about 50mV. This provides 40µV/°C (= 50mV/ = 1.953125μV for PGA= 8 1250°C) of measurement resolution. Equation6-1 Input Signal Level after gain of 8: shows the measurement budget for sensor signal using = (40μV/°C)•8= 320μV/°C the MCP3422/3/4 device with 18bits and PGA=8settings. With this configuration, the 320μV/°C MCP3424 can detect the input signal level as low as No. of LSB/°C = ------------------------- = 20.48 Codes/°C 15.625μV approximately 2µV. The internal PGA boosts the input Where: signal level eight times. The 40µV/°C input from the thermocouple is amplified internally to 320µV/°C 1 LSB = 15.625µV with 18 bit configuration before the conversion takes place. This results in 20.48LSB/°C output codes. This means there are about 20LSB output codes (or about 4.32 bits) per 1°C of change in temperature. DS22088C-page 34 © 2009 Microchip Technology Inc.

MCP3422/3/4 Equation6-2 shows an example of calculating the expected number of output code with various PGA gain settings for Type K thermocouple output. EQUATION 6-2: EXPECTED NUMBER OF OUTPUT CODE FOR TYPE K THERMOCOUPLE Expected ⎛ ⎞ Number of Output Code = log ⎜----5---0------m-----V------⎟ 2⎜15.625μV⎟ ⎝------------------------⎠ PGA = 11.6 bits for PGA = 1 = 12.6 bits for PGA = 2 = 13.6 bits for PGA = 4 = 14.6 bits for PGA = 8 Where: 1 LSB = 15.625µV with 18 Bit configuration. V DD V DD Pressure Sensor Pressure Sensor (NPP301) (NPP301) MCP3424 1 CH1+ CH4- 14 V 2 CH1- CH4+13 IN 3 CH2+ CH3- 12 VDD V IN V 4 CH2- CH3+ 11 DD 5 VSS Adr110 VDD 6 VDD Adr0 9 R1 R 0.1µF 7 SDA SCL 8 1 R Thermistor 2 10µF Thermistor R TO MCU 2 (MASTER) 5kΩ 5kΩ V DD R V = -----------2--------×V IN R +R DD 1 2 R and R = Voltage Divider 1 2 FIGURE 6-7: Example of Pressure and Temperature Measurement. Figure6-7 shows an example of measuring both excitation voltage). Equation6-3 shows an example of pressure and temperature. The pressure is measured calculating the number of output code for the full scale by using NPP 301 (manufactured by GE NovaSensor), output of the NPP301. and temperature is measured by a thermistor. Thepressure sensor output is 20mV/V. This gives 100mV of full scale output for V of 5V (sensor DD © 2009 Microchip Technology Inc. DS22088C-page 35

MCP3422/3/4 EQUATION 6-3: EXPECTED NUMBER OF OUTPUT CODE FOR NPP301 PRESSURE SENSOR Expected ⎛ ⎞ Number of Output Code = log2⎜⎜-1-1--5-0--.-60---2---5-m--μ---V-V---⎟⎟ ⎝------------------------⎠ PGA = 12.64 bits for PGA = 1 = 13.64 bits for PGA = 2 = 14.64 bits for PGA = 4 = 15.64 bits for PGA = 8 Where: 1 LSB = 15.625µV with 18 Bit configuration. The thermistor temperature sensor can measure the temperature range from -100°C to 300°C. The resistance of the thermistor sensor decreases as temperature increases (negative temperature coefficient). As shown in Figure6-7, the thermistor (R ) 2 forms a voltage divider with R . 1 The thermistor sensor is simple to use and widely used for the temperature measurement applications. It has both linear and non-linear responses over temperature range. R is used to adjust the linear region of interest 1 for measurement. DS22088C-page 36 © 2009 Microchip Technology Inc.

MCP3422/3/4 7.0 DEVELOPMENT TOOL SUPPORT USB Cable to PC 7.1 MCP3422/3/4 Evaluation Boards The Evaluation Boards for MCP3422/3/4 devices are available from Microchip Technology Inc. The boards work with Microchip’s PICkit™ Serial Analyzer. The user can simply connect any sensing voltage to the input test pads of the board and read conversion codes using the easy-to-use PICkit™ Serial Analyzer. Refer to www.microchip.com for further information on this PICkit product’s capabilities and availability. Serial Analog Input MCP3424 Evaluation Board FIGURE 7-2: Setup for the MCP3424 FIGURE 7-1: MCP3424 Evaluation Board. Evaluation Board with PICkit™ Serial Analyzer. FIGURE 7-3: Example of PICkit™ Serial User Interface. © 2009 Microchip Technology Inc. DS22088C-page 37

MCP3422/3/4 NOTES: DS22088C-page 38 © 2009 Microchip Technology Inc.

MCP3422/3/4 8.0 PACKAGING INFORMATION 8.1 Package Marking Information 8-Lead DFN (2x3) (MCP3422) Example: XXX AGM YWW 929 NN 25 8-Lead MSOP (MCP3422) Example: XXXXXX 3422A0 YWWNNN 929256 8-Lead SOIC (300 mil) (MCP3422) Example: XXXXXXXX 3422A0E XXXXXNNN SN^e^3256 YYWW 0929 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2009 Microchip Technology Inc. DS22088C-page 39

MCP3422/3/4 Package Marking Information (Continued) 10-Lead DFN (3x3) (MCP3423) Example: 1 10 1 10 XXXX 3423 2 9 2 9 XYWW 0929 3 8 3 8 NNN 256 4 7 4 7 5 6 5 6 10-Lead MSOP (MCP3423) Example: XXXXXX 3423E YWWNNN 929256 14-Lead SOIC (150 mil) (MCP3424) Example: XXXXXXXXXXX MCP3424 XXXXXXXXXXX E/SL^e^3 YYWWNNN 0929256 14-Lead TSSOP (4.4mm) (MCP3424) Example: XXXXXXXX MCP3424E YYWW 0929 NNN 256 DS22088C-page 40 © 2009 Microchip Technology Inc.

MCP3422/3/4 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:8)(cid:17)(cid:10)(cid:6)(cid:12)(cid:18)(cid:8)(cid:19)(cid:20)(cid:8)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:14)(cid:21)(cid:6)(cid:22)(cid:5)(cid:8)(cid:23)(cid:24)(cid:25)(cid:26)(cid:8)(cid:27)(cid:8)(cid:28)(cid:29)(cid:30)(cid:29)(cid:31) !(cid:8)""(cid:8)#(cid:20)(cid:7)$(cid:8)%(cid:15)(cid:17)(cid:19)& (cid:19)(cid:20)(cid:12)(cid:5)’ 2(cid:21)(cid:20)(cid:14)%(cid:22)(cid:13)(cid:14)&(cid:21) %(cid:14)(cid:19)!(cid:20)(cid:20)(cid:13)(cid:24)%(cid:14)(cid:10)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:13)(cid:14)"(cid:20)(cid:11))(cid:18)(cid:24)(cid:12) ’(cid:14)(cid:10)(cid:25)(cid:13)(cid:11) (cid:13)(cid:14) (cid:13)(cid:13)(cid:14)%(cid:22)(cid:13)(cid:14)(cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:14)(cid:30)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:18)(cid:24)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:19)(cid:18)$(cid:18)(cid:19)(cid:11)%(cid:18)(cid:21)(cid:24)(cid:14)(cid:25)(cid:21)(cid:19)(cid:11)%(cid:13)"(cid:14)(cid:11)%(cid:14) (cid:22)%%(cid:10)133)))(cid:28)&(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:28)(cid:19)(cid:21)&3(cid:10)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:18)(cid:24)(cid:12) D e b N N L K E E2 EXPOSEDPAD NOTE1 NOTE1 1 2 2 1 D2 TOPVIEW BOTTOMVIEW A NOTE2 A3 A1 4(cid:24)(cid:18)% (cid:17)(cid:27)55(cid:27)(cid:17),(cid:23),(cid:8)(cid:3) (cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)(cid:14)5(cid:18)&(cid:18)% (cid:17)(cid:27)6 67(cid:17) (cid:17)(cid:7)8 6!&((cid:13)(cid:20)(cid:14)(cid:21)$(cid:14)(cid:30)(cid:18)(cid:24) 6 9 (cid:30)(cid:18)%(cid:19)(cid:22) (cid:13) (cid:4)(cid:28).(cid:4)(cid:14)/(cid:3)0 7(cid:31)(cid:13)(cid:20)(cid:11)(cid:25)(cid:25)(cid:14):(cid:13)(cid:18)(cid:12)(cid:22)% (cid:7) (cid:4)(cid:28)9(cid:4) (cid:4)(cid:28)(cid:6)(cid:4) (cid:29)(cid:28)(cid:4)(cid:4) (cid:3)%(cid:11)(cid:24)"(cid:21)$$(cid:14) (cid:7)(cid:29) (cid:4)(cid:28)(cid:4)(cid:4) (cid:4)(cid:28)(cid:4)(cid:15) (cid:4)(cid:28)(cid:4). 0(cid:21)(cid:24)%(cid:11)(cid:19)%(cid:14)(cid:23)(cid:22)(cid:18)(cid:19)*(cid:24)(cid:13) (cid:7)+ (cid:4)(cid:28)(cid:15)(cid:4)(cid:14)(cid:8),2 7(cid:31)(cid:13)(cid:20)(cid:11)(cid:25)(cid:25)(cid:14)5(cid:13)(cid:24)(cid:12)%(cid:22) (cid:2) (cid:15)(cid:28)(cid:4)(cid:4)(cid:14)/(cid:3)0 7(cid:31)(cid:13)(cid:20)(cid:11)(cid:25)(cid:25)(cid:14);(cid:18)"%(cid:22) , +(cid:28)(cid:4)(cid:4)(cid:14)/(cid:3)0 ,#(cid:10)(cid:21) (cid:13)"(cid:14)(cid:30)(cid:11)"(cid:14)5(cid:13)(cid:24)(cid:12)%(cid:22) (cid:2)(cid:15) (cid:29)(cid:28)+(cid:4) < (cid:29)(cid:28).. ,#(cid:10)(cid:21) (cid:13)"(cid:14)(cid:30)(cid:11)"(cid:14);(cid:18)"%(cid:22) ,(cid:15) (cid:29)(cid:28).(cid:4) < (cid:29)(cid:28)(cid:16). 0(cid:21)(cid:24)%(cid:11)(cid:19)%(cid:14);(cid:18)"%(cid:22) ( (cid:4)(cid:28)(cid:15)(cid:4) (cid:4)(cid:28)(cid:15). (cid:4)(cid:28)+(cid:4) 0(cid:21)(cid:24)%(cid:11)(cid:19)%(cid:14)5(cid:13)(cid:24)(cid:12)%(cid:22) 5 (cid:4)(cid:28)+(cid:4) (cid:4)(cid:28)(cid:5)(cid:4) (cid:4)(cid:28).(cid:4) 0(cid:21)(cid:24)%(cid:11)(cid:19)%(cid:9)%(cid:21)(cid:9),#(cid:10)(cid:21) (cid:13)"(cid:14)(cid:30)(cid:11)" = (cid:4)(cid:28)(cid:15)(cid:4) < < (cid:19)(cid:20)(cid:12)(cid:5)(cid:11)’ (cid:29)(cid:28) (cid:30)(cid:18)(cid:24)(cid:14)(cid:29)(cid:14)(cid:31)(cid:18) !(cid:11)(cid:25)(cid:14)(cid:18)(cid:24)"(cid:13)#(cid:14)$(cid:13)(cid:11)%!(cid:20)(cid:13)(cid:14)&(cid:11)(cid:26)(cid:14)(cid:31)(cid:11)(cid:20)(cid:26)’(cid:14)(!%(cid:14)&! %(cid:14)((cid:13)(cid:14)(cid:25)(cid:21)(cid:19)(cid:11)%(cid:13)"(cid:14))(cid:18)%(cid:22)(cid:18)(cid:24)(cid:14)%(cid:22)(cid:13)(cid:14)(cid:22)(cid:11)%(cid:19)(cid:22)(cid:13)"(cid:14)(cid:11)(cid:20)(cid:13)(cid:11)(cid:28) (cid:15)(cid:28) (cid:30)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:13)(cid:14)&(cid:11)(cid:26)(cid:14)(cid:22)(cid:11)(cid:31)(cid:13)(cid:14)(cid:21)(cid:24)(cid:13)(cid:14)(cid:21)(cid:20)(cid:14)&(cid:21)(cid:20)(cid:13)(cid:14)(cid:13)#(cid:10)(cid:21) (cid:13)"(cid:14)%(cid:18)(cid:13)(cid:14)((cid:11)(cid:20) (cid:14)(cid:11)%(cid:14)(cid:13)(cid:24)" (cid:28) +(cid:28) (cid:30)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:13)(cid:14)(cid:18) (cid:14) (cid:11))(cid:14) (cid:18)(cid:24)(cid:12)!(cid:25)(cid:11)%(cid:13)"(cid:28) (cid:5)(cid:28) (cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)(cid:18)(cid:24)(cid:12)(cid:14)(cid:11)(cid:24)"(cid:14)%(cid:21)(cid:25)(cid:13)(cid:20)(cid:11)(cid:24)(cid:19)(cid:18)(cid:24)(cid:12)(cid:14)(cid:10)(cid:13)(cid:20)(cid:14)(cid:7)(cid:3)(cid:17),(cid:14)-(cid:29)(cid:5)(cid:28).(cid:17)(cid:28) /(cid:3)01 /(cid:11) (cid:18)(cid:19)(cid:14)(cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)(cid:28)(cid:14)(cid:23)(cid:22)(cid:13)(cid:21)(cid:20)(cid:13)%(cid:18)(cid:19)(cid:11)(cid:25)(cid:25)(cid:26)(cid:14)(cid:13)#(cid:11)(cid:19)%(cid:14)(cid:31)(cid:11)(cid:25)!(cid:13)(cid:14) (cid:22)(cid:21))(cid:24)(cid:14))(cid:18)%(cid:22)(cid:21)!%(cid:14)%(cid:21)(cid:25)(cid:13)(cid:20)(cid:11)(cid:24)(cid:19)(cid:13) (cid:28) (cid:8),21 (cid:8)(cid:13)$(cid:13)(cid:20)(cid:13)(cid:24)(cid:19)(cid:13)(cid:14)(cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)’(cid:14)! !(cid:11)(cid:25)(cid:25)(cid:26)(cid:14))(cid:18)%(cid:22)(cid:21)!%(cid:14)%(cid:21)(cid:25)(cid:13)(cid:20)(cid:11)(cid:24)(cid:19)(cid:13)’(cid:14)$(cid:21)(cid:20)(cid:14)(cid:18)(cid:24)$(cid:21)(cid:20)&(cid:11)%(cid:18)(cid:21)(cid:24)(cid:14)(cid:10)!(cid:20)(cid:10)(cid:21) (cid:13) (cid:14)(cid:21)(cid:24)(cid:25)(cid:26)(cid:28) (cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:23)(cid:13)(cid:19)(cid:22)(cid:24)(cid:21)(cid:25)(cid:21)(cid:12)(cid:26)(cid:2)(cid:20)(cid:11))(cid:18)(cid:24)(cid:12)0(cid:4)(cid:5)(cid:9)(cid:29)(cid:15)+0 © 2009 Microchip Technology Inc. DS22088C-page 41

MCP3422/3/4 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:8)(cid:17)(cid:10)(cid:6)(cid:12)(cid:18)(cid:8)(cid:19)(cid:20)(cid:8)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:14)(cid:21)(cid:6)(cid:22)(cid:5)(cid:8)(cid:23)(cid:24)(cid:25)(cid:26)(cid:8)(cid:27)(cid:8)(cid:28)(cid:29)(cid:30)(cid:29)(cid:31) !(cid:8)""(cid:8)#(cid:20)(cid:7)$(cid:8)%(cid:15)(cid:17)(cid:19)& (cid:19)(cid:20)(cid:12)(cid:5)’ 2(cid:21)(cid:20)(cid:14)%(cid:22)(cid:13)(cid:14)&(cid:21) %(cid:14)(cid:19)!(cid:20)(cid:20)(cid:13)(cid:24)%(cid:14)(cid:10)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:13)(cid:14)"(cid:20)(cid:11))(cid:18)(cid:24)(cid:12) ’(cid:14)(cid:10)(cid:25)(cid:13)(cid:11) (cid:13)(cid:14) (cid:13)(cid:13)(cid:14)%(cid:22)(cid:13)(cid:14)(cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:14)(cid:30)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:18)(cid:24)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:19)(cid:18)$(cid:18)(cid:19)(cid:11)%(cid:18)(cid:21)(cid:24)(cid:14)(cid:25)(cid:21)(cid:19)(cid:11)%(cid:13)"(cid:14)(cid:11)%(cid:14) (cid:22)%%(cid:10)133)))(cid:28)&(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:28)(cid:19)(cid:21)&3(cid:10)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:18)(cid:24)(cid:12) DS22088C-page 42 © 2009 Microchip Technology Inc.

MCP3422/3/4 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:24)(cid:13)(cid:14)((cid:20)(cid:8))"(cid:6)(cid:10)(cid:10)(cid:8)*(cid:16)(cid:12)(cid:10)(cid:13)+(cid:5)(cid:8)(cid:9)(cid:6)(cid:14)(cid:21)(cid:6)(cid:22)(cid:5)(cid:8)(cid:23)(cid:24))(cid:26)(cid:8)%(cid:24))*(cid:9)& (cid:19)(cid:20)(cid:12)(cid:5)’ 2(cid:21)(cid:20)(cid:14)%(cid:22)(cid:13)(cid:14)&(cid:21) %(cid:14)(cid:19)!(cid:20)(cid:20)(cid:13)(cid:24)%(cid:14)(cid:10)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:13)(cid:14)"(cid:20)(cid:11))(cid:18)(cid:24)(cid:12) ’(cid:14)(cid:10)(cid:25)(cid:13)(cid:11) (cid:13)(cid:14) (cid:13)(cid:13)(cid:14)%(cid:22)(cid:13)(cid:14)(cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:14)(cid:30)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:18)(cid:24)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:19)(cid:18)$(cid:18)(cid:19)(cid:11)%(cid:18)(cid:21)(cid:24)(cid:14)(cid:25)(cid:21)(cid:19)(cid:11)%(cid:13)"(cid:14)(cid:11)%(cid:14) (cid:22)%%(cid:10)133)))(cid:28)&(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:28)(cid:19)(cid:21)&3(cid:10)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:18)(cid:24)(cid:12) D N E E1 NOTE1 1 2 e b c A A2 φ A1 L1 L 4(cid:24)(cid:18)% (cid:17)(cid:27)55(cid:27)(cid:17),(cid:23),(cid:8)(cid:3) (cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)(cid:14)5(cid:18)&(cid:18)% (cid:17)(cid:27)6 67(cid:17) (cid:17)(cid:7)8 6!&((cid:13)(cid:20)(cid:14)(cid:21)$(cid:14)(cid:30)(cid:18)(cid:24) 6 9 (cid:30)(cid:18)%(cid:19)(cid:22) (cid:13) (cid:4)(cid:28)>.(cid:14)/(cid:3)0 7(cid:31)(cid:13)(cid:20)(cid:11)(cid:25)(cid:25)(cid:14):(cid:13)(cid:18)(cid:12)(cid:22)% (cid:7) < < (cid:29)(cid:28)(cid:29)(cid:4) (cid:17)(cid:21)(cid:25)"(cid:13)"(cid:14)(cid:30)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:13)(cid:14)(cid:23)(cid:22)(cid:18)(cid:19)*(cid:24)(cid:13) (cid:7)(cid:15) (cid:4)(cid:28)(cid:16). (cid:4)(cid:28)9. (cid:4)(cid:28)(cid:6). (cid:3)%(cid:11)(cid:24)"(cid:21)$$(cid:14) (cid:7)(cid:29) (cid:4)(cid:28)(cid:4)(cid:4) < (cid:4)(cid:28)(cid:29). 7(cid:31)(cid:13)(cid:20)(cid:11)(cid:25)(cid:25)(cid:14);(cid:18)"%(cid:22) , (cid:5)(cid:28)(cid:6)(cid:4)(cid:14)/(cid:3)0 (cid:17)(cid:21)(cid:25)"(cid:13)"(cid:14)(cid:30)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:13)(cid:14);(cid:18)"%(cid:22) ,(cid:29) +(cid:28)(cid:4)(cid:4)(cid:14)/(cid:3)0 7(cid:31)(cid:13)(cid:20)(cid:11)(cid:25)(cid:25)(cid:14)5(cid:13)(cid:24)(cid:12)%(cid:22) (cid:2) +(cid:28)(cid:4)(cid:4)(cid:14)/(cid:3)0 2(cid:21)(cid:21)%(cid:14)5(cid:13)(cid:24)(cid:12)%(cid:22) 5 (cid:4)(cid:28)(cid:5)(cid:4) (cid:4)(cid:28)>(cid:4) (cid:4)(cid:28)9(cid:4) 2(cid:21)(cid:21)%(cid:10)(cid:20)(cid:18)(cid:24)% 5(cid:29) (cid:4)(cid:28)(cid:6).(cid:14)(cid:8),2 2(cid:21)(cid:21)%(cid:14)(cid:7)(cid:24)(cid:12)(cid:25)(cid:13) (cid:3) (cid:4)? < 9? 5(cid:13)(cid:11)"(cid:14)(cid:23)(cid:22)(cid:18)(cid:19)*(cid:24)(cid:13) (cid:19) (cid:4)(cid:28)(cid:4)9 < (cid:4)(cid:28)(cid:15)+ 5(cid:13)(cid:11)"(cid:14);(cid:18)"%(cid:22) ( (cid:4)(cid:28)(cid:15)(cid:15) < (cid:4)(cid:28)(cid:5)(cid:4) (cid:19)(cid:20)(cid:12)(cid:5)(cid:11)’ (cid:29)(cid:28) (cid:30)(cid:18)(cid:24)(cid:14)(cid:29)(cid:14)(cid:31)(cid:18) !(cid:11)(cid:25)(cid:14)(cid:18)(cid:24)"(cid:13)#(cid:14)$(cid:13)(cid:11)%!(cid:20)(cid:13)(cid:14)&(cid:11)(cid:26)(cid:14)(cid:31)(cid:11)(cid:20)(cid:26)’(cid:14)(!%(cid:14)&! %(cid:14)((cid:13)(cid:14)(cid:25)(cid:21)(cid:19)(cid:11)%(cid:13)"(cid:14))(cid:18)%(cid:22)(cid:18)(cid:24)(cid:14)%(cid:22)(cid:13)(cid:14)(cid:22)(cid:11)%(cid:19)(cid:22)(cid:13)"(cid:14)(cid:11)(cid:20)(cid:13)(cid:11)(cid:28) (cid:15)(cid:28) (cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24) (cid:14)(cid:2)(cid:14)(cid:11)(cid:24)"(cid:14),(cid:29)(cid:14)"(cid:21)(cid:14)(cid:24)(cid:21)%(cid:14)(cid:18)(cid:24)(cid:19)(cid:25)!"(cid:13)(cid:14)&(cid:21)(cid:25)"(cid:14)$(cid:25)(cid:11) (cid:22)(cid:14)(cid:21)(cid:20)(cid:14)(cid:10)(cid:20)(cid:21)%(cid:20)! (cid:18)(cid:21)(cid:24) (cid:28)(cid:14)(cid:17)(cid:21)(cid:25)"(cid:14)$(cid:25)(cid:11) (cid:22)(cid:14)(cid:21)(cid:20)(cid:14)(cid:10)(cid:20)(cid:21)%(cid:20)! (cid:18)(cid:21)(cid:24) (cid:14) (cid:22)(cid:11)(cid:25)(cid:25)(cid:14)(cid:24)(cid:21)%(cid:14)(cid:13)#(cid:19)(cid:13)(cid:13)"(cid:14)(cid:4)(cid:28)(cid:29).(cid:14)&&(cid:14)(cid:10)(cid:13)(cid:20)(cid:14) (cid:18)"(cid:13)(cid:28) +(cid:28) (cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)(cid:18)(cid:24)(cid:12)(cid:14)(cid:11)(cid:24)"(cid:14)%(cid:21)(cid:25)(cid:13)(cid:20)(cid:11)(cid:24)(cid:19)(cid:18)(cid:24)(cid:12)(cid:14)(cid:10)(cid:13)(cid:20)(cid:14)(cid:7)(cid:3)(cid:17),(cid:14)-(cid:29)(cid:5)(cid:28).(cid:17)(cid:28) /(cid:3)01 /(cid:11) (cid:18)(cid:19)(cid:14)(cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)(cid:28)(cid:14)(cid:23)(cid:22)(cid:13)(cid:21)(cid:20)(cid:13)%(cid:18)(cid:19)(cid:11)(cid:25)(cid:25)(cid:26)(cid:14)(cid:13)#(cid:11)(cid:19)%(cid:14)(cid:31)(cid:11)(cid:25)!(cid:13)(cid:14) (cid:22)(cid:21))(cid:24)(cid:14))(cid:18)%(cid:22)(cid:21)!%(cid:14)%(cid:21)(cid:25)(cid:13)(cid:20)(cid:11)(cid:24)(cid:19)(cid:13) (cid:28) (cid:8),21 (cid:8)(cid:13)$(cid:13)(cid:20)(cid:13)(cid:24)(cid:19)(cid:13)(cid:14)(cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)’(cid:14)! !(cid:11)(cid:25)(cid:25)(cid:26)(cid:14))(cid:18)%(cid:22)(cid:21)!%(cid:14)%(cid:21)(cid:25)(cid:13)(cid:20)(cid:11)(cid:24)(cid:19)(cid:13)’(cid:14)$(cid:21)(cid:20)(cid:14)(cid:18)(cid:24)$(cid:21)(cid:20)&(cid:11)%(cid:18)(cid:21)(cid:24)(cid:14)(cid:10)!(cid:20)(cid:10)(cid:21) (cid:13) (cid:14)(cid:21)(cid:24)(cid:25)(cid:26)(cid:28) (cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:23)(cid:13)(cid:19)(cid:22)(cid:24)(cid:21)(cid:25)(cid:21)(cid:12)(cid:26)(cid:2)(cid:20)(cid:11))(cid:18)(cid:24)(cid:12)0(cid:4)(cid:5)(cid:9)(cid:29)(cid:29)(cid:29)/ © 2009 Microchip Technology Inc. DS22088C-page 43

MCP3422/3/4 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8))"(cid:6)(cid:10)(cid:10)(cid:8)*(cid:16)(cid:12)(cid:10)(cid:13)+(cid:5)(cid:8)(cid:23))(cid:19)(cid:26)(cid:8)(cid:27)(cid:8)(cid:19)(cid:6)(((cid:20),(cid:18)(cid:8)(cid:30) !(cid:31)(cid:8)""(cid:8)#(cid:20)(cid:7)$(cid:8)%)*-(cid:25)& (cid:19)(cid:20)(cid:12)(cid:5)’ 2(cid:21)(cid:20)(cid:14)%(cid:22)(cid:13)(cid:14)&(cid:21) %(cid:14)(cid:19)!(cid:20)(cid:20)(cid:13)(cid:24)%(cid:14)(cid:10)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:13)(cid:14)"(cid:20)(cid:11))(cid:18)(cid:24)(cid:12) ’(cid:14)(cid:10)(cid:25)(cid:13)(cid:11) (cid:13)(cid:14) (cid:13)(cid:13)(cid:14)%(cid:22)(cid:13)(cid:14)(cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:14)(cid:30)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:18)(cid:24)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:19)(cid:18)$(cid:18)(cid:19)(cid:11)%(cid:18)(cid:21)(cid:24)(cid:14)(cid:25)(cid:21)(cid:19)(cid:11)%(cid:13)"(cid:14)(cid:11)%(cid:14) (cid:22)%%(cid:10)133)))(cid:28)&(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:28)(cid:19)(cid:21)&3(cid:10)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:18)(cid:24)(cid:12) D e N E E1 NOTE1 1 2 3 b h α h c A A2 φ A1 L L1 β 4(cid:24)(cid:18)% (cid:17)(cid:27)55(cid:27)(cid:17),(cid:23),(cid:8)(cid:3) (cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)(cid:14)5(cid:18)&(cid:18)% (cid:17)(cid:27)6 67(cid:17) (cid:17)(cid:7)8 6!&((cid:13)(cid:20)(cid:14)(cid:21)$(cid:14)(cid:30)(cid:18)(cid:24) 6 9 (cid:30)(cid:18)%(cid:19)(cid:22) (cid:13) (cid:29)(cid:28)(cid:15)(cid:16)(cid:14)/(cid:3)0 7(cid:31)(cid:13)(cid:20)(cid:11)(cid:25)(cid:25)(cid:14):(cid:13)(cid:18)(cid:12)(cid:22)% (cid:7) < < (cid:29)(cid:28)(cid:16). (cid:17)(cid:21)(cid:25)"(cid:13)"(cid:14)(cid:30)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:13)(cid:14)(cid:23)(cid:22)(cid:18)(cid:19)*(cid:24)(cid:13) (cid:7)(cid:15) (cid:29)(cid:28)(cid:15). < < (cid:3)%(cid:11)(cid:24)"(cid:21)$$(cid:14)(cid:14)@ (cid:7)(cid:29) (cid:4)(cid:28)(cid:29)(cid:4) < (cid:4)(cid:28)(cid:15). 7(cid:31)(cid:13)(cid:20)(cid:11)(cid:25)(cid:25)(cid:14);(cid:18)"%(cid:22) , >(cid:28)(cid:4)(cid:4)(cid:14)/(cid:3)0 (cid:17)(cid:21)(cid:25)"(cid:13)"(cid:14)(cid:30)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:13)(cid:14);(cid:18)"%(cid:22) ,(cid:29) +(cid:28)(cid:6)(cid:4)(cid:14)/(cid:3)0 7(cid:31)(cid:13)(cid:20)(cid:11)(cid:25)(cid:25)(cid:14)5(cid:13)(cid:24)(cid:12)%(cid:22) (cid:2) (cid:5)(cid:28)(cid:6)(cid:4)(cid:14)/(cid:3)0 0(cid:22)(cid:11)&$(cid:13)(cid:20)(cid:14)A(cid:21)(cid:10)%(cid:18)(cid:21)(cid:24)(cid:11)(cid:25)B (cid:22) (cid:4)(cid:28)(cid:15). < (cid:4)(cid:28).(cid:4) 2(cid:21)(cid:21)%(cid:14)5(cid:13)(cid:24)(cid:12)%(cid:22) 5 (cid:4)(cid:28)(cid:5)(cid:4) < (cid:29)(cid:28)(cid:15)(cid:16) 2(cid:21)(cid:21)%(cid:10)(cid:20)(cid:18)(cid:24)% 5(cid:29) (cid:29)(cid:28)(cid:4)(cid:5)(cid:14)(cid:8),2 2(cid:21)(cid:21)%(cid:14)(cid:7)(cid:24)(cid:12)(cid:25)(cid:13) (cid:3) (cid:4)? < 9? 5(cid:13)(cid:11)"(cid:14)(cid:23)(cid:22)(cid:18)(cid:19)*(cid:24)(cid:13) (cid:19) (cid:4)(cid:28)(cid:29)(cid:16) < (cid:4)(cid:28)(cid:15). 5(cid:13)(cid:11)"(cid:14);(cid:18)"%(cid:22) ( (cid:4)(cid:28)+(cid:29) < (cid:4)(cid:28).(cid:29) (cid:17)(cid:21)(cid:25)"(cid:14)(cid:2)(cid:20)(cid:11)$%(cid:14)(cid:7)(cid:24)(cid:12)(cid:25)(cid:13)(cid:14)(cid:23)(cid:21)(cid:10) (cid:4) .? < (cid:29).? (cid:17)(cid:21)(cid:25)"(cid:14)(cid:2)(cid:20)(cid:11)$%(cid:14)(cid:7)(cid:24)(cid:12)(cid:25)(cid:13)(cid:14)/(cid:21)%%(cid:21)& (cid:5) .? < (cid:29).? (cid:19)(cid:20)(cid:12)(cid:5)(cid:11)’ (cid:29)(cid:28) (cid:30)(cid:18)(cid:24)(cid:14)(cid:29)(cid:14)(cid:31)(cid:18) !(cid:11)(cid:25)(cid:14)(cid:18)(cid:24)"(cid:13)#(cid:14)$(cid:13)(cid:11)%!(cid:20)(cid:13)(cid:14)&(cid:11)(cid:26)(cid:14)(cid:31)(cid:11)(cid:20)(cid:26)’(cid:14)(!%(cid:14)&! %(cid:14)((cid:13)(cid:14)(cid:25)(cid:21)(cid:19)(cid:11)%(cid:13)"(cid:14))(cid:18)%(cid:22)(cid:18)(cid:24)(cid:14)%(cid:22)(cid:13)(cid:14)(cid:22)(cid:11)%(cid:19)(cid:22)(cid:13)"(cid:14)(cid:11)(cid:20)(cid:13)(cid:11)(cid:28) (cid:15)(cid:28) @(cid:14)(cid:3)(cid:18)(cid:12)(cid:24)(cid:18)$(cid:18)(cid:19)(cid:11)(cid:24)%(cid:14)0(cid:22)(cid:11)(cid:20)(cid:11)(cid:19)%(cid:13)(cid:20)(cid:18) %(cid:18)(cid:19)(cid:28) +(cid:28) (cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24) (cid:14)(cid:2)(cid:14)(cid:11)(cid:24)"(cid:14),(cid:29)(cid:14)"(cid:21)(cid:14)(cid:24)(cid:21)%(cid:14)(cid:18)(cid:24)(cid:19)(cid:25)!"(cid:13)(cid:14)&(cid:21)(cid:25)"(cid:14)$(cid:25)(cid:11) (cid:22)(cid:14)(cid:21)(cid:20)(cid:14)(cid:10)(cid:20)(cid:21)%(cid:20)! (cid:18)(cid:21)(cid:24) (cid:28)(cid:14)(cid:17)(cid:21)(cid:25)"(cid:14)$(cid:25)(cid:11) (cid:22)(cid:14)(cid:21)(cid:20)(cid:14)(cid:10)(cid:20)(cid:21)%(cid:20)! (cid:18)(cid:21)(cid:24) (cid:14) (cid:22)(cid:11)(cid:25)(cid:25)(cid:14)(cid:24)(cid:21)%(cid:14)(cid:13)#(cid:19)(cid:13)(cid:13)"(cid:14)(cid:4)(cid:28)(cid:29).(cid:14)&&(cid:14)(cid:10)(cid:13)(cid:20)(cid:14) (cid:18)"(cid:13)(cid:28) (cid:5)(cid:28) (cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)(cid:18)(cid:24)(cid:12)(cid:14)(cid:11)(cid:24)"(cid:14)%(cid:21)(cid:25)(cid:13)(cid:20)(cid:11)(cid:24)(cid:19)(cid:18)(cid:24)(cid:12)(cid:14)(cid:10)(cid:13)(cid:20)(cid:14)(cid:7)(cid:3)(cid:17),(cid:14)-(cid:29)(cid:5)(cid:28).(cid:17)(cid:28) /(cid:3)01 /(cid:11) (cid:18)(cid:19)(cid:14)(cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)(cid:28)(cid:14)(cid:23)(cid:22)(cid:13)(cid:21)(cid:20)(cid:13)%(cid:18)(cid:19)(cid:11)(cid:25)(cid:25)(cid:26)(cid:14)(cid:13)#(cid:11)(cid:19)%(cid:14)(cid:31)(cid:11)(cid:25)!(cid:13)(cid:14) (cid:22)(cid:21))(cid:24)(cid:14))(cid:18)%(cid:22)(cid:21)!%(cid:14)%(cid:21)(cid:25)(cid:13)(cid:20)(cid:11)(cid:24)(cid:19)(cid:13) (cid:28) (cid:8),21 (cid:8)(cid:13)$(cid:13)(cid:20)(cid:13)(cid:24)(cid:19)(cid:13)(cid:14)(cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)’(cid:14)! !(cid:11)(cid:25)(cid:25)(cid:26)(cid:14))(cid:18)%(cid:22)(cid:21)!%(cid:14)%(cid:21)(cid:25)(cid:13)(cid:20)(cid:11)(cid:24)(cid:19)(cid:13)’(cid:14)$(cid:21)(cid:20)(cid:14)(cid:18)(cid:24)$(cid:21)(cid:20)&(cid:11)%(cid:18)(cid:21)(cid:24)(cid:14)(cid:10)!(cid:20)(cid:10)(cid:21) (cid:13) (cid:14)(cid:21)(cid:24)(cid:25)(cid:26)(cid:28) (cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:23)(cid:13)(cid:19)(cid:22)(cid:24)(cid:21)(cid:25)(cid:21)(cid:12)(cid:26)(cid:2)(cid:20)(cid:11))(cid:18)(cid:24)(cid:12)0(cid:4)(cid:5)(cid:9)(cid:4).(cid:16)/ DS22088C-page 44 © 2009 Microchip Technology Inc.

MCP3422/3/4 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8))"(cid:6)(cid:10)(cid:10)(cid:8)*(cid:16)(cid:12)(cid:10)(cid:13)+(cid:5)(cid:8)(cid:23))(cid:19)(cid:26)(cid:8)(cid:27)(cid:8)(cid:19)(cid:6)(((cid:20),(cid:18)(cid:8)(cid:30) !(cid:31)(cid:8)""(cid:8)#(cid:20)(cid:7)$(cid:8)%)*-(cid:25)& (cid:19)(cid:20)(cid:12)(cid:5)’ 2(cid:21)(cid:20)(cid:14)%(cid:22)(cid:13)(cid:14)&(cid:21) %(cid:14)(cid:19)!(cid:20)(cid:20)(cid:13)(cid:24)%(cid:14)(cid:10)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:13)(cid:14)"(cid:20)(cid:11))(cid:18)(cid:24)(cid:12) ’(cid:14)(cid:10)(cid:25)(cid:13)(cid:11) (cid:13)(cid:14) (cid:13)(cid:13)(cid:14)%(cid:22)(cid:13)(cid:14)(cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:14)(cid:30)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:18)(cid:24)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:19)(cid:18)$(cid:18)(cid:19)(cid:11)%(cid:18)(cid:21)(cid:24)(cid:14)(cid:25)(cid:21)(cid:19)(cid:11)%(cid:13)"(cid:14)(cid:11)%(cid:14) (cid:22)%%(cid:10)133)))(cid:28)&(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:28)(cid:19)(cid:21)&3(cid:10)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:18)(cid:24)(cid:12) © 2009 Microchip Technology Inc. DS22088C-page 45

MCP3422/3/4 .(cid:31)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:8)(cid:17)(cid:10)(cid:6)(cid:12)(cid:18)(cid:8)(cid:19)(cid:20)(cid:8)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:14)(cid:21)(cid:6)(cid:22)(cid:5)(cid:8)(cid:23)(cid:24)(cid:17)(cid:26)(cid:8)(cid:27)(cid:8)(cid:30)(cid:29)(cid:30)(cid:29)(cid:31) !(cid:8)""(cid:8)#(cid:20)(cid:7)$(cid:8)%(cid:15)(cid:17)(cid:19)& (cid:19)(cid:20)(cid:12)(cid:5)’ 2(cid:21)(cid:20)(cid:14)%(cid:22)(cid:13)(cid:14)&(cid:21) %(cid:14)(cid:19)!(cid:20)(cid:20)(cid:13)(cid:24)%(cid:14)(cid:10)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:13)(cid:14)"(cid:20)(cid:11))(cid:18)(cid:24)(cid:12) ’(cid:14)(cid:10)(cid:25)(cid:13)(cid:11) (cid:13)(cid:14) (cid:13)(cid:13)(cid:14)%(cid:22)(cid:13)(cid:14)(cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:14)(cid:30)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:18)(cid:24)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:19)(cid:18)$(cid:18)(cid:19)(cid:11)%(cid:18)(cid:21)(cid:24)(cid:14)(cid:25)(cid:21)(cid:19)(cid:11)%(cid:13)"(cid:14)(cid:11)%(cid:14) (cid:22)%%(cid:10)133)))(cid:28)&(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:28)(cid:19)(cid:21)&3(cid:10)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:18)(cid:24)(cid:12) D e b N N L K E E2 EXPOSED PAD NOTE1 NOTE1 1 2 2 1 D2 TOPVIEW BOTTOMVIEW A A3 A1 NOTE2 4(cid:24)(cid:18)% (cid:17)(cid:27)55(cid:27)(cid:17),(cid:23),(cid:8)(cid:3) (cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)(cid:14)5(cid:18)&(cid:18)% (cid:17)(cid:27)6 67(cid:17) (cid:17)(cid:7)8 6!&((cid:13)(cid:20)(cid:14)(cid:21)$(cid:14)(cid:30)(cid:18)(cid:24) 6 (cid:29)(cid:4) (cid:30)(cid:18)%(cid:19)(cid:22) (cid:13) (cid:4)(cid:28).(cid:4)(cid:14)/(cid:3)0 7(cid:31)(cid:13)(cid:20)(cid:11)(cid:25)(cid:25)(cid:14):(cid:13)(cid:18)(cid:12)(cid:22)% (cid:7) (cid:4)(cid:28)9(cid:4) (cid:4)(cid:28)(cid:6)(cid:4) (cid:29)(cid:28)(cid:4)(cid:4) (cid:3)%(cid:11)(cid:24)"(cid:21)$$(cid:14) (cid:7)(cid:29) (cid:4)(cid:28)(cid:4)(cid:4) (cid:4)(cid:28)(cid:4)(cid:15) (cid:4)(cid:28)(cid:4). 0(cid:21)(cid:24)%(cid:11)(cid:19)%(cid:14)(cid:23)(cid:22)(cid:18)(cid:19)*(cid:24)(cid:13) (cid:7)+ (cid:4)(cid:28)(cid:15)(cid:4)(cid:14)(cid:8),2 7(cid:31)(cid:13)(cid:20)(cid:11)(cid:25)(cid:25)(cid:14)5(cid:13)(cid:24)(cid:12)%(cid:22) (cid:2) +(cid:28)(cid:4)(cid:4)(cid:14)/(cid:3)0 ,#(cid:10)(cid:21) (cid:13)"(cid:14)(cid:30)(cid:11)"(cid:14)5(cid:13)(cid:24)(cid:12)%(cid:22) (cid:2)(cid:15) (cid:15)(cid:28)(cid:15)(cid:4) (cid:15)(cid:28)+. (cid:15)(cid:28)(cid:5)9 7(cid:31)(cid:13)(cid:20)(cid:11)(cid:25)(cid:25)(cid:14);(cid:18)"%(cid:22) , +(cid:28)(cid:4)(cid:4)(cid:14)/(cid:3)0 ,#(cid:10)(cid:21) (cid:13)"(cid:14)(cid:30)(cid:11)"(cid:14);(cid:18)"%(cid:22) ,(cid:15) (cid:29)(cid:28)(cid:5)(cid:4) (cid:29)(cid:28).9 (cid:29)(cid:28)(cid:16). 0(cid:21)(cid:24)%(cid:11)(cid:19)%(cid:14);(cid:18)"%(cid:22) ( (cid:4)(cid:28)(cid:29)9 (cid:4)(cid:28)(cid:15). (cid:4)(cid:28)+(cid:4) 0(cid:21)(cid:24)%(cid:11)(cid:19)%(cid:14)5(cid:13)(cid:24)(cid:12)%(cid:22) 5 (cid:4)(cid:28)+(cid:4) (cid:4)(cid:28)(cid:5)(cid:4) (cid:4)(cid:28).(cid:4) 0(cid:21)(cid:24)%(cid:11)(cid:19)%(cid:9)%(cid:21)(cid:9),#(cid:10)(cid:21) (cid:13)"(cid:14)(cid:30)(cid:11)" = (cid:4)(cid:28)(cid:15)(cid:4) < < (cid:19)(cid:20)(cid:12)(cid:5)(cid:11)’ (cid:29)(cid:28) (cid:30)(cid:18)(cid:24)(cid:14)(cid:29)(cid:14)(cid:31)(cid:18) !(cid:11)(cid:25)(cid:14)(cid:18)(cid:24)"(cid:13)#(cid:14)$(cid:13)(cid:11)%!(cid:20)(cid:13)(cid:14)&(cid:11)(cid:26)(cid:14)(cid:31)(cid:11)(cid:20)(cid:26)’(cid:14)(!%(cid:14)&! %(cid:14)((cid:13)(cid:14)(cid:25)(cid:21)(cid:19)(cid:11)%(cid:13)"(cid:14))(cid:18)%(cid:22)(cid:18)(cid:24)(cid:14)%(cid:22)(cid:13)(cid:14)(cid:22)(cid:11)%(cid:19)(cid:22)(cid:13)"(cid:14)(cid:11)(cid:20)(cid:13)(cid:11)(cid:28) (cid:15)(cid:28) (cid:30)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:13)(cid:14)&(cid:11)(cid:26)(cid:14)(cid:22)(cid:11)(cid:31)(cid:13)(cid:14)(cid:21)(cid:24)(cid:13)(cid:14)(cid:21)(cid:20)(cid:14)&(cid:21)(cid:20)(cid:13)(cid:14)(cid:13)#(cid:10)(cid:21) (cid:13)"(cid:14)%(cid:18)(cid:13)(cid:14)((cid:11)(cid:20) (cid:14)(cid:11)%(cid:14)(cid:13)(cid:24)" (cid:28) +(cid:28) (cid:30)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:13)(cid:14)(cid:18) (cid:14) (cid:11))(cid:14) (cid:18)(cid:24)(cid:12)!(cid:25)(cid:11)%(cid:13)"(cid:28) (cid:5)(cid:28) (cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)(cid:18)(cid:24)(cid:12)(cid:14)(cid:11)(cid:24)"(cid:14)%(cid:21)(cid:25)(cid:13)(cid:20)(cid:11)(cid:24)(cid:19)(cid:18)(cid:24)(cid:12)(cid:14)(cid:10)(cid:13)(cid:20)(cid:14)(cid:7)(cid:3)(cid:17),(cid:14)-(cid:29)(cid:5)(cid:28).(cid:17)(cid:28) /(cid:3)01 /(cid:11) (cid:18)(cid:19)(cid:14)(cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)(cid:28)(cid:14)(cid:23)(cid:22)(cid:13)(cid:21)(cid:20)(cid:13)%(cid:18)(cid:19)(cid:11)(cid:25)(cid:25)(cid:26)(cid:14)(cid:13)#(cid:11)(cid:19)%(cid:14)(cid:31)(cid:11)(cid:25)!(cid:13)(cid:14) (cid:22)(cid:21))(cid:24)(cid:14))(cid:18)%(cid:22)(cid:21)!%(cid:14)%(cid:21)(cid:25)(cid:13)(cid:20)(cid:11)(cid:24)(cid:19)(cid:13) (cid:28) (cid:8),21 (cid:8)(cid:13)$(cid:13)(cid:20)(cid:13)(cid:24)(cid:19)(cid:13)(cid:14)(cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)’(cid:14)! !(cid:11)(cid:25)(cid:25)(cid:26)(cid:14))(cid:18)%(cid:22)(cid:21)!%(cid:14)%(cid:21)(cid:25)(cid:13)(cid:20)(cid:11)(cid:24)(cid:19)(cid:13)’(cid:14)$(cid:21)(cid:20)(cid:14)(cid:18)(cid:24)$(cid:21)(cid:20)&(cid:11)%(cid:18)(cid:21)(cid:24)(cid:14)(cid:10)!(cid:20)(cid:10)(cid:21) (cid:13) (cid:14)(cid:21)(cid:24)(cid:25)(cid:26)(cid:28) (cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:23)(cid:13)(cid:19)(cid:22)(cid:24)(cid:21)(cid:25)(cid:21)(cid:12)(cid:26)(cid:2)(cid:20)(cid:11))(cid:18)(cid:24)(cid:12)0(cid:4)(cid:5)(cid:9)(cid:4)>+/ DS22088C-page 46 © 2009 Microchip Technology Inc.

MCP3422/3/4 .(cid:31)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:8)(cid:17)(cid:10)(cid:6)(cid:12)(cid:18)(cid:8)(cid:19)(cid:20)(cid:8)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:14)(cid:21)(cid:6)(cid:22)(cid:5)(cid:8)(cid:23)(cid:24)(cid:17)(cid:26)(cid:8)(cid:27)(cid:8)(cid:30)(cid:29)(cid:30)(cid:29)(cid:31) !(cid:8)""(cid:8)#(cid:20)(cid:7)$(cid:8)%(cid:15)(cid:17)(cid:19)& (cid:19)(cid:20)(cid:12)(cid:5)’ 2(cid:21)(cid:20)(cid:14)%(cid:22)(cid:13)(cid:14)&(cid:21) %(cid:14)(cid:19)!(cid:20)(cid:20)(cid:13)(cid:24)%(cid:14)(cid:10)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:13)(cid:14)"(cid:20)(cid:11))(cid:18)(cid:24)(cid:12) ’(cid:14)(cid:10)(cid:25)(cid:13)(cid:11) (cid:13)(cid:14) (cid:13)(cid:13)(cid:14)%(cid:22)(cid:13)(cid:14)(cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:14)(cid:30)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:18)(cid:24)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:19)(cid:18)$(cid:18)(cid:19)(cid:11)%(cid:18)(cid:21)(cid:24)(cid:14)(cid:25)(cid:21)(cid:19)(cid:11)%(cid:13)"(cid:14)(cid:11)%(cid:14) (cid:22)%%(cid:10)133)))(cid:28)&(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:28)(cid:19)(cid:21)&3(cid:10)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:18)(cid:24)(cid:12) © 2009 Microchip Technology Inc. DS22088C-page 47

MCP3422/3/4 .(cid:31)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:24)(cid:13)(cid:14)((cid:20)(cid:8))"(cid:6)(cid:10)(cid:10)(cid:8)*(cid:16)(cid:12)(cid:10)(cid:13)+(cid:5)(cid:8)(cid:9)(cid:6)(cid:14)(cid:21)(cid:6)(cid:22)(cid:5)(cid:8)(cid:23)/(cid:19)(cid:26)(cid:8)%(cid:24))*(cid:9)& (cid:19)(cid:20)(cid:12)(cid:5)’ 2(cid:21)(cid:20)(cid:14)%(cid:22)(cid:13)(cid:14)&(cid:21) %(cid:14)(cid:19)!(cid:20)(cid:20)(cid:13)(cid:24)%(cid:14)(cid:10)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:13)(cid:14)"(cid:20)(cid:11))(cid:18)(cid:24)(cid:12) ’(cid:14)(cid:10)(cid:25)(cid:13)(cid:11) (cid:13)(cid:14) (cid:13)(cid:13)(cid:14)%(cid:22)(cid:13)(cid:14)(cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:14)(cid:30)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:18)(cid:24)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:19)(cid:18)$(cid:18)(cid:19)(cid:11)%(cid:18)(cid:21)(cid:24)(cid:14)(cid:25)(cid:21)(cid:19)(cid:11)%(cid:13)"(cid:14)(cid:11)%(cid:14) (cid:22)%%(cid:10)133)))(cid:28)&(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:28)(cid:19)(cid:21)&3(cid:10)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:18)(cid:24)(cid:12) D N E E1 NOTE1 1 2 b e c A A2 φ L A1 L1 4(cid:24)(cid:18)% (cid:17)(cid:27)55(cid:27)(cid:17),(cid:23),(cid:8)(cid:3) (cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)(cid:14)5(cid:18)&(cid:18)% (cid:17)(cid:27)6 67(cid:17) (cid:17)(cid:7)8 6!&((cid:13)(cid:20)(cid:14)(cid:21)$(cid:14)(cid:30)(cid:18)(cid:24) 6 (cid:29)(cid:4) (cid:30)(cid:18)%(cid:19)(cid:22) (cid:13) (cid:4)(cid:28).(cid:4)(cid:14)/(cid:3)0 7(cid:31)(cid:13)(cid:20)(cid:11)(cid:25)(cid:25)(cid:14):(cid:13)(cid:18)(cid:12)(cid:22)% (cid:7) < < (cid:29)(cid:28)(cid:29)(cid:4) (cid:17)(cid:21)(cid:25)"(cid:13)"(cid:14)(cid:30)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:13)(cid:14)(cid:23)(cid:22)(cid:18)(cid:19)*(cid:24)(cid:13) (cid:7)(cid:15) (cid:4)(cid:28)(cid:16). (cid:4)(cid:28)9. (cid:4)(cid:28)(cid:6). (cid:3)%(cid:11)(cid:24)"(cid:21)$$(cid:14) (cid:7)(cid:29) (cid:4)(cid:28)(cid:4)(cid:4) < (cid:4)(cid:28)(cid:29). 7(cid:31)(cid:13)(cid:20)(cid:11)(cid:25)(cid:25)(cid:14);(cid:18)"%(cid:22) , (cid:5)(cid:28)(cid:6)(cid:4)(cid:14)/(cid:3)0 (cid:17)(cid:21)(cid:25)"(cid:13)"(cid:14)(cid:30)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:13)(cid:14);(cid:18)"%(cid:22) ,(cid:29) +(cid:28)(cid:4)(cid:4)(cid:14)/(cid:3)0 7(cid:31)(cid:13)(cid:20)(cid:11)(cid:25)(cid:25)(cid:14)5(cid:13)(cid:24)(cid:12)%(cid:22) (cid:2) +(cid:28)(cid:4)(cid:4)(cid:14)/(cid:3)0 2(cid:21)(cid:21)%(cid:14)5(cid:13)(cid:24)(cid:12)%(cid:22) 5 (cid:4)(cid:28)(cid:5)(cid:4) (cid:4)(cid:28)>(cid:4) (cid:4)(cid:28)9(cid:4) 2(cid:21)(cid:21)%(cid:10)(cid:20)(cid:18)(cid:24)% 5(cid:29) (cid:4)(cid:28)(cid:6).(cid:14)(cid:8),2 2(cid:21)(cid:21)%(cid:14)(cid:7)(cid:24)(cid:12)(cid:25)(cid:13) (cid:3) (cid:4)? < 9? 5(cid:13)(cid:11)"(cid:14)(cid:23)(cid:22)(cid:18)(cid:19)*(cid:24)(cid:13) (cid:19) (cid:4)(cid:28)(cid:4)9 < (cid:4)(cid:28)(cid:15)+ 5(cid:13)(cid:11)"(cid:14);(cid:18)"%(cid:22) ( (cid:4)(cid:28)(cid:29). < (cid:4)(cid:28)++ (cid:19)(cid:20)(cid:12)(cid:5)(cid:11)’ (cid:29)(cid:28) (cid:30)(cid:18)(cid:24)(cid:14)(cid:29)(cid:14)(cid:31)(cid:18) !(cid:11)(cid:25)(cid:14)(cid:18)(cid:24)"(cid:13)#(cid:14)$(cid:13)(cid:11)%!(cid:20)(cid:13)(cid:14)&(cid:11)(cid:26)(cid:14)(cid:31)(cid:11)(cid:20)(cid:26)’(cid:14)(!%(cid:14)&! %(cid:14)((cid:13)(cid:14)(cid:25)(cid:21)(cid:19)(cid:11)%(cid:13)"(cid:14))(cid:18)%(cid:22)(cid:18)(cid:24)(cid:14)%(cid:22)(cid:13)(cid:14)(cid:22)(cid:11)%(cid:19)(cid:22)(cid:13)"(cid:14)(cid:11)(cid:20)(cid:13)(cid:11)(cid:28) (cid:15)(cid:28) (cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24) (cid:14)(cid:2)(cid:14)(cid:11)(cid:24)"(cid:14),(cid:29)(cid:14)"(cid:21)(cid:14)(cid:24)(cid:21)%(cid:14)(cid:18)(cid:24)(cid:19)(cid:25)!"(cid:13)(cid:14)&(cid:21)(cid:25)"(cid:14)$(cid:25)(cid:11) (cid:22)(cid:14)(cid:21)(cid:20)(cid:14)(cid:10)(cid:20)(cid:21)%(cid:20)! (cid:18)(cid:21)(cid:24) (cid:28)(cid:14)(cid:17)(cid:21)(cid:25)"(cid:14)$(cid:25)(cid:11) (cid:22)(cid:14)(cid:21)(cid:20)(cid:14)(cid:10)(cid:20)(cid:21)%(cid:20)! (cid:18)(cid:21)(cid:24) (cid:14) (cid:22)(cid:11)(cid:25)(cid:25)(cid:14)(cid:24)(cid:21)%(cid:14)(cid:13)#(cid:19)(cid:13)(cid:13)"(cid:14)(cid:4)(cid:28)(cid:29).(cid:14)&&(cid:14)(cid:10)(cid:13)(cid:20)(cid:14) (cid:18)"(cid:13)(cid:28) +(cid:28) (cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)(cid:18)(cid:24)(cid:12)(cid:14)(cid:11)(cid:24)"(cid:14)%(cid:21)(cid:25)(cid:13)(cid:20)(cid:11)(cid:24)(cid:19)(cid:18)(cid:24)(cid:12)(cid:14)(cid:10)(cid:13)(cid:20)(cid:14)(cid:7)(cid:3)(cid:17),(cid:14)-(cid:29)(cid:5)(cid:28).(cid:17)(cid:28) /(cid:3)01 /(cid:11) (cid:18)(cid:19)(cid:14)(cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)(cid:28)(cid:14)(cid:23)(cid:22)(cid:13)(cid:21)(cid:20)(cid:13)%(cid:18)(cid:19)(cid:11)(cid:25)(cid:25)(cid:26)(cid:14)(cid:13)#(cid:11)(cid:19)%(cid:14)(cid:31)(cid:11)(cid:25)!(cid:13)(cid:14) (cid:22)(cid:21))(cid:24)(cid:14))(cid:18)%(cid:22)(cid:21)!%(cid:14)%(cid:21)(cid:25)(cid:13)(cid:20)(cid:11)(cid:24)(cid:19)(cid:13) (cid:28) (cid:8),21 (cid:8)(cid:13)$(cid:13)(cid:20)(cid:13)(cid:24)(cid:19)(cid:13)(cid:14)(cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)’(cid:14)! !(cid:11)(cid:25)(cid:25)(cid:26)(cid:14))(cid:18)%(cid:22)(cid:21)!%(cid:14)%(cid:21)(cid:25)(cid:13)(cid:20)(cid:11)(cid:24)(cid:19)(cid:13)’(cid:14)$(cid:21)(cid:20)(cid:14)(cid:18)(cid:24)$(cid:21)(cid:20)&(cid:11)%(cid:18)(cid:21)(cid:24)(cid:14)(cid:10)!(cid:20)(cid:10)(cid:21) (cid:13) (cid:14)(cid:21)(cid:24)(cid:25)(cid:26)(cid:28) (cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:23)(cid:13)(cid:19)(cid:22)(cid:24)(cid:21)(cid:25)(cid:21)(cid:12)(cid:26)(cid:2)(cid:20)(cid:11))(cid:18)(cid:24)(cid:12)0(cid:4)(cid:5)(cid:9)(cid:4)(cid:15)(cid:29)/ DS22088C-page 48 © 2009 Microchip Technology Inc.

MCP3422/3/4 .0(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8))"(cid:6)(cid:10)(cid:10)(cid:8)*(cid:16)(cid:12)(cid:10)(cid:13)+(cid:5)(cid:8)(cid:23))(cid:4)(cid:26)(cid:8)(cid:27)(cid:8)(cid:19)(cid:6)(((cid:20),(cid:18)(cid:8)(cid:30) !(cid:31)(cid:8)""(cid:8)#(cid:20)(cid:7)$(cid:8)%)*-(cid:25)& (cid:19)(cid:20)(cid:12)(cid:5)’ 2(cid:21)(cid:20)(cid:14)%(cid:22)(cid:13)(cid:14)&(cid:21) %(cid:14)(cid:19)!(cid:20)(cid:20)(cid:13)(cid:24)%(cid:14)(cid:10)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:13)(cid:14)"(cid:20)(cid:11))(cid:18)(cid:24)(cid:12) ’(cid:14)(cid:10)(cid:25)(cid:13)(cid:11) (cid:13)(cid:14) (cid:13)(cid:13)(cid:14)%(cid:22)(cid:13)(cid:14)(cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:14)(cid:30)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:18)(cid:24)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:19)(cid:18)$(cid:18)(cid:19)(cid:11)%(cid:18)(cid:21)(cid:24)(cid:14)(cid:25)(cid:21)(cid:19)(cid:11)%(cid:13)"(cid:14)(cid:11)%(cid:14) (cid:22)%%(cid:10)133)))(cid:28)&(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:28)(cid:19)(cid:21)&3(cid:10)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:18)(cid:24)(cid:12) D N E E1 NOTE1 1 2 3 e h b α h c φ A A2 A1 L L1 β 4(cid:24)(cid:18)% (cid:17)(cid:27)55(cid:27)(cid:17),(cid:23),(cid:8)(cid:3) (cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)(cid:14)5(cid:18)&(cid:18)% (cid:17)(cid:27)6 67(cid:17) (cid:17)(cid:7)8 6!&((cid:13)(cid:20)(cid:14)(cid:21)$(cid:14)(cid:30)(cid:18)(cid:24) 6 (cid:29)(cid:5) (cid:30)(cid:18)%(cid:19)(cid:22) (cid:13) (cid:29)(cid:28)(cid:15)(cid:16)(cid:14)/(cid:3)0 7(cid:31)(cid:13)(cid:20)(cid:11)(cid:25)(cid:25)(cid:14):(cid:13)(cid:18)(cid:12)(cid:22)% (cid:7) < < (cid:29)(cid:28)(cid:16). (cid:17)(cid:21)(cid:25)"(cid:13)"(cid:14)(cid:30)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:13)(cid:14)(cid:23)(cid:22)(cid:18)(cid:19)*(cid:24)(cid:13) (cid:7)(cid:15) (cid:29)(cid:28)(cid:15). < < (cid:3)%(cid:11)(cid:24)"(cid:21)$$(cid:14)(cid:14)@ (cid:7)(cid:29) (cid:4)(cid:28)(cid:29)(cid:4) < (cid:4)(cid:28)(cid:15). 7(cid:31)(cid:13)(cid:20)(cid:11)(cid:25)(cid:25)(cid:14);(cid:18)"%(cid:22) , >(cid:28)(cid:4)(cid:4)(cid:14)/(cid:3)0 (cid:17)(cid:21)(cid:25)"(cid:13)"(cid:14)(cid:30)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:13)(cid:14);(cid:18)"%(cid:22) ,(cid:29) +(cid:28)(cid:6)(cid:4)(cid:14)/(cid:3)0 7(cid:31)(cid:13)(cid:20)(cid:11)(cid:25)(cid:25)(cid:14)5(cid:13)(cid:24)(cid:12)%(cid:22) (cid:2) 9(cid:28)>.(cid:14)/(cid:3)0 0(cid:22)(cid:11)&$(cid:13)(cid:20)(cid:14)A(cid:21)(cid:10)%(cid:18)(cid:21)(cid:24)(cid:11)(cid:25)B (cid:22) (cid:4)(cid:28)(cid:15). < (cid:4)(cid:28).(cid:4) 2(cid:21)(cid:21)%(cid:14)5(cid:13)(cid:24)(cid:12)%(cid:22) 5 (cid:4)(cid:28)(cid:5)(cid:4) < (cid:29)(cid:28)(cid:15)(cid:16) 2(cid:21)(cid:21)%(cid:10)(cid:20)(cid:18)(cid:24)% 5(cid:29) (cid:29)(cid:28)(cid:4)(cid:5)(cid:14)(cid:8),2 2(cid:21)(cid:21)%(cid:14)(cid:7)(cid:24)(cid:12)(cid:25)(cid:13) (cid:3) (cid:4)? < 9? 5(cid:13)(cid:11)"(cid:14)(cid:23)(cid:22)(cid:18)(cid:19)*(cid:24)(cid:13) (cid:19) (cid:4)(cid:28)(cid:29)(cid:16) < (cid:4)(cid:28)(cid:15). 5(cid:13)(cid:11)"(cid:14);(cid:18)"%(cid:22) ( (cid:4)(cid:28)+(cid:29) < (cid:4)(cid:28).(cid:29) (cid:17)(cid:21)(cid:25)"(cid:14)(cid:2)(cid:20)(cid:11)$%(cid:14)(cid:7)(cid:24)(cid:12)(cid:25)(cid:13)(cid:14)(cid:23)(cid:21)(cid:10) (cid:4) .? < (cid:29).? (cid:17)(cid:21)(cid:25)"(cid:14)(cid:2)(cid:20)(cid:11)$%(cid:14)(cid:7)(cid:24)(cid:12)(cid:25)(cid:13)(cid:14)/(cid:21)%%(cid:21)& (cid:5) .? < (cid:29).? (cid:19)(cid:20)(cid:12)(cid:5)(cid:11)’ (cid:29)(cid:28) (cid:30)(cid:18)(cid:24)(cid:14)(cid:29)(cid:14)(cid:31)(cid:18) !(cid:11)(cid:25)(cid:14)(cid:18)(cid:24)"(cid:13)#(cid:14)$(cid:13)(cid:11)%!(cid:20)(cid:13)(cid:14)&(cid:11)(cid:26)(cid:14)(cid:31)(cid:11)(cid:20)(cid:26)’(cid:14)(!%(cid:14)&! %(cid:14)((cid:13)(cid:14)(cid:25)(cid:21)(cid:19)(cid:11)%(cid:13)"(cid:14))(cid:18)%(cid:22)(cid:18)(cid:24)(cid:14)%(cid:22)(cid:13)(cid:14)(cid:22)(cid:11)%(cid:19)(cid:22)(cid:13)"(cid:14)(cid:11)(cid:20)(cid:13)(cid:11)(cid:28) (cid:15)(cid:28) @(cid:14)(cid:3)(cid:18)(cid:12)(cid:24)(cid:18)$(cid:18)(cid:19)(cid:11)(cid:24)%(cid:14)0(cid:22)(cid:11)(cid:20)(cid:11)(cid:19)%(cid:13)(cid:20)(cid:18) %(cid:18)(cid:19)(cid:28) +(cid:28) (cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24) (cid:14)(cid:2)(cid:14)(cid:11)(cid:24)"(cid:14),(cid:29)(cid:14)"(cid:21)(cid:14)(cid:24)(cid:21)%(cid:14)(cid:18)(cid:24)(cid:19)(cid:25)!"(cid:13)(cid:14)&(cid:21)(cid:25)"(cid:14)$(cid:25)(cid:11) (cid:22)(cid:14)(cid:21)(cid:20)(cid:14)(cid:10)(cid:20)(cid:21)%(cid:20)! (cid:18)(cid:21)(cid:24) (cid:28)(cid:14)(cid:17)(cid:21)(cid:25)"(cid:14)$(cid:25)(cid:11) (cid:22)(cid:14)(cid:21)(cid:20)(cid:14)(cid:10)(cid:20)(cid:21)%(cid:20)! (cid:18)(cid:21)(cid:24) (cid:14) (cid:22)(cid:11)(cid:25)(cid:25)(cid:14)(cid:24)(cid:21)%(cid:14)(cid:13)#(cid:19)(cid:13)(cid:13)"(cid:14)(cid:4)(cid:28)(cid:29).(cid:14)&&(cid:14)(cid:10)(cid:13)(cid:20)(cid:14) (cid:18)"(cid:13)(cid:28) (cid:5)(cid:28) (cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)(cid:18)(cid:24)(cid:12)(cid:14)(cid:11)(cid:24)"(cid:14)%(cid:21)(cid:25)(cid:13)(cid:20)(cid:11)(cid:24)(cid:19)(cid:18)(cid:24)(cid:12)(cid:14)(cid:10)(cid:13)(cid:20)(cid:14)(cid:7)(cid:3)(cid:17),(cid:14)-(cid:29)(cid:5)(cid:28).(cid:17)(cid:28) /(cid:3)01 /(cid:11) (cid:18)(cid:19)(cid:14)(cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)(cid:28)(cid:14)(cid:23)(cid:22)(cid:13)(cid:21)(cid:20)(cid:13)%(cid:18)(cid:19)(cid:11)(cid:25)(cid:25)(cid:26)(cid:14)(cid:13)#(cid:11)(cid:19)%(cid:14)(cid:31)(cid:11)(cid:25)!(cid:13)(cid:14) (cid:22)(cid:21))(cid:24)(cid:14))(cid:18)%(cid:22)(cid:21)!%(cid:14)%(cid:21)(cid:25)(cid:13)(cid:20)(cid:11)(cid:24)(cid:19)(cid:13) (cid:28) (cid:8),21 (cid:8)(cid:13)$(cid:13)(cid:20)(cid:13)(cid:24)(cid:19)(cid:13)(cid:14)(cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)’(cid:14)! !(cid:11)(cid:25)(cid:25)(cid:26)(cid:14))(cid:18)%(cid:22)(cid:21)!%(cid:14)%(cid:21)(cid:25)(cid:13)(cid:20)(cid:11)(cid:24)(cid:19)(cid:13)’(cid:14)$(cid:21)(cid:20)(cid:14)(cid:18)(cid:24)$(cid:21)(cid:20)&(cid:11)%(cid:18)(cid:21)(cid:24)(cid:14)(cid:10)!(cid:20)(cid:10)(cid:21) (cid:13) (cid:14)(cid:21)(cid:24)(cid:25)(cid:26)(cid:28) (cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:23)(cid:13)(cid:19)(cid:22)(cid:24)(cid:21)(cid:25)(cid:21)(cid:12)(cid:26)(cid:2)(cid:20)(cid:11))(cid:18)(cid:24)(cid:12)0(cid:4)(cid:5)(cid:9)(cid:4)>./ © 2009 Microchip Technology Inc. DS22088C-page 49

MCP3422/3/4 (cid:19)(cid:20)(cid:12)(cid:5)’ 2(cid:21)(cid:20)(cid:14)%(cid:22)(cid:13)(cid:14)&(cid:21) %(cid:14)(cid:19)!(cid:20)(cid:20)(cid:13)(cid:24)%(cid:14)(cid:10)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:13)(cid:14)"(cid:20)(cid:11))(cid:18)(cid:24)(cid:12) ’(cid:14)(cid:10)(cid:25)(cid:13)(cid:11) (cid:13)(cid:14) (cid:13)(cid:13)(cid:14)%(cid:22)(cid:13)(cid:14)(cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:14)(cid:30)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:18)(cid:24)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:19)(cid:18)$(cid:18)(cid:19)(cid:11)%(cid:18)(cid:21)(cid:24)(cid:14)(cid:25)(cid:21)(cid:19)(cid:11)%(cid:13)"(cid:14)(cid:11)%(cid:14) (cid:22)%%(cid:10)133)))(cid:28)&(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:28)(cid:19)(cid:21)&3(cid:10)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:18)(cid:24)(cid:12) DS22088C-page 50 © 2009 Microchip Technology Inc.

MCP3422/3/4 .0(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)12(cid:13)+(cid:8))2((cid:13)+(cid:21)(cid:8))"(cid:6)(cid:10)(cid:10)(cid:8)*(cid:16)(cid:12)(cid:10)(cid:13)+(cid:5)(cid:8)(cid:23))1(cid:26)(cid:8)(cid:27)(cid:8)0 0(cid:8)""(cid:8)#(cid:20)(cid:7)$(cid:8)%1))*(cid:9)& (cid:19)(cid:20)(cid:12)(cid:5)’ 2(cid:21)(cid:20)(cid:14)%(cid:22)(cid:13)(cid:14)&(cid:21) %(cid:14)(cid:19)!(cid:20)(cid:20)(cid:13)(cid:24)%(cid:14)(cid:10)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:13)(cid:14)"(cid:20)(cid:11))(cid:18)(cid:24)(cid:12) ’(cid:14)(cid:10)(cid:25)(cid:13)(cid:11) (cid:13)(cid:14) (cid:13)(cid:13)(cid:14)%(cid:22)(cid:13)(cid:14)(cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:14)(cid:30)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:18)(cid:24)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:19)(cid:18)$(cid:18)(cid:19)(cid:11)%(cid:18)(cid:21)(cid:24)(cid:14)(cid:25)(cid:21)(cid:19)(cid:11)%(cid:13)"(cid:14)(cid:11)%(cid:14) (cid:22)%%(cid:10)133)))(cid:28)&(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:28)(cid:19)(cid:21)&3(cid:10)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:18)(cid:24)(cid:12) D N E E1 NOTE1 1 2 e b c φ A A2 A1 L1 L 4(cid:24)(cid:18)% (cid:17)(cid:27)55(cid:27)(cid:17),(cid:23),(cid:8)(cid:3) (cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)(cid:14)5(cid:18)&(cid:18)% (cid:17)(cid:27)6 67(cid:17) (cid:17)(cid:7)8 6!&((cid:13)(cid:20)(cid:14)(cid:21)$(cid:14)(cid:30)(cid:18)(cid:24) 6 (cid:29)(cid:5) (cid:30)(cid:18)%(cid:19)(cid:22) (cid:13) (cid:4)(cid:28)>.(cid:14)/(cid:3)0 7(cid:31)(cid:13)(cid:20)(cid:11)(cid:25)(cid:25)(cid:14):(cid:13)(cid:18)(cid:12)(cid:22)% (cid:7) < < (cid:29)(cid:28)(cid:15)(cid:4) (cid:17)(cid:21)(cid:25)"(cid:13)"(cid:14)(cid:30)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:13)(cid:14)(cid:23)(cid:22)(cid:18)(cid:19)*(cid:24)(cid:13) (cid:7)(cid:15) (cid:4)(cid:28)9(cid:4) (cid:29)(cid:28)(cid:4)(cid:4) (cid:29)(cid:28)(cid:4). (cid:3)%(cid:11)(cid:24)"(cid:21)$$(cid:14) (cid:7)(cid:29) (cid:4)(cid:28)(cid:4). < (cid:4)(cid:28)(cid:29). 7(cid:31)(cid:13)(cid:20)(cid:11)(cid:25)(cid:25)(cid:14);(cid:18)"%(cid:22) , >(cid:28)(cid:5)(cid:4)(cid:14)/(cid:3)0 (cid:17)(cid:21)(cid:25)"(cid:13)"(cid:14)(cid:30)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:13)(cid:14);(cid:18)"%(cid:22) ,(cid:29) (cid:5)(cid:28)+(cid:4) (cid:5)(cid:28)(cid:5)(cid:4) (cid:5)(cid:28).(cid:4) (cid:17)(cid:21)(cid:25)"(cid:13)"(cid:14)(cid:30)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:13)(cid:14)5(cid:13)(cid:24)(cid:12)%(cid:22) (cid:2) (cid:5)(cid:28)(cid:6)(cid:4) .(cid:28)(cid:4)(cid:4) .(cid:28)(cid:29)(cid:4) 2(cid:21)(cid:21)%(cid:14)5(cid:13)(cid:24)(cid:12)%(cid:22) 5 (cid:4)(cid:28)(cid:5). (cid:4)(cid:28)>(cid:4) (cid:4)(cid:28)(cid:16). 2(cid:21)(cid:21)%(cid:10)(cid:20)(cid:18)(cid:24)% 5(cid:29) (cid:29)(cid:28)(cid:4)(cid:4)(cid:14)(cid:8),2 2(cid:21)(cid:21)%(cid:14)(cid:7)(cid:24)(cid:12)(cid:25)(cid:13) (cid:3) (cid:4)? < 9? 5(cid:13)(cid:11)"(cid:14)(cid:23)(cid:22)(cid:18)(cid:19)*(cid:24)(cid:13) (cid:19) (cid:4)(cid:28)(cid:4)(cid:6) < (cid:4)(cid:28)(cid:15)(cid:4) 5(cid:13)(cid:11)"(cid:14);(cid:18)"%(cid:22) ( (cid:4)(cid:28)(cid:29)(cid:6) < (cid:4)(cid:28)+(cid:4) (cid:19)(cid:20)(cid:12)(cid:5)(cid:11)’ (cid:29)(cid:28) (cid:30)(cid:18)(cid:24)(cid:14)(cid:29)(cid:14)(cid:31)(cid:18) !(cid:11)(cid:25)(cid:14)(cid:18)(cid:24)"(cid:13)#(cid:14)$(cid:13)(cid:11)%!(cid:20)(cid:13)(cid:14)&(cid:11)(cid:26)(cid:14)(cid:31)(cid:11)(cid:20)(cid:26)’(cid:14)(!%(cid:14)&! %(cid:14)((cid:13)(cid:14)(cid:25)(cid:21)(cid:19)(cid:11)%(cid:13)"(cid:14))(cid:18)%(cid:22)(cid:18)(cid:24)(cid:14)%(cid:22)(cid:13)(cid:14)(cid:22)(cid:11)%(cid:19)(cid:22)(cid:13)"(cid:14)(cid:11)(cid:20)(cid:13)(cid:11)(cid:28) (cid:15)(cid:28) (cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24) (cid:14)(cid:2)(cid:14)(cid:11)(cid:24)"(cid:14),(cid:29)(cid:14)"(cid:21)(cid:14)(cid:24)(cid:21)%(cid:14)(cid:18)(cid:24)(cid:19)(cid:25)!"(cid:13)(cid:14)&(cid:21)(cid:25)"(cid:14)$(cid:25)(cid:11) (cid:22)(cid:14)(cid:21)(cid:20)(cid:14)(cid:10)(cid:20)(cid:21)%(cid:20)! (cid:18)(cid:21)(cid:24) (cid:28)(cid:14)(cid:17)(cid:21)(cid:25)"(cid:14)$(cid:25)(cid:11) (cid:22)(cid:14)(cid:21)(cid:20)(cid:14)(cid:10)(cid:20)(cid:21)%(cid:20)! (cid:18)(cid:21)(cid:24) (cid:14) (cid:22)(cid:11)(cid:25)(cid:25)(cid:14)(cid:24)(cid:21)%(cid:14)(cid:13)#(cid:19)(cid:13)(cid:13)"(cid:14)(cid:4)(cid:28)(cid:29).(cid:14)&&(cid:14)(cid:10)(cid:13)(cid:20)(cid:14) (cid:18)"(cid:13)(cid:28) +(cid:28) (cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)(cid:18)(cid:24)(cid:12)(cid:14)(cid:11)(cid:24)"(cid:14)%(cid:21)(cid:25)(cid:13)(cid:20)(cid:11)(cid:24)(cid:19)(cid:18)(cid:24)(cid:12)(cid:14)(cid:10)(cid:13)(cid:20)(cid:14)(cid:7)(cid:3)(cid:17),(cid:14)-(cid:29)(cid:5)(cid:28).(cid:17)(cid:28) /(cid:3)01 /(cid:11) (cid:18)(cid:19)(cid:14)(cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)(cid:28)(cid:14)(cid:23)(cid:22)(cid:13)(cid:21)(cid:20)(cid:13)%(cid:18)(cid:19)(cid:11)(cid:25)(cid:25)(cid:26)(cid:14)(cid:13)#(cid:11)(cid:19)%(cid:14)(cid:31)(cid:11)(cid:25)!(cid:13)(cid:14) (cid:22)(cid:21))(cid:24)(cid:14))(cid:18)%(cid:22)(cid:21)!%(cid:14)%(cid:21)(cid:25)(cid:13)(cid:20)(cid:11)(cid:24)(cid:19)(cid:13) (cid:28) (cid:8),21 (cid:8)(cid:13)$(cid:13)(cid:20)(cid:13)(cid:24)(cid:19)(cid:13)(cid:14)(cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)’(cid:14)! !(cid:11)(cid:25)(cid:25)(cid:26)(cid:14))(cid:18)%(cid:22)(cid:21)!%(cid:14)%(cid:21)(cid:25)(cid:13)(cid:20)(cid:11)(cid:24)(cid:19)(cid:13)’(cid:14)$(cid:21)(cid:20)(cid:14)(cid:18)(cid:24)$(cid:21)(cid:20)&(cid:11)%(cid:18)(cid:21)(cid:24)(cid:14)(cid:10)!(cid:20)(cid:10)(cid:21) (cid:13) (cid:14)(cid:21)(cid:24)(cid:25)(cid:26)(cid:28) (cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:23)(cid:13)(cid:19)(cid:22)(cid:24)(cid:21)(cid:25)(cid:21)(cid:12)(cid:26)(cid:2)(cid:20)(cid:11))(cid:18)(cid:24)(cid:12)0(cid:4)(cid:5)(cid:9)(cid:4)9(cid:16)/ © 2009 Microchip Technology Inc. DS22088C-page 51

MCP3422/3/4 NOTES: DS22088C-page 52 © 2009 Microchip Technology Inc.

MCP3422/3/4 APPENDIX A: REVISION HISTORY Revision C (August 2009) The following is the list of modifications: 1. Updated the EDS protection parameters. 2. Updated the package marking information and package outline drawings. Revision B (October 2008) The following is the list of modifications: 1. Added MCP3422 and MCP3423 devices throughout this data sheet. 2. Added new package marking information and package outline drawings for MCP3422 and MCP3423 devices. 3. Added MCP3422 and MCP3423 devices to Product Identification System page. Revision A (June 2008) • Original Release of this Document. © 2009 Microchip Technology Inc. DS22088C-page 53

MCP3422/3/4 NOTES: DS22088C-page 54 © 2009 Microchip Technology Inc.

MCP3422/3/4 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. XX X X /XX Examples: Device Address Tape and Temperature Package MCP3422 Options Reel Range a) MCP3422A0-E/MC: 2-Channel ADC, A0 Address Option, Device: MCP3422: 2-Channel 18-Bit ADC 8LD DFN package. MCP3423: 2-Channel 18-Bit ADC b) MCP3422A0T-E/MC:Tape and Reel, MCP3424: 4-Channel 18-Bit ADC 2-Channel ADC, A0 Address Option, Address Options: XX = Address Options. Refer to table below. 8LD DFN package. For MCP3422 only. c) MCP3422A0-E/MS: 2-Channel ADC, A0 Address Option, 8LD MSOP package. Tape and Reel T = Tape and Reel d) MCP3422A0T-E/MS: Tape and Reel, 2-Channel ADC, Temperature Range: E = -40°C to +125°C A0 Address Option, 8LD MSOP package. Package: MC = Plastic Dual Flat, No Lead (2x3 DFN), 8-lead e) MCP3422A0-E/SN: 2-Channel ADC, MF = Plastic Dual Flat, No Lead (3x3 DFN) 10-lead A0 Address Option, MS = Plastic Micro Small Outline (MSOP), 8-lead 8LD SOIC package. SL = Plastic SOIC (150 mil Body), 14-lead f) MCP3422A0T-E/SN: Tape and Reel, SN = Plastic SOIC (3.90mm Body), 8-lead, ST = Plastic TSSOP (4.4mm Body), 14-lead 2-Channel ADC, UN = Plastic Micro Small Outline (MSOP), 10-lead A0 Address Option, 8LD SOIC package. Address Options for MCP3422: MCP3423 a) MCP3423-E/MF: 2-Channel ADC, Address Options 10LD DFN package. b) MCP3423T-E/MF: Tape and Reel, * XX A2 A1 A0 2-Channel ADC, A0 * = 0 0 0 10LD DFN package. A1 = 0 0 1 c) MCP3423-E/UN: 2-Channel ADC, 10LD MSOP pkg. A2 = 0 1 0 d) MCP3423T-E/UN: Tape and Reel, A3 = 0 1 1 2-Channel ADC, A4 = 1 0 0 10LD MSOP pkg. A5 = 1 0 1 MCP3424 A6 = 1 1 0 a) MCP3424-E/SL: 4-Channel ADC, A7 = 1 1 1 14LD SOIC package. * Default option. Contact Microchip factory for other address b) MCP3424T-E/SL: Tape and Reel, options. 4-Channel ADC, 14LD SOIC package. c) MCP3424-E/ST: 4-Channel ADC, 14LD TSSOP pkg. d) MCP3424T-E/ST: Tape and Reel, 4-Channel ADC, 14LD TSSOP pkg. © 2009 Microchip Technology Inc. DS22088C-page 55

MCP3422/3/4 NOTES: DS22088C-page 56 © 2009 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. rfPIC and UNI/O are registered trademarks of Microchip MICROCHIP MAKES NO REPRESENTATIONS OR Technology Incorporated in the U.S.A. and other countries. WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, OTHERWISE, RELATED TO THE INFORMATION, MXDEV, MXLAB, SEEVAL and The Embedded Control INCLUDING BUT NOT LIMITED TO ITS CONDITION, Solutions Company are registered trademarks of Microchip QUALITY, PERFORMANCE, MERCHANTABILITY OR Technology Incorporated in the U.S.A. FITNESS FOR PURPOSE. Microchip disclaims all liability Analog-for-the-Digital Age, Application Maestro, CodeGuard, arising from this information and its use. Use of Microchip dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, devices in life support and/or safety applications is entirely at ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial the buyer’s risk, and the buyer agrees to defend, indemnify and Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB hold harmless Microchip from any and all damages, claims, Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code suits, or expenses resulting from such use. No licenses are Generation, PICC, PICC-18, PICkit, PICDEM, PICDEM.net, conveyed, implicitly or otherwise, under any Microchip PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total intellectual property rights. Endurance, TSHARC, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2009 Microchip Technology Inc. DS22088C-page 57

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: MCP3422A4-E/MS MCP3422A6-E/MC MCP3422A5T-E/MC MCP3422A2T-E/MC MCP3422A7-E/MS MCP3422A3- E/MS MCP3422A6T-E/MS MCP3422A2-E/MC MCP3422A4-E/MC MCP3422A5-E/MC MCP3422A7-E/MC MCP3422A5-E/MS MCP3422A3-E/SN MCP3422A7T-E/MC MCP3422A2T-E/SN MCP3422A2T-E/MS MCP3422A4T- E/SN MCP3422A5T-E/MS MCP3422A3T-E/SN MCP3422A5T-E/SN MCP3422A6-E/MS MCP3422A4-E/SN MCP3422A7-E/SN MCP3422A7T-E/MS MCP3422A3T-E/MC MCP3422A5-E/SN MCP3422A4T-E/MS MCP3422A6- E/SN MCP3422A2-E/SN MCP3422A7T-E/SN MCP3422A2-E/MS MCP3422A3T-E/MS MCP3422A6T-E/MC MCP3422A3-E/MC MCP3422A6T-E/SN MCP3422A4T-E/MC