M MCP3302/04 13-Bit Differential Input, Low Power A/D Converter with SPI™ Serial Interface Features General Description • Full Differential Inputs The Microchip Technology Inc. MCP3302/04 13-bit A/D • MCP3302: 2 Differential or 4 Single ended Inputs converters feature full differential inputs and low power consumption in a small package that is ideal for battery • MCP3304: 4 Differential or 8 Single ended Inputs powered systems and remote data acquisition applica- • ±1LSB max DNL tions. The MCP3302 is programmable to provide two • ±1LSB max INL (MCP3302/04-B) differential input pairs or four single ended inputs. The • ±2LSB max INL (MCP3302/04-C) MCP3304 is programmable and provides four differen- • Single supply operation: 2.7V to 5.5V tial input pairs or eight single ended inputs. • 100ksps sampling rate with 5V supply voltage Incorporating a successive approximation architecture • 50ksps sampling rate with 2.7V supply voltage with on-board sample and hold circuitry, these 13-bit • 50nA typical standby current, 1µA max A/D converters are specified to have ±1LSB Differen- tial Nonlinearity (DNL); ±1LSB Integral Nonlinearity • 450µA max active current at 5V (INL) for B-grade and ±2LSB for C-grade devices. The • Industrial temp range: -40°C to +85°C industry-standard SPI™ serial interface enables 13-bit • 14 and 16-pin PDIP, SOIC and TSSOP packages A/D converter capability to be added to any PICmicro® • MXDEVTM Evaluation kit available microcontroller. The MCP3302/04 devices feature low current design Applications that permits operation with typical standby and active • Remote Sensors currents of only 50nA and 300µA, respectively. The devices operate over a broad voltage range of 2.7V to • Battery Operated Systems 5.5V and are capable of conversion rates of up to • Transducer Interface 100ksps. The reference voltage can be varied from 400mV to 5V, yielding input-referred resolution Package Types between 98µV and 1.22mV. PDIP, SOIC, TSSOP The MCP3302 is available in 14-pin PDIP, 150mil CH0 1 14 VDD SOIC and TSSOP packages. The MCP3304 is avail- CH1 2 M 13 VREF able in 16-pin PDIP and 150mil SOIC packages. The CH2 3 C 12 AGND full differential inputs of these devices enable a wide CH3 4 P3 11 CLK variety of signals to be used in applications such as NC 5 30 10 DOUT remote data acquisition, portable instrumentation and NC 6 2 9 DIN battery operated applications. DGND 7 8 CS/SHDN PDIP, SOIC CH0 1 16 V DD CH1 2 15 VREF M CH2 3 14 AGND C CH3 4 P 13 CLK CH4 5 33 12 DOUT CH5 6 04 11 DIN CH6 7 10 CS/SHDN CH7 8 9 DGND  2002 Microchip Technology Inc. DS21697B-page 1

MCP3302/04 Functional Block Diagram VREF VDD AGNDDGND CH0 CH1 Input Channel Mux CH7* CDAC Comparator Sample - & Hold 13-Bit SAR Circuits + Shift Control Logic Register CS/SHDN DIN CLK DOUT * Channels 5-7 available on MCP3304 Only DS21697B-page 2  2002 Microchip Technology Inc.

MCP3302/04 1.0 ELECTRICAL PIN FUNCTION TABLE CHARACTERISTICS Name Function Maximum Ratings* CH0-CH7 Analog Inputs V ........................................................................7.0V DGND Digital Ground DD CS/SHDN Chip Select / Shutdown Input All inputs and outputs w.r.t. V .....-0.3V to V +0.3V SS DD D Serial Data In Storage temperature..........................-65°C to +150°C IN D Serial Data Out Ambient temp. with power applied.....-65°C to +125°C OUT CLK Serial Clock Maximum Junction Temperature .......................150°C AGND Analog Ground ESD protection on all pins (HBM).........................> 4kV V Reference Voltage Input REF *Notice: Stresses above those listed under “Maximum rat- V +2.7V to 5.5V Power Supply ings” may cause permanent damage to the device. This is a DD stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Expo- sure to maximum rating conditions for extended periods may affect device reliability. ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise noted, all parameters apply at V = 5V, V = 0V, and V = 5V. Full differential DD SS REF input configuration (Figure3-4) with fixed common mode voltage of 2.5V. All parameters apply over temperature with T = -40°C to +85°C (Note7). Conversion speed (F ) is 100ksps with F = 21*F AMB SAMPLE CLK SAMPLE Parameter Symbol Min Typ Max Units Conditions Conversion Rate Maximum Sampling Frequency F — — 100 ksps Note8 SAMPLE — — 50 ksps V = V = 2.7V, V =1.35V DD REF CM Conversion Time T 13 CLK CONV periods Acquisition Time T 1.5 CLK ACQ periods DC Accuracy Resolution 12 data bits + sign bits Integral Nonlinearity INL — ±0.5 ±1 LSB MCP3302/04-B — ±1 ±2 LSB MCP3302/04-C Differential Nonlinearity DNL — ±0.5 ±1 LSB Monotonic over temperature Positive Gain Error -3 -0.75 +2 LSB Negative Gain Error -3 -0.5 +2 LSB Offset Error -3 +3 +6 LSB Note 1: This specification is established by characterization and not 100% tested. 2: See characterization graphs that relate converter performance to V level. REF 3: V = 0.1V to 4.9V @ 1kHz. IN 4: V =5V ±500mV @ 1kHz, see test circuit Figure3-3. DD P-P 5: Maximum clock frequency specification must be met. 6: V = 400mV, V = 0.1V to 4.9V @ 1kHz REF IN 7: TSSOP devices are only specified at 25°C and +85°C. 8: For slow sample rates, see Section 6.2.1 for limitations on clock frequency.  2002 Microchip Technology Inc. DS21697B-page 3

MCP3302/04 ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise noted, all parameters apply at V = 5V, V = 0V, and V = 5V. Full differential DD SS REF input configuration (Figure3-4) with fixed common mode voltage of 2.5V. All parameters apply over temperature with T = -40°C to +85°C (Note7). Conversion speed (F ) is 100ksps with F = 21*F AMB SAMPLE CLK SAMPLE Parameter Symbol Min Typ Max Units Conditions Dynamic Performance Total Harmonic Distortion THD — -91 — dB Note3 Signal to Noise and Distortion SINAD — 78 — dB Note3 Spurious Free Dynamic Range SFDR — 92 — dB Note3 Common Mode Rejection CMRR — 79 — dB Note6 Channel to Channel Crosstalk CT — > -110 — dB Note6 Power Supply Rejection PSR — 74 — dB Note4 Reference Input Voltage Range 0.4 — V V Note2 DD Current Drain — 100 150 µA — 0.001 3 µA CS = V = 5V DD Analog Inputs Full Scale Input Span CH0 - CH7 -V — V V REF REF Absolute Input Voltage CH0 - CH7 -0.3 — V + 0.3 V DD Leakage Current — 0.001 ±1 µA Switch Resistance R — 1 — kΩ See Figure6-3 S Sample Capacitor C — 25 — pF See Figure6-3 SAMPLE Digital Input/Output Data Coding Format Binary Two’s Complement High Level Input Voltage V 0.7 V — — V IH DD Low Level Input Voltage V — — 0.3 V V IL DD High Level Output Voltage V 4.1 — — V I = -1mA, V = 4.5V OH OH DD Low Level Output Voltage V — — 0.4 V I = 1mA, V = 4.5V OL OL DD Input Leakage Current I -10 — 10 µA V = V or V LI IN SS DD Output Leakage Current I -10 — 10 µA V = V or V LO OUT SS DD Pin Capacitance C , C — — 10 pF T = 25°C, F = 1MHz, Note1 IN OUT AMB Note 1: This specification is established by characterization and not 100% tested. 2: See characterization graphs that relate converter performance to V level. REF 3: V = 0.1V to 4.9V @ 1kHz. IN 4: V =5V ±500mV @ 1kHz, see test circuit Figure3-3. DD P-P 5: Maximum clock frequency specification must be met. 6: V = 400mV, V = 0.1V to 4.9V @ 1kHz REF IN 7: TSSOP devices are only specified at 25°C and +85°C. 8: For slow sample rates, see Section 6.2.1 for limitations on clock frequency. DS21697B-page 4  2002 Microchip Technology Inc.

MCP3302/04 ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise noted, all parameters apply at V = 5V, V = 0V, and V = 5V. Full differential DD SS REF input configuration (Figure3-4) with fixed common mode voltage of 2.5V. All parameters apply over temperature with T = -40°C to +85°C (Note7). Conversion speed (F ) is 100ksps with F = 21*F AMB SAMPLE CLK SAMPLE Parameter Symbol Min Typ Max Units Conditions Timing Specifications: Clock Frequency (Note 8) F 0.105 — 2.1 MHz V = 5V, F = 100ksps CLK DD SAMPLE 0.105 — 1.05 MHz V = 2.7V, F = 50ksps DD SAMPLE Clock High Time T 210 — — ns Note5 HI Clock Low Time T 210 — — ns Note5 LO CS Fall To First Rising CLK Edge T 100 — — ns SUCS Data In Setup time T 50 — — ns SU Data In Hold Time T — — 50 ns HD CLK Fall To Output Data Valid T — — 125 ns V = 5V, see Figure3-1 DO DD 200 ns V = 2.7V, see Figure3-1 DD CLK Fall To Output Enable T — — 125 ns V = 5V, see Figure3-1 EN DD 200 ns V = 2.7V, see Figure3-1 DD CS Rise To Output Disable T — — 100 ns See test circuits, Figure3-1 DIS Note1 CS Disable Time T 475 — — ns CSH D Rise Time T — — 100 ns See test circuits, Figure3-1 OUT R Note1 D Fall Time T — — 100 ns See test circuits, Figure3-1 OUT F Note1 Power Requirements: Operating Voltage V 2.7 — 5.5 V DD Operating Current I — 300 450 µA V , V = 5V, D unloaded DD DD REF OUT — 200 — V , V = 2.7V, D unloaded DD REF OUT Standby Current I — 0.05 1 µA CS = V = 5.0V DDS DD Temperature Ranges: Specified Temperature Range T -40 — +85 °C A Operating Temperature Range T -40 — +85 °C A Storage Temperature Range T -65 — +150 °C A Thermal Package Resistance: Thermal Resistance, 14L-PDIP θ — 70 — °C/W JA Thermal Resistance, 14L-SOIC θ — 108 — °C/W JA Thermal Resistance, 14L-TSSOP θ — 100 — °C/W JA Thermal Resistance, 16L-PDIP θ — 70 — °C/W JA Thermal Resistance, 16L-SOIC θ — 90 — °C/W JA Note 1: This specification is established by characterization and not 100% tested. 2: See characterization graphs that relate converter performance to V level. REF 3: V = 0.1V to 4.9V @ 1kHz. IN 4: V =5V ±500mV @ 1kHz, see test circuit Figure3-3. DD P-P 5: Maximum clock frequency specification must be met. 6: V = 400mV, V = 0.1V to 4.9V @ 1kHz REF IN 7: TSSOP devices are only specified at 25°C and +85°C. 8: For slow sample rates, see Section 6.2.1 for limitations on clock frequency.  2002 Microchip Technology Inc. DS21697B-page 5

MCP3302/04 . T CSH CS T SUCS THI TLO CLK TSU THD DIN MSB IN T TDO TR TF TDIS EN DOUT Null Bit Sign BIT LSB FIGURE 1-1: Timing Parameters DS21697B-page 6  2002 Microchip Technology Inc.

MCP3302/04 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, V = V = 5V, Full differential input configuration, V = 0V, DD REF SS F = 100ksps, F = 21*F , T = 25°C. SAMPLE CLK SAMPLE A . . 1 1 0.8 0.8 VDD=VREF=2.7V 0.6 0.6 0.4 Positive INL 0.4 Positive INL B) 0.2 B) 0.2 S S INL (L-0.20 INL (L-0.02 -0.4 Negative INL -0.4 Negative INL -0.6 -0.6 -0.8 -0.8 -1 -1 0 50 100 150 200 0 10 20 30 40 50 60 70 Sample Rate (ksps) Sample Rate (ksps) FIGURE 2-1: Integral Nonlinearity (INL) FIGURE 2-4: Integral Nonlinearity (INL) vs. Sample Rate vs. Sample Rate (V = 2.7V) DD . 2 2 VDD = 2.7V 1.5 1.5 1 1 Positive INL INL (LSB)-00..055 PNoesgitaivteiv eIN ILNL INL(LSB)-00..055 -1 -1 Negative INL -1.5 -1.5 -2 -2 0 1 2 3 4 5 0 0.5 1 1.5 2 2.5 3 VREF(V) VREF(V) FIGURE 2-2: Integral Nonlinearity (INL) FIGURE 2-5: Integral Nonlinearity (INL) vs. V vs. V (V = 2.7V) REF. REF DD 1 1 0.8 0.8 VFSDADM=PVLREE =F= 520. 7kVsps 0.6 0.6 0.4 0.4 B) 0.2 B) 0.2 S S L (L 0 L (L 0 N-0.2 N-0.2 I I -0.4 -0.4 -0.6 -0.6 -0.8 -0.8 -1 -1 -4096 -3072 -2048 -1024 0 1024 2048 3072 4096 -4096 -3072 -2048 -1024 0 1024 2048 3072 4096 Code Code FIGURE 2-3: Integral Nonlinearity (INL) FIGURE 2-6: Integral Nonlinearity (INL) vs. Code (Representative Part). vs. Code (Representative Part, V = 2.7V). DD  2002 Microchip Technology Inc. DS21697B-page 7

MCP3302/04 Note: Unless otherwise indicated, V = V = 5V, Full differential input configuration, V = 0V, DD REF SS F = 100ksps, F = 21*F , T = 25°C. SAMPLE CLK SAMPLE A 1 1 VDD=VREF=2.7V 0.8 0.8 FSAMPLE = 50 ksps 0.6 0.6 Positive INL 0.4 Positive INL 0.4 B) 0.2 B) 0.2 S S L (L 0 L (L 0 IN -0.2 IN -0.2 -0.4 Negative INL -0.4 -0.6 -0.6 Negative INL -0.8 -0.8 -1 -1 -50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150 Temperature(°C) Temperature (°C) FIGURE 2-7: Integral Nonlinearity (INL) FIGURE 2-10: Integral Nonlinearity (INL) vs. Temperature. vs. Temperature (V = 2.7V). DD 1 1 0.8 0.8 VDD=VREF=2.7V 0.6 0.6 0.4 Positive DNL 0.4 Positive DNL DNL (LSB) -00..202 DNL (LSB) -00..202 -0.4 Negative DNL -0.4 Negative DNL -0.6 -0.6 -0.8 -0.8 -1 -1 0 10 20 30 40 50 60 70 0 50 100 150 200 Sample Rate (ksps) Sample Rate (ksps) FIGURE 2-8: Differential Nonlinearity FIGURE 2-11: Differential Nonlinearity (DNL) vs. Sample Rate. (DNL) vs. Sample Rate (V = 2.7V). DD 2 2 VDD=2.7V 1.5 1.5 FSAMPLE = 50 ksps 1 1 Positive DNL B) 0.5 Positive DNL B) 0.5 DNL(LS -0.05 Negative DNL DNL (LS -0.05 Negative DNL -1 -1 -1.5 -1.5 -2 -2 0 1 2 3 4 5 6 0 0.5 1 1.5 2 2.5 3 VREF(V) VREF (V) FIGURE 2-9: Differential Nonlinearity FIGURE 2-12: Differential Nonlinearity (DNL) vs. V . (DNL) vs. V (V = 2.7V).] REF REF DD DS21697B-page 8  2002 Microchip Technology Inc.

MCP3302/04 Note: Unless otherwise indicated, V = V = 5V, Full differential input configuration, V = 0V, DD REF SS F = 100ksps, F = 21*F , T = 25°C. SAMPLE CLK SAMPLE A 1 1 0.8 VDD=VREF=2.7V 0.6 0.8 FSAMPLE = 50 ksps 0.6 0.4 0.4 DNL (LSB) -00..202 DNL (LSB)-00..022 -0.4 -0.4 -0.6 -0.6 -0.8 -0.8 -1 -1 -4096 -3072 -2048 -1024 0 1024 2048 3072 4096 -4096 -3072 -2048 -1024 0 1024 2048 3072 4096 Code Code FIGURE 2-13: Differential Nonlinearity FIGURE 2-16: Differential Nonlinearity (DNL) vs. Code (Representative Part). (DNL) vs. Code (Representative Part, V = 2.7V). DD 1 1 0.8 0.8 VFSDADM=PVLRE E=F =520. 7kVsps 0.6 0.6 0.4 Positive DNL 0.4 Positive DNL B) 0.2 B)0.2 S S L (L 0 L (L 0 DN -0.2 DN-0.2 -0.4 Negaitive DNL -0.4 Negative DNL -0.6 -0.6 -0.8 -0.8 -1 -1 -50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150 Temperature (°C) Temperature (°C) FIGURE 2-14: Differential Nonlinearity FIGURE 2-17: Differential Nonlinearity (DNL) vs. Temperature. (DNL) vs. Temperature (V = 2.7V). DD 4 20 18 3 B) 16 S sitive Gain Error (L -1012 VFSDADM=P5LVE = 100 ksps Offset Error (LSB)11168024 VFSDADM =P L5EV = 100 ksps Po 4 -2 2 VDD = 2.7V -3 0 FSAMPLE = 50 ksps 0 1 2 3 4 5 6 0 1 2 3 4 5 6 VREF(V) VREF(V) FIGURE 2-15: Positive Gain Error vs. FIGURE 2-18: Offset Error vs. V . REF V . REF  2002 Microchip Technology Inc. DS21697B-page 9

MCP3302/04 Note: Unless otherwise indicated, V = V = 5V, Full differential input configuration, V = 0V, DD REF SS F = 100ksps, F = 21*F , T = 25°C. SAMPLE CLK SAMPLE A 0 3.5 -0.2 3 VFSDADM=PVLRE E=F =150V0 ksps B) -0.4 VDD=VREF=5V Positive Gain Error (LS ----1100-....14286 VDD=VREF=2.7V FSAMPLE = 100 ksps Offset Error (LSB) 012...12555 VFSDADM=PVLREE =F =520. 7kVsps -1.6 FSAMPLE = 50 ksps 0 -1.8 -50 0 50 100 150 -50 0 50 100 150 Temperature (°C) Temperature (°C) FIGURE 2-19: Positive Gain Error vs. FIGURE 2-22: Offset Error vs. Temperature. Temperature. 100 90 VDD=VREF=5V 90 FSAMPLE = 100 ksps 80 80 70 NR (db) 567000 VFSDADM=PVLRE E=F =520. 7kVsps NAD (dB) 456000 VFSDADM=PVLRE E=F =520. 7kVsps VFSDADM=PVLRE E=F =150V0 ksps S 40 SI 30 30 20 20 10 10 0 0 1 10 100 1 10 100 Input Frequency (kHz) Input Frequency (kHz) FIGURE 2-20: Signal to Noise Ratio (SNR) FIGURE 2-23: Signal to Noise and vs. Input Frequency. Distortion (SINAD) vs. Input Frequency. 0 80 -10 70 -20 60 -30 THD (dB) ---654000 VFSDADM=PVLREE =F =520. 7kVsps VFSDADM=PVLRE E=F =150V0 ksps SINAD (dB) 345000 VDD=VREF=2.7V VDD=VREF=5V -70 FSAMPLE = 50 ksps FSAMPLE = 100 ksps 20 -80 10 -90 -100 0 1 10 100 -40 -35 -30 -25 -20 -15 -10 -5 0 Input Frequency (kHz) Input Signal Level (dB) FIGURE 2-21: Total Harmonic Distortion FIGURE 2-24: Signal to Noise and (THD) vs. Input Frequency. Distortion (SINAD) vs. Input Signal Level. DS21697B-page 10  2002 Microchip Technology Inc.

MCP3302/04 Note: Unless otherwise indicated, V = V = 5V, Full differential input configuration, V = 0V, DD REF SS F = 100ksps, F = 21*F , T = 25°C. SAMPLE CLK SAMPLE A 13 13 12.8 12 12.6 B (rms)1101 VFSDADM=P2L.E7 V= 50 ksps VFSDADM=P5LVE = 100 ksps B (rms) 1122..24 VDD=VREF=2.7V VFSDADM=PVLRE E=F =150V0 ksps NO NO 12 FSAMPLE = 50 ksps E 9 E 11.8 11.6 8 11.4 7 11.2 0 1 2 3 4 5 1 10 100 VREF(V) Input Frequency (kHz) FIGURE 2-25: Effective Number of Bits FIGURE 2-28: Effective Number of Bits (ENOB) vs. V . (ENOB) vs. Input Frequency. REF 100 -30 VDD=VREF=5V 0.1 µF Bypass 90 FSAMPLE = 100 ksps -35 Capacitor 80 -40 70 -45 dB) 60 B) -50 SFDR ( 4500 VFSDADM=PVLRE E=F =520. 7kVsps PSR(d --6505 30 -65 20 -70 10 -75 0 -80 1 10 100 1 10 100 1000 10000 Input Frequency (kHz) Ripple Frequency (kHz) FIGURE 2-26: Spurious Free Dynamic FIGURE 2-29: Power Supply Rejection Range (SFDR) vs. Input Frequency. (PSR) vs. Ripple Frequency. 0 0 -10 -10 -20 -20 -30 -30 -40 -40 B) -50 B) -50 de (d --7600 de (d --7600 mplitu --9800 mplitu --9800 A -100 A -100 -110 -110 -120 -120 -130 -130 -140 -140 -150 -150 0 10000 20000 30000 40000 50000 0 5000 10000 15000 20000 25000 Frequency (Hz) Frequency (Hz) FIGURE 2-27: Frequency Spectrum of FIGURE 2-30: Frequency Spectrum of 10kHz Input (Representative Part). 1kHz Input (Representative Part, V = 2.7V). DD  2002 Microchip Technology Inc. DS21697B-page 11

MCP3302/04 Note: Unless otherwise indicated, V = V = 5V, Full differential input configuration, V = 0V, DD REF SS F = 100ksps, F = 21*F , T = 25°C. SAMPLE CLK SAMPLE A 450 120 400 100 350 300 80 I (µA)DD 220500 I (µA)REF 60 150 40 100 20 50 0 0 2 2.5 3 3.5 4 4.5 5 5.5 6 2 2.5 3 3.5 4 4.5 5 5.5 6 VDD (V) VDD (V) FIGURE 2-31: I vs. V . FIGURE 2-34: I vs. V . DD DD REF DD 600 120 500 VDD=VREF=5V 100 VDD=VREF=5V 400 80 I (µA)DD 300 I (µA)REF 60 200 40 VDD=VREF=2.7V VDD=VREF=2.7V 100 20 0 0 0 50 100 150 200 0 50 100 150 200 Sample Rate (ksps) Sample Rate (ksps) FIGURE 2-32: I vs. Sample Rate. FIGURE 2-35: I vs. Sample Rate. DD REF 400 100 350 90 I (µA)DD 122350500000 VFSDADM=PVLRE E=F =150V0 ksps I(µA)REF 4567800000 VFVSDADDMD=P=VLVRE ER=FE =F1=502V0.7 kVsps 100 VDD=VREF=2.7V 30 FSAMPLE = 50 ksps FSAMPLE = 50 ksps 20 50 10 0 0 -50 0 50 100 150 -50 0 50 100 150 Temperature (°C) Temperature (°C) FIGURE 2-33: I vs. Temperature. FIGURE 2-36: I vs. Temperature. DD REF DS21697B-page 12  2002 Microchip Technology Inc.

MCP3302/04 Note: Unless otherwise indicated, V = V = 5V, Full differential input configuration, V = 0V, DD REF SS F = 100ksps, F = 21*F , T = 25°C. SAMPLE CLK SAMPLE A 80 2 70 1.5 B) 60 LS 1 I (pA)DDS 345000 e Gain Error ( -00..505 VFSDADM=PVLRE E=F =520. 7kVsps VFSDADM=PVLREE =F= 150V0 ksps v 20 gati -1 e N 10 -1.5 0 -2 2 2.5 3 3.5 4 4.5 5 5.5 6 -50 0 50 100 150 VDD (V) Temperature (°C) FIGURE 2-37: I vs. V . FIGURE 2-40: Negative Gain Error vs. DDS DD Temperature. 100 80 10 B) 79 n(d 78 o I (nA)DDS 0.11 Rejection Rati 777567 de 74 0.01 Mo 73 n mo 72 0.001 m -50 -25 0 25 50 75 100 Co 71 Temperature (°C) 70 1 10 100 1000 Input Frequency (kHz) FIGURE 2-38: I vs. Temperature. DDS FIGURE 2-41: Common Mode Rejection vs. Frequency. 4 3.5 B) 3 S L or ( 2.5 Err 2 ain 1.5 VDD=5V e G 1 FSAMPLE = 100 ksps v ati 0.5 g Ne 0 -0.5 -1 0 1 2 3 4 5 6 VREF (V) FIGURE 2-39: Negative Gain Error vs. Reference Voltage.  2002 Microchip Technology Inc. DS21697B-page 13

MCP3302/04 3.0 TEST CIRCUITS 1kΩ 1/2 MCP602 + 1.4V 5V ±500 mVP-P 0X 3kΩ Test Point 20kΩ - 1kΩ To VDD on DUT 3 D 3 OUT P 2.63V 5VP-P 1kΩ C M C = 100pF L FIGURE 3-3: Power Supply Sensitivity FIGURE 3-1: Load Circuit for T , T ,T . R F DO Test Circuit (PSRR). Test Point V = 5V V = 5V V REF DD DD X T Waveform 2 1µF 30 D 3kΩ VDD/2 DIS 0.1µF 3 OUT T Waveform 0.1µF P EN 5V C P-P M 100pF TDIS Waveform 1 IN(+) V V V REF DD SS MCP330X IN(-) V SS 5V P-P Voltage Waveforms for T DIS V = 2.5V V CM CS IH D OUT 90% Waveform 1* FIGURE 3-4: Full Differential Test Configuration Example. T DIS D 10% OUT Waveform 2† V = 2.5V V = 5V REF DD 1µF *Waveform 1 is for an output with internal con- 0.1µF ditions such that the output is high, unless dis- 0.1µF abled by the output control. IN(+) †Waveform 2 is for an output with internal con- 5V V V P-P REF DD ditions such that the output is low, unless dis- MCP330X IN(-) abled by the output control. VSS V = 2.5V CM FIGURE 3-2: Load circuit for T and DIS T . EN FIGURE 3-5: Pseudo Differential Test Configuration Example. DS21697B-page 14  2002 Microchip Technology Inc.

MCP3302/04 4.0 PIN DESCRIPTIONS 4.6 Serial Clock (CLK) The descriptions of the pins are listed in Table4-1. The SPI clock pin is used to initiate a conversion and to clock out each bit of the conversion as it takes place. TABLE 4-1: PIN FUNCTION TABLE See Section6.2 for constraints on clock speed. See Figure7-2 for serial communication protocol. Name Function CH0-CH7 Analog Inputs 4.7 AGND DGND Digital Ground Ground connection to internal analog circuitry. To CS/SHDN Chip Select / Shutdown Input ensure accuracy, this pin must be connected to the same ground as DGND. If an analog ground plane is D Serial Data In IN available, it is recommended that this device be tied to D Serial Data Out OUT the analog ground plane in the circuit. See Section6.6 CLK Serial Clock for more information regarding circuit layout. AGND Analog Ground 4.8 Voltage Reference (V ) V Reference Voltage Input REF REF V +2.7V to 5.5V Power Supply This input pin provides the reference voltage for the DD device, which determines the maximum range of the 4.1 CH0-CH7 analog input signal and the LSB size. The LSB size is determined according to the equation Analog input channels. These pins have an absolute shown below. As the reference input is reduced, the voltage range of V - 0.3V to V + 0.3V. The full scale SS DD LSB size is reduced accordingly. differential input range is defined as the absolute value of (IN+) - (IN-). This difference can not exceed the EQUATION value of V - 1LSB or digital code saturation will REF occur. 2 x V LSB Size = REF 4.2 DGND 8192 Ground connection to internal digital circuitry. To When using an external voltage reference device, the ensure accuracy this pin must be connected to the system designer should always refer to the manufac- same ground as AGND. If an analog ground plane is turer’s recommendations for circuit layout. Any instabil- available, it is recommended that this device be tied to ity in the operation of the reference device will have a the analog ground plane in the circuit. See Section6.6 direct effect on the accuracy of the ADC conversion for more information regarding circuit layout. results. 4.3 Chip Select/Shutdown (CS/SHDN) 4.9 V DD The CS/SHDN pin is used to initiate communication The voltage on this pin can range from 2.7 to 5.5V. To with the device when pulled low. This pin will end a con- ensure accuracy, a 0.1µF ceramic bypass capacitor version and put the device in low power standby when should be placed as close as possible to the pin. See pulled high. The CS/SHDN pin must be pulled high Section6.6 for more information regarding circuit lay- between conversions and cannot be tied low for multi- out. ple conversions. See Figure7-2 for serial communica- tion protocol. 4.4 Serial Data Input (D ) IN The SPI port serial data input pin is used to clock in input channel configuration data. Data is latched on the rising edge of the clock. See Figure7-2 for serial com- munication protocol. 4.5 Serial Data Output (D ) OUT The SPI serial data output pin is used to shift out the results of the A/D conversion. Data will always change on the falling edge of each clock as the conversion takes place. See Figure7-2 for serial communication protocol.  2002 Microchip Technology Inc. DS21697B-page 15

MCP3302/04 5.0 DEFINITION OF TERMS Signal to Noise Ratio - Signal to Noise Ratio (SNR) is defined as the ratio of the signal to noise measured at Bipolar Operation - This applies to either a differential the output of the converter. The signal is defined as the or single ended input configuration, where both positive rms amplitude of the fundamental frequency of the and negative codes are output from the A/D converter. input signal. The noise value is dependant on the Full bipolar range includes all 8192 codes. For bipolar device noise as well as the quantization error of the operation on a single ended input signal, the A/D con- converter and is directly affected by the number of bits verter must be configured to operate in pseudo differ- in the converter. The theoretical signal to noise ratio ential mode. limit based on quantization error only for an N-bit con- Unipolar Operation - This applies to either a single verter is defined as: ended or differential input signal where only one side of the device transfer is being used. This could be either EQUATION the positive or negative side, depending on which input SNR = (6.02N+1.76)dB (IN+ or IN-) is being used for the DC bias. Full unipolar operation is equivalent to a 12-bit converter. For a 13-bit converter, the theoretical SNR limit is Full Differential Operation - Applying a full differential 80.02dB. signal to both the IN(+) and IN(-) inputs is referred to as Total Harmonic Distortion - Total Harmonic Distortion full differential operation. This configuration is (THD) is the ratio of the rms sum of the harmonics to described in Figure3-4. the fundamental, measured at the output of the con- Pseudo-Differential Operation - Applying a single verter. For the MCP3302/04, it is defined using the first ended signal to only one of the input channels with a 9 harmonics, as is shown in the following equation: bipolar output is referred to as pseudo differential oper- ation. To obtain a bipolar output from a single ended EQUATION input signal the inverting input of the A/D converter 2 2 2 2 2 must be biased above V . This operation is described V +V +V +.....+V +V SS THD(-dB) = –20 log--------2-------------3-------------4--------------------------8-------------9- in Figure3-5. 2 V 1 Integral Nonlinearity - The maximum deviation from a straight line passing through the endpoints of the bipo- Here V is the rms amplitude of the fundamental and V lar transfer function is defined as the maximum integral 1 2 through V are the rms amplitudes of the second nonlinearity error. The endpoints of the transfer func- 9 through ninth harmonics. tion are a point 1/2LSB above the first code transition (0x1000) and 1/2LSB below the last code transition Signal to Noise plus Distortion (SINAD) - Numeri- (0x0FFF). cally defined, SINAD is the calculated combination of SNR and THD. This number represents the dynamic Differential Nonlinearity - The difference between two performance of the converter, including any harmonic measured adjacent code transitions and the 1LSB distortion. ideal is defined as differential nonlinearity. Positive Gain Error - This is the deviation between the EQUATION last positive code transition (0x0FFF) and the ideal volt- age level of V -1/2LSB, after the bipolar offset error REF (SNR⁄10) –(THD⁄10) has been adjusted out. SINAD(dB) = 20 log 10 +10 Negative Gain Error - This is the deviation between the last negative code transition (0X1000) and the ideal EffectIve Number of Bits - Effective Number of Bits voltage level of -V -1/2LSB, after the bipolar offset (ENOB) states the relative performance of the ADC in REF error has been adjusted out. terms of its resolution. This term is directly related to SINAD by the following equation: Offset Error - This is the deviation between the first positive code transition (0x0001) and the ideal 1/2LSB EQUATION voltage level. Acquisition Time - The acquisition time is defined as ENOB(N) = S----I--N-----A----D-----–-----1---.-7---6-- the time during which the internal sample capacitor is 6.02 charging. This occurs for 1.5clock cycles of the exter- nal CLK as defined in Figure7-2. For SINAD performance of 78dB, the effective number of bits is 12.66. Conversion Time - The conversion time occurs imme- diately after the acquisition time. During this time, suc- Spurious Free Dynamic Range - Spurious Free cessive approximation of the input signal occurs as the Dynamic Range (SFDR) is the ratio of the rms value of 13-bit result is being calculated by the internal circuitry. the fundamental to the next largest component in This occurs for 13clock cycles of the external CLK as ADC’s output spectrum. This is, typically, the first har- defined in Figure7-2. monic, but could also be a noise peak. DS21697B-page 16  2002 Microchip Technology Inc.

MCP3302/04 6.0 APPLICATIONS INFORMATION 6.2 Driving the Analog Input The analog input of the MCP3302/04 is easily driven, 6.1 Conversion Description either differentially or single ended. Any signal that is The MCP3302/04 A/D converters employ a conven- common to the two input channels will be rejected by tional SAR architecture. With this architecture, the the common mode rejection of the device. During the potential between the IN+ and IN- inputs are simulta- charging time of the sample capacitor, a small charging neously sampled and stored with the internal sample current will be required. For low source impedances, circuits for 1.5clock cycles. Following this sampling this input can be driven directly. For larger source time, the input hold switches of the converter open and impedances, a larger acquisition time will be required the device uses the collected charge to produce a due to the RC time constant that includes the source serial 13-bit binary two’s complement output code. This impedance. For the A/D Converter to meet specifica- conversion process is driven by the external clock and tion, the charge holding capacitor (CSAMPLE) must be must include 13 clock cycles, one for each bit. During given enough time to acquire a 13-bit accurate voltage this process, the most significant bit (MSB) is output level during the 1.5clock cycle acquisition period. first. This bit is the sign bit and indicates if the IN+ or IN- An analog input model is shown in Figure6-3. This input is at a higher potential. model is accurate for an analog input, regardless if it is configured as a single ended input, or the IN+ and IN- input in differential mode. In this diagram, it is shown CDAC that the source impedance (R ) adds to the internal Hold S IN+ sampling switch (RSS) impedance, directly affecting the time that is required to charge the capacitor (C ). SAMPLE CSAMP Consequently, a larger source impedance with no addi- tional acquisition time increases the offset, gain and + Comp 13-Bit SAR integral linearity errors of the conversion. To overcome - this, a slower clock speed can be used to allow for the longer charging time. Figure6-2 shows the maximum C SAMP IN- clock speed associated with source impedances. Shift Register Hold D OUT z) 2.5 H M FIGURE 6-1: Simplified Block Diagram. y ( 2.0 c n e u eq 1.5 Fr k oc 1.0 Cl m u 0.5 m xi a M 0.0 100 1000 10000 100000 Source Resistance (ohms) FIGURE 6-2: Maximum Clock Frequency vs. Source Resistance (R ) to maintain ±1LSB S INL.  2002 Microchip Technology Inc. DS21697B-page 17

MCP3302/04 V DD Sampling Switch V = 0.6V RSS CHx T SS RS = 1kΩ C SAMPLE VA CPIN V = 0.6V ILEAKAGE = DAC capacitance 7pF T ±1nA = 25pF V SS Legend VA = signal source RSS = source impedance CHx = input channel pad CPIN = input pin capacitance VT = threshold voltage ILEAKAGE = leakage current at the pin due to various junctions SS = sampling switch RS = sampling switch resistor CSAMPLE = sample/hold capacitance FIGURE 6-3: Analog Input Model. bring down the high pass corner. The value of R will need to be 1kΩ, or less, since higher input impedances 6.2.1 MAINTAINING MINIMUM CLOCK require additional acquisition time. Using the RC values SPEED in Figure6-4, we have a 100Hz corner frequency. See Figure2-12 for relation between input impedance and When the MCP3302/04 initiates, charge is stored on acquisition time. the sample capacitor. When the sample period is com- plete, the device converts one bit for each clock that is received. It is important for the user to note that a slow V = 5V DD clock rate will allow charge to bleed off the sample cap while the conversion is taking place. For the MCP330X 0.1µF devices, the recommended minimum clock speed dur- ing the conversion cycle (TCONV) is 105kHz. Failure to C meet this criteria may induce linearity errors into the 10µF IN+ conversion outside the rated specifications. It should VIN 1kΩ R MCP330X be noted that during the entire conversion cycle, the IN- VREF A/D converter does not have requirements for clock speed or duty cycle, as long as all timing specifications are met. VOUT VIN 6.3 Biasing Solutions 1µF MCP1525 0.1µF For pseudo-differential bipolar operation, the biasing circuit (shown in Figure 6-4) shows a single ended input AC coupled to the converter. This configuration FIGURE 6-4: Pseudo-differential biasing will give a digital output range of -4096 to +4095. With circuit for bipolar operation. the 2.5V reference, the LSB size equal to 610µV. Although the ADC is not production tested with a 2.5V Using an external operation amplifier on the input reference as shown, linearity will not change more than allows for gain and also buffers the input signal from the 0.1LSB. See Figure2-2 and Figure2-9 for DNL and input to the ADC allowing for a higher source imped- ance. This circuit is shown in Figure6-5. INL errors versus V at V = 5V. A trade-off exists REF DD between the high pass corner and the acquisition time. The value of C will need to be quite large in order to DS21697B-page 18  2002 Microchip Technology Inc.

MCP3302/04 6.4 Common Mode Input Range The common mode input range has no restriction and is VDD = 5V equal to the absolute input voltage range: V -0.3V to SS 10kΩ 0.1µF VDD + 0.3V. However, for a given VREF, the common mode voltage has a limited swing, if the entire range of 1kΩ MCP6021 the A/D converter is to be used. Figure6-7 and Figure6-8 show the relationship between V and the - IN+ REF common mode voltage swing. A smaller V allows for VIN 1µF + IN- MCPV330X wider flexibility in a common mode voltageR. EVFREF levels, REF 1MΩ down to 400mv, exhibit less than 0.1LSB change in DNL and INL. For characterization graphs that show this performance relationship, see Figure2-9 and Figure2-12. V V OUT IN MCP1525 1µF 0.1µF VDD = 5V 5 4.05V V) 4 e ( 2.8V FIGURE 6-5: Adding an amplifier allows g 3 n a for gain and also buffers the input from any high R impedance sources. de 2 2.3V o M 1 This circuit shows that some headroom will be lost due n 0.95V to the amplifier output not being able to swing all the mo 0 way to the rail. An example would be for an output m o swing of 0V to 5V. This limitation can be overcome by C -1 supplying a V that is slightly less than the common REF 0.25 1.0 2.5 4.0 5.0 mode voltage. Using a 2.048V reference for the A/D V (V) REF converter while biasing the input signal at 2.5V solves the problem. This circuit is shown in Figure6-5. FIGURE 6-7: Common Mode Input Range of Full Differential Input Signal versus V . REF V = 5V DD VDD = 5V 10kΩ 0.1µF 5 4.05V 1kΩ MCP606 e (V) 4 2.8V - IN+ g 3 n VIN + MCP330X Ra 1µF 1MΩ IN- VREF de 2 2.3V o M 1 10kΩ n 0.95V o m 0 m 2.048V o C -1 0.25 0.5 1.25 2.0 2.5 V V OUT IN V (V) 1µF MCP1525 0.1µF REF FIGURE 6-8: Common Mode Input Range versus V for Pseudo Differential Input. REF FIGURE 6-6: Circuit solution to overcome amplifier output swing limitation.  2002 Microchip Technology Inc. DS21697B-page 19

MCP3302/04 6.5 Buffering/Filtering the Analog 6.6 Layout Considerations Inputs When laying out a printed circuit board for use with Inaccurate conversion results may occur if the signal analog components, care should be taken to reduce source for the A/D converter is not a low impedance noise wherever possible. A bypass capacitor from VDD source. Buffering the input will overcome the imped- to ground should always be used with this device and ance issue. It is also recommended that an analog filter should be placed as close as possible to the device pin. be used to eliminate any signals that may be aliased A bypass capacitor value of 0.1µF is recommended. back into the conversion results. This is illustrated in Digital and analog traces on the board should be sepa- Figure6-9, where an op amp is used to drive the ana- rated as much as possible, with no traces running log input of the MCP3302/04. This amplifier provides a underneath the device or the bypass capacitor. Extra low impedance source for the converter input and a low precautions should be taken to keep traces with high pass filter, which eliminates unwanted high frequency frequency signals (such as clock lines) as far as possi- noise. Values shown are for a 10Hz Butterworth Low ble from analog traces. Pass filter. Use of an analog ground plane is recommended in Low pass (anti-aliasing) filters can be designed using order to keep the ground potential the same for all Microchip’s interactive FilterLab® software. FilterLab devices on the board. Providing V connections to DD will calculate capacitor and resistor values, as well as devices in a “star” configuration can also reduce noise determine the number of poles that are required for the by eliminating current return paths and associated application. For more information on filtering signals, errors (see Figure6-10). For more information on lay- see Application Note 699 “Anti-Aliasing Analog Filters out tips when using the MCP3302/04, or other ADC for Data Acquisition Systems”. devices, refer to Application Note 688, “Layout Tips for 12-Bit A/D Converter Applications”. V DD 10µF V 4.096V DD Reference Connection 0.1µF 1µF MCP1541 C L 0.1µF V REF IN+ MCP330X 7.86kΩ 2.2µF MCP601 IN- Device 4 VIN + 14.6kΩ - 1µF Device 1 FIGURE 6-9: The MCP601 Operational Amplifier is used to implement a 2nd order anti- Device 3 aliasing filter for the signal being converted by the MCP3302/04. Device 2 FIGURE 6-10: V traces arranged in a DD ‘Star’ configuration in order to reduce errors caused by current return paths. DS21697B-page 20  2002 Microchip Technology Inc.

MCP3302/04 6.7 Utilizing the Digital and Analog Ground Pins The MCP3302/04 devices provide both digital and ana- log ground connections to provide another means of noise reduction. As shown in Figure6-11, the analog and digital circuitry are separated internal to the device. This reduces noise from the digital portion of the device being coupled into the analog portion of the device. The two grounds are connected internally through the sub- strate which has a resistance of 5 -10Ω. If no ground plane is utilized, then both grounds must be connected to V on the board. If a ground plane is SS available, both digital and analog ground pins should be connected to the analog ground plane. If both an analog and a digital ground plane are available, both the digital and the analog ground pins should be con- nected to the analog ground plane, as shown in Figure6-11. Following these steps will reduce the amount of digital noise from the rest of the board being coupled into the A/D Converter. V DD MCP3302/04 Digital Side Analog Side -SPI Interface -Sample Cap -Shift Register -Capacitor Array -Control Logic -Comparator Substrate 5 - 10Ω DGND AGND 0.1µF Analog Ground Plane FIGURE 6-11: Separation of Analog and Digital Ground Pins.  2002 Microchip Technology Inc. DS21697B-page 21

MCP3302/04 7.0 SERIAL COMMUNICATIONS TABLE 7-1: BINARY TWO’S COMPLEMENT OUTPUT 7.1 Output Code Format CODE EXAMPLES. The output code format is a binary two’s complement Analog Input Levels Sign Binary Data Decimal Bit DATA scheme, with a leading sign bit that indicates the sign of the output. If the IN+ input is higher than the IN- Full Scale Positive input, the sign bit will be a zero. If the IN- input is higher, (IN+)-(IN-)=VREF-1LSB 0 1111 1111 1111 +4095 the sign bit will be a ‘1’. (IN+)-(IN-) = VREF-2LSB 0 1111 1111 1110 +4094 IN+ = (IN-) +2LSB 0 0000 0000 0010 +2 The diagram shown in Figure7-1 shows the output IN+ = (IN-) +1LSB 0 0000 0000 0001 +1 code transfer function. In this diagram, the horizontal IN+ = IN- 0 0000 0000 0000 0 axis is the analog input voltage and the vertical axis is IN+ = (IN-) - 1LSB 1 1111 1111 1111 -1 the output code of the ADC. It shows that when IN+ is equal to IN-, both the sign bit and the data word is zero. IN+ = (IN-) - 2LSB 1 1111 1111 1110 -2 As IN+ gets larger with respect to IN-, the sign bit is a (IN+)-(IN-) = VREF-2LSB 1 0000 0000 0001 -4095 zero and the data word gets larger. The full scale output Full Scale Negative (IN+)-(IN-) = V -1LSB 1 0000 0000 0000 -4096 code is reached at +4095 when the input [(IN+) - (IN-)] REF reaches V - 1LSB. When IN- is larger than IN+, the REF two’s complement output codes will be seen with the sign bit being a one. Some examples of analog input levels and corresponding output codes are shown in Table7-1. Output Positive Full Code Scale Output = V -1LSB REF 0 + 1111 1111 1111 (+4095) 0 + 1111 1111 1110 (+4094) 0 + 0000 0000 0011 (+3) 0 + 0000 0000 0010 (+2) 0 + 0000 0000 0001 (+1) IN+ > IN- Analog Input 0 + 0000 0000 0000 (0) Voltage -VREF IN+ < IN- 11 ++ 11111111 11111111 11111101 ((--21)) VREF IN+ - IN- 1 + 1111 1111 1101 (-3) 1 + 0000 0000 0001 (-4095) 1 + 0000 0000 0000 (-4096) Negative Full Scale Output = -V REF FIGURE 7-1: Output Code Transfer Function. DS21697B-page 22  2002 Microchip Technology Inc.

MCP3302/04 7.2 Communicating with the MCP3302 TABLE 7-2: CONFIGURATION BITS FOR and MCP3304 THE MCP3302 Control Bit Communication with the MCP3302/04 devices is done Selections using a standard SPI-compatible serial interface. Initi- Input Channel ating communication with either device is done by Single Configuration Selection bringing the CS line low (see Figure7-2). If the device /Diff D2* D1 D0 was powered up with the CS pin low, it must be brought high and back low to initiate communication. The first 1 X 0 0 single ended CH0 clock received with CS low and D high will constitute 1 X 0 1 single ended CH1 IN a start bit. The SGL/DIFF bit follows the start bit and will 1 X 1 0 single ended CH2 determine if the conversion will be done using single 1 X 1 1 single ended CH3 ended or differential input mode. Each channel in single ended mode will operate as a 12-bit converter 0 X 0 0 differential CH0 = IN+ with a unipolar output. No negative codes will be output CH1 = IN- in single ended mode. The next three bits (D0, D1 and 0 X 0 1 differential CH0 = IN- D2) are used to select the input channel configuration. CH1 = IN+ Table7-2 and Table7-3 show the configuration bits for 0 X 1 0 differential CH2 = IN+ the MCP3302 and MCP3304, respectively. The device CH3 = IN- will begin to sample the analog input on the fourth rising 0 X 1 1 differential CH2 = IN- edge of the clock after the start bit has been received. CH3 = IN+ The sample period will end on the falling edge of the fifth clock following the start bit. *D2 is don’t care for MCP3302 After the D0 bit is input, one more clock is required to complete the sample and hold period (D is a “don’t TABLE 7-3: CONFIGURATION BITS FOR IN care” for this clock). On the falling edge of the next THE MCP3304 clock, the device will output a low null bit. The next 13 Control Bit clocks will output the result of the conversion with the Selections Input Channel sign bit first, followed by the 12 remaining data bits, as Configuration Selection shown in Figure7-2. Note that if the device is operating SinglE D2 D1 D0 in the single ended mode, the sign bit will always be /Diff transmitted as a ‘0’. Data is always output from the 1 0 0 0 single ended CH0 device on the falling edge of the clock. If all 13 data bits 1 0 0 1 single ended CH1 have been transmitted, and the device continues to receive clocks while the CS is held low, the device will 1 0 1 0 single ended CH2 output the conversion result, LSB, first, as shown in 1 0 1 1 single ended CH3 Figure7-3. If more clocks are provided to the device 1 1 0 0 single ended CH4 while CS is still low (after the LSB first data has been transmitted), the device will clock out zeros indefinitely. 1 1 0 1 single ended CH5 1 1 1 0 single ended CH6 If necessary, it is possible to bring CS low and clock in leading zeros on the D line before the start bit. This is 1 1 1 1 single ended CH7 IN often done when dealing with microcontroller-based 0 0 0 0 differential CH0 = IN+ SPI ports that must send 8 bits at a time. Refer to CH1 = IN- Section7.3 for more details on using the MCP3302/04 0 0 0 1 differential CH0 = IN- devices with hardware SPI ports CH1 = IN+ 0 0 1 0 differential CH2 = IN+ CH3 = IN- 0 0 1 1 differential CH2 = IN- CH3 = IN+ 0 1 0 0 differential CH4 = IN+ CH5 = IN- 0 1 0 1 differential CH4 = IN- CH5 = IN+ 0 1 1 0 differential CH6 = IN+ CH7 = IN- 0 1 1 1 differential CH6 = IN- CH7 = IN+  2002 Microchip Technology Inc. DS21697B-page 23

MCP3302/04 TSAMPLE TSAMPLE T CSH CS T SUCS CLK DIN StartSDGIFLF/ D2 D1 D0 Don’t Care StartSDGIFLF/ D2 DOUT HI-Z NBuitllSB†B11B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 * HI-Z T CONV T ACQ T ** DATA * After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output LSB first data, followed by zeros indefinitely. See Figure7-3 below. ** T : during this time, the bias current and the comparator power down while the reference input becomes DATA a high impedance node, leaving the CLK running to clock out the LSB-first data or zeros. † When operating in single ended mode, the sign bit will always be transmitted as a ‘0’. FIGURE 7-2: Communication with MCP3302/04 (MSB first Format). T SAMPLE T CSH CS T SUCS Power Down CLK Start DIN D2D1D0 Don’t Care SGL/ DIFF HI-Z Null HI-Z DOUT Bit SB†B11B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10B11SB* (MSB) TACQ TCONV TDATA ** * After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output zeros indefinitely. ** T : During this time, the bias circuit and the comparator power down while the reference input becomes DATA a high impedance node, leaving the CLK running to clock out LSB first data or zeroes. † When operating in single ended mode, the sign bit will always be transmitted as a ‘0’. FIGURE 7-3: Communication with MCP3302/04 (LSB first Format). DS21697B-page 24  2002 Microchip Technology Inc.

MCP3302/04 7.3 Using the MCP3302/04 with Microcontroller (MCU) SPI Ports With most microcontroller SPI ports, it is required to send groups of eight bits. It is also required that the microcontroller SPI port be configured to clock out data on the falling edge of clock and latch data in on the ris- ing edge. Because communication with the MCP3302 and MCP3304 devices may not need multiples of eight clocks, it will be necessary to provide more clocks than are required. This is usually done by sending ‘leading zeros’ before the start bit. For example, Figure7-4 and Figure7-5 show how the MCP3302/04 devices can be interfaced to a MCU with a hardware SPI port. Figure7-4 depicts the operation shown in SPI Mode 0,0, which requires that the SCLK from the MCU idles in the ‘low’ state, while Figure7-5 shows the similar case of SPI Mode 1,1, where the clock idles in the ‘high’ state. As shown in Figure7-4, the first byte transmitted to the A/D Converter contains 6 leading zeros before the start bit. Arranging the leading zeros this way produces the 13 data bits to fall in positions easily manipulated by the MCU. The sign bit is clocked out of the A/D Converter on the falling edge of clock number 11, followed by the remaining data bits (MSB first). After the second eight clocks have been sent to the device, the MCU receive buffer will contain 2 unknown bits (the output is at high impedance for the first two clocks), the null bit, the sign bit and the 4 highest order bits of the conversion. After the third byte has been sent to the device, the receive register will contain the lowest order eight bits of the conversion results. Easier manipulation of the con- verted data can be obtained by using this method. Figure7-5 shows the same situation in SPI Mode 1,1, which requires that the clock idles in the high state. As with mode 0,0, the A/D Converter outputs data on the falling edge of the clock and the MCU latches data from the A/D Converter in on the rising edge of the clock.  2002 Microchip Technology Inc. DS21697B-page 25

MCP3302/04 CS MCU latches data from A/D Converter on rising edges of SCLK SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Data is clocked out of A/D Converter on falling edges DIN StartSDGIFLF/ D2 D1 D0 Don’t Care HI-Z NULL DOUT BIT SB B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Start Bit MCU Transmitted Data (Aligned with falling 0 0 0 0 1 SDGIFLF/ D2 D1 DO X X X X X X X X X X X X X X X edge of clock) MCU Received Data (Aligned with rising ? ? ? ? ? ? ? ? ? ? (N0ull) SB B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 edge of clock) Data stored into MCU receive register Data stored into MCU receive register Data stored into MCU receive register ?? == UUnnkknnoowwnn BBiittss after transmission of first 8 bits after transmission of second 8 bits after transmission of last 8 bits X = Don’t Care Bits FIGURE 7-4: SPI Communication with the MCP3302/04 using 8-bit segments (Mode 0,0: SCLK idles low). MCU latches data from A/D Converter CS on rising edges of SCLK SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Data is clocked out of A/D Converter on falling edges DIN StartSDGIFLF/ D2 D1 D0 DDoonn’t’ tC Caarere HI-Z NULL DOUT BIT SB B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Start MCU Transmitted Data Bit (Aligned with falling 0 0 0 0 1 SDGIFLF/ D2 D1 DO X X X X X X X X X X X X X X X edge of clock) MCU Received Data (Aligned with rising ? ? ? ? ? ? ? ? ? ? 0 SB B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 (Null) edge of clock) Data stored into MCU receive register Data stored into MCU receive register Data stored into MCU receive register ? = Unknown Bits after transmission of first 8 bits after transmission of second 8 bits after transmission of last 8 bits X = Don’t Care Bits FIGURE 7-5: SPI Communication with the MCP3302/04 using 8-bit segments (Mode 1,1: SCLK idles high). DS21697B-page 26  2002 Microchip Technology Inc.

MCP3302/04 8.0 PACKAGING INFORMATION 8.1 Package Marking Information 14-Lead PDIP (300 mil) Example: XXXXXXXXXXXXXX MCP3302-B XXXXXXXXXXXXXX I/P YYWWNNN 0125NNN 14-Lead SOIC (150 mil) Example: XXXXXXXXXXX MCP3302-B XXXXXXXXXXX XXXXXXXXXXX YYWWNNN 0YWWNNN 14-Lead TSSOP (4.4mm) † Example: XXXXXXXX 3302-C YYWW IYWW NNN NNN †Please contact Microchip Factory for B-Grade TSSOP devices Legend: XX...X Customer specific information* YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard marking consists of Microchip part number, year code, week code, traceability code (facility code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please check with your Microchip Sales Office.  2002 Microchip Technology Inc. DS21697B-page 27

MCP3302/04 Package Marking Information (Continued) 16-Lead PDIP (300 mil) (MCP3304) Example: XXXXXXXXXXXXXX MCP3304-B XXXXXXXXXXXXXX I/P YYWWNNN YYWWNNN 16-Lead SOIC (150 mil) (MCP3304) Example: XXXXXXXXXXXXX MCP3304-B XXXXXXXXXXXXX XXXXXXXXXX YYWWNNN IYWWNNN Legend: XX...X Customer specific information* YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard marking consists of Microchip part number, year code, week code, traceability code (facility code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. DS21697B-page 28  2002 Microchip Technology Inc.

MCP3302/04 14-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n 1 α E A A2 c L A1 β B1 eB B p Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 14 14 Pitch p .100 2.54 Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32 Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26 Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60 Overall Length D .740 .750 .760 18.80 19.05 19.30 Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43 Lead Thickness c .008 .012 .015 0.20 0.29 0.38 Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78 Lower Lead Width B .014 .018 .022 0.36 0.46 0.56 Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92 Mold Draft Angle Top α 5 10 15 5 10 15 Mold Draft Angle Bottom β 5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-005  2002 Microchip Technology Inc. DS21697B-page 29

MCP3302/04 14-Lead Plastic Small Outline (SL) – Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 α h 45° c A A2 φ A1 L β Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 14 14 Pitch p .050 1.27 Overall Height A .053 .061 .069 1.35 1.55 1.75 Molded Package Thickness A2 .052 .056 .061 1.32 1.42 1.55 Standoff § A1 .004 .007 .010 0.10 0.18 0.25 Overall Width E .228 .236 .244 5.79 5.99 6.20 Molded Package Width E1 .150 .154 .157 3.81 3.90 3.99 Overall Length D .337 .342 .347 8.56 8.69 8.81 Chamfer Distance h .010 .015 .020 0.25 0.38 0.51 Foot Length L .016 .033 .050 0.41 0.84 1.27 Foot Angle φ 0 4 8 0 4 8 Lead Thickness c .008 .009 .010 0.20 0.23 0.25 Lead Width B .014 .017 .020 0.36 0.42 0.51 Mold Draft Angle Top α 0 12 15 0 12 15 Mold Draft Angle Bottom β 0 12 15 0 12 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-065 DS21697B-page 30  2002 Microchip Technology Inc.

MCP3302/04 14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP) E E1 p D 2 n 1 B α A c φ β A1 A2 L Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 14 14 Pitch p .026 0.65 Overall Height A .043 1.10 Molded Package Thickness A2 .033 .035 .037 0.85 0.90 0.95 Standoff § A1 .002 .004 .006 0.05 0.10 0.15 Overall Width E .246 .251 .256 6.25 6.38 6.50 Molded Package Width E1 .169 .173 .177 4.30 4.40 4.50 Molded Package Length D .193 .197 .201 4.90 5.00 5.10 Foot Length L .020 .024 .028 0.50 0.60 0.70 Foot Angle φ 0 4 8 0 4 8 Lead Thickness c .004 .006 .008 0.09 0.15 0.20 Lead Width B1 .007 .010 .012 0.19 0.25 0.30 Mold Draft Angle Top α 0 5 10 0 5 10 Mold Draft Angle Bottom β 0 5 10 0 5 10 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005” (0.127mm) per side. JEDEC Equivalent: MO-153 Drawing No. C04-087  2002 Microchip Technology Inc. DS21697B-page 31

MCP3302/04 16-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 α n 1 E A A2 c L β A1 B1 eB B p Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 16 16 Pitch p .100 2.54 Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32 Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26 Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60 Overall Length D .740 .750 .760 18.80 19.05 19.30 Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43 Lead Thickness c .008 .012 .015 0.20 0.29 0.38 Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78 Lower Lead Width B .014 .018 .022 .036 0.46 0.56 Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92 Mold Draft Angle Top α 5 10 15 5 10 15 Mold Draft Angle Bottom β 5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-017 DS21697B-page 32  2002 Microchip Technology Inc.

MCP3302/04 16-Lead Plastic Small Outline (SL) – Narrow 150 mil (SOIC) E E1 p D 2 B n 1 α h 45° c A A2 φ L A1 β Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 16 16 Pitch p .050 1.27 Overall Height A .053 .061 .069 1.35 1.55 1.75 Molded Package Thickness A2 .052 .057 .061 1.32 1.44 1.55 Standoff § A1 .004 .007 .010 0.10 0.18 0.25 Overall Width E .228 .237 .244 5.79 6.02 6.20 Molded Package Width E1 .150 .154 .157 3.81 3.90 3.99 Overall Length D .386 .390 .394 9.80 9.91 10.01 Chamfer Distance h .010 .015 .020 0.25 0.38 0.51 Foot Length L .016 .033 .050 0.41 0.84 1.27 Foot Angle φ 0 4 8 0 4 8 Lead Thickness c .008 .009 .010 0.20 0.23 0.25 Lead Width B .013 .017 .020 0.33 0.42 0.51 Mold Draft Angle Top α 0 12 15 0 12 15 Mold Draft Angle Bottom β 0 12 15 0 12 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-108  2002 Microchip Technology Inc. DS21697B-page 33

MCP3302/04 NOTES: DS21697B-page 34  2002 Microchip Technology Inc.

MCP3302/04 ON-LINE SUPPORT Systems Information and Upgrade Hot Line The Systems Information and Upgrade Line provides Microchip provides on-line support on the Microchip system users a listing of the latest versions of all of World Wide Web (WWW) site. Microchip's development systems software products. The web site is used by Microchip as a means to make Plus, this line provides information on how customers files and information easily available to customers. To can receive any currently available upgrade kits.The view the site, the user must have access to the Internet Hot Line Numbers are: and a web browser, such as Netscape or Microsoft 1-800-755-2345 for U.S. and most of Canada, and Explorer. Files are also available for FTP download from our FTP site. 1-480-792-7302 for the rest of the world. Connecting to the Microchip Internet Web Site 013001 The Microchip web site is available by using your favorite Internet browser to attach to: www.microchip.com The file transfer site is available by using an FTP ser- vice to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A vari- ety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: • Latest Microchip Press Releases • Technical Support Section with Frequently Asked Questions • Design Tips • Device Errata • Job Postings • Microchip Consultant Program Member Listing • Links to other useful web sites related to Microchip Products • Conferences for products, Development Systems, technical information and more • Listing of seminars and events  2002 Microchip Technology Inc. DS21697B-page 35

MCP3302/04 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this Data Sheet. To: Technical Publications Manager Total Pages Sent RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: MCP3302/04 Literature Number: DS21697B Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this data sheet easy to follow? If not, why? 4. What additions to the data sheet do you think would enhance the structure and subject? 5. What deletions from the data sheet could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? 8. How would you improve our software, systems, and silicon products? DS21697B-page 36  2002 Microchip Technology Inc.

MCP3302/04 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X X /XX Examples: Device Grade Temperature Package a) MCP3302-BI/P: ±1LSB INL, Industrial Tem- Range perature, PDIP package b) MCP3302-BI/SL: ±1LSB INL, Industrial Temperature, SOIC package Device: MCP3302: 13-Bit Serial A/D Converter c) MCP3302-CI/ST: ±2LSB INL, Industrial MCP3302T: 13-Bit Serial A/D Converter (Tape and Reel) Temperature, TSSOP package MCP3304: 13-Bit Serial A/D Converter MCP3304T: 13-Bit Serial A/D Converter (Tape and Reel) a) MCP3304-BI/P: ±1LSB INL, Industrial Temperature, PDIP package Grade: B = ±1LSB INL C = ±2LSB INL b) MCP3304-BI/SL: ±1LSB INL, Industrial Temperature, SOIC package Temperature Range: I = -40°C to +85°C Package: P = Plastic DIP (300 mil Body), 14-lead, 16-lead SL = Plastic SOIC (150 mil Body), 14-lead, 16-lead ST = Plastic TSSOP (4.4mm), 14-lead Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office 2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 3. The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.  2002 Microchip Technology Inc. DS21697B-page37

MCP3302/04 NOTES: DS21697B-page 38  2002 Microchip Technology Inc.

MCP3302/04 Information contained in this publication regarding device Trademarks applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to The Microchip name and logo, the Microchip logo, FilterLab, ensure that your application meets with your specifications. KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER, No representation or warranty is given and no liability is PICSTART, PRO MATE, SEEVAL and The Embedded Control assumed by Microchip Technology Incorporated with respect Solutions Company are registered trademarks of Microchip Tech- to the accuracy or use of such information, or infringement of nology Incorporated in the U.S.A. and other countries. patents or other intellectual property rights arising from such dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, use or otherwise. Use of Microchip’s products as critical com- In-Circuit Serial Programming, ICSP, ICEPIC, microPort, ponents in life support systems is not authorized except with Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, express written approval by Microchip. No licenses are con- MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode veyed, implicitly or otherwise, under any intellectual property and Total Endurance are trademarks of Microchip Technology rights. Incorporated in the U.S.A. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified.  2002 Microchip Technology Inc. DS21697B-page 39

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: MCP3302-CI/P MCP3304-CI/P MCP3302-BI/SL MCP3302-BI/ST MCP3304-BI/SL MCP3302-BI/P MCP3304T- BI/SL MCP3302T-BI/SL MCP3302T-BI/ST MCP3302-CI/SL MCP3302-CI/ST MCP3304-CI/SL MCP3304-BI/P MCP3304T-CI/SL MCP3302T-CI/SL MCP3302T-CI/ST