MCP3204/3208 2.7V 4-Channel/8-Channel 12-Bit A/D Converters with SPI Serial Interface Features Description • 12-bit resolution The Microchip Technology Inc. MCP3204/3208 • ± 1LSB max DNL devices are successive approximation 12-bit Analog- to-Digital (A/D) Converters with on-board sample and • ± 1LSB max INL (MCP3204/3208-B) hold circuitry. The MCP3204 is programmable to • ± 2LSB max INL (MCP3204/3208-C) provide two pseudo-differential input pairs or four • 4 (MCP3204) or 8 (MCP3208) input channels single-ended inputs. The MCP3208 is programmable • Analog inputs programmable as single-ended or to provide four pseudo-differential input pairs or eight pseudo-differential pairs single-ended inputs. Differential Nonlinearity (DNL) is • On-chip sample and hold specified at ±1LSB, while Integral Nonlinearity (INL) is offered in ±1LSB (MCP3204/3208-B) and ±2LSB • SPI serial interface (modes 0,0 and 1,1) (MCP3204/3208-C) versions. • Single supply operation: 2.7V - 5.5V • 100ksps max. sampling rate at V = 5V Communication with the devices is accomplished using DD a simple serial interface compatible with the SPI • 50ksps max. sampling rate at V = 2.7V DD protocol. The devices are capable of conversion rates • Low power CMOS technology: of up to 100ksps. The MCP3204/3208 devices operate - 500nA typical standby current, 2µA max. over a broad voltage range (2.7V - 5.5V). Low current - 400µA max. active current at 5V design permits operation with typical standby and • Industrial temp range: -40°C to +85°C active currents of only 500nA and 320µA, respectively. The MCP3204 is offered in 14-pin PDIP, • Available in PDIP, SOIC and TSSOP packages 150mil SOIC and TSSOP packages. The MCP3208 is offered in 16-pin PDIP and SOIC packages. Applications • Sensor Interface Package Types • Process Control PDIP, SOIC, TSSOP • Data Acquisition CH0 1 14 VDD • Battery Operated Systems CH1 2 M 13 VREF CH2 3 C 12 AGND Functional Block Diagram CH3 4 P 11 CLK 3 NC 5 20 10 DOUT VDD VSS NC 6 4 9 DIN V DGND 7 8 CS/SHDN REF CH0 PDIP, SOIC CH1 Input Channel DAC CH0 1 16 VDD Mux CH1 2 15 VREF CH7* CH2 3 M 14 AGND Comparator C CH3 4 P 13 CLK Sample 12-Bit SAR CH4 5 32 12 DOUT and CH5 6 08 11 DIN Hold CH6 7 10 CS/SHDN CH7 8 9 DGND Shift Control Logic Register CS/SHDND CLK D IN OUT * Note: Channels 5-7 available on MCP3208 Only © 2008 Microchip Technology Inc. DS21298E-page 1

MCP3204/3208 1.0 ELECTRICAL †Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is CHARACTERISTICS a stress rating only and functional operation of the device at those or any other conditions above those indicated in the Absolute Maximum Ratings† operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect VDD...................................................................................7.0V device reliability. All inputs and outputs w.r.t. V ...............-0.6V to V +0.6V SS DD Storage temperature.....................................-65°C to +150°C Ambient temp. with power applied................-65°C to +125°C Soldering temperature of leads (10 seconds).............+300°C ESD protection on all pins.............................................> 4kV ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise noted, all parameters apply at V = 5V, V = 0V, V = 5V, DD SS REF T = -40°C to +85°C,f = 100ksps and f = 20*f A SAMPLE CLK SAMPLE Parameters Sym Min Typ Max Units Conditions Conversion Rate Conversion Time t — — 12 clock CONV cycles Analog Input Sample Time t 1.5 clock SAMPLE cycles Throughput Rate f — — 100 ksps V = V = 5V SAMPLE DD REF — — 50 ksps V = V = 2.7V DD REF DC Accuracy Resolution 12 bits Integral Nonlinearity INL — ±0.75 ±1 LSB MCP3204/3208-B — ±1.0 ±2 MCP3204/3208-C Differential Nonlinearity DNL — ±0.5 ±1 LSB No missing codes over-temperature Offset Error — ±1.25 ±3 LSB Gain Error — ±1.25 ±5 LSB Dynamic Performance Total Harmonic Distortion — -82 — dB V = 0.1V to 4.9V@1kHz IN Signal to Noise and Distortion — 72 — dB V = 0.1V to 4.9V@1kHz IN (SINAD) Spurious Free Dynamic — 86 — dB V = 0.1V to 4.9V@1kHz IN Range Reference Input Voltage Range 0.25 — V V Note2 DD Current Drain — 100 150 µA — 0.001 3.0 µA CS = V = 5V DD Analog Inputs Input Voltage Range for CH0- V — V V SS REF CH7 in Single-Ended Mode Input Voltage Range for IN+ in IN- — V +IN- REF pseudo-differential Mode Note 1: This parameter is established by characterization and not 100% tested. 2: See graphs that relate linearity performance to V levels. REF 3: Because the sample cap will eventually lose charge, effective clock rates below 10kHz can affect linearity performance, particularly at elevated temperatures. See Section6.2 “Maintaining Minimum Clock Speed”, “Maintaining Minimum Clock Speed”, for more information. DS21298E-page 2 © 2008 Microchip Technology Inc.

MCP3204/3208 ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise noted, all parameters apply at V = 5V, V = 0V, V = 5V, DD SS REF T = -40°C to +85°C,f = 100ksps and f = 20*f A SAMPLE CLK SAMPLE Parameters Sym Min Typ Max Units Conditions Input Voltage Range for IN- in V -100 — V +100 mV SS SS pseudo-differential Mode Leakage Current — 0.001 ±1 µA Switch Resistance — 1000 — Ω See Figure4-1 Sample Capacitor — 20 — pF See Figure4-1 Digital Input/Output Data Coding Format Straight Binary High Level Input Voltage V 0.7 V — — V IH DD Low Level Input Voltage V — — 0.3 V V IL DD High Level Output Voltage V 4.1 — — V I = -1mA, V = 4.5V OH OH DD Low Level Output Voltage V — — 0.4 V I = 1mA, V = 4.5V OL OL DD Input Leakage Current I -10 — 10 µA V = V or V LI IN SS DD Output Leakage Current I -10 — 10 µA V = V or V LO OUT SS DD Pin Capacitance C ,C — — 10 pF V = 5.0V (Note1) IN OUT DD (All Inputs/Outputs) T = 25°C, f = 1MHz A Timing Parameters Clock Frequency f — — 2.0 MHz V = 5V (Note3) CLK DD — — 1.0 MHz V = 2.7V (Note3) DD Clock High Time t 250 — — ns HI Clock Low Time t 250 — — ns LO CS Fall To First Rising CLK t 100 — — ns SUCS Edge Data Input Setup Time t 50 — — ns SU Data Input Hold Time t 50 — — ns HD CLK Fall To Output Data Valid t — — 200 ns See Figures1-2 and 1-3 DO CLK Fall To Output Enable t — — 200 ns See Figures1-2 and 1-3 EN CS Rise To Output Disable t — — 100 ns See Figures1-2 and 1-3 DIS CS Disable Time t 500 — — ns CSH D Rise Time t — — 100 ns See Figures1-2 and 1-3 (Note1) OUT R D Fall Time t — — 100 ns See Figures1-2 and 1-3 (Note1) OUT F Power Requirements Operating Voltage V 2.7 — 5.5 V DD Operating Current I — 320 400 µA V =V = 5V, D unloaded DD DD REF OUT — 225 — V =V = 2.7V, D unloaded DD REF OUT Standby Current I — 0.5 2.0 µA CS = V = 5.0V DDS DD Note 1: This parameter is established by characterization and not 100% tested. 2: See graphs that relate linearity performance to V levels. REF 3: Because the sample cap will eventually lose charge, effective clock rates below 10kHz can affect linearity performance, particularly at elevated temperatures. See Section6.2 “Maintaining Minimum Clock Speed”, “Maintaining Minimum Clock Speed”, for more information. © 2008 Microchip Technology Inc. DS21298E-page 3

MCP3204/3208 TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, V = 5V, V = 0V, V = 5V DD SS REF Parameters Sym Min Typ Max Units Conditions Temperature Ranges Specified Temperature Range T -40 — +125 °C A Operating Temperature Range T -40 — +125 °C A Storage Temperature Range T -65 — +150 °C A Thermal Package Resistances Thermal Resistance, 14L-PDIP θ — 70 — °C/W JA Thermal Resistance, 14L-SOIC θ — 95.3 — °C/W JA Thermal Resistance, 14L-TSSOP θ — 100 — °C/W JA Thermal Resistance, 16L-PDIP θ — 70 — °C/W JA Thermal Resistance, 16L-SOIC θ — 86.1 — °C/W JA t CSH CS t SUCS t t HI LO CLK t t SU HD DIN MSB IN tDO tR tF tDIS t EN DOUT Null Bit MSB OUT LSB FIGURE 1-1: Serial Interface Timing. DS21298E-page 4 © 2008 Microchip Technology Inc.

MCP3204/3208 1.4V Test Point V DD t Waveform 2 3kΩ DIS Test Point 3kΩ VDD/2 DOUT DOUT tEN Waveform CL = 100pF 100pF tDIS Waveform 1 V SS Voltage Waveforms for t , t R F Voltage Waveforms for t EN V OH V D OL OUT CS tR tF CLK 1 2 3 4 Voltage Waveforms for t DO D B11 OUT CLK t EN t DO Voltage Waveforms for t DIS D OUT V CS IH FIGURE 1-2: Load Circuit for t , t , t . D R F DO OUT 90% Waveform 1* T DIS D 10% OUT Waveform 2† * Waveform 1 is for an output with internal conditions such that the output is high, unless disabled by the output control. † Waveform 2 is for an output with internal conditions such that the output is low, unless disabled by the output control. FIGURE 1-3: Load circuit for t and t . DIS EN © 2008 Microchip Technology Inc. DS21298E-page 5

MCP3204/3208 NOTES: DS21298E-page 6 © 2008 Microchip Technology Inc.

MCP3204/3208 2.0 TYPICAL PERFORMANCE CHARACTERISTICS Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, V = V = 5V, V = 0V, f = 100ksps, f = 20* f , T = +25°C. DD REF SS SAMPLE CLK SAMPLE A 1.0 2.0 0.8 Positive INL 1.5 VDD = VREF = 2.7 V 0.6 1.0 0.4 Positive INL INL (LSB)--0000....4202 Negative INL INL (LSB)--0010....0505 Negative INL -0.6 -1.5 -0.8 -2.0 -1.0 0 10 20 30 40 50 60 70 80 0 25 50 75 100 125 150 Sample Rate (ksps) Sample Rate (ksps) FIGURE 2-1: Integral Nonlinearity (INL) FIGURE 2-4: Integral Nonlinearity (INL) vs. Sample Rate. vs. Sample Rate (V = 2.7V). DD 2.5 2.0 2.0 1.5 1.5 Positive INL 1.0 LSB) 01..50 Positive INL SB)0.5 NL ( 0.0 L (L0.0 I-0.5 N-0.5 I -1.0 Negative INL -1.0 Negative INL -1.5 -1.5 -2.0 -2.0 0 1 2 3 4 5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 VREF (V) VREF (V) FIGURE 2-2: Integral Nonlinearity (INL) FIGURE 2-5: Integral Nonlinearity (INL) vs. V . vs. V (V = 2.7V). REF REF DD 1.0 1.0 0.8 0.8 VDD = VREF = 2.7 V 0.6 0.6 FSAMPLE = 50 ksps 0.4 0.4 NL (LSB)-000...202 NL (LSB)-000...202 I I -0.4 -0.4 -0.6 -0.6 -0.8 -0.8 -1.0 -1.0 0 512 1024 1536 2048 2560 3072 3584 4096 0 512 1024 1536 2048 2560 3072 3584 4096 Digital Code Digital Code FIGURE 2-3: Integral Nonlinearity (INL) FIGURE 2-6: Integral Nonlinearity (INL) vs. Code (Representative Part). vs. Code (Representative Part, V = 2.7V). DD © 2008 Microchip Technology Inc. DS21298E-page 7

MCP3204/3208 Note: Unless otherwise indicated, V = V = 5V, V = 0V, f = 100ksps, f = 20* f , T = +25°C. DD REF SS SAMPLE CLK SAMPLE A 1.0 1.0 0.8 Positive INL 0.8 VFSDADM =P LVE R=E F5 =0 2k.s7p Vs 0.6 0.6 Positive INL 0.4 0.4 B) 0.2 B) 0.2 S S L 0.0 L 0.0 NL (-0.2 Negative INL NL (-0.2 I-0.4 I-0.4 -0.6 -0.6 Negative INL -0.8 -0.8 -1.0 -1.0 -50 -25 0 25 50 75 100 -50 -25 0 25 50 75 100 Temperature (°C) Temperature (°C) FIGURE 2-7: Integral Nonlinearity (INL) FIGURE 2-10: Integral Nonlinearity (INL) vs. Temperature. vs. Temperature (V = 2.7V). DD 1.0 2.0 0.8 1.5 VDD = VREF = 2.7 V 0.6 1.0 0.4 SB)0.2 SB)0.5 L (L0.0 Positive DNL L (L0.0 Positive DNL DN-0.2 DN-0.5 Negative DNL -0.4 -0.6 Negative DNL -1.0 -0.8 -1.5 -1.0 -2.0 0 25 50 75 100 125 150 0 10 20 30 40 50 60 70 80 Sample Rate (ksps) Sample Rate (ksps) FIGURE 2-8: Differential Nonlinearity FIGURE 2-11: Differential Nonlinearity (DNL) vs. Sample Rate. (DNL) vs. Sample Rate (V = 2.7V). DD 3.0 3.0 VDD = VREF = 2.7 V 2.0 2.0 FSAMPLE = 50 ksps Positive DNL B)1.0 Positive DNL B) 1.0 S S L (L0.0 L (L 0.0 DN-1.0 Negative DNL DN-1.0 Negative DNL -2.0 -2.0 -3.0 -3.0 0 1 2 3 4 5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 V (V) V (V) REF REF FIGURE 2-9: Differential Nonlinearity FIGURE 2-12: Differential Nonlinearity (DNL) vs. V . (DNL) vs. V (V = 2.7V) REF REF DD . DS21298E-page 8 © 2008 Microchip Technology Inc.

MCP3204/3208 Note: Unless otherwise indicated, V = V = 5V, V = 0V, f = 100ksps, f = 20* f , T = +25°C. DD REF SS SAMPLE CLK SAMPLE A 1.0 1.0 0.8 0.8 VDD = VREF = 2.7 V FSAMPLE = 50 ksps 0.6 0.6 0.4 0.4 SB) 0.2 SB) 0.2 L L L ( 0.0 L ( 0.0 N-0.2 N-0.2 D D -0.4 -0.4 -0.6 -0.6 -0.8 -0.8 -1.0 -1.0 0 512 1024 1536 2048 2560 3072 3584 4096 0 512 1024 1536 2048 2560 3072 3584 4096 Digital Code Digital Code FIGURE 2-13: Differential Nonlinearity FIGURE 2-16: Differential Nonlinearity (DNL) vs. Code (Representative Part). (DNL) vs. Code (Representative Part, V =2.7V). DD 1.0 1.0 0.8 0.8 VDD = VREF = 2.7 V 0.6 0.6 FSAMPLE = 50 ksps 0.4 Positive DNL 0.4 Positive DNL B)0.2 B) 0.2 S S NL (L-00..02 NL (L-00..20 D D -0.4 -0.4 Negative DNL Negative DNL -0.6 -0.6 -0.8 -0.8 -1.0 -1.0 -50 -25 0 25 50 75 100 -50 -25 0 25 50 75 100 Temperature (°C) Temperature (°C) FIGURE 2-14: Differential Nonlinearity FIGURE 2-17: Differential Nonlinearity (DNL) vs. Temperature. (DNL) vs. Temperature (V = 2.7V). DD 4 20 3 VDD = VREF = 2.7 V 18 n Error (LSB)-1012 FSAMPLE = 50 ksps et Error (LSB)111102468 VFSDADM =P LVE R=E F1 =0 0V5 VDkDs p=s VREF = 2.7V Gai--32 VFSDADM =P LVE R=E F1 =0 05 kVsps Offs 46 FSAMPLE = 50 ksps 2 -4 0 0 1 2 3 4 5 0 1 2 3 4 5 VREF (V) VREF (V) FIGURE 2-15: Gain Error vs. V . FIGURE 2-18: Offset Error vs. V . REF REF © 2008 Microchip Technology Inc. DS21298E-page 9

MCP3204/3208 Note: Unless otherwise indicated, V = V = 5V, V = 0V, f = 100ksps, f = 20* f , T = +25°C. DD REF SS SAMPLE CLK SAMPLE A 0.2 2.0 0.0 VDD = VREF = 2.7 V 1.8 SB)--00..42 FSAMPLE = 50 ksps LSB)11..46 VFSDADM =P LVE R=E F1 =0 05 kVsps Gain Error (L-----11100.....42086 VFSDADM =P LVE R=E F1 =0 05 kVsps Offset Error (00011.....46802 VFSDADM =P LVE R=E F5 =0 2k.s7p Vs -1.6 0.2 -1.8 0.0 -50 -25 0 25 50 75 100 -50 -25 0 25 50 75 100 Temperature (°C) Temperature (°C) FIGURE 2-19: Gain Error vs. Temperature. FIGURE 2-22: Offset Error vs. Temperature. 100 100 90 VDD = VREF = 5 V 90 VDD = VREF = 5 V 80 FSAMPLE = 100 ksps 80 FSAMPLE = 100 ksps 70 70 dB)60 dB)60 R (50 R (50 VDD = VREF = 2.7 V SN3400 VFSDADM =P LVE R=E F5 =0 2k.s7pVs SFD3400 FSAMPLE = 50 ksps 20 20 10 10 0 0 1 10 100 1 10 100 Input Frequency (kHz) Input Frequency (kHz) FIGURE 2-20: Signal-to-Noise (SNR) vs. FIGURE 2-23: Signal-to-Noise and Input Frequency. Distortion (SINAD) vs. Input Frequency. 0 80 --2100 70 VFSDADM =P LVE R=E F1 =0 05 kVsps -30 60 D (dB)--5400 VFSDADM =P LVE R=E F5 =0 2k.s7pVs D (dB)4500 VFSDADM =P LVE R=E F5 =0 2k.s7p Vs TH-60 NA30 -70 SI 20 -80 -90 VFSDADM =P LVE R=E F1 =0 05 Vksps 10 -100 0 1 10 100 -40 -35 -30 -25 -20 -15 -10 -5 0 Input Frequency (kHz) Input Signal Level (dB) FIGURE 2-21: Total Harmonic Distortion FIGURE 2-24: Signal-to-Noise and (THD) vs. Input Frequency. Distortion (SINAD) vs. Input Signal Level. DS21298E-page 10 © 2008 Microchip Technology Inc.

MCP3204/3208 Note: Unless otherwise indicated, V = V = 5V, V = 0V, f = 100ksps, f = 20* f , T = +25°C. DD REF SS SAMPLE CLK SAMPLE A 12.0 12.00 11.75 11.5 11.50 11.25 11.0 OB (rms)11110001....25705050 VFSDADM =P LVE R=E F5 =0 2k.s7p Vs VFSDADM =P LVE R=E1F 0=0 5k sVps OB (rms)1100..05 VFSDADM =P LVE R=E F1 =0 05 kVsps N N9.5 E10.00 E 9.75 9.0 VDD = VREF = 2.7 V 9.50 FSAMPLE = 50 ksps 9.25 8.5 9.00 8.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 1 10 100 VREF (V) Input Frequency (kHz) FIGURE 2-25: Effective Number of Bits FIGURE 2-28: Effective Number of Bits (ENOB) vs. V . (ENOB) vs. Input Frequency. REF 100 0 8900 VFSDADM =P LVE R=E F1 =0 05 kVsps n (dB)-10 o-20 dB)6700 ejecti-30 SFDR (23450000 VFSDADM =P LVE R=E F5 =0 2k.s7p Vs er Supply R---654000 w-70 10 o P 0 -80 1 10 100 1 10 100 1000 10000 Input Frequency (kHz) Ripple Frequency (kHz) FIGURE 2-26: Spurious Free Dynamic FIGURE 2-29: Power Supply Rejection Range (SFDR) vs. Input Frequency. (PSR) vs. Ripple Frequency. 0 0 -10 VDD = VREF = 5 V -10 VDD = VREF = 2.7 V -20 FSAMPLE = 100 ksps -20 FSAMPLE = 50 ksps -30 FINPUT = 9.985 kHz -30 FINPUT = 998.76 Hz Amplitude (dB)------987654000000 4096 points Amplitude (dB) ------987654000000 4096 points -100 -100 -110 -110 -120 -120 -130 -130 0 10000 20000 30000 40000 50000 0 5000 10000 15000 20000 25000 Frequency (Hz) Frequency (Hz) FIGURE 2-27: Frequency Spectrum of FIGURE 2-30: Frequency Spectrum of 10kHz input (Representative Part). 1kHz input (Representative Part, V = 2.7V). DD © 2008 Microchip Technology Inc. DS21298E-page 11

MCP3204/3208 Note: Unless otherwise indicated, V = V = 5V, V = 0V, f = 100ksps, f = 20* f , T = +25°C. DD REF SS SAMPLE CLK SAMPLE A 500 100 450 VREF = VDD 90 VREF = VDD 345000 Aatl lV pRoEFin =ts V aDtD F=C 2LK.5 = V 2, MFCHLKz ,= e 1x cMeHptz 7800 Aatl lV pRoEFin =ts V aDtD F=C 2LK.5 = V 2, MFCHLKz =e x1c MepHtz A)300 A) 60 I (µDD220500 (µREF 4500 I 150 30 100 20 50 10 0 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 V (V) V (V) DD DD FIGURE 2-31: I vs. V . FIGURE 2-34: I vs. V . DD DD REF DD 400 100 350 90 VDD = VREF = 5 V 80 300 VDD = VREF = 5 V 70 I (µA)DD122505000 VDD = VREF = 2.7 V I (µA)REF 34560000 VDD = VREF = 2.7 V 100 20 50 10 0 0 10 100 1000 10000 10 100 1000 10000 Clock Frequency (kHz) Clock Frequency (kHz) FIGURE 2-32: I vs. Clock Frequency. FIGURE 2-35: I vs. Clock Frequency. DD REF 400 100 350 VFCDLDK = = V 2R EMF H=z 5 V 90 VFCDLDK = = V 2R EMF H=z 5 V 80 300 70 250 A) A) 60 I (µDD125000 VFCDLDK = = V 1R EMF H=z 2.7 V I (µREF 345000 VDD = VREF = 2.7 V 100 FCLK = 1 MHz 20 50 10 0 0 -50 -25 0 25 50 75 100 -50 -25 0 25 50 75 100 Temperature (°C) Temperature (°C) FIGURE 2-33: I vs. Temperature. FIGURE 2-36: I vs. Temperature. DD REF DS21298E-page 12 © 2008 Microchip Technology Inc.

MCP3204/3208 Note: Unless otherwise indicated, V = V = 5V, V = 0V, f = 100ksps, f = 20* f , T = +25°C. DD REF SS SAMPLE CLK SAMPLE A 80 2.0 70 VREF = CS = VDD A)1.8 n 60 e (1.6 g1.4 a I (pA)DDS345000 nput Leak011...802 VFCDLDK = = V 2R EMF H=z 5 V 20 og I0.6 al0.4 10 An0.2 0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 -50 -25 0 25 50 75 100 VDD (V) Temperature (°C) FIGURE 2-37: I vs. V . FIGURE 2-39: Analog Input Leakage DDS DD Current vs. Temperature. 100.00 VDD = VREF = CS = 5 V 10.00 A) n (S 1.00 D D I 0.10 0.01 -50 -25 0 25 50 75 100 Temperature (°C) FIGURE 2-38: I vs. Temperature. DDS © 2008 Microchip Technology Inc. DS21298E-page 13

MCP3204/3208 NOTES: DS21298E-page 14 © 2008 Microchip Technology Inc.

MCP3204/3208 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table3-1. TABLE 3-1: PIN FUNCTION TABLE MCP3204 MCP3208 Symbol Definition PDIP, SOIC, PDIP, SOIC TSSOP 1 1 CH0 Analog Input 2 2 CH1 Analog Input 3 3 CH2 Analog Input 4 4 CH3 Analog Input — 5 CH4 Analog Input — 6 CH5 Analog Input — 7 CH6 Analog Input — 8 CH7 Analog Input 7 9 DGND Digital Ground 8 10 CS/SHDN Chip Select/Shutdown Input 9 11 D Serial Data In IN 10 12 D Serial Data Out OUT 11 13 CLK Serial Clock 12 14 AGND Analog Ground 13 15 V Reference Voltage Input REF 14 16 V +2.7V to 5.5V Power Supply DD 5, 6 — NC No Connection 3.1 Digital Ground (DGND) 3.5 Serial Data Input (D ) IN Digital ground connection to internal digital circuitry. The SPI port serial data input pin is used to load channel configuration data into the device. 3.2 Analog Ground (AGND) Analog ground connection to internal analog circuitry. 3.6 Serial Data Output (D ) OUT 3.3 Analog Inputs (CH0 - CH7) The SPI serial data output pin is used to shift out the results of the A/D conversion. Data will always change Analog inputs for channels 0 - 7 for the multiplexed on the falling edge of each clock as the conversion inputs. Each pair of channels can be programmed to be takes place. used as two independent channels in single-ended mode or as a single pseudo-differential input, where 3.7 Chip Select/Shutdown (CS/SHDN) one channel is IN+ and one channel is IN. See Section4.1 “Analog Inputs”, “Analog Inputs”, and The CS/SHDN pin is used to initiate communication Section5.0 “Serial communications”, “Serial Com- with the device when pulled low and will end a munications”, for information on programming the conversion and put the device in low power standby channel configuration. when pulled high. The CS/SHDN pin must be pulled high between conversions. 3.4 Serial Clock (CLK) The SPI clock pin is used to initiate a conversion and clock out each bit of the conversion as it takes place. See Section6.2 “Maintaining Minimum Clock Speed”, “Maintaining Minimum Clock Speed”, for con- straints on clock speed. © 2008 Microchip Technology Inc. DS21298E-page 15

MCP3204/3208 NOTES: DS21298E-page 16 © 2008 Microchip Technology Inc.

MCP3204/3208 4.0 DEVICE OPERATION 4.2 Reference Input The MCP3204/3208 A/D converters employ a For each device in the family, the reference input conventional SAR architecture. With this architecture, (VREF) determines the analog input voltage range. As a sample is acquired on an internal sample/hold the reference input is reduced, the LSB size is reduced capacitor for 1.5 clock cycles starting on the fourth accordingly. The theoretical digital output code pro- rising edge of the serial clock after the start bit has been duced by the A/D converter is a function of the analog received. Following this sample time, the device uses input signal and the reference input, as shown below. the collected charge on the internal sample/hold capacitor to produce a serial 12-bit digital output code. EQUATION 4-1: Conversion rates of 100ksps are possible on the 4096×V MCP3204/3208. See Section6.2 “Maintaining Mini- Digital Output Code = -----------------------I--N-- V mum Clock Speed”, “Maintaining Minimum Clock REF Speed”, for information on minimum clock rates. Where: Communication with the device is accomplished using a 4-wire SPI-compatible interface. VIN = analog input voltage V = reference voltage REF 4.1 Analog Inputs When using an external voltage reference device, the The MCP3204/3208 devices offer the choice of using system designer should always refer to the the analog input channels configured as single-ended manufacturer’s recommendations for circuit layout. inputs or pseudo-differential pairs. The MCP3204 can Any instability in the operation of the reference device be configured to provide two pseudo-differential input will have a direct effect on the operation of the A/D pairs or four single-ended inputs, while the MCP3208 converter. can be configured to provide four pseudo-differential input pairs or eight single-ended inputs. Configuration is done as part of the serial command before each conversion begins. When used in the pseudo- differential mode, each channel pair (i.e., CH0 and CH1, CH2 and CH3 etc.) is programmed to be the IN+ and IN- inputs as part of the command string transmit- ted to the device. The IN+ input can range from IN- to (V + IN-). The IN- input is limited to ±100mV from REF the V rail. The IN- input can be used to cancel small SS signal common-mode noise which is present on both the IN+ and IN- inputs. When operating in the pseudo-differential mode, if the voltage level of IN+ is equal to or less than IN-, the resultant code will be 000h. If the voltage at IN+ is equal to or greater than {[V + (IN-)] - 1LSB}, then the REF output code will be FFFh. If the voltage level at IN- is more than 1LSB below V , the voltage level at the SS IN+ input will have to go below V to see the 000h SS output code. Conversely, if IN- is more than 1LSB above V , then the FFFh code will not be seen unless SS the IN+ input level goes above V level. REF For the A/D converter to meet specification, the charge holding capacitor (C ) must be given enough SAMPLE time to acquire a 12-bit accurate voltage level during the 1.5 clock cycle sampling period. The analog input model is shown in Figure4-1. This diagram illustrates that the source impedance (R ) S adds to the internal sampling switch (R ) impedance, SS directly effecting the time that is required to charge the capacitor (C ). Consequently, larger source SAMPLE impedances increase the offset, gain and integral linearity errors of the conversion (see Figure4-2). © 2008 Microchip Technology Inc. DS21298E-page 17

MCP3204/3208 V DD Sampling Switch V = 0.6V RSS CHx T SS RS = 1kΩ C VA CPIN V = 0.6V ILEAKEAGE = SDAMAPCLE capacitance 7pF T ±1nA = 20pF V SS Legend VA = Signal Source Ileakage = Leakage Current At The Pin Due To Various Junctions Rss = Source Impedance SS = Sampling switch CHx = Input Channel Pad Rs = Sampling switch resistor Cpin = Input Pin Capacitance Csample = Sample/hold capacitance Vt = Threshold Voltage FIGURE 4-1: Analog Input Model. 2.5 Hz)2.0 VDD = 5 V M y ( c1.5 n e u q e1.0 k Fr VDD = 2.7 V c o0.5 Cl 0.0 100 1000 10000 Input Resistance (Ohms) FIGURE 4-2: Maximum Clock Frequency vs. Input resistance (R ) to maintain less than a S 0.1LSB deviation in INL from nominal conditions. DS21298E-page 18 © 2008 Microchip Technology Inc.

MCP3204/3208 5.0 SERIAL COMMUNICATIONS TABLE 5-1: CONFIGURATION BITS FOR THE MCP3204 Communication with the MCP3204/3208 devices is accomplished using a standard SPI-compatible serial Control Bit interface. Initiating communication with either device is Selections Input Channel done by bringing the CS line low (see Figure5-1). If the Configuration Selection Single/ device was powered up with the CS pin low, it must be D2* D1 D0 Diff brought high and back low to initiate communication. The first clock received with CS low and D high will 1 X 0 0 single-ended CH0 IN constitute a start bit. The SGL/DIFF bit follows the start 1 X 0 1 single-ended CH1 bit and will determine if the conversion will be done 1 X 1 0 single-ended CH2 using single-ended or differential input mode. The next 1 X 1 1 single-ended CH3 three bits (D0, D1 and D2) are used to select the input channel configuration. Table5-1 and Table5-2 show 0 X 0 0 differential CH0 = IN+ the configuration bits for the MCP3204 and MCP3208, CH1 = IN- respectively. The device will begin to sample the 0 X 0 1 differential CH0 = IN- analog input on the fourth rising edge of the clock after CH1 = IN+ the start bit has been received. The sample period will 0 X 1 0 differential CH2 = IN+ end on the falling edge of the fifth clock following the CH3 = IN- start bit. 0 X 1 1 differential CH2 = IN- Once the D0 bit is input, one more clock is required to CH3 = IN+ complete the sample and hold period (D is a “don’t IN * D2 is a “don’t care” for MCP3204 care” for this clock). On the falling edge of the next clock, the device will output a low null bit. The next 12 TABLE 5-2: CONFIGURATION BITS FOR clocks will output the result of the conversion with MSB THE MCP3208 first, as shown in Figure5-1. Data is always output from the device on the falling edge of the clock. If all 12 data Control Bit bits have been transmitted and the device continues to Selections Input Channel receive clocks while the CS is held low, the device will Configuration Selection output the conversion result LSB first, as shown in Single D2 D1 D0 Figure5-2. If more clocks are provided to the device /Diff while CS is still low (after the LSB first data has been 1 0 0 0 single-ended CH0 transmitted), the device will clock out zeros indefinitely. 1 0 0 1 single-ended CH1 If necessary, it is possible to bring CS low and clock in 1 0 1 0 single-ended CH2 leading zeros on the D line before the start bit. This is IN 1 0 1 1 single-ended CH3 often done when dealing with microcontroller-based SPI ports that must send 8 bits at a time. Refer to 1 1 0 0 single-ended CH4 Section6.1 “Using the MCP3204/3208 with Micro- 1 1 0 1 single-ended CH5 controller (MCU) SPI Ports” for more details on using 1 1 1 0 single-ended CH6 the MCP3204/3208 devices with hardware SPI ports. 1 1 1 1 single-ended CH7 0 0 0 0 differential CH0 = IN+ CH1 = IN- 0 0 0 1 differential CH0 = IN- CH1 = IN+ 0 0 1 0 differential CH2 = IN+ CH3 = IN- 0 0 1 1 differential CH2 = IN- CH3 = IN+ 0 1 0 0 differential CH4 = IN+ CH5 = IN- 0 1 0 1 differential CH4 = IN- CH5 = IN+ 0 1 1 0 differential CH6 = IN+ CH7 = IN- 0 1 1 1 differential CH6 = IN- CH7 = IN+ © 2008 Microchip Technology Inc. DS21298E-page 19

MCP3204/3208 tCYC tCYC t CSH CS t SUCS CLK DIN Start SDGIFLF/ D2 D1 D0 Don’t Care StartSDGIFLF/ D2 HI-Z Null HI-Z DOUT Bit B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0* t CONV t t ** SAMPLE DATA * After completing the data transfer, if further clocks are applied with CS low, the A/D converter will output LSB first data, followed by zeros indefinitely (see Figure5-2 below). ** t : during this time, the bias current and the comparator power down while the reference input becomes DATA a high impedance node, leaving the CLK running to clock out the LSB-first data or zeros. FIGURE 5-1: Communication with the MCP3204 or MCP3208. t CYC t CSH CS t SUCS Power Down CLK Start DIN D2D1D0 Don’t Care SGL/ DIFF HI-Z Null * HI-Z DOUT Bit B11B10B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9B10B11 (MSB) t tCONV tDATA ** SAMPLE * After completing the data transfer, if further clocks are applied with CS low, the A/D converter will output zeros indefinitely. ** t : During this time, the bias circuit and the comparator power down while the reference input becomes a DATA high impedance node, leaving the CLK running to clock out LSB first data or zeroes. FIGURE 5-2: Communication with MCP3204 or MCP3208 in LSB First Format. DS21298E-page 20 © 2008 Microchip Technology Inc.

MCP3204/3208 6.0 APPLICATIONS INFORMATION As is shown in Figure6-1, the first byte transmitted to the A/D converter contains five leading zeros before the start bit. Arranging the leading zeros this way 6.1 Using the MCP3204/3208 with allows the output 12 bits to fall in positions easily Microcontroller (MCU) SPI Ports manipulated by the MCU. The MSB is clocked out of With most microcontroller SPI ports, it is required to the A/D converter on the falling edge of clock number send groups of eight bits. It is also required that the 12. Once the second eight clocks have been sent to the microcontroller SPI port be configured to clock out data device, the MCU’s receive buffer will contain three on the falling edge of clock and latch data in on the unknown bits (the output is at high impedance for the rising edge. Because communication with the first two clocks), the null bit and the highest order four MCP3204/3208 devices may not need multiples of bits of the conversion. Once the third byte has been eight clocks, it will be necessary to provide more clocks sent to the device, the receive register will contain the than are required. This is usually done by sending lowest order eight bits of the conversion results. ‘leading zeros’ before the start bit. As an example, Employing this method ensures simpler manipulation Figure6-1 and Figure6-2 illustrate how the MCP3204/ of the converted data. 3208 can be interfaced to a MCU with a hardware SPI Figure6-2 shows the same thing in SPI Mode 1,1, port. Figure6-1 depicts the operation shown in SPI which requires that the clock idles in the high state. As Mode 0,0, which requires that the SCLK from the MCU with mode 0,0, the A/D converter outputs data on the idles in the ‘low’ state, while Figure6-2 shows the falling edge of the clock and the MCU latches data from similar case of SPI Mode 1,1, where the clock idles in the A/D converter in on the rising edge of the clock. the ‘high’ state. CS MCU latches data from A/D converter on rising edges of SCLK SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 2233 24 Data is clocked out of A/D converter on falling edges DIN StartSDGIFLF/ D2 D1 DO DDonon’t’ tC Caarree DOUT HI-Z NUBLITL B11B10 B9 B8 B7 B6 B5 B4 B3 B2 BB11 B0 Start MCU Transmitted Data Bit (eAdlgigen oefd c wloitchk )falling 00 00 00 00 00 11 DSSDGIGIFFLFLF//DD22 DD11 DDOO XX XX XX XX XX XXX XX XX XX XX XX XX XX XX MCU Received Data (eAdlgigen oefd c wloitchk )rising ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ((NN00uullll))BB1111BB1100 BB99 BB88 BB77 BB66 BB55 BB44 BB33 BB22 BB11 BB00 Data stored into MCU receive Data stored into MCU receive Data stored into MCU receive register after transmission of first register after transmission of register after transmission of last X = “Don’t Care” Bits 8 bits second 8 bits 8 bits FIGURE 6-1: SPI Communication using 8-bit segments (Mode 0,0: SCLK idles low). © 2008 Microchip Technology Inc. DS21298E-page 21

MCP3204/3208 CS MCU latches data from A/D converter on rising edges of SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SCLK Data is clocked out of A/D converter on falling edges DIN StartSDGIFLF/ D2 D1 DDOO Don’t Care DOUT HI-Z NBUILTLB11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Start MCU Transmitted Data Bit (Aligned with falling 0 0 0 0 0 1 SGL/ D2 D1 DO X X X X X X X X X X X X X X edge of clock) DIFF MCU Received Data (Aligned with rising ? ? ? ? ? ? ? ? ? ? ? (N0ull)B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 edge of clock) Data stored into MCU receive Data stored into MCU receive Data stored into MCU receive register after transmission of first register after transmission of register after transmission of last X = “Don’t Care” Bits 8 bits second 8 bits 8 bits FIGURE 6-2: SPI Communication using 8-bit segments (Mode 1,1: SCLK idles high). 6.2 Maintaining Minimum Clock Speed 6.3 Buffering/Filtering the Analog Inputs When the MCP3204/3208 initiates the sample period, charge is stored on the sample capacitor. When the If the signal source for the A/D converter is not a low sample period is complete, the device converts one bit impedance source, it will have to be buffered or inaccu- for each clock that is received. It is important for the rate conversion results may occur (see Figure4-2). It is user to note that a slow clock rate will allow charge to also recommended that a filter be used to eliminate any bleed off the sample capacitor while the conversion is signals that may be aliased back into the conversion taking place. At 85°C (worst case condition), the part results, as is illustrated in Figure6-3, where an op amp will maintain proper charge on the sample capacitor for is used to drive the analog input of the MCP3204/3208. at least 1.2ms after the sample period has ended. This This amplifier provides a low impedance source for the means that the time between the end of the sample converter input, and a low pass filter, which eliminates period and the time that all 12 data bits have been unwanted high frequency noise. clocked out must not exceed 1.2ms (effective clock Low-pass (anti-aliasing) filters can be designed using frequency of 10kHz). Failure to meet this criterion may Microchip’s free interactive FilterLab® software. Filter- introduce linearity errors into the conversion outside Lab will calculate capacitor and resistor values, as well the rated specifications. It should be noted that during as determine the number of poles that are required for the entire conversion cycle, the A/D converter does not the application. For more information on filtering require a constant clock speed or duty cycle, as long as signals, see AN699, “Anti-Aliasing Analog Filters for all timing specifications are met. Data Acquisition Systems”. DS21298E-page 22 © 2008 Microchip Technology Inc.

MCP3204/3208 V DD 10µF 4.096V Reference 0.1µF 1µF MCP1541 1µF IN+ V REF MCP3204 C1 MCP601 IN- R 1 V + IN R 2 - C 2 R 4 R 3 FIGURE 6-3: The MCP601 Operational Amplifier is used to implement a second order anti-aliasing filter for the signal being converted by the MCP3204. 6.4 Layout Considerations V DD When laying out a printed circuit board for use with Connection analog components, care should be taken to reduce noise wherever possible. A bypass capacitor should always be used with this device, placed as close as possible to the device pin. A bypass capacitor value of 1µF is recommended. Digital and analog traces should be separated as much Device 4 as possible on the board, with no traces running Device 1 underneath the device or the bypass capacitor. Extra precautions should be taken to keep traces with high frequency signals (such as clock lines) as far as possible from analog traces. Use of an analog ground plane is recommended in Device 3 order to keep the ground potential the same for all devices on the board. Providing V connections to DD devices in a “star” configuration can also reduce noise by eliminating return current paths and associated Device 2 errors (see Figure6-4). For more information on layout tips when using A/D converters, refer to AN688, “Layout Tips for 12-Bit A/D converter Applications”. FIGURE 6-4: V traces arranged in a DD ‘Star’ configuration in order to reduce errors caused by current return paths. © 2008 Microchip Technology Inc. DS21298E-page 23

MCP3204/3208 6.5 Utilizing the Digital and Analog Ground Pins The MCP3204/3208 devices provide both digital and analog ground connections to provide another means of noise reduction. As shown in Figure6-5, the analog and digital circuitry is separated internal to the device. This reduces noise from the digital portion of the device being coupled into the analog portion of the device. The two grounds are connected internally through the substrate, which has a resistance of 5 -10Ω. If no ground plane is utilized, then both grounds must be connected to V on the board. If a ground plane is SS available, both digital and analog ground pins should be connected to the analog ground plane. If both an analog and a digital ground plane are available, both the digital and the analog ground pins should be connected to the analog ground plane. Following these steps will reduce the amount of digital noise from the rest of the board being coupled into the A/D converter. V DD MCP3204/08 Digital Side Analog Side -SPI Interface -Sample Cap -Shift Register -Capacitor Array -Control Logic -Comparator Substrate 5 - 10Ω DGND AGND 0.1µF Analog Ground Plane FIGURE 6-5: Separation of Analog and Digital Ground Pins. DS21298E-page 24 © 2008 Microchip Technology Inc.

MCP3204/3208 7.0 PACKAGING INFORMATION 7.1 Package Marking Information 14-Lead PDIP (300 mil) (MCP3204) Example: XXXXXXXXXXXXXX MCP3204-B XXXXXXXXXXXXXX I/Pe3 YYWWNNN 0819256 14-Lead SOIC (150 mil) (MCP3204) Example: XXXXXXXXXXX MCP3204-B XXXXXXXXXXX XXXXXXXII//SXLXeX3X YYWWNNN 0819256 14-Lead TSSOP (4.4mm)* (MCP3204) Example: XXXXXXXX 3204-C YYWW 0819 NNN 256 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2008 Microchip Technology Inc. DS21298E-page 25

MCP3204/3208 Package Marking Information (Continued) 16-Lead PDIP (300 mil) (MCP3208) Example: XXXXXXXXXXXXXX MCP3208-BI/P e3 XXXXXXXXXXXXXX 0819256 YYWWNNN 16-Lead SOIC (150 mil) (MCP3208) Example: XXXXXXXXXXXXX MCP3208-B XXXXXXXXXXXXX XXXXII/SXLXeX3XXX YYWWNNN 0819256 DS21298E-page 26 © 2008 Microchip Technology Inc.

MCP3204/3208 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:7)(cid:11)(cid:9)(cid:18)(cid:19)(cid:4)(cid:5)(cid:14)(cid:19)(cid:6)(cid:9)(cid:20)(cid:10)(cid:21)(cid:9)(cid:22)(cid:9)(cid:23)(cid:24)(cid:24)(cid:9)(cid:25)(cid:14)(cid:11)(cid:9)(cid:26)(cid:27)(cid:8)(cid:28)(cid:9)(cid:29)(cid:10)(cid:16)(cid:18)(cid:10)(cid:30) (cid:31)(cid:27)(cid:13)(cid:6) 3(cid:10)(cid:9)(cid:2)%(cid:11)(cid:14)(cid:2)&(cid:10) %(cid:2)(cid:8)!(cid:9)(cid:9)(cid:14)(cid:15)%(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)"(cid:9)(cid:28))(cid:7)(cid:15)(cid:17) ’(cid:2)(cid:12)(cid:16)(cid:14)(cid:28) (cid:14)(cid:2) (cid:14)(cid:14)(cid:2)%(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:30)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)$(cid:7)(cid:8)(cid:28)%(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)%(cid:14)"(cid:2)(cid:28)%(cid:2) (cid:11)%%(cid:12)255)))(cid:20)&(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)&5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) N NOTE1 E1 1 2 3 D E A A2 L c A1 b1 b e eB 6(cid:15)(cid:7)% (cid:19)7+8-(cid:22) (cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)&(cid:7)% (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7!&((cid:14)(cid:9)(cid:2)(cid:10)$(cid:2)(cid:30)(cid:7)(cid:15) 7 (cid:29)(cid:23) (cid:30)(cid:7)%(cid:8)(cid:11) (cid:14) (cid:20)(cid:29)(cid:4)(cid:4)(cid:2)1(cid:22)+ (cid:13)(cid:10)(cid:12)(cid:2)%(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)%(cid:7)(cid:15)(cid:17)(cid:2)(cid:30)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25) < < (cid:20)(cid:3)(cid:29)(cid:4) (cid:6)(cid:10)(cid:16)"(cid:14)"(cid:2)(cid:30)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14) (cid:25)(cid:3) (cid:20)(cid:29)(cid:29)0 (cid:20)(cid:29),(cid:4) (cid:20)(cid:29)(cid:24)0 1(cid:28) (cid:14)(cid:2)%(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)%(cid:7)(cid:15)(cid:17)(cid:2)(cid:30)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25)(cid:29) (cid:20)(cid:4)(cid:29)0 < < (cid:22)(cid:11)(cid:10)!(cid:16)"(cid:14)(cid:9)(cid:2)%(cid:10)(cid:2)(cid:22)(cid:11)(cid:10)!(cid:16)"(cid:14)(cid:9)(cid:2)=(cid:7)"%(cid:11) - (cid:20)(cid:3)(cid:24)(cid:4) (cid:20),(cid:29)(cid:4) (cid:20),(cid:3)0 (cid:6)(cid:10)(cid:16)"(cid:14)"(cid:2)(cid:30)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)=(cid:7)"%(cid:11) -(cid:29) (cid:20)(cid:3)(cid:23)(cid:4) (cid:20)(cid:3)0(cid:4) (cid:20)(cid:3)>(cid:4) :(cid:31)(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)%(cid:11) (cid:21) (cid:20)(cid:5),0 (cid:20)(cid:5)0(cid:4) (cid:20)(cid:5)(cid:5)0 (cid:13)(cid:7)(cid:12)(cid:2)%(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)%(cid:7)(cid:15)(cid:17)(cid:2)(cid:30)(cid:16)(cid:28)(cid:15)(cid:14) 9 (cid:20)(cid:29)(cid:29)0 (cid:20)(cid:29),(cid:4) (cid:20)(cid:29)0(cid:4) 9(cid:14)(cid:28)"(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14) (cid:8) (cid:20)(cid:4)(cid:4)> (cid:20)(cid:4)(cid:29)(cid:4) (cid:20)(cid:4)(cid:29)0 6(cid:12)(cid:12)(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)"(cid:2)=(cid:7)"%(cid:11) ((cid:29) (cid:20)(cid:4)(cid:23)0 (cid:20)(cid:4)?(cid:4) (cid:20)(cid:4)(cid:5)(cid:4) 9(cid:10))(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)"(cid:2)=(cid:7)"%(cid:11) ( (cid:20)(cid:4)(cid:29)(cid:23) (cid:20)(cid:4)(cid:29)> (cid:20)(cid:4)(cid:3)(cid:3) :(cid:31)(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)(cid:26)(cid:10))(cid:2)(cid:22)(cid:12)(cid:28)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:2)* (cid:14)1 < < (cid:20)(cid:23),(cid:4) (cid:31)(cid:27)(cid:13)(cid:6)(cid:12) (cid:29)(cid:20) (cid:30)(cid:7)(cid:15)(cid:2)(cid:29)(cid:2)(cid:31)(cid:7) !(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)"(cid:14)#(cid:2)$(cid:14)(cid:28)%!(cid:9)(cid:14)(cid:2)&(cid:28)(cid:18)(cid:2)(cid:31)(cid:28)(cid:9)(cid:18)’(cid:2)(!%(cid:2)&! %(cid:2)((cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)%(cid:14)"(cid:2))(cid:7)%(cid:11)(cid:2)%(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)%(cid:8)(cid:11)(cid:14)"(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) *(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)$(cid:7)(cid:8)(cid:28)(cid:15)%(cid:2)+(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)%(cid:14)(cid:9)(cid:7) %(cid:7)(cid:8)(cid:20) ,(cid:20) (cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15) (cid:2)(cid:21)(cid:2)(cid:28)(cid:15)"(cid:2)-(cid:29)(cid:2)"(cid:10)(cid:2)(cid:15)(cid:10)%(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)!"(cid:14)(cid:2)&(cid:10)(cid:16)"(cid:2)$(cid:16)(cid:28) (cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)%(cid:9)! (cid:7)(cid:10)(cid:15) (cid:20)(cid:2)(cid:6)(cid:10)(cid:16)"(cid:2)$(cid:16)(cid:28) (cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)%(cid:9)! (cid:7)(cid:10)(cid:15) (cid:2) (cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)%(cid:2)(cid:14)#(cid:8)(cid:14)(cid:14)"(cid:2)(cid:20)(cid:4)(cid:29)(cid:4).(cid:2)(cid:12)(cid:14)(cid:9)(cid:2) (cid:7)"(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)"(cid:2)%(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6)-(cid:2)/(cid:29)(cid:23)(cid:20)0(cid:6)(cid:20) 1(cid:22)+2(cid:2)1(cid:28) (cid:7)(cid:8)(cid:2)(cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)%(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)#(cid:28)(cid:8)%(cid:2)(cid:31)(cid:28)(cid:16)!(cid:14)(cid:2) (cid:11)(cid:10))(cid:15)(cid:2))(cid:7)%(cid:11)(cid:10)!%(cid:2)%(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14) (cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28))(cid:7)(cid:15)(cid:17)+(cid:4)(cid:23)(cid:27)(cid:4)(cid:4)01 © 2008 Microchip Technology Inc. DS21298E-page 27

MCP3204/3208 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)!(cid:25)(cid:7)(cid:11)(cid:11)(cid:9)"(cid:17)(cid:13)(cid:11)(cid:14)(cid:19)(cid:6)(cid:9)(cid:20)!(cid:5)(cid:21)(cid:9)(cid:22)(cid:9)(cid:31)(cid:7)##(cid:27)$%(cid:9)(cid:23)&’(cid:24)(cid:9)(cid:25)(cid:25)(cid:9)(cid:26)(cid:27)(cid:8)(cid:28)(cid:9)(cid:29)!"(cid:18)((cid:30) (cid:31)(cid:27)(cid:13)(cid:6) 3(cid:10)(cid:9)(cid:2)%(cid:11)(cid:14)(cid:2)&(cid:10) %(cid:2)(cid:8)!(cid:9)(cid:9)(cid:14)(cid:15)%(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)"(cid:9)(cid:28))(cid:7)(cid:15)(cid:17) ’(cid:2)(cid:12)(cid:16)(cid:14)(cid:28) (cid:14)(cid:2) (cid:14)(cid:14)(cid:2)%(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:30)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)$(cid:7)(cid:8)(cid:28)%(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)%(cid:14)"(cid:2)(cid:28)%(cid:2) (cid:11)%%(cid:12)255)))(cid:20)&(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)&5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D N E E1 NOTE1 1 2 3 e h b α h c φ A A2 A1 L L1 β 6(cid:15)(cid:7)% (cid:6)(cid:19)99(cid:19)(cid:6)-(cid:13)-(cid:26)(cid:22) (cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)&(cid:7)% (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7!&((cid:14)(cid:9)(cid:2)(cid:10)$(cid:2)(cid:30)(cid:7)(cid:15) 7 (cid:29)(cid:23) (cid:30)(cid:7)%(cid:8)(cid:11) (cid:14) (cid:29)(cid:20)(cid:3)(cid:5)(cid:2)1(cid:22)+ :(cid:31)(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)% (cid:25) < < (cid:29)(cid:20)(cid:5)0 (cid:6)(cid:10)(cid:16)"(cid:14)"(cid:2)(cid:30)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14) (cid:25)(cid:3) (cid:29)(cid:20)(cid:3)0 < < (cid:22)%(cid:28)(cid:15)"(cid:10)$$(cid:2)(cid:2)* (cid:25)(cid:29) (cid:4)(cid:20)(cid:29)(cid:4) < (cid:4)(cid:20)(cid:3)0 :(cid:31)(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)=(cid:7)"%(cid:11) - ?(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22)+ (cid:6)(cid:10)(cid:16)"(cid:14)"(cid:2)(cid:30)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)=(cid:7)"%(cid:11) -(cid:29) ,(cid:20)(cid:24)(cid:4)(cid:2)1(cid:22)+ :(cid:31)(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)%(cid:11) (cid:21) >(cid:20)?0(cid:2)1(cid:22)+ +(cid:11)(cid:28)&$(cid:14)(cid:9)(cid:2)@(cid:10)(cid:12)%(cid:7)(cid:10)(cid:15)(cid:28)(cid:16)A (cid:11) (cid:4)(cid:20)(cid:3)0 < (cid:4)(cid:20)0(cid:4) 3(cid:10)(cid:10)%(cid:2)9(cid:14)(cid:15)(cid:17)%(cid:11) 9 (cid:4)(cid:20)(cid:23)(cid:4) < (cid:29)(cid:20)(cid:3)(cid:5) 3(cid:10)(cid:10)%(cid:12)(cid:9)(cid:7)(cid:15)% 9(cid:29) (cid:29)(cid:20)(cid:4)(cid:23)(cid:2)(cid:26)-3 3(cid:10)(cid:10)%(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)B < >B 9(cid:14)(cid:28)"(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14) (cid:8) (cid:4)(cid:20)(cid:29)(cid:5) < (cid:4)(cid:20)(cid:3)0 9(cid:14)(cid:28)"(cid:2)=(cid:7)"%(cid:11) ( (cid:4)(cid:20),(cid:29) < (cid:4)(cid:20)0(cid:29) (cid:6)(cid:10)(cid:16)"(cid:2)(cid:21)(cid:9)(cid:28)$%(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14)(cid:2)(cid:13)(cid:10)(cid:12) (cid:4) 0B < (cid:29)0B (cid:6)(cid:10)(cid:16)"(cid:2)(cid:21)(cid:9)(cid:28)$%(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14)(cid:2)1(cid:10)%%(cid:10)& (cid:5) 0B < (cid:29)0B (cid:31)(cid:27)(cid:13)(cid:6)(cid:12) (cid:29)(cid:20) (cid:30)(cid:7)(cid:15)(cid:2)(cid:29)(cid:2)(cid:31)(cid:7) !(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)"(cid:14)#(cid:2)$(cid:14)(cid:28)%!(cid:9)(cid:14)(cid:2)&(cid:28)(cid:18)(cid:2)(cid:31)(cid:28)(cid:9)(cid:18)’(cid:2)(!%(cid:2)&! %(cid:2)((cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)%(cid:14)"(cid:2))(cid:7)%(cid:11)(cid:7)(cid:15)(cid:2)%(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)%(cid:8)(cid:11)(cid:14)"(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) *(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)$(cid:7)(cid:8)(cid:28)(cid:15)%(cid:2)+(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)%(cid:14)(cid:9)(cid:7) %(cid:7)(cid:8)(cid:20) ,(cid:20) (cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15) (cid:2)(cid:21)(cid:2)(cid:28)(cid:15)"(cid:2)-(cid:29)(cid:2)"(cid:10)(cid:2)(cid:15)(cid:10)%(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)!"(cid:14)(cid:2)&(cid:10)(cid:16)"(cid:2)$(cid:16)(cid:28) (cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)%(cid:9)! (cid:7)(cid:10)(cid:15) (cid:20)(cid:2)(cid:6)(cid:10)(cid:16)"(cid:2)$(cid:16)(cid:28) (cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)%(cid:9)! (cid:7)(cid:10)(cid:15) (cid:2) (cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)%(cid:2)(cid:14)#(cid:8)(cid:14)(cid:14)"(cid:2)(cid:4)(cid:20)(cid:29)0(cid:2)&&(cid:2)(cid:12)(cid:14)(cid:9)(cid:2) (cid:7)"(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)"(cid:2)%(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6)-(cid:2)/(cid:29)(cid:23)(cid:20)0(cid:6)(cid:20) 1(cid:22)+2 1(cid:28) (cid:7)(cid:8)(cid:2)(cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)%(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)#(cid:28)(cid:8)%(cid:2)(cid:31)(cid:28)(cid:16)!(cid:14)(cid:2) (cid:11)(cid:10))(cid:15)(cid:2))(cid:7)%(cid:11)(cid:10)!%(cid:2)%(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14) (cid:20) (cid:26)-32 (cid:26)(cid:14)$(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)’(cid:2)! !(cid:28)(cid:16)(cid:16)(cid:18)(cid:2))(cid:7)%(cid:11)(cid:10)!%(cid:2)%(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)’(cid:2)$(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)$(cid:10)(cid:9)&(cid:28)%(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)!(cid:9)(cid:12)(cid:10) (cid:14) (cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28))(cid:7)(cid:15)(cid:17)+(cid:4)(cid:23)(cid:27)(cid:4)?01 DS21298E-page 28 © 2008 Microchip Technology Inc.

MCP3204/3208 (cid:31)(cid:27)(cid:13)(cid:6) 3(cid:10)(cid:9)(cid:2)%(cid:11)(cid:14)(cid:2)&(cid:10) %(cid:2)(cid:8)!(cid:9)(cid:9)(cid:14)(cid:15)%(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)"(cid:9)(cid:28))(cid:7)(cid:15)(cid:17) ’(cid:2)(cid:12)(cid:16)(cid:14)(cid:28) (cid:14)(cid:2) (cid:14)(cid:14)(cid:2)%(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:30)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)$(cid:7)(cid:8)(cid:28)%(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)%(cid:14)"(cid:2)(cid:28)%(cid:2) (cid:11)%%(cid:12)255)))(cid:20)&(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)&5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) © 2008 Microchip Technology Inc. DS21298E-page 29

MCP3204/3208 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9))*(cid:14)(cid:19)(cid:9)!*#(cid:14)(cid:19)+(cid:9)!(cid:25)(cid:7)(cid:11)(cid:11)(cid:9)"(cid:17)(cid:13)(cid:11)(cid:14)(cid:19)(cid:6)(cid:9)(cid:20)!)(cid:21)(cid:9)(cid:22)(cid:9)(cid:3)&(cid:3)(cid:9)(cid:25)(cid:25)(cid:9)(cid:26)(cid:27)(cid:8)(cid:28)(cid:9)(cid:29))!!"(cid:10)(cid:30) (cid:31)(cid:27)(cid:13)(cid:6) 3(cid:10)(cid:9)(cid:2)%(cid:11)(cid:14)(cid:2)&(cid:10) %(cid:2)(cid:8)!(cid:9)(cid:9)(cid:14)(cid:15)%(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)"(cid:9)(cid:28))(cid:7)(cid:15)(cid:17) ’(cid:2)(cid:12)(cid:16)(cid:14)(cid:28) (cid:14)(cid:2) (cid:14)(cid:14)(cid:2)%(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:30)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)$(cid:7)(cid:8)(cid:28)%(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)%(cid:14)"(cid:2)(cid:28)%(cid:2) (cid:11)%%(cid:12)255)))(cid:20)&(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)&5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D N E E1 NOTE1 1 2 e b c φ A A2 A1 L1 L 6(cid:15)(cid:7)% (cid:6)(cid:19)99(cid:19)(cid:6)-(cid:13)-(cid:26)(cid:22) (cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)&(cid:7)% (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7!&((cid:14)(cid:9)(cid:2)(cid:10)$(cid:2)(cid:30)(cid:7)(cid:15) 7 (cid:29)(cid:23) (cid:30)(cid:7)%(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)?0(cid:2)1(cid:22)+ :(cid:31)(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)% (cid:25) < < (cid:29)(cid:20)(cid:3)(cid:4) (cid:6)(cid:10)(cid:16)"(cid:14)"(cid:2)(cid:30)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14) (cid:25)(cid:3) (cid:4)(cid:20)>(cid:4) (cid:29)(cid:20)(cid:4)(cid:4) (cid:29)(cid:20)(cid:4)0 (cid:22)%(cid:28)(cid:15)"(cid:10)$$(cid:2) (cid:25)(cid:29) (cid:4)(cid:20)(cid:4)0 < (cid:4)(cid:20)(cid:29)0 :(cid:31)(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)=(cid:7)"%(cid:11) - ?(cid:20)(cid:23)(cid:4)(cid:2)1(cid:22)+ (cid:6)(cid:10)(cid:16)"(cid:14)"(cid:2)(cid:30)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)=(cid:7)"%(cid:11) -(cid:29) (cid:23)(cid:20),(cid:4) (cid:23)(cid:20)(cid:23)(cid:4) (cid:23)(cid:20)0(cid:4) (cid:6)(cid:10)(cid:16)"(cid:14)"(cid:2)(cid:30)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)9(cid:14)(cid:15)(cid:17)%(cid:11) (cid:21) (cid:23)(cid:20)(cid:24)(cid:4) 0(cid:20)(cid:4)(cid:4) 0(cid:20)(cid:29)(cid:4) 3(cid:10)(cid:10)%(cid:2)9(cid:14)(cid:15)(cid:17)%(cid:11) 9 (cid:4)(cid:20)(cid:23)0 (cid:4)(cid:20)?(cid:4) (cid:4)(cid:20)(cid:5)0 3(cid:10)(cid:10)%(cid:12)(cid:9)(cid:7)(cid:15)% 9(cid:29) (cid:29)(cid:20)(cid:4)(cid:4)(cid:2)(cid:26)-3 3(cid:10)(cid:10)%(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)B < >B 9(cid:14)(cid:28)"(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14) (cid:8) (cid:4)(cid:20)(cid:4)(cid:24) < (cid:4)(cid:20)(cid:3)(cid:4) 9(cid:14)(cid:28)"(cid:2)=(cid:7)"%(cid:11) ( (cid:4)(cid:20)(cid:29)(cid:24) < (cid:4)(cid:20),(cid:4) (cid:31)(cid:27)(cid:13)(cid:6)(cid:12) (cid:29)(cid:20) (cid:30)(cid:7)(cid:15)(cid:2)(cid:29)(cid:2)(cid:31)(cid:7) !(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)"(cid:14)#(cid:2)$(cid:14)(cid:28)%!(cid:9)(cid:14)(cid:2)&(cid:28)(cid:18)(cid:2)(cid:31)(cid:28)(cid:9)(cid:18)’(cid:2)(!%(cid:2)&! %(cid:2)((cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)%(cid:14)"(cid:2))(cid:7)%(cid:11)(cid:7)(cid:15)(cid:2)%(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)%(cid:8)(cid:11)(cid:14)"(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15) (cid:2)(cid:21)(cid:2)(cid:28)(cid:15)"(cid:2)-(cid:29)(cid:2)"(cid:10)(cid:2)(cid:15)(cid:10)%(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)!"(cid:14)(cid:2)&(cid:10)(cid:16)"(cid:2)$(cid:16)(cid:28) (cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)%(cid:9)! (cid:7)(cid:10)(cid:15) (cid:20)(cid:2)(cid:6)(cid:10)(cid:16)"(cid:2)$(cid:16)(cid:28) (cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)%(cid:9)! (cid:7)(cid:10)(cid:15) (cid:2) (cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)%(cid:2)(cid:14)#(cid:8)(cid:14)(cid:14)"(cid:2)(cid:4)(cid:20)(cid:29)0(cid:2)&&(cid:2)(cid:12)(cid:14)(cid:9)(cid:2) (cid:7)"(cid:14)(cid:20) ,(cid:20) (cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)"(cid:2)%(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6)-(cid:2)/(cid:29)(cid:23)(cid:20)0(cid:6)(cid:20) 1(cid:22)+2 1(cid:28) (cid:7)(cid:8)(cid:2)(cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)%(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)#(cid:28)(cid:8)%(cid:2)(cid:31)(cid:28)(cid:16)!(cid:14)(cid:2) (cid:11)(cid:10))(cid:15)(cid:2))(cid:7)%(cid:11)(cid:10)!%(cid:2)%(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14) (cid:20) (cid:26)-32 (cid:26)(cid:14)$(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)’(cid:2)! !(cid:28)(cid:16)(cid:16)(cid:18)(cid:2))(cid:7)%(cid:11)(cid:10)!%(cid:2)%(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)’(cid:2)$(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)$(cid:10)(cid:9)&(cid:28)%(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)!(cid:9)(cid:12)(cid:10) (cid:14) (cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28))(cid:7)(cid:15)(cid:17)+(cid:4)(cid:23)(cid:27)(cid:4)>(cid:5)1 DS21298E-page 30 © 2008 Microchip Technology Inc.

MCP3204/3208 (cid:2),(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:7)(cid:11)(cid:9)(cid:18)(cid:19)(cid:4)(cid:5)(cid:14)(cid:19)(cid:6)(cid:9)(cid:20)(cid:10)(cid:21)(cid:9)(cid:22)(cid:9)(cid:23)(cid:24)(cid:24)(cid:9)(cid:25)(cid:14)(cid:11)(cid:9)(cid:26)(cid:27)(cid:8)(cid:28)(cid:9)(cid:29)(cid:10)(cid:16)(cid:18)(cid:10)(cid:30) (cid:31)(cid:27)(cid:13)(cid:6) 3(cid:10)(cid:9)(cid:2)%(cid:11)(cid:14)(cid:2)&(cid:10) %(cid:2)(cid:8)!(cid:9)(cid:9)(cid:14)(cid:15)%(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)"(cid:9)(cid:28))(cid:7)(cid:15)(cid:17) ’(cid:2)(cid:12)(cid:16)(cid:14)(cid:28) (cid:14)(cid:2) (cid:14)(cid:14)(cid:2)%(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:30)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)$(cid:7)(cid:8)(cid:28)%(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)%(cid:14)"(cid:2)(cid:28)%(cid:2) (cid:11)%%(cid:12)255)))(cid:20)&(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)&5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) N NOTE1 E1 1 2 3 D E A A2 L c A1 b1 b e eB 6(cid:15)(cid:7)% (cid:19)7+8-(cid:22) (cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)&(cid:7)% (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7!&((cid:14)(cid:9)(cid:2)(cid:10)$(cid:2)(cid:30)(cid:7)(cid:15) 7 (cid:29)? (cid:30)(cid:7)%(cid:8)(cid:11) (cid:14) (cid:20)(cid:29)(cid:4)(cid:4)(cid:2)1(cid:22)+ (cid:13)(cid:10)(cid:12)(cid:2)%(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)%(cid:7)(cid:15)(cid:17)(cid:2)(cid:30)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25) < < (cid:20)(cid:3)(cid:29)(cid:4) (cid:6)(cid:10)(cid:16)"(cid:14)"(cid:2)(cid:30)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14) (cid:25)(cid:3) (cid:20)(cid:29)(cid:29)0 (cid:20)(cid:29),(cid:4) (cid:20)(cid:29)(cid:24)0 1(cid:28) (cid:14)(cid:2)%(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)%(cid:7)(cid:15)(cid:17)(cid:2)(cid:30)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25)(cid:29) (cid:20)(cid:4)(cid:29)0 < < (cid:22)(cid:11)(cid:10)!(cid:16)"(cid:14)(cid:9)(cid:2)%(cid:10)(cid:2)(cid:22)(cid:11)(cid:10)!(cid:16)"(cid:14)(cid:9)(cid:2)=(cid:7)"%(cid:11) - (cid:20)(cid:3)(cid:24)(cid:4) (cid:20),(cid:29)(cid:4) (cid:20),(cid:3)0 (cid:6)(cid:10)(cid:16)"(cid:14)"(cid:2)(cid:30)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)=(cid:7)"%(cid:11) -(cid:29) (cid:20)(cid:3)(cid:23)(cid:4) (cid:20)(cid:3)0(cid:4) (cid:20)(cid:3)>(cid:4) :(cid:31)(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)%(cid:11) (cid:21) (cid:20)(cid:5),0 (cid:20)(cid:5)00 (cid:20)(cid:5)(cid:5)0 (cid:13)(cid:7)(cid:12)(cid:2)%(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)%(cid:7)(cid:15)(cid:17)(cid:2)(cid:30)(cid:16)(cid:28)(cid:15)(cid:14) 9 (cid:20)(cid:29)(cid:29)0 (cid:20)(cid:29),(cid:4) (cid:20)(cid:29)0(cid:4) 9(cid:14)(cid:28)"(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14) (cid:8) (cid:20)(cid:4)(cid:4)> (cid:20)(cid:4)(cid:29)(cid:4) (cid:20)(cid:4)(cid:29)0 6(cid:12)(cid:12)(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)"(cid:2)=(cid:7)"%(cid:11) ((cid:29) (cid:20)(cid:4)(cid:23)0 (cid:20)(cid:4)?(cid:4) (cid:20)(cid:4)(cid:5)(cid:4) 9(cid:10))(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)"(cid:2)=(cid:7)"%(cid:11) ( (cid:20)(cid:4)(cid:29)(cid:23) (cid:20)(cid:4)(cid:29)> (cid:20)(cid:4)(cid:3)(cid:3) :(cid:31)(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)(cid:26)(cid:10))(cid:2)(cid:22)(cid:12)(cid:28)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:2)* (cid:14)1 < < (cid:20)(cid:23),(cid:4) (cid:31)(cid:27)(cid:13)(cid:6)(cid:12) (cid:29)(cid:20) (cid:30)(cid:7)(cid:15)(cid:2)(cid:29)(cid:2)(cid:31)(cid:7) !(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)"(cid:14)#(cid:2)$(cid:14)(cid:28)%!(cid:9)(cid:14)(cid:2)&(cid:28)(cid:18)(cid:2)(cid:31)(cid:28)(cid:9)(cid:18)’(cid:2)(!%(cid:2)&! %(cid:2)((cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)%(cid:14)"(cid:2))(cid:7)%(cid:11)(cid:7)(cid:15)(cid:2)%(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)%(cid:8)(cid:11)(cid:14)"(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) *(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)$(cid:7)(cid:8)(cid:28)(cid:15)%(cid:2)+(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)%(cid:14)(cid:9)(cid:7) %(cid:7)(cid:8)(cid:20) ,(cid:20) (cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15) (cid:2)(cid:21)(cid:2)(cid:28)(cid:15)"(cid:2)-(cid:29)(cid:2)"(cid:10)(cid:2)(cid:15)(cid:10)%(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)!"(cid:14)(cid:2)&(cid:10)(cid:16)"(cid:2)$(cid:16)(cid:28) (cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)%(cid:9)! (cid:7)(cid:10)(cid:15) (cid:20)(cid:2)(cid:6)(cid:10)(cid:16)"(cid:2)$(cid:16)(cid:28) (cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)%(cid:9)! (cid:7)(cid:10)(cid:15) (cid:2) (cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)%(cid:2)(cid:14)#(cid:8)(cid:14)(cid:14)"(cid:2)(cid:20)(cid:4)(cid:29)(cid:4).(cid:2)(cid:12)(cid:14)(cid:9)(cid:2) (cid:7)"(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)"(cid:2)%(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6)-(cid:2)/(cid:29)(cid:23)(cid:20)0(cid:6)(cid:20) 1(cid:22)+2 1(cid:28) (cid:7)(cid:8)(cid:2)(cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)%(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)#(cid:28)(cid:8)%(cid:2)(cid:31)(cid:28)(cid:16)!(cid:14)(cid:2) (cid:11)(cid:10))(cid:15)(cid:2))(cid:7)%(cid:11)(cid:10)!%(cid:2)%(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14) (cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28))(cid:7)(cid:15)(cid:17)+(cid:4)(cid:23)(cid:27)(cid:4)(cid:29)(cid:5)1 © 2008 Microchip Technology Inc. DS21298E-page 31

MCP3204/3208 (cid:2),(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)!(cid:25)(cid:7)(cid:11)(cid:11)(cid:9)"(cid:17)(cid:13)(cid:11)(cid:14)(cid:19)(cid:6)(cid:9)(cid:20)!(cid:5)(cid:21)(cid:9)(cid:22)(cid:9)(cid:31)(cid:7)##(cid:27)$%(cid:9)(cid:23)&’(cid:24)(cid:9)(cid:25)(cid:25)(cid:9)(cid:26)(cid:27)(cid:8)(cid:28)(cid:9)(cid:29)!"(cid:18)((cid:30) (cid:31)(cid:27)(cid:13)(cid:6) 3(cid:10)(cid:9)(cid:2)%(cid:11)(cid:14)(cid:2)&(cid:10) %(cid:2)(cid:8)!(cid:9)(cid:9)(cid:14)(cid:15)%(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)"(cid:9)(cid:28))(cid:7)(cid:15)(cid:17) ’(cid:2)(cid:12)(cid:16)(cid:14)(cid:28) (cid:14)(cid:2) (cid:14)(cid:14)(cid:2)%(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:30)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)$(cid:7)(cid:8)(cid:28)%(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)%(cid:14)"(cid:2)(cid:28)%(cid:2) (cid:11)%%(cid:12)255)))(cid:20)&(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)&5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D N E E1 NOTE1 1 2 3 e b α h h c φ A A2 L β A1 L1 6(cid:15)(cid:7)% (cid:6)(cid:19)99(cid:19)(cid:6)-(cid:13)-(cid:26)(cid:22) (cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)&(cid:7)% (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7!&((cid:14)(cid:9)(cid:2)(cid:10)$(cid:2)(cid:30)(cid:7)(cid:15) 7 (cid:29)? (cid:30)(cid:7)%(cid:8)(cid:11) (cid:14) (cid:29)(cid:20)(cid:3)(cid:5)(cid:2)1(cid:22)+ :(cid:31)(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)% (cid:25) < < (cid:29)(cid:20)(cid:5)0 (cid:6)(cid:10)(cid:16)"(cid:14)"(cid:2)(cid:30)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14) (cid:25)(cid:3) (cid:29)(cid:20)(cid:3)0 < < (cid:22)%(cid:28)(cid:15)"(cid:10)$$(cid:2)(cid:2)* (cid:25)(cid:29) (cid:4)(cid:20)(cid:29)(cid:4) < (cid:4)(cid:20)(cid:3)0 :(cid:31)(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)=(cid:7)"%(cid:11) - ?(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22)+ (cid:6)(cid:10)(cid:16)"(cid:14)"(cid:2)(cid:30)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)=(cid:7)"%(cid:11) -(cid:29) ,(cid:20)(cid:24)(cid:4)(cid:2)1(cid:22)+ :(cid:31)(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)%(cid:11) (cid:21) (cid:24)(cid:20)(cid:24)(cid:4)(cid:2)1(cid:22)+ +(cid:11)(cid:28)&$(cid:14)(cid:9)(cid:2)@(cid:10)(cid:12)%(cid:7)(cid:10)(cid:15)(cid:28)(cid:16)A (cid:11) (cid:4)(cid:20)(cid:3)0 < (cid:4)(cid:20)0(cid:4) 3(cid:10)(cid:10)%(cid:2)9(cid:14)(cid:15)(cid:17)%(cid:11) 9 (cid:4)(cid:20)(cid:23)(cid:4) < (cid:29)(cid:20)(cid:3)(cid:5) 3(cid:10)(cid:10)%(cid:12)(cid:9)(cid:7)(cid:15)% 9(cid:29) (cid:29)(cid:20)(cid:4)(cid:23)(cid:2)(cid:26)-3 3(cid:10)(cid:10)%(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)B < >B 9(cid:14)(cid:28)"(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14) (cid:8) (cid:4)(cid:20)(cid:29)(cid:5) < (cid:4)(cid:20)(cid:3)0 9(cid:14)(cid:28)"(cid:2)=(cid:7)"%(cid:11) ( (cid:4)(cid:20),(cid:29) < (cid:4)(cid:20)0(cid:29) (cid:6)(cid:10)(cid:16)"(cid:2)(cid:21)(cid:9)(cid:28)$%(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14)(cid:2)(cid:13)(cid:10)(cid:12) (cid:4) 0B < (cid:29)0B (cid:6)(cid:10)(cid:16)"(cid:2)(cid:21)(cid:9)(cid:28)$%(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14)(cid:2)1(cid:10)%%(cid:10)& (cid:5) 0B < (cid:29)0B (cid:31)(cid:27)(cid:13)(cid:6)(cid:12) (cid:29)(cid:20) (cid:30)(cid:7)(cid:15)(cid:2)(cid:29)(cid:2)(cid:31)(cid:7) !(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)"(cid:14)#(cid:2)$(cid:14)(cid:28)%!(cid:9)(cid:14)(cid:2)&(cid:28)(cid:18)(cid:2)(cid:31)(cid:28)(cid:9)(cid:18)’(cid:2)(!%(cid:2)&! %(cid:2)((cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)%(cid:14)"(cid:2))(cid:7)%(cid:11)(cid:7)(cid:15)(cid:2)%(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)%(cid:8)(cid:11)(cid:14)"(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) *(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)$(cid:7)(cid:8)(cid:28)(cid:15)%(cid:2)+(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)%(cid:14)(cid:9)(cid:7) %(cid:7)(cid:8)(cid:20) ,(cid:20) (cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15) (cid:2)(cid:21)(cid:2)(cid:28)(cid:15)"(cid:2)-(cid:29)(cid:2)"(cid:10)(cid:2)(cid:15)(cid:10)%(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)!"(cid:14)(cid:2)&(cid:10)(cid:16)"(cid:2)$(cid:16)(cid:28) (cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)%(cid:9)! (cid:7)(cid:10)(cid:15) (cid:20)(cid:2)(cid:6)(cid:10)(cid:16)"(cid:2)$(cid:16)(cid:28) (cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)%(cid:9)! (cid:7)(cid:10)(cid:15) (cid:2) (cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)%(cid:2)(cid:14)#(cid:8)(cid:14)(cid:14)"(cid:2)(cid:4)(cid:20)(cid:29)0(cid:2)&&(cid:2)(cid:12)(cid:14)(cid:9)(cid:2) (cid:7)"(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)"(cid:2)%(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6)-(cid:2)/(cid:29)(cid:23)(cid:20)0(cid:6)(cid:20) 1(cid:22)+2 1(cid:28) (cid:7)(cid:8)(cid:2)(cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)%(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)#(cid:28)(cid:8)%(cid:2)(cid:31)(cid:28)(cid:16)!(cid:14)(cid:2) (cid:11)(cid:10))(cid:15)(cid:2))(cid:7)%(cid:11)(cid:10)!%(cid:2)%(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14) (cid:20) (cid:26)-32 (cid:26)(cid:14)$(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)’(cid:2)! !(cid:28)(cid:16)(cid:16)(cid:18)(cid:2))(cid:7)%(cid:11)(cid:10)!%(cid:2)%(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)’(cid:2)$(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)$(cid:10)(cid:9)&(cid:28)%(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)!(cid:9)(cid:12)(cid:10) (cid:14) (cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28))(cid:7)(cid:15)(cid:17)+(cid:4)(cid:23)(cid:27)(cid:29)(cid:4)>1 DS21298E-page 32 © 2008 Microchip Technology Inc.

MCP3204/3208 (cid:31)(cid:27)(cid:13)(cid:6) 3(cid:10)(cid:9)(cid:2)%(cid:11)(cid:14)(cid:2)&(cid:10) %(cid:2)(cid:8)!(cid:9)(cid:9)(cid:14)(cid:15)%(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)"(cid:9)(cid:28))(cid:7)(cid:15)(cid:17) ’(cid:2)(cid:12)(cid:16)(cid:14)(cid:28) (cid:14)(cid:2) (cid:14)(cid:14)(cid:2)%(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:30)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)$(cid:7)(cid:8)(cid:28)%(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)%(cid:14)"(cid:2)(cid:28)%(cid:2) (cid:11)%%(cid:12)255)))(cid:20)&(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)&5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) © 2008 Microchip Technology Inc. DS21298E-page 33

MCP3204/3208 NOTES: DS21298E-page 34 © 2008 Microchip Technology Inc.

MCP3204/3208 APPENDIX A: REVISION HISTORY Revision E (September 2008) The following is the list of modifications: 1. Updated package outline drawings in Section7.0 “Packaging Information”. Revision D (January 2007) The following is the list of modifications: 1. Undocumented changes Revision C (May 2002) The following is the list of modifications: 1. Undocumented changes Revision B (August 1999) The following is the list of modifications: 1. Undocumented changes Revision A (November 1998) • Initial release of this document. © 2008 Microchip Technology Inc. DS21298E-page 35

MCP3204/3208 NOTES: DS21298E-page 36 © 2008 Microchip Technology Inc.

MCP3204/3208 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. –X X /XX Examples: Device Grade Temperature Package a) MCP3204-BI/P: ±1LSB INL, Range Industrial Temperature, PDIP package. b) MCP3204-BI/SL: ±1LSB INL, Device MCP3204: 4-Channel 12-Bit Serial A/D Converter Industrial Temperature, MCP3204T: 4-Channel 12-Bit Serial A/D Converter (Tape and Reel) SOIC package. MCP3208: 8-Channel 12-Bit Serial A/D Converter c) MCP3204-CI/ST: ±2LSB INL, MCP3208T: 8-Channel 12-Bit Serial A/D Converter Industrial Temperature, (Tape and Reel) TSSOP package. Grade: B = ±1LSB INL a) MCP3208-BI/P: ±1LSB INL, C = ±2LSB INL Industrial Temperature, PDIP package. Temperature Range I = -40°C to +85°C (Industrial) b) MCP3208-BI/SL: ±1LSB INL, Industrial Temperature, SOIC package. Package P = Plastic DIP (300 mil Body), 14-lead, 16-lead c) MCP3208-CI/ST: ±2LSB INL, SL = Plastic SOIC (150 mil Body), 14-lead, 16-lead ST = Plastic TSSOP (4.4mm), 14-lead Industrial Temperature, TSSOP package. © 2008 Microchip Technology Inc. DS21298E-page 37

MCP3204/3208 NOTES: DS21298E-page 38 © 2008 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, Accuron, and may be superseded by updates. It is your responsibility to dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, ensure that your application meets with your specifications. PICSTART, rfPIC, SmartShunt and UNI/O are registered MICROCHIP MAKES NO REPRESENTATIONS OR trademarks of Microchip Technology Incorporated in the WARRANTIES OF ANY KIND WHETHER EXPRESS OR U.S.A. and other countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Linear Active Thermistor, MXDEV, MXLAB, INCLUDING BUT NOT LIMITED TO ITS CONDITION, SEEVAL, SmartSensor and The Embedded Control Solutions QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, CodeGuard, devices in life support and/or safety applications is entirely at dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, the buyer’s risk, and the buyer agrees to defend, indemnify and ECONOMONITOR, FanSense, In-Circuit Serial hold harmless Microchip from any and all damages, claims, Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB suits, or expenses resulting from such use. No licenses are Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, conveyed, implicitly or otherwise, under any Microchip PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, intellectual property rights. PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2008, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2008 Microchip Technology Inc. DS21298E-page 39

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