M MCP3004/3008 2.7V 4-Channel/8-Channel 10-Bit A/D Converters with SPI™ Serial Interface Features Description • 10-bit resolution The Microchip Technology Inc. MCP3004/3008 • ± 1LSB max DNL devices are successive approximation 10-bit Analog- to-Digital (A/D) converters with on-board sample and • ± 1LSB max INL hold circuitry. The MCP3004 is programmable to pro- • 4 (MCP3004) or 8 (MCP3008) input channels vide two pseudo-differential input pairs or four single- • Analog inputs programmable as single-ended or ended inputs. The MCP3008 is programmable to pro- pseudo-differential pairs vide four pseudo-differential input pairs or eight single- • On-chip sample and hold ended inputs. Differential Nonlinearity (DNL) and Inte- • SPI serial interface (modes 0,0 and 1,1) gral Nonlinearity (INL) are specified at ±1LSB. Com- • Single supply operation: 2.7V - 5.5V munication with the devices is accomplished using a simple serial interface compatible with the SPI protocol. • 200ksps max. sampling rate at V = 5V DD The devices are capable of conversion rates of up to • 75ksps max. sampling rate at V = 2.7V DD 200ksps. The MCP3004/3008 devices operate over a • Low power CMOS technology broad voltage range (2.7V - 5.5V). Low current design • 5nA typical standby current, 2µA max. permits operation with typical standby currents of only • 500µA max. active current at 5V 5nA and typical active currents of 320µA. The MCP3004 is offered in 14-pin PDIP, 150mil SOIC and • Industrial temp range: -40°C to +85°C TSSOP packages, while the MCP3008 is offered in 16- • Available in PDIP, SOIC and TSSOP packages pin PDIP and SOIC packages. Applications Functional Block Diagram • Sensor Interface • Process Control VDD VSS • Data Acquisition VREF • Battery Operated Systems CH0 CH1 Input Package Types Channel DAC Max PDIP, SOIC, TSSOP CH7* Comparator CH0 1 14 VDD Sample 10-Bit SAR CH1 2 M 13 VREF and CH2 3 C 12 AGND Hold CH3 4 P 11 CLK 3 Shift NC 5 0 10 D Control Logic 0 OUT Register NC 6 4 9 DIN DGND 7 8 CS/SHDN CS/SHDN DIN CLK DOUT * Note: Channels 4-7 available on MCP3008 Only PDIP, SOIC CH0 1 16 V DD CH1 2 15 VREF CH2 3 M 14 AGND CH3 4 C 13 CLK P CH4 5 3 12 D 0 OUT CH5 6 0 11 D 8 IN CH6 7 10 CS/SHDN CH7 8 9 DGND  2002 Microchip Technology Inc. DS21295B-page 1

MCP3004/3008 1.0 ELECTRICAL PIN FUNCTION TABLE CHARACTERISTICS Name Function Absolute Maximum Ratings* V +2.7V to 5.5V Power Supply DD V ........................................................................7.0V DGND Digital Ground DD All inputs and outputs w.r.t. V .....-0.6V to V +0.6V AGND Analog Ground SS DD Storage temperature..........................-65°C to +150°C CH0-CH7 Analog Inputs Ambient temp. with power applied.....-65°C to +125°C CLK Serial Clock Soldering temperature of leads (10 seconds)..+300°C DIN Serial Data In ESD protection on all pins..................................> 4kV DOUT Serial Data Out *Notice: Stresses above those listed under "Maximum CS/SHDN Chip Select/Shutdown Input Ratings" may cause permanent damage to the device. This is V Reference Voltage Input REF a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise noted, all parameters apply at V = 5V, V = 5V, DD REF T = -40°C to +85°C, f = 200ksps and f = 18*f . Unless otherwise noted, typical values apply for AMB SAMPLE CLK SAMPLE V = 5V, T = 25°C. DD AMB Parameter Sym Min Typ Max Units Conditions Conversion Rate Conversion Time t — — 10 clock CONV cycles Analog Input Sample Time t 1.5 clock SAMPLE cycles Throughput Rate f — — 200 ksps V = V = 5V SAMPLE DD REF 75 ksps V = V = 2.7V DD REF DC Accuracy Resolution 10 bits Integral Nonlinearity INL — ±0.5 ±1 LSB Differential Nonlinearity DNL — ±0.25 ±1 LSB No missing codes over temperature Offset Error — — ±1.5 LSB Gain Error — — ±1.0 LSB Dynamic Performance Total Harmonic Distortion — -76 dB V = 0.1V to 4.9V@1kHz IN Signal to Noise and Distortion — 61 dB V = 0.1V to 4.9V@1kHz IN (SINAD) Spurious Free Dynamic Range — 78 dB V = 0.1V to 4.9V@1kHz IN Reference Input Voltage Range 0.25 — V V Note2 DD Current Drain — 100 150 µA 0.001 3 µA CS = V = 5V DD Note 1: This parameter is established by characterization and not 100% tested. 2: See graphs that relate linearity performance to V levels. REF 3: Because the sample cap will eventually lose charge, effective clock rates below 10kHz can affect linearity performance, especially at elevated temperatures. See Section6.2, “Maintaining Minimum Clock Speed”, for more information. DS21295B-page 2  2002 Microchip Technology Inc.

MCP3004/3008 ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise noted, all parameters apply at V = 5V, V = 5V, DD REF T = -40°C to +85°C, f = 200ksps and f = 18*f . Unless otherwise noted, typical values apply for AMB SAMPLE CLK SAMPLE V = 5V, T = 25°C. DD AMB Parameter Sym Min Typ Max Units Conditions Analog Inputs Input Voltage Range for CH0 or V — V V SS REF CH1 in Single-Ended Mode Input Voltage Range for IN+ in IN- — V +IN- REF pseudo-differential mode Input Voltage Range for IN- in V -100 — V +100 mV SS SS pseudo-differential mode Leakage Current — 0.001 ±1 µA Switch Resistance — 1000 — Ω See Figure4-1 Sample Capacitor — 20 — pF See Figure4-1 Digital Input/Output Data Coding Format Straight Binary High Level Input Voltage V 0.7 V — — V IH DD Low Level Input Voltage V — 0.3 V V IL DD High Level Output Voltage V 4.1 — — V I = -1mA, V = 4.5V OH OH DD Low Level Output Voltage V — — 0.4 V I = 1mA, V = 4.5V OL OL DD Input Leakage Current I -10 — 10 µA V = V or V LI IN SS DD Output Leakage Current I -10 — 10 µA V = V or V LO OUT SS DD Pin Capacitance C , — — 10 pF V = 5.0V (Note1) IN DD (All Inputs/Outputs) C T = 25°C, f = 1MHz OUT AMB Timing Parameters Clock Frequency f — — 3.6 MHz V = 5V (Note3) CLK DD 1.35 MHz VDD = 2.7V (Note3) Clock High Time t 125 — — ns HI Clock Low Time t 125 — — ns LO CS Fall To First Rising CLK Edge t 100 — — ns SUCS CS Fall To Falling CLK Edge t — — 0 ns CSD Data Input Setup Time t — — 50 ns SU Data Input Hold Time t — — 50 ns HD CLK Fall To Output Data Valid t — — 125 ns V = 5V, See Figure1-2 DO DD 200 ns V = 2.7V, See Figure1-2 DD CLK Fall To Output Enable t — — 125 ns V = 5V, See Figure1-2 EN DD 200 ns V = 2.7V, See Figure1-2 DD CS Rise To Output Disable t — — 100 ns See Test Circuits, Figure1-2 DIS CS Disable Time t 270 — — ns CSH D Rise Time t — — 100 ns See Test Circuits, Figure1-2 OUT R (Note1) D Fall Time t — — 100 ns See Test Circuits, Figure1-2 OUT F (Note1) Note 1: This parameter is established by characterization and not 100% tested. 2: See graphs that relate linearity performance to V levels. REF 3: Because the sample cap will eventually lose charge, effective clock rates below 10kHz can affect linearity performance, especially at elevated temperatures. See Section6.2, “Maintaining Minimum Clock Speed”, for more information.  2002 Microchip Technology Inc. DS21295B-page 3

MCP3004/3008 ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise noted, all parameters apply at V = 5V, V = 5V, DD REF T = -40°C to +85°C, f = 200ksps and f = 18*f . Unless otherwise noted, typical values apply for AMB SAMPLE CLK SAMPLE V = 5V, T = 25°C. DD AMB Parameter Sym Min Typ Max Units Conditions Power Requirements Operating Voltage V 2.7 — 5.5 V DD Operating Current I — 425 550 µA V = V = 5V, DD DD REF 225 D unloaded OUT V = V = 2.7V, DD REF D unloaded OUT Standby Current I — 0.005 2 µA CS = V = 5.0V DDS DD Temperature Ranges Specified Temperature Range T -40 — +85 °C A Operating Temperature Range T -40 — +85 °C A Storage Temperature Range T -65 — +150 °C A Thermal Package Resistance Thermal Resistance, 14L-PDIP θ — 70 — °C/W JA Thermal Resistance, 14L-SOIC θ — 108 — °C/W JA Thermal Resistance, 14L-TSSOP θ — 100 — °C/W JA Thermal Resistance, 16L-PDIP θ — 70 — °C/W JA Thermal Resistance, 16L-SOIC θ — 90 — °C/W JA Note 1: This parameter is established by characterization and not 100% tested. 2: See graphs that relate linearity performance to V levels. REF 3: Because the sample cap will eventually lose charge, effective clock rates below 10kHz can affect linearity performance, especially at elevated temperatures. See Section6.2, “Maintaining Minimum Clock Speed”, for more information. T CSH CS T SUCS T T HI LO CLK TSU THD DIN MSB IN TDO TR TF TDIS T EN DOUT NULL BIT MSB OUT LSB FIGURE 1-1: Serial Interface Timing. DS21295B-page 4  2002 Microchip Technology Inc.

MCP3004/3008 1.4V Test Point V DD 3kΩ tDIS Waveform 2 Test Point 3kΩ VDD/2 DOUT DOUT tEN Waveform CL = 100pF 100pF tDIS Waveform 1 V SS Voltage Waveforms for t , t R F Voltage Waveforms for t EN V OH V D OL OUT CS tR tF 1 2 3 4 CLK Voltage Waveforms for t DO D B9 OUT CLK t EN t DO Voltage Waveforms for t DIS D OUT V CS IH FIGURE 1-2: Load Circuit for t , t , t . D R F DO OUT 90% Waveform 1* T DIS D 10% OUT Waveform 2† * Waveform 1 is for an output with internal conditions such that the output is high, unless disabled by the output control. † Waveform 2 is for an output with internal conditions such that the output is low, unless disabled by the output control. FIGURE 1-3: Load circuit for t and t . DIS EN  2002 Microchip Technology Inc. DS21295B-page 5

MCP3004/3008 2.0 TYPICAL PERFORMANCE CHARACTERISTICS Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, V = V = 5V, f = 18* f , T = 25°C. DD REF CLK SAMPLE A 1.0 1.0 0.8 0.8 VDD = VREF = 2.7 V 0.6 0.6 INL (LSB) --00000.....02442 PNoegsiattivivee I NINLL INL (LSB) --00000.....02442 PNoegsiattivivee I NINLL -0.6 -0.6 -0.8 -0.8 -1.0 -1.0 0 25 50 75 100 125 150 175 200 225 250 0 25 50 75 100 Sample Rate (ksps) Sample Rate (ksps) FIGURE 2-1: Integral Nonlinearity (INL) vs. FIGURE 2-4: Integral Nonlinearity (INL) vs. Sample Rate. Sample Rate (V = 2.7V). DD 1.0 1.0 0.8 VDD = VREF = 2.7 V 0.8 0.6 fSAMPLE = 75 ksps 0.6 B) 00..24 Positive INL SB) 00..24 Positive INL S L 0.0 INL(L --000...042 Negative INL INL( --00..42 Negative INL -0.6 -0.6 -0.8 -0.8 -1.0 -1.0 0 1 2 3 4 5 6 0.0 0.5 1.0 1.5 2.0 2.5 3.0 VREF (V) VREF (V) FIGURE 2-2: Integral Nonlinearity (INL) vs. FIGURE 2-5: Integral Nonlinearity (INL) vs. V . V (V = 2.7V). REF REF DD 0.5 0.5 00..34 VfSDADM P=L EV =RE 2F 0=0 5 k Vsps 00..34 VfSDADM P=L EV =RE 7F 5= k 2s.7p sV 0.2 0.2 SB) 0.1 SB) 0.1 NL (L-00..01 NL (L-00..01 I-0.2 I-0.2 -0.3 -0.3 -0.4 -0.4 -0.5 -0.5 0 128 256 384 512 640 768 896 1024 0 128 256 384 512 640 768 896 1024 Digital Code Digital Code FIGURE 2-3: Integral Nonlinearity (INL) vs. FIGURE 2-6: Integral Nonlinearity (INL) vs. Code (Representative Part). Code (Representative Part, V = 2.7V). DD DS21295B-page 6  2002 Microchip Technology Inc.

MCP3004/3008 Note: Unless otherwise indicated, V = V = 5V, f = 18* f , T = 25°C. DD REF CLK SAMPLE A 0.6 0.6 VDD = VREF = 2.7 V 0.4 0.4 fSAMPLE = 75 ksps Positive INL Positive INL 0.2 INL (LSB)-000...022 INL (LSB)-00..02 Negative INL Negative INL -0.4 -0.4 -0.6 -0.6 -50 -25 0 25 50 75 100 -50 -25 0 25 50 75 100 Temperature (°C) Temperature (°C) FIGURE 2-7: Integral Nonlinearity (INL) vs. FIGURE 2-10: Integral Nonlinearity (INL) vs. Temperature. Temperature (V = 2.7V). DD 0.6 0.6 VDD = VREF = 2.7 V 0.4 0.4 NL (LSB) 00..02 Positive DNL NL (LSB) 00..02 Positive DNL D -0.2 Negative DNL D -0.2 Negative DNL -0.4 -0.4 -0.6 -0.6 0 25 50 75 100 125 150 175 200 225 250 0 25 50 75 100 Sample Rate (ksps) Sample Rate (ksps) FIGURE 2-8: Differential Nonlinearity (DNL) FIGURE 2-11: Differential Nonlinearity (DNL) vs. Sample Rate. vs. Sample Rate (V = 2.7V). DD 1.0 0.8 0.8 0.6 VDD = VREF = 2.7 V 0.6 0.4 fSAMPLE = 75 ksps SB) 00..24 Positive DNL B) 0.2 Positive DNL DNL (L -00..02 Negative DNL NL (LS-00..02 Negative DNL -0.4 D-0.4 -0.6 -0.6 -0.8 -0.8 -1.0 -1.0 0 1 2 3 4 5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 V (V) V (V) REF REF FIGURE 2-9: Differential Nonlinearity (DNL) FIGURE 2-12: Differential Nonlinearity (DNL) vs. V . vs. V (V = 2.7V). REF REF DD  2002 Microchip Technology Inc. DS21295B-page 7

MCP3004/3008 Note: Unless otherwise indicated, V = V = 5V, f = 18* f , T = 25°C. DD REF CLK SAMPLE A 1.0 1.0 0.8 VDD = VREF = 5 V 0.8 VDD = VREF = 2.7 V fSAMPLE = 200 ksps fSAMPLE = 75 ksps 0.6 0.6 0.4 0.4 SB) 0.2 SB) 0.2 L (L 0.0 L (L 0.0 N-0.2 N-0.2 D D -0.4 -0.4 -0.6 -0.6 -0.8 -0.8 -1.0 -1.0 0 128 256 384 512 640 768 896 1024 0 128 256 384 512 640 768 896 1024 Digital Code Digital Code FIGURE 2-13: Differential Nonlinearity (DNL) FIGURE 2-16: Differential Nonlinearity (DNL) vs. Code (Representative Part). vs. Code (Representative Part, V = 2.7V). DD 0.6 0.6 VDD = VREF = 2.7 V 0.4 0.4 fSAMPLE = 75 ksps Positive DNL B) 0.2 SB) 0.2 Positive DNL DNL (LS-00..02 DNL (L-00..02 Negative DNL Negative DNL -0.4 -0.4 -0.6 -0.6 -50 -25 0 25 50 75 100 -50 -25 0 25 50 75 100 Temperature (°C) Temperature (°C) FIGURE 2-14: Differential Nonlinearity (DNL) FIGURE 2-17: Differential Nonlinearity (DNL) vs. Temperature. vs. Temperature (V = 2.7V). DD 2.0 8 1.5 7 VDD = 2.7 V Error (LSB) 001...050 fSAMPLE = 75 ksps Error (LSB) 456 VfSDADM P=L E5 =V 200 ksps Gain --10..05 VfSDADM P=L E5 =V 200 ksps Offset 23 VfSDADM P=L E2 .=7 7V5 ksps -1.5 1 -2.0 0 0 1 2 3 4 5 0 1 2 3 4 5 V (V) V (V) REF REF FIGURE 2-15: Gain Error vs. V . FIGURE 2-18: Offset Error vs. V . REF REF DS21295B-page 8  2002 Microchip Technology Inc.

MCP3004/3008 Note: Unless otherwise indicated, V = V = 5V, f = 18* f , T = 25°C. DD REF CLK SAMPLE A 0.0 1.2 Gain Error (LSB)----0000....4321 VVfDSDDAD M= P= LV EVR =REFE 7F = 5= 5k 2 sV.p7 sV Offset Error (LSB)0001....4680 VfSDADM P=L EV =RVfE S2FDA 0D=M0 P =5 Lk EVVs =RpE s7F 5= k 2s.p7 sV -0.5 fSAMPLE = 200 ksps 0.2 -0.6 0.0 -50 -25 0 25 50 75 100 -50 -25 0 25 50 75 100 Temperature (°C) Temperature (°C) FIGURE 2-19: Gain Error vs. Temperature. FIGURE 2-22: Offset Error vs. Temperature. 80 80 70 VfSDADM P=L EV =RE 2F 0=0 5 k Vsps 70 VfSDADM P=L EV =RE 2F 0=0 5 k Vsps 60 60 B)50 B)50 d d SNR (3400 VfSDADM P=L EV =RE 7F 5= k 2s.7p sV SINAD (3400 VfSDADM P=L EV =RE 7F 5= k 2s.7p sV 20 20 10 10 0 0 1 10 100 1 10 100 Input Frequency (kHz) Input Frequency (kHz) FIGURE 2-20: Signal to Noise (SNR) vs. Input FIGURE 2-23: Signal to Noise and Distortion Frequency. (SINAD) vs. Input Frequency. 0 70 -10 60 -20 D (dB) ---543000 VfSDADM P=L EV =RE 7F 5= k 2s.7p sV D (dB) 4500 VfSDADM P=L EV =RE 2F 0=0 5 k Vsps TH -60 NA 30 -70 SI 20 VDD = VREF = 2.7 V -80 VDD = VREF = 5 V fSAMPLE = 75 ksps -90 fSAMPLE = 200 ksps 10 -100 0 1 10 100 -40 -35 -30 -25 -20 -15 -10 -5 0 Input Frequency (kHz) Input Signal Level (dB) FIGURE 2-21: Total Harmonic Distortion (THD) FIGURE 2-24: Signal to Noise and Distortion vs. Input Frequency. (SINAD) vs. Input Signal Level.  2002 Microchip Technology Inc. DS21295B-page 9

MCP3004/3008 Note: Unless otherwise indicated, V = V = 5V, f = 18* f , T = 25°C. DD REF CLK SAMPLE A 10.00 10.0 9.8 VDD = VREF = 5 V 9.75 9.6 fSAMPLE = 200 ksps B (rms) 9.50 VfSDADM P=L EV =RE 7F 5= k 2s.7p sV B (rms)999...024 O O N N8.8 E E8.6 9.25 VfSDADM P=L EV R=E 2F 0=0 5 k Vsps 88..24 VfSDADM P=L EV =RE 7F 5= k 2s.p7 sV 9.00 8.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 1 10 100 VREF (V) Input Frequency (kHz) FIGURE 2-25: Effective Number of Bits (ENOB) FIGURE 2-28: Effective Number of Bits (ENOB) vs. V . vs. Input Frequency. REF 1089000 VfSDADM P=L EV =RE 2F 0=0 5k sVps n (dB) -100 VfSDADM P=L EV =RE 2F 0=0 5 k Vsps o dB)6700 ejecti --3200 SFDR (345000 VfSDADM P=L EV =RE 7F 5= k 2s.7p sV Supply R --5400 20 wer -60 10 o P -70 0 1 10 100 1000 10000 1 10 100 Input Frequency (kHz) Ripple Frequency (kHz) FIGURE 2-26: Spurious Free Dynamic Range FIGURE 2-29: Power Supply Rejection (PSR) (SFDR) vs. Input Frequency. vs. Ripple Frequency. 0 0 -10 VDD = VREF = 5 V -10 VDD = VREF = 2.7 V -20 FSAMPLE = 200 ksps -20 fSAMPLE = 75 ksps -30 FINPUT = 10.0097 kHz -30 fINPUT = 1.00708 kHz B) -40 4096 points B)-40 4096 points de (d --6500 de (d--6500 mplitu --8700 mplitu--8700 A -90 A-90 -100 -100 -110 -110 -120 -120 -130 -130 0 20000 40000 60000 80000 100000 0 5000 10000 15000 20000 25000 30000 35000 Frequency (Hz) Frequency (Hz) FIGURE 2-27: Frequency Spectrum of 10kHz FIGURE 2-30: Frequency Spectrum of 1kHz Input (Representative Part). Input (Representative Part, V = 2.7V). DD DS21295B-page 10  2002 Microchip Technology Inc.

MCP3004/3008 Note: Unless otherwise indicated, V = V = 5V, f = 18* f , T = 25°C. DD REF CLK SAMPLE A 550 550 500 500 450 450 400 400 350 350 µA) 300 µA) 300 I (DD 220500 I (DD 220500 150 VREF = VDD 150 VREF = VDD 100 All points at fCLK = 3.6 MHz except 100 All points at fCLK = 3.6 MHz except 50 at VREF = VDD = 2.5 V, fCLK = 1.35 MHz 50 at VREF = VDD = 2.5 V, fCLK = 1.35 MHz 0 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) VDD (V) FIGURE 2-31: I vs. V . FIGURE 2-34: I vs. V . DD DD REF DD 500 120 450 110 100 400 90 VDD = VREF = 5 V 350 80 (µA)DD 223050000 VDD = VREF = 5 V (µA)REF 567000 I 150 VDD = VREF = 2.7 V I 40 VDD = VREF = 2.7 V 30 100 20 50 10 0 0 10 100 1000 10000 10 100 1000 10000 Clock Frequency (kHz) Clock Frequency (kHz) FIGURE 2-32: I vs. Clock Frequency. FIGURE 2-35: I vs. Clock Frequency. DD REF 550 500 VDD = VREF = 5 V 140 440500 fCLK = 3.6 MHz 120 VfCDLDK == V3R.6E FM =H 5z V 350 100 I (µA)DD223050000 (µA)REF 6800 I 11055000 VfCDLDK == V1R.3E5F =M H2.z7 V 2400 VfCDLDK == V1R.3E5F M= H2.z7 V 0 0 -50 -25 0 25 50 75 100 -50 -25 0 25 50 75 100 Temperature (°C) Temperature (°C) FIGURE 2-33: I vs. Temperature. FIGURE 2-36: I vs. Temperature. DD REF  2002 Microchip Technology Inc. DS21295B-page 11

MCP3004/3008 Note: Unless otherwise indicated, V = V = 5V, f = 18* f , T = 25°C. DD REF CLK SAMPLE A 70 2.0 60 VREF = CS = VDD nA)1.8 VDD = VREF = 5 V e (1.6 50 g1.4 a I (pA)DDS3400 nput Leak011...802 20 g I0.6 10 nalo0.4 A0.2 0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 -50 -25 0 25 50 75 100 VDD (V) Temperature (°C) FIGURE 2-37: I vs. V . FIGURE 2-39: Analog Input Leakage Current DDS DD vs. Temperature. 100.00 VDD = VREF = CS = 5 V 10.00 A) n (S 1.00 D D I 0.10 0.01 -50 -25 0 25 50 75 100 Temperature (°C) FIGURE 2-38: I vs. Temperature. DDS DS21295B-page 12  2002 Microchip Technology Inc.

MCP3004/3008 3.0 PIN DESCRIPTIONS 4.0 DEVICE OPERATION The MCP3004/3008 A/D converters employ a conven- TABLE 3-1: PIN FUNCTION TABLE tional SAR architecture. With this architecture, a sam- Name Function ple is acquired on an internal sample/hold capacitor for 1.5 clock cycles starting on the first rising edge of the V +2.7V to 5.5V Power Supply DD serial clock once CS has been pulled low. Following DGND Digital Ground this sample time, the device uses the collected charge AGND Analog Ground on the internal sample and hold capacitor to produce a serial 10-bit digital output code. Conversion rates of CH0-CH7 Analog Inputs 100ksps are possible on the MCP3004/3008. See CLK Serial Clock Section6.2, “Maintaining Minimum Clock Speed”, for DIN Serial Data In information on minimum clock rates. Communication D Serial Data Out with the device is accomplished using a 4-wire SPI- OUT compatible interface. CS/SHDN Chip Select/Shutdown Input VREF Reference Voltage Input 4.1 Analog Inputs 3.1 DGND The MCP3004/3008 devices offer the choice of using the analog input channels configured as single-ended Digital ground connection to internal digital circuitry. inputs or pseudo-differential pairs. The MCP3004 can be configured to provide two pseudo-differential input 3.2 AGND pairs or four single-ended inputs. The MCP3008 can be Analog ground connection to internal analog circuitry. configured to provide four pseudo-differential input pairs or eight single-ended inputs. Configuration is 3.3 CH0 - CH7 done as part of the serial command before each con- version begins. When used in the pseudo-differential Analog inputs for channels 0 - 7, respectively, for the mode, each channel pair (i.e., CH0 and CH1, CH2 and multiplexed inputs. Each pair of channels can be pro- CH3 etc.) are programmed as the IN+ and IN- inputs as grammed to be used as two independent channels in part of the command string transmitted to the device. single-ended mode or as a single pseudo-differential The IN+ input can range from IN- to (V + IN-). The REF input where one channel is IN+ and one channel is IN. IN- input is limited to ±100mV from the V rail. The IN- SS See Section4.1, “Analog Inputs”, and Section5.0, input can be used to cancel small signal common- “Serial Communication”, for information on mode noise, which is present on both the IN+ and IN- programming the channel configuration. inputs. 3.4 Serial Clock (CLK) When operating in the pseudo-differential mode, if the voltage level of IN+ is equal to or less than IN-, the The SPI clock pin is used to initiate a conversion and resultant code will be 000h. If the voltage at IN+ is clock out each bit of the conversion as it takes place. equal to or greater than {[V + (IN-)] - 1 LSB}, then REF See Section6.2, “Maintaining Minimum Clock Speed”, the output code will be 3FFh. If the voltage level at IN- for constraints on clock speed. is more than 1LSB below V , the voltage level at the SS IN+ input will have to go below V to see the 000h SS 3.5 Serial Data Input (DIN) output code. Conversely, if IN- is more than 1LSB above V , the 3FFh code will not be seen unless the The SPI port serial data input pin is used to load SS IN+ input level goes above V level. channel configuration data into the device. REF For the A/D converter to meet specification, the charge 3.6 Serial Data Output (D ) holding capacitor (C ) must be given enough OUT SAMPLE time to acquire a 10-bit accurate voltage level during The SPI serial data output pin is used to shift out the the 1.5 clock cycle sampling period. The analog input results of the A/D conversion. Data will always change model is shown in Figure4-1. on the falling edge of each clock as the conversion This diagram illustrates that the source impedance (R ) takes place. S adds to the internal sampling switch (R ) impedance, SS 3.7 Chip Select/Shutdown (CS/SHDN) directly affecting the time that is required to charge the capacitor (C ). Consequently, larger source SAMPLE The CS/SHDN pin is used to initiate communication impedances increase the offset, gain and integral lin- with the device when pulled low. When pulled high, it earity errors of the conversion (see Figure4-2). will end a conversion and put the device in low power standby. The CS/SHDN pin must be pulled high between conversions.  2002 Microchip Technology Inc. DS21295B-page 13

MCP3004/3008 4.2 Reference Input EQUATION For each device in the family, the reference input 1024×V Digital Output Code = -----------------------I-N--- (VREF) determines the analog input voltage range. As V REF the reference input is reduced, the LSB size is reduced accordingly. V = analog input voltage IN V = reference voltage EQUATION REF V LSB Size = ----R---E----F-- When using an external voltage reference device, the 1024 system designer should always refer to the manufac- turer’s recommendations for circuit layout. Any instabil- The theoretical digital output code produced by the A/D ity in the operation of the reference device will have a converter is a function of the analog input signal and the direct effect on the operation of the A/D converter. reference input, as shown below. V DD Sampling Switch V = 0.6V RSS CHx T SS RS = 1kΩ C C I SAMPLE VA PIN V = 0.6V LEAKAGE = DAC capacitance 7pF T ±1nA = 20pF V SS Legend VA = Signal Source ILEAKAGE = Leakage Current At The Pin Due To Various Junctions RSS = Source Impedance SS = sampling switch CHx = Input Channel Pad RS = sampling switch resistor CPIN = Input Pin Capacitance CSAMPLE = sample/hold capacitance VT = Threshold Voltage FIGURE 4-1: Analog Input Model. 4 VDD = VREF = 5 V hz) fSAMPLE = 200 ksps M3 y ( c n e u2 q e Fr ock 1 VDD = VREF = 2.7 V Cl fSAMPLE = 75 ksps 0 100 1000 10000 Input Resistance (Ohms) FIGURE 4-2: Maximum Clock Frequency vs. Input resistance (R ) to maintain less than a S 0.1LSB deviation in INL from nominal conditions. DS21295B-page 14  2002 Microchip Technology Inc.

MCP3004/3008 5.0 SERIAL COMMUNICATION TABLE 5-1: CONFIGURE BITS FOR THE MCP3004 Communication with the MCP3004/3008 devices is accomplished using a standard SPI-compatible serial Control Bit Selections interface. Initiating communication with either device is Input Channel done by bringing the CS line low (see Figure5-1). If the Configuration Selection Single/ device was powered up with the CS pin low, it must be D2* D1 D0 Diff brought high and back low to initiate communication. The first clock received with CS low and D high will 1 X 0 0 single-ended CH0 IN constitute a start bit. The SGL/DIFF bit follows the start 1 X 0 1 single-ended CH1 bit and will determine if the conversion will be done 1 X 1 0 single-ended CH2 using single-ended or differential input mode. The next 1 X 1 1 single-ended CH3 three bits (D0, D1 and D2) are used to select the input channel configuration. Table5-1 and Table5-2 show 0 X 0 0 differential CH0 = IN+ the configuration bits for the MCP3004 and MCP3008, CH1 = IN- respectively. The device will begin to sample the ana- 0 X 0 1 differential CH0 = IN- log input on the fourth rising edge of the clock after the CH1 = IN+ start bit has been received. The sample period will end 0 X 1 0 differential CH2 = IN+ on the falling edge of the fifth clock following the start CH3 = IN- bit. 0 X 1 1 differential CH2 = IN- Once the D0 bit is input, one more clock is required to CH3 = IN+ complete the sample and hold period (D is a “don’t IN * D2 is “don’t care” for MCP3004 care” for this clock). On the falling edge of the next clock, the device will output a low null bit. The next 10 clocks will output the result of the conversion with MSB TABLE 5-2: CONFIGURE BITS FOR THE first, as shown in Figure5-1. Data is always output from MCP3008 the device on the falling edge of the clock. If all 10 data Control Bit bits have been transmitted and the device continues to Selections Input Channel receive clocks while the CS is held low, the device will Configuration Selection output the conversion result LSB first, as is shown in Single D2 D1 D0 Figure5-2. If more clocks are provided to the device /Diff while CS is still low (after the LSB first data has been 1 0 0 0 single-ended CH0 transmitted), the device will clock out zeros indefinitely. 1 0 0 1 single-ended CH1 If necessary, it is possible to bring CS low and clock in 1 0 1 0 single-ended CH2 leading zeros on the D line before the start bit. This is IN often done when dealing with microcontroller-based 1 0 1 1 single-ended CH3 SPI ports that must send 8 bits at a time. Refer to 1 1 0 0 single-ended CH4 Section6.1, “Using the MCP3004/3008 with Microcon- 1 1 0 1 single-ended CH5 troller (MCU) SPI Ports”, for more details on using the 1 1 1 0 single-ended CH6 MCP3004/3008 devices with hardware SPI ports. 1 1 1 1 single-ended CH7 0 0 0 0 differential CH0 = IN+ CH1 = IN- 0 0 0 1 differential CH0 = IN- CH1 = IN+ 0 0 1 0 differential CH2 = IN+ CH3 = IN- 0 0 1 1 differential CH2 = IN- CH3 = IN+ 0 1 0 0 differential CH4 = IN+ CH5 = IN- 0 1 0 1 differential CH4 = IN- CH5 = IN+ 0 1 1 0 differential CH6 = IN+ CH7 = IN- 0 1 1 1 differential CH6 = IN- CH7 = IN+  2002 Microchip Technology Inc. DS21295B-page 15

MCP3004/3008 tCYC tCYC t CSH CS t SUCS CLK D Start D2 D1 D0 Don’t Care Start D2 IN SGL/ SGL/ DIFF DIFF HI-Z Null HI-Z DOUT Bit B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 * t CONV t t ** SAMPLE DATA * After completing the data transfer, if further clocks are applied with CS low, the A/D converter will output LSB first data, then followed with zeros indefinitely. See Figure5-2 below. ** t : during this time, the bias current and the comparator powers down while the reference input becomes DATA a high impedance node. FIGURE 5-1: Communication with the MCP3004 or MCP3008. t CYC CS tCSH t SUCS Power Down CLK Start DIN D2 D1D0 Don’t Care SGL/ DIFF DOUT HI-Z NBuitll B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9* HI-Z (MSB) t tCONV tDATA ** SAMPLE * After completing the data transfer, if further clocks are applied with CS low, the A/D converter will output zeros indefinitely. ** t : During this time, the bias circuit and the comparator powers down while the reference input becomes DATA a high impedance node, leaving the CLK running to clock out LSB first data or zeroes. FIGURE 5-2: Communication with MCP3004 or MCP3008 in LSB First Format. DS21295B-page 16  2002 Microchip Technology Inc.

MCP3004/3008 6.0 APPLICATIONS INFORMATION 6.1 Using the MCP3004/3008 with Microcontroller (MCU) SPI Ports With most microcontroller SPI ports, it is required to send groups of eight bits. It is also required that the microcontroller SPI port be configured to clock out data on the falling edge of clock and latch data in on the ris- ing edge. Because communication with the MCP3004/ 3008 devices may not need multiples of eight clocks, it will be necessary to provide more clocks than are required. This is usually done by sending ‘leading zeros’ before the start bit. As an example, Figure6-1 and Figure6-2 shows how the MCP3004/3008 can be interfaced to a MCU with a hardware SPI port. Figure6-1 depicts the operation shown in SPI Mode 0,0, which requires that the SCLK from the MCU idles in the ‘low’ state, while Figure6-2 shows the similar case of SPI Mode 1,1, where the clock idles in the ‘high’ state. As is shown in Figure6-1, the first byte transmitted to the A/D converter contains seven leading zeros before the start bit. Arranging the leading zeros this way induces the 10 data bits to fall in positions easily manip- ulated by the MCU. The MSB is clocked out of the A/D converter on the falling edge of clock number 14. Once the second eight clocks have been sent to the device, the MCU receive buffer will contain five unknown bits (the output is at high impedance for the first two clocks), the null bit and the highest order 2 bits of the conversion. Once the third byte has been sent to the device, the receive register will contain the lowest order eight bits of the conversion results. Employing this method ensures simpler manipulation of the converted data. Figure6-2 shows the same thing in SPI Mode 1,1, which requires that the clock idles in the high state. As with mode 0,0, the A/D converter outputs data on the falling edge of the clock and the MCU latches data from the A/D converter in on the rising edge of the clock.  2002 Microchip Technology Inc. DS21295B-page 17

MCP3004/3008 CS MCU latches data from A/D converter on rising edges of SCLK SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Data is clocked out of A/D converter on falling edges SGL/ DIN Start DIFF D2 D1 DO Don’t Care DOUT HI-Z NBUILTL B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Start MMCCUU TTrraannssmmiitttteedd DDaattaa Bit (Aligned with falling SGL/ edge of clock) 0 0 0 0 0 0 0 1 DIFFD2 D1 DO X X X X X X X X X X X X MCU Received Data (eAdlgigen oefd c wloicthk )rising ? ? ? ? ? ? ? ? ? ? ? ? ? (N0ull)B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Data stored into MCU receive Data stored into MCU receive Data stored into MCU receive register after transmission of first register after transmission of register after transmission of last X = “Don’t Care” Bits 8 bits second 8 bits 8 bits FIGURE 6-1: SPI Communication with the MCP3004/3008 using 8-bit segments (Mode 0,0: SCLK idles low). CS MCU latches data from A/D converter on rising edges of SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SCLK Data is clocked out of A/D converter on falling edges DIN Start DSIGFLF/ D2 D1 DO Don’t Care NULL D HI-Z BIT B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 OUT Start MCU Transmitted Data Bit (eAdlgigen oefd c wloitchk )falling 0 0 0 0 0 0 0 1 DSIGFLF/ D2 D1 DO X X X X X X X X X X X X MCU Received Data (Aligned with rising ? ? ? ? ? ? ? ? ? ? ? ? ? (N0ull) B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 edge of clock) Data stored into MCU receive Data stored into MCU receive Data stored into MCU receive register after transmission of first register after transmission of register after transmission of last X = “Don’t Care” Bits 8 bits second 8 bits 8 bits FIGURE 6-2: SPI Communication with the MCP3004/3008 using 8-bit segments (Mode 1,1: SCLK idles high). DS21295B-page 18  2002 Microchip Technology Inc.

MCP3004/3008 6.2 Maintaining Minimum Clock V DD Speed 10µF 4.096V Reference When the MCP3004/3008 initiates the sample period, 0.1µF 1µF charge is stored on the sample capacitor. When the MCP1541 sample period is complete, the device converts one bit 1µF fuboslere eerd at oco hfnf octhtleoe c tksh aatmht aapt l seils oc warep ccaelociivctoek rdr .aw tIhet i liwes itlilhm aepl locoorwtna vcneht rafsorigor ent h tieos VIN R1 C1 MC+P601 IN+MVCRPE3F004 R2 - IN- taking place. At 85°C (worst case condition), the part C 2 will maintain proper charge on the sample capacitor for R R 4 at least 1.2ms after the sample period has ended. This 3 means that the time between the end of the sample period and the time that all 10 data bits have been FIGURE 6-3: The MCP601 Operational clocked out must not exceed 1.2ms (effective clock Amplifier is used to implement a second order frequency of 10kHz). Failure to meet this criterion may anti-aliasing filter for the signal being converted introduce linearity errors into the conversion outside by the MCP3004. the rated specifications. It should be noted that during the entire conversion cycle, the A/D converter does not 6.4 Layout Considerations require a constant clock speed or duty cycle, as long as When laying out a printed circuit board for use with all timing specifications are met. analog components, care should be taken to reduce 6.3 Buffering/Filtering the Analog noise wherever possible. A bypass capacitor should always be used with this device and should be placed Inputs as close as possible to the device pin. A bypass capac- If the signal source for the A/D converter is not a low itor value of 1µF is recommended. impedance source, it will have to be buffered or inaccu- Digital and analog traces should be separated as much rate conversion results may occur (see Figure4-2). It is as possible on the board, with no traces running under- also recommended that a filter be used to eliminate any neath the device or bypass capacitor. Extra precau- signals that may be aliased back in to the conversion tions should be taken to keep traces with high results, as is illustrated in Figure6-3, where an op amp frequency signals (such as clock lines) as far as possi- is used to drive, filter and gain the analog input of the ble from analog traces. MCP3004/3008. This amplifier provides a low imped- Use of an analog ground plane is recommended in ance source for the converter input, plus a low pass order to keep the ground potential the same for all filter, which eliminates unwanted high frequency noise. devices on the board. Providing V connections to DD Low pass (anti-aliasing) filters can be designed using devices in a “star” configuration can also reduce noise Microchip’s free interactive FilterLab™ software. Filter- by eliminating return current paths and associated Lab will calculate capacitor and resistors values, as errors (see Figure6-4). For more information on layout well as determine the number of poles that are required tips when using A/D converters, refer to AN688, “Lay- for the application. For more information on filtering sig- out Tips for 12-Bit A/D Converter Applications”. nals, see AN699, “Anti-Aliasing Analog Filters for Data Acquisition Systems”. VDD Connection Device 4 Device 1 Device 3 Device 2 FIGURE 6-4: V traces arranged in a ‘Star’ DD configuration in order to reduce errors caused by current return paths.  2002 Microchip Technology Inc. DS21295B-page 19

MCP3004/3008 6.5 Utilizing the Digital and Analog Ground Pins The MCP3004/3008 devices provide both digital and analog ground connections to provide additional means of noise reduction. As is shown in Figure6-5, the analog and digital circuitry is separated internal to the device. This reduces noise from the digital portion of the device being coupled into the analog portion of the device. The two grounds are connected internally through the substrate which has a resistance of 5 -10Ω. If no ground plane is utilized, both grounds must be connected to V on the board. If a ground plane is SS available, both digital and analog ground pins should be connected to the analog ground plane. If both an analog and a digital ground plane are available, both the digital and the analog ground pins should be con- nected to the analog ground plane. Following these steps will reduce the amount of digital noise from the rest of the board being coupled into the A/D converter. V DD MCP3004/08 Digital Side Analog Side -SPI Interface -Sample Cap -Shift Register -Capacitor Array -Control Logic -Comparator Substrate 5 - 10Ω DGND AGND 0.1µF Analog Ground Plane FIGURE 6-5: Separation of Analog and Digital Ground Pins. DS21295B-page 20  2002 Microchip Technology Inc.

MCP3004/3008 7.0 PACKAGING INFORMATION 7.1 Package Marking Information 14-Lead PDIP (300 mil) Example: XXXXXXXXXXXXXX MCP3004-I/P XXXXXXXXXXXXXX YYWWNNN 0212027 14-Lead SOIC (150 mil) Example: XXXXXXXXXXX MCP3004ISL XXXXXXXXXXX XXXXXXXXXXX YYWWNNN 0212027 14-Lead TSSOP (4.4mm) * Example: XXXXXXXX 3004 YYWW I212 NNN 027 * Please contact Microchip Factory for B-Grade TSSOP devices Legend: XX...X Customer specific information* YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard marking consists of Microchip part number, year code, week code, traceability code (facility code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please check with your Microchip Sales Office.  2002 Microchip Technology Inc. DS21295B-page 21

MCP3004/3008 Package Marking Information (Continued) 16-Lead PDIP (300 mil) (MCP3308) Example: XXXXXXXXXXXXXX MCP3008-I/P XXXXXXXXXXXXXX YYWWNNN 0212030 16-Lead SOIC (150 mil) (MCP3308) Example: XXXXXXXXXXXXX MCP3008-I/SL XXXXXXXXXXXXX XXXXXXXXXX YYWWNNN 0212030 DS21295B-page 22  2002 Microchip Technology Inc.

MCP3004/3008 14-Lead Plastic Dual In-line (P) –300 mil (PDIP) E1 D 2 n 1 α E A A2 c L A1 β B1 eB B p Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 14 14 Pitch p .100 2.54 Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32 Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26 Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60 Overall Length D .740 .750 .760 18.80 19.05 19.30 Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43 Lead Thickness c .008 .012 .015 0.20 0.29 0.38 Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78 Lower Lead Width B .014 .018 .022 0.36 0.46 0.56 Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92 Mold Draft Angle Top α 5 10 15 5 10 15 Mold Draft Angle Bottom β 5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-005  2002 Microchip Technology Inc. DS21295B-page 23

MCP3004/3008 14-Lead Plastic Small Outline (SL) –Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 α h 45° c A A2 φ A1 L β Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 14 14 Pitch p .050 1.27 Overall Height A .053 .061 .069 1.35 1.55 1.75 Molded Package Thickness A2 .052 .056 .061 1.32 1.42 1.55 Standoff § A1 .004 .007 .010 0.10 0.18 0.25 Overall Width E .228 .236 .244 5.79 5.99 6.20 Molded Package Width E1 .150 .154 .157 3.81 3.90 3.99 Overall Length D .337 .342 .347 8.56 8.69 8.81 Chamfer Distance h .010 .015 .020 0.25 0.38 0.51 Foot Length L .016 .033 .050 0.41 0.84 1.27 Foot Angle φ 0 4 8 0 4 8 Lead Thickness c .008 .009 .010 0.20 0.23 0.25 Lead Width B .014 .017 .020 0.36 0.42 0.51 Mold Draft Angle Top α 0 12 15 0 12 15 Mold Draft Angle Bottom β 0 12 15 0 12 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-065 DS21295B-page 24  2002 Microchip Technology Inc.

MCP3004/3008 14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP) E E1 p D 2 n 1 B α A c φ β A1 A2 L Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 14 14 Pitch p .026 0.65 Overall Height A .043 1.10 Molded Package Thickness A2 .033 .035 .037 0.85 0.90 0.95 Standoff § A1 .002 .004 .006 0.05 0.10 0.15 Overall Width E .246 .251 .256 6.25 6.38 6.50 Molded Package Width E1 .169 .173 .177 4.30 4.40 4.50 Molded Package Length D .193 .197 .201 4.90 5.00 5.10 Foot Length L .020 .024 .028 0.50 0.60 0.70 Foot Angle φ 0 4 8 0 4 8 Lead Thickness c .004 .006 .008 0.09 0.15 0.20 Lead Width B1 .007 .010 .012 0.19 0.25 0.30 Mold Draft Angle Top α 0 5 10 0 5 10 Mold Draft Angle Bottom β 0 5 10 0 5 10 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005” (0.127mm) per side. JEDEC Equivalent: MO-153 Drawing No. C04-087  2002 Microchip Technology Inc. DS21295B-page 25

MCP3004/3008 16-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 α n 1 E A A2 c L β A1 B1 eB B p Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 16 16 Pitch p .100 2.54 Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32 Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26 Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60 Overall Length D .740 .750 .760 18.80 19.05 19.30 Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43 Lead Thickness c .008 .012 .015 0.20 0.29 0.38 Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78 Lower Lead Width B .014 .018 .022 .036 0.46 0.56 Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92 Mold Draft Angle Top α 5 10 15 5 10 15 Mold Draft Angle Bottom β 5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-017 DS21295B-page 26  2002 Microchip Technology Inc.

MCP3004/3008 16-Lead Plastic Small Outline (SL) –Narrow 150 mil (SOIC) E E1 p D 2 B n 1 α h 45° c A A2 φ L A1 β Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 16 16 Pitch p .050 1.27 Overall Height A .053 .061 .069 1.35 1.55 1.75 Molded Package Thickness A2 .052 .057 .061 1.32 1.44 1.55 Standoff § A1 .004 .007 .010 0.10 0.18 0.25 Overall Width E .228 .237 .244 5.79 6.02 6.20 Molded Package Width E1 .150 .154 .157 3.81 3.90 3.99 Overall Length D .386 .390 .394 9.80 9.91 10.01 Chamfer Distance h .010 .015 .020 0.25 0.38 0.51 Foot Length L .016 .033 .050 0.41 0.84 1.27 Foot Angle φ 0 4 8 0 4 8 Lead Thickness c .008 .009 .010 0.20 0.23 0.25 Lead Width B .013 .017 .020 0.33 0.42 0.51 Mold Draft Angle Top α 0 12 15 0 12 15 Mold Draft Angle Bottom β 0 12 15 0 12 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-108  2002 Microchip Technology Inc. DS21295B-page 27

MCP3004/3008 NOTES: DS21295B-page 28  2002 Microchip Technology Inc.

MCP3004/008 ON-LINE SUPPORT SYSTEMS INFORMATION AND UPGRADE HOT LINE Microchip provides on-line support on the Microchip World Wide Web site. The Systems Information and Upgrade Line provides The web site is used by Microchip as a means to make system users a listing of the latest versions of all of files and information easily available to customers. To Microchip's development systems software products. view the site, the user must have access to the Internet Plus, this line provides information on how customers and a web browser, such as Netscape® or Microsoft® can receive the most current upgrade kits.The Hot Line Internet Explorer. Files are also available for FTP Numbers are: download from our FTP site. 1-800-755-2345 for U.S. and most of Canada, and Connecting to the Microchip Internet Web Site 1-480-792-7302 for the rest of the world. The Microchip web site is available at the following URL: 092002 www.microchip.com The file transfer site is available by using an FTP ser- vice to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A vari- ety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: • Latest Microchip Press Releases • Technical Support Section with Frequently Asked Questions • Design Tips • Device Errata • Job Postings • Microchip Consultant Program Member Listing • Links to other useful web sites related to Microchip Products • Conferences for products, Development Systems, technical information and more • Listing of seminars and events  2002 Microchip Technology Inc. DS21295B-page29

MCP3004/008 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: MCP3004/008 Literature Number: DS21295B Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS21295B-page30  2002 Microchip Technology Inc.

MCP3004/3008 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX Examples: Device Temperature Package a) MCP3004-I/P: Industrial Temperature, PDIP Range package. b) MCP3004-I/SL: Industrial Temperature, SOIC package. Device: MCP3004: 4-Channel 10-Bit Serial A/D Converter c) MCP3004-I/ST: Industrial Temperature, MCP3004T: 4-Channel 10-Bit Serial A/D Converter TSSOP package. (Tape and Reel) MCP3008: 8-Channel 10-Bit Serial A/D Converter d) MCP3004T-I/ST: Industrial Temperature, MCP3008T: 8-Channel 10-Bit Serial A/D Converter TSSOP package, Tape and Reel. (Tape and Reel) a) MCP3008-I/P: Industrial Temperature, PDIP Temperature Range: I = -40°C to +85°C package. b) MCP3008-I/SL: Industrial Temperature, SOIC package. Package: P = Plastic DIP (300 mil Body), 14-lead, 16-lead SL = Plastic SOIC (150 mil Body), 14-lead, 16-lead ST = Plastic TSSOP (4.4mm), 14-lead Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office 2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 3. The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.  2002 Microchip Technology Inc. DS21295B-page31

MCP3004/3008 NOTES: DS21295B-page 32  2002 Microchip Technology Inc.

Information contained in this publication regarding device Trademarks applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to The Microchip name and logo, the Microchip logo, KEELOQ, ensure that your application meets with your specifications. MPLAB, PIC, PICmicro, PICSTART and PRO MATE are No representation or warranty is given and no liability is registered trademarks of Microchip Technology Incorporated assumed by Microchip Technology Incorporated with respect in the U.S.A. and other countries. to the accuracy or use of such information, or infringement of FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL patents or other intellectual property rights arising from such and The Embedded Control Solutions Company are use or otherwise. Use of Microchip’s products as critical com- registered trademarks of Microchip Technology Incorporated ponents in life support systems is not authorized except with in the U.S.A. express written approval by Microchip. No licenses are con- veyed, implicitly or otherwise, under any intellectual property dsPIC, dsPICDEM.net, ECONOMONITOR, FanSense, rights. FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified.  2002 Microchip Technology Inc. DS21295B - page 33

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: MCP3004-I/P MCP3008-I/P MCP3004-I/SL MCP3004-I/ST MCP3008-I/SL MCP3004T-I/ST MCP3004T-I/SL MCP3008T-I/SL