M MCP2502X/5X CAN I/O Expander Family Features Description • Implements CAN V2.0B The MCP2502X/5X devices operate as I/O expanders - Programmable bit rate up to 1Mb/s for a Controller Area Network (CAN) system, supporting CAN V2.0B active, with bus rates up to - One programmable mask 1Mb/s. The MCP2502X/5X allows a simple CAN node - Two programmable filters to be implemented without the need for a - Three auto-transmit buffers microcontroller. - Two message reception buffers The devices are identical, with the following - Does not require synchronization or exceptions: configuration messages • Hardware Features One Wire - Non-volatile memory for user configuration Device A/D Digital - User configuration automatically loaded on CANbus power-up MCP25020 No No - Eight general-purpose I/O lines individually MCP25025 No Yes selectable as inputs or outputs MCP25050 Yes No - Individually selectable transmit-on-pin- change for each input MCP25055 Yes Yes - Four 10-bit, analog input channels with The MCP2502X/5X devices feature a number of programmable conversion clock and VREF peripherals, including digital I/Os, four-channel 10-bit sources (MCP2505X devices only) A/D (MCP2505X) and PWM outputs with automatic - Message scheduling capability message transmission on change-of-input state. This includes an analog input exceeding a preset threshold. - Two 10-bit PWM outputs with independently programmable frequencies One mask and two acceptance filters are provided to give maximum flexibility during system design with - Device configuration can be modified via CAN bus messages respect to identifiers that the device will respond to. The device can also be configured to automatically - In-Circuit Serial Programming™ (ICSP™) of transmit a unique message whenever any of several default configuration memory error conditions occur. - Optional 1-wire CAN bus operation The device is pre-programmed in non-volatile memory • Low-power CMOS technology so that the part defaults to a specific configuration at - Operates from 2.7V to 5.5V power-up. - 10mA active current, typical - 30µA standby current (CAN Sleep mode) • 14-pin PDIP (300mil) and SOIC (150mil) packages • Available temperature ranges: - Industrial (I): -40°C to +85°C - Extended (E): -40°C to +125°C  2003 Microchip Technology Inc. DS21664C-page 1

MCP2502X/5X Package Types Threshold Detection - refers to the MCP2502X/5X’s ability to automatically transmit a message when a PDIP/SOIC predefined analog threshold is reached. GP0/AN0 1 14 VDD GP1/AN1 2 13 TXCAN/TXRXCAN* GP2/AN2/PWM1 3 12 RXCAN/NC* GP3/AN3/PWM2 4 11 GP7/RST/VPP GP4/VREF- 5 10 GP6/CLKOUT GP5/VREF+ 6 9 OSC2 VSS 7 8 OSC1/CLKIN * One-wire option available on MCP250X5 devices. Definition of Terms The following terms are used throughout this document: I/O Expander - refers to the integrated circuit (IC) device being described (MCP2502X/5X). Input Message - term given to messages that are received by the MCP2502X/5X and cause the internal registers to be modified. Once the register modification has been performed, the MCP2502X/5X transmits a Command Acknowledge message to indicate that the command was received and processed. Command Acknowledge Message - term given to the message that is automatically transmitted by the MCP2502X/5X after receiving and processing an input message. Information Request Message - term given to Remote Request messages that are received by the MCP2502X/5X that subsequently generate an output message (data frame) in response. Output Message - term given to the message that the MCP2502X/5X sends in response to an Information Request message. On Bus Message - term given to the message that the MCP2502X/5X transmits after completing the power-on/ self-configuration sequence at timed intervals, if enabled. Self-Configuration - term used to describe the process of transferring the contents of the EPROM memory array to the SRAM memory array. On Bus - term used to describe the condition when the MCP2502X/5X is fully-configured and ready to transmit, or receive, on the bus. This is the only state in which the MCP2502X/5X can transmit on the bus. Edge Detection - refers to the MCP2502X/5X’s ability to automatically transmit a message based upon the occurance of a predefined edge on any digital input. DS21664C-page 2  2003 Microchip Technology Inc.

MCP2502X/5X 1.0 DEVICE OVERVIEW Figure1-1 is the block diagram of the MCP2502X/5X and Table1-1 is the pinout description. This document contains device-specific information on The following sections detail the modules as listed in the MCP2502X/5X family of CAN I/O expanders. The Figure1-1. CAN protocol is not discussed in depth in this document. Additional information on the CAN protocol can be found in the CAN specification, as defined by Robert Bosch GmbH. FIGURE 1-1: MCP2502X/5X BLOCK DIAGRAM GPIO GP0/AN0 GP1/AN1 GP2/AN2/PWM1 GP3/AN3/PWM2 GP4/VREF- GP5/VREF+ User GP6/CLKOUT Memory GP7RST/VPP State Machine and Control Logic TXCAN/ OSC1/CLKIN Timing CAN TXRXCAN OSC2/CLKOUT Generation Protocol Engine RXCAN PWM2 PWM1 A/D* * Only the MCP2505X devices have the A/D module. TABLE 1-1: PINOUT DESCRIPTION Pin Pin Standard Alternate Programming Name Number Function Function Mode Function GP0/AN0 * 1 Bidirectional I/O pin, TTL input buffer Analog input channel None GP1/AN1 * 2 Bidirectional I/O pin, TTL input buffer Analog input channel None GP2/AN2/PWM2 * 3 Bidirectional I/O pin, TTL input buffer Analog input/PWM output None GP3/AN3/PWM3 * 4 Bidirectional I/O pin, TTL input buffer Analog input/PWM output None GP4/VREF- 5 Bidirectional I/O pin, TTL input buffer External VREF- Data GP5/VREF+ 6 Bidirectional I/O pin, TTL input buffer External VREF input Clock VSS 7 Ground None Ground OSC1/CLKIN 8 External oscillator input External clock input None OSC2 9 External oscillator output None None GP6/CLKOUT 10 Bidirectional I/O pin, TTL input buffer CLKOUT output None GP7/RST/VPP 11 Input pin, TTL input buffer External Reset input Vpp RXCAN 12 CAN data receive input Not connected for 1-wire None TXCAN/TXRXCAN 13 CAN data transmit output CAN TX and RX for 1-wire None operation (MCP250X5) VDD 14 Power None Power * Only the MCP2505X devices have the A/D module.  2003 Microchip Technology Inc. DS21664C-page 3

MCP2502X/5X NOTES: DS21664C-page 4  2003 Microchip Technology Inc.

MCP2502X/5X 2.0 CAN MODULE • One full-acceptance mask (standard and extended) The CAN module is a protocol controller that converts • Two full-acceptance filters (standard and between raw digital data and CAN message packets. extended) The main functional block of the CAN module is shown • One filter for each receive buffer in Figure2-1 and consists of: • Three prioritized transmit buffers for transmitting • CAN protocol engine predefined message types • Buffers, masks and filters • Automatic wake-up on bus traffic function The module features include: • Error management logic for transmit and receive • Implementation of the CAN protocol error states • Double-buffered receiver with two separate • Low-power SLEEP mode receive buffers FIGURE 2-1: CAN MODULE BUFFERS TXB0 TXB1 TXB2 E E E G G G A Acceptance Mask A REQTFOAERR SSA REQTFOAERR SSA REQTFOAERR SSA cc RXM cc XBLX E XBLX E XBLX E e e TAMT M TAMT M TAMT M p Acceptance Filter Acceptance Filter p t RXF0 RXF1 t R R M Message X Identifier Identifier X A Queue B B B Control 0 1 Transmit Byte Sequencer Data Field Data Field Receive REC Error PROTOCOL Counter TEC ENGINE Transmit ErrPas Error BusOff Counter Transmit<7:0> Receive<7:0> Shift<14:0> {Transmit<5:0>, Receive<8:0>} Comparator Protocol Finite State CRC<14:0> Machine Bit Transmit Timing Clock Logic Logic Generator TXCAN/TXRXCAN RXCAN Configuration Registers  2003 Microchip Technology Inc. DS21664C-page 5

MCP2502X/5X 2.1 CAN Protocol Finite State Machine 2.3 Error Management Logic The heart of the engine is the Finite State Machine The error management logic is responsible for the fault (FSM). This state machine sequences through confinement of the CAN device. Its two counters (the messages on a bit-by-bit basis, changing states as the Receive Error Counter (REC) and the Transmit Error fields of the various frame types are transmitted or Counter (TEC)) are incremented and decremented by received. The FSM is a sequencer controlling the commands from the Bit Stream processor. According to sequential data stream between the TX/RX Shift the values of the error counters, the MCP2502X/5X is register, the CRC register and the bus line. The FSM set into the states error-active, error-passive or bus-off. also controls the Error Management Logic (EML) and Error-active: Both error counters are below the error- the parallel data stream between the TX/RX Shift passive limit of 128. registers and the buffers. The FSM insures that the pro- cesses of reception, arbitration, transmission and error Error-passive: At least one of the error counters (TEC signaling are performed according to the CAN protocol. or REC) equals or exceeds 128. The automatic retransmission of messages on the bus Bus-off: The transmit error counter (TEC) equals or line is also handled. exceeds the bus-off limit of 256. The device remains in this state until the bus-off recovery sequence is 2.2 Cyclic Redundancy Check (CRC) received. The bus-off recovery sequence consists of 128 occurrences of 11 consecutive recessive bits. The Cyclic Redundancy Check register generates the Cyclic Redundancy Check (CRC) code that is Note: The MCP2502X/5X, after going bus-off, transmitted after either the Control field (for messages will recover back to error-active with 0 data bytes) or the Data field and is used to check automatically if the bus remains idle for the CRC field of incoming messages. 128 x 11 bits. OPTREG2.ERRE must be set to force the MCP2502X/5X to enter Listen-only mode instead of Normal mode during bus recovery. The current error mode (except for bus-off) of the MCP2502X/5X can be determined by reading the EFLG register via the Read CAN error message. FIGURE 2-2: ERROR MODES STATE DIAGRAM RESET Error-Active REC < 127 or TEC < 127 128 occurrences of 11 consecutive “recessive” bits REC > 127 or TEC > 127 Error-Passive TEC > 255 Bus-Off DS21664C-page 6  2003 Microchip Technology Inc.

MCP2502X/5X REGISTER 2-1: TEC - TRANSMITTER ERROR COUNTER R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 bit 7 bit 0 bit 7-0 TEC7:TEC0: Transmit Error Counter bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 2-2: REC - RECEIVER ERROR COUNTER R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 bit 7 bit 0 bit 7-0 REC7:REC0: Receive Error Counter bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown FIGURE 2-3: BIT TIME PARTITIONING Input Signal Prop Phase Phase Sync Segment Segment 1 Segment 2 Sample Point TQ 2.4 Bit Timing Logic nominal bit time is calculated by programming the TQ length and the number of TQ in each time segment, as The Bit Timing Logic (BTL) monitors the bus line input discussed below. and handles the bus-related bit timing based on the CAN protocol. The BTL synchronizes on a recessive- 2.4.1 TIME QUANTUM (TQ) to-dominant bus transition at Start-of-Frame (hard Time Quantum is a fixed unit of time derived from the synchronization) and on any further recessive-to- oscillator period. There is a programmable baud rate dominant bus line transition if the CAN controller itself prescaler (BRP) (with integral values ranging from 1 to does not transmit a dominant bit (resynchronization). 64) as well as a fixed division by two for clock The BTL also provides programmable time segments generation. to compensate for the propagation delay time, phase shifts and to define the position of the sample point within the bit time. These programmable segments are made up of integer units called Time Quanta (TQ). The  2003 Microchip Technology Inc. DS21664C-page 7

MCP2502X/5X The base TQ is defined as twice the oscillator period. 2.4.2.3 Phase Buffer Segments Adding the BRP into the equation yields: The Phase Buffer Segments are used to optimally T = 2*T *(BRP+1) locate the sampling point of the received bit within the Q OSC nominal bit time. The sampling point occurs between where BRP =binary value represented by PS1 and PS2. These segments can be automatically CNF1.BRP<5:0> lengthened or shortened by the resynchronization process. Thus, the variation of the values of the phase By definition, the nominal bit time is programmable buffer segments represent the DPLL functionality. from a minimum of 8TQ to 25TQ. Also, the minimum nominal bit time is 1µs, which corresponds to 1Mb/s. Phase Segment 1 (PS1): The end of PS1 determines the sampling point within a bit time. PS1 is programma- 2.4.2 TIME SEGMENTS ble from 1TQ - 8TQ in duration. Time segments make up the nominal bit time. The Phase Segment 2 (PS2): PS2 provides delay before nominal bit time can be thought of as being divided into the next transmitted data transition and is also pro- separate non-overlapping time segments. These grammable from 1TQ - 8TQ in duration. However, due segments are shown in Figure2-3. to IPT requirements, the actual minimum length of • Synchronization Segment (SyncSeg) phase segment 2 is 2TQ. It may also be defined to be equal to the greater of PS1 or the information process- • Propagation Segment (PropSeg) ing time (IPT). • Phase Buffer Segment 1 (PS1) • Phase Buffer Segment 2 (PS2) 2.4.3 SAMPLE POINT Nominal Bit Time = T *(Sync_Seg+PropSeg The sample point is the point of time at which the bus Q level is read and the value of the received bit is +Phase_Seg1+Phase_Seg2) determined. The sampling point occurs at the end of PS1. If desired, it is possible to specify multiple Rules for Programming the Segments sampling of the bus line at the sample point. The value There are a few rules to follow when programming the of the received bit is determined to be the value of the time segments: majority decision of three values. The three samples are taken at the sample point, and twice before, with a • PropSeg + PS1 ≥ PS2 time of TQ/2 between each sample. • PS2 > Sync Jump Width • PS2 ≥ Information Processing Time 2.4.4 INFORMATION PROCESSING TIME The Information Processing Time (IPT) is the time 2.4.2.1 Synchronization Segment segment (starting at the sample point) that is reserved This part of the bit time is used to synchronize the for calculation of the subsequent bit level. The CAN various CAN nodes on the bus. The edge of the input specification defines this time to be less than or equal signal is expected to occur during the SyncSeg. The to 2TQ. The MCP2502X/5X defines this time to be duration is fixed at 1TQ. 2TQ. Thus, PS2 must be at least 2TQ long. 2.4.2.2 Propagation Segment 2.4.5 SYNCHRONIZATION JUMP WIDTH This part of the bit time is used to compensate for To compensate for phase shifts and oscillator physical delay times within the network. These delay tolerances between the nodes in the system, each times consist of the signal propagation time on the bus CAN controller must be able to synchronize to the line and the internal delay time of the nodes. The delay relevant signal edge of the incoming signal. When a is calculated as being the round-trip time from recessive-to-dominant edge in the transmitted data is transmitter to receiver (twice the signal's propagation detected, the logic will compare the location of the edge time on the bus line), the input comparator delay and to the expected time (SyncSeg). The circuit will then the output driver delay. The length of the Propagation adjust the values of PS1 and PS2, as necessary, using Segment can be programmed from 1TQ to 8TQ by the programmed Synchronization Jump Width (SJW). setting the PRSEG2:PRSEG0 bits of the CNF2 This adjustment is made for resynchronization during a register. message and not hard synchronization, which occurs only at the message Start-of-Frame (SOF). DS21664C-page 8  2003 Microchip Technology Inc.

MCP2502X/5X As a result of resynchronization, PS1 may be 2.4.6.2 CNF2 lengthened or PS2 may be shortened. The amount of The PRSEG<2:0> bits set the length (in TQ’s) of the lengthening or shortening of the phase buffer segments propagation segment. The PS1<2:0> bits set the length has an upper-bound given by the SJW. The SJW is (in TQ’s) of phase segment 1. The SAM bit controls how programmable between 1TQ and 4TQ. The value of many times the RXCAN pin is sampled. Setting this bit the SJW will be added to PS1 (or subtracted from PS2) to a ‘1’ causes the bus to be sampled three times. depending on the phase error (e) of the edge in relation Twice at TQ/2 before the sample point and once at the to the receiver’s SyncSeg. The phase error is defined normal sample point (which is at the end of PS1). The as follows: value of the bus is determined to be the value read • e = 0 if the edge lies within SYNCESEG during at least two of the samples. If the SAM bit is set - No resynchronization is required. to a ‘0’, the RXCAN pin is sampled only once at the • e > 0 if the edge lies before the sample point sample point. The BTLMODE bit controls how the length of PS2 is determined. If this bit is set to a ‘1’, the - PS1 will be lengthened by the amount of the length of PS2 is determined by the PS2<2:0> bits of SJW. CNF3. If the BTLMODE bit is set to a ‘0’ then the length • e < 0 if the edge lies after the sample point of the of PS2 is the greater of PS1 and the information previous bit and before the SyncSeg of the processing time (which is fixed at 2TQ for the current bit MCP2502X/5X). - PS2 will be shortened by the amount of the SJW. 2.4.6.3 CNF3 2.4.6 CONFIGURATION REGISTERS The PS2<2:0> bits set the length, in TQ’s, of PS2, if the CNF2.BTLMODE bit is set to a ‘1’. If the BTLMODE bit There are three registers (in the configuration register is set to a ‘0’, the PS2<2:0> bits have no effect. module) associated with the CAN bit timing logic that Additionally, the wake-up filter (CNF3.WAKFIL) is controls the bit timing for the CAN bus interface. implemented in the CNF3 register. This filter is a low- 2.4.6.1 CNF1 pass filter that can be used to prevent the MCP2502X/ 5X from waking up due to short glitches on the CAN The BRP<5:0> bits control the baud rate prescaler. bus. These bits set the length of TQ relative to the OSC1 input frequency, with the minimum length of TQ being 2TOSC in length (when BRP<5:0> are set to 000000). The SJW<1:0> bits select the synchronization jump width in terms of number of TQ’s. REGISTER 2-3: CNF1 - CAN CONFIGURATION REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 bit 7 bit 0 bit 7-6 SJW1:SJW0: Synchronized Jump Width bits 11 = Length = 4 x TQ 10 = Length = 3 x TQ 01 = Length = 2 x TQ 00 = Length = 1 x TQ bit 5-0 BRP5:BRP0: Baud Rate Prescaler bits 111111 =TQ = 2 x 64 x 1/FOSC - - 000000 =TQ = 2 x 1 x 1/FOSC Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003 Microchip Technology Inc. DS21664C-page 9

MCP2502X/5X REGISTER 2-4: CNF2 - CAN CONFIGURATION REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BTLMODE SAM PHSEG12 PHSEG11 PHSEG10 PRSEG2 PRSEG1 PRSEG0 bit 7 bit 0 bit 7 BTL MODE: Length determination of PHSEG2 bit 1 = Length of Phase_Seg2 determined by bits 2:0 of CNF3 0 = Length of Phase_Seg2 is the greater of Phase_Seg1 or IPT(2Tq) bit 6 SAM: Sample of the CAN bus line bit 1 = Bus line is sampled three times at the sample point 0 = Bus line is sampled once at the sample point bit 5-3 PHSEG12:PHSEG10: Phase Buffer Segment1 bits 111 = length = 8 x TQ - - - 000 = length = 1 x TQ bit 2-0 PRSEG2:PRSEG0: Propagation Time Segment bits 111 = length = 8 x TQ - - - 000 = length = 1 x TΘ Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 2-5: CNF3 - CAN CONFIGURATION REGISTER 3 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — WAKFIL — — — PHSEG22 PHSEG21 PHSEG20 bit 7 bit 0 bit 7 Unimplemented: (Reads as 0) bit 6 WAKFIL: Wake-up filter bit 1 = Wake-up filter enabled 0 = Wake-up filter disabled bit 5-3 Unimplemented: (Reads as 0) bit 2-0 PHSEG22:PHSEG20: Phase Buffer Segment2 bits 111 = length = 8 x TQ - - - 001 = length = 2 x TQ 000 = Invalid Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS21664C-page 10  2003 Microchip Technology Inc.

MCP2502X/5X 2.5 Buffers, Masks, and Filters Command Acknowledge: TXID1 sends a Command Acknowledge message when the MCP2502X/5X This part of the CAN module supports the transmitting, receives an Input Message and processes the receiving and acceptance of CAN messages. instruction (and OPTREG2.CAEN = 1). This message Three transmit buffers are used for the three transmit is used as a hand shake for the node requesting the message IDs, as discussed later in this section. Two modification of the MCP2502X/5X. There is no data receive buffers store the CAN message’s arbitration associated with this message. field, control field and the data field. Receive Overflow: TXID1 sends a Receive Overflow One mask defines which bits are to be applied to either message if there is a Receive Overflow condition (and filter. The mask can be regarded as defining “don’t OPTREG2.CAEN = 0). This only occurs if the device care” bits for the filter. has received a valid message before processing the previous valid message from the same receive buffer. Each of the two filters define a bit pattern that will be There is no data associated with this message. compared to all incoming messages. All filter bits that have not been defined as “don’t care” by the mask are Error Condition: An Error Condition message is applied to the message. transmitted if the TEC or REC counters reach error warning (> 95) or error passive (> 127). This message 2.5.1 TRANSMIT MESSAGE ID’S contains the TXID1 identifier and the TEC, REC and EFLG counters. The MCP2502X/5X device contains three separate transmit message ID’s: TXID0, TXID1 and TXID2. The A hysteresis is implemented in hardware that prevents data length code is predefined for each of the various messages from repeatedly being transmitted due to output messages, with the data that is transmitted error counts changing by one or two bits. Once a coming directly from the contents of the device’s message is sent for an error warning (TEC or REC > peripheral registers. 95), the message will not trigger again until the error counter ≤ 79 and back to > 95 (hysteresis = 17 counts). 2.5.1.1 Transmit Message ID0 (TXID0) Similarly, an error passive message is sent at TEC or TXID0 contains the identifier that is used when trans- REC > 127 and is not sent again until the error counter mitting the On Bus message. If enabled ≤ 111 and back to >127 (hysteresis = 17 counts). (STCON.STEN = 1), the On Bus message will be 2.5.1.3 Transmit Message ID2 (TXID2) transmitted at predefined intervals. Depending on the message-select bit (STCON.STMS = 1), the CAN Transmit ID2 contains the identifier that is used when message will send GPIO and A/D data. transmitting auto-conversion-initiated messages, including digital input edge detection and/or analog Transmit Message ID0 will not automatically be sent input exceeding a threshold. This message will also be when the device is brought out of sleep. sent when the device wakes up from sleep due to a 2.5.1.2 Transmit Message ID1 (TXID1) digital input change-of-state condition (i.e., change-of- state occurs on input configured to transmit on TXID1 contains the identifier that is used when the change-of-state). MCP2502X/5X sends the Command Acknowledge message, the Receive Overflow message and/or the 2.6 Receive Buffers Error Condition message. All message types use the same identifier. The MCP2505X contains two receive buffers, each The CAEN bit, in the OPTREG2 register, selects with their own filter. There is also a Message Assembly between the Command Acknowledge and Receive Buffer (MAB) that acts as a third receive buffer (see Overflow operation. These message types have a DLC Figure2-1). of 0 and do not contain any data. The Error Condition The two receive buffers, combined with the MAB help, message can occur anytime, has a DLC of 3 and insure that received messages will be processed while contains the EFLG, TEC and REC data values. minimizing the chances of receive buffer overrun due to maximum bus loading of messages destined for the Note: A zero data length On Bus message will be MCP2502X/5X. transmitted once after power-up, regardless of scheduled transmission- Note: The receive buffers are used by the enable status. MCP2502X/5X to implement the command messages and are not externally accessible.  2003 Microchip Technology Inc. DS21664C-page 11

MCP2502X/5X 2.7 Acceptance Mask Message with an extended ID - the three least significant bits of the standard identifier The acceptance mask is used to define which bits in (RXMSIDL.SID2:SID0) are configurable and the three the CAN ID are to be compared against the program- least significant bits of the extended identifier mable filters. Individual bits within the mask correspond (RXMEID0.EID2:EID0) are always ‘don’t cares’ and to bits in the CAN ID that, in turn, correspond to bits in effectively becomes ‘0’. the acceptance filters. Any bit in the mask that is set to a ‘1’ will cause the corresponding CAN ID bit to be Note: The EXIDE bit in the Mask register compared against the associated filter bit. Any bit in the (RXMSIDL) can be used to mask the IDE mask that is set to a ‘0’ is not compared and effectively bit in the corresponding Receive buffer sets the associated CAN ID bit to ‘don’t care’. register (RXBnSIDL). 2.7.1 MASKS AND STANDARD/ 2.8 Acceptance Filters EXTENDED IDS There are two separate acceptance filters defined for To insure proper operation of the information request the MCP2502X/5X: RXF0 and RXF1. RXF0 is used for and input messages, some mask bits (as configured in Information Request messages and RXF1 is used for the mask registers) may be ignored as explained: input messages (see Table4-2 and Table4-3). Each bit Message with a standard ID - the three least in the filters corresponds to a bit in the CAN ID. Every significant bits of a standard identifier bit in the CAN ID, for which the corresponding Mask bit (RXMSIDL.SID2:SID0) are ‘don’t care’ for the mask is set, must match the associated filter bit in order for registers and effectively become ‘0’. the message to be accepted. Messages that fail to meet the mask/fIlter criteria are ignored. REGISTER 2-6: TXIDNSIDH - TRANSMIT IDENTIFIER N STANDARD IDENTIFIER HIGH R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 7 bit 0 bit 7-0 SID10:SID3: Standard Identifier bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS21664C-page 12  2003 Microchip Technology Inc.

MCP2502X/5X REGISTER 2-7: TXIDNSIDL - TRANSMIT IDENTIFIER N STANDARD IDENTIFIER LOW R/W-x R/W-x R/W-x U-0 R/W-x U-0 R/W-x R/W-x SID2 SID1 SID0 — EXIDE — EID17 EID16 bit 7 bit 0 bit 7-5 SID2:SID0: Standard Identifier bits bit 4 Unimplemented: Read as '0’ bit 3 EXIDE: Extended Identifier Enable bit 1 = Message will transmit extended identifier 0 = Message will transmit standard identifier bit 2 Unimplemented: Read as '0’ bit 1-0 EID17:EID16: Extended Identifier bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 2-8: TXIDNEID8 - TRANSMIT IDENTIFIER N EXTENDED IDENTIFIER HIGH R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 7 bit 0 bit 7-0 EID15:EID8: Extended Identifier bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 2-9: TXIDNEID0 - TRANSMIT IDENTIFIER N EXTENDED IDENTIFIER LOW R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 bit 7 bit 0 bit 7-0 EID7:EID0: Extended Identifier bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003 Microchip Technology Inc. DS21664C-page 13

MCP2502X/5X REGISTER 2-10: RXMSIDH - ACCEPTANCE FILTER MASK STANDARD IDENTIFIER HIGH R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3* bit 7 bit 0 bit 7-0 SID10:SID3: Standard Identifier bits * If OPTREG2.MTYPE = 1, then SID3 is forced to zero. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 2-11: RXMSIDL - ACCEPTANCE FILTER MASK STANDARD IDENTIFIER LOW R/W-x R/W-x R/W-x U-0 R/W-x U-0 R/W-x R/W-x SID2 SID1 SID0 — EXIDE — EID17 EID16 bit 7 bit 0 bit 7-5 SID2:SID0: Standard Identifier bits Standard messages, bits = b’000’ Extended messages, bits = SID2:SID0 bit 4 Unimplemented: Read as '0’ bit 3 EXIDE: Extended Identifier Enable bit 1 = Apply filter to RXFnSIDL.EXIDE (filter applies to standard or extended message frames depending on filter bit) 0 = Do not apply filter to RXFnSIDL.EXIDE (filter will be applied to both standard and extended message frames) bit 2 Unimplemented: Read as '0’ bit 1-0 EID17:EID16: Extended Identifier bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 2-12: RXMEID8 - ACCEPTANCE FILTER MASK EXTENDED IDENTIFIER MID R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 7 bit 0 bit 7-0 EID15:EID8: Extended Identifier bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS21664C-page 14  2003 Microchip Technology Inc.

MCP2502X/5X REGISTER 2-13: RXMEID0 - ACCEPTANCE FILTER MASK EXTENDED IDENTIFIER LOW R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 bit 7 bit 0 bit 7-3 EID7:EID3: Extended Identifier bits bit 2-0 EID2:EID0: Extended Identifier bits (always reads as ‘0’) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 2-14: RXFNSIDH - ACCEPTANCE FILTER N STANDARD IDENTIFIER HIGH R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3* bit 7 bit 0 bit 7-0 SID10:SID3: Standard Identifier bits * If OPTREG2.MTYPE = 1, then SID3 = X Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 2-15: RXFNSIDL - ACCEPTANCE FILTER N STANDARD IDENTIFIER LOW R/W-x R/W-x R/W-x U-0 R/W-x U-0 R/W-x R/W-x SID2 SID1 SID0 — EXIDE — EID17 EID16 bit 7 bit 0 bit 7-5 SID2:SID0: Standard Identifier bits 1 = When EXIDE = 1, SID2:SID0 = b’xxx’ 0 = When EXIDE = 0, SID2:SID0 = as configured bit 4 Unimplemented: Read as ‘0’ bit 3 EXIDE: Extended Identifier Enable bit 1 = Filter will apply to extended identifier 0 = Filter will apply to standard identifier bit 2 Unimplemented: Read as ‘0’ bit 1-0 EID17:EID16: Extended Identifier bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003 Microchip Technology Inc. DS21664C-page 15

MCP2502X/5X REGISTER 2-16: RXFNEID8 - ACCEPTANCE FILTER N EXTENDED IDENTIFIER MID R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 7 bit 0 bit 7-0 EID15:EID8: Extended Identifier Bit Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 2-17: RXFNEID0 - ACCEPTANCE FILTER N EXTENDED IDENTIFIER LOW R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 bit 7 bit 0 bit 7-0 EID7:EID0: Extended Identifier Bit (always = b’xxx’) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS21664C-page 16  2003 Microchip Technology Inc.

MCP2502X/5X REGISTER 2-18: EFLG - ERROR FLAG REGISTER R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 ESCF RBO TXBO TXEP RXEP TXWAR RXWAR EWARN bit 7 bit 0 bit 7 ESCF: Error State Change (for sending Error state message) 1 = An error state change occurred 0 = No error state change bit 6 RBO: Receive Buffer Overflow 1 = Overflow occurred 0 = No overflow occurred bit 5 TXBO: Transmitter in Bus Off Error State bit 1 = TEC reaches 256 0 = Indicates a successful bus recovery sequence bit 4 TXEP: Transmitter in Error Passive State bit 1 = TEC is equal to or greater than 128 0 = TEC is less than 128 bit 3 RXEP: Receiver in Error Passive State bit 1 = REC is equal to or greater than 128 0 = REC is less than 128 bit 2 TXWAR: Transmitter in Error Warning State bit 1 = TEC is equal to or greater than 96 0 = TEC is less than 96 bit 1 RXWAR: Receiver in Error Warning State bit 1 = REC is equal to or greater than 96 0 = REC is less than 96 bit 0 EWARN; Either the Receive Error counter or Transmit error counter has reached or exceeded 96 errors 1 = TEC or REC is equal to or greater than 96 (TXWAR or RXWAR = 1) 0 = Both REC and TEC are less than 96 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003 Microchip Technology Inc. DS21664C-page 17

MCP2502X/5X NOTES: DS21664C-page 18  2003 Microchip Technology Inc.

MCP2502X/5X 3.0 USER REGISTERS Note 1: When transferred to RAM, the register addresses are offset by 1Ch. Accessing 3.1 Description individual registers using the “Write Register” or “Read Register command The MCP2502X/5X allows the user to pre-program requires use of the offset address. Also, registers pertaining to CAN module and device see Table3-2 for information on configuration into non-volatile EPROM memory. In this accessible registers not contained in user way, the device is initialized to a default state after EPROM. power-up. The user registers are transferred to SRAM 2: Do not address locations outside of the during the power-up sequence and many of the user memory map or unexpected results registers are able to be accessed via the CAN bus once may occur. the device establishes a connection with the bus. Additionally, there are 16 user-defined registers that can be used to store information about the part (e.g., serial number, node identifier, etc.). The registers are summarized in Table3-1. TABLE 3-1: USER MEMORY MAP Address Name Description Address Name Description 00h IOINTEN Enable inputs for Transmit-On-Change 1Bh RXF0EID0 Acceptance Filter 0, Extended ID feature LSB 01h IOINTPO Defines polarity for I/O or greater than/ 1Ch RXF1SIDH Acceptance Filter 1, Standard ID less than operator for A/D Transmit-On- MSB Change inputs 02h GPLAT General Purpose I/O (GPIO) Register 1Dh RXF1SIDL Acceptance Filter 1, Standard ID LSB, Extended ID USB, and Extended ID enable 03h 0xFF Reserved 1Eh RXF1EID8 Acceptance Filter 1, Extended ID MSB 04h OPTREG1 Configuration options, including GPIO 1Fh RXF1EID0 Acceptance Filter 1, Extended ID pull-up enable, clockout enable and LSB prescaler 05h T1CON PWM1 Timer Control Register; contains 20h TXID0SIDH Transmit Buffer 0, Standard ID MSB enable bit, clock prescale and DC LSBs 06h T2CON PWM2 Timer Control Register; contains 21h TXID0SIDL Transmit Buffer 0, Standard ID LSB, enable bits, clock prescale and DC LSBs Extended ID USB, and Extended ID enable 07h PR1 PWM1 Period Register 22h TXID0EID8 Transmit Buffer 0, Extended ID MSB 08h PR2 PWM2 Period Register 23h TXID0EID0 Transmit Buffer 0, Extended ID LSB 09h PWM1DCH PWM1 Duty Cycle (DC) MSBs 24h TXID1SIDH Transmit Buffer 1, Standard ID MSB 0Ah PWM2DCH PWM2 Duty Cycle (DC) MSBs 25h TXID1SIDL Transmit Buffer 1, Standard ID LSB, Extended ID USB, and Extended ID enable 0Bh CNF1 3 CAN module register configures 26h TXID1EID8 Transmit Buffer 1, Extended ID MSB synchronization jump width and baud rate prescaler 0Ch CNF2 3 CAN module register configures 27h TXID1EID0 Transmit Buffer 1, Extended ID LSB propagation segment, phase segment 1, and determines number of sample points 0Dh CNF3 3 CAN module register configures phase 28h TXID2SIDH Transmit Buffer 2, Standard ID MSB buffer segment 2, Sleep mode Note 1: GPDDR is mapped to 1Fh is SRAM and not offset by 1Ch. 2: User memory (35h-44h) is not transferred to RAM on power-up and can only be accessed via “Read User Mem” commands. 3: Cannot be modified from initial programmed values. 4: Unimplemented on MCP2502X devices and read 0x00 (exception, ADCON1 = 0x0F).  2003 Microchip Technology Inc. DS21664C-page 19

MCP2502X/5X TABLE 3-1: USER MEMORY MAP (CONTINUED) Address Name Description Address Name Description 0Eh ADCON04 A/D Control Register; contains enable, 29h TXID2SIDL Transmit Buffer 2, Standard ID LSB, conversion rate, channel select bits Extended ID USB, and Extended ID enable 0Fh ADCON14 A/D Control Register; contains voltage 2Ah TXID2EID8 Transmit Buffer 2, Extended ID MSB reference source, conversion rate and A/D input enable bits 10h STCON Scheduled Transmission Control Register 2Bh TXID2EID0 Transmit Buffer 2, Extended ID LSB 11h OPTREG2 Configuration options, including Sleep 2Ch ADCMP3H4 Analog Channel 3 Compare Value mode, RTR message and error recovery MSB enables 12h — Reserved 2Dh ADCMP3L4 Analog Channel 3 Compare Value LSb’s 13h — Reserved 2Eh ADCMP2H4 Analog Channel 2 Compare Value MSB 14h RXMSIDH Acceptance Filter Mask, Standard ID MSB 2Fh ADCMP2L4 Analog Channel 2 Compare Value LSb’s 15h RXMSIDL Acceptance Filter Mask, Standard ID LSB 30h ADCMP1H4 Analog Channel 1 Compare Value and Extended ID USB MSB 16h RXMEID8 Acceptance Filter Mask, Extended ID 31h ADCMP1L4 Analog Channel 1 Compare Value MSB LSb’s 17h RXMEID0 Acceptance Filter Mask, Extended ID LSB 32h ADCMP0H4 Analog Channel 0 Compare Value MSB 18h RXF0SIDH Acceptance Filter 0, Standard ID MSB 33h ADCMP0L4 Analog Channel 0 Compare Value LSb’s 19h RXF0SIDL Acceptance Filter 0, Standard ID LSB, 34h GPDDR1 General Purpose I/O Data Direction Extended ID USB, and Extended ID Register enable 1Ah RXF0EID8 Acceptance Filter 0, Extended ID MSB 35-44h USER[0:F]2 User Defined Bytes (0-15) Note 1: GPDDR is mapped to 1Fh is SRAM and not offset by 1Ch. 2: User memory (35h-44h) is not transferred to RAM on power-up and can only be accessed via “Read User Mem” commands. 3: Cannot be modified from initial programmed values. 4: Unimplemented on MCP2502X devices and read 0x00 (exception, ADCON1 = 0x0F). TABLE 3-2: ACCESSIBLE RAM REGISTERS NOT IN THE EPROM MAP Value on Value on Addr* Name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 POR RST 1Fh** GPDDR — DDR6 DDR4 DDR4 DDR3 DDR2 DDR1 DDR0 -111 1111 -111 1111 18h EFLG ESCF RBO TXEP TXEP RXEP TXWAR RXWAR EWARN 0000 0000 0000 0000 19h TEC Transmit Error Counters 0000 0000 0000 0000 1Ah REC Receive Error Counters 0000 0000 0000 0000 50h ADRES3H AN3.9 AN3.8 AN3.6 AN3.6 AN3.5 AN3.4 AN3.3 AN3.2 xxxx xxxx uuuu uuuu 51h ADRES3L AN3.1 AN3.0 — — — — — — xx-- ---- uu-- ---- 52h ADRES2H AN2.9 AN2.8 AN2.6 AN2.6 AN2.5 AN2.4 AN2.3 AN2.2 xxxx xxxx uuuu uuuu 53h ADRES2L AN2.1 AN2.0 — — — — — — xx-- ---- uu-- ---- 54h ADRES1H AN1.9 AN1.8 AN1.6 AN1.6 AN1.5 AN1.4 AN1.3 AN1.2 xxxx xxxx uuuu uuuu 55h ADRES1L AN1.1 AN1.0 — — — — — — xx-- ---- uu-- ---- 56h ADRES0H AN0.9 AN0.8 AN0.6 AN0.6 AN0.5 AN0.4 AN0.3 AN0.2 xxxx xxxx uuuu uuuu 57h ADRES0L AN0.1 AN0.0 — — — — — — xx-- ---- uu-- ---- * These addresses are used when using the “Write Register” or “Read Register” command ** The GPDDR register is not offset to RAM the same as the other registers in the EPROM DS21664C-page 20  2003 Microchip Technology Inc.

MCP2502X/5X 4.0 DEVICE OPERATION Scheduled Transmissions Once the MCP2502X/5X has gone on bus it will 4.1 Power-Up Sequence transmit the On Bus message once, regardless of whether enabled or not. This message notifies the The following sections describe the events/actions of network of the MCP2502X/5X’s presence. The On Bus the MCP2502X/5X during normal power-up and message will (if enabled STCON.STEN) repeat at a operation. frequency determined by the STCON register (Register4-1). 4.1.1 POWER-ON RESET This message can also be configured to send the The MCP2502X/5X goes through a sequence of events “Read A/D Register” data bytes along with the at power-on reset (POR) in order to load the predefined identifier in TXID2 by setting programmed configuration and insure that errors are STCON.STMS=1. not introduced on the bus. During this time, the device is prevented from generating a low condition on the Note: The first On Bus message sent after TXCAN pin. The TXCAN pin must remain high from power-up will NOT send the “Read A/D power-on until the device goes on bus. Register” data bytes, regardless of the Operational Mode at Power-On STCON.STMS value. The MCP2502X/5X initially powers up in Configuration Note: If the MCP2502X/5X enters SLEEP mode, mode. While in this mode, the MCP2502X/5X will be the scheduled transmissions will cease prevented from sending or receiving messages via the until the device wakes up again. This CAN interface. The ADC and PWM peripherals are implies that SLEEP mode has priority over disabled while in this mode. scheduled transmissions. Self-Configuration 4.2 Message Functions Once the MCP2502X/5X is out of reset, it will perform a self-configuration. This is accomplished by The MCP2502X/5X uses the global mask (RXMASK), transferring the contents of the EPROM array to the two filters (RXF0 and RXF1) and two receive buffers corresponding locations within the SRAM array. In (RB0 and RB1) to determine if a received message addition, the checksum of the data written to SRAM will should be acted upon. There are 16 functions that can be compared to a pre-programmed value as a test of be performed by the MCP2502X/5X based on received valid data. messages (see Table4-1).These functions allow the device to not only be accessed for Information Going On Bus Request/Input/Output operations, but also to be Once the self-configuration cycle has successfully reconfigured via the CAN bus, if necessary. completed, the MCP2502X/5X switches to Listen-only mode. It will remain in this mode until an error-free CAN 4.3 Message Types message is detected. This is done to ensure that the device is at the correct bus rate for the system. There are three types of messages that are used to implement the functions of Table4-1. Once the device detects an error-free message, it waits for CAN bus idle before switching to Normal mode. This 1. Information Request Messages (IRM) prevents it from going on bus in the middle of another - Received by the MCP2502X/5X. node’s transmission and generating an error frame. 2. Output Messages - Transmitted from the Alternately, the MCP2505X may directly enter Normal MCP2502X/5X as a response to IRMs. mode (without first entering Listen-only Mode) after 3. Input Messages - Received by the MCP2502X/ completing its self-configuration. This is configured by 5X and used to modify registers. the user via a control bit (OPTREG2.PUNRM). Note: Information Request Messages (IRMs) Once the MCP2502X/5X enters Normal mode, it is and Input messages are both input ready to send/receive messages via the CAN interface. messages to the MCP2502X/5X. IRMs are At this point the ADC and PWM peripherals are received into receive buffer 0 and input operational, if enabled. messages are received into receive buffer 1. This must be taken into account while configuring the acceptance filters.  2003 Microchip Technology Inc. DS21664C-page 21

MCP2502X/5X 4.3.1 INFORMATION REQUEST 4.3.1.1 RTR Message Type MESSAGES When RTR message types are selected Information Request Messages (IRM) are messages (OPTREG2.MTYPE) and a node in the system wants that the MCP2502X/5X receives into Receive Buffer 0 information from the MCP2502X/5X, it has to send a (matches Filter 0) and then responds to by transmitting remote frame on the bus. The identifier for the remote a message (output message) containing the requested frame must be such that it will be accepted through the data. MCP2502X/5X’s mask/filter process (using RXF0). The RTR message type (remote frames) is the default IRMs can be implemented as either a Remote Transfer configuration (MTYPE bit = 0). Request (RTR) or a Data Frame message by configuring the MTYPE bit in the OPTREG2 register. Information Request “RTR” messages must not only meet the RXMASK/RXF0 criteria but must also have TABLE 4-1: MESSAGE FUNCTION the RTR bit of the CAN ID set (since the filter registers do not contain an explicit RTR bit). If a message passes Name Description the mask/filter process and the RTR bit is a ‘0’, that Read A/D Transmits a single message containing message will be ignored. Registers the current state of the analog and I/O Once the MCP2502X/5X has received a remote frame, registers, including the configuration it will determine the function to be performed based Read Control Transmits several control registers not upon the three LSb’s (RXB0SIDL.SID2:SID0 for Registers included in other messages standard messages and RXB0EID0.EID2:EID0 for Read Configura- Transmits the contents of many of the extended messages) of the received remote frame. tion Registers configuration registers Additionally, a predefined Data Length Code (DLC) Read CAN Transmits the error flag register and must be sent to signify the number of data bytes that error states the error counts the MCP2502X/5X must return in it’s output message Read PWM Transmits the registers associated with (see Table4-2 and Table4-3). Configuration the PWM modules Read User Transmits the values in bytes 0 - 7 of 4.3.1.2 Data Frame Message Type Registers 1 the user memory When a non-RTR (or data frame) message type is Read User Transmits the values in bytes 8 -15 of selected and a node in the system wants information Registers 2 the user memory from the MCP2502X/5X, it sends an Information Read Register* Transmits a single byte containing the Request in the form of a data frame. The identifier for value in an addressed user memory this request must be such that it will be accepted register through the MCP2502X/5X’s mask/filter process (using Write Register Uses a mask to write a value to an RXF0). addressed register Information request messages in the data frame format Write TX Message Writes the identifiers to a specified must not only meet the RXMASK/RXF0 criteria, but ID0 (TXID0) value must also have the RTR bit of the CAN ID cleared Write TX Message Writes the identifiers to a specified (since the filter registers do not contain an explicit RTR ID1 (TXID1) value bit). If a message passes the mask/filter process and Write TX Message Writes the identifiers to a specified the RTR bit is a ‘1’, that message will be ignored. ID2 (TXID2) value Once the MCP2502X/5X has received a data frame Write I/O Writes specified values to the three Configuration IOCON registers information request, it will determine the function to be Registers performed based upon the three LSb’s Write RX Mask Changes the receive mask to the (RXB0SIDL.SID2:SID0 for standard messages and specified value RXB0EID0.EID2:EID0 for extended messages) of the received data frame. Also, Bit 3 of the received Write RX Filter0 Changes the specified filter to the message ID must be set to a ‘1’. specified value Write RX Filter1 Changes the specified filter to the In addition, the data length code (DLC) must be set to specified value a zero. Refer to Table4-2 and Table4-3 for more * The Read Register command is available when using information. extended message format only. Not available with Regardless of the message format, all messages standard message format. except the Read Register message can use either standard or extended identifiers. The Read Register message has one additional requirement; it must be an extended identifier. This is discussed in more detail in Table4-1 and Table4-3 for more information. DS21664C-page 22  2003 Microchip Technology Inc.

MCP2502X/5X 4.3.2 OUTPUT MESSAGES three bits of the standard identifier (RXF1SIDL.SID2:SID0) will indicate which register(s) The data frame sent in response to the information are to be written. The values for the register(s) are request message is defined as an output message. contained in the data byte registers as defined in If the data fame is in response to a remote frame, it will Table4-2. have the same identifier (standard or extended) and Note: If using more than one controlling node, the contain the same number of data bytes specified by the DLC of the remote frame (per the CAN 2.0B MCP2502X/5X must be set up to accept specification). input messages with different identifiers in order to avoid possible message collisions in Note: If the DLC of the incoming remote frame the DLC or data bytes if transmitted at the differs from the message definitions same time. summarized in Table4-2 and Table4-3, the resulting output message will limit itself to the Note 1: IRMs can theoretically be sent by more erroneous DLC that was received (to than one controlling node because the message is a predefined constant and maintain compliance with the Bosch CAN destructive collisions will not occur. specification). The output message will concatenate the number of data bytes for an 2: The number of data bytes in an input erroneous DLC that is less than the defined message must match the DLC number as number. For an erroneous DLC that is defined in Table4-2 and Table4-3. If the greater than the defined number, the user specifies and transmits an input MCP2502X/5X will extend the number of message with a DLC that is less than the data bytes, with the data value of the last required number of data bytes, the defined data byte being repeated in the extra MCP25020 will operate on corrupted data bytes in the data field. for the bytes that it did not receive and unknown results will occur. If the output message is in response to a data frame, the lower-three LSb’s of the identifier (standard or 4.4 Dynamic Message Handling extended) must be the same as the received message, as well as the upper-seven MSb’s in the case of a The design insures that transmit and receive messages standard identifier, or the upper 25MSb’s in the case of are handled properly for variable bus-loading an extended identifier. Bit 3 of a standard or extended conditions and different transmit/receive combinations. identifier of the output message will differ from the received information request message in that the value 4.4.1 MESSAGE ACCEPTANCE/ equals ‘1’ for an IRM and equals ‘0’ for the resulting REJECTION output message. Messages received that meet the Mask/RXFn criteria Output messages contain the requested data (in the are then compared to the requirements for input data field). Example: The information request messages or IRMs, as determined by the filter used to message Read CAN error is a remote transmit request accept the message. If the message meets the received by the MCP2502X/5X with a DLC of 3. The requirements of one of the associated input or responding output message will return a data frame information request messages, the appropriate actions that contains the same identifier (standard or extended) for that message function are taken. as the receive message. The accompanying data bytes will contain the values of the predefined GPIO registers 4.4.2 RECEIVING MULTIPLE MESSAGES and related control/status registers, as shown in The MCP2502X/5X can only receive and process one Table4-2 and4-3. message at a time. While the MCP2502X/5X should 4.3.3 INPUT MESSAGES have ample time to process any received message before another is completely received, a second Input messages are received into receive buffer 1 and message received before the first message is finished are used to change the values of the pre-defined processing will be lost. groups of registers. There is also an input message that can change a single register’s contents. The However, the MCP2502X/5X has the ability to notify the primary purpose of input messages are to reconfigure network if a message is lost. TXID1 can be configured to transmit a message if a receive overflow occurs MCP2502X/5X parameters (if needed) while in an (OPTREG2.CAEN=0). operating CAN system and are, therefore, optional in system implementation. These messages are in the form of standard (or extended) data frames (per the CAN 2.0B specification) that have identifiers which pass the MCP2502X/5X’s mask/filter process (using RXF1). After passing the mask and filter, the lower-  2003 Microchip Technology Inc. DS21664C-page 23

MCP2502X/5X 4.4.3 TRANSMIT MESSAGE PRIORITY There is a priority for all transmit messages, including TXIDn and all “Output” messages. The transmit message priority is as follows: 1. Output messages have the highest priority. Prioritization of the individual output message types is determined by the three bits that determine message type, with the lowest value having the highest priority (e.g., Read A/D Regs is a higher priority than Read Control Regs). 2. TXID2 (Transmit auto-converted messages) has the second-highest priority. 3. TXID1 (Command acknowledge) has the third- highest priority. 4. TXID0 (On Bus message) has the lowest priority. In the event two or more messages are pending transmission, transmit-message-prioritization will occur and the highest message type will be sent first. Messages that are currently transmitting will not be prioritized. DS21664C-page 24  2003 Microchip Technology Inc.

 TABLE 4-2: COMMAND MESSAGES (STANDARD IDENTIFIER) 2 0 Information Request Messages (to MCP2502X/5X) 0 3 M Standard ID Data Bytes ic ro 1 9 8 7 6 5 4 3 2 1 0 R I ch 0 T D DLC ip T R E e c Read A/D Regs x x x x x x x * 0 0 0 1* 0 1 0 0 0 8* n/a n/a n/a n/a n/a n/a n/a n/a h n Read Control Regs x x x x x x x * 0 0 1 1* 0 0 1 1 1 7* n/a n/a n/a n/a n/a n/a n/a n/a o lo Read Config Regs x x x x x x x * 0 1 0 1* 0 0 1 0 1 5* n/a n/a n/a n/a n/a n/a n/a n/a g y In Read CAN Error x x x x x x x * 0 1 1 1* 0 0 0 1 1 3* n/a n/a n/a n/a n/a n/a n/a n/a c. Read PWM Config x x x x x x x * 1 0 0 1* 0 0 1 1 0 6* n/a n/a n/a n/a n/a n/a n/a n/a Read User Mem (bank1) x x x x x x x * 1 0 1 1* 0 1 0 0 0 8* n/a n/a n/a n/a n/a n/a n/a n/a Read User Mem (bank 2) x x x x x x x * 1 1 0 1* 0 1 0 0 0 8* n/a n/a n/a n/a n/a n/a n/a n/a Output Messages (from MCP2502X/5X) Standard ID Data Bytes 1 9 8 7 6 5 4 3 2 1 0 R I 0 T D DLC R E Read A/D Regs x x x x x x x * 0 0 0 0 0 1 0 0 0 8 IOINTFL GPIO AN0H AN1H AN10L AN2H AN3H AN32L Read Control Regs x x x x x x x * 0 0 1 0 0 0 1 1 1 7 ADCON0 ADCON1 OPTREG OPTREG STCON IOINTEN IOINTPO n/a Read Config Regs x x x x x x x * 0 1 0 0 0 0 1 0 1 5 DDR GPIO CNF1 CNF2 CNF3 n/a n/a n/a Read CAN Error x x x x x x x * 0 1 1 0 0 0 0 1 1 3 EFLG TEC REC n/a n/a n/a n/a n/a Read PWM Config x x x x x x x * 1 0 0 0 0 0 1 1 0 6 PR1 PR2 T1CON T2CON PWM1DC PWM2DC n/a n/a Read User Mem (bank1) x x x x x x x * 1 0 1 0 0 1 0 0 0 8 USERID0 USERID1 USERID2 USERID3 USERID4 USERID5 USERID6 USERID7 Read User Mem (bank 2) x x x x x x x * 1 1 0 0 0 1 0 0 0 8 USERID8 USERID9 USERID1 USERID1 USERID1 USERID1 USERID1 USERID1 Input Messages** (to MCP2502X/5X) Standard ID Data Bytes 1 9 8 7 6 5 4 3 2 1 0 R I M 0 T D DLC R E C Write Register x x x x x x x x 0 0 0 0 0 0 0 1 1 3 addr mask value n/a n/a n/a n/a n/a P Write TX Message ID 0 x x x x x x x x 0 0 1 0 0 0 1 0 0 4 TX0SIDH TX0SIDL TX0EID8 TX0EID0 n/a n/a n/a n/a 2 Write TX Message ID 1 x x x x x x x x 0 1 0 0 0 0 1 0 0 4 TX1SIDH TX1SIDL TX1EID8 TX1EID0 n/a n/a n/a n/a 5 Write TX Message ID 2 x x x x x x x x 0 1 1 0 0 0 1 0 0 4 TX2SIDH TX2SIDL TX2EID8 TX2EID0 n/a n/a n/a n/a D Write I/O Configuration x x x x x x x x 1 0 0 0 0 0 1 0 1 5 IOINTEN IOINTPO DDR OPTREG ADCON1 n/a n/a n/a 0 S 2 Write RX Mask x x x x x x x x 1 0 1 0 0 0 1 0 0 4 RXMSIDH RXMSIDL RXMEID8 RXMEID0 n/a n/a n/a n/a 2 1 66 Write RX Filter0 x x x x x x x x 1 1 0 0 0 0 1 0 0 4 RXF0SID RXF0SID RXF0EID RXF0EID n/a n/a n/a n/a X 4 C Write RX Filter1 x x x x x x x x 1 1 1 0 0 0 1 0 0 4 RXF1SID RXF1SID RXF1EID RXF1EID n/a n/a n/a n/a -pa * If using non-RTR messages for information request messages (IRM), the RTR bit = 0, DLC bit field = 0, and bit 3 of the IRM ID = 1. Also, bit 3 of the output message ID = 0. /5 g e 25 Iofu utpsiuntg m ReTsRsa mgee s=s ax g (edso fno’rt cIRaMres)., the RTR bit = 1, DLC bit field = number of bytes in corresponding output message, and bit three of the IRM ID = x (don’t care), also, bit 3 of the X **User-defined IRM IDs must be different from input message IDs to avoid message contention between the corresponding output message and the input message.

D TABLE 4-3: COMMAND MESSAGES (EXTENDED IDENTIFIER) M S 216 Information Request Messages (to MCP2502X/5X) C 64 Standard ID Extended ID Data Bytes C P -p 1 9 8 76 5 4 3 2 1 0 RI DLC 11 RXBEID8 RXBEID0 ag 0 T D 76 (8 bits) (8 bits) 2 e 2 RE 5 6 Read A/D Regs x x x x x x x x x x x 1 11000 8* xx xxxx xxxx xxxx *000 n/a n/a n/a n/a n/a n/a n/a n/a 0 Read Control Regs x x x x x x x x x x x 1 10111 7* xx xxxx xxxx xxxx *001 n/a n/a n/a n/a n/a n/a n/a n/a 2 Read Config Regs x x x x x x x x x x x 1 10101 5* xx xxxx xxxx xxxx *010 n/a n/a n/a n/a n/a n/a n/a n/a X Read CAN Error x x x x x x x x x x x 1 10011 3* xx xxxx xxxx xxxx *011 n/a n/a n/a n/a n/a n/a n/a n/a / Read PWM Config x x x x x x x x x x x 1 10110 6* xx xxxx xxxx xxxx *100 n/a n/a n/a n/a n/a n/a n/a n/a 5 Read User Mem x x x x x x x x x x x 1 11000 8* xx xxxx xxxx xxxx *101 n/a n/a n/a n/a n/a n/a n/a n/a X Read User Mem x x x x x x x x x x x 1 11000 8* xx xxxx xxxx xxxx *110 n/a n/a n/a n/a n/a n/a n/a n/a Read Register x x x x x x x x x x x 1 10000 1* xx addr xxxx *111 n/a n/a n/a n/a n/a n/a n/a n/a Output Messages (from MCP2502X/5X) Standard ID Extended ID Data Bytes 1 9 8 7 6 5 4 3 2 1 0 R I DLC 11 RXBEID8 RXBEID0 0 T D 76 (8 bits) (8 bits) R E Read A/D Regs x x x x x x x x x x x 0 11000 8 x x xxxx xxxx xxxx *000 IOINTFL GPIO AN0H AN1H AN10L AN2H AN3H AN32L Read Control Regs x x x x x x x x x x x 0 10111 7 x x xxxx xxxx xxxx *001 ADCON0 ADCON1 OPTREG OPTREG STCON IOINTEN IOINTPO n/a Read Config Regs x x x x x x x x x x x 0 10101 5 x x xxxx xxxx xxxx *010 DDR GPIO CNF1 CNF2 CNF3 n/a n/a n/a Read CAN Error x x x x x x x x x x x 0 10011 3 x x xxxx xxxx xxxx *011 EFLG TEC REC n/a n/a n/a n/a n/a Read PWM Config x x x x x x x x x x x 0 10110 6 x x xxxx xxxx xxxx *100 PR1 PR2 T1CON T2CON PWM1D PWM2D n/a n/a Read User Mem x x x x x x x x x x x 0 11000 8 x x xxxx xxxx xxxx *101 USERID0 USERID1 USERID2 USERID3 USERID4 USERID5 USERID6 USERID7 Read User Mem x x x x x x x x x x x 0 11000 8 x x xxxx xxxx xxxx *110 USERID8 USERID9 USERID1 USERID1 USERID1 USERID1 USERID1 USERID1 Read Register x x x x x x x x x x x 0 10000 1 x x addr xxxx *111 value n/a n/a n/a n/a n/a n/a n/a Input Messages (to MCP2502X/5X) Standard ID Extended ID Data Bytes 1 9 8 7 6 5 4 3 2 1 0 R I DLC 11 RXBEID8 RXBEID0  2 0 T D 76 (8 bits) (8 bits) 0 0 R E 3 M Write Register x x x x x x x x x x x 0 10011 3 x x xxxx xxxx xxxx x000 addr mask value n/a n/a n/a n/a n/a ic ro Write TX Message x x x x x x x x x x x 0 10100 4 x x xxxx xxxx xxxx x001 TX0SIDH TX0SIDL TX0EID8 TX0EID0 n/a n/a n/a n/a ch Write TX Message x x x x x x x x x x x 0 10100 4 x x xxxx xxxx xxxx x010 TX1SIDH TX1SIDL TX1EID8 TX1EID0 n/a n/a n/a n/a ip T Write TX Message x x x x x x x x x x x 0 10100 4 x x xxxx xxxx xxxx x011 TX2SIDH TX2SIDL TX2EID8 TX2EID0 n/a n/a n/a n/a ec Write I/O Configura- x x x x x x x x x x x 0 10101 5 x x xxxx xxxx xxxx x100 IOINTEN IOINTPO DDR OPTREG ADCON1 n/a n/a n/a h n Write RX Mask x x x x x x x x x x x 0 10100 4 x x xxxx xxxx xxxx x101 RXM- RXMSIDL RXMEID8 RXMEID0 n/a n/a n/a n/a o lo Write RX Filter0 x x x x x x x x x x x 0 10100 4 x x xxxx xxxx xxxx x110 RXF0SID RXF0SID RXF0EID RXF0EID n/a n/a n/a n/a g y In Write RX Filter1 x x x x x x x x x x x 0 10100 4 x x xxxx xxxx xxxx x111 RXF1SID RXF1SID RXF1EID RXF1EID n/a n/a n/a n/a c * If using non-RTR messages for information request messages (IRM), the RTR bit = 0, DLC bit field = 0, and bit 3 of the IRM ID = 1. Also, bit 3 of the output message ID = 0. . If using RTR messages for IRMs, the RTR bit = 1, DLC bit field = number of bytes in corresponding output message, and bit three of the IRM ID = x (don’t care), also, bit 3 of the output message = x (don’t care). **User-defined IRM IDs must be different from input message IDs to avoid message contention between the corresponding output message and the input message.

MCP2502X/5X 4.5 Automatic Transmission A hysteresis example: • The user sets the upper-eight bits of the 10-bit The MCP2502X/5X can automatically initiate four compare register (ADCMP0H). The lower-two bits different message types to indicate the following of the compare register are not configurable by situations: the user and are forced to either b’11’ or b’00’ • Edge detected on a digital input (TXID2). depending on the polarity of the compare • Threshold exceeded on an analog input (TXID2). threshold (i.e., transmit is triggered above or • Error condition (Read Error output message). below the compare value via the IOINTPO register). • Scheduled transmissions (TXID0). • The user sets the polarity of the compare The buffers have an implied transmit priority, where threshold (IOINTPO). In this example, the buffer 2 is the highest and buffer 0 is the lowest. threshold is set for triggering a message on an Therefore, multiple message buffers can be requested A/D > compare register. The two LSb’s are forced for transmission and each one will be sent in order of to b’11’. priority. • When the A/D conversion exceeds the compare 4.5.1 DIGITAL INPUT EDGE DETECTION register (b’nnnn nnnn 11’), an automatic transmission will occur once. Each GPIO pin configured as a digital input can be • In order for the automatic transmission to occur individually configured to automatically transmit a again, the A/D value must first drop below the message when a defined edge occurs, as explained in compare register b’nnnn nnnn 00’ and then the GPIO module section. When transmitting this back above the compare register message, the MCP2502X/5X uses TXID2. The DLC is b’nnnn nnnn 11’. set to two and the first two bytes of the Read A/D registers (IOINTFL and GPIO) are sent. FIGURE 4-1: HYSTERESIS 4.5.2 ANALOG INPUT THRESHOLD FUNCTION DETECTION Set to Trigger when A/D>Compare Register Each GPIO pin that has been configured as an analog input can be individually configured to automatically LSbs = b’1 1’ transmit a message when a threshold is exceeded as described in the Analog-to-Digital Converter Module LSbs = b’00’ section. The MCP2502X/5X sends TXID2 when A/D above compare, A/D above compare, transmitting this message. The DLC is set to eight and Message sent Message sent the eight bytes of the ‘Read A/D Registers’ are sent. A/D below compare, Reset Note: The GPIO register that is sent with the message (data byte 2) can be ignored if Set to Trigger when A/D<Compare Register there are no digital inputs enabled for LSbs = b’11’ change-of-state, as it contains no useful information for the Analog Input Threshold LSbs = b’00’ Detect function. A/D above compare, 4.5.2.1 Hysteresis Function Reset This function is automatic and will insure that an analog A/D below compare, Message sent value that is on the compare edge (i.e., toggling LSb) A/D below compare, Message sent does not fill the CAN bus with continuous A/D message transmissions. 4.5.3 ERROR CONDITION The hysteresis uses the two LSb’s of the compare The MCP2502X/5X can be configured to automatically register. These two bits are forced and are not transmit a message whenever one or more of the configurable by the user. They will be forced to either following error conditions occur: b’00’ or b’11’, depending on the compare polarity. If configured for A/D result > compare register, the • Receiver has entered error-warning state automatic transmission will occur when the A/D value • Receiver has entered error-passive state is greater than or equal to b’nnnn nnnn 11’ and • Transmitter has entered error-warning state reset when less than or equal to b’nnnn nnnn 00’. • Transmitter has entered error-passive state The opposite conditions must occur if the compare • A Receive buffer has overflowed polarity is set for A/D result < compare register.  2003 Microchip Technology Inc. DS21664C-page 27

MCP2502X/5X If the Error Condition message is enabled (OPTREG2.TXONE = 1) and one of the above Scheduled Transmission conditions occur, the MCP2502X/5X sends TXID1 = STBF1:STBF0(STM3:STM0) identifier with output message Read CAN Error States data field (three data bytes). Message Type - The message sent for scheduled 4.5.4 SCHEDULED TRANSMISSIONS transmissions consists of either TXID0 with zero data bytes or TXID0 with eight data bytes containing the The MCP2502X/5X has the capability of sending Read A/D Regs message, depending on STMS bit in scheduled transmissions (On Bus message), if the STCON register. enabled. Note: The actual scheduled transmission The scheduled transmission control register (STCON) intervals may vary slightly due to the enables and configures the occurrence of the internal event que of the control module. scheduled message. Setting the STEN bit in the STCON register enables the scheduled message. The STBF1:STBF0 and STM3:STM0 bits allow a scheduled transmission to be initiated from a minimum of 256µs to a maximum of 16.8 seconds (using a 16MHz FOSC) and the following equation: REGISTER 4-1: STCON - SCHEDULED TRANSMISSION CONTROL REGISTER R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 STEN STMS STBF1 STBF0 STM3 STM2 STM1 STM0 bit 7 bit 0 bit 7 STEN: Scheduled Transmission Enable bits 1 = Enabled 0 = Disabled bit 6 STMS: Scheduled Transmission Message Select 1 = Sends Transmit ID 0 (TXID0) with the “Read A/D Regs” data (DLC = 8) 0 = Sends Transmit ID 0 (TXID0) with no data (DLC = 0) bit 5-4 STBF1:STBF0: Base Transmission Frequency bits 00 = 4096TOSC 01 = 16•(4096TOSC) 10 = 256•(4096TOSC) 10 = 4096•(4096TOSC) (e.g., STBF1:STBF0 => 00 => 256µs for a 16MHz FOSC) bit 3-0 STM3:STM0: Scheduled Transmission Multiplier bits 0000 = 1 0001 = 2 - - 1110 = 15 1111 = 16 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS21664C-page 28  2003 Microchip Technology Inc.

MCP2502X/5X TABLE 4-4: REGISTERS ASSOCIATED WITH THE CAN MODULE Value on Value on Addr Name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 POR RST 0Bh CNF1 SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 xxxx xxxx uuuu uuuu 0Ch CNF2 BTLM- SAM PHSEG12 PHSEG11 PHSEG10 PRSEG2 PRSEG1 PRSEG0 xxxx xxxx uuuu uuuu ODE 0Dh CNF3 — WAKF — — — PHSEG22 PHSEG21 PHSEG20 -x-- xxxx -u-- uuuu 10h STCON STEM STMS STBF1 STBF0 STM3 STM2 STM1 STM0 0xxx xxxx 0uuu uuuu 11h OPTREG2 CAEN ERRE TXONE SLPEN MTYPE PDEFEN PUSLP PUNRM 0000 0000 uuuu uuuu 14h RXMSIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx uuuu uuuu 15h RXMSIDL SID2 SID1 SID0 — — — EID17 EID16 xxx- --xx uuu- --uu 16h RXMEID8 EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx uuuu uuuu 17h RXMEID0 EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx uuuu uuuu 18h RXF0SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx uuuu uuuu 19h RXF0SIDL SID2 SID1 SID0 — — — EID17 EID16 xxx- --xx uuu- --uu 1Ah RXF0EID8 EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx uuuu uuuu 1Bh RXF0EID0 EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx uuuu uuuu 1Ch RXF1SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx uuuu uuuu 1Dh RXF1SIDL SID2 SID1 SID0 — — — EID17 EID16 xxx- --xx uuu- --uu 1Eh RXF1EID8 EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx uuuu uuuu 1Fh RXF1EID0 EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx uuuu uuuu 20h TXB0SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx uuuu uuuu 21h TXB0SIDL SID2 SID1 SID0 — EXIDE — EID17 EID16 xxx- x-xx uuu- u-uu 22h TXB0EID8 EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx uuuu uuuu 23h TXB0EID0 EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx uuuu uuuu 24h TXB1SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx uuuu uuuu 25h TXB1SIDL SID2 SID1 SID0 — EXIDE — EID17 EID16 xxx- x-xx uuu- u-uu 26h TXB1EID8 EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx uuuu uuuu 27h TXB1EID0 EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx uuuu uuuu 28h TXB2SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx uuuu uuuu 29h TXB2SIDL SID2 SID1 SID0 — EXIDE — EID17 EID16 xxx- x-xx uuu- u-uu 2Ah TXB2EID8 EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx uuuu uuuu 2Bh TXB2EID0 EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx uuuu uuuu  2003 Microchip Technology Inc. DS21664C-page 29

MCP2502X/5X NOTES: DS21664C-page 30  2003 Microchip Technology Inc.

MCP2502X/5X 5.0 GPIO MODULE 5.2 Digital Input Edge Detection All GPIO pins have a digital input edge detection 5.1 Description feature that will automatically transmit a message when an edge with the proper polarity occurs on any of the The MCP2502X/5X has eight general-purpose input/ digital inputs. Only pins configured as inputs and output pins (GP0 to GP7), collectively labeled GPIO. All enabled for this function via control register IOINTPO GPIO port pins have TTL input levels and full CMOS will perform this operation. output drivers, with the exception of GP7, which is input only. Pins GP6:GP0 can be individually configured as Note: Refer to Section7.4 “A/D Threshold input or output via the GPDDR register. Detection” for information regarding A/D channels. Note: The GPDDR register controls the direction Three control registers are associated with this of the GPIO pins, even when they are function. An enable pin for each GPIO pin resides in the being used as analog inputs. The user IOINTEN register. When a bit is set to a '1', the must ensure that the bits in the GPDDR corresponding GPIO pin is enabled to generate a register are maintained set (input) when transmit-on-change message (TXID2) when an edge of using them as analog inputs. specified polarity occurs. Each of the GPIO pins has a weak internal pull-up resistor. A single control bit (OPTREG.GPPU) can turn The digital edge detection function on a GPIO pin on/off all the pull-ups. The weak pull-up is automatically configured as a digital input is edge triggered. A rising- turned off when the port pin is configured as an output. edge will generate a transmission if the corresponding bit in the IOINTPO register is set. A falling-edge will The pull-ups are disabled during a Power-on Reset. generate a transmission if the bit is cleared. When a All pins are multiplexed with an alternate function, valid edge appears on the enabled GPIO pin, CAN including analog-to-digital conversion on up to four of message TXID2 is initiated. the GPIO pins, analog VREF inputs up to two pins, The edge-detection function on any given GPIO pin PWM outputs up to two pins, clock-out function and (configured as a digital input) can wake up the external reset. The operation of each pin is selected by processor from SLEEP if the corresponding interrupt clearing, or setting, control bits in various control registers. GPIO pin functions are summarized in enable bit in the IOINTEN register was set prior to Table5-1. going into SLEEP mode. If a wake-up from SLEEP is caused in this manner, the device will immediately initiate a transmit message (TXID2). TABLE 5-1: GPIO FUNCTIONS Bit Name Function # GP0/AN0 bit0 I/O or analog input GP1/AN1 bit1 I/O or analog input GP2/AN2/PWM2 bit2 I/O, analog input or PWM out GP3/AN3/PWM3 bit3 I/O, analog input or PWM out GP4/VREF- bit4 I/O or analog voltage reference GP5/VREF+ bit5 I/O or analog voltage reference GP6/CLKOUT bit6 I/O or Clock output GP7/nRST/VPP bit7 Input, external reset input or programming voltage input  2003 Microchip Technology Inc. DS21664C-page 31

MCP2502X/5X REGISTER 5-1: GPDDR - DATA DIRECTION REGISTER U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — DDR6 DDR5 DDR4 DDR3 DDR2 DDR1 DDR0 bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6-0 DDR6:DDR0: Data Direction Register* bits 1 = corresponding GPIO pin is configured as an input 0 = corresponding GPIO pin is configured as an output * must bet set if corresponding analog channel is enabled (see ADCON1) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 5-2: GPLAT - GPIO OUTPUT REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — GP6 GP5 GP4 GP3 GP2 GP1 GP0 bit 7 bit 0 bit 7 Unimplemented: Read as '0’ bit 6-0 GP6:GP0: GPIO Bits 1 = corresponding GPIO pin output latch is a ‘1’ 0 = corresponding GPIO pin output latch is a ‘0’ Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 5-3: IOINTEN REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GP7TXC GP6TXC GP5TXC GP4TXC GP3TXC GP2TXC GP1TXC GP0TXC bit 7 bit 0 bit 7-0 GP7TXC:GP0TXC: Transmit-on-change Enable bits 1 = Enable Transmit-On-Change/Compare For Corresponding GPIO/AN Channel 0 = Disable Transmit-On-Change/Compare For Corresponding GPIO/AN Channel Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS21664C-page 32  2003 Microchip Technology Inc.

MCP2502X/5X REGISTER 5-4: IOINTPO REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GP7POL GP6POL GP5POL GP4POL GP3POL GP2POL GP1POL GP0POL bit 7 bit 0 bit 7-0 GP7POL:GP0POL: Transmit-on-change Polarity bits 1 = Digital Inputs: Low-to-High Transition On Corresponding GPIO Input Pin Generates a transmit message Analog Inputs: A/D result above compare value generates a transmit message 0 = Digital Inputs: High-to-Low Transition On Corresponding GPIO Input Generates transmit message Analog Inputs: A/D result below compare value generates a transmit message Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 5-5: IOINTFL REGISTER R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 GP7TXF GP6TXF GP5TXF GP4TXF GP3TXF GP2TXF GP1TXF GP0TXF bit 7 bit 0 bit 7-0 GP7TXF:GP0TXF: Transmit-on-change Polarity bits 1 = Digital Inputs: A valid edge has occurred on the digital input Analog Inputs: A/D result does exceed the compare threshold 0 = Digital Inputs: A valid edge has not occurred on the digital input Analog Inputs: A/D result does not exceed the compare threshold Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003 Microchip Technology Inc. DS21664C-page 33

MCP2502X/5X REGISTER 5-6: OPTREG1 REGISTER R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-0 R/W-0 R/W-0 GPPU CLKEN CLKPS1 CLKPS0 — CMREQ AQT1 AQT0 bit 7 bit 0 bit 7 GPPU: Weak pull-up enabled 1 = Weak pull-ups disabled 0 = Weak pull-ups enabled (GP7:GP0) bit 6 CLKEN: 1 = Clock Out Function disabled 0 = Clock Out Function enabled bit 5-4 CLKPS1:CLKPS0: CLKOUT Prescaler bits 00 = FOSC/1 01 = FOSC/2 10 = FOSC/4 11 = FOSC/8 bit 3 Reserved: bit 2 CMREQ: Requests mode of operation (allows mode changes via the CAN bus) 1 = Requests Listen-only mode 0 = Requests Normal mode * * CMREQ must be cleared as default to avoid device entering Listen-only mode on first “Input” message. bit 1-0 AQT1:AQT0: Analog Acquisition Time bits 00 = 64TOSC 01 = 2•(64TOSC) 10 = 4•(64TOSC) 11 = 8•(64TOSC) (e.g., AQT1:AQT0 => 00 => 2.56µs for a 25MHz FOSC) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS21664C-page 34  2003 Microchip Technology Inc.

MCP2502X/5X REGISTER 5-7: OPTREG2 REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CAEN ERREN TXONEN SLPEN MTYPE PDEFEN PUSLP PUNRM bit 7 bit 0 bit 7 CAEN: Command Acknowledge Enable bit 1 = Enables the command acknowledge message (TXID1) 0 = Enables the receive overflow message (TXID1) bit 6 ERREN: Error Recovery Enable bit 1 = MCP2502X/5X will recover into Listen-only mode from bus off 0 = MCP2502X/5X will recover into Normal mode from bus-off bit 5 TXONEN: Transmit on Error Condition bit(REC or TEC) 1 = Enable, will send message if error counter(s) go high enough 0 = Disable, will NOT send message regardless of error counter values bit 4 SLPEN: Low power SLEEP mode enable/disable 1 = Device will enter Sleep if bus is idle for at least 1408 bit times 0 = SLEEP mode is disabled bit 3 MTYPE: Determines if information request messages use RTR or not 1 = RTR is NOT used for IRM (Data Frame) 0 = RTR is used for IRM (Remote Frame) bit 2 PDEFEN: Enables PWM outputs to return to POR default values when CAN bus communication is lost 1 = Enables PWM output default values 0 = Disables PWM output default values bit 1 PUSLP: Allows device to enter SLEEP while in Listen-only mode during power-up sequence 1 = Enables SLEEP when in Listen-only mode during power-up sequence 0 = Disables SLEEP when in Listen-only mode during power-up sequence bit 0 PUNRM: Enters Normal mode after completing self-configuration during power-up sequence 1 = Enters “Normal” mode after completing self-configuration during power-up sequence 0 = Enables “Listen-only” mode after completing self-configuration during power-up sequence and waits for an error-free message before switching to Normal mode Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH GPIO MODULE Value on Value on Addr Name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 POR RST Bank 0 34h GPDDR — DDR6 DDR5 DDR4 DDR3 DDR2 DDR1 DDR0 -111 1111 -111 1111 00h IOINTEN GP7TXC GP6TXC GP5TXC GP4TXC GP3TXC GP2TXC GP1TXC GP0TXC 0000 0000 0000 0000 01h IOINTPO GP7POL GP6POL GP5POL GP4POL GP3POL GP2POL GP1POL GP0POL 0000 0000 0000 0000 04h OPTREG1 GPPU CLKEN CLKPS1 CLKPS0 — CMREQ AQT1 AQT0 0000 ---- 0000 ---- Legend: x = unknown, U = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used by module.  2003 Microchip Technology Inc. DS21664C-page 35

MCP2502X/5X NOTES: DS21664C-page 36  2003 Microchip Technology Inc.

MCP2502X/5X 6.0 PWM MODULE reconfigure to their default conditions. This includes the PWM module itself being disabled and the GPIO being forced low, high or tri-state. 6.1 Description There are two Pulse Width Modulation (PWM) modules FIGURE 6-2: PWM OUTPUT (PWM1 and PWM2) that generate up to a 10-bit resolution output signal on GP2 and GP3, respectively. Period Each of these outputs can be separately enabled, with each having its own associated timer, duty cycle and period registers for controlling the PWM output shape. Duty Cycle TMRn = PRn Each PWM module contains a set of master/slave duty cycle registers, providing up to a 10-bit resolution PWM TMRn=Duty Cycle TMRn = PRn output. Figure6-1 shows a simplified block diagram of the PWM module. A PWM output has a time base (period) and a time that the output stays high (duty 6.2 PWM Timer Modules cycle), as shown in Figure6-2. The frequency of the PWM is the inverse of the period (1/period). There are two 8-bit timers supporting the two PWM outputs. Both timers have a prescaler only. The timers At power-on, the PWM outputs are not enabled until are readable and writable and are cleared on any after the self-configuration sequence has been device reset or when the timer is turned off. completed (i.e., all SRAM registers have been loaded with their default values) to prevent invalid signals from The input clock (FOSC/4) has a prescale option of 1:1, occurring on the PWM outputs. 1:4 or 1:16, selected by control bits TnCKPS[1:0] in register TnCON<5:4> (where n corresponds to the FIGURE 6-1: SIMPLIFIED BLOCK appropriate timer). DIAGRAM Each timer module has an 8-bit period register, PRn. Duty cycle PRn is a readable and writable register. The timer TnCON registers (2 LSB) module increments from 00h until it matches PRn and then resets to 00h on the next increment cycle. The PWMnDCH PRn register is set when the device is reset. Each timer can be shut off by clearing control bit TMRnON (TnCON<7>). PWMnDBH 6.2.1 TIMER MODULE PRESCALER The prescaler counters are cleared when a write to the Comparator R Q TnCON or TMRn register or any device reset (RST GP<Y> (PWMn) reset or Power-on reset) occurs. S Note DDR<Y> TMRn 1 6.3 PWM Modules Each PWM module contains a set of master/slave duty Comparator cycle registers, providing up to a 10-bit resolution PWM output. Figure6-2 shows a simplified block diagram of the PWM module. Prn 6.3.1 PWM PERIOD Note1: 8-bit timer is concatenated with 2-bit internal The PWM period is specified by writing to the PRn Q clock or 2 bits of the prescaler to create register. The PWM period can be calculated using the 10-bit time base following formula: PWM period = [(PR )+1]*4T *(TMRn prescale value) The PWM outputs can be forced to their default POR n OSC conditions if CAN bus communication is lost and is PWM frequency = 1⁄(PWM period) enabled via OPTREG2.PDEFEN. The system designer must implement a hand-shaking protocol, such that the When TMRn is equal to PRn, the following two events MCP2505X will receive a valid message into one of the occur on the next cycle: receive buffers before four successive scheduled • TMRn is cleared transmissions occur. If a valid message is not received, • The PWM duty cycle is latched from PWMnDCH the PWM outputs GP2 and GP3 will automatically into PWMnDBH  2003 Microchip Technology Inc. DS21664C-page 37

MCP2502X/5X 6.3.2 PWM DUTY CYCLE When the PWMnDBH and 2-bit latch match TMRn concatenated with an internal 2-bit Q clock or 2 bits of The PWM duty cycle is specified by writing to the the TMRn prescaler, the PWM output pin is cleared. PWMnDCH and TnCON registers. Up to 10-bit resolution is available. The PWMnDCH contains the Maximum PWM resolution (bits) for a given PWM eight MSb’s, while the TnCON register contains the two frequency is equal to: LSb’s. This 10-bit value is represented by PWM1DCH:T1CON<1:0> for PWM Module 1 and log((FOSC)⁄(Fpwm))⁄(log(2)bits) PWM2DCH:T2CON<1:0> for PWM Module 2. The following equation is used to calculate the PMW Note: If the PWM duty cycle value is longer than duty cycle: the PWM period (PWM duty cycle PWMDC= (PWMnDC)*T *TMRn (prescale) =100%), the PWM output pin will not be OSC cleared. In order to achieve higher resolution, the PWM PWMnDCH can be written to at any time, but the duty frequency must be decreased. In order to achieve cycle value is not latched into PWMnDBH until after a higher PWM frequency, the resolution must be match between PRn and TMRn occurs (i.e., the period decreased. Table6-1 lists example PWM frequencies is complete). and resolutions for FOSC = 20MHz. TMRn prescaler The PWMnDBH register and 2-bit internal latch are and PRn values are also shown. used to double-buffer the PWM duty cycle. This double-buffering is essential for glitchless PWM operation. TABLE 6-1: PWM FREQUENCIES AND RESOLUTIONS AT 20MHZ PWM Frequency 1.22kHz 4.88kHz 19.53kHz 78.12kHz 156.30kHz 208.30kHz Timer Prescaler (1, 4, 16) 16 4 1 1 1 1 PRn Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 Maximum Resolution (bits) 10 10 10 8 7 5.5 REGISTER 6-1: PWM1 DUTY CYCLE REGISTER MSB (PWM1DCH) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x DC1B9 DC1B8 DC1B7 DC1B6 DC1B5 DC1B4 DC1B3 DC1B2 bit 7 bit 0 bit 7-0 DC1B9:DC1B2: Most Significant PWM0 Duty Cycle bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 6-2: PWM2 DUTY CYCLE REGISTER MSB (PWM2DCH) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x DC2B9 DC2B8 DC2B7 DC2B6 DC2B5 DC2B4 DC2B3 DC2B2 bit 7 bit 0 bit 7-0 DC2B9:DC2B2: Most Significant PWM2 Duty Cycle bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS21664C-page 38  2003 Microchip Technology Inc.

MCP2502X/5X REGISTER 6-3: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-x R/W-x TMR1ON — T1CKPS1 T1CKPS0 — — DC1B1 DC1B0 bit 7 bit 0 bit 7 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Disables Timer1 bit 6 Unimplemented: Read as '0' bit 5-4 T1CKPS1:T1CKPS0: Timer1 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 bit 3-2 Unimplemented: Read as '0' bit 1-0 DC1B1:DC1B0: Least Significant PWM1 Duty Cycle bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 6-4: T2CON: TIMER2 CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-x R/W-x TMR2ON — T2CKPS1 T2CKPS0 — — DC2B1 DC2B0 bit 7 bit 0 bit 7 TMR2ON: Timer2 On bit 1 = Enables Timer2 0 = Disables Timer2 bit 6 Unimplemented: Read as '0' bit 5-4 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 bit 3-2 Unimplemented: Read as '0' bit 1-0 DC2B1:DC2B0: Least Significant PWM2 Duty Cycle bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003 Microchip Technology Inc. DS21664C-page 39

MCP2502X/5X REGISTER 6-5: PR1: PERIOD REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x PR1B7 PR1B6 PR1B5 PR1B4 PR1B3 PR1B2 PR1B1 PR1B0 bit 7 bit 0 bit 7-0 PR1B7:PR1B0: PWM1 Period Register bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 6-6: PR2: PERIOD REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x PR2B7 PR2B6 PR2B5 PR2B4 PR2B3 PR2B2 PR2B1 PR2B0 bit 7 bit 0 bit 7-0 PR2B7:PR2B0: PWM2 Period Register bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown TABLE 6-2: REGISTERS ASSOCIATED WITH THE PWM MODULE Value on Value on Addr Name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 POR RST 34h GPDDR — DDR6 DDR5 DDR4 DDR3 DDR2 DDR1 DDR0 -111 1111 -111 1111 05h T1CON TMR1ON — T1CKPS1 T1CKPS0 — — DC1B1 DC1B0 0-00 --xx 0-00 --uu 06h T2CON TMR2ON — T2CKPS1 T2CKPS0 — — DC2B1 DC2B0 0-00 --xx 0-00 --uu 07h PR1 Timer 1 Module’s Period Register 1111 1111 1111 1111 08h PR2 Timer 2 Module’s Period Register 1111 1111 1111 1111 09h PWM1DCH DC1B9 DC1B8 DC1B7 DC1B6 DC1B5 DC1B4 DC1B3 DC1B2 xxxx xxxx uuuu uuuu 0Ah PWM2DCH DC2B9 DC2B8 DC2B7 DC2B6 DC2B5 DC2B4 DC2B3 DC2B2 xxxx xxxx uuuu uuuu Legend: x = unknown, U = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used by module. DS21664C-page 40  2003 Microchip Technology Inc.

MCP2502X/5X 7.0 ANALOG-TO-DIGITAL 7.3 A/D Conversion Modes CONVERTER (A/D) MODULE There are two modes of conversion that can be individually selected for each analog channel that has 7.1 Description been enabled. These are auto-conversion and conversion-on-request. The Analog-to-Digital (A/D) module is a four-channel, 10-bit successive approximation type of A/D. The A/D 7.3.1 AUTO-CONVERSION MODE allows conversion of an analog input signal to a If the Auto-conversion mode is selected (STCON), an corresponding 10-bit number. The four channels are A/D conversion is performed sequentially for each multiplexed on the GP[3:0] pins. The converter is channel that has been set to Analog Input mode and turned off/on via the ADCON0 register and each has been configured for Auto-conversion mode. channel is individually enabled via the ADCON1 control Conversion starts with AN0 and is immediately register. The VREF+ and VREF- sources are user- followed by AN1, etc. Once the conversion has selectable as internal or external. Each channel can be completed, the value is stored in the analog channel set to one of two conversion modes: registers for the respective channel. 1. Auto-conversion The rate of the auto-conversion is determined by a 2. Convert-on-request. timer and prescaler. The formula for determining conversion rates is: 7.2 A/D Module Registers (T )(1024)(Prescaler rate) OSC The A/D module itself has several registers. The registers are: Typical conversion rates with a 20MHz oscillator input • A/D Control Register 0 (ADCON0) are shown in Table7-1. • A/D Control Register 1 (ADCON1) TABLE 7-1: AUTO-CONVERSION RATES • Transmit-on-Change Register (IOINTEN) FOR GIVEN PRESCALE • Compare and Polarity Register (ADCMPnL) RATES AT 20MHZ • A/D Result Registers (ADRESnL, ADRESnH) Prescale Auto-Conversion The ADCON0 register controls the operation of the TOPS[2:0] Rate Rate A/D module, including auto-conversion rate and enable bit. The ADCON1 register enables the A/D function on 000 1:1 51µs port pins GP3:GP0, A/D conversion rate and selects 001 1:8 410µs the voltage reference source. The IOINTEN register’s 010 1:32 2ms four least significant bits enable/disable the transmit- 011 1:128 7ms on-change function. The ADCMPnL.ADPOL bit sets the polarity (above or below threshold) for the transmit- 100 1:512 26ms on-change function. 101 1:1024 52ms The result of an A/D conversion is made available to 110 1:2048 105ms the user within the data field of the Read A/D Registers 111 1:4096 210ms output message via the CAN bus. This message can be directly requested by another CAN node or be The timer is turned on if one of the GPnTXC bits are set automatically transmitted (TXIDO), as has been in the IOINTEN register and configured as analog described previously. input. Additionally, the individual channel results may be read The prescaler counter is cleared when the device is using the “Read Register” command as described in reset (RST reset or Power-on reset). Section4.3.1 “Information Request Messages” and as shown in Table3-2 by addressing the appropriate A/D result register (ADRESnL and ADRESnH). Note: The GPDDR register controls the direction of the GPIO pins, even when they are being used as analog inputs. The user must ensure that the bits in the GPDDR register are maintained set (input) when using them as analog inputs.  2003 Microchip Technology Inc. DS21664C-page 41

MCP2502X/5X 7.3.2 CONVERSION-ON-REQUEST 7.4 A/D Threshold Detection MODE Once an A/D auto-conversion has been completed, the If the Conversion-on-request mode is selected, the A/D channel result(s) can be compared to a value device performs an A/D conversion only after receiving stored in the associated A/D channel comparator a Read A/D Registers or Read Register Receive registers. message (IRM). In the case of the Read A/D Registers If the value in the analog channel result registers (i.e., command, all of the GPIO pins that have been AN0L and AN10H registers for analog channel 0) is configured as analog input channels will have an A/D lower or higher than the value in the A/D comparator conversion done before the data frame is sent. When a registers (as specified by a corresponding polarity bit), Read Register Receive message is initiated (extended a transmit-on-change message will be sent (TXID2). message format only), the A/D conversion is performed The threshold-detection function for all analog when the MSB of the analog channel is requested, with channels is bit-selectable. the MSB result being transferred. A subsequent read of the LSB will transmit the value latched when the MSB If the A/D channel has been configured for transmit-on- was requested (it is recommended that the Read A/D change mode, the MCP2505 will send a transmit Registers receive message is used to obtain complete message with the appropriate data. It is possible that analog channel values in one message). more than one A/D channel has a change-of-state condition. This does not pose a problem since all analog channel data is provided in the transmit message. REGISTER 7-1: A/D MODULE RESULT REGISTER MSB (ADRESNH) R-x R-x R-x R-x R-x R-x R-x R-x AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 bit 7 bit 0 bit 7-0 AD9:AD2: Most Significant A/D Result bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 7-2: A/D MODULE RESULT REGISTER LSB (ADRESNL) R-x R-x U-0 U-0 U-0 U-0 U-0 U-0 AD1 AD0 — — — — — — bit 7 bit 0 bit 7-6 AD1:AD0: Least significant A/D Result bits bit 5-0 Unimplemented: Reads as ‘0’ Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS21664C-page 42  2003 Microchip Technology Inc.

MCP2502X/5X REGISTER 7-3: A/D MODULE COMPARE REGISTER MSB (ADCMPNH) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x ANnCMP9 ANnCMP8 ANnCMP7 ANnCMP6 ANnCMP5 ANnCMP4 ANnCMP3 ANnCMP2 bit 7 bit 0 bit 7-0 ANnCMP9:ANnCMP2: Most Significant A/D Compare bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 7-4: A/D MODULE COMPARE REGISTER LSB (ADCMPNL) R/W-x R/W-x U-0 U-0 U-0 U-0 U-0 U-0 ANnCMP1 ANnCMP0 — — — — — — bit 7 bit 0 bit 7-6 ANnCMP1:ANnCMP0: Least Significant A/D Compare bits bit 5-0 Unimplemented: Reads as ‘0’ Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 7-5: ADCON0 REGISTER R/W-0 R/W-0 R/W-0 R/W-0 U-x U-0 U-x U-x ADON T0PS2 T0PS1 T0PS0 — — — — bit 7 bit 0 bit 7 ADON: A/D On Bit 1 = A/D converter module is operating 0 = A/D converter module is shut off and consumes no operating current bit 6-4 T0PS2:T0PS0: Timer0 Prescaler Rate Select bits (used for auto-conversions) 000 = 1:1 Prescaller Rate 001 = 1:8 Prescaller Rate 010 = 1:32 Prescaller Rate 011 = 1:128 Prescaller Rate 100 = 1:512 Prescaller Rate 101 = 1:1024 Prescaller Rate 110 = 1:2048 Prescaller Rate 111 = 1:4096 Prescaller Rate Formula: (TOSC)(1024) (Prescaler Rate) bit 3 Reserved bit 2 Unimplemented: Reads as ‘0’ bit 1-0 Reserved Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003 Microchip Technology Inc. DS21664C-page 43

MCP2502X/5X REGISTER 7-6: ADCON1 REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADCS1 ADCS0 VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 bit 7-6 ADCS1:ADCS0: A/D Conversion Select bits 00 = FOSC/2 01 = FOSC/8 10 = FOSC/32 11 = Reserved bit 5-4 VCFG1:VCFG0: Voltage Reference Configuration bits VCFG1:VCFG0 A/D VREF+ A/D VREF- 00 VDD VSS 01 External VREF+ VSS 10 VDD External VREF- 11 External VREF+ External VREF- bit 3-0 PCFG3:PCFG0: A/D Port Configuration Control bits* 1 = Corresponding GPIO pin configured as Digital I/O 0 = Corresponding GPIO pin configured as A/D Input * corresponding data direction bit (GPDDR register) must be set for each enabled analog channel. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS21664C-page 44  2003 Microchip Technology Inc.

MCP2502X/5X 7.5 Read A/D Registers Output Message When the MCP2502X/5X responds to a Read A/D Regs IRM with an OM, the analog values are contained in Register7-7, Register7-8 and Register7-9. REGISTER 7-7: A/D OM RESULT REGISTER (ANnH) R-x R-x R-x R-x R-x R-x R-x R-x ANnR9 ANnR8 ANnR7 ANnR6 ANnR5 ANnR4 ANnR3 ANnR2 bit 7 bit 0 bit 7-0 ANnR9:ANnR2: Bits 9-2 of channel ‘n’ results Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 7-8: A/D OM RESULT REGISTER (AN32L) R-x R-x U-x U-x R-x R-x U-x U-x AN3R.1 AN3R.0 — — AN2R.1 AN2R.0 — — bit 7 bit 0 bit 7-6 AN3R.1:AN3R.0: A/D Channel 3, bits 1:0 results bit 5-4 Unimplemented: Reads as ‘0’ bit 3-2 AN2R.1:AN2R.0: A/D Channel 2, bits 1:0 results bit 1-0 Unimplemented: Reads as ‘0’ Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003 Microchip Technology Inc. DS21664C-page 45

MCP2502X/5X REGISTER 7-9: A/D OM RESULT REGISTER (AN10L) R-x R-x U-x U-x R-x R-x U-x U-x AN1R.1 AN1R.0 — — AN0R.1 AN0R.0 — — bit 7 bit 0 bit 7-6 AN1R.1:AN1R.0: A/D Channel 1, bits 1:0 results bit 5-4 Unimplemented: Reads as ‘0’ bit 3-2 AN0R.1:AN0R.0: A/D Channel 0, bits 1:0 results bit 1-0 Unimplemented: Reads as ‘0’ Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown TABLE 7-2: REGISTERS ASSOCIATED WITH THE A/D MODULE Value on Value on Addr Name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 POR RST 1Eh GPPIN GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 0000 0000 0000 0000 34h GPDDR * — DDR6 DDR5 DDR4 DDR3 DDR2 DDR1 DDR0 -111 1111 -111 1111 00h IOINTEN GP7TXC GP6TXC GP5TXC GP4TXC GP3TXC GP2TXC GP1TXC GP0TXC 0000 0000 0000 0000 01h IOINTPO GP7POL GP6POL GP5POL GP4POL GP3POL GP2POL GP1POL GP0POL 0000 0000 0000 0000 0Eh ADCON0 ADON T0PS2 T0PS1 T0PS0 GO/DONE — CHS1 CHS0 0000 0-00 0000 0-00 0Fh ADCON1 ADCS1 ADCS0 VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 0000 0000 0000 0000 2Ch ADCMP3 AN3CM AN3CMP. AN3CMP. AN3CMP. AN3CMP.5 AN3CMP.4 AN3CMP. AN3CMP2 xxxx xxxx uuuu uuuu 2Dh ADCMP3 AN3CM AN3CMP. — — Reserved ADPOL xx-- ---- uu-- ---- 2Eh ADCMP2 AN2CM AN2CMP. AN2CMP. AN2CMP. AN2CMP.5 AN2CMP.4 AN2CMP. AN2CMP2 xxxx xxxx uuuu uuuu 2Fh ADCMP2 AN2CM AN2CMP. — — Reserved ADPOL xx-- ---- uu-- ---- 30h ADCMP1 AN1CM AN1CMP. AN1CMP. AN1CMP. AN1CMP.5 AN1CMP.4 AN1CMP. AN1CMP2 xxxx xxxx uuuu uuuu 31h ADCMP1 AN1CM AN1CMP. — — Reserved ADPOL xx-- ---- uu-- ---- 32h ADCMP0 AN0CM AN0CMP. AN0CMP. AN0CMP. AN0CMP.5 AN0CMP.4 AN0CMP. AN0CMP2 xxxx xxxx uuuu uuuu 33h ADCMP0 AN0CM AN0CMP. — — Reserved — xx-- ---- uu-- ---- 10h STCON STEM STMS STBF1 STBF0 STM3 STM2 STM1 STM0 0xxx xxxx 0uuu uuuu * The GPDDR register controls the direction of the GPIO pins, even when they are being used as analog inputs. The user must ensure that the bits in the GPDDR register are maintained set (input) when using them as analog inputs. DS21664C-page 46  2003 Microchip Technology Inc.

MCP2502X/5X 8.0 SPECIAL FEATURES OF THE FIGURE 8-2: EXTERNAL CLOCK INPUT MCP2502X/5X OPERATION 8.1 Description There are a number of special circuits in the Clock from OSC1 MCP2502X/5X that deal with the needs of real-time ext. System MCP2505X applications. These features are intended to maximize system reliability, minimize cost through elimination of Open OSC2 external components and provide power-saving operating modes. These are: • Oscillator selection • Reset 8.2 Configuration Bits - Power-on Reset (POR) - Power-up Timer (PWRT) The configuration bits can be either programmed (read - Oscillator Start-up Timer (OST) as ‘0’) or unprogrammed (read as ‘1’) to select various • SLEEP device configurations. These bits are mapped in program memory location 2007h. The configuration • In-Circuit Serial Programming register is actually beyond program memory space and Several oscillator options are offered to allow the belongs to the special test/configuration memory space device to fit the application. XT and HS modes allow (2000h-3FFFh) that can be accessed only during the device to support a wide range of crystal programming. frequencies while the LP crystal option saves power. Two timers are implemented to offer necessary delays 8.3 Oscillator Configurations on power-up. One is the Oscillator Start-up Timer Four different oscillator modes may be selected. The (OST), intended to keep the device in reset until the user can program two configuration bits crystal oscillator is stable. The other is the Power-up (F 1:F 0) in the CONFIG register to select one of Timer (PWRT), which provides a fixed delay of 72ms OSC OSC these modes: (nominal) on power-up only, designed to keep the part in reset while the power supply stabilizes. With these • LP = Low-Power Crystal two timers on-chip, most applications need no external • XT = Crystal/Resonator reset circuitry. • HS = High-speed Crystal Resonator SLEEP mode is designed to offer a very low current In all modes, a crystal or ceramic resonator is power-down mode. The user can wake-up from SLEEP connected to the OSC1/CLKIN and OSC2/CLKOUT through external reset, transmit-on-change or CAN bus pins to establish oscillation (Figure8-1). The oscillator activity. design requires the use of a parallel-cut crystal. The A set of configuration bits are used to select various device can also have an external clock source to drive options. the OSC1/CLKIN pin (Figure8-2). The device will default to HS mode if the CONFIG FIGURE 8-1: CRYSTAL/CERAMIC register is not programmed. RESONATOR OPERATION OSC1 TO INTERNAL LOGIC C1 XTAL RF SLEEP OSC2 MCP2505X C2  2003 Microchip Technology Inc. DS21664C-page 49

MCP2502X/5X REGISTER 8-1: CONFIGURATION REGISTER U-0 U-0 R/W-x R/W-x R/W-x R/W-x — — R R R R bit 13 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W R/W R/W R R R R R RSTEN FOSC1 FOSC0 bit 7 bit 0 bit 13-11 Unimplemented: Read as '0' bit 10-3 Reserved: do not attempt to modify bit 2 RSTEN: Enable RST input on GP7 1 = RST input Enabled 0 = RST input Disabled bit 1-0 F 1:F 0: Oscillator Selection bits OSC OSC 11 = HS oscillator 10 = Reserved for Test (EC oscillator) 01 = XT oscillator 00 = LP oscillator Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown 8.4 Reset 8.4.1 POWER-ON RESET The MCP2502X/5X differentiates between two kinds of A Power-on Reset pulse is generated on-chip when reset: VDD rise is detected (in the range of 1.5V to 2.1V). If the RST input on the GP7 pin is selected, the RST pin may • Power-on Reset (POR) be tied through a series resistor to V , eliminating the DD • External RST reset need for external RC components usually required for Some registers are not affected in any reset condition. a Power-on Reset. A maximum rise time for VDD is Their status is unknown on POR and unchanged in any specified in Section9.0 “Electrical Characteristics” other reset. Most other registers are reset to a reset of this document. state on Power-on Reset (POR), on RST and on RST When the device starts normal operation (exits the during SLEEP. They are not affected by a wake-up from reset condition), device operating parameters (voltage, SLEEP, which is viewed as the resumption of normal frequency, temperature, etc.) must be met to ensure operation. A simplified block diagram of the on-chip proper operation. For additional information, refer to reset circuit is shown in Figure8-3. The MCP2502X/5X AN607, “Power-up Troubleshooting”, DS00607). has a RST noise filter in the RST reset path. The filter will detect and ignore small pulses. DS21664C-page 50  2003 Microchip Technology Inc.

MCP2502X/5X FIGURE 8-3: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT RST VDD Rise Detect Power-on Reset S V DD OST 10-bit Ripple Counter Q Chip Reset OSC1 PWRT On-chip 10-bit Ripple Counter RC OSC Enable PWRT Enable OST 8.4.2 POWER-UP TIMER as a valid message before entering Normal mode. This feature is enabled via the PUSLP bit in the OPTREG2 The Power-up Timer (PWRT) provides a fixed, 72ms register. nominal time-out, on power-up only, from the POR. The Power-up Timer operates on an internal RC oscillator, While in SLEEP, the I/O ports maintain the status they with the device being kept in reset as long as the PWRT had before the SLEEP instruction was executed is active. The PWRT's time delay allows V to rise to (driving high, low or hi-impedance). DD an acceptable level. The power-up time delay will vary The following operations will not function while the from device to device due to VDD, temperature and device is in SLEEP: process variation. For more information, please see • A/D Module data conversion Section9.2 “DC Characteristics”. • Auto-conversion mode 8.5 Oscillator Start-up Timer • Auto-messaging • PWM module and outputs The Oscillator Start-up Timer (OST) provides a 512 • Clock output oscillator cycle (TOSC) delay after the PWRT delay is complete. This ensures that the crystal oscillator has 8.6.1 WAKE-UP FROM SLEEP started and stabilized and must be less than the total time it takes (704 oscillator cycles or 44TQ) for the The MCP2502X/5X can wake-up from SLEEP through minimum standard data frame or remote transmit one of the following events: message to be completed on the CAN bus once a • External reset input on RST pin wake-up from SLEEP occurs. The OST time-out is • Transmit-on-change due to edge detected on invoked only on Power-on Reset or wake-up from GPIO pin SLEEP. • Activity detected on CAN bus 8.6 Power-down Mode (SLEEP) For the device to wake-up due to a GPIO transmit-on- change, the corresponding interrupt enable bit must be Power-down mode (or SLEEP) is enabled via the set (enabled). Wake-up occurs regardless of the state SLPEN bit in the OPTREG2 register. When enabled, of the GIE bit. the MCP2502X/5X will enter SLEEP once the CAN bus If a wake-up from SLEEP is caused by activity on the has been idle for a minimum 1408 bit times while in CAN bus, the message that caused the wake-up will not Normal mode. be received or acknowledged by the MCP2502X/5X. Additionally, the device may be configured to enter SLEEP while in Listen-only mode immediately after power-up if there is no activity on the CAN bus. Subsequent CAN bus activity will wake the device up from SLEEP and the NEXT message will be confirmed  2003 Microchip Technology Inc. DS21664C-page 51

MCP2502X/5X 8.7 In-Circuit Serial Programming The MCP2502X/5X can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground and the programming voltage. This allows customers to manufacture boards with unprogrammed devices and then program the device just before shipping the product, also allowing the most recent firmware (or a custom firmware) to be programmed. The device is placed into a program/verify mode by holding the GP4 and GP5 pins low while raising GP7 (VPP) pin from VIL to VIH (see the MCP2502X/5X programming specification, “MCP250XX In-Circuit Serial Programming™ (ICSP)”, DS20072, for more information). GP4 becomes the programming data and GP5 becomes the programming clock. Both GP4 and GP5 are Schmitt Trigger inputs in this mode. The signal definitions are summarized in Table8-1 TABLE 8-1: IN-CIRCUIT SERIAL PROGRAMMING PIN FUNCTIONS Pin Programming Mode Pin Name Number Function VSS 7 Ground GP4 5 Data GP5 6 Clock GP7 11 VPP VDD 14 Power DS21664C-page 52  2003 Microchip Technology Inc.

MCP2502X/5X 9.0 ELECTRICAL CHARACTERISTICS 9.1 Absolute Maximum Ratings† Ambient temperature under bias.............................................................................................................-55°C to +125°C Storage temperature...............................................................................................................................-65°C to +150°C Voltage on any pin with respect to Vss (except VDD and RST).......................................................-0.3V to (VDD + 0.6V) VDD...................................................................................................................................................................0V to 7.0V Voltage on RST with respect to Vss..................................................................................................................0V to 14V Total power dissipation (Note1)..............................................................................................................................1.0W Maximum source current out of VSS pin...............................................................................................................300mA Maximum sink current into VDD pin.......................................................................................................................250mA Input clamp current, Iik (Vi < 0 or Vi > VDD)..........................................................................................................±20mA Output clamp current, Iok (VO < 0 or VO > VDD)....................................................................................................±20mA Maximum current sunk by any I/O pin.....................................................................................................................25mA Maximum current sourced by any input pin............................................................................................................25mA Maximum current sunk by GPIO port....................................................................................................................200mA Maximum current sourced by GPIO port ..............................................................................................................200mA Soldering temperature of leads (10 seconds).......................................................................................................+300°C ESD protection on all pins..................................................................................................................................................≥ 3.5kV Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOL x IOL) † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. FIGURE 9-1: MCP2505X VOLTAGE-FREQUENCY GRAPH 6.0V 5.5V 5.0V 4.5V MCP2505X 4.5V e 4.0V g a t ol 3.5V V 3.0V 2.7V 2.0V 8MHz 25MHz Frequency Fmax = (9.44MHz/V) (VDDAPPMIN - 2.7V) + 8MHz Note: VDDAPPMIN is the minimum voltage of the MCP2505X device in the application. Characterized and not 100% tested.  2003 Microchip Technology Inc. DS21664C-page 53

MCP2502X/5X 9.2 DC Characteristics Industrial (I): TAMB = -40°C to +85°C VCC = 2.7V to 5.5V DC Characteristics Automotive (E):TAMB = -40°C to +125°C VCC = 4.5V to 5.5V Param. Sym Characteristics Min Max Units Test Conditions No. VDD Supply Voltage 2.7 5.5 V XT and LP OSC configuration 4.5 5.5 V HS OSC configuration (Note2) SVDD VDD Rise Rate to ensure 0.05 — V/ms (Note3) internal power-on reset signal High-level input voltage VIH GPIO pins 2 VDD+0.3 V VIH RXCAN (Schmitt Trigger) .7VDD VDD V OSC1 .85VDD VDD V Low-level input voltage — VIL RXCAN (Schmitt Trigger) VSS 0.2VDD V VIL GPIO pins -0.3 0.5V V OSC1 VSS 0.2VDD V Low-level output voltage VOL TXCAN GPIO pins — 0.6 V IOL = 8.5mA, VDD = 4.5V High-level output voltage V VOH TXCAN, GPIO pins VDD -0.7 — V IOH =-3.0mA, VDD = 4.5V, I-temp Input leakage current ILI All I/O except OSC1, GP7 -1 +1 µA OSC1, GP7 pin -5 +5 µA CINT Internal Capacitance — 7 pF TAMB = 25°C, fC = 1.0MHz, (all inputs and outputs, except VDD = 5.0V (Note3) GP7) GP7 — 15 pF IDD Operating Current — 20 mA XT OSC VDD = 5.5V; FOSC=25MHz IDDS Standby Current — 30 µA Inputs tied to VDD or VSS (CAN Sleep Mode) Note 1: This is the limit to which V can be lowered in SLEEP mode without losing RAM data. DD 2: Refer to Figure9-1. 3: This parameter is periodically sampled and not 100% tested. DS21664C-page 54  2003 Microchip Technology Inc.

MCP2502X/5X 9.3 AC Characteristics Industrial (I): TAMB = -40°C to +85°C VCC = 2.7V to 5.5V AC Characteristics Automotive (E):TAMB = -40°C to +125°C VCC = 4.5V to 5.5V Param. Sym Characteristics Min Max Units Test Conditions No. FOS CLKIN Frequency DC 4 MHz XT osc mode DC 25 MHz HS osc mode (Note3) DC 200 kHz LP osc mode FOS Oscillator Frequency 0.1 4 MHz XT osc mode 4 25 MHz HS osc mode (Note3) 5 200 kHz LP osc mode 1 TOSC CLKIN Period 250 — ns XT osc mode 40 — ns HS osc mode 5 — µs LP osc mode Oscillator Period 0.25 10 µs XT osc mode 40 250 ns HS osc mode 5 — µs LP osc mode 3 TOSL CLKIN High or Low Time 100 — ns XT osc mode TOSH 15 — ns HS osc mode 2.5 — µs LP osc mode 4 Tosr CLKIN Rise or Fall Time — 25 ns XT osc mode (Note1) — 50 ns HS osc mode (Note1) — 15 ns LP osc mode (Note1) 10 TDCLKOUT CLKOUT Propagation Delay — 60 ns VDD = 4.5 V (Note2) 12 TCKR CLKOUT Rise Time — 100 ns Note2 13 TCKR CLKOUT Fall Time — 200 ns Note2 20 TIOR Port output rise time — 40 ns Note1 21 TIOF Port output fall time — 40 ns Note1 30 TMCL RST Pulse Low 2 — µs VDD = 5V 32 TOST Oscillation Start-up Timer 512 — Tosc TOSC = OSC1 period 33 TPWRT Power-up Timer 28 132 ms VDD = 5V 34 TIOZ I/O Hi-impedance from RST — 2.1 µs Note1 low TPWMR PWM output rise time — 25 ns Note1 TPWMF PWM output fall time — 25 ns Note1 TAD A/D clock period 1.6 — µs VREF∆ ≥ 2.5V 3.0 — µs VREF full range TCNV Conversion Time (not — 13 TAD including acquisition time) Note 1: This parameter is periodically sampled and not 100% tested. 2: Measurements are taken with CLKOUT output configured as 4 x TOSC. 3: Refer to Figure9-1.  2003 Microchip Technology Inc. DS21664C-page 55

MCP2502X/5X FIGURE 9-2: I/O TIMING OSC1 I/O Pin (input) I/O Pin Old Value New Value (output) 20, 21 10 13 12 Note: All tests must be done with specified capacitive loads (see data sheet) 50pF on I/O pins. FIGURE 9-3: RESET, OST AND POWER-UP-TIMER VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET 34 34 I/O Pins DS21664C-page 56  2003 Microchip Technology Inc.

MCP2502X/5X 9.4 A/D Converter Characteristics Industrial (I): TAMB = -40°C to +85°C VCC = 2.7V to 5.5V AC Converter Characteristics Automotive (E):TAMB = -40°C to +125°C VCC = 4.5V to 5.5V Param. Sym Characteristics Min Max Units Test Conditions No. NR A/D resolution — 10-bits VREF = VDD = 5.12V, VSS ≤ in ≤VREF NINT A/D Integral error — less than VREF+ = VDD = 5.12V, ±1 LSb VSS- = VSS = 0 V (I TEMP) NDIF A/D Differential error — less than VREF+ = VDD = 5.12V, ±1 LSb VSS- = VSS = 0 V (I TEMP) NG A/D Gain error — less than VREF+ = VDD = 5.12V, ±1 LSb VSS- = VSS = 0 V NOFF A/D Offset error — less than VREF+ = VDD = 5.12V, ±2 LSb VSS- = VSS = 0 V Monotonicity — — VSS ≤ in ≤VREF VREF Reference Voltage 4.096 VDD+0.3 V Absolute minimum to ensure 10-bit accuracy. VREF+ Reference V high VREF- VDD+0.3 V Minimum resolution for A/D is 1mV. VREF- Reference V low VSS-0.3 VREF+ V Minimum resolution for A/D is 1mV. VAIN Analog input V VREF- VREF+ V ZAIN Recommended impedance — 2.5 kΩ Note of analog voltage source IREF VREF input current — 10 µA NHYS Analog Transmit-on-change — 2 LSb Specified by design (see Hysteresis Section4.5.2.1 “Hysteresis Function”) Note: Design guidance only  2003 Microchip Technology Inc. DS21664C-page 57

MCP2502X/5X NOTES: DS21664C-page 58  2003 Microchip Technology Inc.

MCP2502X/5X 10.0 PACKAGING INFORMATION 10.1 Package Marking Information 14-Lead PDIP (300 mil) Example: XXXXXXXXXXXXXX MCP25050 XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN 0325NNN 14-Lead SOIC (208 mil) Example: XXXXXXXXXXX MCP25055 XXXXXXXXXXX XXXXXXXXXXX YYWWNNN 0337NNN Legend: XX...X Customer specific information* Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard device marking consists of Microchip part number, year code, week code and traceability code..  2003 Microchip Technology Inc. DS21664C-page 59

MCP2502X/5X 14-Lead Plastic Dual In-line (P) –300 mil (PDIP) E1 D 2 n 1 α E A A2 c L A1 β B1 eB B p Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 14 14 Pitch p .100 2.54 Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32 Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26 Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60 Overall Length D .740 .750 .760 18.80 19.05 19.30 Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43 Lead Thickness c .008 .012 .015 0.20 0.29 0.38 Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78 Lower Lead Width B .014 .018 .022 0.36 0.46 0.56 Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92 Mold Draft Angle Top α 5 10 15 5 10 15 Mold Draft Angle Bottom β 5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-005 DS21664C-page 60  2003 Microchip Technology Inc.

MCP2502X/5X 14-Lead Plastic Small Outline (SL) –Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 α h 45° c A A2 φ A1 L β Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 14 14 Pitch p .050 1.27 Overall Height A .053 .061 .069 1.35 1.55 1.75 Molded Package Thickness A2 .052 .056 .061 1.32 1.42 1.55 Standoff § A1 .004 .007 .010 0.10 0.18 0.25 Overall Width E .228 .236 .244 5.79 5.99 6.20 Molded Package Width E1 .150 .154 .157 3.81 3.90 3.99 Overall Length D .337 .342 .347 8.56 8.69 8.81 Chamfer Distance h .010 .015 .020 0.25 0.38 0.51 Foot Length L .016 .033 .050 0.41 0.84 1.27 Foot Angle φ 0 4 8 0 4 8 Lead Thickness c .008 .009 .010 0.20 0.23 0.25 Lead Width B .014 .017 .020 0.36 0.42 0.51 Mold Draft Angle Top α 0 12 15 0 12 15 Mold Draft Angle Bottom β 0 12 15 0 12 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-065  2003 Microchip Technology Inc. DS21664C-page 61

MCP2502X/5X NOTES: DS21664C-page 62  2003 Microchip Technology Inc.

MCP2502X/5X PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX Examples: a) MCP25020–I/P: Industrial temperature, Device Temperature Package PDIP package. Range b) MCP25025–I/SL: Industrial temperature, SOIC package. c) MCP25050T-E/SL: Tape and Reel, Extended temperature, Device: MCP25020: CAN I/O Expander SOIC package. MCP25020T:CAN I/O Expander (Tape and Reel) MCP25025: CAN I/O Expander d) MCP25055-I/SL: Industrial temperature MCP25025T:CAN I/O Expander (Tape and Reel) SOIC package. MCP25050: Mixed Signal CAN I/O Expander MCP25050T:Mixed Signal CAN I/O Expander (Tape and Reel) MCP25055: Mixed Signal CAN I/O Expander MCP25055T:Mixed Signal CAN I/O Expander (Tape and Reel) Temperature Range: I = -40°C to +85°C E = -40°C to +125°C (not available on MCP25025 or MCP25055 devices) Package: P = Plastic DIP (300 mil Body), 14-lead SL = Plastic SOIC (150 mil Body), 14-lead Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office 2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 3. The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.  2003 Microchip Technology Inc. DS21664C-page 63

MCP2502X/5X NOTES: DS21664C-page 64  2003 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is intended through suggestion only The Microchip name and logo, the Microchip logo, Accuron, and may be superseded by updates. It is your responsibility to dsPIC, KEELOQ, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. PRO MATE and PowerSmart are registered trademarks of No representation or warranty is given and no liability is Microchip Technology Incorporated in the U.S.A. and other assumed by Microchip Technology Incorporated with respect countries. to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such AmpLab, FilterLab, microID, MXDEV, MXLAB, PICMASTER, use or otherwise. Use of Microchip’s products as critical com- SEEVAL and The Embedded Control Solutions Company are ponents in life support systems is not authorized except with registered trademarks of Microchip Technology Incorporated express written approval by Microchip. No licenses are con- in the U.S.A. veyed, implicitly or otherwise, under any intellectual property Application Maestro, dsPICDEM, dsPICDEM.net, ECAN, rights. ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPIC, Select Mode, SmartSensor, SmartShunt, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2003, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified. DS21664C-page 65  2003 Microchip Technology Inc.

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: MCP25050-E/SL MCP25020-E/SL MCP25055-I/P MCP25025-I/P MCP25050-E/P MCP25050-I/P MCP25055T- I/SL MCP25020T-I/SL MCP25050T-I/SL MCP25025T-I/SL MCP25050T-E/SL MCP25020T-E/SL MCP25020-E/P MCP25050-I/SL MCP25020-I/SL MCP25025-I/SL MCP25055-I/SL MCP25020-I/P