MCP23017/MCP23S17 16-Bit I/O Expander with Serial Interface Features • Configurable Interrupt Source: - Interrupt-on-change from configured register • 16-Bit Remote Bidirectional I/O Port: defaults or pin changes - I/O pins default to input • Polarity Inversion Register to Configure the • High-Speed I2C Interface (MCP23017): Polarity of the Input Port Data - 100kHz • External Reset Input - 400kHz • Low Standby Current: 1µA (max.) - 1.7MHz • Operating Voltage: • High-Speed SPI Interface (MCP23S17): - 1.8V to 5.5V @ -40°C to +85°C - 10MHz (maximum) - 2.7V to 5.5V @ -40°C to +85°C • Three Hardware Address Pins to Allow Up to - 4.5V to 5.5V @ -40°C to +125°C Eight Devices On the Bus • Configurable Interrupt Output Pins: Packages - Configurable as active-high, active-low or open-drain • 28-pin QFN, 6 x 6 mm Body • INTA and INTB Can Be Configured to Operate • 28-pin SOIC, Wide, 7.50 mm Body Independently or Together • 28-pin SPDIP, 300mil Body • 28-pin SSOP, 5.30 mm Body Package Types MCP23017 MCP23S17 GPB0 • 1 28 GPA7 GPB0 • 1 28 GPA7 GPB1 2 27 GPA6 GPB1 2 27 GPA6 GPB2 3 26 GPA5 GPB2 3 26 GPA5 GPB3 4 25 GPA4 GPB3 4 25 GPA4 GPB4 5 24 GPA3 GPB4 5 24 GPA3 GPB5 6 23 GPA2 GPB5 6 23 GPA2 GPB6 7 22 GPA1 SOIC GPB6 7 22 GPA1 GPB7 8 21 GPA0 SPDIP GPB7 8 21 GPA0 VDD 9 20 INTA SSOP VDD 9 20 INTA VSS 10 19 INTB VSS 10 19 INTB NC 11 18 RESET CS 11 18 RESET SCK 12 17 A2 SCK 12 17 A2 SDA 13 16 A1 SI 13 16 A1 NC 14 15 A0 SO 14 15 A0 B3B2B1B0A7A6A5 B3B2B1B0A7A6A5 PPPPPPP PPPPPPP GGGGGGG GGGGGGG 28272625242322 28272625242322 GPB4 1 21 GPA4 GPB4 1 21 GPA4 GPB5 2 20 GPA3 GPB5 2 20 GPA3 GPB6 3 19 GPA2 QFN GPB6 3 19 GPA2 GPB7 4 EP 18 GPA1 GPB7 4 EP 18 GPA1 VDD 5 29 * 17 GPA0 VDD 5 29 * 17 GPA0 VSS 6 16 INTA VSS 6 16 INTA NC 7 15 INTB CS 7 15 INTB 8 91011121314 8 91011121314 CKDANCA0A1A2ET CKSISOA0A1A2ET SS S S S E E R R * Includes Exposed Thermal Pad; see Table2-1.  2005-2016 Microchip Technology Inc. DS20001952C-page 1

MCP23017/MCP23S17 Functional Block Diagram MCP23S17 CS SCK SI SPI SO MCP23017 GPB7 SCL Serializer/ SDA I2C Deserializer GPB6 GPB5 GPB4 3 GPIO GPB3 A2:A0 Decode GPB2 RESET Control GPB1 INTA Interrupt 16 GPB0 INTB Logic GPA7 GPA6 8 GPA5 GPA4 GPIO GPA3 Configuration/ GPA2 Control GPA1 Registers GPA0 DS20001952C-page 2  2005-2016 Microchip Technology Inc.

MCP23017/MCP23S17 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature...............................................................................................................................-65°C to +150°C Voltage on V with respect to V ..........................................................................................................-0.3V to +5.5V DD SS Voltage on all other pins with respect to V (except V ).............................................................-0.6V to (V + 0.6V) SS DD DD Total power dissipation.........................................................................................................................................700mW Maximum current out of V pin...........................................................................................................................150mA SS Maximum current into V pin..............................................................................................................................125mA DD Input clamp current, I (V < 0 or V > V )..........................................................................................................±20mA IK I I DD Output clamp current, IOK (VO < 0 or VO > VDD)...................................................................................................±20mA Maximum output current sunk by any output pin....................................................................................................25mA Maximum output current sourced by any output pin...............................................................................................25mA ESD protection on all pins (HBM:MM)..............................................................................................................4kV:400V † Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.  2005-2016 Microchip Technology Inc. DS20001952C-page 3

MCP23017/MCP23S17 1.1 DC Characteristics TABLE 1-1: DC CHARACTERISTICS Electrical Specifications: Unless otherwise noted, 1.8V V  5.5V at -40C  T  +125C DD A Param. Characteristic Sym. Min. Typ.(1) Max. Units Conditions No. D001 Supply Voltage V 1.8 — 5.5 V DD D002 V Start Voltage to V — V — V DD POR SS ensure Power-on Reset D003 V Rise Rate to ensure SV 0.05 — — V/ms Design guidance only. DD DD Power-on Reset Not tested. D004 Supply Current I — — 1 mA SCL/SCK = 1MHz DD D005 Standby current I — — 1 µA -40°C  T  +85°C DDS8 A — — 3 µA 4.5V V 5.5V DD +85°C  T +125C A (Note1) Input Low Voltage D030 A0, A1, A2 (TTL buffer) V V — 0.15V V IL SS DD D031 CS, GPIO, SCL/SCK, V V — 0.2V V IL SS DD SDA, RESET (Schmitt Trigger) Input High Voltage D040 A0, A1, A2 (TTL buffer) VIH 0.25VDD + 0.8 — VDD V D041 CS, GPIO, SCL/SCK, VIH 0.8VDD — VDD V For entire VDD range SDA, RESET (Schmitt Trigger) Input Leakage Current D060 I/O port pins I — — ±1 µA V V V IL SS PIN DD Output Leakage Current D065 I/O port pins I — — ±1 µA V V V LO SS PIN DD D070 GPIO weak pull-up I 40 75 115 µA V = 5V PU DD current GP pins = V SS Output Low-Voltage D080 GPIO V — — 0.6 V I = 8.0mA OL OL V = 4.5V DD INT V — — 0.6 V I = 1.6mA OL OL V = 4.5V DD SO, SDA V — — 0.6 V I = 3.0mA OL OL V = 1.8V DD SDA V — — 0.8 V I = 3.0mA OL OL V = 4.5V DD Output High-Voltage D090 GPIO, INT, SO V V – 0.7 — — V I = -3.0mA OH DD OH V = 4.5V DD V – 0.7 — — I = -400µA DD OH V = 1.8V DD Capacitive Loading Specs on Output Pins D101 GPIO, SO, INT C — — 50 pF IO D102 SDA C — — 400 pF B Note 1: This parameter is characterized, not 100% tested. DS20001952C-page 4  2005-2016 Microchip Technology Inc.

MCP23017/MCP23S17 1.2 AC Characteristics FIGURE 1-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS V DD Pin 1k SCL and 50pF SDA pin MCP23017 135pF FIGURE 1-2: RESET AND DEVICE RESET TIMER TIMING V DD RESET 30 32 Internal RESET 34 Output pin TABLE 1-2: DEVICE RESET SPECIFICATIONS AC Characteristics: Unless otherwise noted, 1.8V V  5.5V at -40C  T  +125C DD A Param. Characteristic Sym. Min. Typ. (1) Max. Units Conditions No. 30 RESET Pulse Width T 1 — — µs RSTL (Low) 32 Device Active After Reset T — 0 — ns V = 5.0V HLD DD high 34 Output High-Impedance T — — 1 µs IOZ From RESET Low Note 1: This parameter is characterized, not 100% tested.  2005-2016 Microchip Technology Inc. DS20001952C-page 5

MCP23017/MCP23S17 FIGURE 1-3: I2C BUS START/STOP BITS TIMING SCL 91 93 90 92 SDA Start Stop Condition Condition FIGURE 1-4: I2C BUS DATA TIMING 103 100 102 101 SCL 90 106 91 107 92 SDA In 109 109 110 SDA Out TABLE 1-3: I2C BUS DATA REQUIREMENTS I2C Interface AC Characteristics: Unless otherwise noted, 1.8V V  5.5V at -40C  T  +125C, R (SCL, DD A PU SDA) = 1k, C (SCL, SDA) = 135pF L Param. Characteristic Sym. Min. Typ. Max. Units Conditions No. 100 Clock High Time: T HIGH 100kHz mode 4.0 — — µs 1.8V – 5.5V 400kHz mode 0.6 — — µs 2.7V – 5.5V 1.7MHz mode 0.12 — — µs 4.5V – 5.5V 101 Clock Low Time: T LOW 100kHz mode 4.7 — — µs 1.8V – 5.5V 400kHz mode 1.3 — — µs 2.7V – 5.5V 1.7MHz mode 0.32 — — µs 4.5V – 5.5V 102 SDA and SCL Rise Time: T (1) R 100kHz mode — — 1000 ns 1.8V – 5.5V 400kHz mode 20 + 0.1C (2) — 300 ns 2.7V – 5.5V B 1.7MHz mode 20 — 160 ns 4.5V – 5.5V 103 SDA and SCL Fall Time: T (1) F 100kHz mode — — 300 ns 1.8V – 5.5V 400kHz mode 20 + 0.1C (2) — 300 ns 2.7V – 5.5V B 1.7MHz mode 20 — 80 ns 4.5V – 5.5V Note 1: This parameter is characterized, not 100% tested. 2: C is specified to be from 10 to 400pF. B DS20001952C-page 6  2005-2016 Microchip Technology Inc.

MCP23017/MCP23S17 TABLE 1-3: I2C BUS DATA REQUIREMENTS (CONTINUED) I2C Interface AC Characteristics: Unless otherwise noted, 1.8V V  5.5V at -40C  T  +125C, R (SCL, DD A PU SDA) = 1k, C (SCL, SDA) = 135pF L Param. Characteristic Sym. Min. Typ. Max. Units Conditions No. 90 START Condition Setup Time: T SU:STA 100kHz mode 4.7 — — µs 1.8V – 5.5V 400kHz mode 0.6 — — µs 2.7V – 5.5V 1.7MHz mode 0.16 — — µs 4.5V – 5.5V 91 START Condition Hold Time: T HD:STA 100kHz mode 4.0 — — µs 1.8V – 5.5V 400kHz mode 0.6 — — µs 2.7V – 5.5V 1.7MHz mode 0.16 — — µs 4.5V – 5.5V 106 Data Input Hold Time: T HD:DAT 100kHz mode 0 — 3.45 µs 1.8V – 5.5V 400kHz mode 0 — 0.9 µs 2.7V – 5.5V 1.7MHz mode 0 — 0.15 µs 4.5V – 5.5V 107 Data Input Setup Time: T SU:DAT 100kHz mode 250 — — ns 1.8V – 5.5V 400kHz mode 100 — — ns 2.7V – 5.5V 1.7MHz mode 0.01 — — µs 4.5V – 5.5V 92 Stop Condition Setup Time: T SU:STO 100kHz mode 4.0 — — µs 1.8V – 5.5V 400kHz mode 0.6 — — µs 2.7V – 5.5V 1.7MHz mode 0.16 — — µs 4.5V–5.5V 109 Output Valid From Clock: T AA 100kHz mode — — 3.45 µs 1.8V – 5.5V 400kHz mode — — 0.9 µs 2.7V – 5.5V 1.7MHz mode — — 0.18 µs 4.5V – 5.5V 110 Bus Free Time: T BUF 100kHz mode 4.7 — — µs 1.8V – 5.5V 400kHz mode 1.3 — — µs 2.7V – 5.5V 1.7MHz mode N/A — N/A µs 4.5V – 5.5V 111 Bus Capacitive Loading: C B 100kHz and 400kHz — — 400 pF Note1 1.7MHz — — 100 pF Note1 112 Input Filter Spike Suppression T SP (SDA and SCL): 100kHz and 400kHz — — 50 ns 1.7MHz — — 10 ns Spike suppression off Note 1: This parameter is characterized, not 100% tested. 2: C is specified to be from 10 to 400pF. B  2005-2016 Microchip Technology Inc. DS20001952C-page 7

MCP23017/MCP23S17 FIGURE 1-5: SPI INPUT TIMING CS (1) 3 11 1 6 10 Mode 1,1 7 2 SCK Mode 0,0 4 5 SI MSB in LSB in SO High-Impedance Note 1: When using SPI Mode 1,1 the CS pin needs to be toggled once before the first communication after power-up. FIGURE 1-6: SPI OUTPUT TIMING CS 2 8 9 SCK Mode 1,1 Mode 0,0 12 14 13 SO MSB out LSB out Don’t Care SI TABLE 1-4: SPI INTERFACE REQUIREMENTS SPI Interface AC Characteristics: Unless otherwise noted, 1.8V V  5.5V at -40C  T  +125C DD A Param. Characteristic Sym. Min. Typ. Max. Units Conditions No. — Clock Frequency F — — 5 MHz 1.8V – 5.5V CLK — — 10 MHz 2.7V – 5.5V — — 10 MHz 4.5V – 5.5V 1 CS Setup Time T 50 — — ns CSS 2 CS Hold Time T 100 — — ns 1.8V – 5.5V CSH 50 — — ns 2.7V – 5.5V 3 CS Disable Time T 100 — — ns 1.8V – 5.5V CSD 50 — — ns 2.7V – 5.5V 4 Data Setup Time T 20 — — ns 1.8V – 5.5V SU 10 — — ns 2.7V – 5.5V Note 1: This parameter is characterized, not 100% tested. DS20001952C-page 8  2005-2016 Microchip Technology Inc.

MCP23017/MCP23S17 TABLE 1-4: SPI INTERFACE REQUIREMENTS (CONTINUED) SPI Interface AC Characteristics: Unless otherwise noted, 1.8V V  5.5V at -40C  T  +125C DD A Param. Characteristic Sym. Min. Typ. Max. Units Conditions No. 5 Data Hold Time T 20 — — ns 1.8V – 5.5V HD 10 — — ns 2.7V – 5.5V 6 CLK Rise Time T — — 2 µs Note1 R 7 CLK Fall Time T — — 2 µs Note1 F 8 Clock High Time T 90 — — ns 1.8V – 5.5V HI 45 — — ns 2.7V – 5.5V 9 Clock Low Time T 90 — — ns 1.8V – 5.5V LO 45 — — ns 2.7V – 5.5V 10 Clock Delay Time T 50 — — ns CLD 11 Clock Enable Time T 50 — — ns CLE 12 Output Valid from Clock Low T — — 90 ns 1.8V – 5.5V V — — 45 ns 2.7V – 5.5V 13 Output Hold Time T 0 — — ns HO 14 Output Disable Time T — — 100 ns DIS Note 1: This parameter is characterized, not 100% tested. FIGURE 1-7: GPIO AND INT TIMING SCL/SCK SDA/SI In D1 D0 LSb of data byte zero during a write or read command, depending on parameter 50 GPn Output Pin 51 INT Pin INT Pin Active Inactive 53 GPn Input Pin 52 Register Loaded  2005-2016 Microchip Technology Inc. DS20001952C-page 9

MCP23017/MCP23S17 TABLE 1-5: GP AND INT PINSREQUIREMENTS GP and INT Pins AC Characteristics: Unless otherwise noted, 1.8V V  5.5V at -40C  T  +125C DD A Param. Characteristic Sym. Min. Typ. Max. Units Conditions No. 50 Serial Data to Output Valid T — — 500 ns GPOV 51 Interrupt Pin Disable Time T — — 600 ns INTD 52 GP Input Change to T — — 450 ns GPIV Register Valid 53 IOC Event to INT Active T — — 600 ns GPINT Glitch Filter on GP Pins T — — 150 ns Note1 GLITCH Note 1: This parameter is characterized, not 100% tested. DS20001952C-page 10  2005-2016 Microchip Technology Inc.

MCP23017/MCP23S17 2.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table2-1. TABLE 2-1: PINOUT DESCRIPTION SOIC Pin Pin QFN SPDIP Function Name Type SSOP GPB0 25 1 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor. GPB1 26 2 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor. GPB2 27 3 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor. GPB3 28 4 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor. GPB4 1 5 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor. GPB5 2 6 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor. GPB6 3 7 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor. GPB7 4 8 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor. V 5 9 P Power DD V 6 10 P Ground SS NC/CS 7 11 I NC (MCP23017)/Chip Select (MCP23S17) SCK 8 12 I Serial clock input SDA/SI 9 13 I/O Serial data I/O (MCP23017)/Serial data input (MCP23S17) NC/SO 10 14 O NC (MCP23017)/Serial data out (MCP23S17) A0 11 15 I Hardware address pin. Must be externally biased. A1 12 16 I Hardware address pin. Must be externally biased. A2 13 17 I Hardware address pin. Must be externally biased. RESET 14 18 I Hardware reset. Must be externally biased. INTB 15 19 O Interrupt output for PORTB. Can be configured as active-high, active-low or open-drain. INTA 16 20 O Interrupt output for PORTA. Can be configured as active-high, active-low or open-drain. GPA0 17 21 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor. GPA1 18 22 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor. GPA2 19 23 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor. GPA3 20 24 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor. GPA4 21 25 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor. GPA5 22 26 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor. GPA6 23 27 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor. GPA7 24 28 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor. EP 29 — — Exposed Thermal Pad. Either connect to V , or leave unconnected. SS  2005-2016 Microchip Technology Inc. DS20001952C-page 11

MCP23017/MCP23S17 3.0 DEVICE OVERVIEW 3.2 Serial Interface The MCP23017/MCP23S17 (MCP23X17) device This block handles the functionality of the I2C family provides 16-bit, general purpose parallel I/O (MCP23017) or SPI (MCP23S17) interface protocol. expansion for I2C bus or SPI applications. The two The MCP23X17 contains 22 individual registers (11 devices differ only in the serial interface: register pairs) that can be addressed through the Serial • MCP23017 – I2C interface Interface block, as shown in Table3-1. • MCP23S17 – SPI interface TABLE 3-1: REGISTER ADDRESSES The MCP23X17 consists of multiple 8-bit configuration Address Address registers for input, output and polarity selection. The Access to: IOCON.BANK = 1 IOCON.BANK = 0 system master can enable the I/Os as either inputs or outputs by writing the I/O configuration bits (IODIRA/B). 00h 00h IODIRA The data for each input or output is kept in the 10h 01h IODIRB corresponding input or output register. The polarity of 01h 02h IPOLA the Input Port register can be inverted with the Polarity 11h 03h IPOLB Inversion register. All registers can be read by the 02h 04h GPINTENA system master. 12h 05h GPINTENB The 16-bit I/O port functionally consists of two 8-bit 03h 06h DEFVALA ports (PORTA and PORTB). The MCP23X17 can be 13h 07h DEFVALB configured to operate in the 8-bit or 16-bit modes via IOCON.BANK. 04h 08h INTCONA 14h 09h INTCONB There are two interrupt pins, INTA and INTB, that can be associated with their respective ports, or can be 05h 0Ah IOCON logically OR’ed together so that both pins will activate if 15h 0Bh IOCON either port causes an interrupt. 06h 0Ch GPPUA The interrupt output can be configured to activate 16h 0Dh GPPUB under two conditions (mutually exclusive): 07h 0Eh INTFA 1. When any input state differs from its 17h 0Fh INTFB corresponding Input Port register state. This is 08h 10h INTCAPA used to indicate to the system master that an 18h 11h INTCAPB input state has changed. 09h 12h GPIOA 2. When an input state differs from a preconfigured 19h 13h GPIOB register value (DEFVAL register). 0Ah 14h OLATA The Interrupt Capture register captures port values at 1Ah 15h OLATB the time of the interrupt, thereby saving the condition that caused the interrupt. The Power-on Reset (POR) sets the registers to their default values and initializes the device state machine. The hardware address pins are used to determine the device address. 3.1 Power-on Reset (POR) The on-chip POR circuit holds the device in reset until V has reached a high enough voltage to deactivate DD the POR circuit (i.e., release the device from reset). The maximum V rise time is specified in Section1.0 DD “Electrical Characteristics”. When the device exits the POR condition (releases reset), device operating parameters (i.e., voltage, temperature, serial bus frequency, etc.) must be met to ensure proper operation. DS20001952C-page 12  2005-2016 Microchip Technology Inc.

MCP23017/MCP23S17 3.2.1 BYTE MODE AND SEQUENTIAL These two modes are not to be confused with single MODE writes/reads and continuous writes/reads that are serial protocol sequences. For example, the device The MCP23X17 family has the ability to operate in Byte may be configured for Byte mode and the master may mode or Sequential mode (IOCON.SEQOP). perform a continuous read. In this case, the Byte mode disables automatic Address Pointer MCP23X17 would not increment the Address Pointer incrementing. When operating in Byte mode, the and would repeatedly drive data from the same MCP23X17 family does not increment its internal location. address counter after each byte during the data transfer. This gives the ability to continually access the 3.2.2 I2C INTERFACE same address by providing extra clocks (without additional control bytes). This is useful for polling the 3.2.2.1 I2C Write Operation GPIO register for data changes or for continually The I2C write operation includes the control byte and writing to the output latches. register address sequence, as shown in Figure3-1. A special mode (Byte mode with IOCON.BANK = 0) This sequence is followed by eight bits of data from the causes the address pointer to toggle between master and an Acknowledge (ACK) from the associated A/B register pairs. For example, if the BANK MCP23017. The operation is ended with a Stop (P) or bit is cleared and the Address Pointer is initially set to Restart (SR) condition being generated by the master. address 12h (GPIOA) or 13h (GPIOB), the pointer will Data is written to the MCP23017 after every byte toggle between GPIOA and GPIOB. Note that the transfer. If a Stop or Restart condition is generated Address Pointer can initially point to either address in during a data transfer, the data will not be written to the the register pair. MCP23017. Sequential mode enables automatic address pointer Both “byte writes” and “sequential writes” are incrementing. When operating in Sequential mode, the supported by the MCP23017. If Sequential mode is MCP23X17 family increments its address counter after enabled (IOCON, SEQOP=0)(default), the each byte during the data transfer. The Address Pointer MCP23017 increments its address counter after each automatically rolls over to address 00h after accessing ACK during the data transfer. the last register. FIGURE 3-1: BYTE AND SEQUENTIAL WRITE S - Start Byte S OP W ADDR DIN P SR - Restart Sequential S OP W ADDR DIN .... DIN P P - Stop W - Write R - Read OP - Device opcode ADDR - Device register address D - Data out from MCP23017 OUT D - Data in to MCP23017 IN  2005-2016 Microchip Technology Inc. DS20001952C-page 13

MCP23017/MCP23S17 3.2.2.2 I2C Read Operation I2C Read operations include the control byte sequence, as shown in Figure3-2. This sequence is followed by another control byte (including the Start condition and ACK) with the R/W bit set (R/W = 1). The MCP23017 then transmits the data contained in the addressed register. The sequence is ended with the master generating a Stop or Restart condition. FIGURE 3-2: BYTE AND SEQUENTIAL READ Byte S OP W SR OP R DOUT P Sequential S OP W SR OP R DOUT .... DOUT P 3.2.2.3 I2C Sequential Write/Read The sequence ends with the master sending a Stop or Restart condition. For sequential operations (Write or Read), instead of transmitting a Stop or Restart condition after the data The MCP23017 Address Pointer will roll over to transfer, the master clocks the next byte pointed to by address zero after reaching the last register address. the address pointer (see Section3.2.1 “Byte Mode Refer to Figure3-3. and Sequential Mode” for details regarding sequential operation control). FIGURE 3-3: MCP23017 I2C DEVICE PROTOCOL S OP W ADDR DIN .... DIN P SR OP R DOUT .... DOUT P SR OP W DIN .... DIN P P S OP R DOUT .... DOUT P SR OP R DOUT .... DOUT P SR OP W ADDR DIN .... DIN P P DS20001952C-page 14  2005-2016 Microchip Technology Inc.

MCP23017/MCP23S17 3.2.3 SPI INTERFACE four fixed bits and three user-defined hardware address bits (pins A2, A1 and A0). Figure3-4 shows 3.2.3.1 SPI Write Operation the control byte format. The SPI write operation is started by lowering CS. The 3.3.2 ADDRESSING SPI DEVICES Write command (slave address with R/W bit cleared) is (MCP23S17) then clocked into the device. The opcode is followed by an address and at least one data byte. The MCP23S17 is a slave SPI device. The slave address contains four fixed bits and three user-defined 3.2.3.2 SPI Read Operation hardware address bits (if enabled via IOCON.HAEN) The SPI read operation is started by lowering CS. The (pins A2, A1 and A0) with the read/write bit filling out SPI read command (slave address with R/W bit set) is the control byte. Figure3-5 shows the control byte then clocked into the device. The opcode is followed by format. The address pins should be externally biased an address, with at least one data byte being clocked even if disabled (IOCON.HAEN = 0). out of the device. FIGURE 3-4: I2C CONTROL BYTE 3.2.3.3 SPI Sequential Write/Read FORMAT For sequential operations, instead of deselecting the Control Byte device by raising CS, the master clocks the next byte pointed to by the Address Pointer. (see Section3.2.1 S 0 1 0 0 A2 A1 A0 R/W ACK “Byte Mode and Sequential Mode” for details regarding sequential operation control). Slave Address The sequence ends by the raising of CS. Start R/W bit The MCP23S17 Address Pointer will roll over to bit ACK bit address zero after reaching the last register address. R/W = 0 = write R/W = 1 = read 3.3 Hardware Address Decoder The hardware address pins are used to determine the FIGURE 3-5: SPI CONTROL BYTE device address. To address a device, the correspond- FORMAT ing address bits in the control byte must match the pin state. The pins must be biased externally. CS 3.3.1 ADDRESSING I2C DEVICES Control Byte (MCP23017) 0 1 0 0 A2 A1 A0 R/W The MCP23017 is a slave I2C interface device that Slave Address supports 7-bit slave addressing, with the read/write bit filling out the control byte. The slave address contains R/W bit R/W = 0 = write R/W = 1 = read FIGURE 3-6: I2C ADDRESSING REGISTERS S 0 1 0 0 A2 A1 A0 0 ACK * A7 A6 A5 A4 A3 A2 A1 A0 ACK * R/W = 0 Device Opcode Register Address *The ACKs are provided by the MCP23017.  2005-2016 Microchip Technology Inc. DS20001952C-page 15

MCP23017/MCP23S17 FIGURE 3-7: SPI ADDRESSING REGISTERS CS 0 1 0 0 A2 * A1 * A0 * R/W A7 A6 A5 A4 A3 A2 A1 A0 Device Opcode Register Address * Address pins are enabled/disabled via IOCON.HAEN. 3.4 GPIO Port Reading the GPIOn register reads the value on the port. Reading the OLATn register only reads the The GPIO module is a general purpose, 16-bit wide, latches, not the actual value on the port. bidirectional port that is functionally split into two Writing to the GPIOn register actually causes a write to 8-bitwide ports. the latches (OLATn). Writing to the OLATn register The GPIO module contains the data ports (GPIOn), forces the associated output drivers to drive to the level internal pull-up resistors and the output latches in OLATn. Pins configured as inputs turn off the (OLATn). associated output driver and put it in high-impedance. TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE GPIO PORTS (BANK = 1) Register Address POR/RST bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Name (hex) value IODIRA 00 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 1111 1111 IPOLA 01 IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 0000 0000 GPINTENA 02 GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 GPINT1 GPINT0 0000 0000 GPPUA 06 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 0000 0000 GPIOA 09 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 0000 0000 OLATA 0A OL7 OL6 OL5 OL4 OL3 OL2 OL1 OL0 0000 0000 IODIRB 10 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 1111 1111 IPOLB 11 IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 0000 0000 GPINTENB 12 GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 GPINT1 GPINT0 0000 0000 GPPUB 16 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 0000 0000 GPIOB 19 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 0000 0000 OLATB 1A OL7 OL6 OL5 OL4 OL3 OL2 OL1 OL0 0000 0000 TABLE 3-3: SUMMARY OF REGISTERS ASSOCIATED WITH THE GPIO PORTS (BANK = 0) Register Address POR/RST bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Name (hex) value IODIRA 00 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 1111 1111 IODIRB 01 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 1111 1111 IPOLA 02 IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 0000 0000 IPOLB 03 IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 0000 0000 GPINTENA 04 GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 GPINT1 GPINT0 0000 0000 GPINTENB 05 GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 GPINT1 GPINT0 0000 0000 GPPUA 0C PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 0000 0000 GPPUB 0D PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 0000 0000 GPIOA 12 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 0000 0000 GPIOB 13 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 0000 0000 OLATA 14 OL7 OL6 OL5 OL4 OL3 OL2 OL1 OL0 0000 0000 OLATB 15 OL7 OL6 OL5 OL4 OL3 OL2 OL1 OL0 0000 0000 DS20001952C-page 16  2005-2016 Microchip Technology Inc.

MCP23017/MCP23S17 3.5 Configuration and Control associated with PORTB. One register (IOCON) is Registers shared between the two ports. The PORTA registers are identical to the PORTB registers, therefore, they There are 21 registers associated with the MCP23X17, will be referred to without differentiating between the as shown in Tables3-4 and3-5. The two tables show port designation (i.e., they will not have the “A” or “B” the register mapping with the two BANK bit values. Ten designator assigned) in the register tables. registers are associated with PORTA and ten are TABLE 3-4: CONTROL REGISTER SUMMARY (IOCON.BANK = 1) Register Address POR/RST bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Name (hex) value IODIRA 00 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 1111 1111 IPOLA 01 IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 0000 0000 GPINTENA 02 GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 GPINT1 GPINT0 0000 0000 DEFVALA 03 DEF7 DEF6 DEF5 DEF4 DEF3 DEF2 DEF1 DEF0 0000 0000 INTCONA 04 IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 0000 0000 IOCON 05 BANK MIRROR SEQOP DISSLW HAEN ODR INTPOL — 0000 0000 GPPUA 06 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 0000 0000 INTFA 07 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INTO 0000 0000 INTCAPA 08 ICP7 ICP6 ICP5 ICP4 ICP3 ICP2 ICP1 ICP0 0000 0000 GPIOA 09 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 0000 0000 OLATA 0A OL7 OL6 OL5 OL4 OL3 OL2 OL1 OL0 0000 0000 IODIRB 10 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 1111 1111 IPOLB 11 IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 0000 0000 GPINTENB 12 GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 GPINT1 GPINT0 0000 0000 DEFVALB 13 DEF7 DEF6 DEF5 DEF4 DEF3 DEF2 DEF1 DEF0 0000 0000 INTCONB 14 IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 0000 0000 IOCON 15 BANK MIRROR SEQOP DISSLW HAEN ODR INTPOL — 0000 0000 GPPUB 16 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 0000 0000 INTFB 17 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INTO 0000 0000 INTCAPB 18 ICP7 ICP6 ICP5 ICP4 ICP3 ICP2 ICP1 ICP0 0000 0000 GPIOB 19 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 0000 0000 OLATB 1A OL7 OL6 OL5 OL4 OL3 OL2 OL1 OL0 0000 0000 TABLE 3-5: CONTROL REGISTER SUMMARY (IOCON.BANK = 0) Register Address POR/RST bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Name (hex) value IODIRA 00 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 1111 1111 IODIRB 01 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 1111 1111 IPOLA 02 IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 0000 0000 IPOLB 03 IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 0000 0000 GPINTENA 04 GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 GPINT1 GPINT0 0000 0000 GPINTENB 05 GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 GPINT1 GPINT0 0000 0000 DEFVALA 06 DEF7 DEF6 DEF5 DEF4 DEF3 DEF2 DEF1 DEF0 0000 0000 DEFVALB 07 DEF7 DEF6 DEF5 DEF4 DEF3 DEF2 DEF1 DEF0 0000 0000 INTCONA 08 IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 0000 0000 INTCONB 09 IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 0000 0000 IOCON 0A BANK MIRROR SEQOP DISSLW HAEN ODR INTPOL — 0000 0000 IOCON 0B BANK MIRROR SEQOP DISSLW HAEN ODR INTPOL — 0000 0000 GPPUA 0C PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 0000 0000 GPPUB 0D PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 0000 0000  2005-2016 Microchip Technology Inc. DS20001952C-page 17

MCP23017/MCP23S17 TABLE 3-5: CONTROL REGISTER SUMMARY (IOCON.BANK = 0) (CONTINUED) Register Address POR/RST bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Name (hex) value INTFA 0E INT7 INT6 INT5 INT4 INT3 INT2 INT1 INTO 0000 0000 INTFB 0F INT7 INT6 INT5 INT4 INT3 INT2 INT1 INTO 0000 0000 INTCAPA 10 ICP7 ICP6 ICP5 ICP4 ICP3 ICP2 ICP1 ICP0 0000 0000 INTCAPB 11 ICP7 ICP6 ICP5 ICP4 ICP3 ICP2 ICP1 ICP0 0000 0000 GPIOA 12 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 0000 0000 GPIOB 13 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 0000 0000 OLATA 14 OL7 OL6 OL5 OL4 OL3 OL2 OL1 OL0 0000 0000 OLATB 15 OL7 OL6 OL5 OL4 OL3 OL2 OL1 OL0 0000 0000 3.5.1 I/O DIRECTION REGISTER Controls the direction of the data I/O. When a bit is set, the corresponding pin becomes an input. When a bit is clear, the corresponding pin becomes an output. REGISTER 3-1: IODIR: I/O DIRECTION REGISTER (ADDR 0x00) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 IO<7:0>: Controls the direction of data I/O <7:0> 1 = Pin is configured as an input. 0 = Pin is configured as an output. 3.5.2 INPUT POLARITY REGISTER This register allows the user to configure the polarity on the corresponding GPIO port bits. If a bit is set, the corresponding GPIO register bit will reflect the inverted value on the pin. REGISTER 3-2: IPOL: INPUT POLARITY PORT REGISTER (ADDR 0x01) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 IP<7:0>: Controls the polarity inversion of the input pins <7:0> 1 = GPIO register bit reflects the opposite logic state of the input pin. 0 = GPIO register bit reflects the same logic state of the input pin. DS20001952C-page 18  2005-2016 Microchip Technology Inc.

MCP23017/MCP23S17 3.5.3 INTERRUPT-ON-CHANGE CONTROL REGISTER The GPINTEN register controls the interrupt-on-change feature for each pin. If a bit is set, the corresponding pin is enabled for interrupt-on-change. The DEFVAL and INTCON registers must also be configured if any pins are enabled for interrupt-on-change. REGISTER 3-3: GPINTEN: INTERRUPT-ON-CHANGE PINS (ADDR 0x02)(Note1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 GPINT1 GPINT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 GPINT<7:0>: General purpose I/O interrupt-on-change bits <7:0> 1 = Enables GPIO input pin for interrupt-on-change event. 0 = Disables GPIO input pin for interrupt-on-change event. Note 1: Refer to INTCON. 3.5.4 DEFAULT COMPARE REGISTER FOR INTERRUPT-ON-CHANGE The default comparison value is configured in the DEFVAL register. If enabled (via GPINTEN and INTCON) to compare against the DEFVAL register, an opposite value on the associated pin will cause an interrupt to occur. REGISTER 3-4: DEFVAL: DEFAULT VALUE REGISTER (ADDR 0x03) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DEF7 DEF6 DEF5 DEF4 DEF3 DEF2 DEF1 DEF0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 DEF<7:0>: Sets the compare value for pins configured for interrupt-on-change from defaults <7:0> (Note1) If the associated pin level is the opposite from the register bit, an interrupt occurs. (Note2) Note 1: Refer to INTCON. 2: Refer to INTCON and GPINTEN.  2005-2016 Microchip Technology Inc. DS20001952C-page 19

MCP23017/MCP23S17 3.5.5 INTERRUPT CONTROL REGISTER The INTCON register controls how the associated pin value is compared for the interrupt-on-change feature. If a bit is set, the corresponding I/O pin is compared against the associated bit in the DEFVAL register. If a bit value is clear, the corresponding I/O pin is compared against the previous value. REGISTER 3-5: INTCON: INTERRUPT-ON-CHANGE CONTROL REGISTER (ADDR 0x04)(Note1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 IOC<7:0>: Controls how the associated pin value is compared for interrupt-on-change <7:0> 1 = Pin value is compared against the associated bit in the DEFVAL register. 0 = Pin value is compared against the previous pin value. Note 1: Refer to INTCON and GPINTEN. 3.5.6 CONFIGURATION REGISTER For this reason, when changing the BANK bit, it is advised to only perform byte writes to this register. The IOCON register contains several bits for configuring the device: The MIRROR bit controls how the INTA and INTB pins function with respect to each other. The BANK bit changes how the registers are mapped (see Tables3-4 and3-5 for more details). • When MIRROR = 1, the INTn pins are functionally OR’ed so that an interrupt on either port will cause • If BANK = 1, the registers associated with each both pins to activate. port are segregated. Registers associated with PORTA are mapped from address 00h - 0Ah and • When MIRROR = 0, the INT pins are separated. registers associated with PORTB are mapped Interrupt conditions on a port will cause its from 10h - 1Ah. respective INT pin to activate. • If BANK = 0, the A/B registers are paired. For The Sequential Operation (SEQOP) controls the example, IODIRA is mapped to address 00h and incrementing function of the Address Pointer. If the IODIRB is mapped to the next address (address address pointer is disabled, the Address Pointer does 01h). The mapping for all registers is from 00h not automatically increment after each byte is clocked -15h. during a serial transfer. This feature is useful when it is desired to continuously poll (read) or modify (write) a It is important to take care when changing the BANK bit register. as the address mapping changes after the byte is clocked into the device. The address pointer may point The Slew Rate (DISSLW) bit controls the slew rate to an invalid location after the bit is modified. function on the SDA pin. If enabled, the SDA slew rate will be controlled when driving from a high to low. For example, if the device is configured to automatically increment its internal Address Pointer, The Hardware Address Enable (HAEN) bit the following scenario would occur: enables/disables hardware addressing on the MCP23S17 only. The address pins (A2, A1 and A0) • BANK = 0 must be externally biased, regardless of the HAEN bit • Write 80h to address 0Ah (IOCON) to set the value. BANK bit If enabled (HAEN = 1), the device’s hardware address • Once the write completes, the internal address matches the address pins. now points to 0Bh which is an invalid address when the BANK bit is set. If disabled (HAEN = 0), the device’s hardware address is A2 = A1 = A0 = 0. DS20001952C-page 20  2005-2016 Microchip Technology Inc.

MCP23017/MCP23S17 The Open-Drain (ODR) control bit enables/disables the The Interrupt Polarity (INTPOL) sets the polarity of the INT pin for open-drain configuration. Setting this bit INT pin. This bit is functional only when the ODR bit is overrides the INTPOL bit. cleared, configuring the INT pin as active push-pull. REGISTER 3-6: IOCON: I/O EXPANDER CONFIGURATION REGISTER (ADDR 0x05) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 BANK MIRROR SEQOP DISSLW HAEN ODR INTPOL — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 BANK: Controls how the registers are addressed 1 = The registers associated with each port are separated into different banks. 0 = The registers are in the same bank (addresses are sequential). bit 6 MIRROR: INT Pins Mirror bit 1 = The INT pins are internally connected 0 = The INT pins are not connected. INTA is associated with PORTA and INTB is associated with PORTB bit 5 SEQOP: Sequential Operation mode bit 1 = Sequential operation disabled, address pointer does not increment. 0 = Sequential operation enabled, address pointer increments. bit 4 DISSLW: Slew Rate control bit for SDA output 1 = Slew rate disabled 0 = Slew rate enabled bit 3 HAEN: Hardware Address Enable bit (MCP23S17 only) (Note1) 1 = Enables the MCP23S17 address pins. 0 = Disables the MCP23S17 address pins. bit 2 ODR: Configures the INT pin as an open-drain output 1 = Open-drain output (overrides the INTPOL bit.) 0 = Active driver output (INTPOL bit sets the polarity.) bit 1 INTPOL: This bit sets the polarity of the INT output pin 1 = Active-high 0 = Active-low bit 0 Unimplemented: Read as ‘0’ Note 1: Address pins are always enabled on the MCP23017.  2005-2016 Microchip Technology Inc. DS20001952C-page 21

MCP23017/MCP23S17 3.5.7 PULL-UP RESISTOR CONFIGURATION REGISTER The GPPU register controls the pull-up resistors for the port pins. If a bit is set and the corresponding pin is configured as an input, the corresponding port pin is internally pulled up with a 100k resistor. REGISTER 3-7: GPPU: GPIO PULL-UP RESISTOR REGISTER (ADDR 0x06) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 PU<7:0> Controls the weak pull-up resistors on each pin (when configured as an input) 1 = Pull-up enabled 0 = Pull-up disabled 3.5.8 INTERRUPT FLAG REGISTER The INTF register reflects the interrupt condition on the port pins of any pin that is enabled for interrupts via the GPINTEN register. A set bit indicates that the associated pin caused the interrupt. This register is read-only. Writes to this register will be ignored. REGISTER 3-8: INTF: INTERRUPT FLAG REGISTER (ADDR 0x07) R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 INT<7:0>: Reflects the interrupt condition on the port. It reflects the change only if interrupts are enabled per GPINTEN<7:0>. 1 = Pin caused interrupt. 0 = Interrupt not pending DS20001952C-page 22  2005-2016 Microchip Technology Inc.

MCP23017/MCP23S17 3.5.9 INTERRUPT CAPTURED REGISTER The INTCAP register captures the GPIO port value at the time the interrupt occurred. The register is read-only and is updated only when an interrupt occurs. The register remains unchanged until the interrupt is cleared via a read of INTCAP or GPIO. REGISTER 3-9: INTCAP: INTERRUPT CAPTURED VALUE FOR PORT REGISTER (ADDR 0x08) R-x R-x R-x R-x R-x R-x R-x R-x ICP7 ICP6 ICP5 ICP4 ICP3 ICP2 ICP1 ICP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 ICP<7:0>: Reflects the logic level on the port pins at the time of interrupt due to pin change <7:0> 1 = Logic-high 0 = Logic-low 3.5.10 PORT REGISTER The GPIO register reflects the value on the port. Reading from this register reads the port. Writing to this register modifies the Output Latch (OLAT) register. REGISTER 3-10: GPIO: GENERAL PURPOSE I/O PORT REGISTER (ADDR 0x09) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 GP<7:0>: Reflects the logic level on the pins <7:0> 1 = Logic-high 0 = Logic-low  2005-2016 Microchip Technology Inc. DS20001952C-page 23

MCP23017/MCP23S17 3.5.11 OUTPUT LATCH REGISTER (OLAT) The OLAT register provides access to the output latches. A read from this register results in a read of the OLAT and not the port itself. A write to this register modifies the output latches that modifies the pins configured as outputs. REGISTER 3-11: OLAT: OUTPUT LATCH REGISTER 0 (ADDR 0x0A) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OL7 OL6 OL5 OL4 OL3 OL2 OL1 OL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 OL<7:0>: Reflects the logic level on the output latch <7:0> 1 = Logic-high 0 = Logic-low 3.6 Interrupt Logic If IOCON.MIRROR = 1, the internal signals are OR’ed together and routed to the INTn pads. In this case, the If enabled, the MCP23X17 activates the INTn interrupt interrupt will only be cleared if the associated GPIO or output when one of the port pins changes state or when INTCAP is read (see Table3-6). a pin does not match the preconfigured default. Each pin is individually configurable as follows: TABLE 3-6: INTERRUPT OPERATION • Enable/disable interrupt via GPINTEN (IOCON.MIRROR = 1) • Can interrupt on either pin change or change from Interrupt Interrupt default as configured in DEFVAL Read PORTn (1) Condition Result Both conditions are referred to as Interrupt-on-Change PORTA Clear (IOC). GPIOA PORTB Unchanged The interrupt control module uses the following PORTA Unchanged registers/bits: GPIOB PORTB Clear • IOCON.MIRROR – controls if the two interrupt pins mirror each other PORTA Unchanged • GPINTEN – Interrupt enable register GPIOA and PORTB Unchanged • INTCON – controls the source for the IOC GPIOB Both PORTA and Clear • DEFVAL – contains the register default for IOC PORTB operation Note 1: PORTn = GPIOn or INTCAPn 3.6.1 INTA AND INTB 3.6.2 IOC FROM PIN CHANGE There are two interrupt pins: INTA and INTB. By If enabled, the MCP23X17 generates an interrupt if a default, INTA is associated with GPAn pins (PORTA) mismatch condition exists between the current port and INTB is associated with GPBn pins (PORTB). value and the previous port value. Only IOC-enabled Each port has an independent signal which is cleared if pins will be compared. Refer to Registers3-3 and 3-5. its associated GPIO or INTCAP register is read. 3.6.3 IOC FROM REGISTER DEFAULT 3.6.1.1 Mirroring the INT pins If enabled, the MCP23X17 generates an interrupt if a Additionally, the INTn pins can be configured to mirror mismatch occurs between the DEFVAL register and each other so that any interrupt will cause both pins to the port. Only IOC enabled pins are compared. Refer to go active. This is controlled via IOCON.MIRROR. Registers3-3, 3-4 and 3-5. If IOCON.MIRROR = 0, the internal signals are routed independently to the INTA and INTB pads. DS20001952C-page 24  2005-2016 Microchip Technology Inc.

MCP23017/MCP23S17 3.6.4 INTERRUPT OPERATION FIGURE 3-8: INTERRUPT-ON-PIN CHANGE The INTn interrupt output can be configured as active-low, active-high or open-drain via the IOCON register. GPx Only those pins that are configured as an input (IODIR register) with Interrupt-On-Change (IOC) enabled (IOINTEN register) can cause an interrupt. Pins defined as an output have no effect on the interrupt INT ACTIVE ACTIVE output pin. Port value Read GPIO Port value Input change activity on a port input pin that is enabled is captured or INTCAP is captured for IOC generates an internal device interrupt and the into INTCAP into INTCAP device captures the value of the port and copies it into INTCAP. The interrupt remains active until the INTCAP or GPIO register is read. Writing to these registers does FIGURE 3-9: INTERRUPT-ON-CHANGE not affect the interrupt. The interrupt condition is FROM REGISTER cleared after the LSb of the data is clocked out during DEFAULT a read command of GPIO or INTCAP. The first interrupt event causes the port contents to be DEFVAL REGISTER copied into the INTCAP register. Subsequent interrupt conditions on the port will not cause an interrupt to GPx<7:0> 7 6 5 4 3 2 1 0 occur as long as the interrupt is not cleared by a read X X X X X 0 X X of INTCAP or GPIO. Note: The value in INTCAP can be lost if GPIO is read before INTCAP while another IOC GP2 is pending. After reading GPIO, the Pin interrupt will clear and then set due to the pending IOC, causing the INTCAP register to update. INT ACTIVE ACTIVE Pin 3.6.5 INTERRUPT CONDITIONS There are two possible configurations that cause Port value interrupts (configured via INTCON): is captured Read GPIO 1. Pins configured for interrupt-on-pin change into INTCAP or INTCAP (INT clears only if interrupt will cause an interrupt to occur if a pin changes to the opposite state. The default state is reset condition does not exist.) after an interrupt occurs and after clearing the interrupt condition (i.e., after reading GPIO or INTCAP). For example, an interrupt occurs by an input changing from ‘1’ to ‘0’. The new initial state for the pin is a logic ‘0’ after the interrupt is cleared. 2. Pins configured for interrupt-on-change from register value will cause an interrupt to occur if the corresponding input pin differs from the register bit. The interrupt condition will remain as long as the condition exists, regardless if the INTCAP or GPIO is read. See Figures3-8 and 3-9 for more information on interrupt operations.  2005-2016 Microchip Technology Inc. DS20001952C-page 25

MCP23017/MCP23S17 4.0 PACKAGING INFORMATION 4.1 Package Marking Information 28-Lead QFN Example: 23017 E/MLe3 1628256 28-Lead SOIC Example: MCP23017-E/SOe3 1628256 28-Lead SPDIP Example: XXXXXXXXXXXXXXXXX MCP23017-E/SPe3 XXXXXXXXXXXXXXXXX 1628256 YYWWNN 28-Lead SSOP Example: XXXXXXXXXXXX MCP23017 XXXXXXXXXXXX E/SSe3 YYWWNNN 1628256 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. DS20001952C-page 26  2005-2016 Microchip Technology Inc.

MCP23017/MCP23S17  2005-2016 Microchip Technology Inc. DS20001952C-page 27

MCP23017/MCP23S17 DS20001952C-page 28  2005-2016 Microchip Technology Inc.

MCP23017/MCP23S17 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:7)(cid:8)(cid:9)(cid:18)(cid:11)(cid:7)(cid:13)(cid:19)(cid:9)(cid:20)(cid:21)(cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:7)(cid:15)(cid:22)(cid:7)(cid:23)(cid:6)(cid:9)(cid:24)(cid:25)(cid:5)(cid:26)(cid:9)(cid:27)(cid:9)(cid:28)(cid:29)(cid:28)(cid:9)(cid:30)(cid:30)(cid:9)(cid:31)(cid:21)(cid:8) (cid:9)!(cid:16)(cid:18)(cid:20)" #(cid:14)(cid:13)$(cid:9)%&’’(cid:9)(cid:30)(cid:30)(cid:9)((cid:21))(cid:13)(cid:7)(cid:15)(cid:13)(cid:9)(cid:5)(cid:6))(cid:23)(cid:13)$ (cid:20)(cid:21)(cid:13)(cid:6)* (cid:30)(cid:10)(cid:9)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2) (cid:10)!(cid:31)(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)(cid:31)(cid:2)(cid:12)(cid:28)(cid:8)#(cid:28)(cid:17)(cid:14)(cid:2)$(cid:9)(cid:28)%(cid:7)(cid:15)(cid:17)!&(cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)’(cid:28)(cid:8)#(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)((cid:7)(cid:8)(cid:28)(cid:31)(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)(cid:31)(cid:14)$(cid:2)(cid:28)(cid:31)(cid:2) (cid:11)(cid:31)(cid:31)(cid:12))**%%%(cid:20) (cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10) *(cid:12)(cid:28)(cid:8)#(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)  2005-2016 Microchip Technology Inc. DS20001952C-page 29

MCP23017/MCP23S17 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20001952C-page 30  2005-2016 Microchip Technology Inc.

MCP23017/MCP23S17 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2005-2016 Microchip Technology Inc. DS20001952C-page 31

MCP23017/MCP23S17 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20001952C-page 32  2005-2016 Microchip Technology Inc.

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(cid:20)(cid:4)(cid:29)(cid:23) (cid:20)(cid:4)(cid:29)< (cid:20)(cid:4)(cid:3)(cid:3) :,(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)(cid:26)(cid:10)%(cid:2)(cid:22)(cid:12)(cid:28)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:2)/ (cid:14)5 = = (cid:20)(cid:23)1(cid:4) (cid:20)(cid:21)(cid:13)(cid:6)(cid:12)* (cid:29)(cid:20) ’(cid:7)(cid:15)(cid:2)(cid:29)(cid:2),(cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)$(cid:14)-(cid:2)((cid:14)(cid:28)(cid:31)"(cid:9)(cid:14)(cid:2) (cid:28)(cid:18)(cid:2),(cid:28)(cid:9)(cid:18)&(cid:2)."(cid:31)(cid:2) "!(cid:31)(cid:2).(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)(cid:31)(cid:14)$(cid:2)%(cid:7)(cid:31)(cid:11)(cid:7)(cid:15)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)(cid:31)(cid:8)(cid:11)(cid:14)$(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) /(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)((cid:7)(cid:8)(cid:28)(cid:15)(cid:31)(cid:2)0(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)(cid:31)(cid:14)(cid:9)(cid:7)!(cid:31)(cid:7)(cid:8)(cid:20) 1(cid:20) (cid:21)(cid:7) (cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)$(cid:2)2(cid:29)(cid:2)$(cid:10)(cid:2)(cid:15)(cid:10)(cid:31)(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"$(cid:14)(cid:2) (cid:10)(cid:16)$(cid:2)((cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)(cid:31)(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)$(cid:2)((cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)(cid:31)(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)(cid:31)(cid:2)(cid:14)-(cid:8)(cid:14)(cid:14)$(cid:2)(cid:20)(cid:4)(cid:29)(cid:4)3(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)$(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7) (cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)$(cid:2)(cid:31)(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6)2(cid:2)4(cid:29)(cid:23)(cid:20)+(cid:6)(cid:20) 5(cid:22)0) 5(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7) (cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)(cid:31)(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)-(cid:28)(cid:8)(cid:31)(cid:2),(cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)%(cid:15)(cid:2)%(cid:7)(cid:31)(cid:11)(cid:10)"(cid:31)(cid:2)(cid:31)(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)%(cid:7)(cid:15)(cid:17)0(cid:4)(cid:23)(cid:27)(cid:4)(cid:5)(cid:4)5  2005-2016 Microchip Technology Inc. DS20001952C-page 33

MCP23017/MCP23S17 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)+$/(cid:14))(cid:22)(cid:9)+(cid:30)(cid:7)(cid:11)(cid:11)(cid:9)0(cid:17)(cid:13)(cid:11)(cid:14))(cid:6)(cid:9)(cid:24)++(cid:26)(cid:9)(cid:27)(cid:9)’&.%(cid:9)(cid:30)(cid:30)(cid:9)(cid:31)(cid:21)(cid:8) (cid:9)!++0(cid:10)" (cid:20)(cid:21)(cid:13)(cid:6)* (cid:30)(cid:10)(cid:9)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2) (cid:10)!(cid:31)(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)(cid:31)(cid:2)(cid:12)(cid:28)(cid:8)#(cid:28)(cid:17)(cid:14)(cid:2)$(cid:9)(cid:28)%(cid:7)(cid:15)(cid:17)!&(cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)’(cid:28)(cid:8)#(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)((cid:7)(cid:8)(cid:28)(cid:31)(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)(cid:31)(cid:14)$(cid:2)(cid:28)(cid:31)(cid:2) (cid:11)(cid:31)(cid:31)(cid:12))**%%%(cid:20) (cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10) *(cid:12)(cid:28)(cid:8)#(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D N E E1 1 2 b NOTE1 e c A A2 φ A1 L1 L 6(cid:15)(cid:7)(cid:31)! (cid:6)(cid:19)99(cid:19)(cid:6)2(cid:13)2(cid:26)(cid:22) (cid:21)(cid:7) (cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7) (cid:7)(cid:31)! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7" .(cid:14)(cid:9)(cid:2)(cid:10)((cid:2)’(cid:7)(cid:15)! 7 (cid:3)< ’(cid:7)(cid:31)(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)?+(cid:2)5(cid:22)0 :,(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)(cid:31) (cid:25) = = (cid:3)(cid:20)(cid:4)(cid:4) (cid:6)(cid:10)(cid:16)$(cid:14)$(cid:2)’(cid:28)(cid:8)#(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)#(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:29)(cid:20)?+ (cid:29)(cid:20)(cid:5)+ (cid:29)(cid:20)<+ (cid:22)(cid:31)(cid:28)(cid:15)$(cid:10)(((cid:2) (cid:25)(cid:29) (cid:4)(cid:20)(cid:4)+ = = :,(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)$(cid:31)(cid:11) 2 (cid:5)(cid:20)(cid:23)(cid:4) (cid:5)(cid:20)<(cid:4) <(cid:20)(cid:3)(cid:4) (cid:6)(cid:10)(cid:16)$(cid:14)$(cid:2)’(cid:28)(cid:8)#(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)$(cid:31)(cid:11) 2(cid:29) +(cid:20)(cid:4)(cid:4) +(cid:20)1(cid:4) +(cid:20)?(cid:4) :,(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)(cid:31)(cid:11) (cid:21) (cid:24)(cid:20)(cid:24)(cid:4) (cid:29)(cid:4)(cid:20)(cid:3)(cid:4) (cid:29)(cid:4)(cid:20)+(cid:4) (cid:30)(cid:10)(cid:10)(cid:31)(cid:2)9(cid:14)(cid:15)(cid:17)(cid:31)(cid:11) 9 (cid:4)(cid:20)++ (cid:4)(cid:20)(cid:5)+ (cid:4)(cid:20)(cid:24)+ (cid:30)(cid:10)(cid:10)(cid:31)(cid:12)(cid:9)(cid:7)(cid:15)(cid:31) 9(cid:29) (cid:29)(cid:20)(cid:3)+(cid:2)(cid:26)2(cid:30) 9(cid:14)(cid:28)$(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)#(cid:15)(cid:14)!! (cid:8) (cid:4)(cid:20)(cid:4)(cid:24) = (cid:4)(cid:20)(cid:3)+ (cid:30)(cid:10)(cid:10)(cid:31)(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)@ (cid:23)@ <@ 9(cid:14)(cid:28)$(cid:2)>(cid:7)$(cid:31)(cid:11) . (cid:4)(cid:20)(cid:3)(cid:3) = (cid:4)(cid:20)1< (cid:20)(cid:21)(cid:13)(cid:6)(cid:12)* (cid:29)(cid:20) ’(cid:7)(cid:15)(cid:2)(cid:29)(cid:2),(cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)$(cid:14)-(cid:2)((cid:14)(cid:28)(cid:31)"(cid:9)(cid:14)(cid:2) (cid:28)(cid:18)(cid:2),(cid:28)(cid:9)(cid:18)&(cid:2)."(cid:31)(cid:2) "!(cid:31)(cid:2).(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)(cid:31)(cid:14)$(cid:2)%(cid:7)(cid:31)(cid:11)(cid:7)(cid:15)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)(cid:31)(cid:8)(cid:11)(cid:14)$(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7) (cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)$(cid:2)2(cid:29)(cid:2)$(cid:10)(cid:2)(cid:15)(cid:10)(cid:31)(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"$(cid:14)(cid:2) (cid:10)(cid:16)$(cid:2)((cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)(cid:31)(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)$(cid:2)((cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)(cid:31)(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)(cid:31)(cid:2)(cid:14)-(cid:8)(cid:14)(cid:14)$(cid:2)(cid:4)(cid:20)(cid:3)(cid:4)(cid:2) (cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)$(cid:14)(cid:20) 1(cid:20) (cid:21)(cid:7) (cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)$(cid:2)(cid:31)(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6)2(cid:2)4(cid:29)(cid:23)(cid:20)+(cid:6)(cid:20) 5(cid:22)0) 5(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7) (cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)(cid:31)(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)-(cid:28)(cid:8)(cid:31)(cid:2),(cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)%(cid:15)(cid:2)%(cid:7)(cid:31)(cid:11)(cid:10)"(cid:31)(cid:2)(cid:31)(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26)2(cid:30)) (cid:26)(cid:14)((cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7) (cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)&(cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)%(cid:7)(cid:31)(cid:11)(cid:10)"(cid:31)(cid:2)(cid:31)(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)&(cid:2)((cid:10)(cid:9)(cid:2)(cid:7)(cid:15)((cid:10)(cid:9) (cid:28)(cid:31)(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)%(cid:7)(cid:15)(cid:17)0(cid:4)(cid:23)(cid:27)(cid:4)(cid:5)15 DS20001952C-page 34  2005-2016 Microchip Technology Inc.

MCP23017/MCP23S17 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2005-2016 Microchip Technology Inc. DS20001952C-page 35

MCP23017/MCP23S17 NOTES: DS20001952C-page 36  2005-2016 Microchip Technology Inc.

MCP23017/MCP23S17 APPENDIX A: REVISION HISTORY Revision C (July 2016) The following is the list of modifications: 1. Added ESD data to Section1.0, Electrical Characteristics. 2. Updated Table2-1. 3. Updated package outline drawings. 4. Minor typographical errors Revision B (February 2007) 1. Changed Byte and Sequential Read in Figure1-1 from “R” to “W”. 2. Table 2-4, Param No. 51 and 53: Changed from 450 to 600 and 500 to 600, respecively. 3. Added disclaimers to package outline drawings. 4. Updated package outline drawings. Revision A (June 2005) • Original release of this document.  2005-2016 Microchip Technology Inc. DS20001952C-page 37

MCP23017/MCP23S17 NOTES: DS20001952C-page 38  2005-2016 Microchip Technology Inc.

MCP23017/MCP23S17 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. – X /XX X (1) Examples: a) MCP23017-E/ML: Extended temperature, Device Temperature Package Tape and Reel 28LD QFN package Range Option b) MCP23017T-E/ML: Extended temperature, 28LD QFN package, Tape and Reel Device: MCP23017: 16-Bit I/O Expander with I2C Interface c) MCP23017-E/SP: Extended temperature , MCP23S17: 16-Bit I/O Expander with SPI Interface 28LD SPDIP package d) MCP23017-E/SO: Extended temperature, 28LD SOIC package Temperature E = -40C to +125C (Extended) e) MCP23017T-E/SO: Extended temperature, Range: 28LD SOIC package, Tape and Reel f) MCP23017-E/SS: Extended temperature, Package: ML = Plastic Quad Flat, No Lead Package, 6x6mm Body, QFN, 28-lead 28LD SSOP package SO = Plastic Small Outline, Wide, 7.50 mm Body, SOIC, g) MCP23017T-E/SS: Extended temperature, 28-Lead 28LD SSOP package, SP = Skinny Plastic Dual In-Line, 300 mil Body, SPDIP, Tape and Reel 28-Lead SS = Plastic Shrink Small Outline, 5.30mm Body, SSOP, 28-Lead a) MCP23S17-E/ML: Extended temperature, 28LD QFN package b) MCP23S17T-E/ML: Extended temperature, TapeandReel T = Tape and Reel (1) 28LD QFN package, Option: Blank = Tube Tape and Reel c) MCP23S17-E/SP: Extended temperature, 28LD SPDIP package d) MCP23S17-E/SO: Extended temperature, 28LD SOIC package e) MCP23S17T-E/SO: Extended temperature, 28LD SOIC package, Tape and Reel f) MCP23S17-E/SS: Extended temperature, 28LD SSOP package g) MCP23S17T-E/SS: Extended temperature, 28LD SSOP package Tape and Reel Note1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option.  2005-2016 Microchip Technology Inc. DS20001952C-page 39

MCP23017/MCP23S17 NOTES: DS20001952C-page 40  2005-2016 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, AnyRate, and may be superseded by updates. It is your responsibility to dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, ensure that your application meets with your specifications. KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST, MICROCHIP MAKES NO REPRESENTATIONS OR MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, WARRANTIES OF ANY KIND WHETHER EXPRESS OR RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O IMPLIED, WRITTEN OR ORAL, STATUTORY OR are registered trademarks of Microchip Technology OTHERWISE, RELATED TO THE INFORMATION, Incorporated in the U.S.A. and other countries. INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR ClockWorks, The Embedded Control Solutions Company, FITNESS FOR PURPOSE. Microchip disclaims all liability ETHERSYNCH, Hyper Speed Control, HyperLight Load, arising from this information and its use. Use of Microchip IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are devices in life support and/or safety applications is entirely at registered trademarks of Microchip Technology Incorporated the buyer’s risk, and the buyer agrees to defend, indemnify and in the U.S.A. hold harmless Microchip from any and all damages, claims, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, suits, or expenses resulting from such use. No licenses are BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, conveyed, implicitly or otherwise, under any Microchip dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, intellectual property rights unless otherwise stated. EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker, Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Silicon Storage Technology is a registered trademark of Tempe, Arizona; Gresham, Oregon and design centers in California Microchip Technology Inc. in other countries. and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping GestIC is a registered trademarks of Microchip Technology devices, Serial EEPROMs, microperipherals, nonvolatile memory and Germany II GmbH & Co. KG, a subsidiary of Microchip analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. QUALITY MANAGEMENT SYSTEM © 2005-2016, Microchip Technology Incorporated, Printed in CERTIFIED BY DNV the U.S.A., All Rights Reserved. ISBN: 978-1-5224-0755-3 == ISO/TS 16949 ==  2005-2016 Microchip Technology Inc. DS20001952C-page 41

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