MCP23008/MCP23S08 8-Bit I/O Expander with Serial Interface Features Package Types • 8-bit remote bidirectional I/O port MCP23008 PDIP/SOIC - I/O pins default to input (cid:129) High-speed I 2C™ interface (MCP23008) SCL 1 18 VDD SDA 2 17 GP7 - 100kHz A2 3 16 GP6 - 400kHz 8 A1 4 0 15 GP5 0 - 1.7MHz A0 5 23 14 GP4 (cid:129) High-speed SPI™ interface ( MCP23S08) RESET 6 CP 13 GP3 - 10MHz NC 7 M 12 GP2 (cid:129) Hardware address pins INT 8 11 GP1 - Three for the MCP23008 to allow up to eight VSS 9 10 GP0 devices on the bus SSOP - Two for the MCP23S08 to allow up to four devices using the same chip-select SCL 1 20 VDD SDA 2 19 GP7 (cid:129) Configurable interrupt output pin A2 3 18 GP6 - Configurable as active-high, active-low or A1 4 8 17 GP5 open-drain A0 5 00 16 GP4 (cid:129) Configurable interrupt source RESET 6 23 15 GP3 P - Interrupt-on-change from configured defaults NC 7 C 14 GP2 or pin change INT 8 M 13 GP1 (cid:129) Polarity Inversion register to configure the polarity VSS 9 12 GP0 of the input port data N/C 10 11 N/C (cid:129) External reset input (cid:129) Low standby current: 1µA (max.) MCP23S08 PDIP/SOIC (cid:129) Operating voltage: - 1.8V to 5.5V @ -40°C to +85°C (I-Temp) SCK 1 18 VDD - 2.7V to 5.5V @ -40°C to +85°C (I-Temp) SI 2 17 GP7 - 4.5V to 5.5V @ -40°C to +125°C (E-Temp) SO 3 8 16 GP6 A1 4 S0 15 GP5 A0 5 3 14 GP4 Packages 2 RESET 6 CP 13 GP3 18-pin PDIP (300mil) CS 7 M 12 GP2 INT 8 11 GP1 18-pin SOIC (300mil) VSS 9 10 GP0 20-pin SSOP SSOP SCK 1 20 VDD SI 2 19 GP7 SO 3 18 GP6 A1 4 8 17 GP5 0 A0 5 S 16 GP4 3 RESET 6 2 15 GP3 P CS 7 C 14 GP2 M INT 8 13 GP1 VSS 9 12 GP0 N/C 10 11 N/C © 2005 Microchip Technology Inc. DS21919B-page 1

MCP23008/MCP23S08 Block Diagram MCP23S08 SCK SI SO MCP23008 SCL Serial Serializer/ GP0 SDA Interface Deserializer 8 GP1 MCP23S08 GP2 3 GP3 A1:A0 A2:A0 Decode GPIO GP4 Control GP5 RESET GP6 Interrupt GP7 INT Logic 8 VDD POR Configuration/ Control VSS Registers DS21919B-page 2 © 2005 Microchip Technology Inc.

MCP23008/MCP23S08 1.0 DEVICE OVERVIEW The interrupt output can be configured to activate under two conditions (mutually exclusive): The MCP23X08 device provides 8-bit, general purpose, parallel I/O expansion for I2C bus or SPI 1. When any input state differs from its corresponding input port register state. This is applications. The two devices differ in the number of used to indicate to the system master that an hardware address pins and the serial interface: input state has changed. (cid:129) MCP23008 – I 2C interface; three address pins 2. When an input state differs from a preconfigured (cid:129) MCP23S08 – SPI interface; two address pins register value (DEFVAL register). The MCP23X08 consists of multiple 8-bit configuration The Interrupt Capture register captures port values at registers for input, output and polarity selection. The the time of the interrupt, thereby saving the condition system master can enable the I/Os as either inputs or that caused the interrupt. outputs by writing the I/O configuration bits. The data The Power-on Reset (POR) sets the registers to their for each input or output is kept in the corresponding default values and initializes the device state machine. Input or Output register. The polarity of the Input Port register can be inverted with the Polarity Inversion The hardware address pins are used to determine the register. All registers can be read by the system master. device address. 1.1 Pin Descriptions TABLE 1-1: PINOUT DESCRIPTION Pin PDIP/S Pin SSOP Function Name OIC Type SCL/SCK 1 1 I Serial clock input. SDA/SI 2 2 I/O Serial data I/O (MCP23008)/Serial data input (MCP23S08). A2/SO 3 3 I/O Hardware address input (MCP23008)/Serial data output (MCP23S08). A2 must be biased externally. A1 4 4 I Hardware address input. Must be biased externally. A0 5 5 I Hardware address input. Must be biased externally. RESET 6 6 I External reset input NC/CS 7 7 I No connect (MCP23008)/External chip select input (MCP23S08). INT 8 8 O Interrupt output. Can be configured for active-high, active-low or open-drain. VSS 9 9 P Ground. GP0 10 12 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor. GP1 11 13 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor. GP2 12 14 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor. GP3 13 15 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor. GP4 14 16 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor. GP5 15 17 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor. GP6 16 18 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor. GP7 17 19 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor. VDD 18 20 P Power. N/C 10, 11 © 2005 Microchip Technology Inc. DS21919B-page 3

MCP23008/MCP23S08 1.2 Power-on Reset (POR) 1.3.2 I2C™ INTERFACE The on-chip POR circuit holds the device in reset until 1.3.2.1 I2C Write Operation VDD has reached a high enough voltage to deactivate The I2C Write operation includes the control byte and the POR circuit (i.e., release the device from reset). register address sequence, as shown in the bottom of The maximum VDD rise time is specified in Section2.0 Figure1-1. This sequence is followed by eight bits of “Electrical Characteristics”. data from the master and an Acknowledge (ACK) from When the device exits the POR condition (releases the MCP23008. The operation is ended with a STOP reset), device operating parameters (i.e., voltage, or RESTART condition being generated by the master. temperature, serial bus frequency, etc.) must be met to Data is written to the MCP23008 after every byte ensure proper operation. transfer. If a STOP or RESTART condition is generated during a data transfer, the data will not be 1.3 Serial Interface written to the MCP23008. This block handles the functionality of the I2C Byte writes and sequential writes are both supported (MCP23008) or SPI (MCP23S08) interface protocol. by the MCP23008. The MCP23008 increments its The MCP23X08 contains eleven registers that can be address counter after each ACK during the data addressed through the serial interface block (Table1-2): transfer. TABLE 1-2: REGISTER ADDRESSES 1.3.2.2 I2C Read Operation Address Access to: The I2C Read operation includes the control byte sequence, as shown in the bottom of Figure1-1. This 00h IODIR sequence is followed by another control byte (includ- 01h IPOL ing the START condition and ACK) with the R/W bit 02h GPINTEN equal to a logic 1 (R/W = 1). The MCP23008 then 03h DEFVAL transmits the data contained in the addressed register. 04h INTCON The sequence is ended with the master generating a STOP or RESTART condition. 05h IOCON 06h GPPU 1.3.2.3 I2C Sequential Write/Read 07h INTF For sequential operations (Write or Read), instead of 08h INTCAP (Read-only) transmitting a STOP or RESTART condition after the 09h GPIO data transfer, the master clocks the next byte pointed to 0Ah OLAT by the address pointer (see Section1.3.1 “Sequential Operation Bit” for details regarding sequential operation control). 1.3.1 SEQUENTIAL OPERATION BIT The sequence ends with the master sending a STOP or The Sequential Operation (SEQOP) bit (IOCON RESTART condition. register) controls the operation of the address pointer. The address pointer can either be enabled (default) to The MCP23008 address pointer will roll over to allow the address pointer to increment automatically address zero after reaching the last register address. after each data transfer, or it can be disabled. Refer to Figure1-1. When operating in Sequential mode (IOCON.SEQOP = 0), the address pointer automati- 1.3.3 SPI™ INTERFACE cally increments to the next address after each byte 1.3.3.1 SPI Write Operation is clocked. When operating in Byte mode (IOCON.SEQOP = 1), The SPI Write operation is started by lowering CS. The Write command (slave address with R/W bit cleared) is the MCP23X08 does not increment its address then clocked into the device. The opcode is followed by counter after each byte during the data transfer. This an address and at least one data byte. gives the ability to continually read the same address by providing extra clocks (without additional control 1.3.3.2 SPI Read Operation bytes). This is useful for polling the GPIO register for data changes. The SPI Read operation is started by lowering CS. The SPI read command (slave address with R/W bit set) is then clocked into the device. The opcode is followed by an address, with at least one data byte being clocked out of the device. DS21919B-page 4 © 2005 Microchip Technology Inc.

MCP23008/MCP23S08 FIGURE 1-1: MCP23008 I2C™ DEVICE PROTOCOL S - START SR - RESTART S OP W ADDR DIN .... DIN P P - STOP w - Write SR OP R DOUT .... DOUT P R - Read OP - Device opcode SR OP W DIN .... DIN P ADDR - Device address P DOUT - Data out from MCP23008 DIN - Data into MCP23008 S OP R DOUT .... DOUT P SR OP R DOUT .... DOUT P SR OP W ADDR DIN .... DIN P P Byte and Sequential Write Byte S OP W ADDR DIN P Sequential S OP W ADDR DIN .... DIN P Byte and Sequential Read Byte S OP R SR OP R DOUT P Sequential S OP R SR OP R DOUT .... DOUT P 1.3.3.3 SPI Sequential Write/Read 1.4 Hardware Address Decoder For sequential operations, instead of deselecting the The hardware address pins are used to determine the device by raising CS, the master clocks the next byte device address. To address a device, the correspond- pointed to by the address pointer. ing address bits in the control byte must match the pin The sequence ends by the raising of CS. state. The MCP23S08 address pointer will roll over to (cid:129) MCP23008 has address pins A2, A1 and A0. address zero after reaching the last register address. (cid:129) MCP23S08 has address pins A1 and A0. The pins must be biased externally. © 2005 Microchip Technology Inc. DS21919B-page 5

MCP23008/MCP23S08 1.4.1 ADDRESSING I2C DEVICES FIGURE 1-2: I2C™ CONTROL BYTE (MCP23008) FORMAT The MCP23008 is a slave I2C device that supports 7-bit Control Byte slave addressing, with the read/write bit filling out the control byte. The slave address contains four fixed bits S 0 1 0 0 A2 A1 A0 R/W ACK and three user-defined hardware address bits (pins A2, A1 and A0). Figure1-2 shows the control byte format. Slave Address 1.4.2 ADDRESSING SPI DEVICES Start R/W bit (MCP23S08) bit ACK bit R/W = 0 = write The MCP23S08 is a slave SPI device. The slave R/W = 1 = read address contains five fixed bits and two user-defined hardware address bits (pins A1 and A0), with the read/write bit filling out the control byte. Figure1-3 FIGURE 1-3: SPI™ CONTROL BYTE shows the control byte format. FORMAT CS Control Byte 0 1 0 0 0 A1 A0 R/W Slave Address R/W bit R/W = 0 = write R/W = 1 = read FIGURE 1-4: I2C™ ADDRESSING REGISTERS S 0 1 0 0 A2 A1 A0 0 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK R/W = 0 Device Opcode Register Address The ACKs are provided by the MCP23008. FIGURE 1-5: SPI™ ADDRESSING REGISTERS CS 0 1 0 0 0 A1 A0 R/W A7 A6 A5 A4 A3 A2 A1 A0 Device Opcode Register Address DS21919B-page 6 © 2005 Microchip Technology Inc.

MCP23008/MCP23S08 1.5 GPIO Port 1.6 Configuration and Control Registers The GPIO module contains the data port (GPIO), internal pull up resistors and the Output Latches The Configuration and Control blocks contain the (OLAT). registers as shown in Table1-3. Reading the GPIO register reads the value on the port. Reading the OLAT register only reads the OLAT, not the actual value on the port. Writing to the GPIO register actually causes a write to the OLAT. Writing to the OLAT register forces the associated output drivers to drive to the level in OLAT. Pins configured as inputs turn off the associated output driver and put it in high-impedance. TABLE 1-3: CONFIGURATION AND CONTROL REGISTERS Register Address POR/RST bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Name (hex) value IODIR 00 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 1111 1111 IPOL 01 IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 0000 0000 GPINTEN 02 GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 GPINT1 GPINT0 0000 0000 DEFVAL 03 DEF7 DEF6 DEF5 DEF4 DEF3 DEF2 DEF1 DEF0 0000 0000 INTCON 04 IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 0000 0000 IOCON 05 — — SREAD DISSLW HAEN * ODR INTPOL — --00 000- GPPU 06 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 0000 0000 INTF 07 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INTO 0000 0000 INTCAP 08 ICP7 ICP6 ICP5 ICP4 ICP3 ICP2 ICP1 ICP0 0000 0000 GPIO 09 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 0000 0000 OLAT 0A OL7 OL6 OL5 OL4 OL3 OL2 OL1 OL0 0000 0000 * Not used on the MCP23008. © 2005 Microchip Technology Inc. DS21919B-page 7

MCP23008/MCP23S08 1.6.1 I/O DIRECTION (IODIR) REGISTER Controls the direction of the data I/O. When a bit is set, the corresponding pin becomes an input. When a bit is clear, the corresponding pin becomes an output. REGISTER 1-1: IODIR – I/O DIRECTION REGISTER (ADDR 0x00) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 bit 7 bit 0 bit 7-0 IO7:IO0: These bits control the direction of data I/O <7:0>. 1 = Pin is configured as an input. 0 = Pin is configured as an output. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS21919B-page 8 © 2005 Microchip Technology Inc.

MCP23008/MCP23S08 1.6.2 INPUT POLARITY (IPOL) REGISTER The IPOL register allows the user to configure the polarity on the corresponding GPIO port bits. If a bit is set, the corresponding GPIO register bit will reflect the inverted value on the pin. REGISTER 1-2: IPOL – INPUT POLARITY PORT REGISTER (ADDR 0x01) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 bit 7 bit 0 bit 7-0 IP7:IP0: These bits control the polarity inversion of the input pins <7:0>. 1 = GPIO register bit will reflect the opposite logic state of the input pin. 0 = GPIO register bit will reflect the same logic state of the input pin. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2005 Microchip Technology Inc. DS21919B-page 9

MCP23008/MCP23S08 1.6.3 INTERRUPT-ON-CHANGE CONTROL (GPINTEN) REGISTER The GPINTEN register controls the interrupt-on- change feature for each pin. If a bit is set, the corresponding pin is enabled for interrupt-on-change. The DEFVAL and INTCON registers must also be configured if any pins are enabled for interrupt-on-change. REGISTER 1-3: GPINTEN – INTERRUPT-ON-CHANGE PINS (ADDR 0x02) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 GPINT1 GPINT0 bit 7 bit 0 bit 7-0 GPINT7:GPINT0: General purpose I/O interrupt-on-change bits <7:0>. 1 = Enable GPIO input pin for interrupt-on-change event. 0 = Disable GPIO input pin for interrupt-on-change event. Refer to INTCON and GPINTEN. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS21919B-page 10 © 2005 Microchip Technology Inc.

MCP23008/MCP23S08 1.6.4 DEFAULT COMPARE (DEFVAL) REGISTER FOR INTERRUPT-ON- CHANGE The default comparison value is configured in the DEFVAL register. If enabled (via GPINTEN and INTCON) to compare against the DEFVAL register, an opposite value on the associated pin will cause an interrupt to occur. REGISTER 1-4: DEFVAL – DEFAULT VALUE REGISTER (ADDR 0x03) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DEF7 DEF6 DEF5 DEF4 DEF3 DEF2 DEF1 DEF0 bit 7 bit 0 bit 7-0 DEF7:DEF0: These bits set the compare value for pins configured for interrupt-on-change from defaults <7:0>. Refer to INTCON. If the associated pin level is the opposite from the register bit, an interrupt occurs. Refer to INTCON and GPINTEN. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2005 Microchip Technology Inc. DS21919B-page 11

MCP23008/MCP23S08 1.6.5 INTERRUPT CONTROL (INTCON) REGISTER The INTCON register controls how the associated pin value is compared for the interrupt-on-change feature. If a bit is set, the corresponding I/O pin is compared against the associated bit in the DEFVAL register. If a bit value is clear, the corresponding I/O pin is compared against the previous value. REGISTER 1-5: INTCON – INTERRUPT-ON-CHANGE CONTROL REGISTER (ADDR 0x04) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 bit 7 bit 0 bit 7-0 IOC7:IOC0: These bits control how the associated pin value is compared for interrupt-on- change <7:0>. 1 = Controls how the associated pin value is compared for interrupt-on-change. 0 = Pin value is compared against the previous pin value. Refer to INTCON and GPINTEN. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS21919B-page 12 © 2005 Microchip Technology Inc.

MCP23008/MCP23S08 1.6.6 CONFIGURATION (IOCON) (cid:129) The Hardware Address Enable (HAEN) control bit REGISTER enables/disables the hardware address pins (A2, A1) on the MCP23S08. This bit is not used on the The IOCON register contains several bits for MCP23008. The address pins are always enabled configuring the device: on the MCP23008. (cid:129) The Sequential Operation (SEQOP) controls the (cid:129) The Open-Drain (ODR) control bit incrementing function of the address pointer. If enables/disables the INT pin for open-drain the address pointer is disabled, the address configuration. pointer does not automatically increment after (cid:129) The Interrupt Polarity (INTPOL) control bit sets each byte is clocked during a serial transfer. This the polarity of the INT pin. This bit is functional feature is useful when it is desired to continuously only when the ODR bit is cleared, configuring the poll (read) or modify (write) a register. INT pin as active push-pull. (cid:129) The Slew Rate (DISSLW) bit controls the slew rate function on the SDA pin. If enabled, the SDA slew rate will be controlled when driving from a high to a low. REGISTER 1-6: IOCON – I/O EXPANDER CONFIGURATION REGISTER (ADDR 0x05) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 — — SEQOP DISSLW HAEN ODR INTPOL — bit 7 bit 0 bit 7-6 Unimplemented: Read as ‘0’. bit 5 SEQOP: Sequential Operation mode bit. 1 = Sequential operation disabled, address pointer does not increment. 0 = Sequential operation enabled, address pointer increments. bit 4 DISSLW: Slew Rate control bit for SDA output. 1 = Slew rate disabled. 0 = Slew rate enabled. bit 3 HAEN: Hardware Address Enable bit (MCP23S08 only). Address pins are always enabled on MCP23008. 1 = Enables the MCP23S08 address pins. 0 = Disables the MCP23S08 address pins. bit 2 ODR: This bit configures the INT pin as an open-drain output. 1 = Open-drain output (overrides the INTPOL bit). 0 = Active driver output (INTPOL bit sets the polarity). bit 1 INTPOL: This bit sets the polarity of the INT output pin. 1 = Active-high. 0 = Active-low. bit 0 Unimplemented: Read as ‘0’. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2005 Microchip Technology Inc. DS21919B-page 13

MCP23008/MCP23S08 1.6.7 PULL-UP RESISTOR CONFIGURATION (GPPU) REGISTER The GPPU register controls the pull-up resistors for the port pins. If a bit is set and the corresponding pin is configured as an input, the corresponding port pin is internally pulled up with a 100kΩ resistor. REGISTER 1-7: GPPU – GPIO PULL-UP RESISTOR REGISTER (ADDR 0x06) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 bit 7 bit 0 bit 7-0 PU7:PU0: These bits control the weak pull-up resistors on each pin (when configured as an input) <7:0>. 1 = Pull-up enabled. 0 = Pull-up disabled. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS21919B-page 14 © 2005 Microchip Technology Inc.

MCP23008/MCP23S08 1.6.8 INTERRUPT FLAG (INTF) Note: INTF will always reflect the pin(s) that REGISTER have an interrupt condition. For example, The INTF register reflects the interrupt condition on the one pin causes an interrupt to occur and is port pins of any pin that is enabled for interrupts via the captured in INTCAP and INF. If, before GPINTEN register. A ‘set’ bit indicates that the clearing the interrupt, another pin changes associated pin caused the interrupt. which would normally cause an interrupt, it will be reflected in INTF, but not INTCAP. This register is ‘read-only’. Writes to this register will be ignored. REGISTER 1-8: INTF – INTERRUPT FLAG REGISTER (ADDR 0x07) R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 bit 7 bit 0 bit 7-0 INT7:INT0: These bits reflect the interrupt condition on the port. Will reflect the change only if interrupts are enabled (GPINTEN) <7:0>. 1 = Pin caused interrupt. 0 = Interrupt not pending. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2005 Microchip Technology Inc. DS21919B-page 15

MCP23008/MCP23S08 1.6.9 INTERRUPT CAPTURE (INTCAP) REGISTER The INTCAP register captures the GPIO port value at the time the interrupt occurred. The register is ‘read- only’ and is updated only when an interrupt occurs. The register will remain unchanged until the interrupt is cleared via a read of INTCAP or GPIO. REGISTER 1-9: INTCAP – INTERRUPT CAPTURED VALUE FOR PORT REGISTER (ADDR 0x08) R-x R-x R-x R-x R-x R-x R-x R-x ICP7 ICP6 ICP5 ICP4 ICP3 ICP2 ICP1 ICP0 bit 7 bit 0 bit 7-0 ICP7:ICP0: These bits reflect the logic level on the port pins at the time of interrupt due to pin change <7:0>. 1 = Logic-high. 0 = Logic-low. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS21919B-page 16 © 2005 Microchip Technology Inc.

MCP23008/MCP23S08 1.6.10 PORT (GPIO) REGISTER The GPIO register reflects the value on the port. Reading from this register reads the port. Writing to this register modifies the Output Latch (OLAT) register. REGISTER 1-10: GPIO – GENERAL PURPOSE I/O PORT REGISTER (ADDR 0x09) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 bit 7 bit 0 bit 7-0 GP7:GP0: These bits reflect the logic level on the pins <7:0>. 1 = Logic-high. 0 = Logic-low. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2005 Microchip Technology Inc. DS21919B-page 17

MCP23008/MCP23S08 1.6.11 OUTPUT LATCH REGISTER (OLAT) The OLAT register provides access to the output latches. A read from this register results in a read of the OLAT and not the port itself. A write to this register modifies the output latches that modify the pins configured as outputs. REGISTER 1-11: OLAT – OUTPUT LATCH REGISTER 0 (ADDR 0x0A) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OL7 OL6 OL5 OL4 OL3 OL2 OL1 OL0 bit 7 bit 0 bit 7-0 OL7:OL0: These bits reflect the logic level on the output latch <7:0>. 1 = Logic-high. 0 = Logic-low. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS21919B-page 18 © 2005 Microchip Technology Inc.

MCP23008/MCP23S08 1.7 Interrupt Logic FIGURE 1-6: INTERRUPT-ON-PIN- CHANGE The interrupt output pin will activate if an internal interrupt occurs. The interrupt block is configured by GPx the following registers: (cid:129) GPINTEN – enables the individual inputs (cid:129) DEFVAL – holds the values that are compared against the associated input port values INT ACTIVE ACTIVE (cid:129) INTCON – controls if the input values are compared against DEFVAL or the previous values Port value Read GPIU Port value on the port is captured or INTCAP is captured (cid:129) IOCON (ODR and INPOL) – configures the INT into INTCAP into INTCAP pin as push-pull, open-drain and active-level Only pins configured as inputs can cause interrupts. FIGURE 1-7: INTERRUPT-ON-CHANGE Pins configured as outputs have no affect on INT. FROM REGISTER Interrupt activity on the port will cause the port value to DEFAULT be captured and copied into INTCAP. The interrupt will remain active until the INTCAP or GPIO register is DEFVAL read. Writing to these registers will not affect the interrupt. GP: 7 6 5 4 3 2 1 0 The first interrupt event will cause the port contents to X X X X X 0 X X be copied into the INTCAP register. Subsequent interrupt conditions on the port will not cause an interrupt to occur as long as the interrupt is not cleared GP2 by a read of INTCAP or GPIO. 1.7.1 INTERRUPT CONDITIONS There are two possible configurations to cause INT ACTIVE ACTIVE interrupts (configured via INTCON): 1. Pins configured for interrupt-on-pin-change will cause an interrupt to occur if a pin changes Port value to the opposite state. The default state is reset is captured Read GPIU after an interrupt occurs. For example, an into INTCAP or INTCAP interrupt occurs by an input changing from 1 to (INT clears only if interrupt 0. The new initial state for the pin is a logic 0. condition does not exist.) 2. Pins configured for interrupt-on-change from register value will cause an interrupt to occur if the corresponding input pin differs from the register bit. The interrupt condition will remain as long as the condition exists, regardless if the INTAP or GPIO is read. See Figure1-6 and Figure1-7 for more information on interrupt operations. © 2005 Microchip Technology Inc. DS21919B-page 19

MCP23008/MCP23S08 NOTES: DS21919B-page 20 © 2005 Microchip Technology Inc.

MCP23008/MCP23S08 2.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +5.5V Voltage on all other pins with respect to VSS (except VDD).............................................................-0.6V to (VDD + 0.6V) Total power dissipation (Note).............................................................................................................................700mW Maximum current out of VSS pin...........................................................................................................................150mA Maximum current into VDD pin..............................................................................................................................125mA Input clamp current, IIK (VI < 0 or VI > VDD)......................................................................................................................±20mA Output clamp current, IOK (VO < 0 or VO > VDD)..............................................................................................................±20mA Maximum output current sunk by any output pin....................................................................................................25mA Maximum output current sourced by any output pin...............................................................................................25mA Note: Power dissipation is calculated as follows: PDIS = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOL x IOL) † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. © 2005 Microchip Technology Inc. DS21919B-page 21

MCP23008/MCP23S08 2.1 DC Characteristics Operating Conditions (unless otherwise indicated): DC Characteristics 1.8V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +85°C (I-Temp) 4.5V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +125°C (E-Temp) (Note1) Param Characteristic Sym Min Typ Max Units Conditions No. D001 Supply Voltage VDD 1.8 — 5.5 V D002 VDD Start Voltage to VPOR — VSS — V Ensure Power-on Reset D003 VDD Rise Rate to SVDD 0.05 — — V/ms Design guidance only. Ensure Power-on Not tested. Reset D004 Supply Current IDD — — 1 mA SCL/SCK = 1MHz D005 Standby current IDDS — — 1 µA — — 2 µA 4.5V - 5.5V @ +125°C (Note1) Input Low-Voltage D030 A0, A1 (TTL buffer) VIL VSS — 0.15VDD V D031 CS, GPIO, SCL/SCK, VSS — 0.2VDD V SDA, A2, RESET (Schmitt Trigger) Input High-Voltage D040 A0, A1 VIH 0.25VDD + 0.8 — VDD V (TTL buffer) D041 CS, GPIO, SCL/SCK, 0.8VDD — VDD V For entire VDD range. SDA, A2, RESET (Schmitt Trigger) Input Leakage Current D060 I/O port pins IIL — — ±1 µA VSS ≤ VPIN ≤ VDD Output Leakage Current D065 I/O port pins ILO — — ±1 µA VSS ≤ VPIN ≤ VDD D070 GPIO weak pull-up IPU 40 75 115 µA VDD = 5V, GP Pins = VSS current –40°C ≤ TA ≤ +85°C Output Low-Voltage D080 GPIO VOL — — 0.6 V IOL = 8.5mA, VDD = 4.5V INT — — 0.6 V IOL = 1.6mA, VDD = 4.5V SO, SDA — — 0.6 V IOL = 3.0mA, VDD = 1.8V SDA — — 0.8 V IOL = 3.0mA, VDD = 4.5V Output High-Voltage D090 GPIO, INT, SO VOH VDD – 0.7 — — V IOH = -3.0mA, VDD = 4.5V VDD – 0.7 — — IOH = -400µA, VDD = 1.8V Capacitive Loading Specs on Output Pins D101 GPIO, SO, INT CIO — — 50 pF D102 SDA CB — — 400 pF Note 1: This parameter is characterized, not 100% tested. DS21919B-page 22 © 2005 Microchip Technology Inc.

MCP23008/MCP23S08 FIGURE 2-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS VDD Pin 1kΩ SCL and 50pF SDA pin MCP23008 135pF FIGURE 2-2: RESET AND DEVICE RESET TIMER TIMING VDD RESET 30 32 Internal RESET 34 Output pin © 2005 Microchip Technology Inc. DS21919B-page 23

MCP23008/MCP23S08 TABLE 2-1: DEVICE RESET SPECIFICATIONS Operating Conditions (unless otherwise indicated): AC Characteristics 1.8V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +85°C (I-Temp) 4.5V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +125°C (E-Temp) (Note1) Param Characteristic Sym Min Typ(1) Max Units Conditions No. 30 RESET Pulse Width TRSTL 1 — — µs (Low) 32 Device Active After Reset THLD — TBD µs VDD = 5.0V high 34 Output High-Impedance TIOZ — — 1 µs From RESET Low Note 1: This parameter is characterized, not 100% tested. FIGURE 2-3: I2C™ BUS START/STOP BITS TIMING SCL 91 93 90 92 SDA START STOP Condition Condition FIGURE 2-4: I2C™ BUS DATA TIMING 103 100 102 101 SCL 90 106 91 107 92 SDA In 109 109 110 SDA Out DS21919B-page 24 © 2005 Microchip Technology Inc.

MCP23008/MCP23S08 TABLE 2-2: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE) Operating Conditions (unless otherwise indicated): I2C™ AC Characteristics 1.8V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +85°C (I-Temp) 4.5V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +125°C (E-Temp) (Note1) RPU (SCL, SDA) = 1kΩ, CL (SCL, SDA) = 135pF Param Characteristic Sym Min Typ Max Units Conditions No. 100 Clock High Time: THIGH 100kHz mode 4.0 — — µs 1.8V – 5.5V (I-Temp) 400kHz mode 0.6 — — µs 2.7V – 5.5V (I-Temp) 1.7MHz mode 0.12 — — µs 4.5V – 5.5V (E-Temp) 101 Clock Low Time: TLOW 100kHz mode 4.7 — — µs 1.8V – 5.5V (I-Temp) 400kHz mode 1.3 — — µs 2.7V – 5.5V (I-Temp) 1.7MHz mode 0.32 — — µs 4.5V – 5.5V (E-Temp) 102 SDA and SCL Rise Time: TR 100kHz mode (Note1) — — 1000 ns 1.8V – 5.5V (I-Temp) 400kHz mode 20 + 0.1CB(2) — 300 ns 2.7V – 5.5V (I-Temp) 1.7MHz mode 20 — 160 ns 4.5V – 5.5V (E-Temp) 103 SDA and SCL Fall Time: TF 100kHz mode (Note1) — — 300 ns 1.8V – 5.5V (I-Temp) 400kHz mode 20 + 0.1CB(2) — 300 ns 2.7V – 5.5V (I-Temp) 1.7MHz mode 20 — 80 ns 4.5V – 5.5V (E-Temp) 90 START Condition Setup Time: TSU:STA 100kHz mode 4.7 — — µs 1.8V – 5.5V (I-Temp) 400kHz mode 0.6 — — µs 2.7V – 5.5V (I-Temp) 1.7MHz mode 0.16 — — µs 4.5V – 5.5V (E-Temp) 91 START Condition Hold Time: THD:STA 100kHz mode 4.0 — — µs 1.8V – 5.5V (I-Temp) 400kHz mode 0.6 — — µs 2.7V – 5.5V (I-Temp) 1.7MHz mode 0.16 — — µs 4.5V – 5.5V (E-Temp) 106 Data Input Hold Time: THD:DAT 100kHz mode 0 — 3.45 µs 1.8V – 5.5V (I-Temp) 400kHz mode 0 — 0.9 µs 2.7V – 5.5V (I-Temp) 1.7MHz mode 0 — 0.15 µs 4.5V – 5.5V (E-Temp) 107 Data Input Setup Time: TSU:DAT 100kHz mode 250 — — ns 1.8V – 5.5V (I-Temp) 400kHz mode 100 — — ns 2.7V – 5.5V (I-Temp) 1.7MHz mode 0.01 — — µs 4.5V – 5.5V (E-Temp) 92 STOP Condition Setup Time: TSU:STO 100kHz mode 4.0 — — µs 1.8V – 5.5V (I-Temp) 400kHz mode 0.6 — — µs 2.7V – 5.5V (I-Temp) 1.7MHz mode 0.16 — — µs 4.5V – 5.5V (E-Temp) Note 1: This parameter is characterized, not 100% tested. 2: CB is specified to be from 10 to 400pF. © 2005 Microchip Technology Inc. DS21919B-page 25

MCP23008/MCP23S08 TABLE 2-2: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED) Operating Conditions (unless otherwise indicated): I2C™ AC Characteristics 1.8V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +85°C (I-Temp) 4.5V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +125°C (E-Temp) (Note1) RPU (SCL, SDA) = 1kΩ, CL (SCL, SDA) = 135pF Param Characteristic Sym Min Typ Max Units Conditions No. 109 Output Valid From Clock: TAA 100kHz mode — — 3.45 µs 1.8V – 5.5V (I-Temp) 400kHz mode — — 0.9 µs 2.7V – 5.5V (I-Temp) 1.7MHz mode — — 0.18 µs 4.5V – 5.5V (E-Temp) 110 Bus Free Time: TBUF 100kHz mode 4.7 — — µs 1.8V – 5.5V (I-Temp) 400kHz mode 1.3 — — µs 2.7V – 5.5V (I-Temp) 1.7MHz mode N/A — N/A µs 4.5V – 5.5V (E-Temp) Bus Capacitive Loading: CB 100kHz and 400kHz — — 400 pF (Note1) 1.7MHz — — 100 pF (Note1) Input Filter Spike TSP Suppression: (SDA and SCL) 100kHz and 400kHz — — 50 ns 1.7MHz — — 10 ns Spike suppression off Note 1: This parameter is characterized, not 100% tested. 2: CB is specified to be from 10 to 400pF. FIGURE 2-5: SPI™ INPUT TIMING 3 CS 11 1 6 10 Mode 1,1 7 2 SCK Mode 0,0 4 5 SI MSb in LSb in SO high-impedance DS21919B-page 26 © 2005 Microchip Technology Inc.

MCP23008/MCP23S08 FIGURE 2-6: SPI™ OUTPUT TIMING CS 2 8 9 SCK Mode 1,1 Mode 0,0 12 14 13 SO MSb out LSb out don’t care SI TABLE 2-3: SPI™ INTERFACE AC CHARACTERISTICS Operating Conditions (unless otherwise indicated): SPI™ Interface AC Characteristics 1.8V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +85°C (I-Temp) 4.5V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +125°C (E-Temp) (Note1) Param Characteristic Sym Min Typ Max Units Conditions No. Clock Frequency FCLK — — 5 MHz 1.8V – 5.5V (I-Temp) — — 10 MHz 2.7V – 5.5V (I-Temp) — — 10 MHz 4.5V – 5.5V (E-Temp) 1 CS Setup Time TCSS 50 — — ns 2 CS Hold Time TCSH 100 — — ns 1.8V – 5.5V (I-Temp) 50 — — ns 2.7V – 5.5V (I-Temp) 50 — — ns 4.5V – 5.5V (E-Temp) 3 CS Disable Time TCSD 100 — — ns 1.8V – 5.5V (I-Temp) 50 — — ns 2.7V – 5.5V (I-Temp) 50 — — ns 4.5V – 5.5V (E-Temp) 4 Data Setup Time TSU 20 — — ns 1.8V – 5.5V (I-Temp) 10 — — ns 2.7V – 5.5V (I-Temp) 10 — — ns 4.5V – 5.5V (E-Temp) 5 Data Hold Time THD 20 — — ns 1.8V – 5.5V (I-Temp) 10 — — ns 2.7V – 5.5V (I-Temp) 10 — — ns 4.5V – 5.5V (E-Temp) 6 CLK Rise Time TR — — 2 µs Note1 7 CLK Fall Time TF — — 2 µs Note1 8 Clock High Time THI 90 — — ns 1.8V – 5.5V (I-Temp) 45 — — ns 2.7V – 5.5V (I-Temp) 45 — — ns 4.5V – 5.5V (E-Temp) Note 1: This parameter is characterized, not 100% tested. 2: TV = 90 ns (max) when address pointer rolls over from address 0x0A to 0x00. © 2005 Microchip Technology Inc. DS21919B-page 27

MCP23008/MCP23S08 TABLE 2-3: SPI™ INTERFACE AC CHARACTERISTICS (CONTINUED) Operating Conditions (unless otherwise indicated): SPI™ Interface AC Characteristics 1.8V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +85°C (I-Temp) 4.5V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +125°C (E-Temp) (Note1) Param Characteristic Sym Min Typ Max Units Conditions No. 9 Clock Low Time TLO 90 — — ns 1.8V – 5.5V (I-Temp) 45 — — ns 2.7V – 5.5V (I-Temp) 45 — — ns 4.5V – 5.5V (E-Temp) 10 Clock Delay Time TCLD 50 — — ns 11 Clock Enable Time TCLE 50 — — ns 12 Output Valid from Clock Low TV — — 90 ns 1.8V – 5.5V (I-Temp) — — 45 ns 2.7V – 5.5V (I-Temp) — — 45 ns 4.5V – 5.5V (E-Temp) 13 Output Hold Time THO 0 — — ns 14 Output Disable Time TDIS — — 100 ns Note 1: This parameter is characterized, not 100% tested. 2: TV = 90 ns (max) when address pointer rolls over from address 0x0A to 0x00. FIGURE 2-7: GPIO AND INT TIMING SCL/SCK SDA/SI In D1 D0 LSb of data byte zero during a write or read command, depending on parameter. 50 GPn Output Pin 51 INT Pin INT pin active inactive 53 GPn Input Pin 52 Register Loaded DS21919B-page 28 © 2005 Microchip Technology Inc.

MCP23008/MCP23S08 TABLE 2-4: GP AND INT PINS Operating Conditions (unless otherwise indicated): AC Characteristics 1.8V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +85°C (I-Temp) 4.5V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +125°C (E-Temp) (Note1) Param Characteristic Sym Min Typ Max Units Conditions No. 50 Serial data to output valid TGPOV — — 500 ns 51 Interrupt pin disable time TINTD — — 450 ns 52 GP input change to register TGPIV — — 450 ns valid 53 IOC event to INT active TGPINT — — 500 ns Glitch Filter on GP Pins TGLITCH — — 150 ns Note 1: This parameter is characterized, not 100% tested © 2005 Microchip Technology Inc. DS21919B-page 29

MCP23008/MCP23S08 NOTES: DS21919B-page 30 © 2005 Microchip Technology Inc.

MCP23008/MCP23S08 3.0 PACKAGING INFORMATION 3.1 Package Marking Information 18-Lead PDIP (300 mil) Example: XXXXXXXXXXXXXXXXX MCP23008-E/P^e^3 XXXXXXXXXXXXXXXXX YYWWNNN 0434256 18-Lead SOIC (300 mil) Example: XXXXXXXXXXXX MCP23008 XXXXXXXXXXXX E/SO^e^3 XXXXXXXXXXXX YYWWNNN 0434256 20-Lead SSOP Example: XXXXXXXXXXXX MCP23S08 XXXXXXXXXXXX XXXXXXXEXSXSX^Xe^X3 YYWWNNN 0434256 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2005 Microchip Technology Inc. DS21919B-page 31

MCP23008/MCP23S08 18-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n 1 α E A2 A c L A1 B1 β B p eB Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 18 18 Pitch p .100 2.54 Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32 Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26 Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60 Overall Length D .890 .898 .905 22.61 22.80 22.99 Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43 Lead Thickness c .008 .012 .015 0.20 0.29 0.38 Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78 Lower Lead Width B .014 .018 .022 0.36 0.46 0.56 Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92 Mold Draft Angle Top α 5 10 15 5 10 15 Mold Draft Angle Bottom β 5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-007 DS21919B-page 32 © 2005 Microchip Technology Inc.

MCP23008/MCP23S08 18-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC) E p E1 D 2 B n 1 h α 45° c A A2 φ β L A1 Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 18 18 Pitch p .050 1.27 Overall Height A .093 .099 .104 2.36 2.50 2.64 Molded Package Thickness A2 .088 .091 .094 2.24 2.31 2.39 Standoff § A1 .004 .008 .012 0.10 0.20 0.30 Overall Width E .394 .407 .420 10.01 10.34 10.67 Molded Package Width E1 .291 .295 .299 7.39 7.49 7.59 Overall Length D .446 .454 .462 11.33 11.53 11.73 Chamfer Distance h .010 .020 .029 0.25 0.50 0.74 Foot Length L .016 .033 .050 0.41 0.84 1.27 Foot Angle φ 0 4 8 0 4 8 Lead Thickness c .009 .011 .012 0.23 0.27 0.30 Lead Width B .014 .017 .020 0.36 0.42 0.51 Mold Draft Angle Top α 0 12 15 0 12 15 Mold Draft Angle Bottom β 0 12 15 0 12 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-013 Drawing No. C04-051 © 2005 Microchip Technology Inc. DS21919B-page 33

MCP23008/MCP23S08 20-Lead Plastic Shrink Small Outline (SS) – 209 mil Body, 5.30 mm (SSOP) E E1 p D B 2 n 1 c A A2 f L A1 Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 20 20 Pitch p .026 0.65 Overall Height A - - .079 - - 2.00 Molded Package Thickness A2 .065 .069 .073 1.65 1.75 1.85 Standoff A1 .002 - - 0.05 - - Overall Width E .291 .307 .323 7.40 7.80 8.20 Molded Package Width E1 .197 .209 .220 5.00 5.30 5.60 Overall Length D .272 .283 .289 .295 7.20 7.50 Foot Length L .022 .030 .037 0.55 0.75 0.95 Lead Thickness c .004 - .010 0.09 - 0.25 Foot Angle f 0° 4° 8° 0° 4° 8° Lead Width B .009 - .015 0.22 - 0.38 *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MO-150 Drawing No. C04-072 Revised 11/03/03 DS21919B-page 34 © 2005 Microchip Technology Inc.

MCP23008/MCP23S08 APPENDIX A: REVISION HISTORY Revision B (February 2005) The following is the list of modifications: 1. Section1.6 “Configuration and Control Reg- isters”. Added Hardware Address Enable (HAEN) bit to Table 1-3. 2. Section1.6.6 “Configuration (IOCON) Regis- ter”. Added Hardware Address Enable (HAEN) bit to Register 1-6. Revision A (December 2004) Original Release of this Document. © 2005 Microchip Technology Inc. DS21919B-page 35

MCP23008/MCP23S08 NOTES: DS21919B-page 36 © 2005 Microchip Technology Inc.

MCP23008/MCP23S08 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. – X /XX Examples: a) MCP23008-E/P: Extended Temp., Device Temperature Package 18LD PDIP package. Range b) MCP23008-E/SO: Extended Temp., 18LD SOIC package. Device MCP23008: 8-Bit I/O Expander w/ I2C™ Interface c) MCP23008T-E/SO: Tape and Reel, MCP23008T: 8-Bit I/O Expander w/ I2C Interface Extended Temp., (Tape and Reel) 18LD SOIC package. MCP23S08: 8-Bit I/O Expander w/ SPI™ Interface d) MCP23008-E/SS: Extended Temp., MCP23S08T: 8-Bit I/O Expander w/ SPI Interface 20LD SSOP package. (Tape and Reel) e) MCP23008T-E/SS: Tape and Reel, Extended Temp., 20LD SSOP package. Temperature E = -40°C to +125°C (Extended) * Range a) MCP23S08-E/P: Extended Temp., 18LD PDIP package. * While these devices are only offered in the “E” b) MCP23S08-E/SO: Extended Temp., temperature range, the device will operate at different 18LD SOIC package. voltages and temperatures as identified in the Section2.0 “Electrical Characteristics”. c) MCP23S08T-E/SO:Tape and Reel, Extended Temp., 18LD SOIC package. d) MCP23S08-E/SS: Extended Temp., Package P = Plastic DIP (300 mil Body), 18-Lead 20LD SSOP package. SO = Plastic SOIC (300 mil Body), 18-Lead e) MCP23S08T-E/SS: Tape and Reel, SS = SSOP, (209 mil Body, 5.30 mm), 20-Lead Extended Temp., 20LD SSOP package. © 2005 Microchip Technology Inc. DS21919B-page 37

MCP23008/MCP23S08 NOTES: DS21919B-page 38 © 2005 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: (cid:129) Microchip products meet the specification contained in their particular Microchip Data Sheet. (cid:129) Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. (cid:129) There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. (cid:129) Microchip is willing to work with the customer who is concerned about the integrity of their code. (cid:129) Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, Accuron, and may be superseded by updates. It is your responsibility to dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. PROMATE, PowerSmart, rfPIC, and SmartShunt are MICROCHIP MAKES NO REPRESENTATIONS OR WAR- registered trademarks of Microchip Technology Incorporated RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, in the U.S.A. and other countries. WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, PICMASTER, SEEVAL, SmartSensor and The Embedded MERCHANTABILITY OR FITNESS FOR PURPOSE. Control Solutions Company are registered trademarks of Microchip disclaims all liability arising from this information and Microchip Technology Incorporated in the U.S.A. its use. Use of Microchip’s products as critical components in Analog-for-the-Digital Age, Application Maestro, dsPICDEM, life support systems is not authorized except with express dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, written approval by Microchip. No licenses are conveyed, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial implicitly or otherwise, under any Microchip intellectual property Programming, ICSP, ICEPIC, MPASM, MPLIB, MPLINK, rights. MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance and WiperLock are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2005, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company’s quality system processes and procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2005 Microchip Technology Inc. DS21919B-page 39

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