MCP23018/MCP23S18 16-Bit I/O Expander with Open-Drain Outputs Features • Configurable interrupt source: - Interrupt-on-change from configured defaults • 16-bit remote bidirectional I/O port: or pin change - I/O pins default to input • Polarity inversion register to configure the polarity • Open-drain outputs: of the input port data - 5.5V tolerant • External reset input - 25mA sink capable (per pin) • Low standby current: - 400mA total - 1µA (-40°C ≤ TA ≤ +85°C) • High-speed I2C™ interface: (MCP23018) - 6µA (+85°C ≤ TA ≤ +125°C) - 100kHz • Operating voltage: - 400kHz - 1.8V to 5.5V - 3.4MHz • High-speed SPI interface: (MCP23S18) Packages - 10MHz: 2.7V ≤ VDD ≤ 5.5V 28-pin PDIP (300mil) • Single hardware address pin: (MCP23018) 28-pin SOIC (300mil) - Voltage input to allow up to eight devices on the bus 24-pin SSOP (MCP23018 only) • Configurable interrupt output pins: 24-pin QFN (4x4 [mm]) - Configurable as active-high, active-low or open-drain Block Diagram MCP23S18 CS SCK SI SPI SO Open-drain MCP23018 GPB7 SCL Serializer/ I2C GPB6 SDA Deserializer GPB5 GPIO GPB4 GPB3 Multi-bit ADDR GPB2 Decode Control GPB1 RESET 16 GPB0 INTA Interrupt GPA7 INTB Logic GPA6 8 GPA5 GPA4 GPIO GPA3 Configuration/ GPA2 Control GPA1 Registers GPA0 © 2008 Microchip Technology Inc. DS22103A-page 1

MCP23018/MCP23S18 Package Types: MCP23018 PDIP/SOIC SSOP VSS 1 28 NC VSS 1 24 GPA7 NC 2 27 GPA7 GPB0 2 23 GPA6 GPB0 3 26 GPA6 GPB1 3 22 GPA5 GPB1 4 25 GPA5 GPB2 4 21 GPA4 GPB2 5 24 GPA4 GPB3 5 20 GPA3 GPB3 6 23 GPA3 GPB4 6 19 GPA2 GPB4 7 22 GPA2 GPB5 7 18 GPA1 GPB5 8 21 GPA1 GPB6 8 17 GPA0 GPB6 9 20 GPA0 GPB7 9 16 INTA GPB7 10 19 INTA VDD 10 15 INTB VDD 11 18 INTB SCL 11 14 RESET SCL 12 17 NC SDA 12 13 ADDR SDA 13 16 RESET NC 14 15 ADDR QFN G G G G G P V P P P P B S A A A A 0 S 7 6 5 4 2 2 2 2 2 1 4 3 2 1 0 9 GPB1 1 18 GPA3 GPB2 2 17 GPA2 EP GPB3 3 16 GPA1 25 GPB4 4 15 GPA0 GPB5 5 14 INTA GPB6 6 13 INTB 0 1 2 7 8 9 1 1 1 7 D L A R T B D C D D E P V S S D S G A E R DS22103A-page 2 © 2008 Microchip Technology Inc.

MCP23018/MCP23S18 Package Types: MCP23S18 PDIP/SOIC QFN * VSS 1 28 NC G G G G G P V P P P P NC 2 27 GPA7 B S A A A A 0 S 7 6 5 4 GPB0 3 26 GPA6 2 2 2 2 2 1 GPB1 4 25 GPA5 GPB1 14 3 2 1 0 918 GPA3 GPB2 5 24 GPA4 GPB2 2 17 GPA2 GPB3 6 23 GPA3 EP GPB3 3 16 GPA1 GPB4 7 22 GPA2 25 GPB5 8 21 GPA1 GPB4 4 15 GPA0 GPB6 9 20 GPA0 GPB5 5 14 INTA * GPB7 10 19 INTA GPB6 6 13 RESET VDD 11 18 INTB 0 1 2 7 8 9 1 1 1 CS 12 17 NC SCK 13 16 RESET B7 DD CS CK SI SO P V S SI 14 15 SO G * INTB is not bonded out. Can be controlled in IOCON.MIRROR © 2008 Microchip Technology Inc. DS22103A-page 3

MCP23018/MCP23S18 1.0 DEVICE OVERVIEW There are two interrupt pins, INTA and INTB which can be associated with their respective ports, or can be The MCP23X18 device provides 16-bit, general pur- logically OR’ed together so both pins will activate if pose parallel I/O expansion for I2C bus or SPI either port causes an interrupt. applications. The two devices differ only in the serial The interrupt output can be configured to activate interface. under two conditions (mutually exclusive): • MCP23018 - I2C interface 1. When any input state differs from its • MCP23S18 - SPI interface corresponding input port register state. This is The MCP23X18 consists of multiple 8-bit configuration used to indicate to the system master that an registers for input, output and polarity selection. The input state has changed. system master can enable the I/Os as either inputs or 2. When an input state differs from a pre- outputs by writing the I/O configuration bits. The data configured register value (DEFVAL register). for each input or output is kept in the corresponding The Interrupt Capture register captures port values at input or output register. The polarity of the input port the time of the interrupt, thereby saving the condition register can be inverted with the polarity inversion that caused the interrupt. register. All registers can be read by the system master. The Power-on Reset (POR) sets the registers to their The 16-bit I/O port functionally consists of two (2) 8-bit default values and initializes the device state machine. ports (PORTA and PORTB). The MCP23X18 can be configured to operate in 8-bit mode or 16-bit mode via The hardware address pin is used to determine the IOCON.BANK. device address. DS22103A-page 4 © 2008 Microchip Technology Inc.

MCP23018/MCP23S18 1.1 Pin Descriptions TABLE 1-1: I2C PINOUT DESCRIPTION (MCP23018) 28L Pin 24L 24L Pin PDIP/ Standard Function Name QFN SSOP Type SOIC GPB0 3 24 2 I/O Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. GPB1 4 1 3 I/O Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. GPB2 5 2 4 I/O Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. GPB3 6 3 5 I/O Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. GPB4 7 4 6 I/O Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. GPB5 8 5 7 I/O Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. GPB6 9 6 8 I/O Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. GPB7 10 7 9 I/O Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. V 11 8 10 P Power DD V 1 23 1 P Ground SS SCL 12 9 11 I Serial clock input SDA 13 10 12 I/O Serial data I/O ADDR 15 11 13 I Hardware address pin allows up to 8 slave devices on the bus RESET 16 12 14 I Hardware reset INTB 18 13 15 O Interrupt output for port B. Can be configured as active high, active low, or open drain. INTA 19 14 16 O Interrupt output for port A. Can be configured as active high, active low, or open drain. GPA0 20 15 17 I/O Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. GPA1 21 16 18 I/O Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. GPA2 22 17 19 I/O Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. GPA3 23 18 20 I/O Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. GPA4 24 19 21 I/O Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. GPA5 25 20 22 I/O Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. GPA6 26 21 23 I/O Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. GPA7 27 22 24 I/O Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. NC 2, 14, — — Not connected 17, 28 EP — 25 — Exposed Thermal Pad (EP). Do not electrically connect, or connect to VSS. © 2008 Microchip Technology Inc. DS22103A-page 5

MCP23018/MCP23S18 TABLE 1-2: SPI PINOUT DESCRIPTION (MCP23S18) 28L Pin 24L Pin PDIP/ Standard Function Name QFN Type SOIC GPB0 3 24 I/O Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. GPB1 4 1 I/O Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. GPB2 5 2 I/O Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. GPB3 6 3 I/O Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. GPB4 7 4 I/O Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. GPB5 8 5 I/O Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. GPB6 9 6 I/O Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. GPB7 10 7 I/O Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. V 11 8 P Power (high current capable) DD V 1 23 P Ground (high current capable) SS CS 12 9 I Chip select SCK 13 10 I Serial clock input SI 14 11 I Serial data input SO 15 12 O Serial data out RESET 16 13 I Hardware reset (must be externally biased) INTB 18 — O Interrupt output for port B. Can be configured as active high, active low, or open drain. INTA 19 14 O Interrupt output for port A. Can be configured as active high, active low, or open drain. GPA0 20 15 I/O Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. GPA1 21 16 I/O Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. GPA2 22 17 I/O Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. GPA3 23 18 I/O Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. GPA4 24 19 I/O Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. GPA5 25 20 I/O Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. GPA6 26 21 I/O Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. GPA7 27 22 I/O Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. NC 2, 17, — Not connected 28 EP — 25 — Exposed Thermal Pad (EP). Do not electrically connect, or connect to VSS. DS22103A-page 6 © 2008 Microchip Technology Inc.

MCP23018/MCP23S18 1.2 Power-on Reset (POR) modes explained here relate to the device’s internal address pointer and whether or not it is incremented The on-chip POR circuit holds the device in reset until after each byte is clocked on the serial interface. VDD has reached a high enough voltage to deactivate Byte Mode disables automatic address pointer incre- the POR circuit (i.e., release the device from reset). menting. When operating in Byte Mode, the The maximum VDD rise time is specified in the MCP23X18 does not increment its internal address electrical specification section. counter after each byte during the data transfer. This When the device exits the POR condition (releases gives the ability to continually access the same address reset), device operating parameters (i.e., voltage, by providing extra clocks (without additional control temperature, serial bus frequency, etc.) must be met to bytes). This is useful for polling the GPIO register for ensure proper operation. data changes or for continually writing to the output latches. 1.3 Serial Interface A special mode (Byte Mode with IOCON.BANK = 0) This block handles the functionality of the I2C causes the address pointer to toggle between associ- (MCP23018) or SPI (MCP23S18) interface protocol. ated A/B register pairs. For example, if the BANK bit is The MCP23X18 contains twenty two (22) individual cleared and the address pointer is initially set to registers (eleven [11] register pairs) which can be address 12h (GPIOA) or 13h (GPIOB), the pointer will addressed through the Serial Interface block (Table1- toggle between GPIOA and GPIOB. Note, the address 1). pointer can initially point to either address in the regis- ter pair. TABLE 1-1: REGISTER ADDRESSES Sequential Mode enables automatic address pointer incrementing. When operating in Sequential Mode, the Address Address Access to: MCP23X18 increments its address counter after each IOCON.BANK = 1 IOCON.BANK = 0 byte during the data transfer. The address pointer auto- 00h 00h IODIRA matically rolls over to address 00h after accessing the 10h 01h IODIRB last register. 01h 02h IPOLA These two modes are not to be confused with single 11h 03h IPOLB writes/reads and continuous writes/reads which are 02h 04h GPINTENA serial protocol sequences. For example, the device 12h 05h GPINTENB may be configured for Byte Mode and the master may perform a continuous read. In this case, the 03h 06h DEFVALA MCP23X18 would not increment the address pointer 13h 07h DEFVALB and would repeatedly drive data from the same loca- 04h 08h INTCONA tion. 14h 09h INTCONB 1.3.2 I2C INTERFACE 05h 0Ah IOCON 15h 0Bh IOCON 1.3.2.1 I2C Write Operation 06h 0Ch GPPUA The I2C write operation includes the control byte and 16h 0Dh GPPUB register address sequence, as shown in the bottom of 07h 0Eh INTFA Figure1-1. This sequence is followed by eight bits of 17h 0Fh INTFB data from the master and an Acknowledge (ACK) from 08h 10h INTCAPA the MCP23018. The operation is ended with a stop (P) 18h 11h INTCAPB or restart (SR) condition being generated by the mas- ter. 09h 12h GPIOA 19h 13h GPIOB Data is written to the MCP23018 after every byte trans- fer. If a stop or restart condition is generated during a 0Ah 14h OLATA data transfer, the data will not be written to the 1Ah 15h OLATB MCP23018. Both “byte mode” and “sequential mode” are supported 1.3.1 BYTE MODE AND SEQUENTIAL by the MCP23018. If sequential mode is enabled MODE (default), the MCP23018 increments its address The MCP23X18 has the ability to operate in “Byte counter after each ACK during the data transfer. Mode” or “Sequential Mode” (IOCON.SEQOP). Byte mode and sequential mode are not to be confused with I2C byte operations and sequential operations. The © 2008 Microchip Technology Inc. DS22103A-page 7

MCP23018/MCP23S18 1.3.2.2 I2C Read Operation 1.3.3 SPI INTERFACE I2C read operations include the control byte sequence, 1.3.3.1 SPI Write Operation as shown in the bottom of Figure1-1. This sequence is followed by another control byte (including the Start The SPI write operation is started by lowering CS. The condition and ACK) with the R/W bit equal to a logic write command (slave address with R/W bit cleared) is one (R/W = 1). The MCP23018 then transmits the data then clocked into the device. The opcode is followed by contained in the addressed register. The sequence is an address and at least one data byte. ended with the master generating a Stop or Restart 1.3.3.2 SPI Read Operation condition. The SPI read operation is started by lowering CS. The 1.3.2.3 I2C Sequential Write/Read SPI read command (slave address with R/W bit set) is For sequential operations (Write or Read), instead of then clocked into the device. The opcode is followed by transmitting a Stop or Restart condition after the data an address, with at least one data byte being clocked transfer, the master clocks the next byte pointed to by out of the device. the address pointer (see Section1.3.1 “Byte Mode 1.3.3.3 SPI Sequential Write/Read and Sequential Mode” for details regarding sequential operation control). For sequential operations, instead of deselecting the The sequence ends with the master sending a Stop or device by raising CS, the master clocks the next byte Restart condition. pointed to by the address pointer. (see Section1.3.1 “Byte Mode and Sequential Mode” for details regard- The MCP23018 address pointer will roll over to ing sequential operation control). address zero after reaching the last register address. The sequence ends by the raising of CS. Refer to Figure1-1. The MCP23S18 address pointer will roll over to address zero after reaching the last register address. DS22103A-page 8 © 2008 Microchip Technology Inc.

MCP23018/MCP23S18 FIGURE 1-1: MCP23018 I2C™ DEVICE PROTOCOL S - Start SR - Restart S OP W ADDR DIN .... DIN P P - Stop w - Write SR OP R DOUT .... DOUT P R - Read OP - Device opcode SR OP W ADDR .... DIN P ADDR - Device address P DOUT - Data out from MCP23018 DIN - Data in to MCP23018 S OP R DOUT .... DOUT P SR OP R DOUT .... DOUT P SR OP W ADDR DIN .... DIN P P Byte and Sequential Write Byte S OP W ADDR DIN P Sequential S OP W ADDR DIN .... DIN P Byte and Sequential Read Byte S OP W ADDR SR OP R DOUT P Sequential S OP W ADDR SR OP R DOUT .... DOUT P © 2008 Microchip Technology Inc. DS22103A-page 9

MCP23018/MCP23S18 1.4 Multi-bit Address Decoder 2. The 3-bit address is latched after tADDRLAT. 3. The module powers down after the first rising The ADDR pin is used to set the slave address of the MCP23018 (I2C only) to allow up to eight devices on edge of the serial clock is detected (tADDIS). the bus using only a single pin. Typically, this would Once the address bits are latched, the device will keep require three pins. the slave address until a POR or reset condition occurs. The multi-bit Address Decoder employs a basic FLASH ADC architecture (Figure1-4). The seven comparators 1.4.1 CALCULATING VOLTAGE ON ADDR generate 8 unique values based on the analog input. When calculating the required voltage on the ADDR pin This value is converted to a 3-bit code which corre- (V2), the set point should be the mid-point of the LSb of sponds to the address bits (A2, A1, A0) in the serial the ADC. OPCODE. The examples in Figure1-2 and Figure1-3 show how Sequence of Operation (see Figure1-5 for to determine the mid point voltage (V2) and the range timings): of voltages based on a voltage divider circuit. The 1. Upon power up (after VDD stabilizes) the module maximum tolerance is 20%, however, it is recom- becomes active after time tADEN. Note, the ana- mended to use 5% tolerance worst case (10% total tol- log value on the ADDR pin must be stable erance). before this point to ensure accurate address assignment. FIGURE 1-2: VOLTAGE DIVIDER EXAMPLE VDD VDD ADDR MCP23018 A0 R1 A1 A2 V2 R2 VSS VSS DS22103A-page 10 © 2008 Microchip Technology Inc.

MCP23018/MCP23S18 FIGURE 1-3: VOLTAGE AND CODE EXAMPLE Assume: n = A2, A1, A0 in opcode ratio = R2/(R1+R2) V2 = voltage on ADDR pin V2(min) = V2 - (VDD/8) x %tolerance V2(max) = V2 + (VDD/8) x %tolerance VDD=1.8 10% Tolerance (total) n R2=2n+1 R1=16-R2 R2/(R1+R2) V2 V2(min) V2(max) 0 1 15 0.0625 0.113 0.00 0.14 1 3 13 0.1875 0.338 0.32 0.36 2 5 11 0.3125 0.563 0.54 0.59 3 7 9 0.4375 0.788 0.77 0.81 4 9 7 0.5625 1.013 0.99 1.04 5 11 5 0.6875 1.238 1.22 1.26 6 13 3 0.8125 1.463 1.44 1.49 7 15 1 0.9375 1.688 1.67 1.80 VDD=2.7 10% Tolerance (total) n R2=2n+1 R1=16-R2 R2/(R1+R2) V2 V2(min) V2(max) 0 1 15 0.0625 0.169 0.00 0.19 1 3 13 0.1875 0.506 0.48 0.53 2 5 11 0.3125 0.844 0.82 0.87 3 7 9 0.4375 1.181 1.16 1.20 4 9 7 0.5625 1.519 1.50 1.54 5 11 5 0.6875 1.856 1.83 1.88 6 13 3 0.8125 2.194 2.17 2.22 7 15 1 0.9375 2.531 2.51 2.70 VDD=3.3 10% Tolerance (total) n R2=2n+1 R1=16-R2 R2/(R1+R2) V2 V2(min) V2(max) 0 1 15 0.0625 0.206 0.00 0.23 1 3 13 0.1875 0.619 0.60 0.64 2 5 11 0.3125 1.031 1.01 1.05 3 7 9 0.4375 1.444 1.42 1.47 4 9 7 0.5625 1.856 1.83 1.88 5 11 5 0.6875 2.269 2.25 2.29 6 13 3 0.8125 2.681 2.66 2.70 7 15 1 0.9375 3.094 3.07 3.30 VDD=5.5 10% Tolerance (total) n R2=2n+1 R1=16-R2 R2/(R1+R2) V2 V2(min) V2(max) 0 1 15 0.0625 0.344 0.00 0.37 1 3 13 0.1875 1.031 1.01 1.05 2 5 11 0.3125 1.719 1.70 1.74 3 7 9 0.4375 2.406 2.38 2.43 4 9 7 0.5625 3.094 3.07 3.12 5 11 5 0.6875 3.781 3.76 3.80 6 13 3 0.8125 4.469 4.45 4.49 7 15 1 0.9375 5.156 5.13 5.50 © 2008 Microchip Technology Inc. DS22103A-page 11

MCP23018/MCP23S18 FIGURE 1-4: FLASH ADC BLOCK DIAGRAM VDD analog_in addr_out[6] addr[6:0] i2c_addr[2:0] d q adc_en adc_en en addr_out[5] adc_en reset addr_out[4] '0' dsetq adc_en adc_en i2c_clk addr_out[3] adc_en addr_out[2] adc_en addr_out[1] adc_en addr_out[0] adc_en adc_en gnd DS22103A-page 12 © 2008 Microchip Technology Inc.

MCP23018/MCP23S18 FIGURE 1-5: HARDWARE ADDRESS DECODE TIMING tADEN VDD tADDRLAT adc_en i2c_addr[2:0] tADDIS i2c_clk 1.4.2 ADDRESSING I2C DEVICES FIGURE 1-6: I2C™ CONTROL BYTE (MCP23018) FORMAT The MCP23018 is a slave I2C device that supports 7- Control Byte bit slave addressing, with the read/write bit filling out the control byte. The slave address contains four fixed S 0 1 0 0 A2 A1 A0 R/W ACK bits and three user-defined hardware address bits (pins A2, A1, and A0). Figure1-6 shows the control byte Slave Address format. Start R/W bit 1.4.3 ADDRESSING SPI DEVICES bit ACK bit (MCP23S18) R/W = 0 = write R/W = 1 = read The MCP23S18 is a slave SPI device. The slave address contains seven fixed bits(no address bits) with the read/write bit filling out the control byte. Figure1-7 FIGURE 1-7: SPI CONTROL BYTE shows the control byte format. FORMAT CS Control Byte 0 1 0 0 0 0 0 R/W Slave Address R/W bit R/W = 0 = write R/W = 1 = read © 2008 Microchip Technology Inc. DS22103A-page 13

MCP23018/MCP23S18 FIGURE 1-8: I2C™ ADDRESSING REGISTERS S 0 1 0 0 A2 A1 A0 0 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK R/W = 0 Device Opcode Register Address The ACKs are provided by the MCP23X18. FIGURE 1-9: SPI ADDRESSING REGISTERS CS 0 1 0 0 0 0 0 R/W A7 A6 A5 A4 A3 A2 A1 A0 Device Opcode Register Address DS22103A-page 14 © 2008 Microchip Technology Inc.

MCP23018/MCP23S18 1.5 GPIO Port The pull up resistors are individually configured and can be enabled when the pin is cofigured as an input or The GPIO module is a general purpose 16-bit wide output. bidirectional port which is functionally split into two (2) Reading the GPIOn register reads the value on the 8-bit wide ports. port. Reading the OLATn register only reads the The outputs are open-drain. latches, not the actual value on the port. The GPIO module contains the data ports (GPIOn), Writing to the GPIOn register actually causes a write to internal pull up resistors and the Output Latches the latches (OLATn). Writing to the OLATn register (OLATn). forces the associated output drivers to drive to the level in OLATn. Pins configured as inputs turn off the associ- ated output driver and put it in high-impedance. TABLE 1-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE GPIO PORTS (BANK = 1) Register Address POR/RST bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Name (hex) value IODIRA 00 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 1111 1111 IPOLA 01 IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 0000 0000 GPINTENA 02 GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 GPINT1 GPINT0 0000 0000 GPPUA 06 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 0000 0000 GPIOA 09 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 0000 0000 OLATA 0A OL7 OL6 OL5 OL4 OL3 OL2 OL1 OL0 0000 0000 IODIRB 10 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 1111 1111 IPOLB 11 IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 0000 0000 GPINTENB 12 GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 GPINT1 GPINT0 0000 0000 GPPUB 16 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 0000 0000 GPIOB 19 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 0000 0000 OLATB 1A OL7 OL6 OL5 OL4 OL3 OL2 OL1 OL0 0000 0000 TABLE 1-3: SUMMARY OF REGISTERS ASSOCIATED WITH THE GPIO PORTS (BANK = 0) Register Address POR/RST bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Name (hex) value IODIRA 00 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 1111 1111 IODIRB 01 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 1111 1111 IPOLA 02 IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 0000 0000 IPOLB 03 IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 0000 0000 GPINTENA 04 GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 GPINT1 GPINT0 0000 0000 GPINTENB 05 GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 GPINT1 GPINT0 0000 0000 GPPUA 0C PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 0000 0000 GPPUB 0D PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 0000 0000 GPIOA 12 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 0000 0000 GPIOB 13 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 0000 0000 OLATA 14 OL7 OL6 OL5 OL4 OL3 OL2 OL1 OL0 0000 0000 OLATB 15 OL7 OL6 OL5 OL4 OL3 OL2 OL1 OL0 0000 0000 © 2008 Microchip Technology Inc. DS22103A-page 15

MCP23018/MCP23S18 1.6 Configuration and Control with Port A and ten (10) are associated with Port B. Registers One register (IOCON) is shared between the two ports. The Port A registers are identical to the Port B regis- There are twenty two (22) registers associated with the ters, therefore, they will be referred to without differen- MCP23X18 as shown in Table1-4 and Table1-5. The tiating between the port designation (i.e., they will not two tables show the register mapping with the two have the “A” or “B” designator assigned) in the register BANK bit values. Ten (10) registers are associated tables. TABLE 1-4: CONTROL REGISTER SUMMARY (IOCON.BANK = 1) Register Address POR/RST bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Name (hex) value IODIRA 00 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 1111 1111 IPOLA 01 IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 0000 0000 GPINTENA 02 GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 GPINT1 GPINT0 0000 0000 DEFVALA 03 DEF7 DEF6 DEF5 DEF4 DEF3 DEF2 DEF1 DEF0 0000 0000 INTCONA 04 IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 0000 0000 IOCON 05 BANK MIRROR SEQOP — — ODR INTPOL INTCC 0000 0000 GPPUA 06 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 0000 0000 INTFA 07 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INTO 0000 0000 INTCAPA 08 ICP7 ICP6 ICP5 ICP4 ICP3 ICP2 ICP1 ICP0 0000 0000 GPIOA 09 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 0000 0000 OLATA 0A OL7 OL6 OL5 OL4 OL3 OL2 OL1 OL0 0000 0000 IODIRB 10 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 1111 1111 IPOLB 11 IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 0000 0000 GPINTENB 12 GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 GPINT1 GPINT0 0000 0000 DEFVALB 13 DEF7 DEF6 DEF5 DEF4 DEF3 DEF2 DEF1 DEF0 0000 0000 INTCONB 14 IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 0000 0000 IOCON 15 BANK MIRROR SEQOP — — ODR INTPOL INTCC 0000 0000 GPPUB 16 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 0000 0000 INTFB 17 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INTO 0000 0000 INTCAPB 18 ICP7 ICP6 ICP5 ICP4 ICP3 ICP2 ICP1 ICP0 0000 0000 GPIOB 19 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 0000 0000 OLATB 1A OL7 OL6 OL5 OL4 OL3 OL2 OL1 OL0 0000 0000 DS22103A-page 16 © 2008 Microchip Technology Inc.

MCP23018/MCP23S18 TABLE 1-5: CONTROL REGISTER SUMMARY (IOCON.BANK = 0) Register Address POR/RST bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Name (hex) value IODIRA 00 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 1111 1111 IODIRB 01 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 1111 1111 IPOLA 02 IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 0000 0000 IPOLB 03 IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 0000 0000 GPINTENA 04 GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 GPINT1 GPINT0 0000 0000 GPINTENB 05 GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 GPINT1 GPINT0 0000 0000 DEFVALA 06 DEF7 DEF6 DEF5 DEF4 DEF3 DEF2 DEF1 DEF0 0000 0000 DEFVALB 07 DEF7 DEF6 DEF5 DEF4 DEF3 DEF2 DEF1 DEF0 0000 0000 INTCONA 08 IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 0000 0000 INTCONB 09 IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 0000 0000 IOCON 0A BANK MIRROR SEQOP — — ODR INTPOL INTCC 0000 0000 IOCON 0B BANK MIRROR SEQOP — — ODR INTPOL INTCC 0000 0000 GPPUA 0C PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 0000 0000 GPPUB 0D PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 0000 0000 INTFA 0E INT7 INT6 INT5 INT4 INT3 INT2 INT1 INTO 0000 0000 INTFB 0F INT7 INT6 INT5 INT4 INT3 INT2 INT1 INTO 0000 0000 INTCAPA 10 ICP7 ICP6 ICP5 ICP4 ICP3 ICP2 ICP1 ICP0 0000 0000 INTCAPB 11 ICP7 ICP6 ICP5 ICP4 ICP3 ICP2 ICP1 ICP0 0000 0000 GPIOA 12 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 0000 0000 GPIOB 13 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 0000 0000 OLATA 14 OL7 OL6 OL5 OL4 OL3 OL2 OL1 OL0 0000 0000 OLATB 15 OL7 OL6 OL5 OL4 OL3 OL2 OL1 OL0 0000 0000 © 2008 Microchip Technology Inc. DS22103A-page 17

MCP23018/MCP23S18 1.6.1 I/O DIRECTION REGISTER Controls the direction of the data I/O. When a bit is set, the corresponding pin becomes an input. When a bit is clear, the corresponding pin becomes an output. REGISTER 1-3: IODIR – I/O DIRECTION REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 IO7:IO0: Controls the direction of data I/O <7:0> 1 = Pin is configured as an input. 0 = Pin is configured as an output. DS22103A-page 18 © 2008 Microchip Technology Inc.

MCP23018/MCP23S18 1.6.2 INPUT POLARITY REGISTER This register allows the user to configure the polarity on the corresponding GPIO port bits. If a bit is set, the corresponding GPIO register bit will reflect the inverted value on the pin. REGISTER 1-4: IPOL – INPUT POLARITY PORT REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 IP7:IP0: Controls the polarity inversion of the input pins <7:0> 1 = GPIO register bit will reflect the opposite logic state of the input pin. 0 = GPIO register bit will reflect the same logic state of the input pin. © 2008 Microchip Technology Inc. DS22103A-page 19

MCP23018/MCP23S18 1.6.3 INTERRUPT-ON-CHANGE CONTROL REGISTER The GPINTEN register controls the interrupt-on- change feature for each pin. If a bit is set, the corresponding pin is enabled for interrupt-on-change. The DEFVAL and INTCON registers must also be configured if any pins are enabled for interrupt-on-change. REGISTER 1-5: GPINTEN – INTERRUPT-ON-CHANGE PINS R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 GPINT1 GPINT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 GPINT7:GPINT0: General purpose I/O interrupt-on-change pins <7:0> 1 = Enable GPIO input pin for interrupt-on-change event 0 = Disable GPIO input pin for interrupt-on-change event. DS22103A-page 20 © 2008 Microchip Technology Inc.

MCP23018/MCP23S18 1.6.4 DEFAULT COMPARE REGISTER FOR INTERRUPT-ON-CHANGE The default comparison value is configured in the DEFVAL register. If enabled (via GPINTEN and INT- CON) to compare against the DEFVAL register, an opposite value on the associated pin will cause an interrupt to occur. REGISTER 1-6: DEFVAL – DEFAULT VALUE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DEF7 DEF6 DEF5 DEF4 DEF3 DEF2 DEF1 DEF0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 DEF7:DEF0: Sets the compare value for pins configured for interrupt-on-change from defaults <7:0>. Refer to INTCON. If the associated pin level is the opposite from the register bit, an interrupt occurs. Refer to INTCON and GPINTEN. © 2008 Microchip Technology Inc. DS22103A-page 21

MCP23018/MCP23S18 1.6.5 INTERRUPT CONTROL REGISTER The INTCON register controls how the associated pin value is compared for the interrupt-on-change feature. If a bit is set, the corresponding I/O pin is compared against the associated bit in the DEFVAL register. If a bit value is clear, the corresponding I/O pin is compared against the previous value. REGISTER 1-7: INTCON – INTERRUPT-ON-CHANGE CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 IOC7:IOC0: Controls how the associated pin value is compared for interrupt-on-change <7:0>. 1 = Pin value is compared against the associated bit is DEFVAL register 0 = Pin value is compared against the previous pin value. Refer to INTCON and GPINTEN. DS22103A-page 22 © 2008 Microchip Technology Inc.

MCP23018/MCP23S18 1.6.6 CONFIGURATION REGISTER Note: The INTB pin is not bonded out on the The IOCON register contains several bits for MCP23S18 (SPI) device in the 24-lead configuring the device: QFN package. The MIRROR bit must be The BANK bit changes how the registers are mapped configured to a “1” in order for interrupts to (see Table1-4 and Table1-5 for more details). be detected on PORTB. • If BANK = 1, the registers associated with each The MIRROR bit controls how the INTA and INTB pins port are segregated. Registers associated with function with respect to each other. PORTA are are mapped from address 00h - 0Ah • When MIRROR = 1, the INTn pins are functionally and registers associated with PORTB are OR’ed so that an interrupt on either port will cause mapped from Address 10h - 1Ah both pins to activate • If BANK = 0, the A/B registers are paired. For • When MIRROR = 0, the INT pins are separated. example, IODIRA is mapped to address 00h and Interrupt conditions on a port will cause its respec- IODIRB is mapped to the next address (address tive INT pin to activate 01h). The mapping for all registers is from 00h- The Sequential Operation (SEQOP) controls the 15h incrementing function of the address pointer. If the It is important to take care when changing the BANK bit address pointer is disabled, the address pointer does as the address mapping changes after the byte is not automatically increment after each byte is clocked clocked into the device. The address pointer may point during a serial transfer. This feature is useful when it is to an invalid location after the bit is modified. desired to continuously poll (read) or modify (write) a For example, if the device is configured to automati- register. cally increment its internal address pointer the following The Open-Drain (ODR) control bit enables/disables the scenario would occur: INT pin for open-drain configuration. • BANK = 0 The Interrupt Polarity (INTPOL) sets the polarity of the • Write 80h to 0Ah (IOCON) to set the BANK bit INT pin. This bit is functional only when the ODR bit is • After the write completes the internal address now cleared, configuring the INT pin as active push-pull. points to 0Bh which is an invalid address when The Interrupt Clearing Control (INTCC) configures how the BANK bit is set interrupts are cleared. When set (INTCC = 1), the For this reason, it is advised to only perform byte writes interrupt is cleared when the INTCAP register is read. to this register when changing the BANK bit. When cleared (INTCC = 0), the interrupt is cleared when the GPIO register is read. The interrupt can only be cleared when the interrupt condition is inactive. Refer to Section1.7.5 “Clearing Interrupts” for details. © 2008 Microchip Technology Inc. DS22103A-page 23

MCP23018/MCP23S18 REGISTER 1-8: IOCON – I/O EXPANDER CONFIGURATION REGISTER R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 BANK MIRROR SEQOP - - ODR INTPOL INTCC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 BANK: Controls how the registers are addressed (see Figure1-4 and Figure1-5) 1 = The registers associated with each port are separated into different banks 0 = The registers are in the same bank (addresses are sequential) bit 6 MIRROR: INT pins mirror bit 1 = The INT pins are internally connected in a wired OR configuration 0 = The INT pins are not connected. INTA is associated with Port A and INTB is associated with Port B bit 5 SEQOP: Sequential Operation mode bit. 1 = Sequential operation disabled, address pointer does not increment. 0 = Sequential operation enabled, address pointer increments. bit 4 Unimplemented: Reads as 0 bit 3 Unimplemented: Reads as 0 bit 2 ODR: Configures the INT pin as an open-drain output. 1 = Open-drain output (overrides the INTPOL bit). 0 = Active driver output (INTPOL bit sets the polarity). bit 1 INTPOL: Sets the polarity of the INT output pin. 1 = Active-high. 0 = Active-low. bit 0 INTCC: Interrupt Clearing Control 1 = Reading INTCAP register clears the interrupt 0 = Reading GPIO register clears the interrupt DS22103A-page 24 © 2008 Microchip Technology Inc.

MCP23018/MCP23S18 1.6.7 PULL-UP RESISTOR CONFIGURATION REGISTER The GPPU register controls the pull-up resistors for the port pins. If a bit is set the corresponding port pin is internally pulled up with an internal resistor. REGISTER 1-9: GPPU – GPIO PULL-UP RESISTOR REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 PU7:PU0: Controls the internal pull-up resistors on each pin (when configured as an input or output) <7:0>. 1 = Pull-up enabled. 0 = Pull-up disabled. FIGURE 1-10: TYPICAL PERFORMANCE CURVE FOR THE INTERNAL PULL-UP RESISTORS GPIO Pin Internal Pull-up Current vs VDD 400 350 T = -40°C 300 T = +25°C 250 ) A µ 200 ( U P 150 I T = +125°C 100 T = +85°C 50 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VDD (V) © 2008 Microchip Technology Inc. DS22103A-page 25

MCP23018/MCP23S18 1.6.8 INTERRUPT FLAG REGISTER The INTF register reflects the interrupt condition on the port pins of any pin that is enabled for interrupts via the GPINTEN register. A ‘set’ bit indicates that the associated pin caused the interrupt. This register is ‘read only’. Writes to this register will be ignored. REGISTER 1-10: INTF – INTERRUPT FLAG REGISTER R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 INT7:INT0: Reflects the interrupt condition on the port. Will reflect the change only if interrupts are enabled (GPINTEN) <7:0>. 1 = Pin caused interrupt. 0 = Interrupt not pending. DS22103A-page 26 © 2008 Microchip Technology Inc.

MCP23018/MCP23S18 1.6.9 INTERRUPT CAPTURE REGISTER The INTCAP register captures the GPIO port value at the time the interrupt occurred. The register is ‘read only’ and is updated only when an interrupt occurs. The register will remain unchanged until the interrupt is cleared via a read of INTCAP or GPIO. REGISTER 1-11: INTCAP – INTERRUPT CAPTURED VALUE FOR PORT REGISTER R-x R-x R-x R-x R-x R-x R-x R-x ICP7 ICP6 ICP5 ICP4 ICP3 ICP2 ICP1 ICP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 ICP7:ICP0: Reflects the logic level on the port pins at the time of interrupt due to pin change <7:0>. 1 = Logic-high. 0 = Logic-low. © 2008 Microchip Technology Inc. DS22103A-page 27

MCP23018/MCP23S18 1.6.10 PORT REGISTER The GPIO register reflects the value on the port. Reading from this register reads the port. Writing to this register modifies the Output Latch (OLAT) register. REGISTER 1-12: GPIO – GENERAL PURPOSE I/O PORT REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 GP7:GP0: Reflects the logic level on the pins <7:0>. 1 = Logic-high. 0 = Logic-low. DS22103A-page 28 © 2008 Microchip Technology Inc.

MCP23018/MCP23S18 1.6.11 OUTPUT LATCH REGISTER (OLAT) The OLAT register provides access to the output latches. A read from this register results in a read of the OLAT and not the port itself. A write to this register modifies the output latches that modifies the pins configured as outputs. REGISTER 1-13: OLAT – OUTPUT LATCH REGISTER 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OL7 OL6 OL5 OL4 OL3 OL2 OL1 OL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 OL7:OL0: Reflects the logic level on the output latch <7:0>. 1 = Logic-high. 0 = Logic-low. © 2008 Microchip Technology Inc. DS22103A-page 29

MCP23018/MCP23S18 1.7 Interrupt Logic 1.7.2 IOC FROM PIN CHANGE If enabled, the MCP23X18 activates the INTn interrupt If enabled, the MCP23X18 will generate an interrupt if output when one of the port pins changes state or when a mismatch condition exists between the current port a pin does not match the pre-configured default. Each value and the previous port value. Only IOC enabled pin is individually configurable as follows: pins will be compared. See GPINTEN and INTCON registers. • Enable/disable interrupt via GPINTEN • Can interrupt on either pin change or change from 1.7.3 IOC FROM REGISTER DEFAULT default as configured in DEFVAL If enabled, the MCP23X18 will generate an interrupt if Both conditions are referred to as Interrupt on Change a mismatch occurs between the DEFVAL register and (IOC). the port. Only IOC enabled pins will be compared. See GPINTEN, INTCON, and DEFVAL registers. The Interrupt Control (INT) Module uses the following registers/bits: 1.7.4 INTERRUPT OPERATION • IOCON.MIRROR - controls if the two interrupt The INTn interrupt output can be configured as “active pins mirror each other. low”, “active high”, or “open drain” via the IOCON • GPINTEN - Interrupt enable register register. • INTCON - Controls the source for the IOC Only those pins that are configured as an input (IODIR • DEFVAL - Contains the register default for IOC register) with interrupt-on-change (IOC) enabled operation (GPINTEN register) can cause an interrupt. Pins defined as an output have no effect on the interrupt 1.7.1 INTA AND INTB output pin. There are two interrupt pins, INTA and INTB. By Input change activity on a port input pin that is enabled default, INTA is associated with GPAn pins (Port A) and for IOC will generate an internal device interrupt and INTB is associated with GPBn pins (Port B). Each port the device will capture the value of the port and copy it has an independent signal which is cleared if its into INTCAP. associated GPIO or INTCAP register is read. The first interrupt event will cause the port contents to 1.7.1.1 Mirroring the INT pins be copied into the INTCAP register. Subsequent interrupt conditions on the port will not cause an Additionally, the INTn pins can be configured to mirror interrupt to occur as long as the interrupt is not cleared each other so that any interrupt will cause both pins to by a read of INTCAP or GPIO. go active. This is controlled via IOCON.MIRROR. If IOCON.MIRROR = 0, the internal signals are routed 1.7.5 CLEARING INTERRUPTS independently to the INTA and INTB pads. The interrupt will remain active until the INTCAP or If IOCON.MIRROR = 1, the internal signals are OR’ed GPIO register is read (depending on IOCON.INTCC). together and routed to the INTn pads. In this case, the Writing to these registers will not affect the interrupt. interrupt will only be cleared if the associated GPIO or The interrupt condition will be cleared after the LSb of INTCAP is read (see Table1-6). the data is clocked out during a Read command of GPIO or INTCAP (depending on IOCON.INTCC). TABLE 1-6: INTERRUPT OPERATION (IOCON.MIRROR = 1) Note: Assuming IOCON.INTCC = 0 (INT cleared Interrupt Interupt on GPIO read): The value in INTCAP can Read Port N* Condition Result be lost if GPIO is read before INTCAP while another IOC is pending. After read- GPIOA Port A Clear ing GPIO, the interrupt will clear and then Port B Unchanged set due to the pending IOC, causing the GPIOB Port A Unchanged INTCAP register to update. Port B Clear GPIOA and Port A Unchanged GPIOB Port B Unchanged Both Port A Clear and Port B * Port n = GPIOn or INTCAPn DS22103A-page 30 © 2008 Microchip Technology Inc.

MCP23018/MCP23S18 1.7.6 INTERRUPT CONDITIONS FIGURE 1-11: INTERRUPT-ON-PIN- CHANGE There are two possible configurations to cause interrupts (configured via INTCON): GPx 1. Pins configured for interrupt-on-pin-change will cause an interrupt to occur if a pin changes to the opposite state. The default state is reset after an interrupt occurs. For example, an interrupt occurs by an input changing from 1 to INT ACTIVE ACTIVE 0. The new initial state for the pin is a logic 0. 2. Pins configured for interrupt-on-change from Port value Read GPIO Port value is captured or INTCAP is captured register value will cause an interrupt to occur if into INTCAP into INTCAP the corresponding input pin differs from the register bit. The interrupt condition will remain as long as the condition exists, regardless if the FIGURE 1-12: INTERRUPT-ON-CHANGE INTAP or GPIO is read. FROM REGISTER See Figure1-11 and Figure1-12 for more information DEFAULT on interrupt operations. DEFVAL GP: 7 6 5 4 3 2 1 0 X X X X X 1 X X GP2 INT ACTIVE ACTIVE Port value is captured Read GPIO into INTCAP or INTCAP (INT clears only if interrupt condition does not exist.) © 2008 Microchip Technology Inc. DS22103A-page 31

MCP23018/MCP23S18 NOTES: DS22103A-page 32 © 2008 Microchip Technology Inc.

MCP23018/MCP23S18 2.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.0V Voltage on RESET with respect to VSS ..................................................................................................... -0.3V to +14V Voltage on all other pins with respect to VSS (except VDDand GPIOA/B) ......................................-0.6V to (VDD + 0.6V) Voltage on GPIO Pins:.................................................................................................................................-0.6V to 5.5V Total power dissipation (Note 1)...........................................................................................................................700mW Maximum current out of VSS pin...........................................................................................................................400mA Maximum current into VDD pin..............................................................................................................................125mA Input clamp current, IIK (VI < 0 or VI > VDD)......................................................................................................................±20mA Output clamp current, IOK (VO < 0 or VO > VDD)..............................................................................................................±20mA Maximum output current sunk by any Output pin....................................................................................................25mA Maximum output current sunk by any Output pin (VDD = 1.8V)..............................................................................10mA Maximum output current sourced by any Output pin..............................................................................................25mA Maximum output current sourced by any Output pin (VDD = 1.8V).........................................................................10mA Note: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOL x IOL) † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. © 2008 Microchip Technology Inc. DS22103A-page 33

MCP23018/MCP23S18 2.1 DC CHARACTERISTICS Operating Conditions (unless otherwise indicated): DC Characteristics 1.8V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +125°C Param Characteristic Sym Min Typ(2) Max Units Conditions No. D001 Supply Voltage VDD 1.8 — 5.5 V D002 VDD Start Voltage to VPOR — VSS — V Ensure Power-on Reset D003 VDD Rise Rate to SVDD 0.05 — — V/ms Design guidance only. Ensure Power-on Not tested. Reset D004 Supply Current IDD — — 1 mA SCL/SCK = 1MHz D005 Standby (Idle) current IDDS — — 1 µA –40°C ≤ TA ≤ +85°C — — 6 µA +85°C ≤ TA ≤ +125°C Input Low-Voltage D031 CS, GPIO, SCL/SCK, VIL VSS — 0.2VDD V SDA, SI, RESET Input High-Voltage D041 CS, SCL/SCK, SDA, VIH 0.8VDD — VDD V SI, RESET GPIO VIH 0.8VDD — 5.5 V Input Leakage Current D060 I/O port pins IIL — — ±1 µA VSS ≤ VPIN ≤ VDD, Output Leakage Current D065 I/O port pins ILO — — ±1 µA VSS ≤ VPIN ≤ VDD, D070 GPIO internal pull-up IPU — 220 — µA VDD = 5V, GP Pins = VSS current Note1 Output Low-Voltage D080 GPIO VOL — — 0.6 V IOL = 8.5mA, VDD = 4.5V (open-drain) INT — — 0.6 V IOL = 1.6mA, VDD = 4.5V SO, SDA — — 0.6 V IOL = 3.0mA, VDD = 1.8V SDA — — 0.8 V IOL = 3.0mA, VDD = 4.5V Output High-Voltage D090 INT, SO VOH VDD – 0.7 — — V IOH = -3.0mA, VDD = 4.5V VDD – 0.7 — — IOH = -400µA, VDD = 1.8V Capacitive Loading Specs on Output Pins D101 GPIO, SO, INT CIO — — 50 pF D102 SDA CB — — 400 pF Note 1: This parameter is characterized, not 100% tested. 2: Data in the Typical (“Typ”) column is at 5V, +25°C unless otherwise stated. DS22103A-page 34 © 2008 Microchip Technology Inc.

MCP23018/MCP23S18 2.2 AC CHARACTERISTICS FIGURE 2-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS VDD Pin 1kΩ SCL and 50pF SDA pin MCP23018 135pF FIGURE 2-2: RESET AND DEVICE RESET TIMER TIMING VDD RESET 30 32 31 Internal RESET 34 Output pin TABLE 2-1: RESET AND DEVICE RESET TIMER REQUIREMENTS AC Characteristics Standard Operating Conditions (unless otherwise specified) 1.8V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +125°C. Parameter No. Sym Characteristic Min Typ(2) Max Units Conditions 30 TRSTL RESET Pulse Width (low) 1 — — µs VDD = 5.0V 32 THLD Device active after reset high — 0 — µs VDD = 5.0V 31 TPOR POR at device power up — 20 — µs VDD = 5.0V 34 TioZ Output Hi-impedance from — — 1 µs RESET Low Note 1: This parameter is characterized, not 100% tested. 2: Data in the Typical (“Typ”) column is at 5V, +25°C, unless otherwise stated. © 2008 Microchip Technology Inc. DS22103A-page 35

MCP23018/MCP23S18 TABLE 2-2: GP AND INT PINS AC Characteristics Standard Operating Conditions (unless otherwise specified) 1.8V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +125°C. Parameter No. Sym Characteristic Min Typ(2) Max Units Conditions 50 t Serial data to output valid — — 500 ns GPOV 51 t Interrupt pin disable time — — 600 ns INTD 52 t GP input change to register valid — 450 — ns Note1 GPIV 53 t IOC event to INT active — — 600 ns GPINT 54 t Glitch filter on GP pins — — 50 ns Note1 GLITCH Note 1: This parameter is characterized, not 100% tested. 2: Data in the Typical (“Typ”) column is at 5V, 25°C, unless otherwise stated. FIGURE 2-3: GPIO AND INT TIMING SCL SDA In D1 D0 LSb of data byte zero during a write or read command, depending on parameter 50 GPn Output Pin 51 INT Pin INT pin active INT pin inactive 53 GPn Input Pin 52 Register Loaded DS22103A-page 36 © 2008 Microchip Technology Inc.

MCP23018/MCP23S18 TABLE 2-3: HARDWARE ADDRESS LATCH TIMING AC Characteristics Standard Operating Conditions (unless otherwise specified) 1.8V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +125°C. Parameter No. Sym Characteristic Min Typ(2) Max Units Conditions 40 tADEN Time from VDD stable after — 0 — µs Note1 POR to ADC enable 41 t Time from ADC enable to — 50 — ns Note1 ADDRLAT address decode and latch 42 t Time from raising edge of serial — 10 — ns Note1 ADDIS clock to ADC disable Note 1: This parameter is characterized, not 100% tested. 2: Data in the Typical (“Typ”) column is at 5V, +25°C, unless otherwise stated.. FIGURE 2-4: HARDWARE ADDRESS LATCH TIMING 40 VDD 41 adc_en i2c_addr[2:0] 42 SCL © 2008 Microchip Technology Inc. DS22103A-page 37

MCP23018/MCP23S18 FIGURE 2-5: I2C BUS START/STOP BITS TIMING SCL 91 93 90 92 SDA START STOP Condition Condition Note1: Refer to Figure2-1 for load conditions. FIGURE 2-6: I2C BUS DATA TIMING 103 100 102 101 SCL 90 106 91 107 92 SDA In 109 109 110 SDA Out Note1: Refer to Figure2-1 for load conditions. DS22103A-page 38 © 2008 Microchip Technology Inc.

MCP23018/MCP23S18 TABLE 2-4: I2C BUS DATA REQUIREMENTS (SLAVE MODE) Operating Conditions (unless otherwise indicated): I2C™ AC Characteristics 1.8V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +125°C RPU (SCL, SDA) = 1kΩ, CL (SCL, SDA) = 135pF. Param Characteristic Sym Min Typ Max Units Conditions No. 100 Clock High Time: THIGH 100kHz mode 4.0 — — µs 1.8V – 5.5V 400kHz mode 0.6 — — µs 1.8V – 5.5V 3.4MHz mode 0.06 — — µs 2.7V – 5.5V 101 Clock Low Time: TLOW 100kHz mode 4.7 — — µs 1.8V – 5.5V 400kHz mode 1.3 — — µs 1.8V – 5.5V 3.4MHz mode 0.16 — — µs 2.7V – 5.5V 102 SDA and SCL Rise Time: TR 100kHz mode (Note1) — — 1000 ns 1.8V – 5.5V 400kHz mode 20 + 0.1CB(2) — 300 ns 1.8V – 5.5V 3.4MHz mode 10 — 80 ns 2.7V – 5.5V 103 SDA and SCL Fall Time: TF 100kHz mode (Note1) — — 300 ns 1.8V – 5.5V 400kHz mode 20 + 0.1CB(2) — 300 ns 1.8V – 5.5V 3.4MHz mode 10 — 80 ns 2.7V – 5.5V 90 START Condition Setup Time: TSU:STA 100kHz mode 4.7 — — µs 1.8V – 5.5V 400kHz mode 0.6 — — µs 1.8V – 5.5V 3.4MHz mode 0.16 — — µs 2.7V – 5.5V 91 START Condition Hold Time: THD:STA 100kHz mode 4.0 — — µs 1.8V – 5.5V 400kHz mode 0.6 — — µs 1.8V – 5.5V 3.4MHz mode 0.16 — — µs 2.7V – 5.5V 106 Data Input Hold Time: THD:DAT 100kHz mode 0 — 3.45 µs 1.8V – 5.5V 400kHz mode 0 — 0.9 µs 1.8V – 5.5V 3.4MHz mode 0 — 0.07 µs 2.7V – 5.5V 107 Data Input Setup Time: TSU:DAT 100kHz mode 250 — — ns 1.8V – 5.5V 400kHz mode 100 — — ns 1.8V – 5.5V 3.4MHz mode 0.01 — — µs 2.7V – 5.5V 92 STOP Condition Setup Time: TSU:STO 100kHz mode 4.0 — — µs 1.8V – 5.5V 400kHz mode 0.6 — — µs 2.7V – 5.5V 3.4MHz mode 0.16 — — µs 4.5V – 5.5V Note 1: This parameter is characterized, not 100% tested. 2: CB is specified from 10 to 400 (pF). 3: This parameter is not applicable in high-speed mode (3.4MHz). © 2008 Microchip Technology Inc. DS22103A-page 39

MCP23018/MCP23S18 TABLE 2-4: I2C BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED) Operating Conditions (unless otherwise indicated): I2C™ AC Characteristics 1.8V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +125°C RPU (SCL, SDA) = 1kΩ, CL (SCL, SDA) = 135pF. Param Characteristic Sym Min Typ Max Units Conditions No. 109 Output Valid From Clock: TAA 100kHz mode — — 3.45 µs 1.8V – 5.5V 400kHz mode — — 0.9 µs 1.8V – 5.5V 3.4MHz mode — — 0.18 µs 2.7V – 5.5V 110 Bus Free Time: TBUF 100kHz mode (NOTE3) 4.7 — — µs 1.8V – 5.5V 400kHz mode 1.3 — — µs 1.8V – 5.5V 3.4MHz mode N/A — N/A µs 2.7V – 5.5V Bus Capacitive Loading: CB 100kHz and 400kHz (NOTE2) — — 400 pF (Note1) 3.4MHz — — 100 pF (Note1) Input Filter Spike TSP Suppression: (SDA and SCL) 100kHz and 400kHz — — 50 ns (Note1) 3.4MHz — — 10 ns (Note1) Note 1: This parameter is characterized, not 100% tested. 2: CB is specified from 10 to 400 (pF). 3: This parameter is not applicable in high-speed mode (3.4MHz). FIGURE 2-7: SPI INPUT TIMING 3 CS 11 1 6 10 Mode 1,1 7 2 SCK Mode 0,0 4 5 SI MSB in LSB in SO high impedance DS22103A-page 40 © 2008 Microchip Technology Inc.

MCP23018/MCP23S18 FIGURE 2-8: SPI OUTPUT TIMING CS 2 8 9 SCK Mode 1,1 Mode 0,0 12 14 13 SO MSB out LSB out don’t care SI © 2008 Microchip Technology Inc. DS22103A-page 41

MCP23018/MCP23S18 TABLE 2-5: SPI INTERFACE AC CHARACTERISTICS Operating Conditions (unless otherwise indicated): SPI Interface AC Characteristics 1.8V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +125°C. Param Characteristic Sym Min Typ Max Units Conditions No. Clock Frequency FCLK — — 10 MHz 1.8V – 5.5V 1 CS Setup Time TCSS 50 — — ns 2 CS Hold Time TCSH 50 — — ns 1.8V – 5.5V 3 CS Disable Time TCSD 50 — — ns 1.8V – 5.5V 4 Data Setup Time TSU 10 — — ns 1.8V – 5.5V 5 Data Hold Time THD 10 — — ns 1.8V – 5.5V 6 CLK Rise Time TR — — 2 µs Note1 7 CLK Fall Time TF — — 2 µs Note1 8 Clock High Time THI 45 — — ns 1.8V – 5.5V 9 Clock Low Time TLO 45 — — ns 1.8V – 5.5V 10 Clock Delay Time TCLD 50 — — ns 11 Clock Enable Time TCLE 50 — — ns 12 Output Valid from Clock TV — — 45 ns 1.8V – 5.5V Low 13 Output Hold Time THO 0 — — ns 14 Output Disable Time TDIS — — 100 ns Note 1: This parameter is characterized, not 100% tested. FIGURE 2-9: TYPICAL PERFORMANCE CURVE FOR SPI TV SPECIFICATION (PARAM #12) TV vs VDD 40 35 T = +125°C 30 ) 25 s T = +85°C n T = -40°C ( 20 V T 15 10 T = +25°C 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VDD (V) DS22103A-page 42 © 2008 Microchip Technology Inc.

MCP23018/MCP23S18 3.0 PACKAGING INFORMATION 3.1 Package Marking Information 24-Lead QFN Example XXXXX 23018 XXXXXX E/MJ^e3^ XXXXXX 0838 YWWNNN 256 24-Lead SSOP (MCP23018 only) Example: XXXXXXXXXXXX MCP23018 XXXXXXXXXXXX E/SS^e^3 YYWWNNN 0838256 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2008 Microchip Technology Inc. DS22103A-page 43

MCP23018/MCP23S18 Package Marking Information (Continued) 28-Lead SPDIP (300 mil) Example: XXXXXXXXXXXXXXXXX MCP23018 XXXXXXXXXXXXXXXXX E/SP^e^3 YYWWNNN 0838256 28-Lead SOIC (300 mil) Example: XXXXXXXXXXXXXXXXXXXX MCP23018 XXXXXXXXXXXXXXXXXXXX E/SO^e^3 XXXXXXXXXXXXXXXXXXXX YYWW YYWWNNN NNN DS22103A-page 44 © 2008 Microchip Technology Inc.

MCP23018/MCP23S18 24-Lead Plastic Quad Flat, No Lead Package (MJ) – 4x4x0.9 mm Body [QFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2008 Microchip Technology Inc. DS22103A-page 45

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MCP23018/MCP23S18 (cid:7)(cid:8)(cid:9)(cid:10)(cid:5)(cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:11)(cid:16)(cid:4)(cid:17)(cid:18)(cid:13)(cid:19)(cid:20)(cid:21)(cid:17)(cid:22)(cid:23)(cid:13)(cid:19)(cid:24)(cid:11)(cid:15)(cid:15)(cid:13)(cid:25)(cid:26)(cid:4)(cid:15)(cid:17)(cid:22)(cid:5)(cid:13)(cid:27)(cid:19)(cid:19)(cid:28)(cid:13)(cid:29)(cid:13)(cid:30)(cid:31) !(cid:13)(cid:24)(cid:24)(cid:13)"(cid:3)(cid:12)#(cid:13)$(cid:19)(cid:19)(cid:25)(cid:14)% (cid:2)(cid:3)(cid:4)(cid:5)(cid:6) (cid:29)(cid:22)(cid:21)(cid:14)(cid:30)(cid:23)(cid:13)(cid:14)(cid:31)(cid:22) (cid:30)(cid:14)(cid:20)!(cid:21)(cid:21)(cid:13)(cid:24)(cid:30)(cid:14)(cid:10)(cid:11)(cid:20)"(cid:11)(cid:12)(cid:13)(cid:14)#(cid:21)(cid:11)$(cid:19)(cid:24)(cid:12) %(cid:14)(cid:10)(cid:25)(cid:13)(cid:11) (cid:13)(cid:14) (cid:13)(cid:13)(cid:14)(cid:30)(cid:23)(cid:13)(cid:14)(cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:14)&(cid:11)(cid:20)"(cid:11)(cid:12)(cid:19)(cid:24)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:20)(cid:19)’(cid:19)(cid:20)(cid:11)(cid:30)(cid:19)(cid:22)(cid:24)(cid:14)(cid:25)(cid:22)(cid:20)(cid:11)(cid:30)(cid:13)#(cid:14)(cid:11)(cid:30)(cid:14) (cid:23)(cid:30)(cid:30)(cid:10)())$$$(cid:28)(cid:31)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:28)(cid:20)(cid:22)(cid:31))(cid:10)(cid:11)(cid:20)"(cid:11)(cid:12)(cid:19)(cid:24)(cid:12) D N E E1 1 2 b NOTE1 e c φ A A2 A1 L1 L 5(cid:24)(cid:19)(cid:30) (cid:18)(cid:27)66(cid:27)(cid:18)0(cid:8)0*(cid:3) (cid:2)(cid:19)(cid:31)(cid:13)(cid:24) (cid:19)(cid:22)(cid:24)(cid:14)6(cid:19)(cid:31)(cid:19)(cid:30) (cid:18)(cid:27)7 78(cid:18) (cid:18)(cid:7)9 7!(cid:31)/(cid:13)(cid:21)(cid:14)(cid:22)’(cid:14)&(cid:19)(cid:24) 7 (cid:16)(cid:5) &(cid:19)(cid:30)(cid:20)(cid:23) (cid:13) (cid:4)(cid:28):,(cid:14)3(cid:3)4 8-(cid:13)(cid:21)(cid:11)(cid:25)(cid:25)(cid:14);(cid:13)(cid:19)(cid:12)(cid:23)(cid:30) (cid:7) < < (cid:16)(cid:28)(cid:4)(cid:4) (cid:18)(cid:22)(cid:25)#(cid:13)#(cid:14)&(cid:11)(cid:20)"(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:23)(cid:19)(cid:20)"(cid:24)(cid:13) (cid:7)(cid:16) +(cid:28):, +(cid:28)(cid:15), +(cid:28)(cid:17), (cid:3)(cid:30)(cid:11)(cid:24)#(cid:22)’’(cid:14) (cid:7)+ (cid:4)(cid:28)(cid:4), < < 8-(cid:13)(cid:21)(cid:11)(cid:25)(cid:25)(cid:14)=(cid:19)#(cid:30)(cid:23) 0 (cid:15)(cid:28)(cid:5)(cid:4) (cid:15)(cid:28)(cid:17)(cid:4) (cid:17)(cid:28)(cid:16)(cid:4) (cid:18)(cid:22)(cid:25)#(cid:13)#(cid:14)&(cid:11)(cid:20)"(cid:11)(cid:12)(cid:13)(cid:14)=(cid:19)#(cid:30)(cid:23) 0+ ,(cid:28)(cid:4)(cid:4) ,(cid:28)1(cid:4) ,(cid:28):(cid:4) 8-(cid:13)(cid:21)(cid:11)(cid:25)(cid:25)(cid:14)6(cid:13)(cid:24)(cid:12)(cid:30)(cid:23) (cid:2) (cid:15)(cid:28)(cid:6)(cid:4) (cid:17)(cid:28)(cid:16)(cid:4) (cid:17)(cid:28),(cid:4) (cid:29)(cid:22)(cid:22)(cid:30)(cid:14)6(cid:13)(cid:24)(cid:12)(cid:30)(cid:23) 6 (cid:4)(cid:28),, (cid:4)(cid:28)(cid:15), (cid:4)(cid:28)(cid:6), (cid:29)(cid:22)(cid:22)(cid:30)(cid:10)(cid:21)(cid:19)(cid:24)(cid:30) 6+ +(cid:28)(cid:16),(cid:14)*0(cid:29) 6(cid:13)(cid:11)#(cid:14)(cid:8)(cid:23)(cid:19)(cid:20)"(cid:24)(cid:13) (cid:20) (cid:4)(cid:28)(cid:4)(cid:6) < (cid:4)(cid:28)(cid:16), (cid:29)(cid:22)(cid:22)(cid:30)(cid:14)(cid:7)(cid:24)(cid:12)(cid:25)(cid:13) (cid:3) (cid:4)> (cid:5)> (cid:17)> 6(cid:13)(cid:11)#(cid:14)=(cid:19)#(cid:30)(cid:23) / (cid:4)(cid:28)(cid:16)(cid:16) < (cid:4)(cid:28)1(cid:17) (cid:2)(cid:3)(cid:4)(cid:5)(cid:16)(cid:6) +(cid:28) &(cid:19)(cid:24)(cid:14)+(cid:14)-(cid:19) !(cid:11)(cid:25)(cid:14)(cid:19)(cid:24)#(cid:13).(cid:14)’(cid:13)(cid:11)(cid:30)!(cid:21)(cid:13)(cid:14)(cid:31)(cid:11)(cid:26)(cid:14)-(cid:11)(cid:21)(cid:26)%(cid:14)/!(cid:30)(cid:14)(cid:31)! (cid:30)(cid:14)/(cid:13)(cid:14)(cid:25)(cid:22)(cid:20)(cid:11)(cid:30)(cid:13)#(cid:14)$(cid:19)(cid:30)(cid:23)(cid:19)(cid:24)(cid:14)(cid:30)(cid:23)(cid:13)(cid:14)(cid:23)(cid:11)(cid:30)(cid:20)(cid:23)(cid:13)#(cid:14)(cid:11)(cid:21)(cid:13)(cid:11)(cid:28) (cid:16)(cid:28) (cid:2)(cid:19)(cid:31)(cid:13)(cid:24) (cid:19)(cid:22)(cid:24) (cid:14)(cid:2)(cid:14)(cid:11)(cid:24)#(cid:14)0+(cid:14)#(cid:22)(cid:14)(cid:24)(cid:22)(cid:30)(cid:14)(cid:19)(cid:24)(cid:20)(cid:25)!#(cid:13)(cid:14)(cid:31)(cid:22)(cid:25)#(cid:14)’(cid:25)(cid:11) (cid:23)(cid:14)(cid:22)(cid:21)(cid:14)(cid:10)(cid:21)(cid:22)(cid:30)(cid:21)! (cid:19)(cid:22)(cid:24) (cid:28)(cid:14)(cid:18)(cid:22)(cid:25)#(cid:14)’(cid:25)(cid:11) (cid:23)(cid:14)(cid:22)(cid:21)(cid:14)(cid:10)(cid:21)(cid:22)(cid:30)(cid:21)! (cid:19)(cid:22)(cid:24) (cid:14) (cid:23)(cid:11)(cid:25)(cid:25)(cid:14)(cid:24)(cid:22)(cid:30)(cid:14)(cid:13).(cid:20)(cid:13)(cid:13)#(cid:14)(cid:4)(cid:28)(cid:16)(cid:4)(cid:14)(cid:31)(cid:31)(cid:14)(cid:10)(cid:13)(cid:21)(cid:14) (cid:19)#(cid:13)(cid:28) 1(cid:28) (cid:2)(cid:19)(cid:31)(cid:13)(cid:24) (cid:19)(cid:22)(cid:24)(cid:19)(cid:24)(cid:12)(cid:14)(cid:11)(cid:24)#(cid:14)(cid:30)(cid:22)(cid:25)(cid:13)(cid:21)(cid:11)(cid:24)(cid:20)(cid:19)(cid:24)(cid:12)(cid:14)(cid:10)(cid:13)(cid:21)(cid:14)(cid:7)(cid:3)(cid:18)0(cid:14)2+(cid:5)(cid:28),(cid:18)(cid:28) 3(cid:3)4( 3(cid:11) (cid:19)(cid:20)(cid:14)(cid:2)(cid:19)(cid:31)(cid:13)(cid:24) (cid:19)(cid:22)(cid:24)(cid:28)(cid:14)(cid:8)(cid:23)(cid:13)(cid:22)(cid:21)(cid:13)(cid:30)(cid:19)(cid:20)(cid:11)(cid:25)(cid:25)(cid:26)(cid:14)(cid:13).(cid:11)(cid:20)(cid:30)(cid:14)-(cid:11)(cid:25)!(cid:13)(cid:14) (cid:23)(cid:22)$(cid:24)(cid:14)$(cid:19)(cid:30)(cid:23)(cid:22)!(cid:30)(cid:14)(cid:30)(cid:22)(cid:25)(cid:13)(cid:21)(cid:11)(cid:24)(cid:20)(cid:13) (cid:28) *0(cid:29)( *(cid:13)’(cid:13)(cid:21)(cid:13)(cid:24)(cid:20)(cid:13)(cid:14)(cid:2)(cid:19)(cid:31)(cid:13)(cid:24) (cid:19)(cid:22)(cid:24)%(cid:14)! !(cid:11)(cid:25)(cid:25)(cid:26)(cid:14)$(cid:19)(cid:30)(cid:23)(cid:22)!(cid:30)(cid:14)(cid:30)(cid:22)(cid:25)(cid:13)(cid:21)(cid:11)(cid:24)(cid:20)(cid:13)%(cid:14)’(cid:22)(cid:21)(cid:14)(cid:19)(cid:24)’(cid:22)(cid:21)(cid:31)(cid:11)(cid:30)(cid:19)(cid:22)(cid:24)(cid:14)(cid:10)!(cid:21)(cid:10)(cid:22) (cid:13) (cid:14)(cid:22)(cid:24)(cid:25)(cid:26)(cid:28) (cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:8)(cid:13)(cid:20)(cid:23)(cid:24)(cid:22)(cid:25)(cid:22)(cid:12)(cid:26)(cid:2)(cid:21)(cid:11)$(cid:19)(cid:24)(cid:12)4(cid:4)(cid:5)(cid:9)+1(cid:16)3 © 2008 Microchip Technology Inc. DS22103A-page 47

MCP23018/MCP23S18 (cid:7)&(cid:9)(cid:10)(cid:5)(cid:11)(cid:12)(cid:13)(cid:19)(cid:23)(cid:17)(cid:22)(cid:22)#(cid:13)(cid:14)(cid:15)(cid:11)(cid:16)(cid:4)(cid:17)(cid:18)(cid:13)’(cid:26)(cid:11)(cid:15)(cid:13)((cid:22)(cid:9)(cid:10)(cid:17)(cid:22)(cid:5)(cid:13)(cid:27)(cid:19)(cid:14)(cid:28)(cid:13)(cid:29)(cid:13) !!(cid:13)(cid:24)(cid:17)(cid:15)(cid:13)"(cid:3)(cid:12)#(cid:13)$(cid:19)(cid:14)’((cid:14)% (cid:2)(cid:3)(cid:4)(cid:5)(cid:6) (cid:29)(cid:22)(cid:21)(cid:14)(cid:30)(cid:23)(cid:13)(cid:14)(cid:31)(cid:22) (cid:30)(cid:14)(cid:20)!(cid:21)(cid:21)(cid:13)(cid:24)(cid:30)(cid:14)(cid:10)(cid:11)(cid:20)"(cid:11)(cid:12)(cid:13)(cid:14)#(cid:21)(cid:11)$(cid:19)(cid:24)(cid:12) %(cid:14)(cid:10)(cid:25)(cid:13)(cid:11) (cid:13)(cid:14) (cid:13)(cid:13)(cid:14)(cid:30)(cid:23)(cid:13)(cid:14)(cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:14)&(cid:11)(cid:20)"(cid:11)(cid:12)(cid:19)(cid:24)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:20)(cid:19)’(cid:19)(cid:20)(cid:11)(cid:30)(cid:19)(cid:22)(cid:24)(cid:14)(cid:25)(cid:22)(cid:20)(cid:11)(cid:30)(cid:13)#(cid:14)(cid:11)(cid:30)(cid:14) (cid:23)(cid:30)(cid:30)(cid:10)())$$$(cid:28)(cid:31)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:28)(cid:20)(cid:22)(cid:31))(cid:10)(cid:11)(cid:20)"(cid:11)(cid:12)(cid:19)(cid:24)(cid:12) N NOTE1 E1 1 2 3 D E A A2 L c A1 b1 b e eB 5(cid:24)(cid:19)(cid:30) (cid:27)74;0(cid:3) (cid:2)(cid:19)(cid:31)(cid:13)(cid:24) (cid:19)(cid:22)(cid:24)(cid:14)6(cid:19)(cid:31)(cid:19)(cid:30) (cid:18)(cid:27)7 78(cid:18) (cid:18)(cid:7)9 7!(cid:31)/(cid:13)(cid:21)(cid:14)(cid:22)’(cid:14)&(cid:19)(cid:24) 7 (cid:16)(cid:17) &(cid:19)(cid:30)(cid:20)(cid:23) (cid:13) (cid:28)+(cid:4)(cid:4)(cid:14)3(cid:3)4 (cid:8)(cid:22)(cid:10)(cid:14)(cid:30)(cid:22)(cid:14)(cid:3)(cid:13)(cid:11)(cid:30)(cid:19)(cid:24)(cid:12)(cid:14)&(cid:25)(cid:11)(cid:24)(cid:13) (cid:7) < < (cid:28)(cid:16)(cid:4)(cid:4) (cid:18)(cid:22)(cid:25)#(cid:13)#(cid:14)&(cid:11)(cid:20)"(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:23)(cid:19)(cid:20)"(cid:24)(cid:13) (cid:7)(cid:16) (cid:28)+(cid:16)(cid:4) (cid:28)+1, (cid:28)+,(cid:4) 3(cid:11) (cid:13)(cid:14)(cid:30)(cid:22)(cid:14)(cid:3)(cid:13)(cid:11)(cid:30)(cid:19)(cid:24)(cid:12)(cid:14)&(cid:25)(cid:11)(cid:24)(cid:13) (cid:7)+ (cid:28)(cid:4)+, < < (cid:3)(cid:23)(cid:22)!(cid:25)#(cid:13)(cid:21)(cid:14)(cid:30)(cid:22)(cid:14)(cid:3)(cid:23)(cid:22)!(cid:25)#(cid:13)(cid:21)(cid:14)=(cid:19)#(cid:30)(cid:23) 0 (cid:28)(cid:16)(cid:6)(cid:4) (cid:28)1+(cid:4) (cid:28)11, (cid:18)(cid:22)(cid:25)#(cid:13)#(cid:14)&(cid:11)(cid:20)"(cid:11)(cid:12)(cid:13)(cid:14)=(cid:19)#(cid:30)(cid:23) 0+ (cid:28)(cid:16)(cid:5)(cid:4) (cid:28)(cid:16)(cid:17), (cid:28)(cid:16)(cid:6), 8-(cid:13)(cid:21)(cid:11)(cid:25)(cid:25)(cid:14)6(cid:13)(cid:24)(cid:12)(cid:30)(cid:23) (cid:2) +(cid:28)1(cid:5), +(cid:28)1:, +(cid:28)(cid:5)(cid:4)(cid:4) (cid:8)(cid:19)(cid:10)(cid:14)(cid:30)(cid:22)(cid:14)(cid:3)(cid:13)(cid:11)(cid:30)(cid:19)(cid:24)(cid:12)(cid:14)&(cid:25)(cid:11)(cid:24)(cid:13) 6 (cid:28)++(cid:4) (cid:28)+1(cid:4) (cid:28)+,(cid:4) 6(cid:13)(cid:11)#(cid:14)(cid:8)(cid:23)(cid:19)(cid:20)"(cid:24)(cid:13) (cid:20) (cid:28)(cid:4)(cid:4)(cid:17) (cid:28)(cid:4)+(cid:4) (cid:28)(cid:4)+, 5(cid:10)(cid:10)(cid:13)(cid:21)(cid:14)6(cid:13)(cid:11)#(cid:14)=(cid:19)#(cid:30)(cid:23) /+ (cid:28)(cid:4)(cid:5)(cid:4) (cid:28)(cid:4),(cid:4) (cid:28)(cid:4)(cid:15)(cid:4) 6(cid:22)$(cid:13)(cid:21)(cid:14)6(cid:13)(cid:11)#(cid:14)=(cid:19)#(cid:30)(cid:23) / (cid:28)(cid:4)+(cid:5) (cid:28)(cid:4)+(cid:17) (cid:28)(cid:4)(cid:16)(cid:16) 8-(cid:13)(cid:21)(cid:11)(cid:25)(cid:25)(cid:14)*(cid:22)$(cid:14)(cid:3)(cid:10)(cid:11)(cid:20)(cid:19)(cid:24)(cid:12)(cid:14)(cid:14)? (cid:13)3 < < (cid:28)(cid:5)1(cid:4) (cid:2)(cid:3)(cid:4)(cid:5)(cid:16)(cid:6) +(cid:28) &(cid:19)(cid:24)(cid:14)+(cid:14)-(cid:19) !(cid:11)(cid:25)(cid:14)(cid:19)(cid:24)#(cid:13).(cid:14)’(cid:13)(cid:11)(cid:30)!(cid:21)(cid:13)(cid:14)(cid:31)(cid:11)(cid:26)(cid:14)-(cid:11)(cid:21)(cid:26)%(cid:14)/!(cid:30)(cid:14)(cid:31)! (cid:30)(cid:14)/(cid:13)(cid:14)(cid:25)(cid:22)(cid:20)(cid:11)(cid:30)(cid:13)#(cid:14)$(cid:19)(cid:30)(cid:23)(cid:19)(cid:24)(cid:14)(cid:30)(cid:23)(cid:13)(cid:14)(cid:23)(cid:11)(cid:30)(cid:20)(cid:23)(cid:13)#(cid:14)(cid:11)(cid:21)(cid:13)(cid:11)(cid:28) (cid:16)(cid:28) ?(cid:14)(cid:3)(cid:19)(cid:12)(cid:24)(cid:19)’(cid:19)(cid:20)(cid:11)(cid:24)(cid:30)(cid:14)4(cid:23)(cid:11)(cid:21)(cid:11)(cid:20)(cid:30)(cid:13)(cid:21)(cid:19) (cid:30)(cid:19)(cid:20)(cid:28) 1(cid:28) (cid:2)(cid:19)(cid:31)(cid:13)(cid:24) (cid:19)(cid:22)(cid:24) (cid:14)(cid:2)(cid:14)(cid:11)(cid:24)#(cid:14)0+(cid:14)#(cid:22)(cid:14)(cid:24)(cid:22)(cid:30)(cid:14)(cid:19)(cid:24)(cid:20)(cid:25)!#(cid:13)(cid:14)(cid:31)(cid:22)(cid:25)#(cid:14)’(cid:25)(cid:11) (cid:23)(cid:14)(cid:22)(cid:21)(cid:14)(cid:10)(cid:21)(cid:22)(cid:30)(cid:21)! (cid:19)(cid:22)(cid:24) (cid:28)(cid:14)(cid:18)(cid:22)(cid:25)#(cid:14)’(cid:25)(cid:11) (cid:23)(cid:14)(cid:22)(cid:21)(cid:14)(cid:10)(cid:21)(cid:22)(cid:30)(cid:21)! (cid:19)(cid:22)(cid:24) (cid:14) (cid:23)(cid:11)(cid:25)(cid:25)(cid:14)(cid:24)(cid:22)(cid:30)(cid:14)(cid:13).(cid:20)(cid:13)(cid:13)#(cid:14)(cid:28)(cid:4)+(cid:4)@(cid:14)(cid:10)(cid:13)(cid:21)(cid:14) (cid:19)#(cid:13)(cid:28) (cid:5)(cid:28) (cid:2)(cid:19)(cid:31)(cid:13)(cid:24) (cid:19)(cid:22)(cid:24)(cid:19)(cid:24)(cid:12)(cid:14)(cid:11)(cid:24)#(cid:14)(cid:30)(cid:22)(cid:25)(cid:13)(cid:21)(cid:11)(cid:24)(cid:20)(cid:19)(cid:24)(cid:12)(cid:14)(cid:10)(cid:13)(cid:21)(cid:14)(cid:7)(cid:3)(cid:18)0(cid:14)2+(cid:5)(cid:28),(cid:18)(cid:28) 3(cid:3)4( 3(cid:11) (cid:19)(cid:20)(cid:14)(cid:2)(cid:19)(cid:31)(cid:13)(cid:24) (cid:19)(cid:22)(cid:24)(cid:28)(cid:14)(cid:8)(cid:23)(cid:13)(cid:22)(cid:21)(cid:13)(cid:30)(cid:19)(cid:20)(cid:11)(cid:25)(cid:25)(cid:26)(cid:14)(cid:13).(cid:11)(cid:20)(cid:30)(cid:14)-(cid:11)(cid:25)!(cid:13)(cid:14) (cid:23)(cid:22)$(cid:24)(cid:14)$(cid:19)(cid:30)(cid:23)(cid:22)!(cid:30)(cid:14)(cid:30)(cid:22)(cid:25)(cid:13)(cid:21)(cid:11)(cid:24)(cid:20)(cid:13) (cid:28) (cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:8)(cid:13)(cid:20)(cid:23)(cid:24)(cid:22)(cid:25)(cid:22)(cid:12)(cid:26)(cid:2)(cid:21)(cid:11)$(cid:19)(cid:24)(cid:12)4(cid:4)(cid:5)(cid:9)(cid:4)(cid:15)(cid:4)3 DS22103A-page 48 © 2008 Microchip Technology Inc.

MCP23018/MCP23S18 (cid:7)&(cid:9)(cid:10)(cid:5)(cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:11)(cid:16)(cid:4)(cid:17)(cid:18)(cid:13)(cid:19)(cid:24)(cid:11)(cid:15)(cid:15)(cid:13)(cid:25)(cid:26)(cid:4)(cid:15)(cid:17)(cid:22)(cid:5)(cid:13)(cid:27)(cid:19)(cid:25)(cid:28)(cid:13)(cid:29)(cid:13))(cid:17)(cid:12)(cid:5)*(cid:13)+(cid:31)(cid:30)!(cid:13)(cid:24)(cid:24)(cid:13)"(cid:3)(cid:12)#(cid:13)$(cid:19)(cid:25)(,% (cid:2)(cid:3)(cid:4)(cid:5)(cid:6) (cid:29)(cid:22)(cid:21)(cid:14)(cid:30)(cid:23)(cid:13)(cid:14)(cid:31)(cid:22) (cid:30)(cid:14)(cid:20)!(cid:21)(cid:21)(cid:13)(cid:24)(cid:30)(cid:14)(cid:10)(cid:11)(cid:20)"(cid:11)(cid:12)(cid:13)(cid:14)#(cid:21)(cid:11)$(cid:19)(cid:24)(cid:12) %(cid:14)(cid:10)(cid:25)(cid:13)(cid:11) (cid:13)(cid:14) (cid:13)(cid:13)(cid:14)(cid:30)(cid:23)(cid:13)(cid:14)(cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:14)&(cid:11)(cid:20)"(cid:11)(cid:12)(cid:19)(cid:24)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:20)(cid:19)’(cid:19)(cid:20)(cid:11)(cid:30)(cid:19)(cid:22)(cid:24)(cid:14)(cid:25)(cid:22)(cid:20)(cid:11)(cid:30)(cid:13)#(cid:14)(cid:11)(cid:30)(cid:14) (cid:23)(cid:30)(cid:30)(cid:10)())$$$(cid:28)(cid:31)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:28)(cid:20)(cid:22)(cid:31))(cid:10)(cid:11)(cid:20)"(cid:11)(cid:12)(cid:19)(cid:24)(cid:12) D N E E1 NOTE1 1 2 3 e b h α h φ c A A2 L A1 L1 β 5(cid:24)(cid:19)(cid:30) (cid:18)(cid:27)66(cid:27)(cid:18)0(cid:8)0*(cid:3) (cid:2)(cid:19)(cid:31)(cid:13)(cid:24) (cid:19)(cid:22)(cid:24)(cid:14)6(cid:19)(cid:31)(cid:19)(cid:30) (cid:18)(cid:27)7 78(cid:18) (cid:18)(cid:7)9 7!(cid:31)/(cid:13)(cid:21)(cid:14)(cid:22)’(cid:14)&(cid:19)(cid:24) 7 (cid:16)(cid:17) &(cid:19)(cid:30)(cid:20)(cid:23) (cid:13) +(cid:28)(cid:16)(cid:15)(cid:14)3(cid:3)4 8-(cid:13)(cid:21)(cid:11)(cid:25)(cid:25)(cid:14);(cid:13)(cid:19)(cid:12)(cid:23)(cid:30) (cid:7) < < (cid:16)(cid:28):, (cid:18)(cid:22)(cid:25)#(cid:13)#(cid:14)&(cid:11)(cid:20)"(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:23)(cid:19)(cid:20)"(cid:24)(cid:13) (cid:7)(cid:16) (cid:16)(cid:28)(cid:4), < < (cid:3)(cid:30)(cid:11)(cid:24)#(cid:22)’’(cid:14)(cid:14)? (cid:7)+ (cid:4)(cid:28)+(cid:4) < (cid:4)(cid:28)1(cid:4) 8-(cid:13)(cid:21)(cid:11)(cid:25)(cid:25)(cid:14)=(cid:19)#(cid:30)(cid:23) 0 +(cid:4)(cid:28)1(cid:4)(cid:14)3(cid:3)4 (cid:18)(cid:22)(cid:25)#(cid:13)#(cid:14)&(cid:11)(cid:20)"(cid:11)(cid:12)(cid:13)(cid:14)=(cid:19)#(cid:30)(cid:23) 0+ (cid:15)(cid:28),(cid:4)(cid:14)3(cid:3)4 8-(cid:13)(cid:21)(cid:11)(cid:25)(cid:25)(cid:14)6(cid:13)(cid:24)(cid:12)(cid:30)(cid:23) (cid:2) +(cid:15)(cid:28)(cid:6)(cid:4)(cid:14)3(cid:3)4 4(cid:23)(cid:11)(cid:31)’(cid:13)(cid:21)(cid:14)A(cid:22)(cid:10)(cid:30)(cid:19)(cid:22)(cid:24)(cid:11)(cid:25)B (cid:23) (cid:4)(cid:28)(cid:16), < (cid:4)(cid:28)(cid:15), (cid:29)(cid:22)(cid:22)(cid:30)(cid:14)6(cid:13)(cid:24)(cid:12)(cid:30)(cid:23) 6 (cid:4)(cid:28)(cid:5)(cid:4) < +(cid:28)(cid:16)(cid:15) (cid:29)(cid:22)(cid:22)(cid:30)(cid:10)(cid:21)(cid:19)(cid:24)(cid:30) 6+ +(cid:28)(cid:5)(cid:4)(cid:14)*0(cid:29) (cid:29)(cid:22)(cid:22)(cid:30)(cid:14)(cid:7)(cid:24)(cid:12)(cid:25)(cid:13)(cid:14)(cid:8)(cid:22)(cid:10) (cid:3) (cid:4)> < (cid:17)> 6(cid:13)(cid:11)#(cid:14)(cid:8)(cid:23)(cid:19)(cid:20)"(cid:24)(cid:13) (cid:20) (cid:4)(cid:28)+(cid:17) < (cid:4)(cid:28)11 6(cid:13)(cid:11)#(cid:14)=(cid:19)#(cid:30)(cid:23) / (cid:4)(cid:28)1+ < (cid:4)(cid:28),+ (cid:18)(cid:22)(cid:25)#(cid:14)(cid:2)(cid:21)(cid:11)’(cid:30)(cid:14)(cid:7)(cid:24)(cid:12)(cid:25)(cid:13)(cid:14)(cid:8)(cid:22)(cid:10) (cid:4) ,> < +,> (cid:18)(cid:22)(cid:25)#(cid:14)(cid:2)(cid:21)(cid:11)’(cid:30)(cid:14)(cid:7)(cid:24)(cid:12)(cid:25)(cid:13)(cid:14)3(cid:22)(cid:30)(cid:30)(cid:22)(cid:31) (cid:5) ,> < +,> (cid:2)(cid:3)(cid:4)(cid:5)(cid:16)(cid:6) +(cid:28) &(cid:19)(cid:24)(cid:14)+(cid:14)-(cid:19) !(cid:11)(cid:25)(cid:14)(cid:19)(cid:24)#(cid:13).(cid:14)’(cid:13)(cid:11)(cid:30)!(cid:21)(cid:13)(cid:14)(cid:31)(cid:11)(cid:26)(cid:14)-(cid:11)(cid:21)(cid:26)%(cid:14)/!(cid:30)(cid:14)(cid:31)! (cid:30)(cid:14)/(cid:13)(cid:14)(cid:25)(cid:22)(cid:20)(cid:11)(cid:30)(cid:13)#(cid:14)$(cid:19)(cid:30)(cid:23)(cid:19)(cid:24)(cid:14)(cid:30)(cid:23)(cid:13)(cid:14)(cid:23)(cid:11)(cid:30)(cid:20)(cid:23)(cid:13)#(cid:14)(cid:11)(cid:21)(cid:13)(cid:11)(cid:28) (cid:16)(cid:28) ?(cid:14)(cid:3)(cid:19)(cid:12)(cid:24)(cid:19)’(cid:19)(cid:20)(cid:11)(cid:24)(cid:30)(cid:14)4(cid:23)(cid:11)(cid:21)(cid:11)(cid:20)(cid:30)(cid:13)(cid:21)(cid:19) (cid:30)(cid:19)(cid:20)(cid:28) 1(cid:28) (cid:2)(cid:19)(cid:31)(cid:13)(cid:24) (cid:19)(cid:22)(cid:24) (cid:14)(cid:2)(cid:14)(cid:11)(cid:24)#(cid:14)0+(cid:14)#(cid:22)(cid:14)(cid:24)(cid:22)(cid:30)(cid:14)(cid:19)(cid:24)(cid:20)(cid:25)!#(cid:13)(cid:14)(cid:31)(cid:22)(cid:25)#(cid:14)’(cid:25)(cid:11) (cid:23)(cid:14)(cid:22)(cid:21)(cid:14)(cid:10)(cid:21)(cid:22)(cid:30)(cid:21)! (cid:19)(cid:22)(cid:24) (cid:28)(cid:14)(cid:18)(cid:22)(cid:25)#(cid:14)’(cid:25)(cid:11) (cid:23)(cid:14)(cid:22)(cid:21)(cid:14)(cid:10)(cid:21)(cid:22)(cid:30)(cid:21)! (cid:19)(cid:22)(cid:24) (cid:14) (cid:23)(cid:11)(cid:25)(cid:25)(cid:14)(cid:24)(cid:22)(cid:30)(cid:14)(cid:13).(cid:20)(cid:13)(cid:13)#(cid:14)(cid:4)(cid:28)+,(cid:14)(cid:31)(cid:31)(cid:14)(cid:10)(cid:13)(cid:21)(cid:14) (cid:19)#(cid:13)(cid:28) (cid:5)(cid:28) (cid:2)(cid:19)(cid:31)(cid:13)(cid:24) (cid:19)(cid:22)(cid:24)(cid:19)(cid:24)(cid:12)(cid:14)(cid:11)(cid:24)#(cid:14)(cid:30)(cid:22)(cid:25)(cid:13)(cid:21)(cid:11)(cid:24)(cid:20)(cid:19)(cid:24)(cid:12)(cid:14)(cid:10)(cid:13)(cid:21)(cid:14)(cid:7)(cid:3)(cid:18)0(cid:14)2+(cid:5)(cid:28),(cid:18)(cid:28) 3(cid:3)4( 3(cid:11) (cid:19)(cid:20)(cid:14)(cid:2)(cid:19)(cid:31)(cid:13)(cid:24) (cid:19)(cid:22)(cid:24)(cid:28)(cid:14)(cid:8)(cid:23)(cid:13)(cid:22)(cid:21)(cid:13)(cid:30)(cid:19)(cid:20)(cid:11)(cid:25)(cid:25)(cid:26)(cid:14)(cid:13).(cid:11)(cid:20)(cid:30)(cid:14)-(cid:11)(cid:25)!(cid:13)(cid:14) (cid:23)(cid:22)$(cid:24)(cid:14)$(cid:19)(cid:30)(cid:23)(cid:22)!(cid:30)(cid:14)(cid:30)(cid:22)(cid:25)(cid:13)(cid:21)(cid:11)(cid:24)(cid:20)(cid:13) (cid:28) *0(cid:29)( *(cid:13)’(cid:13)(cid:21)(cid:13)(cid:24)(cid:20)(cid:13)(cid:14)(cid:2)(cid:19)(cid:31)(cid:13)(cid:24) (cid:19)(cid:22)(cid:24)%(cid:14)! !(cid:11)(cid:25)(cid:25)(cid:26)(cid:14)$(cid:19)(cid:30)(cid:23)(cid:22)!(cid:30)(cid:14)(cid:30)(cid:22)(cid:25)(cid:13)(cid:21)(cid:11)(cid:24)(cid:20)(cid:13)%(cid:14)’(cid:22)(cid:21)(cid:14)(cid:19)(cid:24)’(cid:22)(cid:21)(cid:31)(cid:11)(cid:30)(cid:19)(cid:22)(cid:24)(cid:14)(cid:10)!(cid:21)(cid:10)(cid:22) (cid:13) (cid:14)(cid:22)(cid:24)(cid:25)(cid:26)(cid:28) (cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:8)(cid:13)(cid:20)(cid:23)(cid:24)(cid:22)(cid:25)(cid:22)(cid:12)(cid:26)(cid:2)(cid:21)(cid:11)$(cid:19)(cid:24)(cid:12)4(cid:4)(cid:5)(cid:9)(cid:4),(cid:16)3 © 2008 Microchip Technology Inc. DS22103A-page 49

MCP23018/MCP23S18 NOTES: DS22103A-page 50 © 2008 Microchip Technology Inc.

MCP23018/MCP23S18 APPENDIX A: REVISION HISTORY Revision A (September 2008) • Original Release of this Document. © 2008 Microchip Technology Inc. DS22103A-page 51

MCP23018/MCP23S18 NOTES: DS22103A-page 52 © 2008 Microchip Technology Inc.

MCP23018/MCP23S18 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. – X /XX Examples: a) MCP23018-E/SP: Extended Temp., Device Temperature Package 28LD SPDIP package. Range b) MCP23018-E/SO: Extended Temp., 28LD SOIC package. Device MCP23018: 16-Bit I/O Expander w/ I2C™ Inter- c) MCP23018T-E/SO: Tape and Reel, face Extended Temp., MCP23018T: 16-Bit I/O Expander w/ I2C Interface 28LD SOIC package. (Tape and Reel) d) MCP23018-E/SS: Extended Temp., MCP23S18: 16-Bit I/O Expander w/ SPI Interface 24LD SSOP package. MCP23S18T: 16-Bit I/O Expander w/ SPI Interface e) MCP23018T-E/SS: Tape and Reel, (Tape and Reel) Extended Temp., 24LD SSOP package. f) MCP23018-E/MJ: Extended Temp., Temperature E = -40°C to +125°C (Extended) * 24LD QFN package. Range a) MCP23S18-E/SP: Extended Temp., Package MJ = Plastic Quad Flat, No Lead Package 28LD SPDIP package. (4x4x0.9mm Body), 24-Lead b) MCP23S18-E/SO: Extended Temp., SP = Skinny Plastic DIP (300 mil Body), 28-Lead 28LD SOIC package. SO = Plastic SOIC (300 mil Body), 28-Lead c) MCP23S18T-E/SO: Tape and Reel, SS = SSOP, (209 mil Body, 5.30mm), 24-Lead Extended Temp., 28LD SOIC package. d) MCP23S18T-E/MJ: Tape and Reel, Extended Temp., 24LD QFN package. © 2008 Microchip Technology Inc. DS22103A-page 53

MCP23018/MCP23S18 NOTES: DS22103A-page 54 © 2008 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, Accuron, and may be superseded by updates. It is your responsibility to dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, ensure that your application meets with your specifications. PICSTART, rfPIC, SmartShunt and UNI/O are registered MICROCHIP MAKES NO REPRESENTATIONS OR trademarks of Microchip Technology Incorporated in the WARRANTIES OF ANY KIND WHETHER EXPRESS OR U.S.A. and other countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Linear Active Thermistor, MXDEV, MXLAB, INCLUDING BUT NOT LIMITED TO ITS CONDITION, SEEVAL, SmartSensor and The Embedded Control Solutions QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, CodeGuard, devices in life support and/or safety applications is entirely at dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, the buyer’s risk, and the buyer agrees to defend, indemnify and ECONOMONITOR, FanSense, In-Circuit Serial hold harmless Microchip from any and all damages, claims, Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB suits, or expenses resulting from such use. No licenses are Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, conveyed, implicitly or otherwise, under any Microchip PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, intellectual property rights. PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2008, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2008 Microchip Technology Inc. DS22103A-page 55

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