MCP2021/2 LIN Transceiver with Voltage Regulator Features Description • The MCP2021 and MCP2022 are compliant with The MCP2021/2 provides a bidirectional, half-duplex LIN Bus Specifications 1.3, 2.0, and 2.1 and are communication physical interface to automotive, and compliant to SAE J2602 industrial LIN systems to meet the LIN bus specification • Support Baud Rates up to 20Kbaud with Revision 2.0. The device incorporates a voltage LIN-compatible output driver regulator with 5V @ 50mA or 3.3V @ 50mA regulated power supply output. The regulator is short circuit • 43V load dump protected protected, and is protected by an internal thermal shut- • Very low EMI meets stringent OEM requirements down circuit. The regulator has been specifically • Wide supply voltage, 6.0V - 18.0V continuous: designed to operate in the automotive environment and - Maximum input voltage of 30V will survive reverse battery connections, +43V load • Extended Temperature Range: -40 to +125°C dump transients, and double-battery jumps. The device has been designed to meet the stringent quiescent • Interface to PIC EUSART and standard USARTs current requirements of the automotive industry. • Local Interconnect Network (LIN) bus pin: - Internal pull-up resistor and diode MCP2021/2 family members: - Protected against ground shorts • 8-pin PDIP, DFN and SOIC packages: - Protected against loss of ground - MCP2021-330, LIN-compatible driver, 8-pin, 3.3V regulator - High current drive - MCP2021-500, LIN-compatible driver, • Automatic thermal shutdown 8-pin, 5.0V regulator • On-Board Voltage Regulator: • 14-lead PDIP, TSSOP and SOIC packages with - Output voltage of 5.0V with tolerances of RESET output: ±3% overtemperature range - MCP2022-330, LIN-compatible driver, - Available with alternate output voltage of 14-pin, 3.3V regulator 3.3V with tolerances of ±3% overtemperature - MCP2022-500, LIN-compatible driver, range 14-pin, 5.0V regulator - Maximum continuous input voltage of 30V - Internal thermal overload protection Package Types - Internal short circuit current limit - External components limited to filter DFN-8, PDIP-8, SOIC-8 capacitor only and load capacitor • Two low-power modes: RXD 1 M 8 FAULT/TXE C - Receiver on, Transmitter off, voltage CS/LWAKE 2 P 7 VBB 2 regulator on (≅85µA) VREG 3 02 6 LBUS - Receiver monitoring bus, Transmitter off, TXD 4 1 5 VSS voltage regulator off (≅ 16µA) PDIP-14, SOIC-14, TSSOP-14 RXD 1 14 FAULT/TXE CS/LWAKE 2 13 VBB VREG 3 M 12 LBUS C TXD 4 P 11 VSS 2 RESET 5 02 10 NC 2 NC 6 9 NC NC 7 8 NC © 2009 Microchip Technology Inc. DS22018E-page 1

MCP2021/2 Block Diagram Thermal Protection Short Circuit RESET Protection Voltage VBB Regulator Ratiometric Reference Internal Circuits VREG Wake-Up Logic and Power Control RXD ~30kΩ CS/LWAKE TXD OC LBUS FAULT/TXE VSS Thermal Short Circuit Protection Protection DS22018E-page 2 © 2009 Microchip Technology Inc.

MCP2021/2 1.0 DEVICE OVERVIEW 1.2 Internal Protection The MCP2021/2 provides a physical interface between 1.2.1 ESD PROTECTION a microcontroller and a LIN half-duplex bus. It is For component-level ESD ratings, please refer to the intended for automotive and industrial applications with maximum operation specifications. serial bus speeds up to 20Kbaud. The MCP2021/2 provides a half-duplex, bidirectional 1.2.2 GROUND LOSS PROTECTION communications interface between a microcontroller The LIN Bus specification states that the LIN pin must and the serial network bus. This device will translate transition to the recessive state when ground is the CMOS/TTL logic levels to LIN level logic, and vice disconnected. Therefore, a loss of ground effectively versa. forces the LIN line to a hi-impedance level. The LIN specification 2.0 requires that the transceiver of all nodes in the system be connected via the LIN pin, 1.2.3 THERMAL PROTECTION referenced to ground and with a maximum external The thermal protection circuit monitors the die termination resistance of 510Ω from LIN bus to battery temperature and is able to shut down the LIN supply. The 510Ω corresponds to 1 Master and 16 transmitter and voltage regulator. Slave nodes. There are three causes for a thermal overload. A The MCP2021-500 provides a +5V 50mA regulated thermal shut down can be triggered by any one, or a power output. The regulator uses a LDO design, is combination of, the following thermal overload short-circuit-protected and will turn the regulator output conditions. off if it falls below 3.5V. The MCP2021/2 also includes thermal shutdown protection. The regulator has been • Voltage regulator overload specifically designed to operate in the automotive • LIN bus output overload environment and will survive reverse battery connec- • Increase in die temperature due to increase in tions, +43V load dump transients and double-battery environment temperature jumps. The other members of the MCP2021-330 family Driving the TXD and checking the RXD pin makes it output +3.3V at 50mA with a turn-off voltage of 2.5V. possible to determine whether there is a bus contention (see Section1.6 “Internal Voltage Regulator”). (Rx = low, Tx = high) or a thermal overload condition (Rx = high, Tx = low). 1.1 Optional External Protection FIGURE 1-1: THERMAL SHUTDOWN 1.1.1 REVERSE BATTERY PROTECTION STATE DIAGRAMS An external reverse-battery-blocking diode should be used to provide polarity protection (see Example1-1). LIN bus Output shorted Overload to VBB 1.1.2 TRANSIENT VOLTAGE PROTECTION (LOAD DUMP) Voltage Operation Transmitter An external 43V transient suppressor (TVS) diode, RSehguutdlaotwonr Mode Shutdown between VBB and ground, with a 50Ω transient protection resistor (RTP) in series with the battery supply and the VBB pin serve to protect the device from Temp < SHUTDOWNTEMP Temp < SHUTDOWNTEMP power transients (see Example1-1) and ESD events. While this protection is optional, it should be considered as good engineering practice. EQUATION 1-1: RTP <= (VBBmin - 5.5) / 250mA. 5.5V = VUVLO + 1.0V, 250mA is the peak current at power-on when VBB = 5.5V © 2009 Microchip Technology Inc. DS22018E-page 3

MCP2021/2 1.3 Modes of Operation 1.3.4 OPERATION MODE For an overview of all operational modes, please refer In this mode, all internal modules are operational. to Table1-1. The MCP2021/2 will go into the Power-down mode on the falling edge of CS/LWAKE. 1.3.1 POWER-ON-RESET MODE 1.3.5 TRANSMITTER OFF MODE Upon application of VBB, the device enters Power-On- Reset mode (POR). During this mode, the part Whenever the FAULT/TXE signal is low and the LBUS maintains the digital section in a reset mode and waits transmitter is off. until the voltage on pin VBB rises above the “ON” The transmitter may be re-enabled whenever the threshold (Typ. 5.75V) to enter to the Ready mode. If FAULT/TXE signal returns high, either by removing the during the operation, the voltage on pin VBB falls below internal fault condition or the CPU returning the FAULT/ the “OFF” threshold (Typ. 4.25V), the part comes back TXE high. The transmitter will not be enabled if the to the Power-On-Reset mode. FAULT/TXE pin is brought high when the internal fault is still present. 1.3.2 POWER-DOWN MODE The transmitter is also turned off whenever the voltage In the Power-down mode, the transmitter and the regulator is unstable or recovering from a fault. This voltage regulator are both off. Only the receiver prevents unwanted disruption of the bus during times of section, and the CS/LWAKE pin wake-up circuits are in uncertain operation. operation. This is the lowest power mode. If any bus activity (e.g. a BREAK character) or CS/ 1.3.5.1 Wake-up LWAKE going to a high level should occur during The Wake-up sub module observes the LBUS in order Power-down mode, the device will immediately enter to detect bus activity. Bus activity is detected when the the Ready mode, enable the voltage regulator, and voltage on the LBUS stays below a threshold of once the output has stabilized (approximately 0.3ms to approximately 3V for at least a typical duration of 10µs. 1.2ms), go to the Operation mode. Such a condition causes the device to leave the Power- down mode. Note: The above time interval < 1.2ms assumes 12V VBB input and no thermal shutdown FIGURE 1-2: OPERATIONAL MODES event. STATE DIAGRAMS The part will also enter the Ready mode, followed by the Operation mode, if the CS/LWAKE pin should CS/LWAKE become active true (‘1’). = false Power-down Bus Activity Mode OR The part may only enter the Power-down mode after CS/LWAKE = true going through an Operation mode step. CS/LWAKE Transmitter = false 1.3.3 READY MODE Off Upon entering the Ready mode, the voltage regulator Mode Operation Ready VBBOK = true Mode Mode and receiver threshold detect circuit are powered up. FAULT/TXE The transmitter remains in power down mode. The = false device is ready to receive data but not to transmit. If a microcontroller is being driven by the voltage regulator FAULT/TXE = true VREGOK = true POR AND output, it will go through a Power-on Reset and initial- CS/LWAKE = true ization sequence. The LIN pin is in the recessive state. Start The device will stay in the Ready mode until the output of the voltage regulator has stabilized and CS/LWAKE Note: While the MCP2021/2 is in shutdown, TXD pin is true (‘1’). After VREG is OK and CS/LWAKE pin is should not be actively driven high or it may true, the transmitter is enabled and the part enters the power internal logic through the ESD Operation mode. diodes and may damage the device. On Power-on of the VBB supply pin, the component will stay in the Ready mode if CS/LWAKE is low. If CS/ LWAKE is high, the device will immediately enter the Operation mode. DS22018E-page 4 © 2009 Microchip Technology Inc.

MCP2021/2 TABLE 1-1: OVERVIEW OF OPERATIONAL MODES Voltage State Transmitter Receiver Operation Comments Regulator POR OFF OFF OFF Read CS/LWAKE, if LOW, then READY, if HIGH, Operational mode READY OFF Activity ON If CS/LWAKE high level, then Operation Bus Off state Detect mode OPERATION ON ON ON If CS/LWAKE low level, then Power down Normal If FAULT/TXE low level, then Transmitter- Operation Off mode mode POWER DOWN OFF Activity OFF On LIN bus falling, go to READY mode. Low Power Detect On CS/LWAKE high level, go to mode Operational mode TRANSMITTER- OFF ON ON If CS/LWAKE low level, then Power down OFF If FAULT/TXE high, then Operation mode 1.4 Typical Applications EXAMPLE 1-1: TYPICAL MCP2021 APPLICATION +12 +12 RTP(5) WAKE-UP 43V(5) CF Master Node Only +12 220kΩ CG VDD VREG VBB TXD TXD 1kΩ RXD RXD LBUS LIN Bus I/O CS/LWAKE 27V(4) (3) I/O FAULT/TXE VSS 100nF Note1: See Figure2-3 for correct capacity and ESR for stable operation.. 2: CF is the filter capacitor for the external voltage supply. 3: This diode is only needed if CS/LWAKE is connected to 12V supply. 4: Transient suppressor diode. Vclamp L = 43V. 5: These components are required for additional load dump protection above 43V.. © 2009 Microchip Technology Inc. DS22018E-page 5

MCP2021/2 EXAMPLE 1-2: TYPICAL MCP2022 APPLICATION +12 +12 RTP(5) WAKE-UP 43V(5) CF Master Node Only +12 220kΩ CG VDD VREG VBB TXD TXD 1kΩ RXD RXD LBUS LIN Bus I/O CS/LWAKE 27V(4) (3) I/O FAULT/TXE INT RESET 100nF VSS VDD(6) Note1: See Figure2-3 for correct capacity and ESR for stable operation. 2: CF is the filter capacitor for the external voltage supply. 3: This diode is only needed if CS/LWAKE is connected to 12V supply. 4: Transient suppressor diode. Vclamp L = 43V. 5: These components are required for additional load dump protection above 43V. 6: Required if CPU does not have internal pullup. DS22018E-page 6 © 2009 Microchip Technology Inc.

MCP2021/2 EXAMPLE 1-3: TYPICAL MCP2022 APPLICATION +12 +12 RTP(5) WAKE-UP 43V(5) CF Master Node Only +12 220kΩ CG VDD VREG VBB TXD TXD 1kΩ RXD RXD LBUS LIN Bus I/O CS/LWAKE 27V(4) (3) I/O FAULT/TXE 1kΩ MCLR RESET VSS 100nF 5V Note1: See Figure2-3 for correct capacity and ESR for stable operation . 2: CF is the filter capacitor for the external voltage supply. 3: This diode is only needed if CS/LWAKE is connected to 12V supply. 4: Transient suppressor diode. Vclamp L = 43V. 5: These components are required for additional load dump protection above 43V. FIGURE 1-3: TYPICAL LIN NETWORK CONFIGURATION 40m + Return LIN bus 1kΩ VBB LIN bus LIN bus LIN bus LIN bus MCP202X MCP202X MCP202X MCP202X Slave 1 Slave 2 Slave n <16 µC µC µC Master µC © 2009 Microchip Technology Inc. DS22018E-page 7

MCP2021/2 1.5 Pin Descriptions TABLE 1-1: PINOUT DESCRIPTIONS Devices Function Pin 8-Pin 14-Pin Pin Name DFN, PDIP, Type Normal Operation PDIP, SOIC, SOIC TSSOP VREG 3 3 O Power Output VSS 5 11 P Ground VBB 7 13 P Battery Supply TXD 4 4 I Transmit Data Input (TTL) RXD 1 1 O Receive Data Output (CMOS) LBUS 6 12 I/O LIN bus (bidirectional) CS/LWAKE 2 2 TTL Chip Select (TTL) FAULT/TXE 8 14 OD Fault Detect Output, Transmitter Enable (OD) RESET — 5 OD RESET signal Output (OD) Legend: TTL = TTL input buffer, ST = Schmitt Trigger input buffer, OD = Open-Drain output, P = Power, O = Output, I = Input 1.5.1 POWER OUTPUT (VREG) The internal LIN Receiver observes the activities on LIN bus, and generates the output signal RXD that Positive Supply Voltage Regulator Output pin. follows the state of the LBUS. A 1st degree 1MHz, low- 1.5.2 GROUND (VSS) pass input filter is placed to maintain EMI immunity. Ground pin. 1.5.7 CS/LWAKE 1.5.3 BATTERY (VBB) Chip Select Input pin. A internal pull-down resistor will Battery Positive Supply Voltage pin. This pin is also the keep the CS/LWAKE pin low. This is done to ensure input for the internal voltage regulator. that no disruptive data will be present on the bus while 1.5.4 TRANSMIT DATA INPUT (TXD) the microcontroller is executing a Power-on Reset and I/O initialization sequence. The pin must see a high The Transmit Data Input pin has an internal pull-up to level to activate the transmitter. VREG. The LIN pin is low (dominant) when TXD is low, and high (recessive) when TXD is high. If CS/LWAKE= ‘0’ when the VBB supply is turned on, the device stays in Ready mode (Low-power mode). In For extra bus security, TXD is internally forced to ‘1’ Ready mode, both the receiver and the voltage when VREG is less than 1.8V (typ.). regulator are on and the LIN transmitter driver is off. In case the thermal protection detects an over-temper- If CS/LWAKE = ‘1’ when the VBB supply is turned on, ature condition while the signal TXD is low, the the device will proceed to the Operation mode as soon transmitter is shutdown. The recovery from the thermal as the VREG output has stabilised. shutdown is equal to adequate cooling time. This pin may also be used as a local wake-up input 1.5.5 RECEIVE DATA OUTPUT (RXD) (See Example1-1). In this implementation, the micro- The Receive Data Output pin is a standard CMOS controller will set the I/O pin that controls the CS/ output and follows the state of the LIN pin. LWAKE as an high-impedance input. The internal pull- down resistor will keep the input low. An external 1.5.6 LIN BUS switch, or other source, can then wake-up both the The bidirectional LIN bus Interface pin is the driver unit transceiver and the microcontroller. for the LIN pin and is controlled by the signal TXD. LIN Note: CS/LWAKE should not be tied directly to has an open collector output with a current limitation. To reduce EMI, the edges during the signal changes VREG as this could force the MCP202x into Operation Mode before the are slope-controlled. To further reduce radiated microcontroller is initialized. emissions, the LBUS pin has corner-rounding control for both falling and rising edges. DS22018E-page 8 © 2009 Microchip Technology Inc.

MCP2021/2 1.5.8 FAULT/TXE The FAULT/TXE also signals a mismatch between the TXD input and the LBUS level. This can be used to Fault Detect output and Transmitter Enable input detect a bus contention. Since the bus exhibits a bidirectional pin. propagation delay, the sampling of the internal This pin is an open-drain output. Its state is defined as compare is debounced to eliminate false faults. shown in Table1-2. The transmitter driver is disabled This pin has an internal pull-up resistor of whenever this pin is low (‘0’), either from an internal approximately 750kΩ. fault condition or by external drive. This allows the transmitter to be placed in an off state and still allow the Note1: The FAULT/TXE pin is true (0) whenever voltage regulator to operate. Refer to Table1-1. the internal circuits have detected a short or thermal excursion and have disabled the LBUS output driver. 2: FAULT/TXE is true (0) when VREG not OK and has disabled the LBUS output driver. The FAULT/TXE pin sampled at a rate faster than every 10µs. TABLE 1-2: FAULT/TXE TRUTH TABLE FAULT/TXE TXD RXD LINBUS Thermal Definition In Out I/O Override External Driven Input Output L H VBB OFF H L FAULT, TXD driven low, LINBUS shorted to VBB (Note1) H H VBB OFF H H OK L L GND OFF H H OK H L GND OFF H H OK, data is being received from the LINBUS x x VBB ON H L FAULT, Tranceiver in thermal shutdown x x VBB x L x NO FAULT, the CPU is commanding the tranceiver to turn off the transmitter driver Legend: x = don’t care Note 1: The FAULT/TXE is valid after approximately 25µs after TXD falling edge. This is to eliminate false fault reporting during bus propagation delays. 1.5.9 RESET RESET is an open-drain output pin. This pin tracks an internal signal that tracks the internal system voltage has reached a valid, stable level. As long as the internal voltage is valid, this pin will remain high (‘1’). When the system voltage drops below the minimum required, the voltage regulator will shut down and immediately convert the RESET output to (‘0’). When connected to a micro-controller input, this can provide a warning that the voltage regulator is shutting down (see Example1- 2). Alternately, it can act as an external brown-out by connecting the RESET output to MCLR (see Example1-3). In addition to monitoring the internal voltage, RESET is asserted immediately upon entering the Powerdown mode. © 2009 Microchip Technology Inc. DS22018E-page 9

MCP2021/2 1.6 Internal Voltage Regulator When the input voltage (VBB) drops below the differential needed to provide stable regulation, the 1.6.1 5.0V REGULATOR output VREG) will track the input down to approximately +4.25V. The regulator will turn off the output at this The MCP2021 has a low-drop-out voltage, positive point. This will allow PIC® microcontrollers, with regulator capable of supplying 5.00VDC ±3% at up to internal POR circuits, to generate a clean arming of the 50mA of load current over the entire operating Power-on Reset trip point. The regulator output will temperature range of -40°C to +125°C. With a load current of 50mA, the minimum input to output voltage stay off until VBB is above +5.75VDC. differential required for the output to remain in In the start phase, the device must see at least 6.0V to regulation is typically +0.5V (+1V maximum over the initiate operation during power up. In the Power-down full operating temperature range). Quiescent current is mode, the VBB monitor will be turned off. less than 100µA with a full 50mA load current when the input to output voltage differential is greater than Note: The regulator has an overload current +3.00V. limiting of approximately 100mA. During a The regulator requires an external output bypass short circuit, the VREG is monitored. If capacitor for stability. See Figure2-3 for correct capac- VREG is lower than 3.5V, the VREG will turn off. After a recovery time of about three ity and ESR for stable operation. milliseconds, the VREG will be checked Designed for automotive applications, the regulator will again. If there is no short circuit, (VREG > protect itself from double-battery jumps and up to +43V 3.5V) then the VREG will be switched back load dump transients. The voltage regulator has both on. short-circuit and thermal shutdown protection built-in. The regulator has a thermal shutdown. If the thermal Regarding the correlation between VBB, VREG and IDD, protection circuit detects an over temperature please refer to Figure1-5 through1-7. When the input condition, and the signals TXD and RXD are LOW, or voltage (VBB) drops below the differential needed to TXD is HIGH, the regulator will shut down. The recovery provide stable regulation, the output Vreg will track the from the thermal shutdown is equal to adequate cooling input down to approximately 3.5V, at which point the time. regulator will turn off. This will allow microcontrollers with internal POR circuits to generate a clean arming of the Power-on Reset trip point. The MCP2021 will then monitor VBB and turn on the regulator when Vbb is 6.0V. FIGURE 1-4: VOLTAGE REGULATOR BLOCK DIAGRAM VREG Pass VBB Element Sampling Network Fast Transient Loop Buffer VSS VREF DS22018E-page 10 © 2009 Microchip Technology Inc.

MCP2021/2 1.6.2 3.3V REGULATOR Note: The regulator has an overload current A metal option provides for a alternate 3.30VDC ±3% limiting of approximately 100mA. If VREG at up to 50mA of load current over the entire operating is lower than 2.5V, the VREG will turn off. temperature range of -40°C to +125°C. All specifications given above for the 5.0V operation apply except for any difference noted here. The same input tracking of 4.25V applies the 3.3V regulator. FIGURE 1-5: VOLTAGE REGULATOR OUTPUT ON POWER-ON RESET VBB V 8 6 4 2 0 t VREG V 5.0 3.5 3 0 t (1) (2) (3) Note 1: Start-up, VBB < 5.75V, regulator off. 2: VBB > 5.75V, regulator on. 3: VBB ≤ 5.5V, regulator tracks VBB 4: VBB < 4.25V, regulator will turn off © 2009 Microchip Technology Inc. DS22018E-page 11

MCP2021/2 FIGURE 1-6: VOLTAGE REGULATOR OUTPUT ON POWER DIP VBB V 12 8 6 4 3.5 2 0 t VREG V 5 4 3.5 3 0 t (1) (2) (3) (4) Note 1: Voltage regulator on. 2: VBB ≤ 5.5V, regulator tracks VBB until VBB < 4.25V. 3: VREG < 3.5V, regulator is off. 4: VBB > 5.75V, regulator on. DS22018E-page 12 © 2009 Microchip Technology Inc.

MCP2021/2 FIGURE 1-7: VOLTAGE REGULATOR OUTPUT ON OVERCURRENT SITUATION IREG mA 50 0 t VREG V 6 5.0 3.5 3 0 t (1) (2) Note 1: IREG less than 50mA, regulator on. 2: After IREG exceeds IREGmax, voltage regulator output will be reduced until VREG off is reached. 1.7 ICSP™ Considerations The following should be considered when the MCP2021/2 is connected to pins supporting in-circuit programming: • Power used for programming the microcontroller can be supplied from the programmer, or from the MCP2021/2. • The voltage on VREG should not exceed the maximum output voltage of VREG. © 2009 Microchip Technology Inc. DS22018E-page 13

MCP2021/2 NOTES: DS22018E-page 14 © 2009 Microchip Technology Inc.

MCP2021/2 2.0 ELECTRICAL CHARACTERISTICS 2.1 Absolute Maximum Ratings† VIN DC Voltage on RXD and TXD........................................................................................................-0.3 to VREG+0.3V VIN DC Voltage on FAULT and RESET.........................................................................................................-0.3 to +5.5V VIN DC Voltage on CS/LWAKE.......................................................................................................................-0.3 to +43V VBB Battery Voltage, non-operating (LIN bus recessive, no regulator load, t < 60s).....................................-0.3 to +43V VBB Battery Voltage, transient ISO 7637 Test 1 ......................................................................................................-200V VBB Battery Voltage, transient ISO 7637 Test 2a ...................................................................................................+150V VBB Battery Voltage, transient ISO 7637 Test 3a ....................................................................................................-300V VBB Battery Voltage, transient ISO 7637 Test 3b ...................................................................................................+200V VBB Battery Voltage, continuous....................................................................................................................-0.3 to +30V VLBUS Bus Voltage, continuous.......................................................................................................................-18 to +30V VLBUS Bus Voltage, transient (Note1)............................................................................................................-27 to +43V ILBUS Bus Short Circuit Current Limit....................................................................................................................200mA ESD protection on LIN, VBB (IEC 61000-4-2, 330 Ohm, 150pF) (Note3)..............................................minimum ±9kV ESD protection on LIN, VBB (Charge Device Model) (Note2)..............................................................................±1500V ESD protection on LIN, VBB (Human Body Model, 1kOhm, 100pF) (Note4).......................................................±8kV ESD protection on LIN, VBB (Machine Model) (Note2)..........................................................................................±800V ESD protection on all other pins (Human Body Model) (Note2)............................................................................>4kV Maximum Junction Temperature.............................................................................................................................150°C Storage Temperature..................................................................................................................................-55 to +150°C Note1: ISO 7637/1 load dump compliant (t < 500ms). 2: According to JESD22-A114-B. 3: According to IBEE, without bus filter. 4: Limited by Test Equipment. † NOTICE: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. © 2009 Microchip Technology Inc. DS22018E-page 15

MCP2021/2 2.2 DC Specifications Electrical Characteristics: Unless otherwise indicated, all limits are specified for: DC Specifications VBB = 6.0V to 18.0V TA = -40°C to +125°C CLOADREG = 10µF Parameter Sym Min. Typ. Max. Units Conditions Power VBB Quiescent Operating IBBQ 115 210 µA IOUT = 0mA, Current LBUS recessive — 120 215 µA VOUT = 3.3V VBB Transmitter-off IBBTO — 90 190 µA With VREG on, transmitter Current off, receiver on, FAULT/ TXE = VIL, CS = VIH — 95 210 µA VOUT = 3.3V VBB Power-down Current IBBPD — 16 26 µA With VREG powered-off, receiver on and transmitter off, FAULT/TXE = VIH, TXD = VIH, CS = VIL) VBB Current with VSS IBBNOGND -1 — 1 mA VBB = 12V, GND to VBB, Floating VLIN = 0-18V Microcontroller Interface High Level Input Voltage VIH 2.0 or — VREG V (TXD, FAULT/TXE) (0.25VREG +0.3 +0.8) Low Level Input Voltage VIL -0.3 — 0.15 VREG V (TXD, FAULT/TXE) High Level Input Current IIH -2.5 — — µA Input voltage = 0.8*VREG (TXD, FAULT/TXE) Low Level Input Current IIL -10 — — µA Input voltage = 0.2*VREG (TXD, FAULT/TXE) Pull-up Current on Input IPUTXD -3.0 — — µA ~800kΩ internal pull-up to (TXD) VREG @ VIH = 0.7*VREG High Level Input Voltage VIH 0.7VREG — VBB V Through a current-limiting (CS/LWAKE) resistor Low Level Input Voltage VIL -0.3 — 0.3VREG V (CS/LWAKE) High Level Input Current IIH — — 7.0 µA Input voltage = 0.8*VREG (CS/LWAKE) Low Level Input Current IIL — — 3.0 µA Input voltage = 0.2*VREG (CS/LWAKE) Pull-down Current on IPDCS — — 6.0 µA ~1.3MΩ internal pull-down Input (CS/LWAKE) to VSS @ VIH = 3.5V Note 1: Internal current limited. 2.0ms maximum recovery time (RLBUS = 0Ω, TX = 0.4 VREG, VLBUS = VBB). 2: For design guidance only, not tested. 3: Node has to sustain the current that can flow under this condition; bus must be operational under this condition. DS22018E-page 16 © 2009 Microchip Technology Inc.

MCP2021/2 2.2 DC Specifications (Continued) Electrical Characteristics: Unless otherwise indicated, all limits are specified for: DC Specifications VBB = 6.0V to 18.0V TA = -40°C to +125°C CLOADREG = 10µF Parameter Sym Min. Typ. Max. Units Conditions Bus Interface High Level Input Voltage VIH(LBUS) 0.6 VBB — 18 V Recessive state Low Level Input Voltage VIL(LBUS) -8 — 0.4 VBB V Dominant state Input Hysteresis VHYS — — 0.175 VBB V VIH(LBUS) - VIL(LBUS) Low Level Output Current IOL(LBUS) 40 — 200 mA Output voltage = 0.1 VBB, VBB = 12V Pull-up Current on Input IPU(LBUS) 5 — 180 µA ~30kΩ internal pull-up @ VIH (LBUS) = 0.7 VBB Short Circuit Current ISC 50 — 200 mA (Note 1) Limit High Level Output VOH(LBUS) 0.8 VBB — VBB V VOH(LBUS) must be at least Voltage 0.8 VBB Low Level Output Voltage VOLLO — — 0.2 VBB V (LBUS) Input Leakage Current (at IBUS_PAS_DOM -1 — — mA Driver off, the receiver during VBUS = 0V, dominant bus level) VBAT = 12V Leakage Current IBUS_NO_GND -1 — +1 mA GNDDEVICE = VBAT, (disconnected from 0V < VBUS < 18V, ground) VBAT = 12V Leakage Current IBUS — — 10 µA VBAT = GND, (disconnected from VBAT) 0 < VBUS < 18V, TA = -40°C to +85°C (Note3) 50 µA TA = +85°C to +125°C Receiver Center Voltage VBUS_CNT 0.475 VBB 0.5 0.525 VBB V VBUS_CNT = (VIL (LBUS) + VBB VIH (LBUS))/2 Slave Termination Rslave 20 30 47 kΩ Note 1: Internal current limited. 2.0ms maximum recovery time (RLBUS = 0Ω, TX = 0.4 VREG, VLBUS = VBB). 2: For design guidance only, not tested. 3: Node has to sustain the current that can flow under this condition; bus must be operational under this condition. © 2009 Microchip Technology Inc. DS22018E-page 17

MCP2021/2 2.2 DC Specification (Continued) Electrical Characteristics: Unless otherwise indicated, all limits are specified for: DC Specifications VBB = 6.0V to 18.0V TA = -40°C to +125°C CLOADREG = 10µF Parameter Sym Min. Typ. Max. Units Conditions Voltage Regulator - 5.0V Output Voltage VOUT 4.85 5.00 5.15 V 0mA < IOUT < 50mA, Load Regulation ΔVOUT2 — 10 50 mV 5mA < IOUT < 50mA refer to Section1.6 “Internal Voltage Regulator” Quiescent Current IVRQ — — 25 µA IOUT = 0mA, (Note2) Power Supply Ripple PSRR — — 50 dB 1VPP @10-20kHz Reject CLOAD = 10µf, ILOAD = 50mA Output Noise Voltage eN — — 100 µVRMS 10Hz – 40MHz CFILTER = 10µf, CBP = 0.1µf, CLOAD 10µf, ILOAD = 50mA Shutdown Voltage VSD 3.5 — 4.0 V See Figure1-5 Input Voltage to Maintain VBB 6.0 — 18.0 V Regulation Input Voltage to Turn Off VOFF 4.0 — 4.5 V Output Input Voltage to Turn On VON 5.5 — 6.0 V Output Note 1: Internal current limited. 2.0ms maximum recovery time (RLBUS = 0Ω, TX = 0.4 VREG, VLBUS = VBB). 2: For design guidance only, not tested. 3: Node has to sustain the current that can flow under this condition; bus must be operational under this condition. FIGURE 2-1: MCP2021-500 SAFE OPERATING RANGE 60 12V DFN ) A m 50 ( 18V DFN d 12V SOIC a o 40 L r 18V SOIC o at 30 ul g e R 20 e g a olt 10 V 0 0482604284062840628406284062 432211- 1223345566788990112 ------ 1111 Temperature (°C) DS22018E-page 18 © 2009 Microchip Technology Inc.

MCP2021/2 2.2 DC Specification (Continued) Electrical Characteristics: Unless otherwise indicated, all limits are specified for: DC Specifications VBB = 6.0V to 18.0V TA = -40°C to +125°C CLOADREG = 10µF Parameter Sym Min. Typ. Max. Units Conditions Voltage Regulator - 3.3V Output Voltage VOUT 3.20 3.30 3.40 V 0mA < IOUT < 50mA Line Regulation ΔVOUT1 — 10 50 mV IOUT = 1mA, 6.0V < VBB < 18V Load Regulation ΔVOUT2 — 10 50 mV 5mA < IOUT < 50mA Refer to Section1.6 “Internal Voltage Regulator” Quiescent Current IVRQ — — 25 µA IOUT = 0mA, (Note2) Power Supply Ripple PSRR — — 50 dB 1VPP @10-20kHz Reject CLOAD = 10µf, ILOAD = 50mA Output Noise Voltage eN — — 100 µVRMS 10Hz – 40MHz /√Hz CFILTER = 10µf, CBP = 0.1µf CLOAD = 10µf, ILOAD = 50mA Shutdown Voltage VSD 2.5 — 2.7 V See Figure1-5 Input Voltage to Maintain VBB 6.0 — 18.0 V Regulation Input Voltage to Turn Off VOFF 4.0 — 4.5 V Output Input Voltage to Turn On VON 5.5 — 6.0 V Output Note 1: Internal current limited. 2.0ms maximum recovery time (RLBUS = 0Ω, TX = 0.4 VREG, VLBUS = VBB). 2: For design guidance only, not tested. 3: Node has to sustain the current that can flow under this condition; bus must be operational under this condition. FIGURE 2-2: MCP2021-330 SAFE OPERATING RANGE 60 12V DFN ) A m 50 d ( 12V SOIC 18V DFN a o 40 L r o at 30 18V SOIC ul g e R 20 e g a t 10 ol V 0 0482604284062840628406284062 432211- 1223345566788990112 ------ 1111 Temperature (°C) © 2009 Microchip Technology Inc. DS22018E-page 19

MCP2021/2 FIGURE 2-3: ESR CURVES FOR LOAD CAPACITOR SELECTION ESR Curves 10 Instable Stable 1 only with Tantalum or Electrolytic cap. Stable ] with m Tantalum, h Electrolytic and o 0.1 Instable Ceramic cap. [ R S E 0.01 Instable 0.001 0.1 1 10 100 1000 Load Capacitor [uF] DS22018E-page 20 © 2009 Microchip Technology Inc.

MCP2021/2 2.3 AC Specification AC CHARACTERISTICS VBB = 6.0V to 18.0V; TA = -40°C to +125°C Parameter Sym Min. Typ. Max. Units Test Conditions Bus Interface - Constant Slope Time Parameters Slope rising and falling tSLOPE 3.5 — 22.5 µs 7.3V <= VBB <= 18V edges Propagation Delay of tTRANSPD — — 4.0 µs tTRANSPD = max (tTRANSPDR or Transmitter tTRANSPDF) Propagation Delay of tRECPD — — 6.0 µs tRECPD = max (tRECPDR or Receiver tRECPDF) Symmetry of Propagation tRECSYM -2.0 — 2.0 µs tRECSYM = max (tRECPDF - Delay of Receiver rising tRECPDR) edge w.r.t. falling edge Symmetry of Propagation tTRANSSYM -2.0 — 2.0 µs tTRANSSYM = max (tTRANSPDF - Delay of Transmitter rising tTRANSPDR) edge w.r.t. falling edge Time to sample of FAULT/ tFAULT — — 32.5 µs tFAULT = max (tTRANSPD + TXE for bus conflict reporting tSLOPE + tRECPD) Duty Cycle 1 @20.0kbit/sec 39.6 — — %tBIT CBUS;RBUS conditions: 1nF; 1kΩ | 6.8nF; 660Ω | 10nF; 500Ω THREC(MAX) = 0.744 x VBB, THDOM(MAX) = 0.581 x VBB, VBB =7.0V - 18V; tBIT = 50µs. D1 = tBUS_REC(MIN) / 2 x tBIT) Duty Cycle 2 @20.0kbit/sec — — 58.1 %tBIT CBUS;RBUS conditions: 1nF; 1kΩ | 6.8nF; 660Ω | 10nF; 500Ω THREC(MAX) = 0.284 x VBB, THDOM(MAX) = 0.422 x VBB, VBB =7.6V - 18V; tBIT = 50µs. D2 = tBUS_REC(MAX) / 2 x tBIT) Duty Cycle 3 @10.4kbit/sec 41.7 — — %tBIT CBUS;RBUS conditions: 1nF; 1kΩ | 6.8nF; 660Ω | 10nF; 500Ω THREC(MAX) = 0.778 x VBB, THDOM(MAX) = 0.616 x VBB, VBB =7.0V - 18V; tBIT = 96µs. D3 = tBUS_REC(MIN) / 2 x tBIT) Duty Cycle 4 @10.4kbit/sec — — 59.0 %tBIT CBUS;RBUS conditions: 1nF; 1kΩ | 6.8nF; 660Ω | 10nF; 500Ω THREC(MAX) = 0.251 x VBB, THDOM(MAX) = 0.389 x VBB, VBB =7.6V - 18V; tBIT = 96µs. D4 = tBUS_REC(MAX) / 2 x tBIT) © 2009 Microchip Technology Inc. DS22018E-page 21

MCP2021/2 2.3 AC Specification (Continued) AC CHARACTERISTICS VBB = 6.0V to 18.0V; TA = -40°C to +125°C Parameter Sym Min. Typ. Max. Units Test Conditions Voltage Regulator Bus Activity Debounce time tBDB 5 10 20 µs Bus debounce time Bus Activity to Voltage tBACTVE 100 250 500 µs After Bus debounce time Regulator Enabled Voltage Regulator Enabled tVEVR — — 1200 µs (Note1) to Ready Chip Select to Operation tCSOR — — 500 µs (Note1) Ready Chip Select to Power-down tCSPD — — 80 µs Short circuit to shut-down tSHUTDOWN 20 — 100 µs RESET Timing VREG OK detect to RESET tRPU — — 10.0 µs inactive VREG OK detect to RESET tRPD — — 10.0 µs active Note 1: Time depends on external capacitance and load. 2.4 Thermal Specifications THERMAL CHARACTERISTICS Parameter Symbol Typ Max Units Test Conditions Recovery Temperature θRECOVERY +140 — °C Shutdown Temperature θSHUTDOWN +150 — °C Short Circuit Recovery Time tTHERM 1.5 5.0 ms Thermal Package Resistances Thermal Resistance, 8L-DFN θJA 35.7 — °C/W Thermal Resistance, 8L-PDIP θJA 89.3 — °C/W Thermal Resistance, 8L-SOIC θJA 149.5 — °C/W Thermal Resistance, 14L-PDIP θJA 70 — °C/W Thermal Resistance, 14L-SOIC θJA 95.3 — °C/W Thermal Resistance, 14L-TSSOP θJA 100 — °C/W Note 1: The maximum power dissipation is a function of TJMAX, ΘJA and ambient temperature TA. The maximum allowable power dissipation at an ambient temperature is PD = (TJMAX - TA) ΘJA. If this dissipation is exceeded, the die temperature will rise above 150°C and the MCP2021 will go into thermal shutdown. DS22018E-page 22 © 2009 Microchip Technology Inc.

MCP2021/2 2.5 Timing Diagrams and Specifications FIGURE 2-4: BUS TIMING DIAGRAM TXD 50% 50% LBUS .95VLBUS .50VBB .0++++++++++++++++++++++++---5V 0.0V TTRANSPDF TTRANSPDR TRECPDF TRECPDR RXD 50% 50% Internal TXD/RXD Compare Match Match Match Match Match FAULT Sampling TFAULT TFAULT Hold Hold FAULT/TXE Output Stable Stable Stable Value Value FIGURE 2-5: REGULATOR CS/LWAKE TIMING DIAGRAM CS/LWAKE T CSOR VREG VOUT TCSPD © 2009 Microchip Technology Inc. DS22018E-page 23

MCP2021/2 FIGURE 2-6: REGULATOR BUS WAKE TIMING DIAGRAM TVEVR LBUS .4VBB TBDB + TBACTVE VREG VOUT FIGURE 2-7: RESET TIMING DIAGRAM 6.0V 5.0V VBB 5.0V 4.0V 3.5V VREG TRPD TRPD RESET TRPU TRPU DS22018E-page 24 © 2009 Microchip Technology Inc.

MCP2021/2 FIGURE 2-8: CS/LWAKE TO RESET TIMING DIAGRAM CS/LWAKE TCSOR VREG VOUT TRPU TCSPD RESET FIGURE 2-9: TYPICAL IBBQ VS. TEMPERATURE 0.2 0.15 A m 0.1 q b b Vbb = 6V I Vbb = 7.3V 0.05 Vbb = 12V Vbb = 14.4V Vbb = 18V 0 -40C 25C 85C 125C Temperature (°C) © 2009 Microchip Technology Inc. DS22018E-page 25

MCP2021/2 FIGURE 2-10: TYPICAL IBBTO VS TEMPERATURE 0.18 0.16 0.14 0.12 A 0.1 m 0.08 Vbb = 6V 0.06 Vbb = 7.3V Vbb = 12V 0.04 Vbb = 14.4V 0.02 Vbb = 18V 0 -40C 25C 85C 125C Temperature (°C) FIGURE 2-11: TYPICAL IPD VS. TEMPERATURE 0.025 0.02 ) A 0.015 m ( d p 0.01 Vbb = 6V I Vbb = 7.3V 0.005 Vbb = 12V Vbb = 14.4V Vbb = 18V 0 -40C 25C 85C 125C Temperature (°C) DS22018E-page 26 © 2009 Microchip Technology Inc.

MCP2021/2 3.0 PACKAGING INFORMATION 3.1 Package Marking Information 8-Lead DFN (4x4) Example: XXXXXXX 202150 XXXXXXX E/MD^e^3 XXYYWW 0733 NNN 256 8-Lead DFN-S (6x5) Example: XXXXXXX 2021500 XXXXXXX E/MF^^e3 XXYYWW 0733 NNN 256 8-Lead PDIP (300 mil) Example: XXXXXXXX 2021500 XXXXXNNN E/P^e3^256 YYWW 0729 8-Lead SOIC (150 mil) Example: XXXXXXXX 2021500E XXXXYYWW SN^e^30729 NNN 256 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2009 Microchip Technology Inc. DS22018E-page 27

MCP2021/2 3.1 Package Marking Information (Continued) 14-Lead PDIP (300 mil) (MCP2022) Example: XXXXXXXXXXXXXX MCP2022-500 XXXXXXXXXXXXXX E/P^e^3 YYWWNNN 0729256 14-Lead SOIC (150 mil) (MCP2022) Example: XXXXXXXXXX MCP2022-500 XXXXXXXXXX E/SL^e^3 YYWWNNN 0729256 14-Lead TSSOP (MCP2022) Example XXXXXXXX 2022500E YYWW 0729 NNN 256 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. DS22018E-page 28 © 2009 Microchip Technology Inc.

MCP2021/2 8-Lead Plastic Dual Flat, No Lead Package (MD) – 4x4x0.9 mm Body [DFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D e b N N L E K E2 EXPOSED PAD 1 2 2 1 NOTE 1 NOTE 1 D2 TOP VIEW BOTTOM VIEW A3 A A1 NOTE 2 Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e 0.80 BSC Overall Height A 0.80 0.90 1.00 Standoff A1 0.00 0.02 0.05 Contact Thickness A3 0.20 REF Overall Length D 4.00 BSC Exposed Pad Width E2 0.00 2.20 2.80 Overall Width E 4.00 BSC Exposed Pad Length D2 0.00 3.00 3.60 Contact Width b 0.25 0.30 0.35 Contact Length L 0.30 0.55 0.65 Contact-to-Exposed Pad K 0.20 – – Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package may have one or more exposed tie bars at ends. 3. Package is saw singulated. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. MicrochipTechnologyDrawingC04-131C © 2009 Microchip Technology Inc. DS22018E-page 29

MCP2021/2 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:8)(cid:17)(cid:10)(cid:6)(cid:12)(cid:18)(cid:8)(cid:19)(cid:20)(cid:8)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:14)(cid:21)(cid:6)(cid:22)(cid:5)(cid:8)(cid:23)(cid:24)D(cid:25)(cid:8)(cid:26)(cid:8)(cid:27)(cid:28)(cid:27)(cid:28)(cid:29)(cid:30)(cid:31)(cid:8) (cid:8)!(cid:20)(cid:7)"(cid:8)#(cid:15)(cid:17)(cid:19)$ (cid:19)(cid:20)(cid:12)(cid:5)% (cid:30)(cid:10)(cid:9)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2) (cid:10)!(cid:31)(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)(cid:31)(cid:2)(cid:12)(cid:28)(cid:8)#(cid:28)(cid:17)(cid:14)(cid:2)$(cid:9)(cid:28)%(cid:7)(cid:15)(cid:17)!&(cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)’(cid:28)(cid:8)#(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)((cid:7)(cid:8)(cid:28)(cid:31)(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)(cid:31)(cid:14)$(cid:2)(cid:28)(cid:31)(cid:2) (cid:11)(cid:31)(cid:31)(cid:12))**%%%(cid:20) (cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10) *(cid:12)(cid:28)(cid:8)#(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) DS22018E-page 30 © 2009 Microchip Technology Inc.

MCP2021/2 8-Lead Plastic Dual Flat, No Lead Package (MF) – 6x5 mm Body [DFN-S] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging e D L b N N K E E2 EXPOSED PAD NOTE 1 NOTE 1 1 2 2 1 D2 TOP VIEW BOTTOM VIEW A A3 A1 NOTE 2 Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e 1.27 BSC Overall Height A 0.80 0.85 1.00 Standoff A1 0.00 0.01 0.05 Contact Thickness A3 0.20 REF Overall Length D 5.00 BSC Overall Width E 6.00 BSC Exposed Pad Length D2 3.90 4.00 4.10 Exposed Pad Width E2 2.20 2.30 2.40 Contact Width b 0.35 0.40 0.48 Contact Length L 0.50 0.60 0.75 Contact-to-Exposed Pad K 0.20 – – Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package may have one or more exposed tie bars at ends. 3. Package is saw singulated. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. MicrochipTechnologyDrawingC04-122B © 2009 Microchip Technology Inc. DS22018E-page 31

MCP2021/2 (cid:19)(cid:20)(cid:12)(cid:5)% (cid:30)(cid:10)(cid:9)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2) (cid:10)!(cid:31)(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)(cid:31)(cid:2)(cid:12)(cid:28)(cid:8)#(cid:28)(cid:17)(cid:14)(cid:2)$(cid:9)(cid:28)%(cid:7)(cid:15)(cid:17)!&(cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)’(cid:28)(cid:8)#(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)((cid:7)(cid:8)(cid:28)(cid:31)(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)(cid:31)(cid:14)$(cid:2)(cid:28)(cid:31)(cid:2) (cid:11)(cid:31)(cid:31)(cid:12))**%%%(cid:20) (cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10) *(cid:12)(cid:28)(cid:8)#(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) DS22018E-page 32 © 2009 Microchip Technology Inc.

MCP2021/2 8-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 2 3 D E A A2 L A1 c e eB b1 b Units INCHES Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e .100 BSC Top to Seating Plane A – – .210 Molded Package Thickness A2 .115 .130 .195 Base to Seating Plane A1 .015 – – Shoulder to Shoulder Width E .290 .310 .325 Molded Package Width E1 .240 .250 .280 Overall Length D .348 .365 .400 Tip to Seating Plane L .115 .130 .150 Lead Thickness c .008 .010 .015 Upper Lead Width b1 .040 .060 .070 Lower Lead Width b .014 .018 .022 Overall Row Spacing § eB – – .430 Notes: 1. Pin 1 visual index feature may vary, but must be located with the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. MicrochipTechnologyDrawingC04-018B © 2009 Microchip Technology Inc. DS22018E-page 33

MCP2021/2 8-Lead Plastic Small Outline (SN) – Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D e N E E1 NOTE 1 1 2 3 α b h h c A A2 φ A1 L L1 β Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e 1.27 BSC Overall Height A – – 1.75 Molded Package Thickness A2 1.25 – – Standoff § A1 0.10 – 0.25 Overall Width E 6.00 BSC Molded Package Width E1 3.90 BSC Overall Length D 4.90 BSC Chamfer (optional) h 0.25 – 0.50 Foot Length L 0.40 – 1.27 Footprint L1 1.04 REF Foot Angle φ 0° – 8° Lead Thickness c 0.17 – 0.25 Lead Width b 0.31 – 0.51 Mold Draft Angle Top α 5° – 15° Mold Draft Angle Bottom β 5° – 15° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. MicrochipTechnologyDrawingC04-057B DS22018E-page 34 © 2009 Microchip Technology Inc.

MCP2021/2 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)& (cid:6)(cid:10)(cid:10)(cid:8)’(cid:16)(cid:12)(cid:10)(cid:13)((cid:5)(cid:8)(cid:23)&(cid:19)(cid:25)(cid:8)(cid:26)(cid:8)(cid:19)(cid:6)))(cid:20)*(cid:18)(cid:8)+(cid:30)(cid:31)(cid:29)(cid:8) (cid:8)!(cid:20)(cid:7)"(cid:8)#&’,-$ (cid:19)(cid:20)(cid:12)(cid:5)% (cid:30)(cid:10)(cid:9)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2) (cid:10)!(cid:31)(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)(cid:31)(cid:2)(cid:12)(cid:28)(cid:8)#(cid:28)(cid:17)(cid:14)(cid:2)$(cid:9)(cid:28)%(cid:7)(cid:15)(cid:17)!&(cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)’(cid:28)(cid:8)#(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)((cid:7)(cid:8)(cid:28)(cid:31)(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)(cid:31)(cid:14)$(cid:2)(cid:28)(cid:31)(cid:2) (cid:11)(cid:31)(cid:31)(cid:12))**%%%(cid:20) (cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10) *(cid:12)(cid:28)(cid:8)#(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) © 2009 Microchip Technology Inc. DS22018E-page 35

MCP2021/2 14-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 2 3 D E A A2 L c A1 b1 b e eB Units INCHES Dimension Limits MIN NOM MAX Number of Pins N 14 Pitch e .100 BSC Top to Seating Plane A – – .210 Molded Package Thickness A2 .115 .130 .195 Base to Seating Plane A1 .015 – – Shoulder to Shoulder Width E .290 .310 .325 Molded Package Width E1 .240 .250 .280 Overall Length D .735 .750 .775 Tip to Seating Plane L .115 .130 .150 Lead Thickness c .008 .010 .015 Upper Lead Width b1 .045 .060 .070 Lower Lead Width b .014 .018 .022 Overall Row Spacing § eB – – .430 Notes: 1. Pin 1 visual index feature may vary, but must be located with the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. MicrochipTechnologyDrawingC04-005B DS22018E-page 36 © 2009 Microchip Technology Inc.

MCP2021/2 14-Lead Plastic Small Outline (SL) – Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 3 e h b α h φ c A A2 A1 L β L1 Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 14 Pitch e 1.27 BSC Overall Height A – – 1.75 Molded Package Thickness A2 1.25 – – Standoff § A1 0.10 – 0.25 Overall Width E 6.00 BSC Molded Package Width E1 3.90 BSC Overall Length D 8.65 BSC Chamfer (optional) h 0.25 – 0.50 Foot Length L 0.40 – 1.27 Footprint L1 1.04 REF Foot Angle φ 0° – 8° Lead Thickness c 0.17 – 0.25 Lead Width b 0.31 – 0.51 Mold Draft Angle Top α 5° – 15° Mold Draft Angle Bottom β 5° – 15° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. MicrochipTechnologyDrawingC04-065B © 2009 Microchip Technology Inc. DS22018E-page 37

MCP2021/2 (cid:19)(cid:20)(cid:12)(cid:5)% (cid:30)(cid:10)(cid:9)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2) (cid:10)!(cid:31)(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)(cid:31)(cid:2)(cid:12)(cid:28)(cid:8)#(cid:28)(cid:17)(cid:14)(cid:2)$(cid:9)(cid:28)%(cid:7)(cid:15)(cid:17)!&(cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)’(cid:28)(cid:8)#(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)((cid:7)(cid:8)(cid:28)(cid:31)(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)(cid:31)(cid:14)$(cid:2)(cid:28)(cid:31)(cid:2) (cid:11)(cid:31)(cid:31)(cid:12))**%%%(cid:20) (cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10) *(cid:12)(cid:28)(cid:8)#(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) DS22018E-page 38 © 2009 Microchip Technology Inc.

MCP2021/2 14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 e b c φ A A2 A1 L1 L Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 14 Pitch e 0.65 BSC Overall Height A – – 1.20 Molded Package Thickness A2 0.80 1.00 1.05 Standoff A1 0.05 – 0.15 Overall Width E 6.40 BSC Molded Package Width E1 4.30 4.40 4.50 Molded Package Length D 4.90 5.00 5.10 Foot Length L 0.45 0.60 0.75 Footprint L1 1.00 REF Foot Angle φ 0° – 8° Lead Thickness c 0.09 – 0.20 Lead Width b 0.19 – 0.30 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. MicrochipTechnologyDrawingC04-087B © 2009 Microchip Technology Inc. DS22018E-page 39

MCP2021/2 NOTES: DS22018E-page 40 © 2009 Microchip Technology Inc.

MCP2021/2 APPENDIX A: REVISION HISTORY Revision B (August 2007) The following is the list of modifications: Revision E (February 2009) 1. Modified Block Diagram on page 2. The following is the list of modifications. 2. Section1.3.5 “Transmitter OFF Mode”: 1. Added Example1-2 and Example1-3. Deleted text in 1st paragraph. 2. Updated Section1.5.9 “RESET”. 3. Example1-1: Removed +5V notation. 3. Updated Section1.7 “ICSP™ Consider- 4. Section1.5 “Pin Descriptions”: Removed 10- ations”. pin DFN, MSOP column from table. 4. Updated Section2.1 “Absolute Maximum 5. Section1.5.8 “Fault/TXE”: Deleted text from Ratings†”. 2nd paragraph. 5. Updated Section2.2 “DC Specifications” and 6. Section3.0 “Packaging Information”: Added Section2.3 “AC Specification”. 8-lead 4x4 and 6x5 DFN and 14-lead TSSOP packages. Updated package outline drawings 6. Added FIGURE 2-3: “ESR Curves For Load and added drawings for 8-lead DFN and 14-lead Capacitor Selection”. TSSOP drawings. 7. Updated the Product Identification System section. Revision A (November 2005) Revision D (July 2008) • Original Release of this Document. The following is the list of modifications. 1. Updated ESD specs under ‘Absolute DC’. 2. Updated notes in Example 1-1. 3. Updated Package Outline Drawings. Revision C (April 2008) The following is the list of modifications. 1. Added LIN2.1 and J2602 compliance statement to Features section. 2. Added recommended RC network for CS/ LWAKE in Example 1-1. 3. Updated 2.1 Absolute Maximum Ratings to reflect current test results. 4. Updated 2.2 DC Specifications and 2.3 AC Specifications to reflect current production device. 5. Added 8-Lead SOIC Landing Pattern Outline drawing. © 2009 Microchip Technology Inc. DS22018E-page 41

MCP2021/2 NOTES: DS22018E-page 42 © 2009 Microchip Technology Inc.

MCP2021/2 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. –X /XX Examples: a) MCP2021-330E/SN: 3.3V, 8L-SOIC pkg. Device Temperature Package b) MCP2021-330E/P: 3.3V, 8L-PDIP pkg. Range c) MCP2021-500E/MF: 5.0V, 8L-DFN-S pkg. d) MCP2021-500E/SN: 5.0V, 8L-SOIC pkg. Device: MCP2021: LIN Transceiver with Voltage Regulator e) MCP2021-500E/MD: 5.0V, 8L-DFN pkg. MCP2021T: LIN Transceiver with Voltage Regulator f) MCP2021-330E/P: 5.0V, 8L-PDIP pkg. (Tape and Reel) (SOIC only) g) MCP2021T-330E/SN: Tape and Reel, MCP2022: LIN Transceiver with Voltage Regulator 3.3V, 8L-SOIC pkg. MCP2022T: LIN Transceiver with Voltage Regulator (Tape and Reel) (SOIC only) h) MCP2021T-500E/MD: Tape and Reel, 5.0V, 8L-DFN pkg. i) MCP2021T-500E/SN: Tape and Reel, Temperature Range: E = -40°C to +125°C 5.0V, 8L-SOIC pkg. Package: MD = Plastic Micro Small Outline (4x4), 8-lead a) MCP2022-330E/SL: 3.3V, 14L-SOIC pkg. MF = Plastic Micro Small Outline (6x5), 8-lead b) MCP2022-330E/P: 3.3V, 14L-PDIP pkg. P = Plastic DIP (300 mil Body), 8-lead, 14-lead c) MCP2022-500E/SL: 5.0V, 14L-SOIC pkg. SN = Plastic SOIC, (150 mil Body), 8-lead SL = Plastic SOIC, (150 mil Body), 14-lead d) MCP2022-500E/P: 5.0V, 14L-PDIP pkg. ST = Plastic Thin Shrink Small Outline, 14-lead e) MCP2022T-330E/SL: Tape and Reel, 3.3V, 14L-SOIC pkg. f) MCP2022T-500E/SL: Tape and Reel, 5.0V, 14L-SOIC pkg. g) MCP2022T-500E/ST: Tape and Reel, 5.0V, 14L-TSSOP pkg. © 2009 Microchip Technology Inc. DS22018E-page 43

MCP2021/2 NOTES: DS22018E-page 44 © 2009 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, Accuron, and may be superseded by updates. It is your responsibility to dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, ensure that your application meets with your specifications. PICSTART, rfPIC, SmartShunt and UNI/O are registered MICROCHIP MAKES NO REPRESENTATIONS OR trademarks of Microchip Technology Incorporated in the WARRANTIES OF ANY KIND WHETHER EXPRESS OR U.S.A. and other countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Linear Active Thermistor, MXDEV, MXLAB, INCLUDING BUT NOT LIMITED TO ITS CONDITION, SEEVAL, SmartSensor and The Embedded Control Solutions QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, CodeGuard, devices in life support and/or safety applications is entirely at dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, the buyer’s risk, and the buyer agrees to defend, indemnify and ECONOMONITOR, FanSense, In-Circuit Serial hold harmless Microchip from any and all damages, claims, Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB suits, or expenses resulting from such use. No licenses are Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, conveyed, implicitly or otherwise, under any Microchip PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, intellectual property rights. PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2009 Microchip Technology Inc. DS22018E-page 45

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: MCP2021-330E/MD MCP2021-330E/P MCP2021-330E/SN MCP2021-500E/MD MCP2021-500E/P MCP2021- 500E/SN MCP2021T-330E/MD MCP2021T-330E/SN MCP2021T-500E/MD MCP2021T-500E/SN MCP2022-330E/P MCP2022-330E/SL MCP2022-330E/ST MCP2022-500E/P MCP2022-500E/SL MCP2022-500E/ST MCP2022T- 330E/SL MCP2022T-330E/ST MCP2022T-500E/SL MCP2022T-500E/ST MCP2021P-330E/MD MCP2021P- 330E/SN MCP2021P-500E/MD MCP2021P-500E/SN MCP2021PT-330E/MD MCP2021PT-330E/SN MCP2021PT- 500E/MD MCP2021PT-500E/SN MCP2022P-330E/SL MCP2022P-330E/ST MCP2022P-500E/SL MCP2022P- 500E/ST MCP2022PT-330E/SL MCP2022PT-330E/ST MCP2022PT-500E/SL MCP2022PT-500E/ST