Not Recommended for New Designs Please use ATA663211 or MCP2003B MCP2003/4/3A/4A LIN J2602 Transceiver Features Description • The MCP2003/2003A and MCP2004/2004A are This device provides a bidirectional, half-duplex commu- Compliant with Local Interconnect Network (LIN) nication, physical interface to automotive and industrial Bus Specifications 1.3, 2.0 and 2.1, and are LIN systems to meet the LIN Bus Specification Compliant to SAE J2602 Revision2.1 and SAE J2602. The device is short-circuit • Supports Baud Rates up to 20Kbaudwith and overtemperature protected by internal circuitry. The LIN Bus Compatible Output Driver device has been specifically designed to operate in the automotive operating environment and will survive all • 43V Load Dump Protected specified transient conditions, while meeting all of the • Very Low/High Electromagnetic Immunity (EMI) stringent quiescent current requirements. meets Stringent Original Equipment Manufacturers (OEM) Requirements MCP200X family members: • Very High Electrostatic Discharge (ESD) • 8-pin PDIP, DFN and SOIC packages: Immunity: - MCP2003: LIN bus compatible driver with - >20kV on V (IEC 61000-4-2) WAKE pins, wake-up on falling edge of L BB BUS - >14kV on L (IEC 61000-4-2) - MCP2003A: LIN bus compatible driver with BUS • Very High Immunity to RF Disturbances meets WAKE pins, wake-up on rising edge of LBUS Stringent OEM Requirements - MCP2004: LIN bus compatible driver with • Wide Supply Voltage, 6.0V-27.0V Continuous FAULT/TXE pins, wake-up on falling edge of L • Extended Temperature Range: -40°C to +125°C BUS • Interface to PIC® MCU EUSART and Standard - MCP2004A: LIN bus compatible driver with FAULT/T pins, wake-up on rising edge of USARTs XE L • LIN Bus Pin: BUS - Internal pull-up resistor and diode Package Types - Protected against battery shorts - Protected against loss of ground MCP2003/2003A MCP2004/2004A - High-current drive PDIP, SOIC PDIP, SOIC • Automatic Thermal Shutdown RXD 1 8 VREN RXD 1 8 VREN • Low-Power mode: CS 2 7 VBB CS/WAKE 2 7 VBB - Receiver monitoring bus and transmitter off (5µA) WAKE 3 6 LBUS FAULT/TXE 3 6 LBUS TXD 4 5 VSS TXD 4 5 VSS MCP2003/2003A MCP2004/2004A 4x4DFN* 4x4DFN* RXD 1 8 VREN RXD 1 8 VREN CS 2 EP 7 VBB CS/WAKE 2 EP 7 VBB WAKE 3 9 6 LBUS FAULT/TXE 3 9 6 LBUS TXD 4 5 VSS TXD 4 5 VSS * Includes Exposed Thermal Pad (EP); see Table1-2.  2010-2016 Microchip Technology Inc. DS20002230G-page 1

MCP2003/4/3A/4A MCP2003/2003A Block Diagram V V REN BB Ratiometric Reference 4.3V Wake-up Logic and WAKE Power Control – R XD + CS ~30k TXD OC LBUS V SS Thermal Short-Circuit Protection Protection MCP2004/2004A Block Diagram V V REN BB Ratiometric Reference 4.3V 4.3V Wake-up Logic and Power Control – R XD + CS/WAKE ~30k TXD OC LBUS FAULT/TXE VSS Thermal Short-Circuit Protection Protection DS20002230G-page 2  2010-2016 Microchip Technology Inc.

MCP2003/4/3A/4A 1.0 DEVICE OVERVIEW 1.2.2 GROUND LOSS PROTECTION The LIN Bus Specification states that the LIN pin must The MCP2003/4/3A/4A devices provide a physical transition to the Recessive state when the ground is interface between a microcontroller and a LIN bus. disconnected. Therefore, a loss of ground effectively These devices will translate the CMOS/TTL logic levels forces the LIN line to a high-impedance level. to the LIN logic level and vice versa. It is intended for automotive and industrial applications with serial bus 1.2.3 THERMAL PROTECTION speeds up to 20Kbaud. The thermal protection circuit monitors the die LIN Bus Specification Revision 2.1 requires that the temperature and is able to shut down the LIN transceiver of all nodes in the system is connected via transmitter. the LIN pin, referenced to ground, and with a maximum external termination resistance load of 510 from LIN There are two causes for a thermal overload. A thermal bus to battery supply. The 510 corresponds to shutdown can be triggered by either, or both, of the 1master and 15slave nodes. following thermal overload conditions: The V pin can be used to drive the logic input of an • LIN bus output overload REN external voltage regulator. This pin is high in all modes • Increase in die temperature due to increase in except for Power-Down mode. environment temperature Driving the T pin and checking the R pin makes it XD XD 1.1 External Protection possible to determine whether there is a bus contention (R = low, T = high) or a thermal overload condition XD XD 1.1.1 REVERSE BATTERY PROTECTION (R = high, T = low). After a thermal overload event, XD XD An external reverse battery blocking diode should be the device will automatically recover once the die used to provide polarity protection (see Example1-1). temperature has fallen below the recovery temperature threshold (see Figure1-1). 1.1.2 TRANSIENT VOLTAGE PROTECTION (LOAD DUMP) FIGURE 1-1: THERMAL SHUTDOWN STATE DIAGRAM An external 43V Transient Suppressor (TVS) diode, between V and ground with a 50 Transient BB Protection Resistor (RTP) in series with the battery Shorted LIN Bus to VBB supply and the V pin, serve to protect the device from BB power transients (see Example1-1) and ESD events. While this protection is optional, it is considered good Operation Transmitter engineering practice. Mode Shutdown 1.2 Internal Protection 1.2.1 ESD PROTECTION Temp < ShutdownTEMP For component-level ESD ratings, please refer to the maximum operation specifications.  2010-2016 Microchip Technology Inc. DS20002230G-page 3

MCP2003/4/3A/4A 1.3 Modes of Operation Upon V supply pin power-on, the device will remain BB in Ready mode as long as CS is low. When CS For an overview of all operational modes, refer to transitions high, the device will either enter Operation Table1-1. mode, if the T pin is held high, or the device will enter XD Transmitter Off mode, if the T pin is held low. 1.3.1 POWER-DOWN MODE XD In Power-Down mode, everything is off except the 1.3.3 OPERATION MODE wake-up section. This is the lowest power mode. The In this mode, all internal modules are operational. receiver is off, thus its output is open-drain. The device will go into Power-Down mode on the falling On CS going to a high level or a falling edge on WAKE edge of CS. For the MCP2003/4 device, a specific (MCP2003/MCP2003A only), the device will enter process should be followed to put all nodes into Power- Ready mode as soon as the internal voltage stabilizes. Down mode. Refer to Section1.6 “MCP2003/4 and Refer to Section2.4 “AC Specifications” for further MCP2003A/4A Difference Details” and Figure1-6. information. In addition, LIN bus activity will change the The device will enter Transmitter Off mode in the event device from Power-Down mode to Ready mode; of a Fault condition, such as thermal overload, bus MCP2003/4 wakes up on a falling edge on LBUS, contention and TXD timer expiration. followed by a low level lasting at least 20 µs. The MCP2004/2004A device can also enter Transmitter MCP2003A/4A wakes up on a rising edge on L , BUS Off mode if the FAULT/T pin is pulled low. The V to followed by a high level lasting 70µs, typically. See XE BB L pull-up resistor is connected only in Operation Figures1-2 to1-5 about remote wake-up. If CS is held BUS mode. high as the device transitions from Power-Down to Ready mode, the device will transition to either Opera- 1.3.4 TRANSMITTER OFF MODE tion or Transmitter Off mode, depending on the T XD input, as soon as internal voltages stabilize. Transmitter Off mode is reached whenever the transmitter is disabled, either due to a Fault condition or 1.3.2 READY MODE pulling the FAULT/T pin low on the MCP2004/2004A. XE The Fault conditions include: thermal overload, bus Upon entering Ready mode, V is enabled and the REN contention, R monitoring or T timer expiration. receiver detect circuit is powered up. The transmitter XD XD remains disabled and the device is ready to receive The device will go into Power-Down mode on the falling data but not to transmit. edge of CS or return to Operation mode if all Faults are resolved and the FAULT/T pin on the MCP2004/2004A XE is high. FIGURE 1-2: OPERATIONAL MODES STATE DIAGRAM – MCP2003 Ready POR V > 5.5V V ON V OFF BAT RRXEN ON REN RX OFF TX OFF TX OFF CS = 1 and T = 1 XD CS = 1 and T = 0 XD TOFF CS = 1 and TXD = 1 and No Fault Operation Falling Edge on LIN Mode Mode or CS = 1 V ON V ON REN REN or Falling Edge on WAKE Pin RX ON Fault (thermal or timer) RX ON TX OFF TX ON CS = 0 CS = 0 POWER- DOWN V OFF REN RX OFF TX OFF DS20002230G-page 4  2010-2016 Microchip Technology Inc.

MCP2003/4/3A/4A FIGURE 1-3: OPERATIONAL MODES STATE DIAGRAM – MCP2003A Ready VPO ORFF VBAT > 5.5V RVXRE NO OFNF REN RX OFF TX OFF TX OFF CS = 1 and T = 1 XD CS = 1 and T = 0 XD TOFF CS = 1 and TXD = 1 and No Fault Operation Rising Edge on LIN Mode Mode or CS = 1 V ON V ON REN REN or Falling Edge on WAKE Pin RX ON Fault (thermal or timer) RX ON TX OFF TX ON CS = 0 CS = 0 POWER- DOWN V OFF REN RX OFF TX OFF FIGURE 1-4: OPERATIONAL MODES STATE DIAGRAM – MCP2004 Ready VPO ORFF VBAT > 5.5V VRRXEN O ONN REN RX OFF TX OFF TX OFF CS = 1 and T = 1 and T = 1 XD XE CS = 1 and (T = 0 or T = 0) XE XD CS = 1 and T = 1 and T = 1 XD XE T and No Fault Operation OFF Falling Edge on LIN or Mode Mode CS = 1 V ON Fault (thermal or time-out) or V ON RRXEN ON FAULT/T = 0 RRXEN ON XE TX OFF TX ON CS = 0 CS = 0 POWER- DOWN V OFF REN RX OFF TX OFF  2010-2016 Microchip Technology Inc. DS20002230G-page 5

MCP2003/4/3A/4A FIGURE 1-5: OPERATIONAL MODES STATE DIAGRAM – MCP2004A Ready VPO ORFF VBAT > 5.5V VRRXEN O ONN REN RX OFF TX OFF TX OFF CS = 1 and T = 1 and T = 1 XD XE CS = 1 and (T = 0 or T = 0) XE XD CS = 1 and T = 1 and TOFF TXE = 1 and NXoD Fault Operation Rising Edge on LIN Mode Mode or CS = 1 V ON Fault (thermal or time-out) or V ON RRXEN ON FAULT/T = 0 RRXEN ON XE TX OFF TX ON CS = 0 CS = 0 POWER- DOWN V OFF REN RX OFF TX OFF TABLE 1-1: OVERVIEW OF OPERATIONAL MODES State Transmitter Receiver V Operation Comments REN POR OFF OFF OFF Check CS; if low, then proceed to Ready mode. V > V and BB BB(MIN) If high, transitions to either T or Operation internal supply is OFF mode, depending on T (MCP2003/A), or T stable XD XD and FAULT/T (MCP2004/A). XE Ready OFF ON ON If CS is a high level, then proceed to Operation Bus Off state or T mode. OFF Operation ON ON ON If CS is a low level, then proceed to Normal Operation Power-Down mode. If FAULT/T is a low level, mode XE then proceed to Transmitter Off mode. Power-Down OFF Activity OFF On CS high level, proceed to Ready mode; then Low-Power mode Detect proceed to either Operation mode or TOFF mode. MCP2003/2003A: Falling edge on WAKE will put the device into Ready mode. MCP2003/MCP2004: Falling edge on LIN bus will put the device into Ready mode. MCP2003A/MCP2004A: Rising edge on LIN bus will put the device into Ready mode. Transmitter Off OFF ON ON If CS is a low level, then proceed to FAULT/T is only XE Power-Down mode. If FAULT/T and T are available on XE XD high, then proceed to Operation mode. MCP2004/2004A DS20002230G-page 6  2010-2016 Microchip Technology Inc.

MCP2003/4/3A/4A 1.4 Typical Applications EXAMPLE 1-1: TYPICAL MCP2003/2003A APPLICATION +12 Optional Resistor and +12 Transient Suppressor 50 Master Node Only 43V (Note 1) +12 3.9k 1.0µF VDD Voltage Reg VREN VBB 4.7k TXD TXD 1k RXD RXD LBUS LIN Bus I/O CS MMBZ27V(2) 33k 220 pF WAKE Wake-up V SS Note 1: For applications with current requirements of less than 20mA, the connection to +12V can be deleted and voltage to the regulator can be supplied directly from the V pin. REN 2: ESD protection diode. EXAMPLE 1-2: TYPICAL MCP2004/2004A APPLICATION +12 +12 Optional Resistor and Transient Suppressor 50 Wake-up (Note 1) 43V 1.0µF Master Node Only +12 220k VDD Voltage Reg VREN VBB 4.7k TXD TXD 1k RXD RXD LBUS LIN Bus I/O CS/WAKE MMBZ27V(2) 220 pF I/O FAULT/TXE V 100nF SS Note 1: For applications with current requirements of less than 20mA, the connection to +12V can be deleted and voltage to the regulator can be supplied directly from the V pin. REN 2: ESD protection diode.  2010-2016 Microchip Technology Inc. DS20002230G-page 7

MCP2003/4/3A/4A EXAMPLE 1-3: TYPICAL LIN NETWORK CONFIGURATION 40m + Return LIN Bus 1k V BB LIN Bus Slave 1 LIN Bus LIN Bus MCP2000X (MCU) MCP200X MCP200X LIN Bus Slave 2 Slave n < 23 MCP200X (MCU) (MCU) Master (MCU) DS20002230G-page 8  2010-2016 Microchip Technology Inc.

MCP2003/4/3A/4A 1.5 Pin Descriptions TABLE 1-2: PINOUT DESCRIPTIONS 8-Lead MCP2003/2003A MCP2004/2004A 4x4 Pin Name PDIP, DFN SOIC Normal Operation Normal Operation R 1 1 Receive Data Output (OD), Receive Data Output (OD), XD HV tolerant HV tolerant CS 2 2 Chip Select (TTL), HV tolerant Chip Select/Local WAKE (TTL), HV tolerant WAKE 3 3 Wake-up, HV tolerant Fault Detect Output (OD), (MCP2003/2003A only) Transmitter Enable (TTL), HV tolerant FAULT/T XE (MCP2004/2004A only) T 4 4 Transmit Data Input (TTL), Transmit Data Input (TTL), XD HV tolerant HV tolerant V 5 5 Ground Ground SS L 6 6 LIN Bus (bidirectional) LIN Bus (bidirectional) BUS V 7 7 Battery Positive Battery Positive BB V 8 8 Voltage Regulator Enable Output Voltage Regulator Enable Output REN EP — 9 Exposed Thermal Pad; do not Exposed Thermal Pad; do not electrically connect or connect electrically connect or connect to V to V SS SS Legend: TTL=TTL Input Buffer; OD=Open-Drain Output 1.5.1 RECEIVE DATA OUTPUT (RXD) If CS = 1 when the VBB supply is turned on, the device The Receive Data Output pin is an Open-Drain (OD) will proceed to Operation mode or TOFF mode (refer to output and follows the state of the LIN pin, except in Figures1-2 to1-5) as soon as internal voltages Power-Down mode. stabilize. 1.5.1.1 R Monitoring This pin may also be used as a local wake-up input XD (refer to Example1-1). In this implementation, the The R pin is internally monitored. It has to be at a XD microcontroller I/O controlling the CS should be con- high level (> 2.5V typical) while L is recessive. BUS verted to a high-impedance input, allowing the internal Otherwise, an internal Fault will be created and the pull-down resistor to keep CS low. An external switch, device will transition to Transmitter Off mode. On the or other source, can then wake-up both the transceiver MCP2004/2004A, the FAULT/T pin will be driven low XE and the microcontroller (if powered). Refer to to indicate the Transmitter Off state. Section1.3 “Modes of Operation”, for detailed 1.5.2 CHIP SELECT (CS) operation of CS. This is the Chip Select input pin. An internal pull-down Note: It is not recommended to tie CS high as resistor will keep the CS pin low. This is done to ensure this can result in the device entering that no disruptive data will be present on the bus while Operation mode before the microcontrol- the microcontroller is executing a Power-on Reset and ler is initialized and may result in an I/O initialization sequence. The pin must detect a high unintentional LIN traffic. level to activate the transmitter. An internal low-pass filter, with a typical time constant of 10 µs, prevents 1.5.3 WAKE-UP INPUT (WAKE) unwanted wake-up (or transition to Power-Down mode) on glitches. This pin is only available on the MCP2003/2003A. If CS = 0 when the VBB supply is turned on, the device The WAKE pin has an internal 800 kΩ pull-up to VBB. goes to Ready mode as soon as internal voltages sta- A falling edge on the WAKE pin causes the device to bilize and stays there as long as the CS pin is held low wake from Power-Down mode. Upon waking, the (0). In Ready mode, the receiver is on and the LIN MCP2003/3A will enter Ready mode. transmitter driver is off.  2010-2016 Microchip Technology Inc. DS20002230G-page 9

MCP2003/4/3A/4A 1.5.4 FAULT/T Fault condition or by an external drive. While the trans- XE mitter is disabled, the internal 30 k pull-up resistor on This pin is only available on the MCP2004/2004A. This the L pin is also disconnected to reduce current. pin is bidirectional and allows disabling of the transmitter, BUS as well as Fault reporting related to disabling the Note: The FAULT/TXE pin is true (‘0’) whenever transmitter. This pin is an open-drain output with states the internal circuits have detected a short as defined in Table1-3. The transmitter is disabled or thermal excursion and have disabled whenever this pin is low (‘0’), either from an internal the L output driver. BUS TABLE 1-3: FAULT/T TRUTH TABLE XE FAULT/T XE R LIN Thermal T In XD BUS Definition XD Out I/O Override External Driven Input Output L H V OFF H L FAULT, T driven low, L shorted to V BB XD BUS BB (Note1) H H V OFF H H OK BB L L GND OFF H H OK H L GND OFF H H OK, data is being received from L BUS x x V ON H L FAULT, transceiver in thermal shutdown BB x x V x L x NO FAULT, the CPU is commanding the BB transceiver to turn off the transmitter driver Legend: x = don’t care. Note 1: The FAULT/T is valid after approximately 25 µs after the T falling edge. This is to eliminate false Fault XE XD reporting during bus propagation delays. 1.5.5 TRANSMIT DATA INPUT (T ) 1.5.7.1 Bus Dominant Timer XD The Transmit Data input pin has an internal pull-up. The Bus Dominant Timer is an internal timer that The LIN pin is low (dominant) when T is low and high deactivates the L transmitter after approximately XD BUS (recessive) when T is high. 25ms of Dominant state on the L pin. The timer is XD BUS reset on any recessive L state. For extra bus security, TXD is internally forced to ‘1’ BUS whenever the transmitter is disabled, regardless of the The LIN bus transmitter will be reenabled after a external T voltage. Recessive state on the L pin as long as CS is high. XD BUS Disabling can be caused by the LIN bus being 1.5.5.1 TXD Dominant Time-out externally held dominant or by TXD being driven low. If T is driven low for longer than approximately Additionally, on the MCP2004/2004A, the FAULT pin XD 25ms, the L pin is switched to Recessive mode and will be driven low to indicate the Transmitter Off state. BUS the part enters T mode. This is to prevent the LIN OFF 1.5.8 BATTERY (V ) node from permanently driving the LIN bus dominant. BB The transmitter is reenabled on the T rising edge. This is the Battery Positive Supply Voltage pin. XD 1.5.6 GROUND (V ) 1.5.9 VOLTAGE REGULATOR ENABLE SS OUTPUT (V ) This is the Ground pin. REN This is the External Voltage Regulator Enable pin. The 1.5.7 LIN BUS (L ) BUS open source output is pulled high to VBB in all modes, The bidirectional LIN Bus pin (L ) is controlled by the except Power-Down. BUS T input. L has a current-limited open-collector XD BUS 1.5.10 EXPOSED THERMAL PAD (EP) output. To reduce EMI, the edges, during the signal changes, are slope controlled, and include corner Do not electrically connect or connect to V . SS rounding control for both falling and rising edges. The internal LIN receiver observes the activities on the LIN bus and matches the output signal, R , to follow XD the state of the L pin. BUS DS20002230G-page 10  2010-2016 Microchip Technology Inc.

MCP2003/4/3A/4A 1.6 MCP2003/4 and MCP2003A/4A If the MCP2003/4 is placed into Operational mode, the Difference Details VBB to LBUS pull-up resistor is automatically connected, which will raise the LIN bus to a Recessive level; then The differences between the MCP2003/4 and the putting the device into Power-Down mode may cause MCP2003A/4A devices are isolated to the wake-up L to be floating, and thus, wake-up all bus nodes. To BUS functionality. The changes were implemented to make prevent this, the designer should ensure T (MCP2003) XD the device more robust to LIN bus conditions outside of or T (MCP2004) is held low until valid bus activity is XE the normal operating conditions. The MCP2003/4 will verified (see Figure1-6). This will ensure the transceiver wake-up from Power-Down mode during any LIN falling transitions from Ready mode to Transmitter Off mode edge held low longer than 20µs. until bus activity can be verified. In the case where a LIN system is designed to minimize In the case of valid bus activity, the transceiver can shift to standby current by disconnecting all bus pull-up resis- Operation mode; while if there is no bus activity, the tors (including the external master pull-up resistor to device can again be placed into Power-Down mode. The VBB), the original MCP2003/4 could wake-up if the float- design practices needed to accomplish this are fully ing bus drifted to a valid low level. The MCP2003A/4A detailed in Tech Brief TB3067, “MCP2003 Power-Down revisions were modified to require a rising edge after a Mode and Wake-up Handling in the Case of LIN Bus valid low level. This will prevent an undesired system Loss” (DS93067). wake-up in this scenario, while maintaining functional The revised MCP2003A/4A devices now eliminate the capability with the original version. need for firmware to prevent system wide wake-up. It should be noted that the original MCP2003/4 meets The revised devices now require a longer valid bus low all LIN transceiver specification requirements and (see updated t value in Section2.3 “DC Specifi- BDB modules can be designed to pass all LIN system cations” and Figure2-7), which enables a rising edge requirements. However, when all bus pull-up resistors detect circuit. The device will now only wake-up after a are disconnected, the MCP2003/4 requires the module rising edge, following a low longer than t . While BDB designer to write firmware to monitor the LIN bus, after the module designer can still hold T (MCP2003) or XD any wake-up event, to prevent the transceiver from T (MCP2004) low during wake-up to enter Transmitter XE automatically transitioning from Ready mode to Off mode from Ready mode, it is not required to prevent Operational mode. an advertent system wake-up. In addition to the longer t value, the time from wake- BDB up detect to V enable is shortened, as documented REN in Section2.3 “DC Specifications”. FIGURE 1-6: MCP2003/2004 SWITCHING TIMING DIAGRAM FOR THE FORCED POWER-DOWN MODE SEQUENCE tTx2CS (cid:149)(cid:3)(cid:20)(cid:19)(cid:19)(cid:3)(cid:81)(cid:86) tCSactive (cid:149)(cid:3)(cid:20)(cid:19)(cid:19) (cid:3)(cid:151)(cid:86) CS T State Depending XD on how the Slave V Microcontroller is T to ‘0’ REN Powered FXoDrced Externally T XD L BUS LIN Bus Disconnected Power-Down Ready Transmitter Off Power-Down State Mode after Master Mode Mode Mode SLEEP Instruction  2010-2016 Microchip Technology Inc. DS20002230G-page 11

MCP2003/4/3A/4A 2.0 ELECTRICAL CHARACTERISTICS 2.1 Absolute Maximum Ratings† V DC Voltage on R , T , FAULT/T , CS..............................................................................................-0.3 to +43V IN XD XD XE V DC Voltage on WAKE and V .............................................................................................................-0.3 to +V IN REN BB V Battery Voltage, Continuous, Non-Operating (Note1)...........................................................................-0.3 to +40V BB V Battery Voltage, Non-Operating (LIN bus recessive) (Note2)...............................................................-0.3 to +43V BB V Battery Voltage, Transient ISO 7637 Test 1.....................................................................................................-200V BB V Battery Voltage, Transient ISO 7637 Test 2a...................................................................................................+150V BB V Battery Voltage, Transient ISO 7637 Test 3a...................................................................................................-300V BB V Battery Voltage, Transient ISO 7637 Test 3b...................................................................................................+200V BB V Bus Voltage, Continuous.....................................................................................................................-18 to +40V LBUS V Bus Voltage, Transient (Note3)..........................................................................................................-27 to +43V LBUS I Bus Short-Circuit Current Limit....................................................................................................................200mA LBUS ESD Protection on LIN, V , WAKE (IEC 61000-4-2) (Note4)..............................................................................±8 KV BB ESD Protection on LIN, V (Human Body Model) (Note5)..................................................................................±8 KV BB ESD Protection on All Other Pins (Human Body Model) (Note5)..........................................................................±4KV ESD Protection on All Pins (Charge Device Model) (Note6).................................................................................±2 KV ESD Protection on All Pins (Machine Model) (Note7)............................................................................................±200V Maximum Junction Temperature.............................................................................................................................150C Storage Temperature...................................................................................................................................-65 to +150C † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device, at those or any other conditions above those indicated in the operational listings of this specification, is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Note 1: LIN 2.x compliant specification. 2: SAE J2602 compliant specification. 3: ISO 7637/1 load dump compliant (t < 500ms). 4: According to IEC 61000-4-2, 330 ohm, 150 pF and Transceiver EMC Test Specifications [2] to [4]. For WAKE pin to meet the specification, a series resistor must be in place (refer to Example1-2). 5: According to AEC-Q100-002/JESD22-A114. 6: According to AEC-Q100-011B. 7: According to AEC-Q100-003/JESD22-A115. 2.2 Nomenclature Used in This Document Some terms and names used in this data sheet deviate from those referred to in the LIN specifications. Equivalent values are shown below. LIN 2.1 Name Term Used in the Following Tables Definition V not used ECU operating voltage BAT V V Supply voltage at device pin SUP BB I I Current limit of driver BUS_LIM SC V V Recessive state BUSREC IH(LBUS) V V Dominant state BUSDOM IL(LBUS) DS20002230G-page 12  2010-2016 Microchip Technology Inc.

MCP2003/4/3A/4A 2.3 DC Specifications Electrical Characteristics: Unless otherwise indicated, all limits are specified for DC Specifications V = 6.0V to 30.0V, T = -40°C to +125°C BB A Parameter Sym. Min. Typ. Max. Units Conditions Power V Quiescent Operating I — 90 150 µA Operating mode, bus is BB BBQ Current Recessive (Note1) V Transmitter Off I — 75 120 µA Transmitter off, bus is BB BBTO Current Recessive (Note1) V Power-Down Current I — 5 15 µA BB BBPD V Current I -1 — 1 mA V =12V, GND to V , BB BBNOGND BB BB with V Floating V =0-27V SS LIN Microcontroller Interface High-Level Input Voltage V 2.0 — 30 V IH (T , FAULT/T ) XD XE Low-Level Input Voltage V -0.3 — 0.8 V IL (T , FAULT/T ) XD XE High-Level Input Current I -2.5 — — µA Input voltage=4.0V IH (T , FAULT/T ) XD XE Low-Level Input Current I -10 — — µA Input voltage=0.5V IL (T , FAULT/T ) XD XE High-Level Voltage (V ) V -0.3 — V + 0.3 V REN HVREN BB High-Level Output Current I -40 — -10 mA Output voltage=V – 0.5V HVREN BB (VREN) -125 — -35 Output voltage=VBB-2.0V High-Level Input Voltage V 2.0 — 30 V Through a current-limiting IH (CS) resistor Low-Level Input Voltage V -0.3 — 0.8 V IL (CS) High-Level Input Current I — — 10.0 µA Input voltage=4.0V IH (CS) Low-Level Input Current I — — 5.0 µA Input voltage=0.5V IL (CS) Low-Level Input Voltage V V – 4.0V — — V IL BB (WAKE) Low-Level Output Voltage V — — 0.4 V I = 2mA OL IN (R ) XD High-Level Output Current I -1 — -1 µA V = V , V = 5.5V OH LIN BB RXD (R ) XD Note 1: Internal current limited; 2.0ms maximum recovery time (R = 0, TX = 0.4 V , V = V ). LBUS REG LBUS BB 2: Node has to sustain the current that can flow under this condition; bus must be operational under this condition.  2010-2016 Microchip Technology Inc. DS20002230G-page 13

MCP2003/4/3A/4A 2.3 DC Specifications (Continued) Electrical Characteristics: Unless otherwise indicated, all limits are specified for DC Specifications V = 6.0V to 30.0V, T = -40°C to +125°C BB A Parameter Sym. Min. Typ. Max. Units Conditions Bus Interface High-Level Input Voltage V 0.6 V — — V Recessive state IH(LBUS) BB Low-Level Input Voltage V -8 — 0.4 V V Dominant state IL(LBUS) BB Input Hysteresis V — — 0.175 V V V – V HYS BB IH(LBUS) IL(LBUS) Low-Level Output Current I 40 — 200 mA Output voltage = 0.1 V , OL(LBUS) BB V = 12V BB High-Level Output Current I — — 20 µA OH(LBUS) Pull-up Current on Input I 5 — 180 µA ~30k internal pull-up PU(LBUS) @ V = 0.7 V IH(LBUS) BB Short-Circuit Current Limit I 50 — 200 mA (Note1) SC High-Level Output Voltage V 0.9 V — V V OH(LBUS) BB BB Driver Dominant Voltage V_ — — 1.2 V V = 7V, R = 500 LOSUP BB LOAD Driver Dominant Voltage V_ — — 2.0 V V = 18V, R = 500 HISUP BB LOAD Driver Dominant Voltage V_ –1k 0.6 — — V V = 7V, R = 1k LOSUP BB LOAD Driver Dominant Voltage V_ –1k 0.8 — — V V = 18V, R = 1k HISUP BB LOAD Input Leakage Current I -1 -0.4 — mA Driver off, V = 0V, BUS_PAS_DOM BUS (at the receiver during V = 12V BB Dominant bus level) Input Leakage Current I — 12 20 µA Driver off, 8V < V < 18V, BUS_PAS_REC BB (at the receiver during 8V < V < 18V, BUS Recessive bus level) V  V BUS BB Leakage Current I -10 1.0 +10 µA GND = V , BUS_NO_GND DEVICE BB (disconnected from ground) 0V < V < 18V, BUS V = 12V BB Leakage Current I — — 10 µA V = GND, BUS_NO_VBB BB (disconnected from V ) 0 < V < 18V (Note2) BB BUS Receiver Center Voltage V 0.475 V 0.5 V 0.525 V V V = (V + BUS_CNT BB BB BB BUS_CNT IL(LBUS) V /2 IH(LBUS) Slave Termination R 20 30 47 k SLAVE Capacitance of Slave C — — 50 pF SLAVE Node Note 1: Internal current limited; 2.0ms maximum recovery time (R = 0, TX = 0.4 V , V = V ). LBUS REG LBUS BB 2: Node has to sustain the current that can flow under this condition; bus must be operational under this condition. DS20002230G-page 14  2010-2016 Microchip Technology Inc.

MCP2003/4/3A/4A 2.4 AC Specifications Electrical Characteristics: Unless otherwise indicated, all limits are specified for AC Characteristics V = 6.0V to 27.0V; T = -40°C to +125°C BB A Parameter Sym. Min. Typ. Max. Units Test Conditions Bus Interface – Constant Slope Time Parameters Slope Rising and Falling Edges t 3.5 — 22.5 µs 7.3V  V  18V SLOPE BB Propagation Delay of t — — 4.0 µs t = max (t or TRANSPD TRANSPD TRANSPDR Transmitter t ) TRANSPDF Propagation Delay of Receiver t — — 6.0 µs t = max (t or t ) RECPD RECPD RECPDR RECPDF Symmetry of Propagation t -2.0 — 2.0 µs t = max (t – t ) RECSYM RECSYM RECPDF RECPDR Delay of Receiver Rising Edge R 2.4 to V , C 20pF RXD CC RXD w.r.t. Falling Edge Symmetry of Propagation t -2.0 — 2.0 µs t = max TRANSSYM TRANSSYM Delay of Transmitter Rising (t – t ) TRANSPDF TRANSPDR Edge w.r.t. Falling Edge Time to Sample FAULT/T for t — — 32.5 µs t = max XE FAULT FAULT Bus Conflict Reporting (t + + t ) TRANSPD TSLOPE RECPD Duty Cycle 1 @ 20.0kbit/sec 0.396 — — — C ; R Conditions: BUS BUS 1nF; 1k | 6.8nF; 660 | 10nF; 500, TH = 0.744 x V , REC(MAX) BB TH = 0.581 x V , DOM(MAX) BB V = 7.0V – 18V, t = 50µs, BB BIT D1 = t /2 x t ) BUS_REC(MIN) BIT Duty Cycle 2 @ 20.0kbit/sec — — 0.581 — C ; R Conditions: BUS BUS 1nF; 1k | 6.8nF; 660 | 10nF; 500, TH = 0.284 x V , REC(MAX) BB TH = 0.422 x V , DOM(MAX) BB V = 7.6V – 18V, t = 50µs, BB BIT D2 = t /2 x t ) BUS_REC(MAX) BIT Duty Cycle 3 @ 10.4kbit/sec 0.417 — — — C ; R Conditions: BUS BUS 1nF; 1k | 6.8nF; 660 | 10nF; 500, TH = 0.778 x V , REC(MAX) BB TH = 0.616 x V , DOM(MAX) BB V = 7.0V – 18V, t = 96µs, BB BIT D3 = t /2 x t ) BUS_REC(MIN) BIT Duty Cycle 4 @ 10.4kbit/sec — — 0.590 — C ; R Conditions: BUS BUS 1nF; 1k | 6.8nF; 660 | 10nF; 500, TH = 0.251 x V , REC(MAX) BB TH = 0.389 x V , DOM(MAX) BB V = 7.6V – 18V, t = 96µs, BB BIT D4 = t /2 x t BUS_REC(MAX) BIT Wake-up Timing Bus Activity Debounce Time t 5 — 20 µs MCP2003/2004 BDB 30 70 125 µs MCP2003A/2004A Bus Activity to V On t 35 — 150 µs MCP2003/2004 REN BACTVE 10 30 90 µs MCP2003A/2004A WAKE to V On t — — 150 µs REN WAKE Chip Select to V On t — — 150 µs V floating REN CSOR REN Chip Select to V Off t — — 80 µs V floating REN CSPD REN  2010-2016 Microchip Technology Inc. DS20002230G-page 15

MCP2003/4/3A/4A 2.5 Thermal Specifications(1) Parameter Symbol Typ. Max. Units Test Conditions Recovery Temperature  +140 — C RECOVERY Shutdown Temperature  +150 — C SHUTDOWN Short-Circuit Recovery Time t 1.5 5.0 ms THERM Thermal Package Resistances Thermal Resistance, 8L-DFN JA 35.7 — C/W Thermal Resistance, 8L-PDIP JA 89.3 — C/W Thermal Resistance, 8L-SOIC JA 149.5 — C/W Note 1: The maximum power dissipation is a function of T ,  and ambient temperature, T . The maximum JMAX JA A allowable power dissipation at an ambient temperature is P = (T – T ) . If this dissipation is D JMAX A JA exceeded, the die temperature will rise above +150C and the device will go into thermal shutdown. DS20002230G-page 16  2010-2016 Microchip Technology Inc.

MCP2003/4/3A/4A 2.6 Typical Performance Curves Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, V = 6.0V to 18.0V, T = -40°C to +125°C. BB A FIGURE 2-1: TYPICAL I FIGURE 2-3: TYPICAL I BBQ BBTO 0.14 0.12 0.12 0.1 A) 0.1 A)0.08 m -40C m -40C Current (000...000468 (cid:14)(cid:14)(cid:14)218525C5CC Current (00..0046 (cid:14)(cid:14)(cid:14)812525C5CC 0.02 0.02 0 0 6 7.3 12 14.4 18 6V 7.3V 12V 14.4V 18V VBB (V) VBB (V) FIGURE 2-2: TYPICAL I BBPD 0.008 0.007 0.006 A) m0.005 -40C nt (0.004 (cid:14)25C e (cid:14)85C urr0.003 (cid:14)125C C 0.002 0.001 0 6 7.3 12 14.4 18 VBB (V)  2010-2016 Microchip Technology Inc. DS20002230G-page 17

MCP2003/4/3A/4A 2.7 Timing Diagrams and Specifications FIGURE 2-4: BUS TIMING DIAGRAM TXD 50% 50% LBUS .95 VLBUS .50 V BB 0.05 V LBUS 0.0V T T TRANSPDF TRANSPDR T T RECPDF RECPDR RXD 50% 50% Internal TXD/RXD Match Match Match Match Match Compare FAULT Sampling TFAULT TFAULT Hold Hold FAULT/TXE Output Stable Value Stable Value Stable FIGURE 2-5: CS TO V TIMING DIAGRAM REN CS T CSOR V BB V REN Off T CSPD DS20002230G-page 18  2010-2016 Microchip Technology Inc.

MCP2003/4/3A/4A FIGURE 2-6: MCP2003/4 REMOTE WAKE-UP L BUS 0.4 V BB t BDB t BACTIVE V BB V REN FIGURE 2-7: MCP2003A/4A REMOTE WAKE-UP L BUS 0.4 V BB t BDB t BACT IVE V BB V REN  2010-2016 Microchip Technology Inc. DS20002230G-page 19

MCP2003/4/3A/4A 3.0 PACKAGING INFORMATION 3.1 Package Marking Information 8-Lead DFN (4x4x0.9 mm) Example: 2003 E/MD^e3^ 1642 256 8-Lead PDIP (300 mil) Example: MCP2003 E/P^e^3256 1642 8-Lead SOIC (150 mil) Example: MCP2003E SN^e^31642 NNN 256 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC® designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. DS20002230G-page 20  2010-2016 Microchip Technology Inc.

MCP2003/4/3A/4A 8-Lead Plastic Dual Flat, No Lead Package (MD) – 4x4x0.9 mm Body [DFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging MicrochipTechnologyDrawingC04-131E Sheet 1 of 2  2010-2016 Microchip Technology Inc. DS20002230G-page 21

MCP2003/4/3A/4A 8-Lead Plastic Dual Flat, No Lead Package (MD) – 4x4x0.9 mm Body [DFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging MicrochipTechnologyDrawingC04-131E Sheet 2 of 2 DS20002230G-page 22  2010-2016 Microchip Technology Inc.

MCP2003/4/3A/4A Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2010-2016 Microchip Technology Inc. DS20002230G-page 23

MCP2003/4/3A/4A 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A N B E1 NOTE 1 1 2 TOP VIEW E C A A2 PLANE L c A1 e eB 8X b1 8X b .010 C SIDE VIEW END VIEW Microchip Technology Drawing No. C04-018D Sheet 1 of 2 DS20002230G-page 24  2010-2016 Microchip Technology Inc.

MCP2003/4/3A/4A 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging ALTERNATE LEAD DESIGN (VENDOR DEPENDENT) DATUM A DATUM A b b e e 2 2 e e Units INCHES Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e .100 BSC Top to Seating Plane A - - .210 Molded Package Thickness A2 .115 .130 .195 Base to Seating Plane A1 .015 - - Shoulder to Shoulder Width E .290 .310 .325 Molded Package Width E1 .240 .250 .280 Overall Length D .348 .365 .400 Tip to Seating Plane L .115 .130 .150 Lead Thickness c .008 .010 .015 Upper Lead Width b1 .040 .060 .070 Lower Lead Width b .014 .018 .022 Overall Row Spacing § eB - - .430 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-018D Sheet 2 of 2  2010-2016 Microchip Technology Inc. DS20002230G-page 25

MCP2003/4/3A/4A Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20002230G-page 26  2010-2016 Microchip Technology Inc.

MCP2003/4/3A/4A Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2010-2016 Microchip Technology Inc. DS20002230G-page 27

MCP2003/4/3A/4A (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:10)(cid:8)(cid:17)(cid:18)(cid:12)(cid:10)(cid:13)(cid:19)(cid:5)(cid:8)(cid:20)(cid:15)(cid:21)(cid:22)(cid:8)(cid:23)(cid:8)(cid:21)(cid:6)(cid:24)(cid:24)(cid:25)(cid:26)(cid:27)(cid:8)(cid:28)(cid:29)(cid:30)(cid:31)(cid:8)(cid:16)(cid:16)(cid:8) (cid:25)(cid:7)!(cid:8)"(cid:15)(cid:17)#$% (cid:21)(cid:25)(cid:12)(cid:5)& (cid:30)(cid:10)(cid:9)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2)!(cid:10)"(cid:31)(cid:2)(cid:8)#(cid:9)(cid:9)(cid:14)(cid:15)(cid:31)(cid:2)(cid:12)(cid:28)(cid:8)$(cid:28)(cid:17)(cid:14)(cid:2)%(cid:9)(cid:28)&(cid:7)(cid:15)(cid:17)"’(cid:2)(cid:12)(cid:16)(cid:14)(cid:28)"(cid:14)(cid:2)"(cid:14)(cid:14)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)((cid:28)(cid:8)$(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7))(cid:7)(cid:8)(cid:28)(cid:31)(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)(cid:31)(cid:14)%(cid:2)(cid:28)(cid:31)(cid:2) (cid:11)(cid:31)(cid:31)(cid:12)*++&&&(cid:20)!(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)!+(cid:12)(cid:28)(cid:8)$(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) DS20002230G-page 28  2010-2016 Microchip Technology Inc.

MCP2003/4/3A/4A APPENDIX A: REVISION HISTORY Revision G (December 2016) The following is the list of modifications” 1. Added note to page 1 header: “Not recommended for new designs”. 2. Updated Section3.1 “Package Marking Information”. 3. Minor typographical corrections. Revision F (November 2014) The following is the list of modifications: 1. Updated typical application circuits with values used during ESD tests. Revision E (October 2013) The following is the list of modifications: 1. Added additional specification for IHVREN in Section2.3 “DC Specifications”. 2. Clarified wake-up on L functionality. BUS 3. Added R monitoring description. XD Revision D (December 2011) The following is the list of modifications: 1. Added the MCP2003A and MCP2004A devices and related information throughout the docu- ment. 2. Updated Figures 1.2, 1.3, 1.4, 1.5, 2.6, 2.7. Revision C (August 2010) The following is the list of modifications: 1. Updated all references of Sleep mode to Power- Down mode, and updated the Max. parameter for Duty Cycle 2 in Section2.4 “AC Specifica- tions”. Revision B (July 2010) The following is the list of modifications: 1. Added Section2.2 “Nomenclature Used in This Document”, and added the “Capacitance of Slave Node” parameter to Section2.3 “DC Specifications”. Revision A (March 2010) • Original release of this document.  2010-2016 Microchip Technology Inc. DS20002230G-page 29

MCP2003/4/3A/4A NOTES: DS20002230G-page 30  2010-2016 Microchip Technology Inc.

MCP2003/4/3A/4A PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX Examples: a) MCP2003A-E/MD: Extended Temperature, Device Temperature Package 8L-DFN package Range b) MCP2003A-E/P: Extended Temperature, 8L-PDIP package c) MCP2003A-E/SN: Extended Temperature, Device: MCP2003: LIN Transceiver with WAKE pins, wake-up on 8L-SOIC package falling edge of LBUS d) MCP2003AT-E/MD: Tape and Reel, MCP2003T: LIN Transceiver with WAKE pins, wake-up on Extended Temperature, falling edge of LBUS (Tape and Reel) (DFN and SOIC only) 8L-DFN package MCP2003A: LIN Transceiver with WAKE pins, wake-up on e) MCP2003AT-E/SN: Tape and Reel, rising edge of LBUS Extended Temperature, MCP2003AT: LIN Transceiver with WAKE pins, wake-up on 8L-SOIC package rising edge of LBUS (Tape and Reel) (DFN and SOIC only) a) MCP2004-E/MD: Extended Temperature, 8L-DFN package MCP2004: LIN Transceiver with FAULT/TXE pins, wake-up b) MCP2004-E/P: Extended Temperature, on falling edge of LBUS 8L-PDIP package MCP2004T: LIN Transceiver with FAULT/TXE pins, wake-up on falling edge of LBUS (Tape and Reel) (DFN c) MCP2004A-E/SN: Extended Temperature, and SOIC only) 8L-SOIC package MCP2004A: LIN Transceiver with FAULT/TXE pins, wake-up d) MCP2004AT-E/MD: Tape and Reel, on rising edge of LBUS Extended Temperature, MCP2004AT: LIN Transceiver with FAULT/TXE pins, wake-up 8L-DFN package on rising edge of LBUS (Tape and Reel) (DFN e) MCP2004AT-E/SN: Tape and Reel, and SOIC only) Extended Temperature, 8L-SOIC package Temperature Range: E = -40°C to +125°C Package: MD = Plastic Dual Flat, No Lead Package – 4x4x0.9mm Body, 8-Lead P = Plastic Dual In-Line – 300 mil Body, 8-Lead SN = Plastic Small Outline – Narrow 3.90 mm Body, 8-Lead  2010-2016 Microchip Technology Inc. DS20002230G-page 31

MCP2003/4/3A/4A NOTES: DS20002230G-page 32  2010-2016 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, AnyRate, AVR, and may be superseded by updates. It is your responsibility to AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory, ensure that your application meets with your specifications. CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELOQ, MICROCHIP MAKES NO REPRESENTATIONS OR KEELOQ logo, Kleer, LANCheck, LINK MD, maXStylus, WARRANTIES OF ANY KIND WHETHER EXPRESS OR maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB, IMPLIED, WRITTEN OR ORAL, STATUTORY OR OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip OTHERWISE, RELATED TO THE INFORMATION, Designer, QTouch, RightTouch, SAM-BA, SpyNIC, SST, SST INCLUDING BUT NOT LIMITED TO ITS CONDITION, Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered QUALITY, PERFORMANCE, MERCHANTABILITY OR trademarks of Microchip Technology Incorporated in the U.S.A. FITNESS FOR PURPOSE. Microchip disclaims all liability and other countries. arising from this information and its use. Use of Microchip ClockWorks, The Embedded Control Solutions Company, devices in life support and/or safety applications is entirely at EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, the buyer’s risk, and the buyer agrees to defend, indemnify and mTouch, Precision Edge, and Quiet-Wire are registered hold harmless Microchip from any and all damages, claims, trademarks of Microchip Technology Incorporated in the U.S.A. suits, or expenses resulting from such use. No licenses are Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any conveyed, implicitly or otherwise, under any Microchip Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, intellectual property rights unless otherwise stated. CodeGuard, CryptoAuthentication, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in Microchip received ISO/TS-16949:2009 certification for its worldwide the U.S.A. headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California Silicon Storage Technology is a registered trademark of Microchip and India. The Company’s quality system processes and procedures Technology Inc. in other countries. are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and GestIC is a registered trademark of Microchip Technology analog products. In addition, Microchip’s quality system for the design Germany II GmbH & Co. KG, a subsidiary of Microchip Technology and manufacture of development systems is ISO 9001:2000 certified. Inc., in other countries. All other trademarks mentioned herein are property of their QUALITY MANAGEMENT SYSTEM respective companies. © 2010-2016, Microchip Technology Incorporated, All Rights CERTIFIED BY DNV Reserved. ISBN: 978-1-5224-1230-4 == ISO/TS 16949 ==  2010-2016 Microchip Technology Inc. DS20002230G-page 33

Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office Asia Pacific Office China - Xiamen Austria - Wels 2355 West Chandler Blvd. Suites 3707-14, 37th Floor Tel: 86-592-2388138 Tel: 43-7242-2244-39 Chandler, AZ 85224-6199 Tower 6, The Gateway Fax: 86-592-2388130 Fax: 43-7242-2244-393 Tel: 480-792-7200 Harbour City, Kowloon China - Zhuhai Denmark - Copenhagen Fax: 480-792-7277 Hong Kong Tel: 86-756-3210040 Tel: 45-4450-2828 Technical Support: Tel: 852-2943-5100 Fax: 86-756-3210049 Fax: 45-4485-2829 http://www.microchip.com/ Fax: 852-2401-3431 India - Bangalore Finland - Espoo support Australia - Sydney Tel: 91-80-3090-4444 Tel: 358-9-4520-820 Web Address: www.microchip.com Tel: 61-2-9868-6733 Fax: 91-80-3090-4123 France - Paris Fax: 61-2-9868-6755 India - New Delhi Tel: 33-1-69-53-63-20 Atlanta China - Beijing Tel: 91-11-4160-8631 Fax: 33-1-69-30-90-79 Duluth, GA Tel: 678-957-9614 Tel: 86-10-8569-7000 Fax: 91-11-4160-8632 France - Saint Cloud Fax: 678-957-1455 Fax: 86-10-8528-2104 India - Pune Tel: 33-1-30-60-70-00 China - Chengdu Tel: 91-20-3019-1500 Germany - Garching Austin, TX Tel: 512-257-3370 Tel: 86-28-8665-5511 Japan - Osaka Tel: 49-8931-9700 Fax: 86-28-8665-7889 Tel: 81-6-6152-7160 Germany - Haan Boston China - Chongqing Fax: 81-6-6152-9310 Tel: 49-2129-3766400 Westborough, MA Tel: 774-760-0087 Tel: 86-23-8980-9588 Japan - Tokyo Germany - Heilbronn Fax: 86-23-8980-9500 Tel: 81-3-6880- 3770 Tel: 49-7131-67-3636 Fax: 774-760-0088 China - Dongguan Fax: 81-3-6880-3771 Germany - Karlsruhe Chicago Itasca, IL Tel: 86-769-8702-9880 Korea - Daegu Tel: 49-721-625370 Tel: 630-285-0071 China - Guangzhou Tel: 82-53-744-4301 Germany - Munich Fax: 630-285-0075 Tel: 86-20-8755-8029 Fax: 82-53-744-4302 Tel: 49-89-627-144-0 China - Hangzhou Korea - Seoul Fax: 49-89-627-144-44 Dallas Addison, TX Tel: 86-571-8792-8115 Tel: 82-2-554-7200 Germany - Rosenheim Tel: 972-818-7423 Fax: 86-571-8792-8116 Fax: 82-2-558-5932 or Tel: 49-8031-354-560 Fax: 972-818-2924 China - Hong Kong SAR 82-2-558-5934 Israel - Ra’anana Detroit Tel: 852-2943-5100 Malaysia - Kuala Lumpur Tel: 972-9-744-7705 Fax: 852-2401-3431 Tel: 60-3-6201-9857 Novi, MI Italy - Milan Tel: 248-848-4000 China - Nanjing Fax: 60-3-6201-9859 Tel: 39-0331-742611 Houston, TX Tel: 86-25-8473-2460 Malaysia - Penang Fax: 39-0331-466781 Fax: 86-25-8473-2470 Tel: 60-4-227-8870 Tel: 281-894-5983 Italy - Padova Indianapolis China - Qingdao Fax: 60-4-227-4068 Tel: 39-049-7625286 Noblesville, IN Tel: 86-532-8502-7355 Philippines - Manila Netherlands - Drunen Fax: 86-532-8502-7205 Tel: 63-2-634-9065 Tel: 317-773-8323 Tel: 31-416-690399 Fax: 63-2-634-9069 Fax: 317-773-5453 China - Shanghai Fax: 31-416-690340 Tel: 317-536-2380 Tel: 86-21-3326-8000 Singapore Norway - Trondheim Fax: 86-21-3326-8021 Tel: 65-6334-8870 Los Angeles Tel: 47-7289-7561 Mission Viejo, CA China - Shenyang Fax: 65-6334-8850 Poland - Warsaw Tel: 949-462-9523 Tel: 86-24-2334-2829 Taiwan - Hsin Chu Tel: 48-22-3325737 Fax: 949-462-9608 Fax: 86-24-2334-2393 Tel: 886-3-5778-366 Tel: 951-273-7800 China - Shenzhen Fax: 886-3-5770-955 Romania - Bucharest Tel: 40-21-407-87-50 Raleigh, NC Tel: 86-755-8864-2200 Taiwan - Kaohsiung Tel: 919-844-7510 Fax: 86-755-8203-1760 Tel: 886-7-213-7830 Spain - Madrid Tel: 34-91-708-08-90 New York, NY China - Wuhan Taiwan - Taipei Fax: 34-91-708-08-91 Tel: 631-435-6000 Tel: 86-27-5980-5300 Tel: 886-2-2508-8600 Fax: 86-27-5980-5118 Fax: 886-2-2508-0102 Sweden - Gothenberg San Jose, CA Tel: 46-31-704-60-40 Tel: 408-735-9110 China - Xian Thailand - Bangkok Tel: 408-436-4270 Tel: 86-29-8833-7252 Tel: 66-2-694-1351 Sweden - Stockholm Fax: 86-29-8833-7256 Fax: 66-2-694-1350 Tel: 46-8-5090-4654 Canada - Toronto Tel: 905-695-1980 UK - Wokingham Fax: 905-695-2078 Tel: 44-118-921-5800 Fax: 44-118-921-5820 DS20002230G-page 34  2010-2016 Microchip Technology Inc. 11/07/16