MCP1827/MCP1827S 1.5A, Low-Voltage, Low Quiescent Current LDO Regulator Features: Description: • 1.5A Output Current Capability The MCP1827/MCP1827S is a 1.5A Low Dropout • Input Operating Voltage Range: 2.3V to 6.0V (LDO) linear regulator that provides high current and low output voltages. The MCP1827 comes in a fixed or • Adjustable Output Voltage Range: 0.8V to 5.0V adjustable output voltage version, with an output (MCP1827 only) voltage range of 0.8V to 5.0V. The 1.5A output current • Standard Fixed Output Voltages: capability, combined with the low output voltage - 0.8V, 1.2V, 1.8V, 2.5V, 3.0V, 3.3V, 5.0V capability, make the MCP1827 a good choice for new • Other Fixed Output Voltage Options Available sub-1.8V output voltage LDO applications that have Upon Request high current demands. The MCP1827S is a 3-pin fixed • Low Dropout Voltage: 330mV Typical at 1.5A voltage version. The MCP1827/MCP1827S is based • Typical Output Voltage Tolerance: 0.5% upon the MCP1727 LDO device. • Stable with 1.0µF Ceramic Output Capacitor The MCP1827/MCP1827S is stable using ceramic output capacitors that inherently provide lower output • Fast response to Load Transients noise and reduce the size and cost of the entire • Low Supply Current: 120µA (typ) regulator solution. Only 1µF of output capacitance is • Low Shutdown Supply Current: 0.1µA (typ) needed to stabilize the LDO. (MCP1827 only) Using CMOS construction, the quiescent current • Fixed Delay on Power Good Output consumed by the MCP1827/MCP1827S is typically (MCP1827 only) less than 120µA over the entire input voltage range, • Short Circuit Current Limiting and making it attractive for portable computing applications Overtemperature Protection that demand high output current. The MCP1827 • 5-Lead Plastic DDPAK, 5-Lead TO-220 Package versions have a Shutdown (SHDN) pin. When shut Options (MCP1827) down, the quiescent current is reduced to less than 0.1µA. • 3-Lead Plastic DDPAK, 3-Lead TO-220 Package Options (MCP1827S) On the MCP1827 fixed output versions the scaled- down output voltage is internally monitored and a Applications: power good (PWRGD) output is provided when the output is within 92% of regulation (typical). The • High-Speed Driver Chipset Power PWRGD delay is internally fixed at 200µs (typical). • Networking Backplane Cards The overtemperature and short circuit current-limiting • Notebook Computers provide additional protection for the LDO during system Fault conditions. • Network Interface Cards • Palmtop Computers Package Types • 2.5V to 1.XV Regulators 5-LD DDPAK 5-LD TO-220 Fixed/Adjustable 3-LD DDPAK 3-LD TO-220 MCP1827 MCP1827S MCP1827S MCP1827 1 2 3 1 2 3 4 5 SHDNVINGND(TAB)VOUTPWRGD SHDN1VIN2D(TAB)3VOUT4ADJ5 VIN GND(TAB) VOUT V1IN D(TAB)2 V3OUT N N G G  2006-2013 Microchip Technology Inc. DS22001D-page 1

MCP1827/MCP1827S Typical Application MCP1827 Fixed Output Voltage PWRGD R 1 On 100k Off SHDN 1 2 3 4 5 VIN = 2.3V to 2.8V VIN VOUT VOUT = 1.8V @ 1A GND C 1 C 4.7µF 2 1µF MCP1827 Adjustable Output Voltage VADJ R 2 20k R 1 On 40k Off SHDN 1 2 3 4 5 VIN = 2.3V to 2.8V VIN VOUT VOUT = 1.2V @ 1A GND C 1 C 4.7µF 2 1µF DS22001D-page 2  2006-2013 Microchip Technology Inc.

MCP1827/MCP1827S Functional Block Diagram – Adjustable Output PMOS VIN VOUT Undervoltage Lock Out (UVLO) I SNS Cf Rf SHDN ADJ + Driver w/limit and SHDN EA Overtemperature – Sensing SHDN V REF VIN SHDN Reference Soft-Start Comp T DELAY GND 92% of V REF  2006-2013 Microchip Technology Inc. DS22001D-page 3

MCP1827/MCP1827S Functional Block Diagram – Fixed Output (5-pin) PMOS VIN VOUT Undervoltage Sense Lock Out (UVLO) I SNS Cf Rf SHDN + Driver w/limit and SHDN EA Overtemperature – Sensing SHDN V REF VIN SHDN Reference Soft-Start PWRGD Comp T DELAY GND 92% of V REF DS22001D-page 4  2006-2013 Microchip Technology Inc.

MCP1827/MCP1827S Functional Block Diagram – Fixed Output (3-Pin) PMOS VIN VOUT Undervoltage Sense Lock Out (UVLO) I SNS Cf Rf SHDN + Driver w/limit and SHDN EA Overtemperature – Sensing SHDN V REF V IN SHDN Reference Soft-Start Comp T DELAY GND 92% of V REF  2006-2013 Microchip Technology Inc. DS22001D-page 5

MCP1827/MCP1827S 1.0 ELECTRICAL † Notice: Stresses above those listed under “Maximum Rat- ings” may cause permanent damage to the device. This is a CHARACTERISTICS stress rating only and functional operation of the device at those or any other conditions above those indicated in the Absolute Maximum Ratings † operational listings of this specification is not implied. Expo- sure to maximum rating conditions for extended periods may VIN....................................................................................6.5V affect device reliability. Maximum Voltage on Any Pin..(GND – 0.3V) to (V + 0.3)V DD Maximum Power Dissipation.........Internally-Limited (Note6) Output Short Circuit Duration................................Continuous Storage temperature.....................................-65°C to +150°C Maximum Junction Temperature, T ...........................+150°C J ESD protection on all pins (HBM/MM) 2kV;  200V AC/DC CHARACTERISTICS Electrical Specifications: Unless otherwise noted, V = V + V Note1, V =1.8V for Adjustable Output, IN OUT(MAX) DROPOUT(MAX) R I = 1mA, C = C = 4.7µF (X7R Ceramic), T = +25°C. Boldface type applies for junction temperatures, T (Note7) of OUT IN OUT A J -40°C to +125°C Parameters Sym. Min. Typ. Max. Units Conditions Input Operating Voltage V 2.3 6.0 V IN Input Quiescent Current I — 120 220 µA I = 0mA, q L V = 0.8V to 5.0V OUT Input Quiescent Current for I — 0.1 3 µA SHDN = GND SHDN SHDN Mode Maximum Output Current I 1.5 — — A V = 2.3V to 6.0V OUT IN V = 0.8V to 5.0V R Line Regulation V / — 0.05 0.16 %/V (Note1) V 6V OUT IN (V x V ) OUT IN Load Regulation V /V -1.0 ±0.5 1.0 % I = 1mA to 1.5A OUT OUT OUT (Note4) Output Short Circuit Current I — 2.2 — A R <0.1, Peak Current OUT_SC LOAD Adjust Pin Characteristics (Adjustable Output Only) Adjust Pin Reference Voltage V 0.402 0.410 0.418 V V = 2.3V to V =6.0V, ADJ IN IN I = 1mA OUT Adjust Pin Leakage Current I -10 ±0.01 +10 nA V = 6.0V, V =0Vto6V ADJ IN ADJ Adjust Temperature Coefficient TCV — 40 — ppm/°C Note3 OUT Fixed-Output Characteristics (Fixed Output Only) Voltage Regulation V V - 2.5% V V + 2.5% V Note2 OUT R R R ±0.5% Note 1: The minimum V must meet two conditions: V 2.3V and V V V IN IN IN OUT(MAX) DROPOUT(MAX). 2: V is the nominal regulator output voltage for the fixed cases. V = 1.2V, 1.8V, etc. V is the desired set point output R R R voltage for the adjustable cases. V = V ((R /R )+1). Figure4-1. R ADJ* 1 2 3: TCV = (V – V ) *106 / (V * Temperature). V is the highest voltage measured over the OUT OUT-HIGH OUT-LOW R OUT-HIGH temperature range. V is the lowest voltage measured over the temperature range. OUT-LOW 4: Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is tested over a load range from 1mA to the maximum specified output current. 5: Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its nominal value that was measured with an input voltage of V V + V . IN = OUTMAX DROPOUT(MAX) 6: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air. (i.e., T , T ,  ). Exceeding the maximum allowable power A J JA dissipation will cause the device operating junction temperature to exceed the maximum +150°C rating. Sustained junction temperatures above 150°C can impact device reliability. 7: The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the desired junction temperature. The test time is small enough such that the rise in the junction temperature over the ambient temperature is not significant. DS22001D-page 6  2006-2013 Microchip Technology Inc.

MCP1827/MCP1827S AC/DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise noted, V = V + V Note1, V =1.8V for Adjustable Output, IN OUT(MAX) DROPOUT(MAX) R I = 1mA, C = C = 4.7µF (X7R Ceramic), T = +25°C. Boldface type applies for junction temperatures, T (Note7) of OUT IN OUT A J -40°C to +125°C Parameters Sym. Min. Typ. Max. Units Conditions Dropout Characteristics Dropout Voltage V -V — 330 600 mV Note5, I = 1.5A, IN OUT OUT V =2.3V IN(MIN) Power Good Characteristics PWRGD Input Voltage Operat- V 1.0 — 6.0 V T = +25°C PWRGD_VIN A ing Range 1.2 — 6.0 T = -40°C to +125°C A For V < 2.3V, I =100µA IN SINK PWRGD Threshold Voltage V %V Falling Edge PWRGD_TH OUT (Referenced to V ) OUT 89 92 95 V < 2.5V Fixed, V = Adj. OUT OUT 90 92 94 V >= 2.5V Fixed OUT PWRGD Threshold Hysteresis V 1.0 2.0 3.0 %V PWRGD_HYS OUT PWRGD Output Voltage Low V — 0.2 0.4 V I = 1.2mA, PWRGD_L PWRGDSINK ADJ = 0V PWRGD Leakage P _ — 1 — nA V = V = 6.0V WRGD LK PWRGD IN PWRGD Time Delay T — 200 — µs Rising Edge PG R = 10k PULLUP Detect Threshold to PWRGD T — 200 — µs V or V = V + VDET-PWRGD ADJ OUT PWRGD_TH Active Time Delay 20mV to V - 20mV PWRGD_TH Shutdown Input Logic High Input V 45 %V V = 2.3V to 6.0V SHDN-HIGH IN IN Logic Low Input V 15 %V V = 2.3V to 6.0V SHDN-LOW IN IN SHDN Input Leakage Current SHDN -0.1 ±0.001 +0.1 µA V =6V, SHDN =V , ILK IN IN SHDN = GND AC Performance Output Delay From SHDN T 100 µs SHDN = GND to V OR IN V = GND to 95% V OUT R Output Noise e — 2.0 — µV/Hz I = 200mA, f = 1kHz, C N OUT OUT = 10µF (X7R Ceramic), V = OUT 2.5V Power Supply Ripple Rejection PSRR — 60 — dB f = 100Hz, C = 10µF, OUT Ratio I = 10mA, OUT V = 30mV pk-pk, INAC C = 0µF IN Note 1: The minimum V must meet two conditions: V 2.3V and V V V IN IN IN OUT(MAX) DROPOUT(MAX). 2: V is the nominal regulator output voltage for the fixed cases. V = 1.2V, 1.8V, etc. V is the desired set point output R R R voltage for the adjustable cases. V = V ((R /R )+1). Figure4-1. R ADJ* 1 2 3: TCV = (V – V ) *106 / (V * Temperature). V is the highest voltage measured over the OUT OUT-HIGH OUT-LOW R OUT-HIGH temperature range. V is the lowest voltage measured over the temperature range. OUT-LOW 4: Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is tested over a load range from 1mA to the maximum specified output current. 5: Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its nominal value that was measured with an input voltage of V V + V . IN = OUTMAX DROPOUT(MAX) 6: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air. (i.e., T , T ,  ). Exceeding the maximum allowable power A J JA dissipation will cause the device operating junction temperature to exceed the maximum +150°C rating. Sustained junction temperatures above 150°C can impact device reliability. 7: The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the desired junction temperature. The test time is small enough such that the rise in the junction temperature over the ambient temperature is not significant.  2006-2013 Microchip Technology Inc. DS22001D-page 7

MCP1827/MCP1827S AC/DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise noted, V = V + V Note1, V =1.8V for Adjustable Output, IN OUT(MAX) DROPOUT(MAX) R I = 1mA, C = C = 4.7µF (X7R Ceramic), T = +25°C. Boldface type applies for junction temperatures, T (Note7) of OUT IN OUT A J -40°C to +125°C Parameters Sym. Min. Typ. Max. Units Conditions Thermal Shutdown Temperature T — 150 — °C I = 100µA, V = 1.8V, SD OUT OUT V = 2.8V IN Thermal Shutdown Hysteresis T — 10 — °C I = 100µA, V = 1.8V, SD OUT OUT V = 2.8V IN Note 1: The minimum V must meet two conditions: V 2.3V and V V V IN IN IN OUT(MAX) DROPOUT(MAX). 2: V is the nominal regulator output voltage for the fixed cases. V = 1.2V, 1.8V, etc. V is the desired set point output R R R voltage for the adjustable cases. V = V ((R /R )+1). Figure4-1. R ADJ* 1 2 3: TCV = (V – V ) *106 / (V * Temperature). V is the highest voltage measured over the OUT OUT-HIGH OUT-LOW R OUT-HIGH temperature range. V is the lowest voltage measured over the temperature range. OUT-LOW 4: Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is tested over a load range from 1mA to the maximum specified output current. 5: Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its nominal value that was measured with an input voltage of V V + V . IN = OUTMAX DROPOUT(MAX) 6: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air. (i.e., T , T ,  ). Exceeding the maximum allowable power A J JA dissipation will cause the device operating junction temperature to exceed the maximum +150°C rating. Sustained junction temperatures above 150°C can impact device reliability. 7: The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the desired junction temperature. The test time is small enough such that the rise in the junction temperature over the ambient temperature is not significant. TEMPERATURE SPECIFICATIONS Electrical Specifications: Unless otherwise indicated, all limits apply for V = 2.3V to 6.0V. IN Parameters Sym. Min. Typ. Max. Units Conditions Temperature Ranges Operating Junction Temperature T -40 — +125 °C Steady State J Range Maximum Junction Temperature T — — +150 °C Transient J Storage Temperature Range T -65 — +150 °C A Thermal Package Resistances Thermal Resistance, 5LD DDPAK  — 31.2 — °C/W 4-Layer JC51 Standard Board JA Thermal Resistance, 3LD DDPAK  — 31.4 — °C/W 4-Layer JC51 Standard Board JA Thermal Resistance, 5LD TO-220  — 29.3 — °C/W 4-Layer JC51 Standard Board JA Thermal Resistance, 3LD TO-220  — 29.4 — °C/W 4-Layer JC51 Standard Board JA DS22001D-page 8  2006-2013 Microchip Technology Inc.

MCP1827/MCP1827S 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, V = 1.8V (Adjustable), V = 2.8V, C = 4.7µF Ceramic (X7R), C = 4.7µF OUT IN OUT IN Ceramic (X7R), I = 1mA, Temperature = +25°C, V = V + 0.6V, R = 10k To V . OUT IN OUT PWRGD IN Note: Junction Temperature (T ) is approximated by soaking the device under test to an ambient temperature equal to J the desired Junction temperature. The test time is small enough such that the rise in Junction temperature over the Ambient temperature is not significant. 150 0.1 0.09 VOUT = 1.2V adj nt (μA) 113400 130°C n (%/V) 00..0078 IOUT = 1 mA VIN = 2.3V to 6.0V scent Curre 111200 2950°°CC e Regulatio 0000....00003456 IOUT = 100 mA IOUT = 1000I OmUTA = 500 mA Quie 100 -45°C VIOOUUTT = = 0 1 m.2AV Adj Lin 00..0012 90 0 2 3 4 5 6 -45 -20 5 30 55 80 105 130 Input Voltage (V) Temperature (°C) FIGURE 2-1: Quiescent Current vs. Input FIGURE 2-4: Line Regulation vs. Voltage (1.2V Adjustable). Temperature (1.2V Adjustable). 0.15 200 IOUT = 1.0 mA to 1500 mA urrent (µA) 111115678900000 VIN=5.0V gulation (%) 000...001050 VOUT = 0.8VVOUT = 3.3V VOUT = 1.8V Ground C 111112340000 VIN=3.3V VIN=2.3V VOUT = 1.2V Adj Load Re --00..1005 VOUT = 5.0V 100 -0.15 0 250 500 750 1000 1250 1500 -45 -20 5 30 55 80 105 130 Load Current (mA) Temperature (°C) FIGURE 2-5: Load Regulation vs. FIGURE 2-2: Ground Current vs. Load Temperature (Adjustable Version). Current (1.2V Adjustable). 0.411 140 Quiescent Current (μA) 111111101122335050505 VIN=5.0V VIN= V4 .O 0 U V TI O=U 1T .=2 VV0I NAm=d2Aj.5V Adjust Pin Voltage (V) 0000....444400119900 VIVNV I=NIN =6 = .20 5.V3.0VV IOUT = 1.0 mA 100 0.408 -45 -20 5 30 55 80 105 130 -45 -20 5 30 55 80 105 130 Temperature (°C) Temperature (°C) FIGURE 2-3: Quiescent Current vs. FIGURE 2-6: Adjust Pin Voltage vs. Junction Temperature (1.2V Adjustable). Temperature.  2006-2013 Microchip Technology Inc. DS22001D-page 9

MCP1827/MCP1827S Note: Unless otherwise indicated, V = 1.8V (Adjustable), V = 2.8V, C = 4.7µF Ceramic (X7R), C = 4.7µF OUT IN OUT IN Ceramic (X7R), I = 1mA, Temperature = +25°C, V = V + 0.6V, R = 10k To V . OUT IN OUT PWRGD IN 0.35 150 ut Voltage (V) 0000....12235050 VOUT = V5O.0UVT =A d2.j5V Adj nt Current (μA) 111112340000 VIOOUUTT = = 0 0 m.8AV +-++148235550°°°°CCCC Dropo 00..0150 uiesce 10900 Q 0.00 80 0 250 500 750 1000 1250 1500 2 3 4 5 6 Load Current (mA) Input Voltage (V) FIGURE 2-7: Dropout Voltage vs. Load FIGURE 2-10: Quiescent Current vs. Input Current (Adjustable Version). Voltage (0.8V Fixed). 0.42 150 IOUT = 1.5A VOUT = 2.5V Voltage (V) 000...334680 VOUT = 5.0V Adj Current (μA) 111234000 IOUT = 0 mA +++1293500°°°CCC Dropout 00..3324 VOUT = 2.5V Adj VOUT = 3.3V Adj Quiescent 11019000 -45°C 0.30 80 -45 -20 5 30 55 80 105 130 3 3.5 4 4.5 5 5.5 6 Temperature (°C) Input Voltage (V) FIGURE 2-8: Dropout Voltage vs. FIGURE 2-11: Quiescent Current vs. Input Temperature (Adjustable Version). Voltage (2.5V Fixed). 370 250.00 ower Good Time Delay (µs) 333333123456000000 VVIINN V== IN35 ..=90 VV4.5V VOUT = 3.3V Fixed Ground Current (μA) 11205050000....00000000 VOUT=0.8VVOUVVTI=INN2 ==.5 23V..31VV ffoorr VVRR==02..85VV P 300 0.00 -45 -20 5 30 55 80 105 130 0 250 500 750 1000 1250 1500 Temperature (°C) Load Current (mA) FIGURE 2-9: Power Good (PWRGD) FIGURE 2-12: Ground Current vs. Load Time Delay vs. Temperature (Adjustable Current. Version). DS22001D-page 10  2006-2013 Microchip Technology Inc.

MCP1827/MCP1827S Note: Unless otherwise indicated, V = 1.8V (Adjustable), V = 2.8V, C = 4.7µF Ceramic (X7R), C = 4.7µF OUT IN OUT IN Ceramic (X7R), I = 1mA, Temperature = +25°C, V = V + 0.6V, R = 10k To V . OUT IN OUT PWRGD IN 130 0.045 ent (μA) 112205 IOUT = 0 mA n (%/V) 00..003450 IOUT = 1 mA V I N = 3 .V1R t =o 26..50VV Quiescent Curr 111100110505 VOUT = 0.8V Line Regulatio 000...000223050 IOUT =I O1U0T0 =0 1m0A0 mA IOUT = 500 mA VOUT = 2.5V IOUT = 1500 mA 95 0.015 -45 -20 5 30 55 80 105 130 -45 -20 5 30 55 80 105 130 Temperature (°C) Temperature (°C) FIGURE 2-13: Quiescent Current vs. FIGURE 2-16: Line Regulation vs. Temperature. Temperature (2.5V Fixed). 0.30 0.25 VR = 0.8V %) 00..2300 VOUT = 0.8V VIN = 2.3V hdn (μA) 00..1250 VVIINN == 46..00VV gulation ( 00..0100 Is 0.10 VIN = 2.3V d Re -0.10 IOUT = 1 mA to 1500 mA 0.05 oa -0.20 L 0.00 -0.30 -45 -20 5 30 55 80 105 130 -45 -20 5 30 55 80 105 130 Temperature (°C) Temperature (°C) FIGURE 2-14: I vs. Temperature. FIGURE 2-17: Load Regulation vs. SHDN Temperature (V < 2.5V Fixed). OUT 0.10 0.00 -0.05 IOUT = 1 mA to 1500 mA Regulation (%/V) 000...000468 IOUT = 500mIOAUT = 1A IOUITO =UT 1 =0 01 mmAA Regulation (%) -----00000.....3221105050 VVOOUUTT == 52..05VV Line 0.02 VVOINU =T =2 .03.V8 Vto 6.0V Load --00..4305 0.00 -0.45 -45 -20 5 30 55 80 105 130 -45 -20 5 30 55 80 105 130 Temperature (°C) Temperature (°C) FIGURE 2-15: Line Regulation vs. FIGURE 2-18: Load Regulation vs. Temperature (0.8V Fixed). Temperature (V 2.5V Fixed). OUT  2006-2013 Microchip Technology Inc. DS22001D-page 11

MCP1827/MCP1827S Note: Unless otherwise indicated, V = 1.8V (Adjustable), V = 2.8V, C = 4.7µF Ceramic (X7R), C = 4.7µF OUT IN OUT IN Ceramic (X7R), I = 1mA, Temperature = +25°C, V = V + 0.6V, R = 10k To V . OUT IN OUT PWRGD IN 0.40 10.000 Temperature = 25°C V) 00..3305 VOUT = 2.5V VR=0.8V, VIN=2.3V COUT=C1I Nμ=F1 0c eμrFa mceicra Xm7iRc Dropout Voltage ( 0000....11220505 VOUT = 5.0V Noise (µV/Hz) 01..100000 VR=3.3V, VIN=4.1V IOUT=200 mA 0.05 0.00 0.010 0 250 500 750 1000 1250 1500 0.01 0.1 1 10 100 1000 Load Current (mA) Frequency (kHz) FIGURE 2-19: Dropout Voltage vs. Load FIGURE 2-22: Output Noise Voltage Current. Density vs. Frequency. 0.45 0 IOUT = 1.5A -10 e (V) 0.40 -20 ag B) -30 out Volt 0.35 VOUT = 5.0V SRR (d --5400 VCRO=UT1=.21V0 AμFd jceramic X7R Drop 0.30 VOUT = 2.5V P --7600 VCIOIIUNNT===301. 1μ0V FmA 0.25 -80 -45 -20 5 30 55 80 105 130 0.01 0.1 1 10 100 1000 Temperature (°C) Frequency (kHz) FIGURE 2-20: Dropout Voltage vs. FIGURE 2-23: Power Supply Ripple Temperature. Rejection (PSRR) vs. Frequency (V = 1.2V OUT Adj.). 0 3.00 nt (A) 2.50 --2100 urre 2.00 dB)-30 uit C 1.50 RR (-40 VR=1.2V Adj ort Circ 01..5000 VOUT = 2.5V PS--6500 CVCIOINNU==T30=. 21μ2VF μF ceramic X7R Sh Temperature = 25°C -70 IOUT=10 mA 0.00 -80 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0.01 0.1 1 10 100 1000 Input Voltage (V) Frequency (kHz) FIGURE 2-21: Short Circuit Current vs. FIGURE 2-24: Power Supply Ripple Input Voltage. Rejection (PSRR) vs. Frequency (V = 1.2V OUT Adj.). DS22001D-page 12  2006-2013 Microchip Technology Inc.

MCP1827/MCP1827S Note: Unless otherwise indicated, V = 1.8V (Adjustable), V = 2.8V, C = 4.7µF Ceramic (X7R), C = 4.7µF OUT IN OUT IN Ceramic (X7R), I = 1mA, Temperature = +25°C, V = V + 0.6V, R = 10k To V . OUT IN OUT PWRGD IN 0 -10 -20 B)-30 d RR (-40 VR=3.3V Fixed PS--6500 CVIONU=T3=.190V μF ceramic X7R CIN=0 μF -70 IOUT=10 mA -80 0.01 0.1 1 10 100 1000 Frequency (kHz) FIGURE 2-25: Power Supply Ripple FIGURE 2-28: 2.5V (Adj.) Startup from Rejection (PSRR) vs. Frequency (V = 3.3V Shutdown. OUT Fixed). 0 -10 -20 B)-30 d R (-40 R VR=3.3V Fixed PS-50 COUT=22 μF ceramic X7R -60 VIN=3.9V CIN=0 μF -70 IOUT=10 mA -80 0.01 0.1 1 10 100 1000 Frequency (kHz) FIGURE 2-26: Power Supply Ripple FIGURE 2-29: Power Good (PWRGD) Rejection (PSRR) vs. Frequency (V = 3.3V Timing. OUT Fixed). FIGURE 2-27: 2.5V (Adj.) Startup from V . FIGURE 2-30: Dynamic Line Response IN (3.3V Fixed).  2006-2013 Microchip Technology Inc. DS22001D-page 13

MCP1827/MCP1827S Note: Unless otherwise indicated, V = 1.8V (Adjustable), V = 2.8V, C = 4.7µF Ceramic (X7R), C = 4.7µF OUT IN OUT IN Ceramic (X7R), I = 1mA, Temperature = +25°C, V = V + 0.6V, R = 10k To V . OUT IN OUT PWRGD IN FIGURE 2-31: Dynamic Load Response FIGURE 2-32: Dynamic Load Response (3.3V Fixed, 10mA to 1500mA). (3.3V Fixed, 100mA to 1500mA). DS22001D-page 14  2006-2013 Microchip Technology Inc.

MCP1827/MCP1827S 3.0 PIN DESCRIPTION The descriptions of the pins are listed in Table3-1. TABLE 3-1: PIN FUNCTION TABLE 3-Pin Fixed 5-Pin Fixed Adjustable Name Description Output Output Output — 1 1 SHDN Shutdown Control Input (active-low) 1 2 2 V Input Voltage Supply IN 2 3 3 GND Ground 3 4 4 V Regulated Output Voltage OUT — 5 — PWRGD Power Good Output — — 5 ADJ Voltage Adjust/Sense Input Pad Pad Pad EP Exposed Pad of the Package (ground potential) 3.1 Input Voltage Supply (V ) 3.4 Power Good Output (PWRGD) IN Connect the unregulated or regulated input voltage The PWRGD output is an open-drain output used to source to V . If the input voltage source is located indicate when the LDO output voltage is within 92% IN several inches away from the LDO, or the input source (typically) of its nominal regulation value. The PWRGD is a battery, it is recommended that an input capacitor threshold has a typical hysteresis value of 2%. The be used. A typical input capacitance value of 1µF to PWRGD output is delayed by 200µs (typical) from the 10µF should be sufficient for most applications. time the LDO output is within 92% + 3% (max hysteresis) of the regulated output value on power-up. 3.2 Shutdown Control Input (SHDN) This delay time is internally fixed. The SHDN input is used to turn the LDO output voltage 3.5 Output Voltage Adjust Input (ADJ) on and off. When the SHDN input is at a logic-high level, the LDO output voltage is enabled. When the For adjustable applications, the output voltage is SHDN input is pulled to a logic-low level, the LDO connected to the ADJ input through a resistor divider output voltage is disabled. When the SHDN input is that sets the output voltage regulation value. This pulled low, the PWRGD output also goes low and the provides the user the capability to set the output LDO enters a low quiescent current shutdown state voltage to any value they desire within the 0.8V to 5.0V where the typical quiescent current is 0.1µA. range of the device. 3.3 Ground (GND) 3.6 Regulated Output Voltage (V ) OUT Connect the GND pin of the LDO to a quiet circuit The V pin is the regulated output voltage of the OUT ground. This will help the LDO power supply rejection LDO. A minimum output capacitance of 1.0µF is ratio and noise performance. The ground pin of the required for LDO stability. The MCP1827/MCP1827S is LDO only conducts the quiescent current of the LDO stable with ceramic, tantalum and aluminum-electro- (typically 120µA), so a heavy trace is not required. lytic capacitors. See Section4.3 “Output Capacitor” For applications have switching or noisy inputs tie the for output capacitor selection guidance. GND pin to the return of the output capacitor. Ground 3.7 Exposed Pad (EP) planes help lower inductance and voltage spikes caused by fast transient load currents and are The DDPAK and TO-220 package have an exposed tab recommended for applications that are subjected to on the package. A heat sink may be mount to the tab to fast load transients. aid in the removal of heat from the package during operation. The exposed tab is at the ground potential of the LDO.  2006-2013 Microchip Technology Inc. DS22001D-page 15

MCP1827/MCP1827S 4.0 DEVICE OVERVIEW EQUATION 4-2: V –V The MCP1827/MCP1827S is a high output current, R = R ----O----U----T------------A----D---J- 1 2 V  Low Dropout (LDO) voltage regulator. The low dropout ADJ Where: voltage of 330mV typical at 1.5A of current makes it ideal for battery-powered applications. Unlike other V = LDO Output Voltage OUT high output current LDOs, the MCP1827/MCP1827S V = ADJ Pin Voltage ADJ only draws a maximum of 220µA of quiescent current. (typically 0.41V) The MCP1827 has a shutdown control input and a power good output. 4.2 Output Current and Current 4.1 LDO Output Voltage Limiting The 5-pin MCP1827 LDO is available with either a fixed The MCP1827/MCP1827S LDO is tested and ensured output voltage or an adjustable output voltage. The to supply a minimum of 1.5A of output current. The output voltage range is 0.8V to 5.0V for both versions. MCP1827/MCP1827S has no minimum output load, so The 3-pin MCP1827S LDO is available as a fixed the output load current can go to 0mA and the LDO will voltage device. continue to regulate the output voltage to within tolerance. 4.1.1 ADJUST INPUT The MCP1827/MCP1827S also incorporates an output The adjustable version of the MCP1827 uses the ADJ current limit. If the output voltage falls below 0.7V due pin (pin 5) to get the output voltage feedback for output to an overload condition (usually represents a shorted voltage regulation. This allows the user to set the load condition), the output current is limited to 2.2A output voltage of the device with two external resistors. (typical). If the overload condition is a soft overload, the The nominal voltage for ADJ is 0.41V. MCP1827/MCP1827S will supply higher load currents Figure4-1 shows the adjustable version of the of up to 3A. The MCP1827/MCP1827S should not be MCP1827. Resistors R and R form the resistor operated in this condition continuously as it may result 1 2 divider network necessary to set the output voltage. in failure of the device. However, this does allow for With this configuration, the equation for setting V is: device usage in applications that have higher pulsed OUT load currents having an average output current value of EQUATION 4-1: 1.5A or less. R +R Output overload conditions may also result in an over- VOUT = VADJ----1---R----------2- temperature shutdown of the device. If the junction Where: 2 temperature rises above 150°C, the LDO will shut down the output voltage. See Section4.8 VOUT = LDO Output Voltage “Overtemperature Protection” for more information V = ADJ Pin Voltage on overtemperature shutdown. ADJ (typically 0.41V) 4.3 Output Capacitor The MCP1827/MCP1827S requires a minimum output MCP1827-ADJ capacitance of 1µF for output voltage stability. Ceramic VOUT capacitors are recommended because of their size, Off On 1 2 3 4 5 R1 C2 cost and environmental robustness qualities. SHDN ADJ 1µF Aluminum-electrolytic and tantalum capacitors can be used on the LDO output as well. The Equivalent Series VIN Resistance (ESR) of the electrolytic output capacitor 4C.71µF GND R2 must be no greater than 1 ohm. The output capacitor should be located as close to the LDO output as is practical. Ceramic materials X7R and X5R have low temperature coefficients and are well within the FIGURE 4-1: Typical adjustable output acceptable ESR range required. A typical 1µF X7R voltage application circuit. 0805 capacitor has an ESR of 50 milli-ohms. The allowable resistance value range for resistor R is 2 from 10k to 200k. Solving the equation for R 1 yields the following equation: DS22001D-page 16  2006-2013 Microchip Technology Inc.

MCP1827/MCP1827S Larger LDO output capacitors can be used with the When the LDO is put into Shutdown mode using the MCP1827/MCP1827S to improve dynamic SHDN input, the power good output is pulled low performance and power supply ripple rejection. A immediately, indicating that the output voltage will be maximum of 22µF is recommended. Aluminum- out of regulation. The timing diagram for the power electrolytic capacitors are not recommended for low- good output when using the shutdown input is shown in temperature applications of 25°C. Figure4-3. The power good output is an open-drain output that can 4.4 Input Capacitor be pulled up to any voltage that is equal to or less than the LDO input voltage. This output is capable of sinking Low input source impedance is necessary for the LDO 1.2mA (V < 0.4V maximum). output to operate properly. When operating from PWRGD batteries, or in applications with long lead length (> 10 inches) between the input source and the LDO, some input capacitance is recommended. A minimum VPWRGD_TH of 1.0µF to 4.7µF is recommended for most applications. VOUT For applications that have output step load TPG requirements, the input capacitance of the LDO is very important. The input capacitance provides the LDO VOH with a good local low-impedance source to pull the TVDET_PWRGD transient currents from in order to respond quickly to the output load step. For good step response PWRGD performance, the input capacitor should be of equivalent (or higher) value than the output capacitor. VOL The capacitor should be placed as close to the input of the LDO as is practical. Larger input capacitors will also help reduce any high-frequency noise on the input and FIGURE 4-2: Power Good Timing. output of the LDO and reduce the effects of any inductance that exists between the input source voltage and the input capacitance of the LDO. VIN 4.5 Power Good Output (PWRGD) TOR The PWRGD output is used to indicate when the output 70µs 30 µs voltage of the LDO is within 92% (typical value, see Section1.0 “Electrical Characteristics” for Minimum and Maximum specifications) of its nominal regulation SHDN TPG value. As the output voltage of the LDO rises, the PWRGD output will be held low until the output voltage has exceeded the power good threshold plus the hysteresis VOUT value. Once this threshold has been exceeded, the power good time delay is started (shown as T in the PG Electrical Characteristics table). The power good time delay is fixed at 200µs (typical). After the time delay PWRGD period, the PWRGD output will go high, indicating that the output voltage is stable and within regulation limits. If the output voltage of the LDO falls below the power FIGURE 4-3: Power Good Timing from good threshold, the power good output will transition low. The power good circuitry has a 170µs delay when Shutdown. detecting a falling output voltage, which helps to increase noise immunity of the power good output and 4.6 Shutdown Input (SHDN) avoid false triggering of the power good output during The SHDN input is an active-low input signal that turns fast output transients. See Figure4-2 for power good the LDO on and off. The SHDN threshold is a timing characteristics. percentage of the input voltage. The typical value of this shutdown threshold is 30% of V , with minimum IN and maximum limits over the entire operating temperature range of 45% and 15%, respectively.  2006-2013 Microchip Technology Inc. DS22001D-page 17

MCP1827/MCP1827S The SHDN input will ignore low-going pulses (pulses Since the MCP1827/MCP1827S LDO undervoltage meant to shut down the LDO) that are up to 400ns in lockout activates at 2.04V as the input voltage is falling, pulse width. If the shutdown input is pulled low for more the dropout voltage specification does not apply for than 400ns, the LDO will enter Shutdown mode. This output voltages that are less than 1.9V. small bit of filtering helps to reject any system noise For high-current applications, voltage drops across the spikes on the shutdown input signal. PCB traces must be taken into account. The trace On the rising edge of the SHDN input, the shutdown resistances can cause significant voltage drops circuitry has a 30µs delay before allowing the LDO between the input voltage source and the LDO. For output to turn on. This delay helps to reject any false applications with input voltages near 2.3V, these PCB turn-on signals or noise on the SHDN input signal. After trace voltage drops can sometimes lower the input the 30µs delay, the LDO output enters its soft-start voltage enough to trigger a shutdown due to period as it rises from 0V to its final regulation value. If undervoltage lockout. the SHDN input signal is pulled low during the 30µs delay period, the timer will be reset and the delay time 4.8 Overtemperature Protection will start over again on the next rising edge of the SHDN input. The total time from the SHDN input going The MCP1827/MCP1827S LDO has temperature- high (turn-on) to the LDO output being in regulation is sensing circuitry to prevent the junction temperature typically 100µs. See Figure4-4 for a timing diagram of from exceeding approximately 150°C. If the LDO the SHDN input. junction temperature does reach 150°C, the LDO output will be turned off until the junction temperature cools to approximately 140°C, at which point the LDO TOR output will automatically resume normal operation. If 400ns (typ) the internal power dissipation continues to be 70µs 30µs excessive, the device will again shut off. The junction temperature of the die is a function of power SHDN dissipation, ambient temperature and package thermal resistance. See Section5.0 “Application Circuits/ Issues” for more information on LDO power dissipation and junction temperature. VOUT FIGURE 4-4: Shutdown Input Timing Diagram. 4.7 Dropout Voltage and Undervoltage Lockout Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below the nominal value that was measured with a V + 0.6V differential applied. The MCP1827/ R MCP1827S LDO has a very low dropout voltage specification of 330mV (typical) at 1.5A of output current. See Section1.0 “Electrical Characteristics” for maximum dropout voltage specifications. The MCP1827/MCP1827S LDO operates across an input voltage range of 2.3V to 6.0V and incorporates input Undervoltage Lockout (UVLO) circuitry that keeps the LDO output voltage off until the input voltage reaches a minimum of 2.18V (typical) on the rising edge of the input voltage. As the input voltage falls, the LDO output will remain on until the input voltage level reaches 2.04V (typical). DS22001D-page 18  2006-2013 Microchip Technology Inc.

MCP1827/MCP1827S 5.0 APPLICATION CIRCUITS/ In addition to the LDO pass element power dissipation, ISSUES there is power dissipation within the MCP1827/ MCP1827S as a result of quiescent or ground current. The power dissipation as a result of the ground current 5.1 Typical Application can be calculated using the following equation: The MCP1827/MCP1827S is used for applications that EQUATION 5-2: require high LDO output current and a power good output. P = V I IGND INMAX VIN Where: VOUT = 2.5V @ 1.5A P = Power dissipation due to the MCP1827-2.5 I(GND On R1 quiescent current of the LDO Off SHDN 1 2 3 4 5 10k 1C02µF VIN(MAX) = Maximum input voltage I = Current flowing in the V pin VIN VIN IN 3.3V with no LDO output current C1 (LDO quiescent current) 4.7µF GND PWRGD The total power dissipated within the MCP1827/ MCP1827S is the sum of the power dissipated in the FIGURE 5-1: Typical Application Circuit. LDO pass device and the P(I ) term. Because of the GND CMOS construction, the typical I for the MCP1827/ GND 5.1.1 APPLICATION CONDITIONS MCP1827S is 120µA. Operating at a maximum of 3.465V results in a power dissipation of 0.49milli- Package Type = TO-220-5 Watts. For most applications, this is small compared to Input Voltage Range = 3.3V ± 5% the LDO pass device power dissipation and can be VIN maximum = 3.465V neglected. VIN minimum = 3.135V The maximum continuous operating junction V = 0.600V temperature specified for the MCP1827/MCP1827S is DROPOUT (max) V (typical) = 2.5V +125°C. To estimate the internal junction temperature OUT of the MCP1827/MCP1827S, the total internal power I = 1.5A maximum OUT dissipation is multiplied by the thermal resistance from PDISS (typical) = 1.2W junction to ambient (RJA) of the device. The thermal Temperature Rise = 35.2°C resistance from junction to ambient for the TO-220-5 package is estimated at 29.3°C/W. 5.2 Power Calculations EQUATION 5-3: 5.2.1 POWER DISSIPATION T = P R +T JMAX TOTAL JA AMAX The internal power dissipation within the MCP1827/ T = Maximum continuous junction MCP1827S is a function of input voltage, output J(MAX) temperature voltage, output current and quiescent current. Equation5-1 can be used to calculate the internal P = Total device power dissipation TOTAL power dissipation for the LDO. R = Thermal resistance from junction to JA ambient EQUATION 5-1: T = Maximum ambient temperature A(MAX) P = V –V I LDO INMAX OUTMIN OUTMAX Where: P = LDO Pass device internal LDO power dissipation V = Maximum input voltage IN(MAX) V = LDO minimum output voltage OUT(MIN)  2006-2013 Microchip Technology Inc. DS22001D-page 19

MCP1827/MCP1827S The maximum power dissipation capability for a 5.3 Typical Application package can be calculated given the junction-to- ambient thermal resistance and the maximum ambient Internal power dissipation, junction temperature rise, temperature for the application. Equation5-4 can be junction temperature and maximum power dissipation used to determine the package maximum internal is calculated in the following example. The power power dissipation. dissipation as a result of ground current is small enough to be neglected. EQUATION 5-4: 5.3.1 POWER DISSIPATION EXAMPLE T –T  P = -------J----M----A---X---------------A-----M----A---X------ DMAX R Package JA Package Type = TO-220-5 P = Maximum device power dissipation D(MAX) Input Voltage T = maximum continuous junction J(MAX) V = 3.3V ± 5% temperature IN LDO Output Voltage and Current T = maximum ambient temperature A(MAX) V = 2.5V R = Thermal resistance from junction to OUT JA I = 1.5A ambient OUT Maximum Ambient Temperature T = 60°C EQUATION 5-5: A(MAX) Internal Power Dissipation T = P R JRISE DMAX JA P = (V – V ) x I LDO(MAX) IN(MAX) OUT(MIN) OUT(MAX) TJ(RISE) = Rise in device junction temperature PLDO = ((3.3V x 1.05) – (2.5V x 0.975)) over the ambient temperature x 1.5A PD(MAX) = Maximum device power dissipation PLDO = 1.54 Watts R = Thermal resistance from junction to JA 5.3.1.1 Device Junction Temperature Rise ambient The internal junction temperature rise is a function of internal power dissipation and the thermal resistance EQUATION 5-6: from junction-to-ambient for the application. The thermal resistance from junction-to-ambient (R ) is T = T +T JA J JRISE A derived from EIA/JEDEC standards for measuring thermal resistance. The EIA/JEDEC specification is T = Junction temperature J JESD51. The standard describes the test method and TJ(RISE) = Rise in device junction temperature board specifications for measuring the thermal over the ambient temperature resistance from junction to ambient. The actual thermal T = Ambient temperature resistance for a particular application can vary A depending on many factors such as copper area and thickness. Refer to AN792, “A Method to Determine How Much Power a SOT23 Can Dissipate in an Application” (DS00792), for more information regarding this subject. T = P x R J(RISE) TOTAL JA TJ(RISE) = 1.54 W x 29.3° C/W TJ(RISE) = 45.12°C DS22001D-page 20  2006-2013 Microchip Technology Inc.

MCP1827/MCP1827S 5.3.1.2 Junction Temperature Estimate To estimate the internal junction temperature, the calculated temperature rise is added to the ambient or offset temperature. For this example, the worst-case junction temperature is estimated below: T = T + T J J(RISE) A(MAX) T = 45.12°C + 60.0°C J T = 105.12°C J As you can see from the result, this application will be operating within the maximum operating junction temperature of 125°C. 5.3.1.3 Maximum Package Power Dissipation at 60°C Ambient Temperature TO-220-5 (29.3° C/W R ): JA P = (125°C – 60°C) / 29.3° C/W D(MAX) P = 2.218W D(MAX) DDPAK-5 (31.2°C/Watt R ): JA P = (125°C – 60°C)/ 31.2° C/W D(MAX) P = 2.083W D(MAX) From this table you can see the difference in maximum allowable power dissipation between the TO-220-5 package and the DDPAK-5 package.  2006-2013 Microchip Technology Inc. DS22001D-page 21

MCP1827/MCP1827S 6.0 PACKAGING INFORMATION 6.1 Package Marking Information 3-Lead DDPAK (MCP1827S) Example: XXXXXXXXX MCP1827S XXXXXXXXX 0.8EEB^e^3 YYWWNNN 0630256 1 2 3 1 2 3 3-Lead TO-220 (MCP1827S) Example: XXXXXXXXX MCP1827S XXXXXXXXX 12EAB^e^3 YYWWNNN 0630256 1 2 3 1 2 3 5-Lead DDPAK (Fixed) (MCP1827) Example: XXXXXXXXX MCP1827 XXXXXXXXX 1.0EET^e^3 YYWWNNN 0630256 1 2 3 4 5 1 2 3 4 5 5-Lead TO-220 (Adj) (MCP1827) Example: XXXXXXXXX MCP1827 XXXXXXXXX 08EAT^e^3 YYWWNNN 0630256 1 2 3 4 5 1 2 3 4 5 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. DS22001D-page 22  2006-2013 Microchip Technology Inc.

MCP1827/MCP1827S (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:17)(cid:18)(cid:8)(cid:19)(cid:20)(cid:20)(cid:9)(cid:21)(cid:22)(cid:23) (cid:24)(cid:25)(cid:12)(cid:5)(cid:26) 0(cid:10)(cid:9)(cid:2) (cid:11)(cid:14)(cid:2)#(cid:10)" (cid:2)(cid:8)&(cid:9)(cid:9)(cid:14)(cid:15) (cid:2)(cid:12)(cid:28)(cid:8)1(cid:28)(cid:17)(cid:14)(cid:2)$(cid:9)(cid:28)/(cid:7)(cid:15)(cid:17)"2(cid:2)(cid:12)(cid:16)(cid:14)(cid:28)"(cid:14)(cid:2)"(cid:14)(cid:14)(cid:2) (cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)3(cid:28)(cid:8)1(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)(cid:31)(cid:7)(cid:8)(cid:28) (cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28) (cid:14)$(cid:2)(cid:28) (cid:2) (cid:11) (cid:12)-44///(cid:20)#(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)#4(cid:12)(cid:28)(cid:8)1(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) E E1 L1 D1 D H 1 N b e BOTTOMVIEW TOPVIEW b1 CHAMFER OPTIONAL A C2 φ A1 c L 5(cid:15)(cid:7) " (cid:19)6!7%(cid:22) (cid:21)(cid:7)#(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:2)8(cid:7)#(cid:7) " (cid:6)(cid:19)6 69(cid:6) (cid:6)(cid:25): 6&#;(cid:14)(cid:9)(cid:2)(cid:10)(cid:31)(cid:2)3(cid:7)(cid:15)" 6 * 3(cid:7) (cid:8)(cid:11) (cid:14) (cid:20)(cid:29)(cid:4)(cid:4)(cid:2),(cid:22)! 9.(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)7(cid:14)(cid:7)(cid:17)(cid:11) (cid:25) (cid:20)(cid:29)<(cid:4) = (cid:20)(cid:29)(cid:24)(cid:4) (cid:22) (cid:28)(cid:15)$(cid:10)(cid:31)(cid:31)(cid:2)(cid:2)(cid:30) (cid:25)(cid:29) (cid:20)(cid:4)(cid:4)(cid:4) = (cid:20)(cid:4)(cid:29)(cid:4) 9.(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)$ (cid:11) % (cid:20)*?(cid:4) = (cid:20)(cid:23)(cid:3)(cid:4) %’(cid:12)(cid:10)"(cid:14)$(cid:2)3(cid:28)$(cid:2)>(cid:7)$ (cid:11) %(cid:29) (cid:20)(cid:3)(cid:23)( = = (cid:6)(cid:10)(cid:16)$(cid:14)$(cid:2)3(cid:28)(cid:8)1(cid:28)(cid:17)(cid:14)(cid:2)8(cid:14)(cid:15)(cid:17) (cid:11) (cid:21) (cid:20)**(cid:4) = (cid:20)*?(cid:4) 9.(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:15)(cid:17) (cid:11) 7 (cid:20)((cid:23)(cid:24) = (cid:20)<(cid:3)( %’(cid:12)(cid:10)"(cid:14)$(cid:2)3(cid:28)$(cid:2)8(cid:14)(cid:15)(cid:17) (cid:11) (cid:21)(cid:29) (cid:20)(cid:3)(cid:5)(cid:4) = = 8(cid:14)(cid:28)$(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)1(cid:15)(cid:14)"" (cid:8) (cid:20)(cid:4)(cid:29)(cid:23) = (cid:20)(cid:4)(cid:3)(cid:24) 3(cid:28)$(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)1(cid:15)(cid:14)"" !(cid:3) (cid:20)(cid:4)(cid:23)( = (cid:20)(cid:4)<( 8(cid:10)/(cid:14)(cid:9)(cid:2)8(cid:14)(cid:28)$(cid:2)>(cid:7)$ (cid:11) ; (cid:20)(cid:4)(cid:3)(cid:4) = (cid:20)(cid:4)*(cid:24) 5(cid:12)(cid:12)(cid:14)(cid:9)(cid:2)8(cid:14)(cid:28)$(cid:2)>(cid:7)$ (cid:11) ;(cid:29) (cid:20)(cid:4)(cid:23)( = (cid:20)(cid:4)(cid:5)(cid:4) 0(cid:10)(cid:10) (cid:2)8(cid:14)(cid:15)(cid:17) (cid:11) 8 (cid:20)(cid:4)<? = (cid:20)(cid:29)(cid:29)(cid:4) 3(cid:28)$(cid:2)8(cid:14)(cid:15)(cid:17) (cid:11) 8(cid:29) = = (cid:20)(cid:4)<(cid:5) 0(cid:10)(cid:10) (cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)@ = ?@ (cid:24)(cid:25)(cid:12)(cid:5)(cid:11)(cid:26) (cid:29)(cid:20) (cid:30)(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)(cid:31)(cid:7)(cid:8)(cid:28)(cid:15) (cid:2)!(cid:11)(cid:28)(cid:9)(cid:28)(cid:8) (cid:14)(cid:9)(cid:7)" (cid:7)(cid:8)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7)#(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)"(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)$(cid:2)%(cid:2)$(cid:10)(cid:2)(cid:15)(cid:10) (cid:2)(cid:7)(cid:15)(cid:8)(cid:16)&$(cid:14)(cid:2)#(cid:10)(cid:16)$(cid:2)(cid:31)(cid:16)(cid:28)"(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10) (cid:9)&"(cid:7)(cid:10)(cid:15)"(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)$(cid:2)(cid:31)(cid:16)(cid:28)"(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10) (cid:9)&"(cid:7)(cid:10)(cid:15)"(cid:2)"(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10) (cid:2)(cid:14)’(cid:8)(cid:14)(cid:14)$(cid:2)(cid:20)(cid:4)(cid:4)()(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)"(cid:7)$(cid:14)(cid:20) *(cid:20) (cid:21)(cid:7)#(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)$(cid:2) (cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6)%(cid:2)+(cid:29)(cid:23)(cid:20)((cid:6)(cid:20) ,(cid:22)!- ,(cid:28)"(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)#(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14) (cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)’(cid:28)(cid:8) (cid:2).(cid:28)(cid:16)&(cid:14)(cid:2)"(cid:11)(cid:10)/(cid:15)(cid:2)/(cid:7) (cid:11)(cid:10)& (cid:2) (cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)"(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)/(cid:7)(cid:15)(cid:17)!(cid:4)(cid:23)(cid:27)(cid:4)(cid:29)(cid:29),  2006-2013 Microchip Technology Inc. DS22001D-page 23

MCP1827/MCP1827S Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22001D-page 24  2006-2013 Microchip Technology Inc.

MCP1827/MCP1827S (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:27)(cid:28)(cid:6)(cid:29)(cid:11)(cid:13)(cid:11)(cid:12)(cid:25)(cid:28)(cid:8)(cid:30)(cid:31)(cid:12)(cid:10)(cid:13)(cid:29)(cid:5)(cid:8)(cid:15)(cid:21)(cid:17)(cid:18)(cid:8)(cid:19)(cid:27)(cid:30)(cid:3) !(cid:23) (cid:24)(cid:25)(cid:12)(cid:5)(cid:26) 0(cid:10)(cid:9)(cid:2) (cid:11)(cid:14)(cid:2)#(cid:10)" (cid:2)(cid:8)&(cid:9)(cid:9)(cid:14)(cid:15) (cid:2)(cid:12)(cid:28)(cid:8)1(cid:28)(cid:17)(cid:14)(cid:2)$(cid:9)(cid:28)/(cid:7)(cid:15)(cid:17)"2(cid:2)(cid:12)(cid:16)(cid:14)(cid:28)"(cid:14)(cid:2)"(cid:14)(cid:14)(cid:2) (cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)3(cid:28)(cid:8)1(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)(cid:31)(cid:7)(cid:8)(cid:28) (cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28) (cid:14)$(cid:2)(cid:28) (cid:2) (cid:11) (cid:12)-44///(cid:20)#(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)#4(cid:12)(cid:28)(cid:8)1(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) E CHAMFER A OPTIONAL φP A1 Q H1 D D1 L1 L b2 1 2 N b c e A2 e1 5(cid:15)(cid:7) " (cid:19)6!7%(cid:22) (cid:21)(cid:7)#(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:2)8(cid:7)#(cid:7) " (cid:6)(cid:19)6 69(cid:6) (cid:6)(cid:25): 6&#;(cid:14)(cid:9)(cid:2)(cid:10)(cid:31)(cid:2)3(cid:7)(cid:15)" 6 * 3(cid:7) (cid:8)(cid:11) (cid:14) (cid:20)(cid:29)(cid:4)(cid:4)(cid:2),(cid:22)! 9.(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)3(cid:7)(cid:15)(cid:2)3(cid:7) (cid:8)(cid:11) (cid:14)(cid:29) (cid:20)(cid:3)(cid:4)(cid:4)(cid:2),(cid:22)! 9.(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)7(cid:14)(cid:7)(cid:17)(cid:11) (cid:25) (cid:20)(cid:29)(cid:23)(cid:4) = (cid:20)(cid:29)(cid:24)(cid:4) (cid:13)(cid:28);(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)1(cid:15)(cid:14)"" (cid:25)(cid:29) (cid:20)(cid:4)(cid:3)(cid:4) = (cid:20)(cid:4)(( ,(cid:28)"(cid:14)(cid:2) (cid:10)(cid:2)8(cid:14)(cid:28)$ (cid:25)(cid:3) (cid:20)(cid:4)?(cid:4) = (cid:20)(cid:29)(cid:29)( 9.(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)$ (cid:11) % (cid:20)*((cid:5) = (cid:20)(cid:23)(cid:3)(cid:4) (cid:6)(cid:10)&(cid:15) (cid:7)(cid:15)(cid:17)(cid:2)7(cid:10)(cid:16)(cid:14)(cid:2)!(cid:14)(cid:15) (cid:14)(cid:9) A (cid:20)(cid:29)(cid:4)(cid:4) = (cid:20)(cid:29)(cid:3)(cid:4) 9.(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:15)(cid:17) (cid:11) (cid:21) (cid:20)(<(cid:4) = (cid:20)<((cid:4) (cid:6)(cid:10)(cid:16)$(cid:14)$(cid:2)3(cid:28)(cid:8)1(cid:28)(cid:17)(cid:14)(cid:2)8(cid:14)(cid:15)(cid:17) (cid:11) (cid:21)(cid:29) (cid:20)**(cid:4) = (cid:20)*(( (cid:13)(cid:28);(cid:2)8(cid:14)(cid:15)(cid:17) (cid:11) 7(cid:29) (cid:20)(cid:3)*(cid:4) = (cid:20)(cid:3)(cid:5)(cid:4) (cid:6)(cid:10)&(cid:15) (cid:7)(cid:15)(cid:17)(cid:2)7(cid:10)(cid:16)(cid:14)(cid:2)(cid:21)(cid:7)(cid:28)#(cid:14) (cid:14)(cid:9) (cid:3)3 (cid:20)(cid:29)*(cid:24) = (cid:20)(cid:29)(< 8(cid:14)(cid:28)$(cid:2)8(cid:14)(cid:15)(cid:17) (cid:11) 8 (cid:20)((cid:4)(cid:4) = (cid:20)(?(cid:4) 8(cid:14)(cid:28)$(cid:2)(cid:22)(cid:11)(cid:10)&(cid:16)$(cid:14)(cid:9) 8(cid:29) = = (cid:20)(cid:3)((cid:4) 8(cid:14)(cid:28)$(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)1(cid:15)(cid:14)"" (cid:8) (cid:20)(cid:4)(cid:29)(cid:3) = (cid:20)(cid:4)(cid:3)(cid:23) 8(cid:14)(cid:28)$(cid:2)>(cid:7)$ (cid:11) ; (cid:20)(cid:4)(cid:29)( (cid:20)(cid:4)(cid:3)(cid:5) (cid:20)(cid:4)(cid:23)(cid:4) (cid:22)(cid:11)(cid:10)&(cid:16)$(cid:14)(cid:9)(cid:2)>(cid:7)$ (cid:11) ;(cid:3) (cid:20)(cid:4)(cid:23)( (cid:20)(cid:4)((cid:5) (cid:20)(cid:4)(cid:5)(cid:4) (cid:24)(cid:25)(cid:12)(cid:5)(cid:11)(cid:26) (cid:29)(cid:20) (cid:21)(cid:7)#(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)"(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)$(cid:2)%(cid:2)$(cid:10)(cid:2)(cid:15)(cid:10) (cid:2)(cid:7)(cid:15)(cid:8)(cid:16)&$(cid:14)(cid:2)#(cid:10)(cid:16)$(cid:2)(cid:31)(cid:16)(cid:28)"(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10) (cid:9)&"(cid:7)(cid:10)(cid:15)"(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)$(cid:2)(cid:31)(cid:16)(cid:28)"(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10) (cid:9)&"(cid:7)(cid:10)(cid:15)"(cid:2)"(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10) (cid:2)(cid:14)’(cid:8)(cid:14)(cid:14)$(cid:2)(cid:20)(cid:4)(cid:4)()(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)"(cid:7)$(cid:14)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7)#(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)$(cid:2) (cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6)%(cid:2)+(cid:29)(cid:23)(cid:20)((cid:6)(cid:20) ,(cid:22)!- ,(cid:28)"(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)#(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14) (cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)’(cid:28)(cid:8) (cid:2).(cid:28)(cid:16)&(cid:14)(cid:2)"(cid:11)(cid:10)/(cid:15)(cid:2)/(cid:7) (cid:11)(cid:10)& (cid:2) (cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)"(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)/(cid:7)(cid:15)(cid:17)!(cid:4)(cid:23)(cid:27)(cid:4)*(cid:23),  2006-2013 Microchip Technology Inc. DS22001D-page 25

MCP1827/MCP1827S "(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:27)(cid:18)(cid:8)(cid:19)(cid:20)(cid:20)(cid:9)(cid:21)(cid:22)(cid:23) (cid:24)(cid:25)(cid:12)(cid:5)(cid:26) 0(cid:10)(cid:9)(cid:2) (cid:11)(cid:14)(cid:2)#(cid:10)" (cid:2)(cid:8)&(cid:9)(cid:9)(cid:14)(cid:15) (cid:2)(cid:12)(cid:28)(cid:8)1(cid:28)(cid:17)(cid:14)(cid:2)$(cid:9)(cid:28)/(cid:7)(cid:15)(cid:17)"2(cid:2)(cid:12)(cid:16)(cid:14)(cid:28)"(cid:14)(cid:2)"(cid:14)(cid:14)(cid:2) (cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)3(cid:28)(cid:8)1(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)(cid:31)(cid:7)(cid:8)(cid:28) (cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28) (cid:14)$(cid:2)(cid:28) (cid:2) (cid:11) (cid:12)-44///(cid:20)#(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)#4(cid:12)(cid:28)(cid:8)1(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) E E1 L1 D1 D H 1 N b e BOTTOMVIEW TOPVIEW CHAMFER OPTIONAL A C2 φ A1 c L 5(cid:15)(cid:7) " (cid:19)6!7%(cid:22) (cid:21)(cid:7)#(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:2)8(cid:7)#(cid:7) " (cid:6)(cid:19)6 69(cid:6) (cid:6)(cid:25): 6&#;(cid:14)(cid:9)(cid:2)(cid:10)(cid:31)(cid:2)3(cid:7)(cid:15)" 6 ( 3(cid:7) (cid:8)(cid:11) (cid:14) (cid:20)(cid:4)<(cid:5)(cid:2),(cid:22)! 9.(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)7(cid:14)(cid:7)(cid:17)(cid:11) (cid:25) (cid:20)(cid:29)<(cid:4) = (cid:20)(cid:29)(cid:24)(cid:4) (cid:22) (cid:28)(cid:15)$(cid:10)(cid:31)(cid:31)(cid:2)(cid:2)(cid:30) (cid:25)(cid:29) (cid:20)(cid:4)(cid:4)(cid:4) = (cid:20)(cid:4)(cid:29)(cid:4) 9.(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)$ (cid:11) % (cid:20)*?(cid:4) = (cid:20)(cid:23)(cid:3)(cid:4) %’(cid:12)(cid:10)"(cid:14)$(cid:2)3(cid:28)$(cid:2)>(cid:7)$ (cid:11) %(cid:29) (cid:20)(cid:3)(cid:23)( = = (cid:6)(cid:10)(cid:16)$(cid:14)$(cid:2)3(cid:28)(cid:8)1(cid:28)(cid:17)(cid:14)(cid:2)8(cid:14)(cid:15)(cid:17) (cid:11) (cid:21) (cid:20)**(cid:4) = (cid:20)*?(cid:4) 9.(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:15)(cid:17) (cid:11) 7 (cid:20)((cid:23)(cid:24) = (cid:20)<(cid:3)( %’(cid:12)(cid:10)"(cid:14)$(cid:2)3(cid:28)$(cid:2)8(cid:14)(cid:15)(cid:17) (cid:11) (cid:21)(cid:29) (cid:20)(cid:3)(cid:5)(cid:4) = = 8(cid:14)(cid:28)$(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)1(cid:15)(cid:14)"" (cid:8) (cid:20)(cid:4)(cid:29)(cid:23) = (cid:20)(cid:4)(cid:3)(cid:24) 3(cid:28)$(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)1(cid:15)(cid:14)"" !(cid:3) (cid:20)(cid:4)(cid:23)( = (cid:20)(cid:4)<( 8(cid:14)(cid:28)$(cid:2)>(cid:7)$ (cid:11) ; (cid:20)(cid:4)(cid:3)(cid:4) = (cid:20)(cid:4)*(cid:24) 0(cid:10)(cid:10) (cid:2)8(cid:14)(cid:15)(cid:17) (cid:11) 8 (cid:20)(cid:4)<? = (cid:20)(cid:29)(cid:29)(cid:4) 3(cid:28)$(cid:2)8(cid:14)(cid:15)(cid:17) (cid:11) 8(cid:29) = = (cid:20)(cid:4)<(cid:5) 0(cid:10)(cid:10) (cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)@ = ?@ (cid:24)(cid:25)(cid:12)(cid:5)(cid:11)(cid:26) (cid:29)(cid:20) (cid:30)(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)(cid:31)(cid:7)(cid:8)(cid:28)(cid:15) (cid:2)!(cid:11)(cid:28)(cid:9)(cid:28)(cid:8) (cid:14)(cid:9)(cid:7)" (cid:7)(cid:8)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7)#(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)"(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)$(cid:2)%(cid:2)$(cid:10)(cid:2)(cid:15)(cid:10) (cid:2)(cid:7)(cid:15)(cid:8)(cid:16)&$(cid:14)(cid:2)#(cid:10)(cid:16)$(cid:2)(cid:31)(cid:16)(cid:28)"(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10) (cid:9)&"(cid:7)(cid:10)(cid:15)"(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)$(cid:2)(cid:31)(cid:16)(cid:28)"(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10) (cid:9)&"(cid:7)(cid:10)(cid:15)"(cid:2)"(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10) (cid:2)(cid:14)’(cid:8)(cid:14)(cid:14)$(cid:2)(cid:20)(cid:4)(cid:4)()(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)"(cid:7)$(cid:14)(cid:20) *(cid:20) (cid:21)(cid:7)#(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)$(cid:2) (cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6)%(cid:2)+(cid:29)(cid:23)(cid:20)((cid:6)(cid:20) ,(cid:22)!- ,(cid:28)"(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)#(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14) (cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)’(cid:28)(cid:8) (cid:2).(cid:28)(cid:16)&(cid:14)(cid:2)"(cid:11)(cid:10)/(cid:15)(cid:2)/(cid:7) (cid:11)(cid:10)& (cid:2) (cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)"(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)/(cid:7)(cid:15)(cid:17)!(cid:4)(cid:23)(cid:27)(cid:4)(cid:29)(cid:3), DS22001D-page 26  2006-2013 Microchip Technology Inc.

MCP1827/MCP1827S Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2006-2013 Microchip Technology Inc. DS22001D-page 27

MCP1827/MCP1827S "(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:27)(cid:28)(cid:6)(cid:29)(cid:11)(cid:13)(cid:11)(cid:12)(cid:25)(cid:28)(cid:8)(cid:30)(cid:31)(cid:12)(cid:10)(cid:13)(cid:29)(cid:5)(cid:8)(cid:15)(cid:21)(cid:27)(cid:18)(cid:8)(cid:19)(cid:27)(cid:30)(cid:3) !(cid:23) (cid:24)(cid:25)(cid:12)(cid:5)(cid:26) 0(cid:10)(cid:9)(cid:2) (cid:11)(cid:14)(cid:2)#(cid:10)" (cid:2)(cid:8)&(cid:9)(cid:9)(cid:14)(cid:15) (cid:2)(cid:12)(cid:28)(cid:8)1(cid:28)(cid:17)(cid:14)(cid:2)$(cid:9)(cid:28)/(cid:7)(cid:15)(cid:17)"2(cid:2)(cid:12)(cid:16)(cid:14)(cid:28)"(cid:14)(cid:2)"(cid:14)(cid:14)(cid:2) (cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)3(cid:28)(cid:8)1(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)(cid:31)(cid:7)(cid:8)(cid:28) (cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28) (cid:14)$(cid:2)(cid:28) (cid:2) (cid:11) (cid:12)-44///(cid:20)#(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)#4(cid:12)(cid:28)(cid:8)1(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) E A φP CHAMFER A1 OPTIONAL Q H1 D D1 L 1 2 3 N b e c e1 A2 5(cid:15)(cid:7) " (cid:19)6!7%(cid:22) (cid:21)(cid:7)#(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:2)8(cid:7)#(cid:7) " (cid:6)(cid:19)6 69(cid:6) (cid:6)(cid:25): 6&#;(cid:14)(cid:9)(cid:2)(cid:10)(cid:31)(cid:2)3(cid:7)(cid:15)" 6 ( 3(cid:7) (cid:8)(cid:11) (cid:14) (cid:20)(cid:4)<(cid:5)(cid:2),(cid:22)! 9.(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)3(cid:7)(cid:15)(cid:2)3(cid:7) (cid:8)(cid:11) (cid:14)(cid:29) (cid:20)(cid:3)<?(cid:2),(cid:22)! 9.(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)7(cid:14)(cid:7)(cid:17)(cid:11) (cid:25) (cid:20)(cid:29)(cid:23)(cid:4) = (cid:20)(cid:29)(cid:24)(cid:4) 9.(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)$ (cid:11) % (cid:20)*?(cid:4) = (cid:20)(cid:23)(cid:3)(cid:4) 9.(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:15)(cid:17) (cid:11) (cid:21) (cid:20)(<(cid:4) = (cid:20)<((cid:4) (cid:6)(cid:10)(cid:16)$(cid:14)$(cid:2)3(cid:28)(cid:8)1(cid:28)(cid:17)(cid:14)(cid:2)8(cid:14)(cid:15)(cid:17) (cid:11) (cid:21)(cid:29) (cid:20)**(cid:4) = (cid:20)*(( (cid:13)(cid:28);(cid:2)8(cid:14)(cid:15)(cid:17) (cid:11) 7(cid:29) (cid:20)(cid:3)(cid:4)(cid:23) = (cid:20)(cid:3)(cid:24)* (cid:13)(cid:28);(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)1(cid:15)(cid:14)"" (cid:25)(cid:29) (cid:20)(cid:4)(cid:3)(cid:4) = (cid:20)(cid:4)(( (cid:6)(cid:10)&(cid:15) (cid:7)(cid:15)(cid:17)(cid:2)7(cid:10)(cid:16)(cid:14)(cid:2)!(cid:14)(cid:15) (cid:14)(cid:9) A (cid:20)(cid:29)(cid:4)(cid:4) = (cid:20)(cid:29)(cid:3)(cid:4) (cid:6)(cid:10)&(cid:15) (cid:7)(cid:15)(cid:17)(cid:2)7(cid:10)(cid:16)(cid:14)(cid:2)(cid:21)(cid:7)(cid:28)#(cid:14) (cid:14)(cid:9) (cid:3)3 (cid:20)(cid:29)*(cid:24) = (cid:20)(cid:29)(< 8(cid:14)(cid:28)$(cid:2)8(cid:14)(cid:15)(cid:17) (cid:11) 8 (cid:20)(cid:23)?(cid:3) = (cid:20)((cid:24)(cid:4) ,(cid:28)"(cid:14)(cid:2) (cid:10)(cid:2),(cid:10) (cid:10)#(cid:2)(cid:10)(cid:31)(cid:2)8(cid:14)(cid:28)$ (cid:25)(cid:3) (cid:20)(cid:4)?(cid:4) = (cid:20)(cid:29)(cid:29)( 8(cid:14)(cid:28)$(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)1(cid:15)(cid:14)"" (cid:8) (cid:20)(cid:4)(cid:29)(cid:3) = (cid:20)(cid:4)(cid:3)( 8(cid:14)(cid:28)$(cid:2)>(cid:7)$ (cid:11) ; (cid:20)(cid:4)(cid:29)( (cid:20)(cid:4)(cid:3)(cid:5) (cid:20)(cid:4)(cid:23)(cid:4) (cid:24)(cid:25)(cid:12)(cid:5)(cid:11)(cid:26) (cid:29)(cid:20) (cid:21)(cid:7)#(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)"(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)$(cid:2)%(cid:2)$(cid:10)(cid:2)(cid:15)(cid:10) (cid:2)(cid:7)(cid:15)(cid:8)(cid:16)&$(cid:14)(cid:2)#(cid:10)(cid:16)$(cid:2)(cid:31)(cid:16)(cid:28)"(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10) (cid:9)&"(cid:7)(cid:10)(cid:15)"(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)$(cid:2)(cid:31)(cid:16)(cid:28)"(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10) (cid:9)&"(cid:7)(cid:10)(cid:15)"(cid:2)"(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10) (cid:2)(cid:14)’(cid:8)(cid:14)(cid:14)$(cid:2)(cid:20)(cid:4)(cid:4)()(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)"(cid:7)$(cid:14)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7)#(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)$(cid:2) (cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6)%(cid:2)+(cid:29)(cid:23)(cid:20)((cid:6)(cid:20) ,(cid:22)!- ,(cid:28)"(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)#(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14) (cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)’(cid:28)(cid:8) (cid:2).(cid:28)(cid:16)&(cid:14)(cid:2)"(cid:11)(cid:10)/(cid:15)(cid:2)/(cid:7) (cid:11)(cid:10)& (cid:2) (cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)"(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)/(cid:7)(cid:15)(cid:17)!(cid:4)(cid:23)(cid:27)(cid:4)*<, DS22001D-page 28  2006-2013 Microchip Technology Inc.

MCP1827/MCP1827S APPENDIX A: REVISION HISTORY Revision D (March 2013) The following is the list of modifications: • Updated the value of V in DROPOUT(max) Section5.1 “Typical Application”. • Updated the 5-lead DDPAK (MCP1827) informa- tion in the Product Identification Systemsection. Revision C (February 2007) • Figure2-22: Revised label on Y-axis. • Section2.0 “Typical Performance Curves”: Added note on Junction Temperature. • Pages 9-14: Revised notes. Revision B (September 2006) • Correction to maximum Dropout Voltage in Section 1.0. • Added additional graphs in Section 2.0. • Added disclaimer to package outline drawings. Revision A (July 2006) • Original Release of this Document.  2006-2013 Microchip Technology Inc. DS22001D-page 29

MCP1827/MCP1827S NOTES: DS22001D-page 30  2006-2013 Microchip Technology Inc.

MCP1827/MCP1827S PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. XX X X X/ XX Examples: a) MCP1827-0802E/AT: 0.8V LDO Regulator Device Output Feature Tolerance Temp. Package 5LD TO-220 Voltage Code b) MCP1827-1002E/ET: 1.0V LDO Regulator 5LD DDPAK c) MCP1827-1202E/AT: 1.2V LDO Regulator Device: MCP1827: 1.5A Low Dropout Regulator 5LD TO-220 MCP1827T: 1.5A Low Dropout Regulator Tape and Reel d) MCP1827-1802E/AT: 1.8V LDO Regulator MCP1827S: 1.5A Low Dropout Regulator 5LD TO-220 MCP1827ST:1.5A Low Dropout Regulator e) MCP1827-2502E/ET: 2.5V LDO Regulator Tape and Reel 5LD DDPAK f) MCP1827-3002E/ET: 3.0V LDO Regulator Output Voltage *: 08 = 0.8V “Standard” 5LD DDPAK 12 = 1.2V “Standard” g) MCP1827-3302E/AT 3.3V LDO Regulator 18 = 1.8V “Standard” 5LD TO-220 25 = 2.5V “Standard” 30 = 3.0V “Standard” h) MCP1827-5002E/ET: 5.0V LDO Regulator 33 = 3.3V “Standard” 5LD DDPAK 50 = 5.0V “Standard” i) MCP1827-ADJE/AT: ADJ LDO Regulator *Contact factory for other output voltage options 5LD TO-220 Extra Feature Code: 0 = Fixed j) MCP1827-ADJE/ET ADJ LDO Regulator 5LD DDPAK Tolerance: 2 = 2.0% (Standard) a) MCP1827S-0802E/EB:0.8V LDO Regulator 3LD DDPAK Temperature: E = -40C to +125C b) MCP1827S-0802E/AB:0.8V LDO Regulator 3LD TO-220 Package Type: AB = Plastic Transistor Outline, TO-220, 3-lead c) MCP1827S-1002E/EB:1.0V LDO Regulator AT = Plastic Transistor Outline, TO-220, 5-lead 3LD DDPAK EB = Plastic, DDPAK, 3-lead d) MCP1827S-1202E/AB1.2V LDO Regulator ET = Plastic, DDPAK, 5-lead 3LD TO-220 e) MCP1827S-1802E/EB1.8V LDO Regulator 3LD DDPAK f) MCP1827S-2502E/EB2.5V LDO Regulator 3LD DDPAK g) MCP1827S-2502E/EB3.0V LDO Regulator 3LD DDPAK h) MCP1827S-3302E/AB3.3V LDO Regulator 3LD TO-220 i) MCP1827S-5002E/EB5.0V LDO Regulator 3LD DDPAK  2006-2013 Microchip Technology Inc. DS22001D-page 31

MCP1827/MCP1827S NOTES: DS22001D-page 32  2006-2013 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, ensure that your application meets with your specifications. PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash MICROCHIP MAKES NO REPRESENTATIONS OR and UNI/O are registered trademarks of Microchip Technology WARRANTIES OF ANY KIND WHETHER EXPRESS OR Incorporated in the U.S.A. and other countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MTP, SEEVAL and The Embedded Control Solutions QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Silicon Storage Technology is a registered trademark of devices in life support and/or safety applications is entirely at Microchip Technology Inc. in other countries. the buyer’s risk, and the buyer agrees to defend, indemnify and Analog-for-the-Digital Age, Application Maestro, BodyCom, hold harmless Microchip from any and all damages, claims, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, suits, or expenses resulting from such use. No licenses are dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, conveyed, implicitly or otherwise, under any Microchip ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial intellectual property rights. Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2006-2013, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 9781620770412 QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures == ISO/TS 16949 == are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2006-2013 Microchip Technology Inc. DS22001D-page 33

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