MCP1826/MCP1826S 1000 mA, Low-Voltage, Low Quiescent Current LDO Regulator Features: Description: • 1000mA Output Current Capability The MCP1826/MCP1826S is a 1000mA Low Dropout • Input Operating Voltage Range: 2.3V to 6.0V (LDO) linear regulator that provides high-current and low-output voltages. The MCP1826 comes in a fixed or • Adjustable Output Voltage Range: 0.8V to 5.0V adjustable output voltage version, with an output (MCP1826 only) voltage range of 0.8V to 5.0V. The 1000mA output cur- • Standard Fixed Output Voltages: rent capability, combined with the low-output voltage - 0.8V, 1.2V, 1.8V, 2.5V, 3.0V, 3.3V, 5.0V capability, make the MCP1826 a good choice for new • Other Fixed Output Voltage Options Available sub-1.8V output voltage LDO applications that have Upon Request high current demands. The MCP1826S is a 3-pin fixed • Low Dropout Voltage: 250mV Typical at 1000mA voltage version. • Typical Output Voltage Tolerance: 0.5% The MCP1826/MCP1826S is stable using ceramic • Stable with 1.0µF Ceramic Output Capacitor output capacitors that inherently provide lower output • Fast Response to Load Transients noise and reduce the size and cost of the entire regulator solution. Only 1µF of output capacitance is • Low Supply Current: 120µA (typ) needed to stabilize the LDO. • Low Shutdown Supply Current: 0.1µA (typ) (MCP1826 only) Using CMOS construction, the quiescent current consumed by the MCP1826/MCP1826S is typically • Fixed Delay on Power Good Output less than 120µA over the entire input voltage range, (MCP1826 only) making it attractive for portable computing applications • Short Circuit Current Limiting and that demand high-output current. The MCP1826 Overtemperature Protection versions have a Shutdown (SHDN) pin. When shut • TO-263-5 (DDPAK-5), TO-220-5, SOT-223-5 down, the quiescent current is reduced to less than Package Options (MCP1826). 0.1µA. • TO-263-3 (DDPAK-3), TO-220-3, SOT-223-3 On the MCP1826 fixed output versions the scaled- Package Options (MCP1826S). down output voltage is internally monitored and a power good (PWRGD) output is provided when the Applications: output is within 92% of regulation (typical). The PWRGD delay is internally fixed at 200µs (typical). • High-Speed Driver Chipset Power • Networking Backplane Cards The overtemperature and short circuit current-limiting provide additional protection for the LDO during system • Notebook Computers Fault conditions. • Network Interface Cards • Palmtop Computers  2007-2013 Microchip Technology Inc. DS22057B-page 1

MCP1826/MCP1826S Package Types MCP1826 MCP1826S DDPAK-5 TO-220-5 DDPAK-3 TO-220-3 Fixed/Adjustable 1 2 3 1 2 3 1 2 3 4 5 1 2 3 4 5 SOT-223-5 SOT-223-3 6 4 1 2 3 4 5 1 2 3 Pin Fixed Adjustable Pin 1 SHDN SHDN 1 VIN 2 V V 2 GND (TAB) IN IN 3 V 3 GND (TAB) GND (TAB) OUT 4 GND (TAB) 4 V V OUT OUT 5 PWRGD ADJ 6 GND (TAB) GND (TAB) DS22057B-page 2  2007-2013 Microchip Technology Inc.

MCP1826/MCP1826S Typical Application MCP1826 Fixed Output Voltage PWRGD R 1 On 100k Off SHDN 1 VIN = 2.3V to 2.8V VIN VOUT VOUT = 1.8V @ 1000mA GND C 1 C 4.7µF 2 1µF MCP1826 Adjustable Output Voltage V ADJ R 2 20k R 1 On 40k Off SHDN VIN = 2.3V to 2.8V VIN 1 VOUT VOUT = 1.2V @ 1000mA C 1 C 4.7µF 2 1µF GND  2007-2013 Microchip Technology Inc. DS22057B-page 3

MCP1826/MCP1826S Functional Block Diagram – Adjustable Output PMOS VIN VOUT Undervoltage Lockout (UVLO) I SNS Cf Rf SHDN ADJ/SENSE + Driver w/limit EA and SHDN Overtemperature – Sensing SHDN V REF VIN SHDN Reference Soft-Start Comp T DELAY GND 92% of V REF DS22057B-page 4  2007-2013 Microchip Technology Inc.

MCP1826/MCP1826S Functional Block Diagram – Fixed Output (3-Pin) PMOS VIN VOUT Undervoltage Sense Lockout (UVLO) I SNS Cf Rf SHDN + Driver w/limit EA and SHDN Overtemperature – Sensing SHDN V REF VIN SHDN Reference Soft-Start Comp T DELAY GND 92% of V REF  2007-2013 Microchip Technology Inc. DS22057B-page 5

MCP1826/MCP1826S Functional Block Diagram – Fixed Output (5-Pin) PMOS VIN VOUT Undervoltage Sense Lockout (UVLO) I SNS Cf Rf SHDN + Driver w/limit EA and SHDN Overtemperature – Sensing SHDN V REF VIN SHDN Reference Soft-Start PWRGD Comp T DELAY GND 92% of V REF DS22057B-page 6  2007-2013 Microchip Technology Inc.

MCP1826/MCP1826S 1.0 ELECTRICAL † Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is CHARACTERISTICS a stress rating only and functional operation of the device at those or any other conditions above those indicated in the Absolute Maximum Ratings † operational listings of this specification is not implied. Expo- sure to maximum rating conditions for extended periods may VIN....................................................................................6.5V affect device reliability. Maximum Voltage on Any Pin..(GND – 0.3V) to (V + 0.3)V DD Maximum Power Dissipation.........Internally-Limited (Note6) Output Short Circuit Duration................................Continuous Storage temperature.....................................-65°C to +150°C Maximum Junction Temperature, T ...........................+150°C J ESD protection on all pins (HBM/MM) 4kV;  300V AC/DC CHARACTERISTICS Electrical Specifications: Unless otherwise noted, V = V + V , Note1, V =1.8V for Adjustable Output, IN OUT(MAX) DROPOUT(MAX) R I = 1mA, C = C = 4.7µF (X7R Ceramic), T = +25°C. OUT IN OUT A Boldface type applies for junction temperatures, T (Note7) of -40°C to +125°C J Parameters Sym. Min. Typ. Max. Units Conditions Input Operating Voltage V 2.3 6.0 V Note1 IN Input Quiescent Current I — 120 220 µA I = 0mA, V = 0.8V to q L OUT 5.0V Input Quiescent Current for I — 0.1 3 µA SHDN = GND SHDN SHDN Mode Maximum Output Current I 1000 — — mA V = 2.3V to 6.0V OUT IN V = 0.8V to 5.0V, Note1 R Line Regulation V / — ±0.05 ±0.20 %/V (Note1) V 6V OUT IN (V x V ) OUT IN Load Regulation V /V -1.0 ±0.5 1.0 % I = 1mA to 1000mA, OUT OUT OUT (Note4) Output Short Circuit Current I — 2.2 — A R <0.1, Peak Current OUT_SC LOAD Adjust Pin Characteristics (Adjustable Output Only) Adjust Pin Reference Voltage V 0.402 0.410 0.418 V V = 2.3V to V =6.0V, ADJ IN IN I = 1mA OUT Adjust Pin Leakage Current I -10 ±0.01 +10 nA V = 6.0V, V =0Vto6V ADJ IN ADJ Adjust Temperature Coefficient TCV — 40 — ppm/°C Note3 OUT Fixed-Output Characteristics (Fixed Output Only) Voltage Regulation V V - 2.5% V ±0.5% V + 2.5% V Note2 OUT R R R Note 1: The minimum V must meet two conditions: V 2.3V and V V V IN IN IN OUT(MAX) DROPOUT(MAX). 2: V is the nominal regulator output voltage for the fixed cases. V = 1.2V, 1.8V, etc. V is the desired set point output R R R voltage for the adjustable cases. V = V ((R /R )+1). Figure4-1. R ADJ* 1 2 3: TCV = (V – V ) *106 / (V * Temperature). V is the highest voltage measured over the OUT OUT-HIGH OUT-LOW R OUT-HIGH temperature range. V is the lowest voltage measured over the temperature range. OUT-LOW 4: Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is tested over a load range from 1mA to the maximum specified output current. 5: Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its nominal value that was measured with an input voltage of V = V + V . IN OUT(MAX) DROPOUT(MAX) 6: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air. (i.e., T , T ,  ). Exceeding the maximum allowable power A J JA dissipation will cause the device operating junction temperature to exceed the maximum +150°C rating. Sustained junction temperatures above 150°C can impact device reliability. 7: The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the desired junction temperature. The test time is small enough such that the rise in the junction temperature over the ambient temperature is not significant.  2007-2013 Microchip Technology Inc. DS22057B-page 7

MCP1826/MCP1826S AC/DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise noted, V = V + V , Note1, V =1.8V for Adjustable Output, IN OUT(MAX) DROPOUT(MAX) R I = 1mA, C = C = 4.7µF (X7R Ceramic), T = +25°C. OUT IN OUT A Boldface type applies for junction temperatures, T (Note7) of -40°C to +125°C J Parameters Sym. Min. Typ. Max. Units Conditions Dropout Characteristics Dropout Voltage V — 250 400 mV Note5, I = 1000mA, DROPOUT OUT V =2.3V IN(MIN) Power Good Characteristics PWRGD Input Voltage Operat- V 1.0 — 6.0 V T = +25°C PWRGD_VIN A ing Range 1.2 — 6.0 T = -40°C to +125°C A For V < 2.3V, I =100µA IN SINK PWRGD Threshold Voltage V %V Falling Edge PWRGD_TH OUT (Referenced to V ) OUT 89 92 95 V < 2.5V Fixed, OUT V = Adj. OUT 90 92 94 V >= 2.5V Fixed OUT PWRGD Threshold Hysteresis V 1.0 2.0 3.0 %V PWRGD_HYS OUT PWRGD Output Voltage Low V — 0.2 0.4 V I = 1.2mA, PWRGD_L PWRGDSINK ADJ = 0V PWRGD Leakage P _ — 1 — nA V = V = 6.0V WRGD LK PWRGD IN PWRGD Time Delay T — 125 — µs Rising Edge PG R = 10k PULLUP Detect Threshold to PWRGD T — 200 — µs V = V + 20mV VDET-PWRGD OUT PWRGD_TH Active Time Delay to V - 20mV PWRGD_TH Shutdown Input Logic High Input V 45 — — %V V = 2.3V to 6.0V SHDN-HIGH IN IN Logic Low Input V — — 15 %V V = 2.3V to 6.0V SHDN-LOW IN IN SHDN Input Leakage Current SHDN -0.1 ±0.001 +0.1 µA V =6V, SHDN =V , ILK IN IN SHDN = GND AC Performance Output Delay From SHDN T — 100 — µs SHDN = GND to V OR IN V = GND to 95% V OUT R Output Noise e — 2.0 — µV/Hz I = 200mA, f = 1kHz, N OUT C = 10µF (X7R Ceramic), OUT V = 2.5V OUT Note 1: The minimum V must meet two conditions: V 2.3V and V V V IN IN IN OUT(MAX) DROPOUT(MAX). 2: V is the nominal regulator output voltage for the fixed cases. V = 1.2V, 1.8V, etc. V is the desired set point output R R R voltage for the adjustable cases. V = V ((R /R )+1). Figure4-1. R ADJ* 1 2 3: TCV = (V – V ) *106 / (V * Temperature). V is the highest voltage measured over the OUT OUT-HIGH OUT-LOW R OUT-HIGH temperature range. V is the lowest voltage measured over the temperature range. OUT-LOW 4: Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is tested over a load range from 1mA to the maximum specified output current. 5: Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its nominal value that was measured with an input voltage of V = V + V . IN OUT(MAX) DROPOUT(MAX) 6: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air. (i.e., T , T ,  ). Exceeding the maximum allowable power A J JA dissipation will cause the device operating junction temperature to exceed the maximum +150°C rating. Sustained junction temperatures above 150°C can impact device reliability. 7: The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the desired junction temperature. The test time is small enough such that the rise in the junction temperature over the ambient temperature is not significant. DS22057B-page 8  2007-2013 Microchip Technology Inc.

MCP1826/MCP1826S AC/DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise noted, V = V + V , Note1, V =1.8V for Adjustable Output, IN OUT(MAX) DROPOUT(MAX) R I = 1mA, C = C = 4.7µF (X7R Ceramic), T = +25°C. OUT IN OUT A Boldface type applies for junction temperatures, T (Note7) of -40°C to +125°C J Parameters Sym. Min. Typ. Max. Units Conditions Power Supply Ripple Rejection PSRR — 60 — dB f = 100Hz, C = 4.7µF, OUT Ratio I = 100µA, OUT V = 100mV pk-pk, INAC C = 0µF IN Thermal Shutdown Temperature T — 150 — °C I = 100µA, V = 1.8V, SD OUT OUT V = 2.8V IN Thermal Shutdown Hysteresis T — 10 — °C I = 100µA, V = 1.8V, SD OUT OUT V = 2.8V IN Note 1: The minimum V must meet two conditions: V 2.3V and V V V IN IN IN OUT(MAX) DROPOUT(MAX). 2: V is the nominal regulator output voltage for the fixed cases. V = 1.2V, 1.8V, etc. V is the desired set point output R R R voltage for the adjustable cases. V = V ((R /R )+1). Figure4-1. R ADJ* 1 2 3: TCV = (V – V ) *106 / (V * Temperature). V is the highest voltage measured over the OUT OUT-HIGH OUT-LOW R OUT-HIGH temperature range. V is the lowest voltage measured over the temperature range. OUT-LOW 4: Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is tested over a load range from 1mA to the maximum specified output current. 5: Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its nominal value that was measured with an input voltage of V = V + V . IN OUT(MAX) DROPOUT(MAX) 6: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air. (i.e., T , T ,  ). Exceeding the maximum allowable power A J JA dissipation will cause the device operating junction temperature to exceed the maximum +150°C rating. Sustained junction temperatures above 150°C can impact device reliability. 7: The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the desired junction temperature. The test time is small enough such that the rise in the junction temperature over the ambient temperature is not significant. TEMPERATURE SPECIFICATIONS Parameters Sym. Min. Typ. Max. Units Conditions Temperature Ranges Operating Junction Temperature Range T -40 — +125 °C Steady State J Maximum Junction Temperature T — — +150 °C Transient J Storage Temperature Range T -65 — +150 °C A Thermal Package Resistances Thermal Resistance, 3L-DDPAK  — 31.4 — °C/W 4-Layer JC51 Standard JA Board  — 3.0 — °C/W JC Thermal Resistance, 3L-TO-220  — 29.4 — °C/W 4-Layer JC51 Standard JA  — 2.0 — °C/W Board JC Thermal Resistance, 3L-SOT-223  — 62 — °C/W EIA/JEDEC JESD51-751-7 JA  — 15.0 — °C/W 4 Layer Board JC Thermal Resistance, 5L-DDPAK  — 31.2 — °C/W 4-Layer JC51 Standard JA Board  — 3.0 — °C/W JC Thermal Resistance, 5L-TO-220  — 29.3 — °C/W 4-Layer JC51 Standard JA  — 2.0 — °C/W Board JC Thermal Resistance, 5L-SOT-223  — 62 — °C/W EIA/JEDEC JESD51-751-7 JA  — 15.0 — °C/W 4 Layer Board JC  2007-2013 Microchip Technology Inc. DS22057B-page 9

MCP1826/MCP1826S 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, C = 4.7µF Ceramic (X7R), C = 4.7µF Ceramic (X7R), I = 1mA, OUT IN OUT Temperature = +25°C, V = V + 0.6V, Fixed output. IN OUT 140 0.10 μescent Current (A) 111110230000 ++++1+92293100550030CCCCCC C VIOOUUTT = = 0 1 m.2AV Adj ne Regulation (%/V) 00000.....0000056789 IIIOOOUUUTTT = == 21150 m00 mAmAA IOUT = 50 mA VINV O=U 2T .=3 V1 .t2oV 6 A.0dVj Qui 90 -45C Li 0.04 IOUT = 1000 mA 0.03 80 -45 -20 5 30 55 80 105 130 2 3 4 5 6 Input Voltage (V) Temperature (°C) FIGURE 2-1: Quiescent Current vs. Input FIGURE 2-4: Line Regulation vs. Voltage (Adjustable Version). Temperature (Adjustable Version). 180 0.15 A) 170 VOUT = 1.2V Adj %) 0.10 VOUT = 3.3VIOUT = 1.0 mA to 1000 mA urrent (μ 111456000 VIN = 5.0V ulation ( 00..0005 VOUT = 1.8V ound C 112300 VIN = 3.3V ad Reg -0.05 VOUT = 5.0V VOUT = 0.8V Gr 110 VIN = 2.3V Lo -0.10 100 -0.15 0 250 500 750 1000 -45 -20 5 30 55 80 105 130 Load Current (mA) Temperature (°C) FIGURE 2-2: Ground Current vs. Load FIGURE 2-5: Load Regulation vs. Current (Adjustable Version). Temperature (Adjustable Version). 140 0.411 μurrent (A) 111111223350505 VIN = 6.0V VIOOUUTT = = 0 1 m.2VA Adj Voltage (V) 00..440190 VVININ = = 6 5.0.0VV VIOOUUTT = = 1 1.0.2 mV A Quiescent C 1119910005005 V = 2.3V VIN = 3.0V VIN = 4.0V VIN = 5.0V Adjust Pin 00..440078 VIN = 2.3V IN 85 0.406 -45 -20 5 30 55 80 105 130 -45 -20 5 30 55 80 105 130 Temperature (°C) Temperature (°C) FIGURE 2-3: Quiescent Current vs. FIGURE 2-6: Adjust Pin Voltage vs. Junction Temperature (Adjustable Version). Temperature (Adjustable Version). DS22057B-page 10  2007-2013 Microchip Technology Inc.

MCP1826/MCP1826S Note: Unless otherwise indicated, C = 4.7µF Ceramic (X7R), C = 4.7µF Ceramic (X7R), I = 1mA, OUT IN OUT Temperature = +25°C, V = V + 0.6V, Fixed output. IN OUT 0.30 150 VOUT = 0.8V V) 0.25 μA) 140 IOUT = 0 mA age ( 0.20 VOUT = 5.0V Adj ent ( 130 +130°C Dropout Volt 000...011505 VOUT = 2.5V Adj Quiescent Curr 111012000 0-++4°925C05°°°CCC 0.00 90 0 200 400 600 800 1000 2 3 4 5 6 Load Current (mA) Input Voltage (V) FIGURE 2-7: Dropout Voltage vs. Load FIGURE 2-10: Quiescent Current vs. Input Current (Adjustable Version). Voltage. 0.34 150 oltage (V) 00..2381 VOUT = 5.0V Adj IOUT = 1.0A μCurrent (A) 111423000 ++19300CC VIOOUUTT = = 0 2 m.5AV ut V 0.25 ent 110 +02C5 C Dropo 0.22 VOUT = 2.5V Adj Quiesc 19000 -45C 0.19 80 -45 -20 5 30 55 80 105 130 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Temperature (°C) Input Voltage (V) FIGURE 2-8: Dropout Voltage vs. FIGURE 2-11: Quiescent Current vs. Input Temperature (Adjustable Version). Voltage. ay (µS) 116700 VIOOUUTT= = 0 2 m.5AV A) 128000 VVIINN == 23..39VV ffoorr VVRR==03..83VV Time Del 114500 VIN = 6.0V urrent (μ 114600 VOUT=3.3V ower Good 111231000 VIN = 5.0V VIN = 3.9V VIN = 3.1V Ground C 11028000 VOUT=0.8V P 100 60 -45 -20 5 30 55 80 105 130 0 250 500 750 1000 Temperature (°C) Load Current (mA) FIGURE 2-9: Power Good (PWRGD) FIGURE 2-12: Ground Current vs. Load Time Delay vs. Temperature. Current.  2007-2013 Microchip Technology Inc. DS22057B-page 11

MCP1826/MCP1826S Note: Unless otherwise indicated, C = 4.7µF Ceramic (X7R), C = 4.7µF Ceramic (X7R), I = 1mA, OUT IN OUT Temperature = +25°C, V = V + 0.6V, Fixed output. IN OUT 130 0.040 cent Current (μA) 111110112250505 VOUT = 2.5V IOUT = 0 mA Regulation (%/V) 000...000233505 IIIOOOUUUTTT === 152 05m 0m AmAA V I N = 3 .V1R t =o 26..50VV Quies 10905 VOUT = 0.8V Line 0.020 IOUT = 1000 mA IOUT = 500 mA 90 0.015 -45 -20 5 30 55 80 105 130 -45 -20 5 30 55 80 105 130 Temperature (°C) Temperature (°C) FIGURE 2-13: Quiescent Current vs. FIGURE 2-16: Line Regulation vs. Temperature. Temperature. 0.50 VR = 0.8V 0.30 0.40 VOUT = 0.8V μ (A) HDN 00..2300 VIN = 6.0V VVIINN == 34..00VV gulation (%) 000...012000 IOUT = 1 mA toV 1IN0 0=0 2 m.3AV IS 0.10 VIN = 5.0V VIN = 2.3V oad Re --00..2100 L 0.00 -0.30 -45 -20 5 30 55 80 105 130 -45 -20 5 30 55 80 105 130 Temperature (°C) Temperature (°C) FIGURE 2-14: I vs. Temperature. FIGURE 2-17: Load Regulation vs. SHDN Temperature (V < 2.5V Fixed). OUT 0.10 0.00 on (%/V) 00..0068 IIOOUUTT == 15 0m mAA VVOINU =T =2I .O03U.V8T V=to 1 60.00 VmA on (%) ---000...110505 VOUT = 2.5V IOUT = 1 mA to 1000 mA egulati 0.04 egulati --00..2250 VOUT = 5.0V Line R 0.02 IOUT = I1OAUT = 500mA Load R --00..3350 0.00 -0.40 -45 -20 5 30 55 80 105 130 -45 -20 5 30 55 80 105 130 Temperature (°C) Temperature (°C) FIGURE 2-15: Line Regulation vs. FIGURE 2-18: Load Regulation vs. Temperature. Temperature (V 2.5V Fixed). OUT DS22057B-page 12  2007-2013 Microchip Technology Inc.

MCP1826/MCP1826S Note: Unless otherwise indicated, C = 4.7µF Ceramic (X7R), C = 4.7µF Ceramic (X7R), I = 1mA, OUT IN OUT Temperature = +25°C, V = V + 0.6V, Fixed output. IN OUT 0.30 10.000 V=0.8V, V =2.3V C =1 μF ceramic X7R R IN OUTC =10 μF ceramic 0.25 IN e (V) 0.20 VOUT = 2.5V Hz) 1.000 ut Voltag 0.15 VOUT = 5.0V (cid:2)(cid:2)(cid:3)(cid:3)se (V/ VR=3.3V, VIN=4.1V IOUT=200 mA opo 0.10 Noi 0.100 Dr 0.05 0.00 0.010 0 200 400 600 800 1000 0.01 0.1 1 10 100 1000 Load Current (mA) Frequency (kHz) FIGURE 2-19: Dropout Voltage vs. Load FIGURE 2-22: Output Noise Voltage Current. Density vs. Frequency. 0.34 0 IOUT = 1000 mA 0.32 -10 V) out Voltage ( 000...223680 VOUT = 2.5V SRR (dB) ----54320000 VCRO=UT1=.21V0 AμFd jceramic X7R Drop 00..2224 VOUT = 5.0V P -60 VCIINN==30. 1μVF -70 IOUT=10 mA 0.20 -80 -45 -20 5 30 55 80 105 130 0.01 0.1 1 10 100 1000 Temperature (°C) Frequency (kHz) FIGURE 2-20: Dropout Voltage vs. FIGURE 2-23: Power Supply Ripple Temperature. Rejection (PSRR) vs. Frequency (Adjustable). 0 2.00 A) 1.80 VOUT = 0.8V -10 nt ( 1.60 -20 urre 11..2400 dB)-30 Short Circuit C 00001.....2468000000 PSRR (----76540000 VCVCIORIOIUNN=UT===T330=1.. 329μ0V2V Fm FμAiFx ecderamic X7R 0.00 -80 0 1 2 3 4 5 6 0.01 0.1 1 10 100 1000 Input Voltage (V) Frequency (kHz) FIGURE 2-21: Short Circuit Current vs. FIGURE 2-24: Power Supply Ripple Input Voltage. Rejection (PSRR) vs. Frequency.  2007-2013 Microchip Technology Inc. DS22057B-page 13

MCP1826/MCP1826S Note: Unless otherwise indicated, C = 4.7µF Ceramic (X7R), C = 4.7µF Ceramic (X7R), I = 1mA, OUT IN OUT Temperature = +25°C, V = V + 0.6V, Fixed output. IN OUT FIGURE 2-25: 2.5V (Adj.) Start-up from FIGURE 2-28: Dynamic Line Response. V . IN FIGURE 2-29: Dynamic Load Response FIGURE 2-26: 2.5V (Adj.) Start-up from (10mA to 1000mA). Shutdown. FIGURE 2-30: Dynamic Load Response FIGURE 2-27: Power Good (PWRGD) (100mA to 1000mA). Timing. DS22057B-page 14  2007-2013 Microchip Technology Inc.

MCP1826/MCP1826S 3.0 PIN DESCRIPTION The descriptions of the pins are listed in Table3-1. TABLE 3-1: PIN FUNCTION TABLE 3-Pin Fixed 5-Pin Fixed Adjustable Name Description Output Output Output — 1 1 SHDN Shutdown Control Input (active-low) 1 2 2 V Input Voltage Supply IN 2 3 3 GND Ground 3 4 4 V Regulated Output Voltage OUT — 5 — PWRGD Power Good Output — — 5 ADJ Voltage Adjust/Sense Input Exposed Pad Exposed Pad Exposed Pad EP Exposed Pad of the Package (ground potential) 3.1 Shutdown Control Input (SHDN) 3.5 Power Good Output (PWRGD) The SHDN input is used to turn the LDO output voltage The PWRGD output is an open-drain output used to on and off. When the SHDN input is at a logic-high indicate when the LDO output voltage is within 92% level, the LDO output voltage is enabled. When the (typically) of its nominal regulation value. The PWRGD SHDN input is pulled to a logic-low level, the LDO threshold has a typical hysteresis value of 2%. The output voltage is disabled. When the SHDN input is PWRGD output is delayed by 200µs (typical) from the pulled low, the PWRGD output also goes low and the time the LDO output is within 92% + 3% (max hystere- LDO enters a low quiescent current shutdown state sis) of the regulated output value on power-up. This where the typical quiescent current is 0.1µA. delay time is internally fixed. 3.2 Input Voltage Supply (V ) 3.6 Output Voltage Adjust Input (ADJ) IN Connect the unregulated or regulated input voltage For adjustable applications, the output voltage is source to V . If the input voltage source is located connected to the ADJ input through a resistor divider IN several inches away from the LDO, or the input source that sets the output voltage regulation value. This is a battery, it is recommended that an input capacitor provides the user the capability to set the output be used. A typical input capacitance value of 1µF to voltage to any value they desire within the 0.8V to 5.0V 10µF should be sufficient for most applications. range of the device. 3.7 Exposed Pad (EP) 3.3 Ground (GND) The DDPAK and TO-220 package have an exposed tab Connect the GND pin of the LDO to a quiet circuit on the package. A heat sink may be mounted to the tab ground. This will help the LDO power supply rejection to aid in the removal of heat from the package during ratio and noise performance. The ground pin of the operation. The exposed tab is at the ground potential of LDO only conducts the quiescent current of the LDO the LDO. (typically 120µA), so a heavy trace is not required. For applications have switching or noisy inputs tie the GND pin to the return of the output capacitor. Ground planes help lower inductance and voltage spikes caused by fast transient load currents and are recommended for applications that are subjected to fast load transients. 3.4 Regulated Output Voltage (V ) OUT The V pin is the regulated output voltage of the OUT LDO. A minimum output capacitance of 1.0µF is required for LDO stability. The MCP1826/MCP1826S is stable with ceramic, tantalum and aluminum-electro- lytic capacitors. See Section4.3 “Output Capacitor” for output capacitor selection guidance.  2007-2013 Microchip Technology Inc. DS22057B-page 15

MCP1826/MCP1826S 4.0 DEVICE OVERVIEW EQUATION 4-2: V –V The MCP1826/MCP1826S is a high output current, R = R ----O----U----T------------A----D---J- 1 2 V  Low Dropout (LDO) voltage regulator. The low dropout ADJ Where: voltage of 300mV typical at 1000mA of current makes it ideal for battery-powered applications. Unlike other V = LDO Output Voltage OUT high output current LDOs, the MCP1826/MCP1826S V = ADJ Pin Voltage ADJ only draws a maximum of 220µA of quiescent current. (typically 0.41V) The MCP1826 has a shutdown control input and a power good output. 4.2 Output Current and Current 4.1 LDO Output Voltage Limiting The 5-pin MCP1826 LDO is available with either a fixed The MCP1826/MCP1826S LDO is tested and ensured output voltage or an adjustable output voltage. The to supply a minimum of 1000mA of output current. The output voltage range is 0.8V to 5.0V for both versions. MCP1826/MCP1826S has no minimum output load, so The 3-pin MCP1826S LDO is available as a fixed the output load current can go to 0mA and the LDO will voltage device. continue to regulate the output voltage to within tolerance. 4.1.1 ADJUST INPUT The MCP1826/MCP1826S also incorporates an output The adjustable version of the MCP1826 uses the ADJ current limit. If the output voltage falls below 0.7V due pin (pin 5) to get the output voltage feedback for output to an overload condition (usually represents a shorted voltage regulation. This allows the user to set the load condition), the output current is limited to 2.2A output voltage of the device with two external resistors. (typical). If the overload condition is a soft overload, the The nominal voltage for ADJ is 0.41V. MCP1826/MCP1826S will supply higher load currents Figure4-1 shows the adjustable version of the of up to 2.5A. The MCP1826/MCP1826S should not be MCP1826. Resistors R and R form the resistor operated in this condition continuously as it may result 1 2 divider network necessary to set the output voltage. in failure of the device. However, this does allow for With this configuration, the equation for setting V is: device usage in applications that have higher pulsed OUT load currents having an average output current value of EQUATION 4-1: 1000mA or less. R +R Output overload conditions may also result in an over- VOUT = VADJ----1---R----------2- temperature shutdown of the device. If the junction Where: 2 temperature rises above 150°C, the LDO will shut down the output voltage. See Section4.8 “Overtem- VOUT = LDO Output Voltage perature Protection” for more information on V = ADJ Pin Voltage overtemperature shutdown. ADJ (typically 0.41V) 4.3 Output Capacitor The MCP1826/MCP1826S requires a minimum output MCP1826-ADJ capacitance of 1µF for output voltage stability. Ceramic VOUT capacitors are recommended because of their size, cost and environmental robustness qualities. OffOn SHDN 1 2 3 4 5 ADJ R1 1C2µF Aluminum-electrolytic and tantalum capacitors can be used on the LDO output as well. The Equivalent Series VIN Resistance (ESR) of the electrolytic output capacitor 4C.71µF GND R2 must be no greater than 1 ohm. The output capacitor should be located as close to the LDO output as is practical. Ceramic materials X7R and X5R have low temperature coefficients and are well within the FIGURE 4-1: Typical adjustable output acceptable ESR range required. A typical 1µF X7R voltage application circuit. 0805 capacitor has an ESR of 50milli-ohms. The allowable resistance value range for resistor R is 2 from 10k to 200k. Solving the equation for R 1 yields the following equation: DS22057B-page 16  2007-2013 Microchip Technology Inc.

MCP1826/MCP1826S Larger LDO output capacitors can be used with the When the LDO is put into Shutdown mode using the MCP1826/MCP1826S to improve dynamic SHDN input, the power good output is pulled low performance and power supply ripple rejection immediately, indicating that the output voltage will be performance. A maximum of 22µF is recommended. out of regulation. The timing diagram for the power Aluminum-electrolytic capacitors are not recom- good output when using the shutdown input is shown in mended for low-temperature applications of  -25°C. Figure4-3. The power good output is an open-drain output that can 4.4 Input Capacitor be pulled up to any voltage that is equal to or less than the LDO input voltage. This output is capable of sinking Low input source impedance is necessary for the LDO 1.2mA (V < 0.4V maximum). output to operate properly. When operating from PWRGD batteries, or in applications with long lead length (> 10 inches) between the input source and the LDO, some input capacitance is recommended. A minimum VPWRGD_TH of 1.0µF to 4.7µF is recommended for most applications. VOUT For applications that have output step load TPG requirements, the input capacitance of the LDO is very important. The input capacitance provides the LDO VOH with a good local low-impedance source to pull the TVDET_PWRGD transient currents from in order to respond quickly to the output load step. For good step response PWRGD performance, the input capacitor should be of equivalent (or higher) value than the output capacitor. VOL The capacitor should be placed as close to the input of the LDO, as is practical. Larger input capacitors will also help reduce any high-frequency noise on the input FIGURE 4-2: Power Good Timing. and output of the LDO and reduce the effects of any inductance that exists between the input source voltage and the input capacitance of the LDO. 4.5 Power Good Output (PWRGD) VIN TOR The PWRGD output is used to indicate when the output 70µs voltage of the LDO is within 92% (typical value, see 30 µs Section1.0 “Electrical Characteristics” for Minimum and Maximum specifications) of its nominal regulation SHDN TPG value. As the output voltage of the LDO rises, the PWRGD output will be held low until the output voltage has exceeded the power good threshold plus the hysteresis value. Once this threshold has been exceeded, the VOUT power good time delay is started (shown as T in the PG Electrical Characteristics table). The power good time delay is fixed at 200µs (typical). After the time delay period, the PWRGD output will go high, indicating that PWRGD the output voltage is stable and within regulation limits. If the output voltage of the LDO falls below the power good threshold, the power good output will transition FIGURE 4-3: Power Good Timing from low. The power good circuitry has a 170µs delay when Shutdown. detecting a falling output voltage, which helps to increase noise immunity of the power good output and avoid false triggering of the power good output during fast output transients. See Figure4-2 for power good timing characteristics.  2007-2013 Microchip Technology Inc. DS22057B-page 17

MCP1826/MCP1826S 4.6 Shutdown Input (SHDN) 4.7 Dropout Voltage and Undervoltage Lockout The SHDN input is an active-low input signal that turns the LDO on and off. The SHDN threshold is a Dropout voltage is defined as the input-to-output percentage of the input voltage. The typical value of voltage differential at which the output voltage drops this shutdown threshold is 30% of VIN, with minimum 2% below the nominal value that was measured with a and maximum limits over the entire operating V + 0.5V differential applied. The MCP1826/ R temperature range of 45% and 15%, respectively. MCP1826S LDO has a very low dropout voltage The SHDN input will ignore low-going pulses (pulses specification of 300mV (typical) at 1000mA of output meant to shut down the LDO) that are up to 400ns in current. See Section1.0 “Electrical Characteristics” pulse width. If the shutdown input is pulled low for more for maximum dropout voltage specifications. than 400ns, the LDO will enter Shutdown mode. This The MCP1826/MCP1826S LDO operates across an small bit of filtering helps to reject any system noise input voltage range of 2.3V to 6.0V and incorporates spikes on the shutdown input signal. input Undervoltage Lockout (UVLO) circuitry that keeps On the rising edge of the SHDN input, the shutdown the LDO output voltage off until the input voltage circuitry has a 30µs delay before allowing the LDO reaches a minimum of 2.00V (typical) on the rising output to turn on. This delay helps to reject any false edge of the input voltage. As the input voltage falls, the turn-on signals or noise on the SHDN input signal. After LDO output will remain on until the input voltage level the 30µs delay, the LDO output enters its soft-start reaches 1.82V (typical). period as it rises from 0V to its final regulation value. If Since the MCP1826/MCP1826S LDO undervoltage the SHDN input signal is pulled low during the 30µs lockout activates at 1.82V as the input voltage is falling, delay period, the timer will be reset and the delay time the dropout voltage specification does not apply for will start over again on the next rising edge of the output voltages that are less than 1.8V. SHDN input. The total time from the SHDN input going For high-current applications, voltage drops across the high (turn-on) to the LDO output being in regulation is PCB traces must be taken into account. The trace typically 100µs. See Figure4-4 for a timing diagram of resistances can cause significant voltage drops the SHDN input. between the input voltage source and the LDO. For applications with input voltages near 2.3V, these PCB TOR trace voltage drops can sometimes lower the input 400ns (typ) voltage enough to trigger a shutdown due to 70µs undervoltage lockout. 30µs 4.8 Overtemperature Protection SHDN The MCP1826/MCP1826S LDO has temperature- sensing circuitry to prevent the junction temperature from exceeding approximately 150°C. If the LDO junction temperature does reach 150°C, the LDO VOUT output will be turned off until the junction temperature cools to approximately 140°C, at which point the LDO output will automatically resume normal operation. If FIGURE 4-4: Shutdown Input Timing the internal power dissipation continues to be Diagram. excessive, the device will again shut off. The junction temperature of the die is a function of power dissipa- tion, ambient temperature and package thermal resistance. See Section5.0 “Application Circuits/ Issues” for more information on LDO power dissipation and junction temperature. DS22057B-page 18  2007-2013 Microchip Technology Inc.

MCP1826/MCP1826S 5.0 APPLICATION CIRCUITS/ In addition to the LDO pass element power dissipation, ISSUES there is power dissipation within the MCP1826/ MCP1826S as a result of quiescent or ground current. The power dissipation as a result of the ground current 5.1 Typical Application can be calculated using the following equation: The MCP1826/MCP1826S is used for applications that EQUATION 5-2: require high LDO output current and a power good output. P = V I IGND INMAX VIN Where: VOUT = 2.5V @ 1000mA P = Power dissipation due to the MCP1826-2.5 I(GND) On R1 quiescent current of the LDO Off 1 2 3 4 5 10k C2 V = Maximum input voltage SHDN 10µF IN(MAX) I = Current flowing in the V pin 3.3V VIN VIN with no LDO output currIeNnt C1 (LDO quiescent current) 4.7µF GND PWRGD The total power dissipated within the MCP1826/ MCP1826S is the sum of the power dissipated in the FIGURE 5-1: Typical Application Circuit. LDO pass device and the P(I ) term. Because of the GND CMOS construction, the typical I for the MCP1826/ GND 5.1.1 APPLICATION CONDITIONS MCP1826S is 120µA. Operating at a maximum V of IN 3.465V results in a power dissipation of 0.12milli-Watts Package Type = TO-220-5 for a 2.5V output. For most applications, this is small Input Voltage Range = 3.3V ± 5% compared to the LDO pass device power dissipation VIN maximum = 3.465V and can be neglected. VIN minimum = 3.135V The maximum continuous operating junction V = 0.400V temperature specified for the MCP1826/MCP1826S is DROPOUT (max) V (typical) = 2.5V +125°C. To estimate the internal junction temperature OUT of the MCP1826/MCP1826S, the total internal power I = 1000mA maximum OUT dissipation is multiplied by the thermal resistance from PDISS (typical) = 0.965W junction-to-ambient (RJA) of the device. The thermal Temperature Rise = 28.27°C resistance from junction to ambient for the TO-220-5 package is estimated at 29.3°C/W. 5.2 Power Calculations EQUATION 5-3: 5.2.1 POWER DISSIPATION T = P R +T JMAX TOTAL JA AMAX The internal power dissipation within the MCP1826/ T = Maximum continuous junction MCP1826S is a function of input voltage, output J(MAX) temperature voltage, output current and quiescent current. Equation5-1 can be used to calculate the internal P = Total device power dissipation TOTAL power dissipation for the LDO. R = Thermal resistance from junction to JA ambient EQUATION 5-1: T = Maximum ambient temperature A(MAX) P = V –V I LDO INMAX OUTMIN OUTMAX Where: P = LDO Pass device internal LDO power dissipation V = Maximum input voltage IN(MAX) V = LDO minimum output voltage OUT(MIN)  2007-2013 Microchip Technology Inc. DS22057B-page 19

MCP1826/MCP1826S The maximum power dissipation capability for a 5.3 Typical Application package can be calculated given the junction-to- ambient thermal resistance and the maximum ambient Internal power dissipation, junction temperature rise, temperature for the application. Equation5-4 can be junction temperature and maximum power dissipation used to determine the package maximum internal is calculated in the following example. The power power dissipation. dissipation as a result of ground current is small enough to be neglected. EQUATION 5-4: 5.3.1 POWER DISSIPATION EXAMPLE T –T  P = -------J----M----A---X---------------A-----M----A---X------ DMAX R Package JA Package Type = TO-220-5 P = Maximum device power dissipation D(MAX) Input Voltage T = Maximum continuous junction J(MAX) V = 3.3V ± 5% temperature IN LDO Output Voltage and Current T = Maximum ambient temperature A(MAX) V = 2.5V R = Thermal resistance from junction to OUT JA I = 1000mA ambient OUT Maximum Ambient Temperature T = 60°C EQUATION 5-5: A(MAX) Internal Power Dissipation T = P R JRISE DMAX JA P = (V – V ) x I LDO(MAX) IN(MAX) OUT(MIN) OUT(MAX) TJ(RISE) = Rise in device junction temperature PLDO = ((3.3V x 1.05) – (2.5V x 0.975)) over the ambient temperature x 1000mA PD(MAX) = Maximum device power dissipation PLDO = 1.028 Watts R = Thermal resistance from junction to JA 5.3.1.1 Device Junction Temperature Rise ambient The internal junction temperature rise is a function of internal power dissipation and the thermal resistance EQUATION 5-6: from junction to ambient for the application. The thermal resistance from junction-to-ambient (R ) is T = T +T JA J JRISE A derived from EIA/JEDEC standards for measuring thermal resistance. The EIA/JEDEC specification is T = Junction temperature J JESD51. The standard describes the test method and TJ(RISE) = Rise in device junction temperature board specifications for measuring the thermal over the ambient temperature resistance from junction to ambient. The actual thermal T = Ambient temperature resistance for a particular application can vary A depending on many factors such as copper area and thickness. Refer to AN792, “A Method to Determine How Much Power a SOT23 Can Dissipate in an Appli- cation” (DS00792), for more information regarding this subject. T = P x R J(RISE) TOTAL JA TJ(RISE) = 1.028 W x 29.3°C/W TJ(RISE) = 30.12°C DS22057B-page 20  2007-2013 Microchip Technology Inc.

MCP1826/MCP1826S 5.3.1.2 Junction Temperature Estimate To estimate the internal junction temperature, the calculated temperature rise is added to the ambient or offset temperature. For this example, the worst-case junction temperature is estimated below: T = T + T J J(RISE) A(MAX) T = 30.12°C + 60.0°C J T = 90.12°C J 5.3.1.3 Maximum Package Power Dissipation at 60°C Ambient Temperature TO-220-5 (29.3° C/W R ): JA P = (125°C – 60°C) / 29.3°C/W D(MAX) P = 2.218W D(MAX) DDPAK-5 (31.2°C/Watt R ): JA P = (125°C – 60°C)/ 31.2°C/W D(MAX) P = 2.083W D(MAX) From this table, you can see the difference in maximum allowable power dissipation between the TO-220-5 package and the DDPAK-5 package.  2007-2013 Microchip Technology Inc. DS22057B-page 21

MCP1826/MCP1826S 6.0 PACKAGING INFORMATION 6.1 Package Marking Information 3-Lead DDPAK (MCP1826S) Example: XXXXXXXXX MCP1826S XXXXXXXXX 08EEB^e^3 YYWWNNN 0730256 1 2 3 1 2 3 3-Lead SOT-223 (MCP1826S) Example: XXXXXXX 1826S08 XXXYYWW EDB0730 NNN 256 3-Lead TO-220 (MCP1826S) Example: XXXXXXXXX MCP1826S XXXXXXXXX 12EAB^e^3 YYWWNNN 0730256 1 2 3 1 2 3 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. DS22057B-page 22  2007-2013 Microchip Technology Inc.

MCP1826/MCP1826S Package Marking Information (Continued) 5-Lead DDPAK (MCP1826) Example: XXXXXXXXX MCP1826 XXXXXXXXX 10EET^e^3 YYWWNNN 0730256 1 2 3 4 5 1 2 3 4 5 5-Lead SOT-223 (MCP1826) Example: XXXXXXX 1826-08 XXXYYWW EDC0730 NNN 256 5-Lead TO-220 (MCP1826) Example: XXXXXXXXX MCP1826 XXXXXXXXX 08EAT^e^3 YYWWNNN 0730256 1 2 3 4 5 1 2 3 4 5 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2007-2013 Microchip Technology Inc. DS22057B-page 23

MCP1826/MCP1826S (cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:18)(cid:19)(cid:9)(cid:20)(cid:21)(cid:21)(cid:10)(cid:22)(cid:23)(cid:24) (cid:25)(cid:26)(cid:13)(cid:6)(cid:27) 0(cid:10)(cid:9)(cid:2) (cid:11)(cid:14)(cid:2)#(cid:10)" (cid:2)(cid:8)&(cid:9)(cid:9)(cid:14)(cid:15) (cid:2)(cid:12)(cid:28)(cid:8)1(cid:28)(cid:17)(cid:14)(cid:2)$(cid:9)(cid:28)/(cid:7)(cid:15)(cid:17)"2(cid:2)(cid:12)(cid:16)(cid:14)(cid:28)"(cid:14)(cid:2)"(cid:14)(cid:14)(cid:2) (cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)3(cid:28)(cid:8)1(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)(cid:31)(cid:7)(cid:8)(cid:28) (cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28) (cid:14)$(cid:2)(cid:28) (cid:2) (cid:11) (cid:12)-44///(cid:20)#(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)#4(cid:12)(cid:28)(cid:8)1(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) E E1 L1 D1 D H 1 N b e BOTTOMVIEW TOPVIEW b1 CHAMFER OPTIONAL A C2 φ A1 c L 5(cid:15)(cid:7) " (cid:19)6!7%(cid:22) (cid:21)(cid:7)#(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:2)8(cid:7)#(cid:7) " (cid:6)(cid:19)6 69(cid:6) (cid:6)(cid:25): 6&#;(cid:14)(cid:9)(cid:2)(cid:10)(cid:31)(cid:2)3(cid:7)(cid:15)" 6 * 3(cid:7) (cid:8)(cid:11) (cid:14) (cid:20)(cid:29)(cid:4)(cid:4)(cid:2),(cid:22)! 9.(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)7(cid:14)(cid:7)(cid:17)(cid:11) (cid:25) (cid:20)(cid:29)<(cid:4) = (cid:20)(cid:29)(cid:24)(cid:4) (cid:22) (cid:28)(cid:15)$(cid:10)(cid:31)(cid:31)(cid:2)(cid:2)(cid:30) (cid:25)(cid:29) (cid:20)(cid:4)(cid:4)(cid:4) = (cid:20)(cid:4)(cid:29)(cid:4) 9.(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)$ (cid:11) % (cid:20)*?(cid:4) = (cid:20)(cid:23)(cid:3)(cid:4) %’(cid:12)(cid:10)"(cid:14)$(cid:2)3(cid:28)$(cid:2)>(cid:7)$ (cid:11) %(cid:29) (cid:20)(cid:3)(cid:23)( = = (cid:6)(cid:10)(cid:16)$(cid:14)$(cid:2)3(cid:28)(cid:8)1(cid:28)(cid:17)(cid:14)(cid:2)8(cid:14)(cid:15)(cid:17) (cid:11) (cid:21) (cid:20)**(cid:4) = (cid:20)*?(cid:4) 9.(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:15)(cid:17) (cid:11) 7 (cid:20)((cid:23)(cid:24) = (cid:20)<(cid:3)( %’(cid:12)(cid:10)"(cid:14)$(cid:2)3(cid:28)$(cid:2)8(cid:14)(cid:15)(cid:17) (cid:11) (cid:21)(cid:29) (cid:20)(cid:3)(cid:5)(cid:4) = = 8(cid:14)(cid:28)$(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)1(cid:15)(cid:14)"" (cid:8) (cid:20)(cid:4)(cid:29)(cid:23) = (cid:20)(cid:4)(cid:3)(cid:24) 3(cid:28)$(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)1(cid:15)(cid:14)"" !(cid:3) (cid:20)(cid:4)(cid:23)( = (cid:20)(cid:4)<( 8(cid:10)/(cid:14)(cid:9)(cid:2)8(cid:14)(cid:28)$(cid:2)>(cid:7)$ (cid:11) ; (cid:20)(cid:4)(cid:3)(cid:4) = (cid:20)(cid:4)*(cid:24) 5(cid:12)(cid:12)(cid:14)(cid:9)(cid:2)8(cid:14)(cid:28)$(cid:2)>(cid:7)$ (cid:11) ;(cid:29) (cid:20)(cid:4)(cid:23)( = (cid:20)(cid:4)(cid:5)(cid:4) 0(cid:10)(cid:10) (cid:2)8(cid:14)(cid:15)(cid:17) (cid:11) 8 (cid:20)(cid:4)<? = (cid:20)(cid:29)(cid:29)(cid:4) 3(cid:28)$(cid:2)8(cid:14)(cid:15)(cid:17) (cid:11) 8(cid:29) = = (cid:20)(cid:4)<(cid:5) 0(cid:10)(cid:10) (cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)@ = ?@ (cid:25)(cid:26)(cid:13)(cid:6)(cid:12)(cid:27) (cid:29)(cid:20) (cid:30)(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)(cid:31)(cid:7)(cid:8)(cid:28)(cid:15) (cid:2)!(cid:11)(cid:28)(cid:9)(cid:28)(cid:8) (cid:14)(cid:9)(cid:7)" (cid:7)(cid:8)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7)#(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)"(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)$(cid:2)%(cid:2)$(cid:10)(cid:2)(cid:15)(cid:10) (cid:2)(cid:7)(cid:15)(cid:8)(cid:16)&$(cid:14)(cid:2)#(cid:10)(cid:16)$(cid:2)(cid:31)(cid:16)(cid:28)"(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10) (cid:9)&"(cid:7)(cid:10)(cid:15)"(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)$(cid:2)(cid:31)(cid:16)(cid:28)"(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10) (cid:9)&"(cid:7)(cid:10)(cid:15)"(cid:2)"(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10) (cid:2)(cid:14)’(cid:8)(cid:14)(cid:14)$(cid:2)(cid:20)(cid:4)(cid:4)()(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)"(cid:7)$(cid:14)(cid:20) *(cid:20) (cid:21)(cid:7)#(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)$(cid:2) (cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6)%(cid:2)+(cid:29)(cid:23)(cid:20)((cid:6)(cid:20) ,(cid:22)!- ,(cid:28)"(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)#(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14) (cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)’(cid:28)(cid:8) (cid:2).(cid:28)(cid:16)&(cid:14)(cid:2)"(cid:11)(cid:10)/(cid:15)(cid:2)/(cid:7) (cid:11)(cid:10)& (cid:2) (cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)"(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)/(cid:7)(cid:15)(cid:17)!(cid:4)(cid:23)(cid:27)(cid:4)(cid:29)(cid:29), DS22057B-page 24  2007-2013 Microchip Technology Inc.

MCP1826/MCP1826S Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2007-2013 Microchip Technology Inc. DS22057B-page 25

MCP1826/MCP1826S (cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:28)(cid:29)(cid:7)(cid:11)(cid:11)(cid:9)(cid:30)(cid:31)(cid:13)(cid:11)(cid:14) (cid:6)(cid:9)!"(cid:7) (cid:12)(cid:14)(cid:12)(cid:13)(cid:26)"(cid:9)(cid:16)(cid:21)(cid:18)(cid:19)(cid:9)(cid:20)(cid:28)(cid:30)!(cid:4)##(cid:3)(cid:24) (cid:25)(cid:26)(cid:13)(cid:6)(cid:27) 0(cid:10)(cid:9)(cid:2) (cid:11)(cid:14)(cid:2)#(cid:10)" (cid:2)(cid:8)&(cid:9)(cid:9)(cid:14)(cid:15) (cid:2)(cid:12)(cid:28)(cid:8)1(cid:28)(cid:17)(cid:14)(cid:2)$(cid:9)(cid:28)/(cid:7)(cid:15)(cid:17)"2(cid:2)(cid:12)(cid:16)(cid:14)(cid:28)"(cid:14)(cid:2)"(cid:14)(cid:14)(cid:2) (cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)3(cid:28)(cid:8)1(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)(cid:31)(cid:7)(cid:8)(cid:28) (cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28) (cid:14)$(cid:2)(cid:28) (cid:2) (cid:11) (cid:12)-44///(cid:20)#(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)#4(cid:12)(cid:28)(cid:8)1(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D b2 E1 E 1 2 3 e e1 A A2 φ c b A1 L 5(cid:15)(cid:7) " (cid:6)(cid:19)88(cid:19)(cid:6)%(cid:13)%(cid:26)(cid:22) (cid:21)(cid:7)#(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:2)8(cid:7)#(cid:7) " (cid:6)(cid:19)6 69(cid:6) (cid:6)(cid:25): 6&#;(cid:14)(cid:9)(cid:2)(cid:10)(cid:31)(cid:2)8(cid:14)(cid:28)$" 6 * 8(cid:14)(cid:28)$(cid:2)3(cid:7) (cid:8)(cid:11) (cid:14) (cid:3)(cid:20)*(cid:4)(cid:2),(cid:22)! 9& "(cid:7)$(cid:14)(cid:2)8(cid:14)(cid:28)$(cid:2)3(cid:7) (cid:8)(cid:11) (cid:14)(cid:29) (cid:23)(cid:20)<(cid:4)(cid:2),(cid:22)! 9.(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)7(cid:14)(cid:7)(cid:17)(cid:11) (cid:25) = = (cid:29)(cid:20)?(cid:4) (cid:22) (cid:28)(cid:15)$(cid:10)(cid:31)(cid:31) (cid:25)(cid:29) (cid:4)(cid:20)(cid:4)(cid:3) = (cid:4)(cid:20)(cid:29)(cid:4) (cid:6)(cid:10)(cid:16)$(cid:14)$(cid:2)3(cid:28)(cid:8)1(cid:28)(cid:17)(cid:14)(cid:2)7(cid:14)(cid:7)(cid:17)(cid:11) (cid:25)(cid:3) (cid:29)(cid:20)((cid:4) (cid:29)(cid:20)<(cid:4) (cid:29)(cid:20)(cid:5)(cid:4) 9.(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)$ (cid:11) % <(cid:20)(cid:5)(cid:4) (cid:5)(cid:20)(cid:4)(cid:4) (cid:5)(cid:20)*(cid:4) (cid:6)(cid:10)(cid:16)$(cid:14)$(cid:2)3(cid:28)(cid:8)1(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)$ (cid:11) %(cid:29) *(cid:20)*(cid:4) *(cid:20)((cid:4) *(cid:20)(cid:5)(cid:4) 9.(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:15)(cid:17) (cid:11) (cid:21) <(cid:20)*(cid:4) <(cid:20)((cid:4) <(cid:20)(cid:5)(cid:4) 8(cid:14)(cid:28)$(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)1(cid:15)(cid:14)"" (cid:8) (cid:4)(cid:20)(cid:3)* (cid:4)(cid:20)*(cid:4) (cid:4)(cid:20)*( 8(cid:14)(cid:28)$(cid:2)>(cid:7)$ (cid:11) ; (cid:4)(cid:20)<(cid:4) (cid:4)(cid:20)(cid:5)< (cid:4)(cid:20)?(cid:23) (cid:13)(cid:28);(cid:2)8(cid:14)(cid:28)$(cid:2)>(cid:7)$ (cid:11) ;(cid:3) (cid:3)(cid:20)(cid:24)(cid:4) *(cid:20)(cid:4)(cid:4) *(cid:20)(cid:29)(cid:4) 0(cid:10)(cid:10) (cid:2)8(cid:14)(cid:15)(cid:17) (cid:11) 8 (cid:4)(cid:20)(cid:5)( = = 8(cid:14)(cid:28)$(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)@ = (cid:29)(cid:4)@ (cid:25)(cid:26)(cid:13)(cid:6)(cid:12)(cid:27) (cid:29)(cid:20) (cid:21)(cid:7)#(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)"(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)$(cid:2)%(cid:29)(cid:2)$(cid:10)(cid:2)(cid:15)(cid:10) (cid:2)(cid:7)(cid:15)(cid:8)(cid:16)&$(cid:14)(cid:2)#(cid:10)(cid:16)$(cid:2)(cid:31)(cid:16)(cid:28)"(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10) (cid:9)&"(cid:7)(cid:10)(cid:15)"(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)$(cid:2)(cid:31)(cid:16)(cid:28)"(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10) (cid:9)&"(cid:7)(cid:10)(cid:15)"(cid:2)"(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10) (cid:2)(cid:14)’(cid:8)(cid:14)(cid:14)$(cid:2)(cid:4)(cid:20)(cid:29)(cid:3)(cid:5)(cid:2)##(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)"(cid:7)$(cid:14)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7)#(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)$(cid:2) (cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6)%(cid:2)+(cid:29)(cid:23)(cid:20)((cid:6)(cid:20) ,(cid:22)!- ,(cid:28)"(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)#(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14) (cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)’(cid:28)(cid:8) (cid:2).(cid:28)(cid:16)&(cid:14)(cid:2)"(cid:11)(cid:10)/(cid:15)(cid:2)/(cid:7) (cid:11)(cid:10)& (cid:2) (cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)"(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)/(cid:7)(cid:15)(cid:17)!(cid:4)(cid:23)(cid:27)(cid:4)*(cid:3), DS22057B-page 26  2007-2013 Microchip Technology Inc.

MCP1826/MCP1826S (cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:28)(cid:29)(cid:7)(cid:11)(cid:11)(cid:9)(cid:30)(cid:31)(cid:13)(cid:11)(cid:14) (cid:6)(cid:9)!"(cid:7) (cid:12)(cid:14)(cid:12)(cid:13)(cid:26)"(cid:9)(cid:16)(cid:21)(cid:18)(cid:19)(cid:9)(cid:20)(cid:28)(cid:30)!(cid:4)##(cid:3)(cid:24) (cid:25)(cid:26)(cid:13)(cid:6)(cid:27) 0(cid:10)(cid:9)(cid:2) (cid:11)(cid:14)(cid:2)#(cid:10)" (cid:2)(cid:8)&(cid:9)(cid:9)(cid:14)(cid:15) (cid:2)(cid:12)(cid:28)(cid:8)1(cid:28)(cid:17)(cid:14)(cid:2)$(cid:9)(cid:28)/(cid:7)(cid:15)(cid:17)"2(cid:2)(cid:12)(cid:16)(cid:14)(cid:28)"(cid:14)(cid:2)"(cid:14)(cid:14)(cid:2) (cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)3(cid:28)(cid:8)1(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)(cid:31)(cid:7)(cid:8)(cid:28) (cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28) (cid:14)$(cid:2)(cid:28) (cid:2) (cid:11) (cid:12)-44///(cid:20)#(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)#4(cid:12)(cid:28)(cid:8)1(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)  2007-2013 Microchip Technology Inc. DS22057B-page 27

MCP1826/MCP1826S (cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)!"(cid:7) (cid:12)(cid:14)(cid:12)(cid:13)(cid:26)"(cid:9)(cid:30)(cid:31)(cid:13)(cid:11)(cid:14) (cid:6)(cid:9)(cid:16)(cid:22)(cid:18)(cid:19)(cid:9)(cid:20)!(cid:30)(cid:4)##$(cid:24) (cid:25)(cid:26)(cid:13)(cid:6)(cid:27) 0(cid:10)(cid:9)(cid:2) (cid:11)(cid:14)(cid:2)#(cid:10)" (cid:2)(cid:8)&(cid:9)(cid:9)(cid:14)(cid:15) (cid:2)(cid:12)(cid:28)(cid:8)1(cid:28)(cid:17)(cid:14)(cid:2)$(cid:9)(cid:28)/(cid:7)(cid:15)(cid:17)"2(cid:2)(cid:12)(cid:16)(cid:14)(cid:28)"(cid:14)(cid:2)"(cid:14)(cid:14)(cid:2) (cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)3(cid:28)(cid:8)1(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)(cid:31)(cid:7)(cid:8)(cid:28) (cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28) (cid:14)$(cid:2)(cid:28) (cid:2) (cid:11) (cid:12)-44///(cid:20)#(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)#4(cid:12)(cid:28)(cid:8)1(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) E CHAMFER A OPTIONAL φP A1 Q H1 D D1 L1 L b2 1 2 N b c e A2 e1 5(cid:15)(cid:7) " (cid:19)6!7%(cid:22) (cid:21)(cid:7)#(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:2)8(cid:7)#(cid:7) " (cid:6)(cid:19)6 69(cid:6) (cid:6)(cid:25): 6&#;(cid:14)(cid:9)(cid:2)(cid:10)(cid:31)(cid:2)3(cid:7)(cid:15)" 6 * 3(cid:7) (cid:8)(cid:11) (cid:14) (cid:20)(cid:29)(cid:4)(cid:4)(cid:2),(cid:22)! 9.(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)3(cid:7)(cid:15)(cid:2)3(cid:7) (cid:8)(cid:11) (cid:14)(cid:29) (cid:20)(cid:3)(cid:4)(cid:4)(cid:2),(cid:22)! 9.(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)7(cid:14)(cid:7)(cid:17)(cid:11) (cid:25) (cid:20)(cid:29)(cid:23)(cid:4) = (cid:20)(cid:29)(cid:24)(cid:4) (cid:13)(cid:28);(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)1(cid:15)(cid:14)"" (cid:25)(cid:29) (cid:20)(cid:4)(cid:3)(cid:4) = (cid:20)(cid:4)(( ,(cid:28)"(cid:14)(cid:2) (cid:10)(cid:2)8(cid:14)(cid:28)$ (cid:25)(cid:3) (cid:20)(cid:4)?(cid:4) = (cid:20)(cid:29)(cid:29)( 9.(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)$ (cid:11) % (cid:20)*((cid:5) = (cid:20)(cid:23)(cid:3)(cid:4) (cid:6)(cid:10)&(cid:15) (cid:7)(cid:15)(cid:17)(cid:2)7(cid:10)(cid:16)(cid:14)(cid:2)!(cid:14)(cid:15) (cid:14)(cid:9) A (cid:20)(cid:29)(cid:4)(cid:4) = (cid:20)(cid:29)(cid:3)(cid:4) 9.(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:15)(cid:17) (cid:11) (cid:21) (cid:20)(<(cid:4) = (cid:20)<((cid:4) (cid:6)(cid:10)(cid:16)$(cid:14)$(cid:2)3(cid:28)(cid:8)1(cid:28)(cid:17)(cid:14)(cid:2)8(cid:14)(cid:15)(cid:17) (cid:11) (cid:21)(cid:29) (cid:20)**(cid:4) = (cid:20)*(( (cid:13)(cid:28);(cid:2)8(cid:14)(cid:15)(cid:17) (cid:11) 7(cid:29) (cid:20)(cid:3)*(cid:4) = (cid:20)(cid:3)(cid:5)(cid:4) (cid:6)(cid:10)&(cid:15) (cid:7)(cid:15)(cid:17)(cid:2)7(cid:10)(cid:16)(cid:14)(cid:2)(cid:21)(cid:7)(cid:28)#(cid:14) (cid:14)(cid:9) (cid:3)3 (cid:20)(cid:29)*(cid:24) = (cid:20)(cid:29)(< 8(cid:14)(cid:28)$(cid:2)8(cid:14)(cid:15)(cid:17) (cid:11) 8 (cid:20)((cid:4)(cid:4) = (cid:20)(?(cid:4) 8(cid:14)(cid:28)$(cid:2)(cid:22)(cid:11)(cid:10)&(cid:16)$(cid:14)(cid:9) 8(cid:29) = = (cid:20)(cid:3)((cid:4) 8(cid:14)(cid:28)$(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)1(cid:15)(cid:14)"" (cid:8) (cid:20)(cid:4)(cid:29)(cid:3) = (cid:20)(cid:4)(cid:3)(cid:23) 8(cid:14)(cid:28)$(cid:2)>(cid:7)$ (cid:11) ; (cid:20)(cid:4)(cid:29)( (cid:20)(cid:4)(cid:3)(cid:5) (cid:20)(cid:4)(cid:23)(cid:4) (cid:22)(cid:11)(cid:10)&(cid:16)$(cid:14)(cid:9)(cid:2)>(cid:7)$ (cid:11) ;(cid:3) (cid:20)(cid:4)(cid:23)( (cid:20)(cid:4)((cid:5) (cid:20)(cid:4)(cid:5)(cid:4) (cid:25)(cid:26)(cid:13)(cid:6)(cid:12)(cid:27) (cid:29)(cid:20) (cid:21)(cid:7)#(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)"(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)$(cid:2)%(cid:2)$(cid:10)(cid:2)(cid:15)(cid:10) (cid:2)(cid:7)(cid:15)(cid:8)(cid:16)&$(cid:14)(cid:2)#(cid:10)(cid:16)$(cid:2)(cid:31)(cid:16)(cid:28)"(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10) (cid:9)&"(cid:7)(cid:10)(cid:15)"(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)$(cid:2)(cid:31)(cid:16)(cid:28)"(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10) (cid:9)&"(cid:7)(cid:10)(cid:15)"(cid:2)"(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10) (cid:2)(cid:14)’(cid:8)(cid:14)(cid:14)$(cid:2)(cid:20)(cid:4)(cid:4)()(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)"(cid:7)$(cid:14)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7)#(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)$(cid:2) (cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6)%(cid:2)+(cid:29)(cid:23)(cid:20)((cid:6)(cid:20) ,(cid:22)!- ,(cid:28)"(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)#(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14) (cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)’(cid:28)(cid:8) (cid:2).(cid:28)(cid:16)&(cid:14)(cid:2)"(cid:11)(cid:10)/(cid:15)(cid:2)/(cid:7) (cid:11)(cid:10)& (cid:2) (cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)"(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)/(cid:7)(cid:15)(cid:17)!(cid:4)(cid:23)(cid:27)(cid:4)*(cid:23), DS22057B-page 28  2007-2013 Microchip Technology Inc.

MCP1826/MCP1826S %(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)!(cid:19)(cid:9)(cid:20)(cid:21)(cid:21)(cid:10)(cid:22)(cid:23)(cid:24) (cid:25)(cid:26)(cid:13)(cid:6)(cid:27) 0(cid:10)(cid:9)(cid:2) (cid:11)(cid:14)(cid:2)#(cid:10)" (cid:2)(cid:8)&(cid:9)(cid:9)(cid:14)(cid:15) (cid:2)(cid:12)(cid:28)(cid:8)1(cid:28)(cid:17)(cid:14)(cid:2)$(cid:9)(cid:28)/(cid:7)(cid:15)(cid:17)"2(cid:2)(cid:12)(cid:16)(cid:14)(cid:28)"(cid:14)(cid:2)"(cid:14)(cid:14)(cid:2) (cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)3(cid:28)(cid:8)1(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)(cid:31)(cid:7)(cid:8)(cid:28) (cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28) (cid:14)$(cid:2)(cid:28) (cid:2) (cid:11) (cid:12)-44///(cid:20)#(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)#4(cid:12)(cid:28)(cid:8)1(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) E E1 L1 D1 D H 1 N b e BOTTOMVIEW TOPVIEW CHAMFER OPTIONAL A C2 φ A1 c L 5(cid:15)(cid:7) " (cid:19)6!7%(cid:22) (cid:21)(cid:7)#(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:2)8(cid:7)#(cid:7) " (cid:6)(cid:19)6 69(cid:6) (cid:6)(cid:25): 6&#;(cid:14)(cid:9)(cid:2)(cid:10)(cid:31)(cid:2)3(cid:7)(cid:15)" 6 ( 3(cid:7) (cid:8)(cid:11) (cid:14) (cid:20)(cid:4)<(cid:5)(cid:2),(cid:22)! 9.(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)7(cid:14)(cid:7)(cid:17)(cid:11) (cid:25) (cid:20)(cid:29)<(cid:4) = (cid:20)(cid:29)(cid:24)(cid:4) (cid:22) (cid:28)(cid:15)$(cid:10)(cid:31)(cid:31)(cid:2)(cid:2)(cid:30) (cid:25)(cid:29) (cid:20)(cid:4)(cid:4)(cid:4) = (cid:20)(cid:4)(cid:29)(cid:4) 9.(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)$ (cid:11) % (cid:20)*?(cid:4) = (cid:20)(cid:23)(cid:3)(cid:4) %’(cid:12)(cid:10)"(cid:14)$(cid:2)3(cid:28)$(cid:2)>(cid:7)$ (cid:11) %(cid:29) (cid:20)(cid:3)(cid:23)( = = (cid:6)(cid:10)(cid:16)$(cid:14)$(cid:2)3(cid:28)(cid:8)1(cid:28)(cid:17)(cid:14)(cid:2)8(cid:14)(cid:15)(cid:17) (cid:11) (cid:21) (cid:20)**(cid:4) = (cid:20)*?(cid:4) 9.(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:15)(cid:17) (cid:11) 7 (cid:20)((cid:23)(cid:24) = (cid:20)<(cid:3)( %’(cid:12)(cid:10)"(cid:14)$(cid:2)3(cid:28)$(cid:2)8(cid:14)(cid:15)(cid:17) (cid:11) (cid:21)(cid:29) (cid:20)(cid:3)(cid:5)(cid:4) = = 8(cid:14)(cid:28)$(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)1(cid:15)(cid:14)"" (cid:8) (cid:20)(cid:4)(cid:29)(cid:23) = (cid:20)(cid:4)(cid:3)(cid:24) 3(cid:28)$(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)1(cid:15)(cid:14)"" !(cid:3) (cid:20)(cid:4)(cid:23)( = (cid:20)(cid:4)<( 8(cid:14)(cid:28)$(cid:2)>(cid:7)$ (cid:11) ; (cid:20)(cid:4)(cid:3)(cid:4) = (cid:20)(cid:4)*(cid:24) 0(cid:10)(cid:10) (cid:2)8(cid:14)(cid:15)(cid:17) (cid:11) 8 (cid:20)(cid:4)<? = (cid:20)(cid:29)(cid:29)(cid:4) 3(cid:28)$(cid:2)8(cid:14)(cid:15)(cid:17) (cid:11) 8(cid:29) = = (cid:20)(cid:4)<(cid:5) 0(cid:10)(cid:10) (cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)@ = ?@ (cid:25)(cid:26)(cid:13)(cid:6)(cid:12)(cid:27) (cid:29)(cid:20) (cid:30)(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)(cid:31)(cid:7)(cid:8)(cid:28)(cid:15) (cid:2)!(cid:11)(cid:28)(cid:9)(cid:28)(cid:8) (cid:14)(cid:9)(cid:7)" (cid:7)(cid:8)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7)#(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)"(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)$(cid:2)%(cid:2)$(cid:10)(cid:2)(cid:15)(cid:10) (cid:2)(cid:7)(cid:15)(cid:8)(cid:16)&$(cid:14)(cid:2)#(cid:10)(cid:16)$(cid:2)(cid:31)(cid:16)(cid:28)"(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10) (cid:9)&"(cid:7)(cid:10)(cid:15)"(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)$(cid:2)(cid:31)(cid:16)(cid:28)"(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10) (cid:9)&"(cid:7)(cid:10)(cid:15)"(cid:2)"(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10) (cid:2)(cid:14)’(cid:8)(cid:14)(cid:14)$(cid:2)(cid:20)(cid:4)(cid:4)()(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)"(cid:7)$(cid:14)(cid:20) *(cid:20) (cid:21)(cid:7)#(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)$(cid:2) (cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6)%(cid:2)+(cid:29)(cid:23)(cid:20)((cid:6)(cid:20) ,(cid:22)!- ,(cid:28)"(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)#(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14) (cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)’(cid:28)(cid:8) (cid:2).(cid:28)(cid:16)&(cid:14)(cid:2)"(cid:11)(cid:10)/(cid:15)(cid:2)/(cid:7) (cid:11)(cid:10)& (cid:2) (cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)"(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)/(cid:7)(cid:15)(cid:17)!(cid:4)(cid:23)(cid:27)(cid:4)(cid:29)(cid:3),  2007-2013 Microchip Technology Inc. DS22057B-page 29

MCP1826/MCP1826S Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22057B-page 30  2007-2013 Microchip Technology Inc.

MCP1826/MCP1826S %(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:28)(cid:29)(cid:7)(cid:11)(cid:11)(cid:9)(cid:30)(cid:31)(cid:13)(cid:11)(cid:14) (cid:6)(cid:9)!"(cid:7) (cid:12)(cid:14)(cid:12)(cid:13)(cid:26)"(cid:9)(cid:16)(cid:21)&(cid:19)(cid:9)(cid:20)(cid:28)(cid:30)!(cid:4)##(cid:3)(cid:24) (cid:25)(cid:26)(cid:13)(cid:6)(cid:27) 0(cid:10)(cid:9)(cid:2) (cid:11)(cid:14)(cid:2)#(cid:10)" (cid:2)(cid:8)&(cid:9)(cid:9)(cid:14)(cid:15) (cid:2)(cid:12)(cid:28)(cid:8)1(cid:28)(cid:17)(cid:14)(cid:2)$(cid:9)(cid:28)/(cid:7)(cid:15)(cid:17)"2(cid:2)(cid:12)(cid:16)(cid:14)(cid:28)"(cid:14)(cid:2)"(cid:14)(cid:14)(cid:2) (cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)3(cid:28)(cid:8)1(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)(cid:31)(cid:7)(cid:8)(cid:28) (cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28) (cid:14)$(cid:2)(cid:28) (cid:2) (cid:11) (cid:12)-44///(cid:20)#(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)#4(cid:12)(cid:28)(cid:8)1(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D b2 E1 E 1 2 3 4 N e e1 A A2 φ c b A1 L 5(cid:15)(cid:7) " (cid:6)(cid:19)88(cid:19)(cid:6)%(cid:13)%(cid:26)(cid:22) (cid:21)(cid:7)#(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:2)8(cid:7)#(cid:7) " (cid:6)(cid:19)6 69(cid:6) (cid:6)(cid:25): 6&#;(cid:14)(cid:9)(cid:2)(cid:10)(cid:31)(cid:2)8(cid:14)(cid:28)$" 6 ( 8(cid:14)(cid:28)$(cid:2)3(cid:7) (cid:8)(cid:11) (cid:14) (cid:29)(cid:20)(cid:3)(cid:5)(cid:2),(cid:22)! 9& "(cid:7)$(cid:14)(cid:2)8(cid:14)(cid:28)$(cid:2)3(cid:7) (cid:8)(cid:11) (cid:14)(cid:29) ((cid:20)(cid:4)?(cid:2),(cid:22)! 9.(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)7(cid:14)(cid:7)(cid:17)(cid:11) (cid:25) = = (cid:29)(cid:20)?(cid:4) (cid:22) (cid:28)(cid:15)$(cid:10)(cid:31)(cid:31) (cid:25)(cid:29) (cid:4)(cid:20)(cid:4)(cid:3) (cid:4)(cid:20)(cid:4)< (cid:4)(cid:20)(cid:29)(cid:4) (cid:6)(cid:10)(cid:16)$(cid:14)$(cid:2)3(cid:28)(cid:8)1(cid:28)(cid:17)(cid:14)(cid:2)7(cid:14)(cid:7)(cid:17)(cid:11) (cid:25)(cid:3) (cid:29)(cid:20)(( (cid:29)(cid:20)<(cid:4) (cid:29)(cid:20)<( 9.(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)$ (cid:11) % <(cid:20)?< (cid:5)(cid:20)(cid:4)(cid:4) (cid:5)(cid:20)(cid:3)< (cid:6)(cid:10)(cid:16)$(cid:14)$(cid:2)3(cid:28)(cid:8)1(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)$ (cid:11) %(cid:29) *(cid:20)(cid:23)( *(cid:20)((cid:4) *(cid:20)(( 9.(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:15)(cid:17) (cid:11) (cid:21) <(cid:20)(cid:23)( <(cid:20)((cid:4) <(cid:20)(( 8(cid:14)(cid:28)$(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)1(cid:15)(cid:14)"" (cid:8) (cid:4)(cid:20)(cid:3)(cid:23) (cid:4)(cid:20)(cid:3)? (cid:4)(cid:20)*(cid:3) 8(cid:14)(cid:28)$(cid:2)>(cid:7)$ (cid:11) ; (cid:4)(cid:20)(cid:23)(cid:29) (cid:4)(cid:20)(cid:23)((cid:5) (cid:4)(cid:20)((cid:29) (cid:13)(cid:28);(cid:2)8(cid:14)(cid:28)$(cid:2)>(cid:7)$ (cid:11) ;(cid:3) (cid:3)(cid:20)(cid:24)( *(cid:20)(cid:4)(cid:4) *(cid:20)(cid:4)( 0(cid:10)(cid:10) (cid:2)8(cid:14)(cid:15)(cid:17) (cid:11) 8 (cid:4)(cid:20)(cid:24)(cid:29) = (cid:29)(cid:20)(cid:29)(cid:23) 8(cid:14)(cid:28)$(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)@ (cid:23)@ ?@ (cid:25)(cid:26)(cid:13)(cid:6)(cid:12)(cid:27) (cid:29)(cid:20) (cid:21)(cid:7)#(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)"(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)$(cid:2)%(cid:29)(cid:2)$(cid:10)(cid:2)(cid:15)(cid:10) (cid:2)(cid:7)(cid:15)(cid:8)(cid:16)&$(cid:14)(cid:2)#(cid:10)(cid:16)$(cid:2)(cid:31)(cid:16)(cid:28)"(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10) (cid:9)&"(cid:7)(cid:10)(cid:15)"(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)$(cid:2)(cid:31)(cid:16)(cid:28)"(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10) (cid:9)&"(cid:7)(cid:10)(cid:15)"(cid:2)"(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10) (cid:2)(cid:14)’(cid:8)(cid:14)(cid:14)$(cid:2)(cid:4)(cid:20)(cid:29)(cid:3)(cid:5)(cid:2)##(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)"(cid:7)$(cid:14)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7)#(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)$(cid:2) (cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6)%(cid:2)+(cid:29)(cid:23)(cid:20)((cid:6)(cid:20) ,(cid:22)!- ,(cid:28)"(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)#(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14) (cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)’(cid:28)(cid:8) (cid:2).(cid:28)(cid:16)&(cid:14)(cid:2)"(cid:11)(cid:10)/(cid:15)(cid:2)/(cid:7) (cid:11)(cid:10)& (cid:2) (cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)"(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)/(cid:7)(cid:15)(cid:17)!(cid:4)(cid:23)(cid:27)(cid:29)*(cid:5),  2007-2013 Microchip Technology Inc. DS22057B-page 31

MCP1826/MCP1826S %(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:28)(cid:29)(cid:7)(cid:11)(cid:11)(cid:9)(cid:30)(cid:31)(cid:13)(cid:11)(cid:14) (cid:6)(cid:9)!"(cid:7) (cid:12)(cid:14)(cid:12)(cid:13)(cid:26)"(cid:9)(cid:16)(cid:21)&(cid:19)(cid:9)(cid:20)(cid:28)(cid:30)!(cid:4)##(cid:3)(cid:24) (cid:25)(cid:26)(cid:13)(cid:6)(cid:27) 0(cid:10)(cid:9)(cid:2) (cid:11)(cid:14)(cid:2)#(cid:10)" (cid:2)(cid:8)&(cid:9)(cid:9)(cid:14)(cid:15) (cid:2)(cid:12)(cid:28)(cid:8)1(cid:28)(cid:17)(cid:14)(cid:2)$(cid:9)(cid:28)/(cid:7)(cid:15)(cid:17)"2(cid:2)(cid:12)(cid:16)(cid:14)(cid:28)"(cid:14)(cid:2)"(cid:14)(cid:14)(cid:2) (cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)3(cid:28)(cid:8)1(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)(cid:31)(cid:7)(cid:8)(cid:28) (cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28) (cid:14)$(cid:2)(cid:28) (cid:2) (cid:11) (cid:12)-44///(cid:20)#(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)#4(cid:12)(cid:28)(cid:8)1(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) DS22057B-page 32  2007-2013 Microchip Technology Inc.

MCP1826/MCP1826S %(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)!"(cid:7) (cid:12)(cid:14)(cid:12)(cid:13)(cid:26)"(cid:9)(cid:30)(cid:31)(cid:13)(cid:11)(cid:14) (cid:6)(cid:9)(cid:16)(cid:22)!(cid:19)(cid:9)(cid:20)!(cid:30)(cid:4)##$(cid:24) (cid:25)(cid:26)(cid:13)(cid:6)(cid:27) 0(cid:10)(cid:9)(cid:2) (cid:11)(cid:14)(cid:2)#(cid:10)" (cid:2)(cid:8)&(cid:9)(cid:9)(cid:14)(cid:15) (cid:2)(cid:12)(cid:28)(cid:8)1(cid:28)(cid:17)(cid:14)(cid:2)$(cid:9)(cid:28)/(cid:7)(cid:15)(cid:17)"2(cid:2)(cid:12)(cid:16)(cid:14)(cid:28)"(cid:14)(cid:2)"(cid:14)(cid:14)(cid:2) (cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)3(cid:28)(cid:8)1(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)(cid:31)(cid:7)(cid:8)(cid:28) (cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28) (cid:14)$(cid:2)(cid:28) (cid:2) (cid:11) (cid:12)-44///(cid:20)#(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)#4(cid:12)(cid:28)(cid:8)1(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) E A φP CHAMFER A1 OPTIONAL Q H1 D D1 L 1 2 3 N b e c e1 A2 5(cid:15)(cid:7) " (cid:19)6!7%(cid:22) (cid:21)(cid:7)#(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:2)8(cid:7)#(cid:7) " (cid:6)(cid:19)6 69(cid:6) (cid:6)(cid:25): 6&#;(cid:14)(cid:9)(cid:2)(cid:10)(cid:31)(cid:2)3(cid:7)(cid:15)" 6 ( 3(cid:7) (cid:8)(cid:11) (cid:14) (cid:20)(cid:4)<(cid:5)(cid:2),(cid:22)! 9.(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)3(cid:7)(cid:15)(cid:2)3(cid:7) (cid:8)(cid:11) (cid:14)(cid:29) (cid:20)(cid:3)<?(cid:2),(cid:22)! 9.(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)7(cid:14)(cid:7)(cid:17)(cid:11) (cid:25) (cid:20)(cid:29)(cid:23)(cid:4) = (cid:20)(cid:29)(cid:24)(cid:4) 9.(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)$ (cid:11) % (cid:20)*?(cid:4) = (cid:20)(cid:23)(cid:3)(cid:4) 9.(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:15)(cid:17) (cid:11) (cid:21) (cid:20)(<(cid:4) = (cid:20)<((cid:4) (cid:6)(cid:10)(cid:16)$(cid:14)$(cid:2)3(cid:28)(cid:8)1(cid:28)(cid:17)(cid:14)(cid:2)8(cid:14)(cid:15)(cid:17) (cid:11) (cid:21)(cid:29) (cid:20)**(cid:4) = (cid:20)*(( (cid:13)(cid:28);(cid:2)8(cid:14)(cid:15)(cid:17) (cid:11) 7(cid:29) (cid:20)(cid:3)(cid:4)(cid:23) = (cid:20)(cid:3)(cid:24)* (cid:13)(cid:28);(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)1(cid:15)(cid:14)"" (cid:25)(cid:29) (cid:20)(cid:4)(cid:3)(cid:4) = (cid:20)(cid:4)(( (cid:6)(cid:10)&(cid:15) (cid:7)(cid:15)(cid:17)(cid:2)7(cid:10)(cid:16)(cid:14)(cid:2)!(cid:14)(cid:15) (cid:14)(cid:9) A (cid:20)(cid:29)(cid:4)(cid:4) = (cid:20)(cid:29)(cid:3)(cid:4) (cid:6)(cid:10)&(cid:15) (cid:7)(cid:15)(cid:17)(cid:2)7(cid:10)(cid:16)(cid:14)(cid:2)(cid:21)(cid:7)(cid:28)#(cid:14) (cid:14)(cid:9) (cid:3)3 (cid:20)(cid:29)*(cid:24) = (cid:20)(cid:29)(< 8(cid:14)(cid:28)$(cid:2)8(cid:14)(cid:15)(cid:17) (cid:11) 8 (cid:20)(cid:23)?(cid:3) = (cid:20)((cid:24)(cid:4) ,(cid:28)"(cid:14)(cid:2) (cid:10)(cid:2),(cid:10) (cid:10)#(cid:2)(cid:10)(cid:31)(cid:2)8(cid:14)(cid:28)$ (cid:25)(cid:3) (cid:20)(cid:4)?(cid:4) = (cid:20)(cid:29)(cid:29)( 8(cid:14)(cid:28)$(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)1(cid:15)(cid:14)"" (cid:8) (cid:20)(cid:4)(cid:29)(cid:3) = (cid:20)(cid:4)(cid:3)( 8(cid:14)(cid:28)$(cid:2)>(cid:7)$ (cid:11) ; (cid:20)(cid:4)(cid:29)( (cid:20)(cid:4)(cid:3)(cid:5) (cid:20)(cid:4)(cid:23)(cid:4) (cid:25)(cid:26)(cid:13)(cid:6)(cid:12)(cid:27) (cid:29)(cid:20) (cid:21)(cid:7)#(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)"(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)$(cid:2)%(cid:2)$(cid:10)(cid:2)(cid:15)(cid:10) (cid:2)(cid:7)(cid:15)(cid:8)(cid:16)&$(cid:14)(cid:2)#(cid:10)(cid:16)$(cid:2)(cid:31)(cid:16)(cid:28)"(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10) (cid:9)&"(cid:7)(cid:10)(cid:15)"(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)$(cid:2)(cid:31)(cid:16)(cid:28)"(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10) (cid:9)&"(cid:7)(cid:10)(cid:15)"(cid:2)"(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10) (cid:2)(cid:14)’(cid:8)(cid:14)(cid:14)$(cid:2)(cid:20)(cid:4)(cid:4)()(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)"(cid:7)$(cid:14)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7)#(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)$(cid:2) (cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6)%(cid:2)+(cid:29)(cid:23)(cid:20)((cid:6)(cid:20) ,(cid:22)!- ,(cid:28)"(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)#(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14) (cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)’(cid:28)(cid:8) (cid:2).(cid:28)(cid:16)&(cid:14)(cid:2)"(cid:11)(cid:10)/(cid:15)(cid:2)/(cid:7) (cid:11)(cid:10)& (cid:2) (cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)"(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)/(cid:7)(cid:15)(cid:17)!(cid:4)(cid:23)(cid:27)(cid:4)*<,  2007-2013 Microchip Technology Inc. DS22057B-page 33

MCP1826/MCP1826S NOTES: DS22057B-page 34  2007-2013 Microchip Technology Inc.

MCP1826/MCP1826S APPENDIX A: REVISION HISTORY Revision B (February 2013) The following is the list of modifications: • Updated the value of V in DROPOUT(max) Section5.1 “Typical Application”. Revision A (August 2007) • Original Release of this Document.  2007-2013 Microchip Technology Inc. DS22057B-page 35

MCP1826/MCP1826S PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. XX X X X/ XX Examples: a) MCP1826-0802E/XX: 0.8V LDO Regulator Device Output Feature Tolerance Temp. Package b) MCP1826-1002E/XX: 1.0V LDO Regulator Voltage Code c) MCP1826-1202E/XX: 1.2V LDO Regulator d) MCP1826-1802E/XX 1.8V LDO Regulator Device: MCP1826: 1000mA Low Dropout Regulator e) MCP1826-2502EXX: 25V LDO Regulator MCP1826T: 1000mA Low Dropout Regulator f) MCP1826-3002E/XX: 3.0V LDO Regulator Tape and Reel g) MCP1826-3302E/XX 3.3V LDO Regulator MCP1826S: 1000mA Low Dropout Regulator h) MCP1826-5002E/XX: 5.0V LDO Regulator MCP1826ST:1000mA Low Dropout Regulator Tape and Reel i) MCP1826-ADJE/XX: ADJ LDO Regulator a) MCP1826S-0802E/XX:0.8V LDO Regulator Output Voltage *: 08 = 0.8V “Standard” 12 = 1.2V “Standard” b) MCP1826S-1002E/XX:1.0V LDO Regulator 18 = 1.8V “Standard” c) MCP1826S-1202E/XX1.2V LDO Regulator 25 = 2.5V “Standard” d) MCP1826S-1802E/XX1.8V LDO Regulator 30 = 3.0V “Standard” 33 = 3.3V “Standard” e) MCP1826S-2502E/XX2.5V LDO Regulator 50 = 5.0V “Standard” f) MCP1826S-2502E/XX3.0V LDO Regulator ADJ= Adjustable Output Voltage ** (MCP1826 only) g) MCP1826S-3302E/XX3.3V LDO Regulator *Contact factory for other output voltage options h) MCP1826S-5002E/XX5.0V LDO Regulator ** When ADJ is used, the “extra feature code” and “tolerance” columns do not apply. Refer to examples. Extra Feature Code: 0 = Fixed XX = AB for 3LD TO-220 package = AT for 5LD TO-220 package = DB for 3LD SOT-223 package Tolerance: 2 = 2.0% (Standard) = DC for 5LD SOT-223 package = EB for 3LD DDPAK package Temperature: E = -40C to +125C = ET for 5LD DDPAK package Package Type: AB = Plastic Transistor Outline, TO-220, 3-lead AT = Plastic Transistor Outline, TO-220, 5-lead DB = Plastic Transistor Outline, SOT-223, 3-lead DC = Plastic Transistor Outline, SOT-223, 5-lead EB = Plastic, DDPAK, 3-lead ET = Plastic, DDPAK, 5-lead Note: ADJ (Adjustable) only available in 5-lead version. DS22057B-page 36  2007-2013 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, ensure that your application meets with your specifications. PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash MICROCHIP MAKES NO REPRESENTATIONS OR and UNI/O are registered trademarks of Microchip Technology WARRANTIES OF ANY KIND WHETHER EXPRESS OR Incorporated in the U.S.A. and other countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MTP, SEEVAL and The Embedded Control Solutions QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Silicon Storage Technology is a registered trademark of devices in life support and/or safety applications is entirely at Microchip Technology Inc. in other countries. the buyer’s risk, and the buyer agrees to defend, indemnify and Analog-for-the-Digital Age, Application Maestro, BodyCom, hold harmless Microchip from any and all damages, claims, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, suits, or expenses resulting from such use. No licenses are dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, conveyed, implicitly or otherwise, under any Microchip ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial intellectual property rights. Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. & KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2007-2013, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 9781620769850 QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures == ISO/TS 16949 == are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2007-2013 Microchip Technology Inc. DS22057B-page 37

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: MCP1826-0802E/AT MCP1826-0802E/ET MCP1826-1202E/AT MCP1826-1202E/ET MCP1826-1802E/AT MCP1826-1802E/ET MCP1826-2502E/AT MCP1826-2502E/ET MCP1826-3002E/AT MCP1826-3002E/ET MCP1826-3302E/AT MCP1826-3302E/ET MCP1826-5002E/AT MCP1826-5002E/ET MCP1826-ADJE/AT MCP1826- ADJE/ET MCP1826S-0802E/AB MCP1826S-0802E/DB MCP1826S-0802E/EB MCP1826S-1202E/AB MCP1826S- 1202E/DB MCP1826S-1202E/EB MCP1826S-1802E/AB MCP1826S-1802E/DB MCP1826S-1802E/EB MCP1826S- 2502E/AB MCP1826S-2502E/DB MCP1826S-2502E/EB MCP1826S-3002E/AB MCP1826S-3002E/DB MCP1826S- 3002E/EB MCP1826S-3302E/AB MCP1826S-3302E/DB MCP1826S-3302E/EB MCP1826S-5002E/AB MCP1826S- 5002E/DB MCP1826S-5002E/EB MCP1826ST-0802E/DB MCP1826ST-0802E/EB MCP1826ST-1202E/DB MCP1826ST-1202E/EB MCP1826ST-1802E/DB MCP1826ST-1802E/EB MCP1826ST-2502E/DB MCP1826ST- 2502E/EB MCP1826ST-3002E/DB MCP1826ST-3002E/EB MCP1826ST-3302E/DB MCP1826ST-3302E/EB MCP1826ST-5002E/DB MCP1826ST-5002E/EB MCP1826T-0802E/DC MCP1826T-0802E/ET MCP1826T-1202E/DC MCP1826T-1202E/ET MCP1826T-1802E/DC MCP1826T-1802E/ET MCP1826T-2502E/DC MCP1826T-2502E/ET MCP1826T-3002E/DC MCP1826T-3002E/ET MCP1826T-3302E/ET MCP1826T-5002E/DC MCP1826T-5002E/ET MCP1826T-ADJE/DC MCP1826T-ADJE/ET