MCP1825/MCP1825S 500 mA, Low Voltage, Low Quiescent Current LDO Regulator Features Description • 500mA Output Current Capability The MCP1825/MCP1825S is a 500mA Low Dropout • Input Operating Voltage Range: 2.1V to 6.0V (LDO) linear regulator that provides high current and low output voltages. The MCP1825 comes in a fixed or • Adjustable Output Voltage Range: 0.8V to 5.0V adjustable output voltage version, with an output (MCP1825 only) voltage range of 0.8V to 5.0V. The 500mA output • Standard Fixed Output Voltages: current capability, combined with the low output voltage - 0.8V, 1.2V, 1.8V, 2.5V, 3.0V, 3.3V, 5.0V capability, make the MCP1825 a good choice for new • Other Fixed Output Voltage Options Available sub-1.8V output voltage LDO applications that have Upon Request high current demands. The MCP1825S is a 3-pin fixed • Low Dropout Voltage: 210mV Typical at 500mA voltage version. • Typical Output Voltage Tolerance: 0.5% The MCP1825/MCP1825S is stable using ceramic • Stable with 1.0µF Ceramic Output Capacitor output capacitors that inherently provide lower output noise and reduce the size and cost of the entire • Fast response to Load Transients regulator solution. Only 1µF of output capacitance is • Low Supply Current: 120µA (typical) needed to stabilize the LDO. • Low Shutdown Supply Current: 0.1µA (typical) (MCP1825 only) Using CMOS construction, the quiescent current consumed by the MCP1825/MCP1825S is typically • Fixed Delay on Power Good Output less than 120µA over the entire input voltage range, (MCP1825 only) making it attractive for portable computing applications • Short Circuit Current Limiting and that demand high output current. The MCP1825 Overtemperature Protection versions have a Shutdown (SHDN) pin. When shut • TO-263-5 (DDPAK-5), TO-220-5, SOT-223-5 down, the quiescent current is reduced to less than Package Options (MCP1825). 0.1µA. • TO-263-3 (DDPAK-3), TO-220-3, SOT-223-3 On the MCP1825 fixed output versions, the scaled- Package Options (MCP1825S). down output voltage is internally monitored and a power good (PWRGD) output is provided when the Applications output is within 92% of regulation (typical). The PWRGD delay is internally fixed at 110µs (typical). • High-Speed Driver Chipset Power • Networking Backplane Cards The overtemperature and short circuit current-limiting provide additional protection for the LDO during system • Notebook Computers fault conditions. • Network Interface Cards • Palmtop Computers • 2.5V to 1.XV Regulators © 2008 Microchip Technology Inc. DS22056B-page 1

MCP1825/MCP1825S Package Types MCP1825 MCP1825S DDPAK-5 TO-220-5 DDPAK-3 TO-220-3 Fixed/Adjustable 1 2 3 1 2 3 1 2 3 4 5 1 2 3 4 5 SOT-223-5 SOT-223-3 6 4 1 2 3 4 5 1 2 3 Pin Fixed Adjustable Pin 1 SHDN SHDN 1 VIN 2 V V 2 GND (TAB) IN IN 3 V 3 GND (TAB) GND (TAB) OUT 4 GND (TAB) 4 V V OUT OUT 5 PWRGD ADJ 6 GND (TAB) GND (TAB) DS22056B-page 2 © 2008 Microchip Technology Inc.

MCP1825/MCP1825S Typical Applications MCP1825 Fixed Output Voltage PWRGD R 1 On 100kΩ Off SHDN 1 VIN = 2.3V to 2.8V VIN VOUT VOUT = 1.8V @ 500mA GND C 1 C 4.7µF 2 1µF MCP1825 Adjustable Output Voltage V ADJ R 2 20kΩ R 1 On 40kΩ Off SHDN VIN = 2.1V to 2.8V VIN 1 VOUT VOUT = 1.2V @ 500mA C 1 C 4.7µF 2 1µF GND © 2008 Microchip Technology Inc. DS22056B-page 3

MCP1825/MCP1825S Functional Block Diagram - Adjustable Output PMOS VIN VOUT Undervoltage Lock Out (UVLO) I SNS Cf Rf SHDN ADJ/SENSE + Driver w/limit EA and SHDN Overtemperature – Sensing SHDN V REF VIN SHDN Reference Soft-Start Comp T DELAY GND 92% of V REF DS22056B-page 4 © 2008 Microchip Technology Inc.

MCP1825/MCP1825S Functional Block Diagram - Fixed Output (3-Pin) PMOS VIN VOUT Undervoltage Sense Lock Out (UVLO) I SNS Cf Rf SHDN + Driver w/limit EA and SHDN Overtemperature – Sensing SHDN V REF VIN SHDN Reference Soft-Start Comp T DELAY GND 92% of V REF © 2008 Microchip Technology Inc. DS22056B-page 5

MCP1825/MCP1825S Functional Block Diagram - Fixed Output (5-Pin) PMOS VIN VOUT Undervoltage Sense Lock Out (UVLO) I SNS Cf Rf SHDN + Driver w/limit EA and SHDN Overtemperature – Sensing SHDN V REF VIN SHDN Reference Soft-Start PWRGD Comp T DELAY GND 92% of V REF DS22056B-page 6 © 2008 Microchip Technology Inc.

MCP1825/MCP1825S 1.0 ELECTRICAL † Notice: Stresses above those listed under “Maximum Rat- ings” may cause permanent damage to the device. This is a CHARACTERISTICS stress rating only and functional operation of the device at those or any other conditions above those indicated in the Absolute Maximum Ratings † operational listings of this specification is not implied. Expo- sure to maximum rating conditions for extended periods may VIN....................................................................................6.5V affect device reliability. Maximum Voltage on Any Pin..(GND – 0.3V) to (V + 0.3)V DD Maximum Power Dissipation.........Internally-Limited (Note6) Output Short Circuit Duration................................Continuous Storage temperature.....................................-65°C to +150°C Maximum Junction Temperature, T ...........................+150°C J ESD protection on all pins (HBM/MM)........... ≥ 4kV; ≥ 300V AC/DC CHARACTERISTICS Electrical Specifications: Unless otherwise noted, V = V + V , Note1, V = 1.8V for Adjustable Output, IN OUT(MAX) DROPOUT(MAX) R I = 1mA, C = C = 4.7µF (X7R Ceramic), T = +25°C. OUT IN OUT A Boldface type applies for junction temperatures, T (Note7) of -40°C to +125°C J Parameters Sym Min Typ Max Units Conditions Input Operating Voltage V 2.1 6.0 V Note1 IN Input Quiescent Current I — 120 220 µA I = 0mA, V = 0.8V to q L OUT 5.0V Input Quiescent Current for I — 0.1 3 µA SHDN = GND SHDN SHDN Mode Maximum Output Current I 500 — — mA V = 2.1V to 6.0V OUT IN V = 0.8V to 5.0V, Note1 R Line Regulation ΔV / — ±0.05 ±0.16 %/V (Note1) ≤ V ≤ 6V OUT IN (V x ΔV ) OUT IN Load Regulation ΔV /V -1.0 ±0.5 1.0 % I = 1mA to 500mA, OUT OUT OUT (Note4) Output Short Circuit Current I — 1.2 — A R <0.1Ω, Peak Current OUT_SC LOAD Adjust Pin Characteristics (Adjustable Output Only) Adjust Pin Reference Voltage V 0.402 0.410 0.418 V V = 2.1V to V =6.0V, ADJ IN IN I = 1mA OUT Adjust Pin Leakage Current I -10 ±0.01 +10 nA V = 6.0V, V =0Vto6V ADJ IN ADJ Adjust Temperature Coefficient TCV — 40 — ppm/°C Note3 OUT Fixed-Output Characteristics (Fixed Output Only) Voltage Regulation V V - 2.5% V ±0.5% V + 2.5% V Note2 OUT R R R Note 1: The minimum V must meet two conditions: V ≥ 2.1V and V ≥ V + V IN IN IN OUT(MAX) DROPOUT(MAX). 2: V is the nominal regulator output voltage for the fixed cases. V = 1.2V, 1.8V, etc. V is the desired set point output R R R voltage for the adjustable cases. V = V ((R /R )+1). Figure4-1. R ADJ* 1 2 3: TCV = (V – V ) *106 / (V * ΔTemperature). V is the highest voltage measured over the OUT OUT-HIGH OUT-LOW R OUT-HIGH temperature range. V is the lowest voltage measured over the temperature range. OUT-LOW 4: Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is tested over a load range from 1mA to the maximum specified output current. 5: Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its nominal value that was measured with an input voltage of V = V + V . IN OUT(MAX) DROPOUT(MAX) 6: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air. (i.e., T , T , θ ). Exceeding the maximum allowable power A J JA dissipation will cause the device operating junction temperature to exceed the maximum +150°C rating. Sustained junction temperatures above 150°C can impact device reliability. 7: The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the desired junction temperature. The test time is small enough such that the rise in the junction temperature over the ambient temperature is not significant. © 2008 Microchip Technology Inc. DS22056B-page 7

MCP1825/MCP1825S AC/DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise noted, V = V + V , Note1, V = 1.8V for Adjustable Output, IN OUT(MAX) DROPOUT(MAX) R I = 1mA, C = C = 4.7µF (X7R Ceramic), T = +25°C. OUT IN OUT A Boldface type applies for junction temperatures, T (Note7) of -40°C to +125°C J Parameters Sym Min Typ Max Units Conditions Dropout Characteristics Dropout Voltage V — 210 350 mV Note5, I = 500mA, DROPOUT OUT V =2.1V IN(MIN) Power Good Characteristics PWRGD Input Voltage Operat- V 1.0 — 6.0 V T = +25°C PWRGD_VIN A ing Range 1.2 — 6.0 T = -40°C to +125°C A For V < 2.1V, I =100µA IN SINK PWRGD Threshold Voltage V %V Falling Edge PWRGD_TH OUT (Referenced to V ) OUT 89 92 95 V < 2.5V Fixed, OUT V = Adj. OUT 90 92 94 V >= 2.5V Fixed OUT PWRGD Threshold Hysteresis V 1.0 2.0 3.0 %V PWRGD_HYS OUT PWRGD Output Voltage Low V — 0.2 0.4 V I = 1.2mA, PWRGD_L PWRGDSINK ADJ = 0V PWRGD Leakage P _ — 1 — nA V = V = 6.0V WRGD LK PWRGD IN PWRGD Time Delay T — 110 — µs Rising Edge PG R = 10kΩ PULLUP Detect Threshold to PWRGD T — 200 — µs V = V + 20mV VDET-PWRGD OUT PWRGD_TH Active Time Delay to V - 20mV PWRGD_TH Shutdown Input Logic High Input V 45 — — %V V = 2.1V to 6.0V SHDN-HIGH IN IN Logic Low Input V — — 15 %V V = 2.1V to 6.0V SHDN-LOW IN IN SHDN Input Leakage Current SHDN -0.1 ±0.001 +0.1 µA V =6V, SHDN =V , ILK IN IN SHDN = GND AC Performance Output Delay From SHDN T — 100 — µs SHDN = GND to V , OR IN V = GND to 95% V OUT R Output Noise e — 2.0 — µV/√Hz I = 200mA, f = 1kHz, N OUT C = 10µF (X7R Ceramic), OUT V = 2.5V OUT Note 1: The minimum V must meet two conditions: V ≥ 2.1V and V ≥ V + V IN IN IN OUT(MAX) DROPOUT(MAX). 2: V is the nominal regulator output voltage for the fixed cases. V = 1.2V, 1.8V, etc. V is the desired set point output R R R voltage for the adjustable cases. V = V ((R /R )+1). Figure4-1. R ADJ* 1 2 3: TCV = (V – V ) *106 / (V * ΔTemperature). V is the highest voltage measured over the OUT OUT-HIGH OUT-LOW R OUT-HIGH temperature range. V is the lowest voltage measured over the temperature range. OUT-LOW 4: Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is tested over a load range from 1mA to the maximum specified output current. 5: Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its nominal value that was measured with an input voltage of V = V + V . IN OUT(MAX) DROPOUT(MAX) 6: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air. (i.e., T , T , θ ). Exceeding the maximum allowable power A J JA dissipation will cause the device operating junction temperature to exceed the maximum +150°C rating. Sustained junction temperatures above 150°C can impact device reliability. 7: The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the desired junction temperature. The test time is small enough such that the rise in the junction temperature over the ambient temperature is not significant. DS22056B-page 8 © 2008 Microchip Technology Inc.

MCP1825/MCP1825S AC/DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise noted, V = V + V , Note1, V = 1.8V for Adjustable Output, IN OUT(MAX) DROPOUT(MAX) R I = 1mA, C = C = 4.7µF (X7R Ceramic), T = +25°C. OUT IN OUT A Boldface type applies for junction temperatures, T (Note7) of -40°C to +125°C J Parameters Sym Min Typ Max Units Conditions Power Supply Ripple Rejection PSRR — 60 — dB f = 100Hz, C = 4.7µF, OUT Ratio I = 100µA, OUT V = 100mV pk-pk, INAC C = 0µF IN Thermal Shutdown Temperature T — 150 — °C I = 100µA, V = 1.8V, SD OUT OUT V = 2.8V IN Thermal Shutdown Hysteresis ΔT — 10 — °C I = 100µA, V = 1.8V, SD OUT OUT V = 2.8V IN Note 1: The minimum V must meet two conditions: V ≥ 2.1V and V ≥ V + V IN IN IN OUT(MAX) DROPOUT(MAX). 2: V is the nominal regulator output voltage for the fixed cases. V = 1.2V, 1.8V, etc. V is the desired set point output R R R voltage for the adjustable cases. V = V ((R /R )+1). Figure4-1. R ADJ* 1 2 3: TCV = (V – V ) *106 / (V * ΔTemperature). V is the highest voltage measured over the OUT OUT-HIGH OUT-LOW R OUT-HIGH temperature range. V is the lowest voltage measured over the temperature range. OUT-LOW 4: Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is tested over a load range from 1mA to the maximum specified output current. 5: Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its nominal value that was measured with an input voltage of V = V + V . IN OUT(MAX) DROPOUT(MAX) 6: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air. (i.e., T , T , θ ). Exceeding the maximum allowable power A J JA dissipation will cause the device operating junction temperature to exceed the maximum +150°C rating. Sustained junction temperatures above 150°C can impact device reliability. 7: The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the desired junction temperature. The test time is small enough such that the rise in the junction temperature over the ambient temperature is not significant. © 2008 Microchip Technology Inc. DS22056B-page 9

MCP1825/MCP1825S TEMPERATURE SPECIFICATIONS Parameters Sym Min Typ Max Units Conditions Temperature Ranges Operating Junction Temperature Range T -40 — +125 °C Steady State J Maximum Junction Temperature T — — +150 °C Transient J Storage Temperature Range T -65 — +150 °C A Thermal Package Resistances Thermal Resistance, 3LD DDPAK θ — 31.4 — °C/W 4-Layer JC51 Standard JA θ — 3.0 — Board JC Thermal Resistance, 3LD TO-220 θ — 29.4 — °C/W 4-Layer JC51 Standard JA θ — 2.0 — Board JC Thermal Resistance, 3LD SOT-223 θ — 62 — °C/W EIA/JEDEC JESD51-751-7 JA θ — 15.0 — 4 Layer Board JC Thermal Resistance, 5LD DDPAK θ — 31.2 — °C/W 4-Layer JC51 Standard JA θ — 3.0 — Board JC Thermal Resistance, 5LD TO-220 θ — 29.3 — °C/W 4-Layer JC51 Standard JA θ — 2.0 — Board JC Thermal Resistance, 5LD SOT-223 θ — 62 — °C/W EIA/JEDEC JESD51-751-7 JA θ — 15.0 — 4 Layer Board JC DS22056B-page 10 © 2008 Microchip Technology Inc.

MCP1825/MCP1825S 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated,C = 4.7µF Ceramic (X7R), C = 4.7µF Ceramic (X7R), I = 1mA, OUT IN OUT Temperature = +25°C, V = V + 0.5V, Fixed output. IN OUT 140 0.10 Quiescent Current (μA) 111101230000 1-92403055°0°°C°C°CCCVIOOUUTT = = 0 1 m.2AV Adj Line Regulation (%/V) 000000000.........000000000123456789 IOUT=100 mAIOUT I=OU 1T= m50A0 mA VINV =OI UOI2OTU. U1T=T V= =1 2t5.o250V 0 6m .ma0AdVAj 90 0.00 2 3 4 5 6 -45 -20 5 30 55 80 105 130 Input Voltage (V) Temperature (°C) FIGURE 2-1: Quiescent Current vs. Input FIGURE 2-4: Line Regulation vs. Voltage (Adjustable Version). Temperature (Adjustable Version). 200 0.20 190 VOUT = 1.2V Adj 0.15 IOUT = 1.0 mA to 500 mA A) 180 %) Ground Current (μ 111111234567000000 VIN=3.3VVIN=5.0V Load Regulation ( --00000.....1000105050 VOUT = 5.0V VVOOUUTT = = 3 1.3.8VV VOUT = 0.8V 110 VIN=2.5V 100 -0.15 0 100 200 300 400 500 600 -45 -20 5 30 55 80 105 130 Load Current (mA) Temperature (°C) FIGURE 2-2: Ground Current vs. Load FIGURE 2-5: Load Regulation vs. Current (Adjustable Version). Temperature (Adjustable Version). 170 0.4110 Quiescent Current (μA) 111111101234560000000 VIN=5.0V VIN=6.0VV O IUOTU =T =1 .02 Vm AAdj VIN=4.0V Adjust Pin Voltage (V) 0000000.......4444444000001178899005050505 VIN = 4.0V VIN = 6.0V VIOOUUTT = = 1 1.0.8 mVA VIN=2.1V VIN=3.0V VIN = 2.3V 90 0.4070 -45 -20 5 30 55 80 105 130 -45 -20 5 30 55 80 105 130 Temperature (°C) Temperature (°C) FIGURE 2-3: Quiescent Current vs. FIGURE 2-6: Adjust Pin Voltage vs. Junction Temperature (Adjustable Version). Temperature (Adjustable Version). © 2008 Microchip Technology Inc. DS22056B-page 11

MCP1825/MCP1825S Note: Unless otherwise indicated,C = 4.7µF Ceramic (X7R), C = 4.7µF Ceramic (X7R), I = 1mA, OUT IN OUT Temperature = +25°C, V = V + 0.5V, Fixed output. IN OUT 0.30 160 VOUT = 0.8V 0.25 A) 150 IOUT = 0 mA V) μ out Voltage ( 000...112050 VOUT = 5.0VVO UATd =j 2.5V Adj ent Current ( 111234000 +++1923 0500°°°°CCCC Drop 0.05 uiesc 110100 -45°C Q 0.00 90 0 50 100 150 200 250 300 350 400 450 500 2 3 4 5 6 Load Current (mA) Input Voltage (V) FIGURE 2-7: Dropout Voltage vs. Load FIGURE 2-10: Quiescent Current vs. Input Current (Adjustable Version). Voltage. 0.30 150 IOUT = 500 mA VOUT = 2.5V V) 0.28 μA) 140 IOUT = 0 mA ut Voltage ( 00..2246 VOUT = 5.0V Adj VOUT = 3.3V Adj nt Current ( 112300 +++1293500°°°CCC Dropo 0.22 VOUT = 2.5V Adj uiesce 110100 -4+50°°CC Q 0.20 90 -45 -20 5 30 55 80 105 130 3 3.5 4 4.5 5 5.5 6 Temperature (°C) Input Voltage (V) FIGURE 2-8: Dropout Voltage vs. FIGURE 2-11: Quiescent Current vs. Input Temperature (Adjustable Version). Voltage. 170 250 y (µS) 160 VOUT = 2.5V Fixed A) 200 VVIINN == 23..30VV ffoorr VVRR==02..85VV wer Good Time Dela 111111234500000 VIN = 3V.I0NV = 6.0VVIN = 4.0V VIN = 5.0V Ground Current (μ 11055000 VVOOUUTT==02..85VV o P 100 0 -45 -20 5 30 55 80 105 130 0 100 200 300 400 500 600 Temperature (°C) Load Current (mA) FIGURE 2-9: Power Good (PWRGD) FIGURE 2-12: Ground Current vs. Load Time Delay vs. Temperature. Current. DS22056B-page 12 © 2008 Microchip Technology Inc.

MCP1825/MCP1825S Note: Unless otherwise indicated,C = 4.7µF Ceramic (X7R), C = 4.7µF Ceramic (X7R), I = 1mA, OUT IN OUT Temperature = +25°C, V = V + 0.5V, Fixed output. IN OUT 140 0.045 A) 135 IOUT = 0 mA V) 0.040 IOUT = 1 mA V I N = 3 .V1RV = t o2 .65.V0V Quiescent Current (μ 111111100112230505050 VOUTV =O 2UT.5 =V 5VVOUT = 0.8V Line Regulation (%/ 0000....000022330505 IIOOUUTT == 25500 m mAA IOUT = 500 mA IOUT = 100 mA 95 0.015 -45 -20 5 30 55 80 105 130 -45 -20 5 30 55 80 105 130 Temperature (°C) Temperature (°C) FIGURE 2-13: Quiescent Current vs. FIGURE 2-16: Line Regulation vs. Temperature. Temperature. 0.30 VR = 0.8V 0.25 0.25 VOUT = 0.8V hdn (μA) 00..1250 VIN = 6V.I0NV = 5.0V VIN = 4.0V gulation (%) -000...010555 VVININ == 25..10VV VIN= 4.0V IOUT = 1 mA to 500 mA Is 0.10 VIN = 2.3V Re d VIN= 6.0V 0.05 oa -0.15 L 0.00 -0.25 -45 -20 5 30 55 80 105 130 -45 -20 5 30 55 80 105 130 Temperature (°C) Temperature (°C) FIGURE 2-14: I vs. Temperature. FIGURE 2-17: Load Regulation vs. SHDN Temperature (V < 2.5V Fixed). OUT 0.09 0.00 Line Regulation (%/V) 000000......000000345678 IIOOIUOUTTU =T= = 25 5100 mm mAAA VVOINU =T =2I O.01U.VT8 V=to 1 60.00 VmA Load Regulation (%) ------000000......322110050505 VVOUOTU T= =5 .20.V5V IOUT = 1 mA to 500 mA IOUT = 500 mA 0.02 -0.35 -45 -20 5 30 55 80 105 130 -45 -20 5 30 55 80 105 130 Temperature (°C) Temperature (°C) FIGURE 2-15: Line Regulation vs. FIGURE 2-18: Load Regulation vs. Temperature. Temperature (V ≥ 2.5V Fixed). OUT © 2008 Microchip Technology Inc. DS22056B-page 13

MCP1825/MCP1825S Note: Unless otherwise indicated, C = 4.7µF Ceramic (X7R), C = 4.7µF Ceramic (X7R), I = 1mA, OUT IN OUT Temperature = +25°C, V = V + 0.5V, Fixed output. IN OUT 0.30 10 V) 0.25 VR=2.5V, VIN=3.3V CCOINU=T=101 μμFF cceerr ge ( 0.20 VOUT = 5.0V Hz) 1 Volta 0.15 VOUT = 2.5V mV/√ VR=0.8V, VIN=2.3V IOUT=200 mA ut e ( Dropo 00..0150 Nois 0.1 0.00 0.01 0 100 200 300 400 500 0.01 0.1 1 10 100 1000 Load Current (mA) Frequency (kHz) FIGURE 2-19: Dropout Voltage vs. Load FIGURE 2-22: Output Noise Voltage Current. Density vs. Frequency. 0.30 0.0 IOUT = 500 mA V) 0.28 -10.0 age ( 0.26 B) --3200..00 out Volt 00..2224 VOUT = 5.0V SRR (d --5400..00 VCRO=UT1=.21V0 AμFd jceramic X7R Drop 0.20 P -60.0 VCIINN==20. 5μVF VOUT = 2.5V -70.0 IOUT=10 mA 0.18 -80.0 -45 -20 5 30 55 80 105 130 0.01 0.1 1 10 100 1000 Temperature (°C) Frequency (kHz) FIGURE 2-20: Dropout Voltage vs. FIGURE 2-23: Power Supply Ripple Temperature. Rejection (PSRR) vs. Frequency (Adj.). 0.0 0.80 A) 0.70 VOUT = 2.5V -10.0 nt ( 0.60 -20.0 uit Curre 00..4500 RR (dB)---543000...000 VR=2.5V (Fixed) hort Circ 000...123000 PS---876000...000 CVCIOIOIUNNUT===T30=1. 23μ02V Fm μAF ceramic X7R S 0.00 -90.0 0.00 1.00 2.00 3.00 4.00 5.00 6.00 0.01 0.1 1 10 100 1000 Input Voltage (V) Frequency (kHz) FIGURE 2-21: Short Circuit Current vs. FIGURE 2-24: Power Supply Ripple Input Voltage. Rejection (PSRR) vs. Frequency. DS22056B-page 14 © 2008 Microchip Technology Inc.

MCP1825/MCP1825S Note: Unless otherwise indicated, C = 4.7µF Ceramic (X7R), C = 4.7µF Ceramic (X7R), I = 1mA, OUT IN OUT Temperature = +25°C, V = V + 0.5V, Fixed output. IN OUT FIGURE 2-25: 2.5V (Adj.) Startup from V . FIGURE 2-28: Dynamic Line Response. IN FIGURE 2-26: 2.5V (Adj.) Startup from FIGURE 2-29: Dynamic Load Response Shutdown. (1mA to 500mA). FIGURE 2-27: Power Good (PWRGD) FIGURE 2-30: Dynamic Load Response Timing. (10mA to 500mA). © 2008 Microchip Technology Inc. DS22056B-page 15

MCP1825/MCP1825S 3.0 PIN DESCRIPTION The descriptions of the pins are listed in Table3-1. TABLE 3-1: PIN FUNCTION TABLE 3-Pin Fixed 5-Pin Fixed Adjustable Name Description Output Output Output — 1 1 SHDN Shutdown Control Input (active-low) 1 2 2 V Input Voltage Supply IN 2 3 3 GND Ground 3 4 4 V Regulated Output Voltage OUT — 5 — PWRGD Power Good Output — — 5 ADJ Voltage Adjust/Sense Input Exposed Pad Exposed Pad Exposed Pad EP Exposed Pad of the Package (ground potential) 3.1 Shutdown Control Input (SHDN) 3.5 Power Good Output (PWRGD) The SHDN input is used to turn the LDO output voltage The PWRGD output is an open-drain output used to on and off. When the SHDN input is at a logic-high indicate when the LDO output voltage is within 92% level, the LDO output voltage is enabled. When the (typically) of its nominal regulation value. The PWRGD SHDN input is pulled to a logic-low level, the LDO threshold has a typical hysteresis value of 2%. The output voltage is disabled. When the SHDN input is PWRGD output is delayed by 110µs (typical) from the pulled low, the PWRGD output also goes low and the time the LDO output is within 92% + 3% (maximum LDO enters a low quiescent current shutdown state hysteresis) of the regulated output value on power-up. where the typical quiescent current is 0.1µA. This delay time is internally fixed. 3.2 Input Voltage Supply (V ) 3.6 Output Voltage Adjust Input (ADJ) IN Connect the unregulated or regulated input voltage For adjustable applications, the output voltage is source to V . If the input voltage source is located connected to the ADJ input through a resistor divider IN several inches away from the LDO, or the input source that sets the output voltage regulation value. This is a battery, it is recommended that an input capacitor provides the user the capability to set the output be used. A typical input capacitance value of 1µF to voltage to any value they desire within the 0.8V to 5.0V 10µF should be sufficient for most applications. range of the device. 3.7 Exposed Pad (EP) 3.3 Ground (GND) The DDPAK and TO-220 package have an exposed Connect the GND pin of the LDO to a quiet circuit tab on the package. A heat sink may may be mount to ground. This will help the LDO power supply rejection the tab to aid in the removal of heat from the package ratio and noise performance. The ground pin of the during operation. The exposed tab is at the ground LDO only conducts the quiescent current of the LDO potential of the LDO. (typically 120µA), so a heavy trace is not required. For applications that have switching or noisy inputs, tie the GND pin to the return of the output capacitor. Ground planes help lower inductance and voltage spikes caused by fast transient load currents and are recommended for applications that are subjected to fast load transients. 3.4 Regulated Output Voltage (V ) OUT The V pin is the regulated output voltage of the OUT LDO. A minimum output capacitance of 1.0µF is required for LDO stability. The MCP1825/MCP1825S is stable with ceramic, tantalum and aluminum-electro- lytic capacitors. See Section4.3 “Output Capacitor” for output capacitor selection guidance. DS22056B-page 16 © 2008 Microchip Technology Inc.

MCP1825/MCP1825S 4.0 DEVICE OVERVIEW EQUATION 4-2: V –V The MCP1825/MCP1825S is a high output current, R = R ⎛----O----U----T------------A----D---J-⎞ 1 2⎝ V ⎠ Low Dropout (LDO) voltage regulator. The low dropout ADJ Where: voltage of 210mV typical at 500mA of current makes it ideal for battery-powered applications. Unlike other V = LDO Output Voltage OUT high output current LDOs, the MCP1825/MCP1825S V = ADJ Pin Voltage ADJ only draws a maximum of 220µA of quiescent current. (typically 0.41V) The MCP1825 has a shutdown control input and a power good output. 4.2 Output Current and Current 4.1 LDO Output Voltage Limiting The 5-pin MCP1825 LDO is available with either a fixed The MCP1825/MCP1825S LDO is tested and ensured output voltage or an adjustable output voltage. The to supply a minimum of 500mA of output current. The output voltage range is 0.8V to 5.0V for both versions. MCP1825/MCP1825S has no minimum output load, so The 3-pin MCP1825S LDO is available as a fixed the output load current can go to 0mA and the LDO will voltage device. continue to regulate the output voltage to within tolerance. 4.1.1 ADJUST INPUT The MCP1825/MCP1825S also incorporates an output The adjustable version of the MCP1825 uses the ADJ current limit. If the output voltage falls below 0.7V due pin (pin 5) to get the output voltage feedback for output to an overload condition (usually represents a shorted voltage regulation. This allows the user to set the load condition), the output current is limited to 1.2A output voltage of the device with two external resistors. (typical). If the overload condition is a soft overload, the The nominal voltage for ADJ is 0.41V. MCP1825/MCP1825S will supply higher load currents Figure4-1 shows the adjustable version of the of up to 1.5A. The MCP1825/MCP1825S should not be MCP1825. Resistors R and R form the resistor operated in this condition continuously as it may result 1 2 divider network necessary to set the output voltage. in failure of the device. However, this does allow for With this configuration, the equation for setting V is: device usage in applications that have higher pulsed OUT load currents having an average output current value of EQUATION 4-1: 500mA or less. R +R Output overload conditions may also result in an over- VOUT = VADJ⎝⎛----1---R----------2-⎠⎞ temperature shutdown of the device. If the junction Where: 2 temperature rises above 150°C, the LDO will shut down the output voltage. See Section4.8 “Overtem- VOUT = LDO Output Voltage perature Protection” for more information on V = ADJ Pin Voltage overtemperature shutdown. ADJ (typically 0.41V) 4.3 Output Capacitor The MCP1825/MCP1825S requires a minimum output MCP1825-ADJ capacitance of 1µF for output voltage stability. VOUT Ceramic capacitors are recommended because of their size, cost and environmental robustness qualities. Off On SHDN 1 2 3 4 5 ADJ R1 1C2µF Aluminum-electrolytic and tantalum capacitors can be used on the LDO output as well. The Equivalent Series VIN Resistance (ESR) of the electrolytic output capacitor 4C.17µF GND R2 must be no greater than 1 ohm. The output capacitor should be located as close to the LDO output as is practical. Ceramic materials X7R and X5R have low temperature coefficients and are well within the FIGURE 4-1: Typical adjustable output acceptable ESR range required. A typical 1µF X7R voltage application circuit. 0805 capacitor has an ESR of 50 milli-ohms. The allowable resistance value range for resistor R2 is Larger LDO output capacitors can be used with the from 10kΩ to 200kΩ. Solving the equation for R1 MCP1825/MCP1825S to improve dynamic yields the following equation: performance and power supply ripple rejection performance. A maximum of 22µF is recommended. Aluminum-electrolytic capacitors are not recom- mended for low temperature applications of < -25°C. © 2008 Microchip Technology Inc. DS22056B-page 17

MCP1825/MCP1825S 4.4 Input Capacitor The power good output is an open-drain output that can be pulled up to any voltage that is equal to or less than Low input source impedance is necessary for the LDO the LDO input voltage. This output is capable of sinking output to operate properly. When operating from 1.2mA (V < 0.4V maximum). PWRGD batteries, or in applications with long lead length (> 10 inches) between the input source and the LDO, some input capacitance is recommended. A minimum of 1.0µF to 4.7µF is recommended for most VPWRGD_TH applications. VOUT For applications that have output step load TPG requirements, the input capacitance of the LDO is very important. The input capacitance provides the LDO with a good local low-impedance source to pull the VOH transient currents from in order to respond quickly to TVDET_PWRG the output load step. For good step response performance, the input capacitor should be of PWRGD equivalent (or higher) value than the output capacitor. The capacitor should be placed as close to the input of VOL the LDO as is practical. Larger input capacitors will also help reduce any high-frequency noise on the input and output of the LDO and reduce the effects of any FIGURE 4-2: Power Good Timing. inductance that exists between the input source voltage and the input capacitance of the LDO. 4.5 Power Good Output (PWRGD) V IN T OR The PWRGD output is used to indicate when the output voltage of the LDO is within 92% (typical value, see 70µs 30 µs Section1.0 “Electrical Characteristics” for Minimum and Maximum specifications) of its nominal regulation value. SHDN TPG As the output voltage of the LDO rises, the PWRGD output will be held low until the output voltage has exceeded the power good threshold plus the hysteresis value. Once this threshold has been exceeded, the V OUT power good time delay is started (shown as T in the PG Electrical Characteristics table). The power good time delay is fixed at 110µs (typical). After the time delay period, the PWRGD output will go high, indicating that PWRGD the output voltage is stable and within regulation limits. If the output voltage of the LDO falls below the power good threshold, the power good output will transition FIGURE 4-3: Power Good Timing from low. The power good circuitry has a 170µs delay when Shutdown. detecting a falling output voltage, which helps to increase noise immunity of the power good output and avoid false triggering of the power good output during 4.6 Shutdown Input (SHDN) fast output transients. See Figure4-2 for power good The SHDN input is an active-low input signal that turns timing characteristics. the LDO on and off. The SHDN threshold is a When the LDO is put into Shutdown mode using the percentage of the input voltage. The typical value of SHDN input, the power good output is pulled low this shutdown threshold is 30% of V , with minimum IN immediately, indicating that the output voltage will be and maximum limits over the entire operating out of regulation. The timing diagram for the power temperature range of 45% and 15%, respectively. good output when using the shutdown input is shown in The SHDN input will ignore low-going pulses (pulses Figure4-3. meant to shut down the LDO) that are up to 400ns in pulse width. If the shutdown input is pulled low for more than 400ns, the LDO will enter Shutdown mode. This small bit of filtering helps to reject any system noise spikes on the shutdown input signal. DS22056B-page 18 © 2008 Microchip Technology Inc.

MCP1825/MCP1825S On the rising edge of the SHDN input, the shutdown 4.7 Dropout Voltage and circuitry has a 30µs delay before allowing the LDO Undervoltage Lockout output to turn on. This delay helps to reject any false turn-on signals or noise on the SHDN input signal. After Dropout voltage is defined as the input-to-output the 30µs delay, the LDO output enters its soft-start voltage differential at which the output voltage drops period as it rises from 0V to its final regulation value. If 2% below the nominal value that was measured with a the SHDN input signal is pulled low during the 30µs VR + 0.5V differential applied. The MCP1825/ delay period, the timer will be reset and the delay time MCP1825S LDO has a very low dropout voltage will start over again on the next rising edge of the specification of 210mV (typical) at 500mA of output SHDN input. The total time from the SHDN input going current. See Section1.0 “Electrical Characteristics” high (turn-on) to the LDO output being in regulation is for maximum dropout voltage specifications. typically 100µs. See Figure4-4 for a timing diagram of The MCP1825/MCP1825S LDO operates across an the SHDN input. input voltage range of 2.1V to 6.0V and incorporates input Undervoltage Lockout (UVLO) circuitry that T keeps the LDO output voltage off until the input voltage OR 400ns (typ) reaches a minimum of 2.00V (typical) on the rising 70µs edge of the input voltage. As the input voltage falls, the 30µs LDO output will remain on until the input voltage level reaches 1.82V (typical). SHDN Since the MCP1825/MCP1825S LDO undervoltage lockout activates at 1.82V as the input voltage is falling, the dropout voltage specification does not apply for output voltages that are less than 1.8V. VOUT For high-current applications, voltage drops across the PCB traces must be taken into account. The trace resistances can cause significant voltage drops FIGURE 4-4: Shutdown Input Timing between the input voltage source and the LDO. For Diagram. applications with input voltages near 2.1V, these PCB trace voltage drops can sometimes lower the input voltage enough to trigger a shutdown due to undervoltage lockout. 4.8 Overtemperature Protection The MCP1825/MCP1825S LDO has temperature- sensing circuitry to prevent the junction temperature from exceeding approximately 150°C. If the LDO junction temperature does reach 150°C, the LDO output will be turned off until the junction temperature cools to approximately 140°C, at which point the LDO output will automatically resume normal operation. If the internal power dissipation continues to be excessive, the device will again shut off. The junction temperature of the die is a function of power dissipation, ambient temperature and package thermal resistance. See Section5.0 “Application Circuits/ Issues” for more information on LDO power dissipation and junction temperature. © 2008 Microchip Technology Inc. DS22056B-page 19

MCP1825/MCP1825S 5.0 APPLICATION CIRCUITS/ In addition to the LDO pass element power dissipation, ISSUES there is power dissipation within the MCP1825/ MCP1825S as a result of quiescent or ground current. The power dissipation as a result of the ground current 5.1 Typical Application can be calculated using the following equation: The MCP1825/MCP1825S is used for applications that EQUATION 5-2: require high LDO output current and a power good output. P = V ×I I(GND) IN(MAX) VIN Where: VOUT = 2.5V @ 500mA P = Power dissipation due to the I(GND MCP1825-2.5 quiescent current of the LDO On R1 Off SHDN 1 2 3 4 5 10kΩ 1C02µF VIN(MAX) = Maximum input voltage I = Current flowing in the V pin VIN IN 3.3V VIN with no LDO output current C1 (LDO quiescent current) 4.7µF GND PWRGD The total power dissipated within the MCP1825/ MCP1825S is the sum of the power dissipated in the FIGURE 5-1: Typical Application Circuit. LDO pass device and the P(I ) term. Because of the GND CMOS construction, the typical I for the MCP1825/ GND 5.1.1 APPLICATION CONDITIONS MCP1825S is 120µA. Operating at a maximum V of IN 3.465V results in a power dissipation of 0.12milli-Watts Package Type = TO-220-5 for a 2.5V output. For most applications, this is small Input Voltage Range = 3.3V ± 5% compared to the LDO pass device power dissipation V maximum = 3.465V and can be neglected. IN VIN minimum = 3.135V The maximum continuous operating junction V = 0.350V temperature specified for the MCP1825/MCP1825S is DROPOUT (max) +125°C. To estimate the internal junction temperature V (typical) = 2.5V OUT of the MCP1825/MCP1825S, the total internal power I = 500mA maximum OUT dissipation is multiplied by the thermal resistance from P (typical) = 0.483W junction to ambient (Rθ ) of the device. The thermal DISS JA Temperature Rise = 14.2°C resistance from junction to ambient for the TO-220-5 package is estimated at 29.3°C/W. 5.2 Power Calculations EQUATION 5-3: 5.2.1 POWER DISSIPATION T = P ×Rθ +T J(MAX) TOTAL JA AMAX The internal power dissipation within the MCP1825/ T = Maximum continuous junction MCP1825S is a function of input voltage, output J(MAX) temperature voltage, output current and quiescent current. Equation5-1 can be used to calculate the internal PTOTAL = Total device power dissipation power dissipation for the LDO. Rθ = Thermal resistance from junction to JA ambient EQUATION 5-1: T = Maximum ambient temperature AMAX P = (V –V )×I LDO IN(MAX)) OUT(MIN) OUT(MAX)) Where: P = LDO Pass device internal LDO power dissipation V = Maximum input voltage IN(MAX) V = LDO minimum output voltage OUT(MIN) DS22056B-page 20 © 2008 Microchip Technology Inc.

MCP1825/MCP1825S The maximum power dissipation capability for a 5.3 Typical Application package can be calculated given the junction-to- ambient thermal resistance and the maximum ambient Internal power dissipation, junction temperature rise, temperature for the application. Equation5-4 can be junction temperature and maximum power dissipation used to determine the package maximum internal is calculated in the following example. The power power dissipation. dissipation as a result of ground current is small enough to be neglected. EQUATION 5-4: 5.3.1 POWER DISSIPATION EXAMPLE (T –T ) P = ------J---(--M----A---X---)------------A---(--M----A---X---)--- D(MAX) Rθ Package JA Package Type = TO-220-5 P = Maximum device power dissipation D(MAX) Input Voltage T = maximum continuous junction J(MAX) V = 3.3V ± 5% temperature IN LDO Output Voltage and Current T = maximum ambient temperature A(MAX) V = 2.5V Rθ = Thermal resistance from junction-to- OUT JA I = 500mA ambient OUT Maximum Ambient Temperature T = 60°C EQUATION 5-5: A(MAX) Internal Power Dissipation T = P ×Rθ J(RISE) D(MAX) JA P = (V – V ) x I LDO(MAX) IN(MAX) OUT(MIN) OUT(MAX) TJ(RISE) = Rise in device junction temperature PLDO = ((3.3V x 1.05) – (2.5V x 0.975)) over the ambient temperature x 500mA PD(MAX) = Maximum device power dissipation PLDO = 0.514 Watts Rθ = Thermal resistance from junction-to- JA 5.3.1.1 Device Junction Temperature Rise ambient The internal junction temperature rise is a function of internal power dissipation and the thermal resistance EQUATION 5-6: from junction-to-ambient for the application. The thermal resistance from junction-to-ambient (Rθ ) is T = T +T JA J J(RISE) A derived from EIA/JEDEC standards for measuring thermal resistance. The EIA/JEDEC specification is T = Junction temperature J JESD51. The standard describes the test method and TJ(RISE) = Rise in device junction temperature board specifications for measuring the thermal over the ambient temperature resistance from junction to ambient. The actual thermal T = Ambient temperature resistance for a particular application can vary A depending on many factors such as copper area and thickness. Refer to AN792, “A Method to Determine How Much Power a SOT23 Can Dissipate in an Application” (DS00792), for more information regarding this subject. T = P x Rθ J(RISE) TOTAL JA TJRISE = 0.514 W x 29.3° C/W T = 15.06°C JRISE © 2008 Microchip Technology Inc. DS22056B-page 21

MCP1825/MCP1825S 5.3.1.2 Junction Temperature Estimate To estimate the internal junction temperature, the calculated temperature rise is added to the ambient or offset temperature. For this example, the worst-case junction temperature is estimated below: T = T + T J JRISE A(MAX) T = 15.06°C + 60.0°C J T = 75.06°C J 5.3.1.3 Maximum Package Power Dissipation at 60°C Ambient Temperature TO-220-5 (29.3°C/W Rθ ): JA P = (125°C – 60°C) / 29.3°C/W D(MAX) P = 2.218W D(MAX) DDPAK-5 (31.2°C/Watt Rθ ): JA P = (125°C – 60°C)/ 31.2°C/W D(MAX) P = 2.083W D(MAX) From this table, you can see the difference in maximum allowable power dissipation between the TO-220-5 package and the DDPAK-5 package. DS22056B-page 22 © 2008 Microchip Technology Inc.

MCP1825/MCP1825S 6.0 PACKAGING INFORMATION 6.1 Package Marking Information 3-Lead DDPAK (MCP1825S) Example: XXXXXXXXX MCP1825S XXXXXXXXX 08EEBe3 YYWWNNN 0710256 1 2 3 1 2 3 3-Lead SOT-223 (MCP1825S) Example: XXXXXXX 1825S08 XXXYYWW EDB0710 NNN 256 3-Lead TO-220 (MCP1825S) Example: XXXXXXXXX MCP1825S XXXXXXXXX 12EABe3 YYWWNNN 0710256 1 2 3 1 2 3 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2008 Microchip Technology Inc. DS22056B-page 23

MCP1825/MCP1825S Package Marking Information (Continued) 5-Lead DDPAK (MCP1825) Example: XXXXXXXXX MCP1825 XXXXXXXXX 12EETe3 YYWWNNN 0710256 1 2 3 4 5 1 2 3 4 5 5-Lead SOT-223 (MCP1825) Example: XXXXXXX 1825-08 XXXYYWW EDC0710 NNN 256 5-Lead TO-220 (MCP1825) Example: XXXXXXXXX MCP1825 XXXXXXXXX 08EAT^e^3 YYWWNNN 0710256 1 2 3 4 5 1 2 3 4 5 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. DS22056B-page 24 © 2008 Microchip Technology Inc.

MCP1825/MCP1825S 3-Lead Plastic (EB) [DDPAK] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 L1 D1 D H 1 N b e BOTTOM VIEW TOP VIEW b1 CHAMFER OPTIONAL A C2 φ A1 c L Units INCHES Dimension Limits MIN NOM MAX Number of Pins N 3 Pitch e .100 BSC Overall Height A .160 – .190 Standoff § A1 .000 – .010 Overall Width E .380 – .420 Exposed Pad Width E1 .245 – – Molded Package Length D .330 – .380 Overall Length H .549 – .625 Exposed Pad Length D1 .270 – – Lead Thickness c .014 – .029 Pad Thickness C2 .045 – .065 Lower Lead Width b .020 – .039 Upper Lead Width b1 .045 – .070 Foot Length L .068 – .110 Pad Length L1 – – .067 Foot Angle φ 0° – 8° Notes: 1. § Significant Characteristic. 2. Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" per side. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. MicrochipTechnologyDrawingC04-011B © 2008 Microchip Technology Inc. DS22056B-page 25

MCP1825/MCP1825S 3-Lead Plastic Small Outline Transistor (DB) [SOT-223] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D b2 E1 E 1 2 3 e e1 A A2 c φ b A1 L Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Leads N 3 Lead Pitch e 2.30 BSC Outside Lead Pitch e1 4.60 BSC Overall Height A – – 1.80 Standoff A1 0.02 – 0.10 Molded Package Height A2 1.50 1.60 1.70 Overall Width E 6.70 7.00 7.30 Molded Package Width E1 3.30 3.50 3.70 Overall Length D 6.30 6.50 6.70 Lead Thickness c 0.23 0.30 0.35 Lead Width b 0.60 0.76 0.84 Tab Lead Width b2 2.90 3.00 3.10 Foot Length L 0.75 – – Lead Angle φ 0° – 10° Notes: 1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.127 mm per side. 2. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. MicrochipTechnologyDrawingC04-032B DS22056B-page 26 © 2008 Microchip Technology Inc.

MCP1825/MCP1825S (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:10)(cid:8)(cid:17)(cid:18)(cid:12)(cid:10)(cid:13)(cid:19)(cid:5)(cid:8)(cid:20)(cid:21)(cid:6)(cid:19)(cid:11)(cid:13)(cid:11)(cid:12)(cid:22)(cid:21)(cid:8)(cid:23)(cid:24)(cid:25)(cid:26)(cid:8)(cid:27)(cid:15)(cid:17)(cid:20)(cid:3)(cid:28)(cid:28)(cid:2)(cid:29) (cid:30)(cid:22)(cid:12)(cid:5)(cid:31) (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:5)(cid:9)(cid:3)(cid:10)(cid:6)(cid:5)(cid:11)(cid:12)(cid:4)(cid:4)(cid:8)(cid:13)(cid:6)(cid:5)(cid:14)(cid:15)(cid:11)(cid:16)(cid:15)(cid:17)(cid:8)(cid:5)(cid:18)(cid:4)(cid:15)(cid:19)(cid:20)(cid:13)(cid:17)(cid:10)(cid:21)(cid:5)(cid:14)(cid:22)(cid:8)(cid:15)(cid:10)(cid:8)(cid:5)(cid:10)(cid:8)(cid:8)(cid:5)(cid:6)(cid:7)(cid:8)(cid:5)(cid:23)(cid:20)(cid:11)(cid:4)(cid:3)(cid:11)(cid:7)(cid:20)(cid:14)(cid:5)(cid:24)(cid:15)(cid:11)(cid:16)(cid:15)(cid:17)(cid:20)(cid:13)(cid:17)(cid:5)(cid:25)(cid:14)(cid:8)(cid:11)(cid:20)(cid:26)(cid:20)(cid:11)(cid:15)(cid:6)(cid:20)(cid:3)(cid:13)(cid:5)(cid:22)(cid:3)(cid:11)(cid:15)(cid:6)(cid:8)(cid:18)(cid:5)(cid:15)(cid:6)(cid:5) (cid:7)(cid:6)(cid:6)(cid:14)(cid:27)(cid:28)(cid:28)(cid:19)(cid:19)(cid:19)(cid:29)(cid:9)(cid:20)(cid:11)(cid:4)(cid:3)(cid:11)(cid:7)(cid:20)(cid:14)(cid:29)(cid:11)(cid:3)(cid:9)(cid:28)(cid:14)(cid:15)(cid:11)(cid:16)(cid:15)(cid:17)(cid:20)(cid:13)(cid:17) © 2008 Microchip Technology Inc. DS22056B-page 27

MCP1825/MCP1825S 3-Lead Plastic Transistor Outline (AB) [TO-220] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E CHAMFER A OPTIONAL φP A1 Q H1 D D1 L1 L b2 1 2 N b c e A2 e1 Units INCHES Dimension Limits MIN NOM MAX Number of Pins N 3 Pitch e .100 BSC Overall Pin Pitch e1 .200 BSC Overall Height A .140 – .190 Tab Thickness A1 .020 – .055 Base to Lead A2 .080 – .115 Overall Width E .357 – .420 Mounting Hole Center Q .100 – .120 Overall Length D .560 – .650 Molded Package Length D1 .330 – .355 Tab Length H1 .230 – .270 Mounting Hole Diameter φP .139 – .156 Lead Length L .500 – .580 Lead Shoulder L1 – – .250 Lead Thickness c .012 – .024 Lead Width b .015 .027 .040 Shoulder Width b2 .045 .057 .070 Notes: 1. Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" per side. 2. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. MicrochipTechnologyDrawingC04-034B DS22056B-page 28 © 2008 Microchip Technology Inc.

MCP1825/MCP1825S 5-Lead Plastic (ET) [DDPAK] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 L1 D1 D H 1 N b e BOTTOM VIEW TOP VIEW CHAMFER OPTIONAL A C2 φ A1 c L Units INCHES Dimension Limits MIN NOM MAX Number of Pins N 5 Pitch e .067 BSC Overall Height A .160 – .190 Standoff § A1 .000 – .010 Overall Width E .380 – .420 Exposed Pad Width E1 .245 – – Molded Package Length D .330 – .380 Overall Length H .549 – .625 Exposed Pad Length D1 .270 – – Lead Thickness c .014 – .029 Pad Thickness C2 .045 – .065 Lead Width b .020 – .039 Foot Length L .068 – .110 Pad Length L1 – – .067 Foot Angle φ 0° – 8° Notes: 1. § Significant Characteristic. 2. Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" per side. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. MicrochipTechnologyDrawingC04-012B © 2008 Microchip Technology Inc. DS22056B-page 29

MCP1825/MCP1825S (cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:10)(cid:8)(cid:17)(cid:18)(cid:12)(cid:10)(cid:13)(cid:19)(cid:5)(cid:8)(cid:20)(cid:21)(cid:6)(cid:19)(cid:11)(cid:13)(cid:11)(cid:12)(cid:22)(cid:21)(cid:8)(cid:23)(cid:24)!(cid:26)(cid:8)(cid:27)(cid:15)(cid:17)(cid:20)(cid:3)(cid:28)(cid:28)(cid:2)(cid:29) (cid:30)(cid:22)(cid:12)(cid:5)(cid:31) (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:5)(cid:9)(cid:3)(cid:10)(cid:6)(cid:5)(cid:11)(cid:12)(cid:4)(cid:4)(cid:8)(cid:13)(cid:6)(cid:5)(cid:14)(cid:15)(cid:11)(cid:16)(cid:15)(cid:17)(cid:8)(cid:5)(cid:18)(cid:4)(cid:15)(cid:19)(cid:20)(cid:13)(cid:17)(cid:10)(cid:21)(cid:5)(cid:14)(cid:22)(cid:8)(cid:15)(cid:10)(cid:8)(cid:5)(cid:10)(cid:8)(cid:8)(cid:5)(cid:6)(cid:7)(cid:8)(cid:5)(cid:23)(cid:20)(cid:11)(cid:4)(cid:3)(cid:11)(cid:7)(cid:20)(cid:14)(cid:5)(cid:24)(cid:15)(cid:11)(cid:16)(cid:15)(cid:17)(cid:20)(cid:13)(cid:17)(cid:5)(cid:25)(cid:14)(cid:8)(cid:11)(cid:20)(cid:26)(cid:20)(cid:11)(cid:15)(cid:6)(cid:20)(cid:3)(cid:13)(cid:5)(cid:22)(cid:3)(cid:11)(cid:15)(cid:6)(cid:8)(cid:18)(cid:5)(cid:15)(cid:6)(cid:5) (cid:7)(cid:6)(cid:6)(cid:14)(cid:27)(cid:28)(cid:28)(cid:19)(cid:19)(cid:19)(cid:29)(cid:9)(cid:20)(cid:11)(cid:4)(cid:3)(cid:11)(cid:7)(cid:20)(cid:14)(cid:29)(cid:11)(cid:3)(cid:9)(cid:28)(cid:14)(cid:15)(cid:11)(cid:16)(cid:15)(cid:17)(cid:20)(cid:13)(cid:17) D b2 E1 E 1 2 3 4 N e e1 A A2 c φ b A1 L .(cid:13)(cid:20)(cid:6)(cid:10) (cid:23)/00/(cid:23) + 1(cid:25) (cid:31)(cid:20)(cid:9)(cid:8)(cid:13)(cid:10)(cid:20)(cid:3)(cid:13)(cid:5)0(cid:20)(cid:9)(cid:20)(cid:6)(cid:10) (cid:23)/2 23(cid:23) (cid:23)%4 2(cid:12)(cid:9)5(cid:8)(cid:4)(cid:5)(cid:3)(cid:26)(cid:5)0(cid:8)(cid:15)(cid:18)(cid:10) 2 ( 0(cid:8)(cid:15)(cid:18)(cid:5)(cid:24)(cid:20)(cid:6)(cid:11)(cid:7) (cid:8) (cid:30)(cid:29)#$(cid:5))(cid:25)* 3(cid:12)(cid:6)(cid:10)(cid:20)(cid:18)(cid:8)(cid:5)0(cid:8)(cid:15)(cid:18)(cid:5)(cid:24)(cid:20)(cid:6)(cid:11)(cid:7) (cid:8)(cid:30) ((cid:29)"6(cid:5))(cid:25)* 3-(cid:8)(cid:4)(cid:15)(cid:22)(cid:22)(cid:5)7(cid:8)(cid:20)(cid:17)(cid:7)(cid:6) % 8 8 (cid:30)(cid:29)6" (cid:25)(cid:6)(cid:15)(cid:13)(cid:18)(cid:3)(cid:26)(cid:26) %(cid:30) "(cid:29)"# "(cid:29)"9 "(cid:29)(cid:30)" (cid:23)(cid:3)(cid:22)(cid:18)(cid:8)(cid:18)(cid:5)(cid:24)(cid:15)(cid:11)(cid:16)(cid:15)(cid:17)(cid:8)(cid:5)7(cid:8)(cid:20)(cid:17)(cid:7)(cid:6) %# (cid:30)(cid:29)(( (cid:30)(cid:29)9" (cid:30)(cid:29)9( 3-(cid:8)(cid:4)(cid:15)(cid:22)(cid:22)(cid:5):(cid:20)(cid:18)(cid:6)(cid:7) 9(cid:29)69 $(cid:29)"" $(cid:29)#9 (cid:23)(cid:3)(cid:22)(cid:18)(cid:8)(cid:18)(cid:5)(cid:24)(cid:15)(cid:11)(cid:16)(cid:15)(cid:17)(cid:8)(cid:5):(cid:20)(cid:18)(cid:6)(cid:7) (cid:30) ;(cid:29)’( ;(cid:29)(" ;(cid:29)(( 3-(cid:8)(cid:4)(cid:15)(cid:22)(cid:22)(cid:5)0(cid:8)(cid:13)(cid:17)(cid:6)(cid:7) (cid:31) 9(cid:29)’( 9(cid:29)(" 9(cid:29)(( 0(cid:8)(cid:15)(cid:18)(cid:5)+(cid:7)(cid:20)(cid:11)(cid:16)(cid:13)(cid:8)(cid:10)(cid:10) (cid:11) "(cid:29)#’ "(cid:29)#6 "(cid:29);# 0(cid:8)(cid:15)(cid:18)(cid:5):(cid:20)(cid:18)(cid:6)(cid:7) 5 "(cid:29)’(cid:30) "(cid:29)’($ "(cid:29)((cid:30) +(cid:15)5(cid:5)0(cid:8)(cid:15)(cid:18)(cid:5):(cid:20)(cid:18)(cid:6)(cid:7) 5# #(cid:29)<( ;(cid:29)"" ;(cid:29)"( (cid:2)(cid:3)(cid:3)(cid:6)(cid:5)0(cid:8)(cid:13)(cid:17)(cid:6)(cid:7) 0 "(cid:29)<(cid:30) 8 (cid:30)(cid:29)(cid:30)’ 0(cid:8)(cid:15)(cid:18)(cid:5)%(cid:13)(cid:17)(cid:22)(cid:8) (cid:2) "= ’= 6= (cid:30)(cid:22)(cid:12)(cid:5)(cid:11)(cid:31) (cid:30)(cid:29) (cid:31)(cid:20)(cid:9)(cid:8)(cid:13)(cid:10)(cid:20)(cid:3)(cid:13)(cid:10)(cid:5)(cid:31)(cid:5)(cid:15)(cid:13)(cid:18)(cid:5) (cid:30)(cid:5)(cid:18)(cid:3)(cid:5)(cid:13)(cid:3)(cid:6)(cid:5)(cid:20)(cid:13)(cid:11)(cid:22)(cid:12)(cid:18)(cid:8)(cid:5)(cid:9)(cid:3)(cid:22)(cid:18)(cid:5)(cid:26)(cid:22)(cid:15)(cid:10)(cid:7)(cid:5)(cid:3)(cid:4)(cid:5)(cid:14)(cid:4)(cid:3)(cid:6)(cid:4)(cid:12)(cid:10)(cid:20)(cid:3)(cid:13)(cid:10)(cid:29)(cid:5)(cid:23)(cid:3)(cid:22)(cid:18)(cid:5)(cid:26)(cid:22)(cid:15)(cid:10)(cid:7)(cid:5)(cid:3)(cid:4)(cid:5)(cid:14)(cid:4)(cid:3)(cid:6)(cid:4)(cid:12)(cid:10)(cid:20)(cid:3)(cid:13)(cid:10)(cid:5)(cid:10)(cid:7)(cid:15)(cid:22)(cid:22)(cid:5)(cid:13)(cid:3)(cid:6)(cid:5)(cid:8)!(cid:11)(cid:8)(cid:8)(cid:18)(cid:5)"(cid:29)(cid:30)#$(cid:5)(cid:9)(cid:9)(cid:5)(cid:14)(cid:8)(cid:4)(cid:5)(cid:10)(cid:20)(cid:18)(cid:8)(cid:29) #(cid:29) (cid:31)(cid:20)(cid:9)(cid:8)(cid:13)(cid:10)(cid:20)(cid:3)(cid:13)(cid:20)(cid:13)(cid:17)(cid:5)(cid:15)(cid:13)(cid:18)(cid:5)(cid:6)(cid:3)(cid:22)(cid:8)(cid:4)(cid:15)(cid:13)(cid:11)(cid:20)(cid:13)(cid:17)(cid:5)(cid:14)(cid:8)(cid:4)(cid:5)%(cid:25)(cid:23) (cid:5)&(cid:30)’(cid:29)((cid:23)(cid:29) )(cid:25)*(cid:27) )(cid:15)(cid:10)(cid:20)(cid:11)(cid:5)(cid:31)(cid:20)(cid:9)(cid:8)(cid:13)(cid:10)(cid:20)(cid:3)(cid:13)(cid:29)(cid:5)+(cid:7)(cid:8)(cid:3)(cid:4)(cid:8)(cid:6)(cid:20)(cid:11)(cid:15)(cid:22)(cid:22),(cid:5)(cid:8)!(cid:15)(cid:11)(cid:6)(cid:5)-(cid:15)(cid:22)(cid:12)(cid:8)(cid:5)(cid:10)(cid:7)(cid:3)(cid:19)(cid:13)(cid:5)(cid:19)(cid:20)(cid:6)(cid:7)(cid:3)(cid:12)(cid:6)(cid:5)(cid:6)(cid:3)(cid:22)(cid:8)(cid:4)(cid:15)(cid:13)(cid:11)(cid:8)(cid:10)(cid:29) (cid:23)(cid:20)(cid:11)(cid:4)(cid:3)(cid:11)(cid:7)(cid:20)(cid:14)+(cid:8)(cid:11)(cid:7)(cid:13)(cid:3)(cid:22)(cid:3)(cid:17),(cid:31)(cid:4)(cid:15)(cid:19)(cid:20)(cid:13)(cid:17)*"’>(cid:30);$) DS22056B-page 30 © 2008 Microchip Technology Inc.

MCP1825/MCP1825S (cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:10)(cid:8)(cid:17)(cid:18)(cid:12)(cid:10)(cid:13)(cid:19)(cid:5)(cid:8)(cid:20)(cid:21)(cid:6)(cid:19)(cid:11)(cid:13)(cid:11)(cid:12)(cid:22)(cid:21)(cid:8)(cid:23)(cid:24)!(cid:26)(cid:8)(cid:27)(cid:15)(cid:17)(cid:20)(cid:3)(cid:28)(cid:28)(cid:2)(cid:29) (cid:30)(cid:22)(cid:12)(cid:5)(cid:31) (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:5)(cid:9)(cid:3)(cid:10)(cid:6)(cid:5)(cid:11)(cid:12)(cid:4)(cid:4)(cid:8)(cid:13)(cid:6)(cid:5)(cid:14)(cid:15)(cid:11)(cid:16)(cid:15)(cid:17)(cid:8)(cid:5)(cid:18)(cid:4)(cid:15)(cid:19)(cid:20)(cid:13)(cid:17)(cid:10)(cid:21)(cid:5)(cid:14)(cid:22)(cid:8)(cid:15)(cid:10)(cid:8)(cid:5)(cid:10)(cid:8)(cid:8)(cid:5)(cid:6)(cid:7)(cid:8)(cid:5)(cid:23)(cid:20)(cid:11)(cid:4)(cid:3)(cid:11)(cid:7)(cid:20)(cid:14)(cid:5)(cid:24)(cid:15)(cid:11)(cid:16)(cid:15)(cid:17)(cid:20)(cid:13)(cid:17)(cid:5)(cid:25)(cid:14)(cid:8)(cid:11)(cid:20)(cid:26)(cid:20)(cid:11)(cid:15)(cid:6)(cid:20)(cid:3)(cid:13)(cid:5)(cid:22)(cid:3)(cid:11)(cid:15)(cid:6)(cid:8)(cid:18)(cid:5)(cid:15)(cid:6)(cid:5) (cid:7)(cid:6)(cid:6)(cid:14)(cid:27)(cid:28)(cid:28)(cid:19)(cid:19)(cid:19)(cid:29)(cid:9)(cid:20)(cid:11)(cid:4)(cid:3)(cid:11)(cid:7)(cid:20)(cid:14)(cid:29)(cid:11)(cid:3)(cid:9)(cid:28)(cid:14)(cid:15)(cid:11)(cid:16)(cid:15)(cid:17)(cid:20)(cid:13)(cid:17) © 2008 Microchip Technology Inc. DS22056B-page 31

MCP1825/MCP1825S 5-Lead Plastic Transistor Outline (AT) [TO-220] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E A φP CHAMFER A1 OPTIONAL Q H1 D D1 L 1 2 3 N b e c e1 A2 Units INCHES Dimension Limits MIN NOM MAX Number of Pins N 5 Pitch e .067 BSC Overall Pin Pitch e1 .268 BSC Overall Height A .140 – .190 Overall Width E .380 – .420 Overall Length D .560 – .650 Molded Package Length D1 .330 – .355 Tab Length H1 .204 – .293 Tab Thickness A1 .020 – .055 Mounting Hole Center Q .100 – .120 Mounting Hole Diameter φP .139 – .156 Lead Length L .482 – .590 Base to Bottom of Lead A2 .080 – .115 Lead Thickness c .012 – .025 Lead Width b .015 .027 .040 Notes: 1. Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" per side. 2. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. MicrochipTechnologyDrawingC04-036B DS22056B-page 32 © 2008 Microchip Technology Inc.

MCP1825/MCP1825S APPENDIX A: REVISION HISTORY Revision B (February 2008) The following is the list of modifications 1. Updated Figure2-4, Figure2-5, Figure2-16, Figure2-29, and Figure2-30. 2. Updated package outline drawings and landing pattern drawings to Section6.0 “Packaging Information”. 3. Updated Appendix A: “Revision History”. Revision A (August 2007) • Original Release of this Document. © 2008 Microchip Technology Inc. DS22056B-page 33

MCP1825/MCP1825S NOTES: DS22056B-page 34 © 2008 Microchip Technology Inc.

MCP1825/MCP1825S PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. XX X X X/ XX Examples: a) MCP1825-0802E/XX: 0.8V LDO Regulator Device Output Feature Tolerance Temp. Package b) MCP1825-1202E/XX: 1.2V LDO Regulator Voltage Code c) MCP1825-1802E/XX: 1.8V LDO Regulator d) MCP1825-2502E/XX: 2.5V LDO Regulator Device: MCP1825: 500mA Low Dropout Regulator e) MCP1825-3002E/XX: 3.0V LDO Regulator MCP1825T: 500mA Low Dropout Regulator f) MCP1825-3302E/XX: 3.3V LDO Regulator Tape and Reel g) MCP1825-5002E/XX: 5.0V LDO Regulator MCP1825S: 500mA Low Dropout Regulator h) MCP1825-ADJE/XX: ADJ LDO Regulator MCP1825ST:500mA Low Dropout Regulator Tape and Reel a) MCP1825S-0802E/YY:0.8V LDO Regulator b) MCP1825S-1202E/YY:1.2V LDO Regulator Output Voltage *: 08 = 0.8V “Standard” 12 = 1.2V “Standard” c) MCP1825S-1802E/YY:1.8V LDO Regulator 18 = 1.8V “Standard” d) MCP1825S-2502E/YY:2.5V LDO Regulator 25 = 2.5V “Standard” e) MCP1825S-2502E/YY:3.0V LDO Regulator 30 = 3.0V “Standard” 33 = 3.3V “Standard” f) MCP1825S-3302E/YY:3.3V LDO Regulator 50 = 5.0V “Standard” g) MCP1825S-5002E/YY:5.0V LDO Regulator ADJ= Adjustable Output Voltage ** (MCP1825 Only) *Contact factory for other output voltage options ** When ADJ is used, the “extra feature code” and XX = AT for 5LD TO-220 package “tolerance” columns do not apply. Refer to examples. = DC for 5LD SOT-223 package Extra Feature Code: 0 = Fixed = ET for 5LD DDPAK package Tolerance: 2 = 2.5% (Standard) YY = AB for 3LD TO-220 package = DB for 3LD SOT-223 package = EB for 3LD DDPAK package Temperature: E = -40°C to +125°C Package Type: AB = Plastic Transistor Outline, TO-220, 3-lead AT = Plastic Transistor Outline, TO-220, 5-lead EB = Plastic, DDPAK, 3-lead ET = Plastic, DDPAK, 5-lead DB = Plastic Small Transistor Outline, SOT-223, 3-lead DC = Plastic Small Transistor Outline, SOT-223, 5-lead Note: ADJ (Adjustable) only available in 5-lead version. © 2008 Microchip Technology Inc. DS22056B-page 35

MCP1825/MCP1825S NOTES: DS22056B-page 36 © 2008 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, Accuron, and may be superseded by updates. It is your responsibility to dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, ensure that your application meets with your specifications. PICSTART, PROMATE, rfPIC and SmartShunt are registered MICROCHIP MAKES NO REPRESENTATIONS OR trademarks of Microchip Technology Incorporated in the WARRANTIES OF ANY KIND WHETHER EXPRESS OR U.S.A. and other countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Linear Active Thermistor, MXDEV, MXLAB, INCLUDING BUT NOT LIMITED TO ITS CONDITION, SEEVAL, SmartSensor and The Embedded Control Solutions QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, CodeGuard, devices in life support and/or safety applications is entirely at dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, the buyer’s risk, and the buyer agrees to defend, indemnify and ECONOMONITOR, FanSense, In-Circuit Serial hold harmless Microchip from any and all damages, claims, Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB suits, or expenses resulting from such use. No licenses are Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, conveyed, implicitly or otherwise, under any Microchip PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, intellectual property rights. PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2008, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2008 Microchip Technology Inc. DS22056B-page 37

WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office Asia Pacific Office India - Bangalore Austria - Wels 2355 West Chandler Blvd. Suites 3707-14, 37th Floor Tel: 91-80-4182-8400 Tel: 43-7242-2244-39 Chandler, AZ 85224-6199 Tower 6, The Gateway Fax: 91-80-4182-8422 Fax: 43-7242-2244-393 Tel: 480-792-7200 Harbour City, Kowloon India - New Delhi Denmark - Copenhagen Fax: 480-792-7277 Hong Kong Tel: 91-11-4160-8631 Tel: 45-4450-2828 Technical Support: Tel: 852-2401-1200 Fax: 91-11-4160-8632 Fax: 45-4485-2829 http://support.microchip.com Web Address: Fax: 852-2401-3431 India - Pune France - Paris www.microchip.com Australia - Sydney Tel: 91-20-2566-1512 Tel: 33-1-69-53-63-20 Tel: 61-2-9868-6733 Fax: 33-1-69-30-90-79 Fax: 91-20-2566-1513 Atlanta Fax: 61-2-9868-6755 Germany - Munich Duluth, GA Japan - Yokohama China - Beijing Tel: 49-89-627-144-0 Tel: 678-957-9614 Tel: 81-45-471- 6166 Tel: 86-10-8528-2100 Fax: 49-89-627-144-44 Fax: 678-957-1455 Fax: 81-45-471-6122 Fax: 86-10-8528-2104 Italy - Milan Boston Korea - Daegu Westborough, MA China - Chengdu Tel: 82-53-744-4301 Tel: 39-0331-742611 Tel: 774-760-0087 Tel: 86-28-8665-5511 Fax: 82-53-744-4302 Fax: 39-0331-466781 Fax: 774-760-0088 Fax: 86-28-8665-7889 Korea - Seoul Netherlands - Drunen Chicago China - Hong Kong SAR Tel: 82-2-554-7200 Tel: 31-416-690399 Itasca, IL Tel: 852-2401-1200 Fax: 82-2-558-5932 or Fax: 31-416-690340 Tel: 630-285-0071 Fax: 852-2401-3431 82-2-558-5934 Spain - Madrid Fax: 630-285-0075 China - Nanjing Malaysia - Kuala Lumpur Tel: 34-91-708-08-90 Dallas Tel: 86-25-8473-2460 Tel: 60-3-6201-9857 Fax: 34-91-708-08-91 Addison, TX Fax: 86-25-8473-2470 Fax: 60-3-6201-9859 UK - Wokingham Tel: 972-818-7423 China - Qingdao Malaysia - Penang Tel: 44-118-921-5869 Fax: 972-818-2924 Tel: 86-532-8502-7355 Tel: 60-4-227-8870 Fax: 44-118-921-5820 Detroit Fax: 86-532-8502-7205 Fax: 60-4-227-4068 Farmington Hills, MI China - Shanghai Philippines - Manila Tel: 248-538-2250 Tel: 86-21-5407-5533 Tel: 63-2-634-9065 Fax: 248-538-2260 Fax: 86-21-5407-5066 Fax: 63-2-634-9069 Kokomo China - Shenyang Singapore Kokomo, IN Tel: 86-24-2334-2829 Tel: 65-6334-8870 Tel: 765-864-8360 Fax: 86-24-2334-2393 Fax: 65-6334-8850 Fax: 765-864-8387 China - Shenzhen Taiwan - Hsin Chu Los Angeles Tel: 86-755-8203-2660 Tel: 886-3-572-9526 Mission Viejo, CA Fax: 86-755-8203-1760 Fax: 886-3-572-6459 Tel: 949-462-9523 Fax: 949-462-9608 China - Wuhan Taiwan - Kaohsiung Tel: 86-27-5980-5300 Tel: 886-7-536-4818 Santa Clara Fax: 86-27-5980-5118 Fax: 886-7-536-4803 Santa Clara, CA China - Xiamen Taiwan - Taipei Tel: 408-961-6444 Tel: 86-592-2388138 Tel: 886-2-2500-6610 Fax: 408-961-6445 Fax: 86-592-2388130 Fax: 886-2-2508-0102 Toronto China - Xian Thailand - Bangkok Mississauga, Ontario, Tel: 86-29-8833-7252 Tel: 66-2-694-1351 Canada Fax: 86-29-8833-7256 Fax: 66-2-694-1350 Tel: 905-673-0699 Fax: 905-673-6509 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 01/02/08 DS22056B-page 38 © 2008 Microchip Technology Inc.

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: MCP1825-0802E/AT MCP1825-0802E/ET MCP1825-1202E/AT MCP1825-1202E/ET MCP1825-1802E/AT MCP1825-1802E/ET MCP1825-2502E/AT MCP1825-2502E/ET MCP1825-3002E/AT MCP1825-3002E/ET MCP1825-3302E/AT MCP1825-3302E/ET MCP1825-5002E/AT MCP1825-5002E/ET MCP1825-ADJE/AT MCP1825- ADJE/ET MCP1825S-0802E/AB MCP1825S-0802E/DB MCP1825S-0802E/EB MCP1825S-1202E/AB MCP1825S- 1202E/DB MCP1825S-1202E/EB MCP1825S-1802E/AB MCP1825S-1802E/DB MCP1825S-1802E/EB MCP1825S- 2502E/AB MCP1825S-2502E/DB MCP1825S-2502E/EB MCP1825S-3002E/AB MCP1825S-3002E/DB MCP1825S- 3002E/EB MCP1825S-3302E/AB MCP1825S-3302E/DB MCP1825S-3302E/EB MCP1825S-5002E/AB MCP1825S- 5002E/DB MCP1825S-5002E/EB MCP1825ST-0802E/DB MCP1825ST-0802E/EB MCP1825ST-1202E/DB MCP1825ST-1202E/EB MCP1825ST-1802E/DB MCP1825ST-1802E/EB MCP1825ST-2502E/DB MCP1825ST- 2502E/EB MCP1825ST-3002E/DB MCP1825ST-3002E/EB MCP1825ST-3302E/DB MCP1825ST-3302E/EB MCP1825ST-5002E/DB MCP1825ST-5002E/EB MCP1825T-0802E/DC MCP1825T-0802E/ET MCP1825T-1202E/DC MCP1825T-1202E/ET MCP1825T-1802E/DC MCP1825T-1802E/ET MCP1825T-2502E/DC MCP1825T-2502E/ET MCP1825T-3002E/DC MCP1825T-3002E/ET MCP1825T-3302E/DC MCP1825T-3302E/ET MCP1825T-5002E/DC MCP1825T-5002E/ET MCP1825T-ADJE/DC MCP1825T-ADJE/ET