MCP1824/MCP1824S 300 mA, Low Voltage, Low Quiescent Current LDO Regulator Features Description • 300mA Output Current Capability The MCP1824/MCP1824S is a 300mA Low Dropout (cid:129) Input Operating Voltage Range: 2.1V to 6.0V (LDO) linear regulator that provides high current and low output voltages. The MCP1824 comes in a fixed or (cid:129) Adjustable Output Voltage Range: 0.8V to 5.0V adjustable output voltage version, with an output (MCP1824 only) voltage range of 0.8V to 5.0V. The 300mA output (cid:129) Standard Fixed Output Voltages: current capability, combined with the low output voltage - 0.8V, 1.2V, 1.8V, 2.5V, 3.0V, 3.3V, 5.0V capability, make the MCP1824 a good choice for new (cid:129) Other Fixed Output Voltage Options Available sub-1.8V output voltage LDO applications that have Upon Request high current demands. The MCP1824S is a 3-pin fixed (cid:129) Low Dropout Voltage: 200mV Typical at 300mA voltage version. (cid:129) Typical Output Voltage Tolerance: 0.4% The MCP1824/MCP1824S is stable using ceramic (cid:129) Stable with 1.0µF Ceramic Output Capacitor output capacitors that inherently provide lower output (cid:129) Fast Response to Load Transients noise and reduce the size and cost of the entire regulator solution. Only 1µF of output capacitance is (cid:129) Low Supply Current: 120µA (typical) needed to stabilize the LDO. (cid:129) Low Shutdown Supply Current: 0.1µA (typical) (MCP1824 only) Using CMOS construction, the quiescent current consumed by the MCP1824/MCP1824S is typically (cid:129) Fixed Delay on Power Good Output less than 120µA over the entire input voltage range, (MCP1824 only) making it attractive for portable computing applications (cid:129) Short Circuit Current Limiting and that demand high output current. The MCP1824 Overtemperature Protection versions have a Shutdown (SHDN) pin. When shut (cid:129) 5-Lead Plastic SOT-223, SOT-23 Package down, the quiescent current is reduced to less than Options (MCP1824) 0.1µA. (cid:129) 3-Lead Plastic SOT-223 Package Option On the MCP1824 fixed output versions, the scaled- (MCP1824S) down output voltage is internally monitored and a power good (PWRGD) output is provided when the Applications output is within 92% of regulation (typical). The PWRGD delay is internally fixed at 110µs (typical). (cid:129) High-Speed Driver Chipset Power (cid:129) Networking Backplane Cards The overtemperature and short circuit current-limiting provide additional protection for the LDO during system (cid:129) Notebook Computers fault conditions. (cid:129) Network Interface Cards (cid:129) Palmtop Computers (cid:129) 2.5V to 1.XV Regulators © 2007 Microchip Technology Inc. DS22070A-page 1

MCP1824/MCP1824S Package Types MCP1824 MCP1824S Fixed/Adjustable SOT-223-5 SOT-23-5 SOT-223-3 6 4 5 4 1 2 3 1 2 3 4 5 1 2 3 SOT-223 SOT-23 Pin SOT-223 Pin Fixed Adjustable Fixed Adjustable 1 VIN 2 GND (TAB) 1 SHDN SHDN VIN VIN 3 VOUT 2 VIN VIN GND (TAB) GND (TAB) 4 GND (TAB) 3 GND (TAB) GND (TAB) SHDN SHDN 4 VOUT VOUT PWRGD ADJ 5 PWRGD ADJ VOUT VOUT 6 GND (TAB) GND (TAB) — — © DS22070A-page 2 2007 Microchip Technology Inc.

MCP1824/MCP1824S Typical Applications MCP1824 Fixed Output Voltage PWRGD R 1 On 100kΩ Off SHDN 1 VIN = 2.3V to 2.8V VIN VOUT VOUT = 1.8V @ 300mA GND C 1 C 4.7µF 2 1µF MCP1824 Adjustable Output Voltage V ADJ R 2 20kΩ R 1 On 40kΩ Off SHDN VIN = 2.1V to 2.8V VIN 1 VOUT VOUT = 1.2V @ 300mA C 1 C 4.7µF 2 1µF GND © 2007 Microchip Technology Inc. DS22070A-page 3

MCP1824/MCP1824S Functional Block Diagram - Adjustable Output (MCP1824) PMOS VIN VOUT Undervoltage Lock Out (UVLO) I SNS Cf Rf SHDN ADJ/SENSE + Driver w/limit EA and SHDN Overtemperature – Sensing SHDN V REF VIN SHDN Reference Soft-Start Comp T DELAY GND 92% of V REF © DS22070A-page 4 2007 Microchip Technology Inc.

MCP1824/MCP1824S Functional Block Diagram - Fixed Output (MCP1824S) PMOS VIN VOUT Undervoltage Sense Lock Out (UVLO) I SNS Cf Rf SHDN + Driver w/limit EA and SHDN Overtemperature – Sensing SHDN V REF VIN SHDN Reference Soft-Start Comp T DELAY GND 92% of V REF © 2007 Microchip Technology Inc. DS22070A-page 5

MCP1824/MCP1824S Functional Block Diagram - Fixed Output (MCP1824) PMOS VIN VOUT Undervoltage Sense Lock Out (UVLO) I SNS Cf Rf SHDN + Driver w/limit EA and SHDN Overtemperature – Sensing SHDN V REF VIN SHDN Reference Soft-Start PWRGD Comp T DELAY GND 92% of V REF © DS22070A-page 6 2007 Microchip Technology Inc.

MCP1824/MCP1824S 1.0 ELECTRICAL † Notice: Stresses above those listed under “Maximum Rat- ings” may cause permanent damage to the device. This is a CHARACTERISTICS stress rating only and functional operation of the device at those or any other conditions above those indicated in the Absolute Maximum Ratings † operational listings of this specification is not implied. Expo- sure to maximum rating conditions for extended periods may Input Voltage, VIN.............................................................6.5V affect device reliability. Maximum Voltage on Any Pin...(GND – 0.3V) to (V + 0.3)V IN Maximum Power Dissipation.........Internally-Limited (Note6) Output Short Circuit Duration................................Continuous Storage temperature.....................................-65°C to +150°C Maximum Junction Temperature, T ...........................+150°C J Operating Junction Temperature, T .............-40°C to +125°C J EESD protection on all pins........... ≥ 4kV HBM; ≥ 300V MM AC/DC CHARACTERISTICS Electrical Specifications: Unless otherwise noted, V = V + V , Note1, V = 1.8V for Adjustable Output, IN OUT(MAX) DROPOUT(MAX) R I = 1mA, C = C = 4.7µF (X7R Ceramic), T = +25°C. OUT IN OUT A Boldface type applies for junction temperatures, T (Note7) of -40°C to +125°C J Parameters Sym Min Typ Max Units Conditions Input Operating Voltage V 2.1 — 6.0 V IN Output Voltage Range V 0.8 — 5.0 V OUT Input Quiescent Current I — 120 220 µA I = 0mA, V = 0.8V to q L OUT 5.0V Input Quiescent Current for I — 0.1 3 µA SHDN = GND SHDN SHDN Mode Maximum Continuous Output I 300 — — mA V = 2.1V to 6.0V OUT IN Current V = 0.8V to 5.0V R Line Regulation ΔV / — ±0.05 ±0.17 %/V (Note1) ≤ V ≤ 6V OUT IN (V x ΔV ) OUT IN Load Regulation ΔV /V -1.0 ±0.5 1.0 % I = 1mA to 300mA, OUT OUT OUT (Note4) Output Short Circuit Current I — 720 — mA R <0.1Ω, Peak Current OUT_SC LOAD Dropout Voltage V — 200 320 mV Note5, I = 300mA, DROPOUT OUT V =2.1V IN(MIN) Pulsed Applications Maximum Pulsed Output I — 500 — mA V = 2.1V to 6.0V PULSE IN Current V = 0.8V to 5.0V, R Duty Cycle ≤ 60%, Period < 10ms Note 1: The minimum V must meet two conditions: V ≥ 2.1V and V ≥ V + V IN IN IN OUT(MAX) DROPOUT(MAX). 2: V is the nominal regulator output voltage for the fixed cases. V = 1.2V, 1.8V, etc. V is the desired set point output R R R voltage for the adjustable cases. V = V ((R /R )+1). Figure4-1. R ADJ* 1 2 3: TCV = (V – V ) *106 / (V * ΔTemperature). V is the highest voltage measured over the OUT OUT-HIGH OUT-LOW R OUT-HIGH temperature range. V is the lowest voltage measured over the temperature range. OUT-LOW 4: Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is tested over a load range from 1mA to the maximum specified output current. 5: Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its nominal value that was measured with an input voltage of V = V + V . IN OUT(MAX) DROPOUT(MAX) 6: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air. (i.e., T , T , θ ). Exceeding the maximum allowable power A J JA dissipation will cause the device operating junction temperature to exceed the maximum +150°C rating. Sustained junction temperatures above 150°C can impact device reliability. 7: The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the desired junction temperature. The test time is small enough such that the rise in the junction temperature over the ambient temperature is not significant. © 2007 Microchip Technology Inc. DS22070A-page 7

MCP1824/MCP1824S AC/DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise noted, V = V + V , Note1, V = 1.8V for Adjustable Output, IN OUT(MAX) DROPOUT(MAX) R I = 1mA, C = C = 4.7µF (X7R Ceramic), T = +25°C. OUT IN OUT A Boldface type applies for junction temperatures, T (Note7) of -40°C to +125°C J Parameters Sym Min Typ Max Units Conditions Maximum Pulsed Output Duty I — — 60 % V = 2.1V to 6.0V, PULSE_DUTY IN Cycle V = 0.8V to 5.0V, R I = 500mA, OUT Period < 10ms Maximum Pulsed Output Period I — — 10 ms V = 2.1V to 6.0V PULSE_PERIOD IN V = 0.8V to 5.0V, R I = 500mA OUT Adjust Pin Characteristics (Adjustable Output Only) Adjustable Output Voltage V 0.8 — 5.5 V OUT_ADJ Range Adjust Pin Reference Voltage V 0.402 0.410 0.418 V V = 2.1V to V =6.0V, ADJ IN IN I = 1mA OUT Adjust Pin Leakage Current I -10 ±0.01 +10 nA V = 6.0V, V =0Vto6V ADJ IN ADJ Adjust Temperature Coefficient TCV — 40 — ppm/°C Note3 OUT Fixed-Output Characteristics (Fixed Output Only) Voltage Regulation V V - 2.5% V ±0.5% V + 2.5% V Note2 OUT R R R Power Good Characteristics PWRGD Input Voltage Operat- V 1.0 — 6.0 V T = +25°C PWRGD_VIN A ing Range 1.2 — 6.0 T = -40°C to +125°C A For V < 2.1V, I =100µA IN SINK PWRGD Threshold Voltage V %V Falling Edge PWRGD_TH OUT (Referenced to V ) OUT 89 92 95 V < 2.5V Fixed, OUT V = Adj. OUT 90 92 94 V >= 2.5V Fixed OUT PWRGD Threshold Hysteresis V 1.0 2.0 3.0 %V PWRGD_HYS OUT PWRGD Output Voltage Low V — 0.05 0.4 V I = 1.2mA, PWRGD_L PWRGDSINK ADJ = 0V PWRGD Output Current Sink I 1.2 6.0 — mA V = 0.200V PWRGD PWRGD Capability PWRGD Leakage P _ — 1 — nA V = V = 6.0V WRGD LK PWRGD IN PWRGD Time Delay T — 110 — µs Rising Edge PG R = 10kΩ PULLUP Note 1: The minimum V must meet two conditions: V ≥ 2.1V and V ≥ V + V IN IN IN OUT(MAX) DROPOUT(MAX). 2: V is the nominal regulator output voltage for the fixed cases. V = 1.2V, 1.8V, etc. V is the desired set point output R R R voltage for the adjustable cases. V = V ((R /R )+1). Figure4-1. R ADJ* 1 2 3: TCV = (V – V ) *106 / (V * ΔTemperature). V is the highest voltage measured over the OUT OUT-HIGH OUT-LOW R OUT-HIGH temperature range. V is the lowest voltage measured over the temperature range. OUT-LOW 4: Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is tested over a load range from 1mA to the maximum specified output current. 5: Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its nominal value that was measured with an input voltage of V = V + V . IN OUT(MAX) DROPOUT(MAX) 6: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air. (i.e., T , T , θ ). Exceeding the maximum allowable power A J JA dissipation will cause the device operating junction temperature to exceed the maximum +150°C rating. Sustained junction temperatures above 150°C can impact device reliability. 7: The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the desired junction temperature. The test time is small enough such that the rise in the junction temperature over the ambient temperature is not significant. © DS22070A-page 8 2007 Microchip Technology Inc.

MCP1824/MCP1824S AC/DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise noted, V = V + V , Note1, V = 1.8V for Adjustable Output, IN OUT(MAX) DROPOUT(MAX) R I = 1mA, C = C = 4.7µF (X7R Ceramic), T = +25°C. OUT IN OUT A Boldface type applies for junction temperatures, T (Note7) of -40°C to +125°C J Parameters Sym Min Typ Max Units Conditions Detect Threshold to PWRGD T — 200 — µs V = V + 50mV VDET-PWRGD OUT PWRGD_TH Active Time Delay to V - 50mV PWRGD_TH Shutdown Input Logic High Input V 45 — — %V V = 2.1V to 6.0V SHDN-HIGH IN IN Logic Low Input V — — 15 %V V = 2.1V to 6.0V SHDN-LOW IN IN SHDN Input Leakage Current SHDN -0.1 ±0.001 +0.1 µA V =6V, SHDN =V , ILK IN IN SHDN = GND AC Performance Output Delay From SHDN T — 100 — µs SHDN = GND to V , OR IN V = GND to 95% V OUT R Output Noise e — 2.0 — µV/√Hz I = 200mA, f = 1kHz, N OUT C = 10µF (X7R Ceramic), OUT V = 2.5V OUT Power Supply Ripple Rejection PSRR — 55 — dB f = 100Hz, Ratio I = 10mA, OUT V = 200mV pk-pk, INAC C = 0µF IN Thermal Shutdown Temperature T — 150 — °C I = 100µA, V = 1.8V, SD OUT OUT V = 2.8V IN Thermal Shutdown Hysteresis ΔT — 10 — °C I = 100µA, V = 1.8V, SD OUT OUT V = 2.8V IN Note 1: The minimum V must meet two conditions: V ≥ 2.1V and V ≥ V + V IN IN IN OUT(MAX) DROPOUT(MAX). 2: V is the nominal regulator output voltage for the fixed cases. V = 1.2V, 1.8V, etc. V is the desired set point output R R R voltage for the adjustable cases. V = V ((R /R )+1). Figure4-1. R ADJ* 1 2 3: TCV = (V – V ) *106 / (V * ΔTemperature). V is the highest voltage measured over the OUT OUT-HIGH OUT-LOW R OUT-HIGH temperature range. V is the lowest voltage measured over the temperature range. OUT-LOW 4: Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is tested over a load range from 1mA to the maximum specified output current. 5: Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its nominal value that was measured with an input voltage of V = V + V . IN OUT(MAX) DROPOUT(MAX) 6: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air. (i.e., T , T , θ ). Exceeding the maximum allowable power A J JA dissipation will cause the device operating junction temperature to exceed the maximum +150°C rating. Sustained junction temperatures above 150°C can impact device reliability. 7: The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the desired junction temperature. The test time is small enough such that the rise in the junction temperature over the ambient temperature is not significant. © 2007 Microchip Technology Inc. DS22070A-page 9

MCP1824/MCP1824S TEMPERATURE SPECIFICATIONS Parameters Sym Min Typ Max Units Conditions Temperature Ranges Operating Junction Temperature Range T -40 — +125 °C Steady State J Maximum Junction Temperature T — — +150 °C Transient J Storage Temperature Range T -65 — +150 °C A Thermal Package Resistances Thermal Resistance, 3LD SOT-223 θ — 62 — °C/W EIA/JEDEC JESD51-751-7 JA θ — 15 — 4 Layer Board JC Thermal Resistance, 5LD SOT-23 θ — 256 — °C/W EIA/JEDEC JESD51-751-7 JA θ — 81 — 4 Layer Board JC Thermal Resistance, 5LD SOT-223 θ — 62 — °C/W EIA/JEDEC JESD51-751-7 JA θ — 15 — 4 Layer Board JC © DS22070A-page 10 2007 Microchip Technology Inc.

MCP1824/MCP1824S 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated,C = 4.7µF Ceramic (X7R), C = 4.7µF Ceramic (X7R), I = 1mA, OUT IN OUT Temperature = +25°C, V = V + 0.5V, Fixed output, SHDN = 10kΩ pullup to V . IN OUT IN 140 0.10 Quiescent Current (A)μ111101230000 VIOOUUTT = = 10- 29314 05m00.5°2°°°°CCAVCCC Adj Line Regulation (%/V) ----000000000.........000000000864202468 IOUT=100 mIOAUT=20IO0U ImTO =UAT 1= 3m0A0I OmUTA = 50 mVAINV =O U2T. 1=V 1 t.2oV 6 .a0dVj 90 -0.10 2 3 4 5 6 -45 -20 5 30 55 80 105 130 Input Voltage (V) Temperature (°C) FIGURE 2-1: Quiescent Current vs. Input FIGURE 2-4: Line Regulation vs. Voltage (Adjustable Version). Temperature (Adjustable Version). 180 0.10 170 VOUT = 1.2V Adj VOUT = 3.3V IOUT = 1.0 mA to 300 mA A)μ %) 0.05 VOUT = 0.8V urrent ( 111456000 VIN=3.3VVIN=5.0V ulation ( -00..0050 VOUT = 1.8V C g und 130 d Re -0.10 Gro 120 Loa -0.15 VOUT = 5.0V 110 VIN=2.5V 100 -0.20 0 50 100 150 200 250 300 -45 -20 5 30 55 80 105 130 Load Current (mA) Temperature (°C) FIGURE 2-2: Ground Current vs. Load FIGURE 2-5: Load Regulation vs. Current (Adjustable Version). Temperature (Adjustable Version). 170 0.413 urrent (A)μ111456000 VIN=6.0V V O IUOTU =T =0 .08 Vm AAdj oltage (V) 00..441112 VIN = 6.0V VIOOUUTT = = 1 1.0.2 mVA Quiescent C 111101230000 VIN=5.0V VIN=4.0V Adjust Pin V 000...444001890 VVINI N= = 4 2.0.1VV VIN=2.1V VIN=3.0V 90 0.407 -45 -20 5 30 55 80 105 130 -45 -20 5 30 55 80 105 130 Temperature (°C) Temperature (°C) FIGURE 2-3: Quiescent Current vs. FIGURE 2-6: Adjust Pin Voltage vs. Junction Temperature (Adjustable Version). Temperature (Adjustable Version). © 2007 Microchip Technology Inc. DS22070A-page 11

MCP1824/MCP1824S Note: Unless otherwise indicated,C = 4.7µF Ceramic (X7R), C = 4.7µF Ceramic (X7R), I = 1mA, OUT IN OUT Temperature = +25°C, V = V + 0.5V, Fixed output, SHDN = 10kΩ pullup to V IN OUT IN. 0.30 160 VOUT = 0.8V V) 0.25 A)μ150 IOUT = 0 mA ut Voltage ( 00..1250 VOUT = 5.0V Adj nt Current ( 111234000 +1++392005°°°CCC Dropo 00..0150 VOUT = 2.5V Adj Quiesce 110100 -4 05°°CC 0.00 90 0 50 100 150 200 250 300 2 3 4 5 6 Load Current (mA) Input Voltage (V) FIGURE 2-7: Dropout Voltage vs. Load FIGURE 2-10: Quiescent Current vs. Input Current (Adjustable Version). Voltage. 0.24 150 0.23 IOUT = 300 mA VOUT = 2.5V V) 0.22 A)μ140 IOUT = 0 mA Voltage ( 000...122901 VOUT = 5.0V Adj Current ( 112300 ++19300°°CC Dropout 000...111678 VOUT = 2.5V AdjVOUT = 3.3V Adj uiescent 110100 +-+42505°°°CCC 0.15 Q 0.14 90 -45 -20 5 30 55 80 105 130 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Temperature (°C) Input Voltage (V) FIGURE 2-8: Dropout Voltage vs. FIGURE 2-11: Quiescent Current vs. Input Temperature (Adjustable Version). Voltage. µS) 110 VOUT = 0.8V Fixed 250 VIN = 2.1V for VR=0.8V e Delay ( 19000 VIN = 5.0V IOUT = 0 mA ent (A)μ125000 VOUTV=I3N .=0 V3.5V for VR=3.0V er Good Tim 678000 VIN = 2.1V VIN = 3.3V Ground Curr 15000 VOUT=0.8V w o P 50 0 -45 -20 5 30 55 80 105 130 0 50 100 150 200 250 300 Temperature (°C) Load Current (mA) FIGURE 2-9: Power Good (PWRGD) FIGURE 2-12: Ground Current vs. Load Time Delay vs. Temperature. Current. © DS22070A-page 12 2007 Microchip Technology Inc.

MCP1824/MCP1824S Note: Unless otherwise indicated,C = 4.7µF Ceramic (X7R), C = 4.7µF Ceramic (X7R), I = 1mA, OUT IN OUT Temperature = +25°C, V = V + 0.5V, Fixed output, SHDN = 10kΩ pullup to V . IN OUT IN 130 0.042 A)μ125 IOUT = 0 mA V) 0.038 IOUT = 1 mA V I N = 3 .V0RV = t o2 .65.V0V cent Current ( 111101125050 VOUT = 2.5VVOUT c= 0.8V Regulation (%/ 0000....000022332604 IOUT = 50 mA IOUT = 100 mA Quies 19050 Line 00..001148 IOUT = 200 mA IOUT = 300 mA 90 0.010 -45 -20 5 30 55 80 105 130 -45 -20 5 30 55 80 105 130 Temperature (°C) Temperature (°C) FIGURE 2-13: Quiescent Current vs. FIGURE 2-16: Line Regulation vs. Temperature. Temperature. 0.20 0.20 0.18 VR = 0.8V 0.15 VOUT = 0.8V A)μ000...111246 on (%) 00..0150 VIN = 4.0V IOUT = 1 mA to 300 mA Ishdn ( 0000....00014680 VIN = 6.0V VIN = 3.3V VIN = 2.3V ad Regulati ---0000....11005050 VVININ = = 2 6.1.0VV VIN = 5.0V o 0.02 L -0.20 0.00 -0.25 -45 -20 5 30 55 80 105 130 -45 -20 5 30 55 80 105 130 Temperature (°C) Temperature (°C) FIGURE 2-14: I vs. Temperature. FIGURE 2-17: Load Regulation vs. SHDN Temperature. 0.10 0.10 %/V) 00..0089 IOUT = 1 mA VVOINU =T =2 .01.V8 Vto 6.0V %) 00..0005 VOUT = 0.8V IOUT = 1 mA to 300 mA Line Regulation ( 0000000.......00000001234567 IIOOUUTT == 25000 m mAA IOUT = 300 mA IOUT = 100 mA Load Regulation ( -----00000.....2211050505 VVOOUUTT == 25..50VV 0.00 -0.30 -45 -20 5 30 55 80 105 130 -45 -20 5 30 55 80 105 130 Temperature (°C) Temperature (°C) FIGURE 2-15: Line Regulation vs. FIGURE 2-18: Load Regulation vs. Temperature. Temperature. © 2007 Microchip Technology Inc. DS22070A-page 13

MCP1824/MCP1824S Note: Unless otherwise indicated, C = 4.7µF Ceramic (X7R), C = 4.7µF Ceramic (X7R), I = 1mA, OUT IN OUT Temperature = +25°C, V = V + 0.5V, Fixed output, SHDN = 10kΩ pullup to V . IN OUT IN 0.20 10.000 μ 0.18 VR=3.0V, VIN=3.8V COUT=10 μF cer V) 0.16 CIN=4.7 F cer ut Voltage ( 0000....01118024 VOUT = 5.0V VOUT = 2.5V √e (mV/Hz) 1.000 VR=0.8V, VIN=2.1V IOUT=200 mA Dropo 00..0046 Nois 0.100 0.02 0.00 0.010 0 50 100 150 200 250 300 0.01 0.1 1 10 100 1000 Load Current (mA) Frequency (kHz) FIGURE 2-19: Dropout Voltage vs. Load FIGURE 2-22: Output Noise Voltage Current. Density vs. Frequency. 0.24 0.0 IOUT = 300 mA V) 0.22 -10.0 ut Voltage ( 00..1280 VOUT = 5.0V RR (dB) ---432000...000 VR=1.2V Adj Dropo 00..1146 VOUT = 2.5V PS --6500..00 VVCIIINNN=A=C20 . =5μ V2F00 mV p-p -70.0 IOUT=10 mA 0.12 -80.0 -45 -20 5 30 55 80 105 130 0.01 0.1 1 10 100 1000 Temperature (°C) Frequency (kHz) FIGURE 2-20: Dropout Voltage vs. FIGURE 2-23: Power Supply Ripple Temperature. Rejection (PSRR) vs. Frequency (Adj.). 0.0 600.00 mA) VOUT = 0.8V -10.0 Circuit Current ( 234500000000....00000000 PSRR (dB)-----6543200000.....00000 VVVRIINN==A3C3=..05μ2VV0 0(F mixVe dp)-p hort 100.00 --8700..00 ICOIUNT==01 0 FmA S 0.00 -90.0 0 1 2 3 4 5 6 0.01 0.1 1 10 100 1000 Input Voltage (V) Frequency (kHz) FIGURE 2-21: Short Circuit Current vs. FIGURE 2-24: Power Supply Ripple Input Voltage. Rejection (PSRR) vs. Frequency. © DS22070A-page 14 2007 Microchip Technology Inc.

MCP1824/MCP1824S Note: Unless otherwise indicated, C = 4.7µF Ceramic (X7R), C = 4.7µF Ceramic (X7R), I = 1mA, OUT IN OUT Temperature = +25°C, V = V + 0.5V, Fixed output, SHDN = 10kΩ pullup to V . IN OUT IN FIGURE 2-25: Startup from V FIGURE 2-28: Power Good (PWRGD) IN (Adjustable Version). Timing. FIGURE 2-26: Startup from Shutdown FIGURE 2-29: Dynamic Line Response. (Adjustable Version). FIGURE 2-27: Power Good (PWRGD) FIGURE 2-30: Dynamic Line Response. Timing. © 2007 Microchip Technology Inc. DS22070A-page 15

MCP1824/MCP1824S Note: Unless otherwise indicated, C = 4.7µF Ceramic (X7R), C = 4.7µF Ceramic (X7R), I = 1mA, OUT IN OUT Temperature = +25°C, V = V + 0.5V, Fixed output, SHDN = 10kΩ pullup to V . IN OUT IN 900 800 mV) 700 ge ( 600 VR = 0.8V Volta 450000 VR = 3.0V D G 300 R W 200 P 100 VR = 5.0V 0 0 2 4 6 8 10 12 14 16 18 20 PWRGD Sink Current (mA) FIGURE 2-31: Dynamic Load Response. FIGURE 2-33: Power Good Pulldown Voltage Vs Load. FIGURE 2-32: Dynamic Load Response. FIGURE 2-34: Startup Current. © DS22070A-page 16 2007 Microchip Technology Inc.

MCP1824/MCP1824S 3.0 PIN DESCRIPTION The descriptions of the pins are listed in Table3-1. TABLE 3-1: PIN FUNCTION TABLE SOT-223 SOT-23 Name Description 3-Pin 5-Pin 5-Pin 5-Pin 5-Pin Fixed Fixed Adj Fixed Adj — 1 1 3 3 SHDN Shutdown Control Input (active-low) 1 2 2 1 1 V Input Voltage Supply IN 2 3 3 2 2 GND Ground 3 4 4 5 5 V Regulated Output Voltage OUT — 5 — 4 — PWRGD Power Good Output — — 5 — 4 ADJ Output Voltage Adjust/Sense Input Exposed Exposed Exposed — — EP Exposed Pad of the Package (ground potential) Pad Pad Pad 3.1 Shutdown Control Input (SHDN) 3.4 Regulated Output Voltage (V ) OUT The SHDN input is used to turn the LDO output voltage The V pin is the regulated output voltage of the OUT on and off. When the SHDN input is at a logic-high LDO. A minimum output capacitance of 1.0µF is level, the LDO output voltage is enabled. When the required for LDO stability. The MCP1824/MCP1824S is SHDN input is pulled to a logic-low level, the LDO stable with ceramic, tantalum, and aluminum- output voltage is disabled. When the SHDN input is electrolytic capacitors. See Section4.3 “Output pulled low, the PWRGD output also goes low and the Capacitor” for output capacitor selection guidance. LDO enters a low quiescent current shutdown state where the typical quiescent current is 0.1µA. 3.5 Power Good Output (PWRGD) 3.2 Input Voltage Supply (V ) For fixed applications, the PWRGD output is an open- IN drain output used to indicate when the LDO output Connect the unregulated or regulated input voltage voltage is within 92% (typically) of its nominal source to V . If the input voltage source is located regulation value. The PWRGD threshold has a typical IN several inches away from the LDO, or the input source hysteresis value of 2%. The PWRGD output is delayed is a battery, it is recommended that an input capacitor by 110µs (typical) from the time the LDO output is be used. A typical input capacitance value of 1µF to within 92% + 3% (maximum hysteresis) of the 10µF should be sufficient for most applications. The regulated output value on power-up. This delay time is type of capacitor used can be ceramic, tantalum, or internally fixed. aluminum electrolytic. The low ESR characteristics of the ceramic capacitor will yield better noise and PSRR 3.6 Output Voltage Adjust Input (ADJ) performance at high frequency. For adjustable applications, the output voltage is 3.3 Ground (GND) connected to the ADJ input through a resistor divider that sets the output voltage regulation value. This For the optimal Noise and Power Supply Rejection provides the users the capability to set the output Ratio (PSRR) performance, the GND pin of the LDO voltage to any value they desire within the 0.8V to 5.0V should be tied to an electrically quiet circuit ground. range of the device. This will help the LDO power supply rejection ratio and 3.7 Exposed Pad (EP) noise performance. The ground pin of the LDO only conducts the ground current of the LDO, so a heavy The SOT-223 package has an exposed metal pad on trace is not required. For applications that have the bottom of the package. The exposed metal pad switching or noisy inputs, tie the GND pin to the return gives the device better thermal characteristics by of the output capacitor. Ground planes help lower providing a good thermal path to either the PCB or inductance and voltage spikes caused by fast transient heatsink to remove heat from the device. The exposed load currents and are recommended for applications pad of the package is at ground potential. that are subjected to fast load transients. © 2007 Microchip Technology Inc. DS22070A-page 17

MCP1824/MCP1824S 4.0 DEVICE OVERVIEW The allowable resistance value range for resistor R is 2 from 10kΩ to 200kΩ. Solving Equation4-1 for R 1 The MCP1824/MCP1824S is a 300mA output current, yields Equation4-2. Low Dropout (LDO) voltage regulator. The low dropout voltage of 200mV typical at 300mA of current makes EQUATION 4-2: CALCULATING ADJ PIN it ideal for battery-powered applications. The input RESISTOR VALUES voltage range is 2.1V to 6.0V. Unlike other high output ⎛ ⎞ current LDOs, the MCP1824/MCP1824S only draws a R = R ⎝V----O----U----T-–1⎠ maximum of 220µA of quiescent current. The 1 2 V ADJ MCP1824 adds a shutdown control input pin and a Where: power good output pin. The two output voltage options V = LDO Output Voltage are fixed or adjustable. The adjustable option is OUT available on the MCP1824 devices. The adjustable out- VADJ = ADJ Pin Voltage put voltage is set using two external resistors. (typically 0.41V) 4.1 LDO Output Voltage 4.2 Output Current and Current The MCP1824 LDO is available with either a fixed Limiting output voltage or an adjustable output voltage. The output voltage range is 0.8V to 5.0V for either version. The MCP1824/MCP1824S LDO is tested and ensured The MCP1824S LDO is available as a fixed voltage to supply a minimum of 300mA of output current. The device. MCP1824/MCP1824S has no minimum output load, so the output load current can go to 0mA and the LDO will 4.1.1 ADJUST INPUT continue to regulate the output voltage to within tolerance. The adjustable version of the MCP1824 uses the ADJ pin to get the output voltage feedback for output voltage The MCP1824/MCP1824S also incorporates an output regulation. This allows the user to set the output volt- current limit. If the output voltage falls below 0.7V due age of the device with two external resistors. The nom- to an overload condition (usually represents a shorted inal voltage for ADJ is 0.41V. load condition), the output current is limited to 720 mA (typical). If the overload condition is a soft overload, the Figure4-1 shows the adjustable version of the MCP1824/MCP1824S will supply higher load currents MCP1824. Resistors R and R form the resistor 1 2 of up to 900mA. The MCP1824/MCP1824S should not divider network necessary to set the output voltage. be operated in this condition continuously as it may With this configuration, Equation4-1 represents the result in failure of the device. However, this does allow equation for setting V . OUT for device usage in applications that have higher pulsed load currents having an average output current EQUATION 4-1: CALCULATING V ⎛ ⎞ OUT value of 300mA or less. V = V ⎝R----1----+-----R----2-⎠ Output overload conditions may also result in an over- OUT ADJ R 2 temperature shutdown of the device. If the junction Where: temperature rises above 150°C (typical), the LDO will V = LDO Output Voltage shut down the output voltage. See Section4.8 “Over- OUT temperature Protection” for more information on V = ADJ Pin Voltage ADJ overtemperature shutdown. (typically 0.41V) MCP1824-ADJ VOUT OffOn 1 2 3 4 5 R1 C2 SHDN ADJ 1µF VIN 4C.71µF GND R2 FIGURE 4-1: Typical Adjustable Output Voltage Application Circuit. © DS22070A-page 18 2007 Microchip Technology Inc.

MCP1824/MCP1824S 4.3 Output Capacitor delay is fixed at 110µs (typical). After the time delay period, the PWRGD output will go high, indicating that The MCP1824/MCP1824S requires a minimum output the output voltage is stable and within regulation limits. capacitance of 1µF for output voltage stability. Ceramic If the output voltage of the LDO falls below the power capacitors are recommended because of their size, good threshold, the power good output will transition cost, and environmental robustness qualities. low. The power good circuitry has a 200µs delay when Aluminum-electrolytic and tantalum capacitors can be detecting a falling output voltage, which helps to used on the LDO output as well. The Equivalent Series increase noise immunity of the power good output and Resistance (ESR) of the electrolytic output capacitor avoid false triggering of the power good output during must be no greater than 1 ohm. The output capacitor fast output transients. See Figure4-2 for power good should be located as close to the LDO output as is timing characteristics. practical. Ceramic materials X7R and X5R have low When the LDO is put into Shutdown mode using the temperature coefficients and are well within the SHDN input, the power good output is pulled low acceptable ESR range required. A typical 1µF X7R immediately, indicating that the output voltage will be 0805 capacitor has an ESR of 50 milli-ohms. out of regulation. The timing diagram for the power Larger LDO output capacitors can be used with the good output when using the shutdown input is shown in MCP1824/MCP1824S to improve dynamic Figure4-3. performance and power supply ripple rejection The power good output is an open-drain output that can performance. A maximum of 22µF is recommended. be pulled up to any voltage that is equal to or less than Aluminum-electrolytic capacitors are not recom- the LDO input voltage. This output is capable of sinking mended for low temperature applications of < -25°C. 1.2mA minimum (V < 0.4V maximum). PWRGD 4.4 Input Capacitor VPWRGD_TH Low input source impedance is necessary for the LDO output to operate properly. When operating from VOUT batteries, or in applications with long lead length TPG (> 10 inches) between the input source and the LDO, some input capacitance is recommended. A minimum of 1.0µF to 4.7µF is recommended for most VOH applications. TVDET_PWRGD For applications that have output step load PWRGD requirements, the input capacitance of the LDO is very important. The input capacitance provides the LDO VOL with a good local low-impedance source to pull the transient currents from, in order to respond quickly to the output load step. For good step response FIGURE 4-2: Power Good Timing. performance, the input capacitor should be of equivalent (or higher) value than the output capacitor. The capacitor should be placed as close to the input of the LDO as is practical. Larger input capacitors will also V help reduce any high-frequency noise on the input and IN TOR output of the LDO and reduce the effects of any inductance that exists between the input source 30 µs 70µs voltage and the input capacitance of the LDO. SHDN TPG 4.5 Power Good Output (PWRGD) The PWRGD output is used to indicate when the output voltage of the LDO is within 92% (typical value, see Section1.0 “Electrical Characteristics” for Minimum V OUT and Maximum specifications) of its nominal regulation value. As the output voltage of the LDO rises, the PWRGD output will be held low until the output voltage has PWRGD exceeded the power good threshold plus the hysteresis value. Once this threshold has been exceeded, the power good time delay is started (shown as T in the PG Electrical Characteristics table). The power good time FIGURE 4-3: Power Good Timing from Shutdown. © 2007 Microchip Technology Inc. DS22070A-page 19

MCP1824/MCP1824S 4.6 Shutdown Input (SHDN) 4.7 Dropout Voltage and Undervoltage Lockout The SHDN input is an active-low input signal that turns the LDO on and off. The SHDN threshold is a Dropout voltage is defined as the input-to-output percentage of the input voltage. The typical value of voltage differential at which the output voltage drops this shutdown threshold is 30% of VIN, with minimum 2% below the nominal value that was measured with a and maximum limits over the entire operating V + 0.5V differential applied. The MCP1824/ R temperature range of 45% and 15%, respectively. MCP1824S LDO has a very low dropout voltage The SHDN input will ignore low-going pulses (pulses specification of 210mV (typical) at 300mA of output meant to shut down the LDO) that are up to 400ns in current. See Section1.0 “Electrical Characteristics” pulse width. If the shutdown input is pulled low for more for maximum dropout voltage specifications. than 400ns, the LDO will enter Shutdown mode. This The MCP1824/MCP1824S LDO operates across an small bit of filtering helps to reject any system noise input voltage range of 2.1V to 6.0V and incorporates spikes on the shutdown input signal. input Undervoltage Lockout (UVLO) circuitry that keeps On the rising edge of the SHDN input, the shutdown the LDO output voltage off until the input voltage circuitry has a 30µs delay before allowing the LDO reaches a minimum of 2.00V (typical) on the rising output to turn on. This delay helps to reject any false edge of the input voltage. As the input voltage falls, the turn-on signals or noise on the SHDN input signal. After LDO output will remain on until the input voltage level the 30µs delay, the LDO output enters its soft-start reaches 1.82V (typical). period as it rises from 0V to its final regulation value. If Since the MCP1824/MCP1824S LDO undervoltage the SHDN input signal is pulled low during the 30µs lockout activates at 1.82V as the input voltage is falling, delay period, the timer will be reset and the delay time the dropout voltage specification does not apply for will start over again on the next rising edge of the output voltages that are less than 1.8V. SHDN input. The total time from the SHDN input going For high-current applications, voltage drops across the high (turn-on) to the LDO output being in regulation is PCB traces must be taken into account. The trace typically 100µs. See Figure4-4 for a timing diagram of resistances can cause significant voltage drops the SHDN input. between the input voltage source and the LDO. For applications with input voltages near 2.1V, these PCB TOR trace voltage drops can sometimes lower the input 400ns (typ) voltage enough to trigger a shutdown due to 70µs undervoltage lockout. 30µs 4.8 Overtemperature Protection SHDN The MCP1824/MCP1824S LDO has temperature- sensing circuitry to prevent the junction temperature from exceeding approximately 150°C. If the LDO junction temperature does reach 150°C, the LDO V OUT output will be turned off until the junction temperature cools to approximately 140°C, at which point the LDO output will automatically resume normal operation. If FIGURE 4-4: Shutdown Input Timing the internal power dissipation continues to be Diagram. excessive, the device will again shut off. The junction temperature of the die is a function of power dissipation, ambient temperature and package thermal resistance. See Section5.0 “Application Circuits/ Issues” for more information on LDO power dissipation and junction temperature. © DS22070A-page 20 2007 Microchip Technology Inc.

MCP1824/MCP1824S 5.0 APPLICATION CIRCUITS/ In addition to the LDO pass element power dissipation, ISSUES there is power dissipation within the MCP1824/ MCP1824S as a result of quiescent or ground current. The power dissipation as a result of the ground current 5.1 Typical Application can be calculated using the following equation: The MCP1824/MCP1824S is used for applications that EQUATION 5-2: require high LDO output current and a power good output. PI(GND) = VIN(MAX)×IVIN Where: VOUT = 2.5V @ 300mA P = Power dissipation due to the I(GND MCP1824-2.5 quiescent current of the LDO On R1 Off SHDN 1 2 3 4 5 10kΩ 1C02µF VIN(MAX) = Maximum input voltage I = Current flowing in the V pin VIN IN 3.3V VIN with no LDO output current C1 (LDO quiescent current) 4.7µF GND PWRGD The total power dissipated within the MCP1824/ MCP1824S is the sum of the power dissipated in the FIGURE 5-1: Typical Application Circuit. LDO pass device and the P(I ) term. Because of the GND CMOS construction, the typical I for the MCP1824/ GND 5.1.1 APPLICATION CONDITIONS MCP1824S is 120µA. Operating at a maximum V of IN 3.465V results in a power dissipation of 0.12milli-Watts Package Type = SOT-223-5 for a 2.5V output. For most applications, this is small Input Voltage Range = 3.3V ± 5% compared to the LDO pass device power dissipation V maximum = 3.465V and can be neglected. IN VIN minimum = 3.135V The maximum continuous operating junction V = 0.350V temperature specified for the MCP1824/MCP1824S is DROPOUT (max) +125°C. To estimate the internal junction temperature V (typical) = 2.5V OUT of the MCP1824/MCP1824S, the total internal power I = 300mA maximum OUT dissipation is multiplied by the thermal resistance from P (typical) = 0.240W junction to ambient (Rθ ) of the device. The thermal DISS JA Temperature Rise = 14.88°C resistance from junction to ambient for the SOT-223-5 package is estimated at 62°C/W. 5.2 Power Calculations EQUATION 5-3: 5.2.1 POWER DISSIPATION TJ(MAX) = PTOTAL×RθJA+TAMAX The internal power dissipation within the MCP1824/ T = Maximum continuous junction MCP1824S is a function of input voltage, output J(MAX) temperature voltage, output current and quiescent current. Equation5-1 can be used to calculate the internal PTOTAL = Total device power dissipation power dissipation for the LDO. Rθ = Thermal resistance from junction to JA ambient EQUATION 5-1: T = Maximum ambient temperature AMAX PLDO = (VIN(MAX))–VOUT(MIN))×IOUT(MAX)) Where: P = LDO Pass device internal LDO power dissipation V = Maximum input voltage IN(MAX) V = LDO minimum output voltage OUT(MIN) © 2007 Microchip Technology Inc. DS22070A-page 21

MCP1824/MCP1824S The maximum power dissipation capability for a 5.3 Typical Application package can be calculated given the junction-to- ambient thermal resistance and the maximum ambient Internal power dissipation, junction temperature rise, temperature for the application. Equation5-4 can be junction temperature, and maximum power dissipation used to determine the package maximum internal is calculated in the following example. The power power dissipation. dissipation as a result of ground current is small enough to be neglected. EQUATION 5-4: 5.3.1 POWER DISSIPATION EXAMPLE PD(MAX) = (---T----J--(--M----A---X--R--)--θ-–----T----A---(--M----A---X---)---) Package JA Package Type = SOT-223-5 P = Maximum device power dissipation D(MAX) Input Voltage T = maximum continuous junction J(MAX) V = 3.3V ± 5% temperature IN LDO Output Voltage and Current T = maximum ambient temperature A(MAX) Rθ = Thermal resistance from junction-to- VOUT = 2.5V JA ambient IOUT = 300mA Maximum Ambient Temperature EQUATION 5-5: TA(MAX) = 60°C TJ(RISE) = PD(MAX)×RθJA Internal Power Dissipation P = (V – V ) x I LDO(MAX) IN(MAX) OUT(MIN) OUT(MAX) T = Rise in device junction temperature P = ((3.3V x 1.05) – (2.5V x 0.975)) J(RISE) LDO over the ambient temperature x 300mA P = Maximum device power dissipation P = 0.308 Watts D(MAX) LDO RθJA = Thermal resistance from junction-to- 5.3.1.1 Device Junction Temperature Rise ambient The internal junction temperature rise is a function of internal power dissipation and the thermal resistance EQUATION 5-6: from junction-to-ambient for the application. The thermal resistance from junction-to-ambient (Rθ ) is TJ = TJ(RISE)+TA derived from EIA/JEDEC standards for measJuAring thermal resistance. The EIA/JEDEC specification is T = Junction temperature J JESD51. The standard describes the test method and TJ(RISE) = Rise in device junction temperature board specifications for measuring the thermal over the ambient temperature resistance from junction to ambient. The actual thermal T = Ambient temperature resistance for a particular application can vary A depending on many factors such as copper area and thickness. Refer to AN792, “A Method to Determine How Much Power a SOT23 Can Dissipate in an Application” (DS00792), for more information regarding this subject. T = P x Rθ J(RISE) TOTAL JA TJRISE = 0.308 W x 62° C/W T = 19.1°C JRISE © DS22070A-page 22 2007 Microchip Technology Inc.

MCP1824/MCP1824S 5.3.1.2 Junction Temperature Estimate To estimate the internal junction temperature, the calculated temperature rise is added to the ambient or offset temperature. For this example, the worst-case junction temperature is estimated below: T = T + T J JRISE A(MAX) T = 19.1°C + 60.0°C J T = 79.1°C J 5.3.1.3 Maximum Package Power Dissipation at 60°C Ambient Temperature SOT-223-5 (62°C/W Rθ ): JA P = (125°C – 60°C) / 62°C/W D(MAX) P = 1.048W D(MAX) SOT-23-5 (256°C/Watt Rθ ): JA P = (125°C – 60°C)/ 256°C/W D(MAX) P = 0.254W D(MAX) From this table, you can see the difference in maximum allowable power dissipation between the SOT-223-5 package and the SOT-23-5 package. © 2007 Microchip Technology Inc. DS22070A-page 23

MCP1824/MCP1824S 6.0 PACKAGING INFORMATION 6.1 Package Marking Information 3-Lead SOT-223 (MCP1824S) Example: Marking Part Number Code XXXXXXX MCP1824ST-0802E/DB 1824S08 1824S08 XXXYYWW MCP1824ST-1202E/DB 1824S12 EDB0710 NNN MCP1824ST-1802E/DB 1824S18 256 MCP1824ST-2502E/DB 1824S25 MCP1824ST-3002E/DB 1824S30 MCP1824ST-3302E/DB 1824S33 MCP1824ST-5002E/DB 1824S50 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © DS22070A-page 24 2007 Microchip Technology Inc.

MCP1824/MCP1824S Package Marking Information (Continued) 5-Lead SOT-223 (MCP1824) Example: Marking Part Number Code XXXXXXX MCP1824T-0802E/DC 1824082 1824082 XXXYYWW MCP1824T-1202E/DC 1824122 EDC0710 NNN MCP1824T-1802E/DC 1824182 256 MCP1824T-2502E/DC 1824252 MCP1824T-3002E/DC 1824302 MCP1824T-3302E/DC 1824332 MCP1824T-5002E/DC 1824502 MCP1824T-ADJE/DC 1824ADJ 5-Lead SOT-23 Example: Marking Part Number Code XXNN MCP1824T-0802E/OT ULNN UL25 MCP1824T-1202E/OT UMNN MCP1824T-1802E/OT UPNN 1 MCP1824T-2502E/OT UQNN 1 MCP1824T-3002E/OT URNN MCP1824T-3302E/OT USNN MCP1824T-5002E/OT UTNN MCP1824T-ADJE/OT UKNN © 2007 Microchip Technology Inc. DS22070A-page 25

MCP1824/MCP1824S (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:10)(cid:8)(cid:17)(cid:18)(cid:12)(cid:10)(cid:13)(cid:19)(cid:5)(cid:8)(cid:20)(cid:21)(cid:6)(cid:19)(cid:11)(cid:13)(cid:11)(cid:12)(cid:22)(cid:21)(cid:8)(cid:23)(cid:24)(cid:25)(cid:26)(cid:8)(cid:27)(cid:15)(cid:17)(cid:20)(cid:3)(cid:28)(cid:28)(cid:2)(cid:29) (cid:30)(cid:22)(cid:12)(cid:5)(cid:31) )(cid:10)(cid:21)(cid:11)(cid:15)(cid:20)(cid:7)(cid:11)(cid:6)(cid:10)(cid:9)(cid:15)(cid:11)(cid:16)(cid:18)(cid:21)(cid:21)(cid:7)(cid:8)(cid:15)(cid:11)(cid:22)(cid:12)(cid:16)*(cid:12)(cid:28)(cid:7)(cid:11)(cid:13)(cid:21)(cid:12)((cid:5)(cid:8)(cid:28)(cid:9)+(cid:11)(cid:22)(cid:17)(cid:7)(cid:12)(cid:9)(cid:7)(cid:11)(cid:9)(cid:7)(cid:7)(cid:11)(cid:15)(cid:20)(cid:7)(cid:11)(cid:23)(cid:5)(cid:16)(cid:21)(cid:10)(cid:16)(cid:20)(cid:5)(cid:22)(cid:11),(cid:12)(cid:16)*(cid:12)(cid:28)(cid:5)(cid:8)(cid:28)(cid:11)(cid:30)(cid:22)(cid:7)(cid:16)(cid:5)(cid:19)(cid:5)(cid:16)(cid:12)(cid:15)(cid:5)(cid:10)(cid:8)(cid:11)(cid:17)(cid:10)(cid:16)(cid:12)(cid:15)(cid:7)(cid:13)(cid:11)(cid:12)(cid:15)(cid:11) (cid:20)(cid:15)(cid:15)(cid:22)$--((((cid:3)(cid:6)(cid:5)(cid:16)(cid:21)(cid:10)(cid:16)(cid:20)(cid:5)(cid:22)(cid:3)(cid:16)(cid:10)(cid:6)-(cid:22)(cid:12)(cid:16)*(cid:12)(cid:28)(cid:5)(cid:8)(cid:28) D b2 E1 E 1 2 3 e e1 A A2 c φ b A1 L .(cid:8)(cid:5)(cid:15)(cid:9) (cid:23)/00/(cid:23)(cid:14)%(cid:14)1(cid:30) (cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:5)(cid:10)(cid:8)(cid:11)0(cid:5)(cid:6)(cid:5)(cid:15)(cid:9) (cid:23)/2 23(cid:23) (cid:23)(cid:29)4 2(cid:18)(cid:6)5(cid:7)(cid:21)(cid:11)(cid:10)(cid:19)(cid:11)0(cid:7)(cid:12)(cid:13)(cid:9) 2 6 0(cid:7)(cid:12)(cid:13)(cid:11),(cid:5)(cid:15)(cid:16)(cid:20) (cid:7) (cid:26)(cid:3)6(cid:25)(cid:11)"(cid:30)# 3(cid:18)(cid:15)(cid:9)(cid:5)(cid:13)(cid:7)(cid:11)0(cid:7)(cid:12)(cid:13)(cid:11),(cid:5)(cid:15)(cid:16)(cid:20) (cid:7)(cid:2) (cid:3)7(cid:25)(cid:11)"(cid:30)# 3’(cid:7)(cid:21)(cid:12)(cid:17)(cid:17)(cid:11)8(cid:7)(cid:5)(cid:28)(cid:20)(cid:15) (cid:29) 9 9 (cid:2)(cid:3):(cid:25) (cid:30)(cid:15)(cid:12)(cid:8)(cid:13)(cid:10)(cid:19)(cid:19) (cid:29)(cid:2) (cid:25)(cid:3)(cid:25)(cid:26) 9 (cid:25)(cid:3)(cid:2)(cid:25) (cid:23)(cid:10)(cid:17)(cid:13)(cid:7)(cid:13)(cid:11),(cid:12)(cid:16)*(cid:12)(cid:28)(cid:7)(cid:11)8(cid:7)(cid:5)(cid:28)(cid:20)(cid:15) (cid:29)(cid:26) (cid:2)(cid:3)!(cid:25) (cid:2)(cid:3)7(cid:25) (cid:2)(cid:3)(cid:27)(cid:25) 3’(cid:7)(cid:21)(cid:12)(cid:17)(cid:17)(cid:11);(cid:5)(cid:13)(cid:15)(cid:20) (cid:14) 7(cid:3)(cid:27)(cid:25) (cid:27)(cid:3)(cid:25)(cid:25) (cid:27)(cid:3)6(cid:25) (cid:23)(cid:10)(cid:17)(cid:13)(cid:7)(cid:13)(cid:11),(cid:12)(cid:16)*(cid:12)(cid:28)(cid:7)(cid:11);(cid:5)(cid:13)(cid:15)(cid:20) (cid:14)(cid:2) 6(cid:3)6(cid:25) 6(cid:3)!(cid:25) 6(cid:3)(cid:27)(cid:25) 3’(cid:7)(cid:21)(cid:12)(cid:17)(cid:17)(cid:11)0(cid:7)(cid:8)(cid:28)(cid:15)(cid:20) (cid:4) 7(cid:3)6(cid:25) 7(cid:3)!(cid:25) 7(cid:3)(cid:27)(cid:25) 0(cid:7)(cid:12)(cid:13)(cid:11)%(cid:20)(cid:5)(cid:16)*(cid:8)(cid:7)(cid:9)(cid:9) (cid:16) (cid:25)(cid:3)(cid:26)6 (cid:25)(cid:3)6(cid:25) (cid:25)(cid:3)6! 0(cid:7)(cid:12)(cid:13)(cid:11);(cid:5)(cid:13)(cid:15)(cid:20) 5 (cid:25)(cid:3)7(cid:25) (cid:25)(cid:3)(cid:27)7 (cid:25)(cid:3): %(cid:12)5(cid:11)0(cid:7)(cid:12)(cid:13)(cid:11);(cid:5)(cid:13)(cid:15)(cid:20) 5(cid:26) (cid:26)(cid:3)<(cid:25) 6(cid:3)(cid:25)(cid:25) 6(cid:3)(cid:2)(cid:25) )(cid:10)(cid:10)(cid:15)(cid:11)0(cid:7)(cid:8)(cid:28)(cid:15)(cid:20) 0 (cid:25)(cid:3)(cid:27)! 9 9 0(cid:7)(cid:12)(cid:13)(cid:11)(cid:29)(cid:8)(cid:28)(cid:17)(cid:7) (cid:2) (cid:25)= 9 (cid:2)(cid:25)= (cid:30)(cid:22)(cid:12)(cid:5)(cid:11)(cid:31) (cid:2)(cid:3) (cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:5)(cid:10)(cid:8)(cid:9)(cid:11)(cid:4)(cid:11)(cid:12)(cid:8)(cid:13)(cid:11)(cid:14)(cid:2)(cid:11)(cid:13)(cid:10)(cid:11)(cid:8)(cid:10)(cid:15)(cid:11)(cid:5)(cid:8)(cid:16)(cid:17)(cid:18)(cid:13)(cid:7)(cid:11)(cid:6)(cid:10)(cid:17)(cid:13)(cid:11)(cid:19)(cid:17)(cid:12)(cid:9)(cid:20)(cid:11)(cid:10)(cid:21)(cid:11)(cid:22)(cid:21)(cid:10)(cid:15)(cid:21)(cid:18)(cid:9)(cid:5)(cid:10)(cid:8)(cid:9)(cid:3)(cid:11)(cid:23)(cid:10)(cid:17)(cid:13)(cid:11)(cid:19)(cid:17)(cid:12)(cid:9)(cid:20)(cid:11)(cid:10)(cid:21)(cid:11)(cid:22)(cid:21)(cid:10)(cid:15)(cid:21)(cid:18)(cid:9)(cid:5)(cid:10)(cid:8)(cid:9)(cid:11)(cid:9)(cid:20)(cid:12)(cid:17)(cid:17)(cid:11)(cid:8)(cid:10)(cid:15)(cid:11)(cid:7)(cid:24)(cid:16)(cid:7)(cid:7)(cid:13)(cid:11)(cid:25)(cid:3)(cid:2)(cid:26)(cid:27)(cid:11)(cid:6)(cid:6)(cid:11)(cid:22)(cid:7)(cid:21)(cid:11)(cid:9)(cid:5)(cid:13)(cid:7)(cid:3) (cid:26)(cid:3) (cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:5)(cid:10)(cid:8)(cid:5)(cid:8)(cid:28)(cid:11)(cid:12)(cid:8)(cid:13)(cid:11)(cid:15)(cid:10)(cid:17)(cid:7)(cid:21)(cid:12)(cid:8)(cid:16)(cid:5)(cid:8)(cid:28)(cid:11)(cid:22)(cid:7)(cid:21)(cid:11)(cid:29)(cid:30)(cid:23)(cid:14)(cid:11)(cid:31)(cid:2) (cid:3)!(cid:23)(cid:3) "(cid:30)#$ "(cid:12)(cid:9)(cid:5)(cid:16)(cid:11)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:5)(cid:10)(cid:8)(cid:3)(cid:11)%(cid:20)(cid:7)(cid:10)(cid:21)(cid:7)(cid:15)(cid:5)(cid:16)(cid:12)(cid:17)(cid:17)&(cid:11)(cid:7)(cid:24)(cid:12)(cid:16)(cid:15)(cid:11)’(cid:12)(cid:17)(cid:18)(cid:7)(cid:11)(cid:9)(cid:20)(cid:10)((cid:8)(cid:11)((cid:5)(cid:15)(cid:20)(cid:10)(cid:18)(cid:15)(cid:11)(cid:15)(cid:10)(cid:17)(cid:7)(cid:21)(cid:12)(cid:8)(cid:16)(cid:7)(cid:9)(cid:3) (cid:23)(cid:5)(cid:16)(cid:21)(cid:10)(cid:16)(cid:20)(cid:5)(cid:22)%(cid:7)(cid:16)(cid:20)(cid:8)(cid:10)(cid:17)(cid:10)(cid:28)&(cid:4)(cid:21)(cid:12)((cid:5)(cid:8)(cid:28)#(cid:25) >(cid:25)6(cid:26)" © DS22070A-page 26 2007 Microchip Technology Inc.

MCP1824/MCP1824S (cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:10)(cid:8)(cid:17)(cid:18)(cid:12)(cid:10)(cid:13)(cid:19)(cid:5)(cid:8)(cid:20)(cid:21)(cid:6)(cid:19)(cid:11)(cid:13)(cid:11)(cid:12)(cid:22)(cid:21)(cid:8)(cid:23)(cid:24)!(cid:26)(cid:8)(cid:27)(cid:15)(cid:17)(cid:20)(cid:3)(cid:28)(cid:28)(cid:2)(cid:29) (cid:30)(cid:22)(cid:12)(cid:5)(cid:31) )(cid:10)(cid:21)(cid:11)(cid:15)(cid:20)(cid:7)(cid:11)(cid:6)(cid:10)(cid:9)(cid:15)(cid:11)(cid:16)(cid:18)(cid:21)(cid:21)(cid:7)(cid:8)(cid:15)(cid:11)(cid:22)(cid:12)(cid:16)*(cid:12)(cid:28)(cid:7)(cid:11)(cid:13)(cid:21)(cid:12)((cid:5)(cid:8)(cid:28)(cid:9)+(cid:11)(cid:22)(cid:17)(cid:7)(cid:12)(cid:9)(cid:7)(cid:11)(cid:9)(cid:7)(cid:7)(cid:11)(cid:15)(cid:20)(cid:7)(cid:11)(cid:23)(cid:5)(cid:16)(cid:21)(cid:10)(cid:16)(cid:20)(cid:5)(cid:22)(cid:11),(cid:12)(cid:16)*(cid:12)(cid:28)(cid:5)(cid:8)(cid:28)(cid:11)(cid:30)(cid:22)(cid:7)(cid:16)(cid:5)(cid:19)(cid:5)(cid:16)(cid:12)(cid:15)(cid:5)(cid:10)(cid:8)(cid:11)(cid:17)(cid:10)(cid:16)(cid:12)(cid:15)(cid:7)(cid:13)(cid:11)(cid:12)(cid:15)(cid:11) (cid:20)(cid:15)(cid:15)(cid:22)$--((((cid:3)(cid:6)(cid:5)(cid:16)(cid:21)(cid:10)(cid:16)(cid:20)(cid:5)(cid:22)(cid:3)(cid:16)(cid:10)(cid:6)-(cid:22)(cid:12)(cid:16)*(cid:12)(cid:28)(cid:5)(cid:8)(cid:28) D b2 E1 E 1 2 3 4 N e e1 A A2 c φ b A1 L .(cid:8)(cid:5)(cid:15)(cid:9) (cid:23)/00/(cid:23)(cid:14)%(cid:14)1(cid:30) (cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:5)(cid:10)(cid:8)(cid:11)0(cid:5)(cid:6)(cid:5)(cid:15)(cid:9) (cid:23)/2 23(cid:23) (cid:23)(cid:29)4 2(cid:18)(cid:6)5(cid:7)(cid:21)(cid:11)(cid:10)(cid:19)(cid:11)0(cid:7)(cid:12)(cid:13)(cid:9) 2 ! 0(cid:7)(cid:12)(cid:13)(cid:11),(cid:5)(cid:15)(cid:16)(cid:20) (cid:7) (cid:2)(cid:3)(cid:26)(cid:27)(cid:11)"(cid:30)# 3(cid:18)(cid:15)(cid:9)(cid:5)(cid:13)(cid:7)(cid:11)0(cid:7)(cid:12)(cid:13)(cid:11),(cid:5)(cid:15)(cid:16)(cid:20) (cid:7)(cid:2) !(cid:3)(cid:25):(cid:11)"(cid:30)# 3’(cid:7)(cid:21)(cid:12)(cid:17)(cid:17)(cid:11)8(cid:7)(cid:5)(cid:28)(cid:20)(cid:15) (cid:29) 9 9 (cid:2)(cid:3):(cid:25) (cid:30)(cid:15)(cid:12)(cid:8)(cid:13)(cid:10)(cid:19)(cid:19) (cid:29)(cid:2) (cid:25)(cid:3)(cid:25)(cid:26) (cid:25)(cid:3)(cid:25)7 (cid:25)(cid:3)(cid:2)(cid:25) (cid:23)(cid:10)(cid:17)(cid:13)(cid:7)(cid:13)(cid:11),(cid:12)(cid:16)*(cid:12)(cid:28)(cid:7)(cid:11)8(cid:7)(cid:5)(cid:28)(cid:20)(cid:15) (cid:29)(cid:26) (cid:2)(cid:3)!! (cid:2)(cid:3)7(cid:25) (cid:2)(cid:3)7! 3’(cid:7)(cid:21)(cid:12)(cid:17)(cid:17)(cid:11);(cid:5)(cid:13)(cid:15)(cid:20) (cid:14) 7(cid:3):7 (cid:27)(cid:3)(cid:25)(cid:25) (cid:27)(cid:3)(cid:26)7 (cid:23)(cid:10)(cid:17)(cid:13)(cid:7)(cid:13)(cid:11),(cid:12)(cid:16)*(cid:12)(cid:28)(cid:7)(cid:11);(cid:5)(cid:13)(cid:15)(cid:20) (cid:14)(cid:2) 6(cid:3) ! 6(cid:3)!(cid:25) 6(cid:3)!! 3’(cid:7)(cid:21)(cid:12)(cid:17)(cid:17)(cid:11)0(cid:7)(cid:8)(cid:28)(cid:15)(cid:20) (cid:4) 7(cid:3) ! 7(cid:3)!(cid:25) 7(cid:3)!! 0(cid:7)(cid:12)(cid:13)(cid:11)%(cid:20)(cid:5)(cid:16)*(cid:8)(cid:7)(cid:9)(cid:9) (cid:16) (cid:25)(cid:3)(cid:26) (cid:25)(cid:3)(cid:26): (cid:25)(cid:3)6(cid:26) 0(cid:7)(cid:12)(cid:13)(cid:11);(cid:5)(cid:13)(cid:15)(cid:20) 5 (cid:25)(cid:3) (cid:2) (cid:25)(cid:3) !(cid:27) (cid:25)(cid:3)!(cid:2) %(cid:12)5(cid:11)0(cid:7)(cid:12)(cid:13)(cid:11);(cid:5)(cid:13)(cid:15)(cid:20) 5(cid:26) (cid:26)(cid:3)<! 6(cid:3)(cid:25)(cid:25) 6(cid:3)(cid:25)! )(cid:10)(cid:10)(cid:15)(cid:11)0(cid:7)(cid:8)(cid:28)(cid:15)(cid:20) 0 (cid:25)(cid:3)<(cid:2) 9 (cid:2)(cid:3)(cid:2) 0(cid:7)(cid:12)(cid:13)(cid:11)(cid:29)(cid:8)(cid:28)(cid:17)(cid:7) (cid:2) (cid:25)= = := (cid:30)(cid:22)(cid:12)(cid:5)(cid:11)(cid:31) (cid:2)(cid:3) (cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:5)(cid:10)(cid:8)(cid:9)(cid:11)(cid:4)(cid:11)(cid:12)(cid:8)(cid:13)(cid:11)(cid:14)(cid:2)(cid:11)(cid:13)(cid:10)(cid:11)(cid:8)(cid:10)(cid:15)(cid:11)(cid:5)(cid:8)(cid:16)(cid:17)(cid:18)(cid:13)(cid:7)(cid:11)(cid:6)(cid:10)(cid:17)(cid:13)(cid:11)(cid:19)(cid:17)(cid:12)(cid:9)(cid:20)(cid:11)(cid:10)(cid:21)(cid:11)(cid:22)(cid:21)(cid:10)(cid:15)(cid:21)(cid:18)(cid:9)(cid:5)(cid:10)(cid:8)(cid:9)(cid:3)(cid:11)(cid:23)(cid:10)(cid:17)(cid:13)(cid:11)(cid:19)(cid:17)(cid:12)(cid:9)(cid:20)(cid:11)(cid:10)(cid:21)(cid:11)(cid:22)(cid:21)(cid:10)(cid:15)(cid:21)(cid:18)(cid:9)(cid:5)(cid:10)(cid:8)(cid:9)(cid:11)(cid:9)(cid:20)(cid:12)(cid:17)(cid:17)(cid:11)(cid:8)(cid:10)(cid:15)(cid:11)(cid:7)(cid:24)(cid:16)(cid:7)(cid:7)(cid:13)(cid:11)(cid:25)(cid:3)(cid:2)(cid:26)(cid:27)(cid:11)(cid:6)(cid:6)(cid:11)(cid:22)(cid:7)(cid:21)(cid:11)(cid:9)(cid:5)(cid:13)(cid:7)(cid:3) (cid:26)(cid:3) (cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:5)(cid:10)(cid:8)(cid:5)(cid:8)(cid:28)(cid:11)(cid:12)(cid:8)(cid:13)(cid:11)(cid:15)(cid:10)(cid:17)(cid:7)(cid:21)(cid:12)(cid:8)(cid:16)(cid:5)(cid:8)(cid:28)(cid:11)(cid:22)(cid:7)(cid:21)(cid:11)(cid:29)(cid:30)(cid:23)(cid:14)(cid:11)(cid:31)(cid:2) (cid:3)!(cid:23)(cid:3) "(cid:30)#$ "(cid:12)(cid:9)(cid:5)(cid:16)(cid:11)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:5)(cid:10)(cid:8)(cid:3)(cid:11)%(cid:20)(cid:7)(cid:10)(cid:21)(cid:7)(cid:15)(cid:5)(cid:16)(cid:12)(cid:17)(cid:17)&(cid:11)(cid:7)(cid:24)(cid:12)(cid:16)(cid:15)(cid:11)’(cid:12)(cid:17)(cid:18)(cid:7)(cid:11)(cid:9)(cid:20)(cid:10)((cid:8)(cid:11)((cid:5)(cid:15)(cid:20)(cid:10)(cid:18)(cid:15)(cid:11)(cid:15)(cid:10)(cid:17)(cid:7)(cid:21)(cid:12)(cid:8)(cid:16)(cid:7)(cid:9)(cid:3) (cid:23)(cid:5)(cid:16)(cid:21)(cid:10)(cid:16)(cid:20)(cid:5)(cid:22)%(cid:7)(cid:16)(cid:20)(cid:8)(cid:10)(cid:17)(cid:10)(cid:28)&(cid:4)(cid:21)(cid:12)((cid:5)(cid:8)(cid:28)#(cid:25) >(cid:2)6(cid:27)" © 2007 Microchip Technology Inc. DS22070A-page 27

MCP1824/MCP1824S (cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:10)(cid:8)(cid:17)(cid:18)(cid:12)(cid:10)(cid:13)(cid:19)(cid:5)(cid:8)(cid:20)(cid:21)(cid:6)(cid:19)(cid:11)(cid:13)(cid:11)(cid:12)(cid:22)(cid:21)(cid:8)(cid:23)(cid:17)(cid:20)(cid:26)(cid:8)(cid:27)(cid:15)(cid:17)(cid:20)(cid:3)(cid:28)(cid:2)(cid:29) (cid:30)(cid:22)(cid:12)(cid:5)(cid:31) )(cid:10)(cid:21)(cid:11)(cid:15)(cid:20)(cid:7)(cid:11)(cid:6)(cid:10)(cid:9)(cid:15)(cid:11)(cid:16)(cid:18)(cid:21)(cid:21)(cid:7)(cid:8)(cid:15)(cid:11)(cid:22)(cid:12)(cid:16)*(cid:12)(cid:28)(cid:7)(cid:11)(cid:13)(cid:21)(cid:12)((cid:5)(cid:8)(cid:28)(cid:9)+(cid:11)(cid:22)(cid:17)(cid:7)(cid:12)(cid:9)(cid:7)(cid:11)(cid:9)(cid:7)(cid:7)(cid:11)(cid:15)(cid:20)(cid:7)(cid:11)(cid:23)(cid:5)(cid:16)(cid:21)(cid:10)(cid:16)(cid:20)(cid:5)(cid:22)(cid:11),(cid:12)(cid:16)*(cid:12)(cid:28)(cid:5)(cid:8)(cid:28)(cid:11)(cid:30)(cid:22)(cid:7)(cid:16)(cid:5)(cid:19)(cid:5)(cid:16)(cid:12)(cid:15)(cid:5)(cid:10)(cid:8)(cid:11)(cid:17)(cid:10)(cid:16)(cid:12)(cid:15)(cid:7)(cid:13)(cid:11)(cid:12)(cid:15)(cid:11) (cid:20)(cid:15)(cid:15)(cid:22)$--((((cid:3)(cid:6)(cid:5)(cid:16)(cid:21)(cid:10)(cid:16)(cid:20)(cid:5)(cid:22)(cid:3)(cid:16)(cid:10)(cid:6)-(cid:22)(cid:12)(cid:16)*(cid:12)(cid:28)(cid:5)(cid:8)(cid:28) b N E E1 1 2 3 e e1 D A A2 c φ A1 L L1 .(cid:8)(cid:5)(cid:15)(cid:9) (cid:23)/00/(cid:23)(cid:14)%(cid:14)1(cid:30) (cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:5)(cid:10)(cid:8)(cid:11)0(cid:5)(cid:6)(cid:5)(cid:15)(cid:9) (cid:23)/2 23(cid:23) (cid:23)(cid:29)4 2(cid:18)(cid:6)5(cid:7)(cid:21)(cid:11)(cid:10)(cid:19)(cid:11),(cid:5)(cid:8)(cid:9) 2 ! 0(cid:7)(cid:12)(cid:13)(cid:11),(cid:5)(cid:15)(cid:16)(cid:20) (cid:7) (cid:25)(cid:3)<!(cid:11)"(cid:30)# 3(cid:18)(cid:15)(cid:9)(cid:5)(cid:13)(cid:7)(cid:11)0(cid:7)(cid:12)(cid:13)(cid:11),(cid:5)(cid:15)(cid:16)(cid:20) (cid:7)(cid:2) (cid:2)(cid:3)<(cid:25)(cid:11)"(cid:30)# 3’(cid:7)(cid:21)(cid:12)(cid:17)(cid:17)(cid:11)8(cid:7)(cid:5)(cid:28)(cid:20)(cid:15) (cid:29) (cid:25)(cid:3)<(cid:25) 9 (cid:2)(cid:3) ! (cid:23)(cid:10)(cid:17)(cid:13)(cid:7)(cid:13)(cid:11),(cid:12)(cid:16)*(cid:12)(cid:28)(cid:7)(cid:11)%(cid:20)(cid:5)(cid:16)*(cid:8)(cid:7)(cid:9)(cid:9) (cid:29)(cid:26) (cid:25)(cid:3):< 9 (cid:2)(cid:3)6(cid:25) (cid:30)(cid:15)(cid:12)(cid:8)(cid:13)(cid:10)(cid:19)(cid:19) (cid:29)(cid:2) (cid:25)(cid:3)(cid:25)(cid:25) 9 (cid:25)(cid:3)(cid:2)! 3’(cid:7)(cid:21)(cid:12)(cid:17)(cid:17)(cid:11);(cid:5)(cid:13)(cid:15)(cid:20) (cid:14) (cid:26)(cid:3)(cid:26)(cid:25) 9 6(cid:3)(cid:26)(cid:25) (cid:23)(cid:10)(cid:17)(cid:13)(cid:7)(cid:13)(cid:11),(cid:12)(cid:16)*(cid:12)(cid:28)(cid:7)(cid:11);(cid:5)(cid:13)(cid:15)(cid:20) (cid:14)(cid:2) (cid:2)(cid:3)6(cid:25) 9 (cid:2)(cid:3):(cid:25) 3’(cid:7)(cid:21)(cid:12)(cid:17)(cid:17)(cid:11)0(cid:7)(cid:8)(cid:28)(cid:15)(cid:20) (cid:4) (cid:26)(cid:3)(cid:27)(cid:25) 9 6(cid:3)(cid:2)(cid:25) )(cid:10)(cid:10)(cid:15)(cid:11)0(cid:7)(cid:8)(cid:28)(cid:15)(cid:20) 0 (cid:25)(cid:3)(cid:2)(cid:25) 9 (cid:25)(cid:3)7(cid:25) )(cid:10)(cid:10)(cid:15)(cid:22)(cid:21)(cid:5)(cid:8)(cid:15) 0(cid:2) (cid:25)(cid:3)6! 9 (cid:25)(cid:3):(cid:25) )(cid:10)(cid:10)(cid:15)(cid:11)(cid:29)(cid:8)(cid:28)(cid:17)(cid:7) (cid:2) (cid:25)= 9 6(cid:25)= 0(cid:7)(cid:12)(cid:13)(cid:11)%(cid:20)(cid:5)(cid:16)*(cid:8)(cid:7)(cid:9)(cid:9) (cid:16) (cid:25)(cid:3)(cid:25): 9 (cid:25)(cid:3)(cid:26)7 0(cid:7)(cid:12)(cid:13)(cid:11);(cid:5)(cid:13)(cid:15)(cid:20) 5 (cid:25)(cid:3)(cid:26)(cid:25) 9 (cid:25)(cid:3)!(cid:2) (cid:30)(cid:22)(cid:12)(cid:5)(cid:11)(cid:31) (cid:2)(cid:3) (cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:5)(cid:10)(cid:8)(cid:9)(cid:11)(cid:4)(cid:11)(cid:12)(cid:8)(cid:13)(cid:11)(cid:14)(cid:2)(cid:11)(cid:13)(cid:10)(cid:11)(cid:8)(cid:10)(cid:15)(cid:11)(cid:5)(cid:8)(cid:16)(cid:17)(cid:18)(cid:13)(cid:7)(cid:11)(cid:6)(cid:10)(cid:17)(cid:13)(cid:11)(cid:19)(cid:17)(cid:12)(cid:9)(cid:20)(cid:11)(cid:10)(cid:21)(cid:11)(cid:22)(cid:21)(cid:10)(cid:15)(cid:21)(cid:18)(cid:9)(cid:5)(cid:10)(cid:8)(cid:9)(cid:3)(cid:11)(cid:23)(cid:10)(cid:17)(cid:13)(cid:11)(cid:19)(cid:17)(cid:12)(cid:9)(cid:20)(cid:11)(cid:10)(cid:21)(cid:11)(cid:22)(cid:21)(cid:10)(cid:15)(cid:21)(cid:18)(cid:9)(cid:5)(cid:10)(cid:8)(cid:9)(cid:11)(cid:9)(cid:20)(cid:12)(cid:17)(cid:17)(cid:11)(cid:8)(cid:10)(cid:15)(cid:11)(cid:7)(cid:24)(cid:16)(cid:7)(cid:7)(cid:13)(cid:11)(cid:25)(cid:3)(cid:2)(cid:26)(cid:27)(cid:11)(cid:6)(cid:6)(cid:11)(cid:22)(cid:7)(cid:21)(cid:11)(cid:9)(cid:5)(cid:13)(cid:7)(cid:3) (cid:26)(cid:3) (cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:5)(cid:10)(cid:8)(cid:5)(cid:8)(cid:28)(cid:11)(cid:12)(cid:8)(cid:13)(cid:11)(cid:15)(cid:10)(cid:17)(cid:7)(cid:21)(cid:12)(cid:8)(cid:16)(cid:5)(cid:8)(cid:28)(cid:11)(cid:22)(cid:7)(cid:21)(cid:11)(cid:29)(cid:30)(cid:23)(cid:14)(cid:11)(cid:31)(cid:2) (cid:3)!(cid:23)(cid:3) "(cid:30)#$ "(cid:12)(cid:9)(cid:5)(cid:16)(cid:11)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:5)(cid:10)(cid:8)(cid:3)(cid:11)%(cid:20)(cid:7)(cid:10)(cid:21)(cid:7)(cid:15)(cid:5)(cid:16)(cid:12)(cid:17)(cid:17)&(cid:11)(cid:7)(cid:24)(cid:12)(cid:16)(cid:15)(cid:11)’(cid:12)(cid:17)(cid:18)(cid:7)(cid:11)(cid:9)(cid:20)(cid:10)((cid:8)(cid:11)((cid:5)(cid:15)(cid:20)(cid:10)(cid:18)(cid:15)(cid:11)(cid:15)(cid:10)(cid:17)(cid:7)(cid:21)(cid:12)(cid:8)(cid:16)(cid:7)(cid:9)(cid:3) (cid:23)(cid:5)(cid:16)(cid:21)(cid:10)(cid:16)(cid:20)(cid:5)(cid:22)%(cid:7)(cid:16)(cid:20)(cid:8)(cid:10)(cid:17)(cid:10)(cid:28)&(cid:4)(cid:21)(cid:12)((cid:5)(cid:8)(cid:28)#(cid:25) >(cid:25)<(cid:2)" © DS22070A-page 28 2007 Microchip Technology Inc.

MCP1824/MCP1824S APPENDIX A: REVISION HISTORY Revision A (November 2007) (cid:129) Original Release of this Document. © 2007 Microchip Technology Inc. DS22070A-page 29

MCP1824/MCP1824S NOTES: © DS22070A-page 30 2007 Microchip Technology Inc.

MCP1824/MCP1824S PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. XX X X X/ XX Examples: a) MCP1824-0802E/XX: 0.8V LDO Regulator Device Output Feature Tolerance Temp. Package b) MCP1824-1002E/XX: 1.0V LDO Regulator Voltage Code c) MCP1824-1202E/XX: 1.2V LDO Regulator d) MCP1824-1802E/XX: 1.8V LDO Regulator Device: MCP1824: 300mA Low Dropout Regulator e) MCP1824-2502E/XX: 2.5V LDO Regulator MCP1824T: 300mA Low Dropout Regulator f) MCP1824-3002E/XX: 3.0V LDO Regulator Tape and Reel g) MCP1824-3302E/XX: 3.3V LDO Regulator MCP1824S: 300mA Low Dropout Regulator h) MCP1824-5002E/XX: 5.0V LDO Regulator MCP1824ST:300mA Low Dropout Regulator Tape and Reel i) MCP1824-ADJE/XX: ADJ LDO Regulator a) MCP1824S-0802E/XX:0.8V LDO Regulator Output Voltage *: 08 = 0.8V “Standard” 12 = 1.2V “Standard” b) MCP1824S-1002E/XX:1.0V LDO Regulator 18 = 1.8V “Standard” c) MCP1824S-1202E/XX:1.2V LDO Regulator 25 = 2.5V “Standard” d) MCP1824S-1802E/XX:1.8V LDO Regulator 30 = 3.0V “Standard” 33 = 3.3V “Standard” e) MCP1824S-2502E/XX:2.5V LDO Regulator 50 = 5.0V “Standard” f) MCP1824S-2502E/XX:3.0V LDO Regulator ADJ= Adjustable Output Voltage ** (MCP1824 Only) g) MCP1824S-3302E/XX:3.3V LDO Regulator *Contact factory for other output voltage options h) MCP1824S-5002E/XX:5.0V LDO Regulator ** When ADJ is used, the “extra feature code” and “tolerance” columns do not apply. Refer to examples. Extra Feature Code: 0 = Fixed XX = DB for 3LD SOT-223 package = DC for 5LD SOT-223 package = OT for 5LD SOT-23 package Tolerance: 2 = 2.5% (Standard) Temperature: E = -40°C to +125°C Package Type: DB = Plastic Small Transistor Outline, SOT-223, 3-lead DC = Plastic Small Transistor Outline, SOT-223, 5-lead OT = Plastic Small Transistor Outline, SOT-23, 5-lead Note: ADJ (Adjustable) only available in 5-lead version. © 2007 Microchip Technology Inc. DS22070A-page 31

MCP1824/MCP1824S NOTES: © DS22070A-page 32 2007 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: (cid:129) Microchip products meet the specification contained in their particular Microchip Data Sheet. (cid:129) Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. (cid:129) There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. (cid:129) Microchip is willing to work with the customer who is concerned about the integrity of their code. (cid:129) Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, Accuron, and may be superseded by updates. It is your responsibility to dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC, ensure that your application meets with your specifications. PICmicro, PICSTART, PROMATE, rfPIC and SmartShunt are MICROCHIP MAKES NO REPRESENTATIONS OR registered trademarks of Microchip Technology Incorporated WARRANTIES OF ANY KIND WHETHER EXPRESS OR in the U.S.A. and other countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, AmpLab, FilterLab, Linear Active Thermistor, Migratable INCLUDING BUT NOT LIMITED TO ITS CONDITION, Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The QUALITY, PERFORMANCE, MERCHANTABILITY OR Embedded Control Solutions Company are registered FITNESS FOR PURPOSE. Microchip disclaims all liability trademarks of Microchip Technology Incorporated in the arising from this information and its use. Use of Microchip U.S.A. devices in life support and/or safety applications is entirely at Analog-for-the-Digital Age, Application Maestro, CodeGuard, the buyer’s risk, and the buyer agrees to defend, indemnify and dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, hold harmless Microchip from any and all damages, claims, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, suits, or expenses resulting from such use. No licenses are In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, conveyed, implicitly or otherwise, under any Microchip MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit, intellectual property rights. PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2007, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2007 Microchip Technology Inc. DS22070A-page 33

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: MCP1824ST-0802E/DB MCP1824ST-1802E/DB MCP1824ST-5002E/DB MCP1824ST-1202E/DB MCP1824ST- 3002E/DB MCP1824ST-3302E/DB MCP1824ST-ADJE/DB MCP1824ST-2502E/DB MCP1824T-0802E/DC MCP1824T-0802E/OT MCP1824T-1202E/DC MCP1824T-1202E/OT MCP1824T-1802E/DC MCP1824T-1802E/OT MCP1824T-2502E/DC MCP1824T-2502E/OT MCP1824T-3002E/DC MCP1824T-3002E/OT MCP1824T-3302E/DC MCP1824T-3302E/OT MCP1824T-5002E/DC MCP1824T-5002E/OT MCP1824T-ADJE/DC MCP1824T-ADJE/OT