MCP1790/MCP1791 70 mA, High Voltage Regulator Features General Description • 48V (43.5V ±10%) load dump protected for <500ms The MCP1790/MCP1791 regulator provides up to 70mA with a 30second repetition rate (FORD Test Pulse of current. The input operating voltage range is specified G Loaded) from 6.0V to 30V continuous, 48V absolute max, making • Wide steady state supply voltage, 6.0V - 30.0V it ideal for automotive and commercial 12/24VDC systems. • Extended Junction Temperature Range: -40 to +125°C The MCP1790/MCP1791 has a tight tolerance output • Fixed output voltages: 3.0V, 3.3V, 5.0V voltage load regulation of ±0.2% (typical) and a very good line regulation at ±0.0002%/V (typical). The • Low quiescent current: 70µA typical regulator output is stable with ceramic, tantalum and • Low shutdown quiescent current: 10µA typical electrolytic capacitors. The MCP1790/MCP1791 • Output Voltage Tolerances of ±2.5% over the regulator incorporates both thermal and short circuit temperature range protection. • Maximum output current of 70mA @ +125°C The MCP1790 is the 3-pin version of the MCP1790/ Junction Temperature MCP1791 family. The MCP1791 is the 5-pin version • Maximum continuous input voltage of 30V and incorporates a Shutdown input signal and a Power • Internal thermal overload protection, +157°C Good output signal. (typical) Junction Temperature The regulator is specifically designed to operate in the • Internal short circuit current limit, 120mA (typical) automotive environment and will survive +48V (43.5V for +5V option ±10%) load dump transients and double-battery jumps. • Short Circuit Current Foldback The device is designed to meet the stringent quiescent • Shutdown Input option (MCP1791) current requirements of the automotive industry. The device is also designed for the commercial low voltage • Power Good Output option (MCP1791) fire alarm/detector systems, which use 24 VDC to • High PSRR, -90dB@100Hz (typical) supply the required alarms throughout buildings. The • Stable with 1µF to 1000µF Tantalum and low ground current, 110µA (typ.), of the CMOS device Electrolytic Capacitors will provide a power cost savings to the end users over • Stable with 4.7µF to 1000µF Ceramic Capacitors similar bipolar devices. Typical buildings using hundreds of 24V powered fire and smoke detectors can Applications see substantial savings on energy consumption and wiring gage reduction compared to bipolar regulators. • Low Voltage A/C powered (24VAC) Fire Alarms, CO Sensors, HVAC Controls The MCP1790 device will be offered in the 3-pin 2 DD-PAK, and SOT-223 packages. • Automotive Electronics • Automotive Accessory Power Adapters The MCP1791 device will be offered in the 5-pin DD-PAK, and SOT-223 packages. • Electronic Thermostat Controls • Microcontroller power The MCP1790/MCP1791 will have a junction temperature operating range of -40°C to +125°C. © 2010 Microchip Technology Inc. DS22075B-page 1

MCP1790/MCP1791 Package Types MCP1790 MCP1791 DDPAK-3 SOT-223-3 DDPAK-5 SOT-223-5 4 6 1 2 3 1 2 3 1 2 3 4 5 1 2 3 4 5 Pin Pin 1 VIN 1 SHDN 2 GND (TAB) 2 V IN 3 V OUT 3 GND (TAB) 4 GND (TAB) 4 V OUT 5 PWRGD 6 GND (TAB) DS22075B-page 2 © 2010 Microchip Technology Inc.

MCP1790/MCP1791 TYPICAL APPLICATION PWRGD MCP1791 R 1 On 100kΩ Off SHDN 1 VIN = 6V to 30V VIN VOUT VOUT = 5.0V @ 70mA GND C 1 C 4.7µF 2 1µF Tantalum MCP1790 1 VIN = 8.0V to 16V VIN VOUT VOUT = 3.3V @ 70mA 5Ω C 1 C 1.0µF 2 1.0µF Tantalum GND © 2010 Microchip Technology Inc. DS22075B-page 3

MCP1790/MCP1791 1.0 ELECTRICAL † Notice: Stresses above those listed under “Maximum Rat- ings” may cause permanent damage to the device. This is a CHARACTERISTICS stress rating only and functional operation of the device at those or any other conditions above those indicated in the Absolute Maximum Ratings † operational listings of this specification is not implied. Expo- sure to maximum rating conditions for extended periods may Input Voltage, VIN........................................................+48.0V affect device reliability. VIN, PWRGD, SHDN.....................(GND-0.3V) to (VIN+0.3V) V ....................................................(GND-0.3V) to (+5.5V) OUT Internal Power Dissipation............Internally-Limited (Note4) Output Short Circuit Current..................................Continuous Storage temperature.....................................-55°C to +150°C Maximum Junction Temperature.....................165°C (Note7) Operating Junction Temperature...................-40°C to +125°C ESD protection on all pins........≥ 6kV HBM and ≥ 400V MM AC/DC CHARACTERISTICS Electrical Specifications: Unless otherwise noted, V = V + V (Note1), I = 1mA, IN OUT(MAX) DROPOUT(MAX), OUT C = 4.7µF (X7R Ceramic), C =4.7µF (X7R Ceramic), T = +25°C, SHDN > 2.4V. OUT IN A Boldface type applies for junction temperatures, T (Note5) of -40°C to +125°C. J Parameters Symbol Min Typ Max Units Conditions Input Operating Voltage VIN 6.0 — 30.0 V +48VDC Load Dump Peak < 500ms Input Quiescent Current I — 70 130 µA I = 0mA q L Input Quiescent Current for SHDN I — 10 25 µA SHDN = GND SHDN Mode Ground Current IGND — 110 210 µA IL = 70mA Maximum Output Current I 70 — — mA OUT Line Regulation ΔV / — ±0.0002 ±0.05 %/V 6.0V < V < 30V OUT IN (V XΔV ) OUT IN Load Regulation ΔV /V -0.45 ±0.2 0.45 % I = 1mA to 70mA OUT OUT OUT (Note3) Output Peak Short Circuit Current I — V /10 — A R <0.1Ω, OUT_SC R LOAD Peak Current Output Voltage Regulation V V -2.5% V V +2.5% V — OUT R R R V Temperature Coefficient TCV — 65 — ppm/°C Note9 OUT OUT Input Voltage to Turn On Output V — 5.5 6.0 V Rising V ON IN Note 1: The minimum V , V must meet two conditions: V ≥ 6.0V and V ≥ V + V IN IN(MIN) IN IN OUT(MAX) DROPOUT(MAX). 2: V is the nominal regulator output voltage. R 3: Load regulation is measured at a constant junction temperature using low duty cycle pulse testing. Load regulation is tested over a load range from 1 mA to the maximum specified output current. 4: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air. (i.e., T , T , θ ). Exceeding the maximum allowable power A J JA dissipation will cause the device operating junction temperature to exceed the maximum 165°C rating. Sustained junction temperatures above 165°C can impact the device reliability. 5: The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the desired Junction temperature. The test time is small enough such that the rise in the Junction temperature over the ambient temperature is not significant. 6: Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its nominal value that was measured with an input voltage of V = V + V . IN R DROPOUT(MAX) 7: Sustained junction temperatures above 165°C can impact the device reliability. 8: The Short Circuit Recovery Time test is done by placing the device into a short circuit condition and then removing the short circuit condition before the device die temperature reaches 125 °C. If the device goes into thermal shutdown, then the Short Circuit Recovery Time will depend upon the thermal dissipation properties of the package and circuit board. 9: TCV = (V - V ) *10^6/(V * ΔTemperature), V = highest voltage measured over the temperature OUT OUT-HIGH OUT-LOW R OUT-HIGH range. V = lowest voltage measured over the temperature range. OUT-LOW DS22075B-page 4 © 2010 Microchip Technology Inc.

MCP1790/MCP1791 AC/DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise noted, V = V + V (Note1), I = 1mA, IN OUT(MAX) DROPOUT(MAX), OUT C = 4.7µF (X7R Ceramic), C =4.7µF (X7R Ceramic), T = +25°C, SHDN > 2.4V. OUT IN A Boldface type applies for junction temperatures, T (Note5) of -40°C to +125°C. J Parameters Symbol Min Typ Max Units Conditions Short Circuit Foldback Voltage Corner V — 4.2 — V V = 5.0V FOLDBACK R Falling V R <0.1Ω OUT, LOAD — 3.0 — V V = 3.3V R Falling V R <0.1Ω OUT, LOAD — 2.7 — V V = 3.0V R Falling V R <0.1Ω OUT, LOAD Short Circuit Foldback Current — 105 — mA V ~= 0V, OUT R <0.1Ω, LOAD V = 5.0V (Note2) R — 99 — mA V = 3.3V (Note2) R — 99 — mA V = 3.0V (Note2) R Startup Voltage Overshoot V — 0.10 — % V V = 0V to 6.0V OVER OUT IN Dropout Voltage V — 700 1300 mV I = 70mA, (Note6) DROPOUT OUT Dropout Current I — 130 — µA V = 5.0V, V = 4.500V DO R IN IOUT = 0 mA — 75 — µA VR = 3.3V, VIN = 4.500V — 75 — µA V = 3.0V, V = 4.500V R IN Shutdown Input Logic High Input V 2.4 — V V — SHDN-HIGH IN(MAX) Logic Low Input V 0 — 0.8 V — SHDN-LOW Shutdown Input Leakage Current SHDN — 0.100 0.500 µA SHDN = GND ILK — 3.0 5.0 SHDN = 6V Power Good Characteristics PWRGD Input Voltage Operating V 2.8 — — V — PWRGD_VIN Range PWRGD Threshold Voltage V 88 90 92 %V Falling Edge of V PWRGD_TH OUT OUT (Referenced to V ) OUT PWRGD Threshold Hysteresis V 1.0 2.0 3.0 %V Rising Edge of V PWRGD_HYS OUT OUT PWRGD Output Voltage LOW V — 0.2 0.4 V I = 5.0mA, PWRGD_L PWRGDSINK V = 0V OUT PWRGD Output Sink Current I 5.0 — — mA V <= 0.4V PWRGD_L PWRGD PWRGD Leakage I _ — 1.0 — nA V = V = 6.0V PWRGD LK PWRGD IN PWRGD Time Delay T — 30 — µs Rising Edge PG Note 1: The minimum V , V must meet two conditions: V ≥ 6.0V and V ≥ V + V IN IN(MIN) IN IN OUT(MAX) DROPOUT(MAX). 2: V is the nominal regulator output voltage. R 3: Load regulation is measured at a constant junction temperature using low duty cycle pulse testing. Load regulation is tested over a load range from 1 mA to the maximum specified output current. 4: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air. (i.e., T , T , θ ). Exceeding the maximum allowable power A J JA dissipation will cause the device operating junction temperature to exceed the maximum 165°C rating. Sustained junction temperatures above 165°C can impact the device reliability. 5: The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the desired Junction temperature. The test time is small enough such that the rise in the Junction temperature over the ambient temperature is not significant. 6: Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its nominal value that was measured with an input voltage of V = V + V . IN R DROPOUT(MAX) 7: Sustained junction temperatures above 165°C can impact the device reliability. 8: The Short Circuit Recovery Time test is done by placing the device into a short circuit condition and then removing the short circuit condition before the device die temperature reaches 125 °C. If the device goes into thermal shutdown, then the Short Circuit Recovery Time will depend upon the thermal dissipation properties of the package and circuit board. 9: TCV = (V - V ) *10^6/(V * ΔTemperature), V = highest voltage measured over the temperature OUT OUT-HIGH OUT-LOW R OUT-HIGH range. V = lowest voltage measured over the temperature range. OUT-LOW © 2010 Microchip Technology Inc. DS22075B-page 5

MCP1790/MCP1791 AC/DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise noted, V = V + V (Note1), I = 1mA, IN OUT(MAX) DROPOUT(MAX), OUT C = 4.7µF (X7R Ceramic), C =4.7µF (X7R Ceramic), T = +25°C, SHDN > 2.4V. OUT IN A Boldface type applies for junction temperatures, T (Note5) of -40°C to +125°C. J Parameters Symbol Min Typ Max Units Conditions Detect Threshold to PWRGD Active TV — 235 — µs V = V + DET-PWRG OUT PWRGD_TH Time Delay 100mV to V - D PWRGD_TH 100mV AC Performance Output Delay from SHDN T — 200 — µs SHDN = GND to V OR IN, V = GND to 95% V OUT R, C = 1.0µF OUT PWRGD Delay from SHDN T — 400 — ns SHDN = V to GND SHDN_PG IN , C = 1.0µF OUT Output Noise e — 1.2 — (µV/√Hz) I = 50mA, f = 1kHz N OUT Power Supply Ripple Rejection Ratio PSRR dB VIN = 7.0V, CIN = 0µF, I = 10mA, OUT V = 400mVpp INAC — 90 — f = 100Hz — 75 — f = 1kHz, V = 5.0V R — 80 — f = 1kHz, V = < 5.0V R Thermal Shutdown Temperature T — 157 — °C Rising Temperature SD Thermal Shutdown Hysteresis ΔT — 20 — °C Falling Temperature SD Short Circuit Recovery Time t — 0 — ms (Note8) THERM Note 1: The minimum V , V must meet two conditions: V ≥ 6.0V and V ≥ V + V IN IN(MIN) IN IN OUT(MAX) DROPOUT(MAX). 2: V is the nominal regulator output voltage. R 3: Load regulation is measured at a constant junction temperature using low duty cycle pulse testing. Load regulation is tested over a load range from 1 mA to the maximum specified output current. 4: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air. (i.e., T , T , θ ). Exceeding the maximum allowable power A J JA dissipation will cause the device operating junction temperature to exceed the maximum 165°C rating. Sustained junction temperatures above 165°C can impact the device reliability. 5: The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the desired Junction temperature. The test time is small enough such that the rise in the Junction temperature over the ambient temperature is not significant. 6: Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its nominal value that was measured with an input voltage of V = V + V . IN R DROPOUT(MAX) 7: Sustained junction temperatures above 165°C can impact the device reliability. 8: The Short Circuit Recovery Time test is done by placing the device into a short circuit condition and then removing the short circuit condition before the device die temperature reaches 125 °C. If the device goes into thermal shutdown, then the Short Circuit Recovery Time will depend upon the thermal dissipation properties of the package and circuit board. 9: TCV = (V - V ) *10^6/(V * ΔTemperature), V = highest voltage measured over the temperature OUT OUT-HIGH OUT-LOW R OUT-HIGH range. V = lowest voltage measured over the temperature range. OUT-LOW DS22075B-page 6 © 2010 Microchip Technology Inc.

MCP1790/MCP1791 TEMPERATURE SPECIFICATIONS Parameters Symbol Min Typ Max Units Conditions Temperature Ranges Specified Temperature Range T -40 — +125 °C — J Operating Temperature Range T -40 — +125 °C — J Storage Temperature Range T -55 — +150 °C — A Package Thermal Resistances Thermal Resistance, 3LD DDPAK θ — 31.4 — °C/W EIA/JEDEC JESD51-751-7 JA θ 3 4 Layer Board JC Thermal Resistance, 3LD SOT-223 θ — 62 — °C/W EIA/JEDEC JESD51-751-7 JA θ 15 4 Layer Board JC Thermal Resistance, 5LD DDPAK θ — 31.4 — °C/W EIA/JEDEC JESD51-751-7 JA θ 3 4 Layer Board JC Thermal Resistance, 5LD SOT-223 θ — 62 — °C/W EIA/JEDEC JESD51-751-7 JA θ 15 4 Layer Board JC © 2010 Microchip Technology Inc. DS22075B-page 7

MCP1790/MCP1791 2.0 TYPICAL PERFORMANCE CHARACTERISTICS Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, C = 4.7uF Ceramic (X7R), C = 10.0µF Ceramic (X7R), I = 1mA, Temperature = +25°C, OUT IN OUT V = 6.0V, R = 10kΩ To V , V = V and device is MCP1790. IN PWRGD_PULLUP OUT SHDN IN, Note: Junction Temperature (TJ) is approximated by soaking the device under test to an ambient temperature equal to the desired junction temperature. The test time is small enough such that the rise in Junction Temperature over the Ambient temperature is not significant. 50 120.00 µs) 40 VIOOUUTT = = 0 5 µ.0AV µA)100.00 VIOIUNT = = 6 0VµA VOUT = 3.0V e Delay ( 30 VIN = 6V VIN = 10V,15V,25V,30V Current ( 6800..0000 VOUT = 3.3V Tim 20 ent 40.00 VOUT = 5.0V D sc G 10 e R ui 20.00 W Q P 0 0.00 -45 -20 5 30 55 80 105 130 -45 -20 5 30 55 80 105 130 Temperature (°C) Junction Temperature (°C) FIGURE 2-1: Power Good Time Delay vs. FIGURE 2-4: Quiescent Current vs. Temperature (MCP1791). Junction Temperature. 140 140 urrent (µA)11028000 +++1293500°°°CCC VIOOUUTT = = 0 3 µ.3AV ent (µA)11028000 VOVUOTU =T =5 .30.V3V VOUT = 3.0V nt C 60 -450°°CC Curr 60 sce 40 ND 40 e G ui 20 20 Q 0 0 0 5 10 15 20 25 30 35 0 10 20 30 40 50 60 70 Input Voltage (V) Load Current (mA) FIGURE 2-2: Quiescent Current vs. Input FIGURE 2-5: Ground Current vs. Load Voltage. Current. 140 28 µA)120 VIOOUUTT = = 0 5 µ.0AV 24 VVRSHEGDN = = 3 0.0VV nt (100 +130°C 20 cent Curre 468000 ++-2945005°°°°CCCC I (µA)SHDN11268 VIN = 10V, 30V s uie 20 4 VIN = 6.0V Q 0 0 0 5 10 15 20 25 30 35 -45 -20 5 30 55 80 105 130 Input Voltage (V) Temperature (°C) FIGURE 2-3: Quiescent Current vs. Input FIGURE 2-6: I vs Temperature. SHDN Voltage. DS22075B-page 8 © 2010 Microchip Technology Inc.

MCP1790/MCP1791 Note: Unless otherwise indicated, C = 4.7uF Ceramic (X7R), C = 10.0µF Ceramic (X7R), I = 1mA, Temperature = +25°C, OUT IN OUT V = 6.0V, R = 10kΩ To V , V = V and device is MCP1790. IN PWRGD_PULLUP OUT SHDN IN, 0.006 5.04 VOUT = 3.3V 5.03 VOUT = 5.0V %/V) 00..000024 10 mA 0 mA VIN = 6V to 30V e (V) 55..0012 VIN = 6.3V n ( ag 5.00 atio 0.000 Volt 4.99 gul -0.002 ut 4.98 e Re -0.004 70 mA Outp 44..9967 Lin 4.95 --4455°°CC 00°°CC ++2255°°CC ++9900°°CC ++113300°°CC -0.006 4.94 -45 -20 5 30 55 80 105 130 0 10 20 30 40 50 60 70 Temperature (°C) Load Current (mA) FIGURE 2-7: Line Regulation vs. FIGURE 2-10: Output Voltage vs. Load Temperature. Current. 0.006 1.0 VOUT = 5.0V 0.9 VOUT = 5.0V V) 0.004 VIN = 6V to 30V V)0.8 ation (%/ 00..000002 0 mA Voltage (000...567 +90°C+130°C Line Regul --00..000042 30 mA 70 mA Dropout 0000....1234 -45°C 0°C +25°C -0.006 0.0 -45 -20 5 30 55 80 105 130 0 10 20 30 40 50 60 70 Temperature (°C) Load Current (mA) FIGURE 2-8: Line Regulation vs. FIGURE 2-11: Dropout Voltage vs. Load Temperature. Current. 0.00 1.0 ILOAD = 1 mA to 70 mA 0.9 VOUT = 5.0V n (%) --00..1005 VREG=5.0V age (V)000...678 70 mA ad Regulatio ---000...221505 VREG=3.0VVREG=3.3V Dropout Volt0000....2345 513000 mmmAAA 1 mA o 0.1 L -0.30 0.0 -45 -20 5 30 55 80 105 130 -45 -20 5 30 55 80 105 130 Temperature (°C) Temperature (°C) FIGURE 2-9: Load Regulation vs. FIGURE 2-12: Dropout Voltage vs. Temperature. Temperature. © 2010 Microchip Technology Inc. DS22075B-page 9

MCP1790/MCP1791 Note: Unless otherwise indicated, C = 4.7uF Ceramic (X7R), C = 10.0µF Ceramic (X7R), I = 1mA, Temperature = +25°C, OUT IN OUT V = 6.0V, R = 10kΩ To V , V = V and device is MCP1790. IN PWRGD_PULLUP OUT SHDN IN, 130 -20 mA)125 ROUT < 0.1Ω -30 VR=5.0V Circuit Current (111112050 VOUT = 5.0V VOUT = 3.3V PSRR (dB) ------987654000000 VVCIOIIIUNNNT=A==C701 . =0μ0 V 4Fm00A mV p-p ort 105 VOUT = 3.0V -100 h S100 -110 -120 6 10 14 18 22 26 30 0.01 0.1 1 10 100 1000 Input Voltage (V) Frequency (kHz) FIGURE 2-13: Short Circuit Current vs FIGURE 2-16: Power Supply Ripple Input Voltage. Rejection vs. Frequency. 10.00 VR=5.0V IOUT=50mA 1.00 z) (cid:2)H VR=3.3V μV/ 0.10 e ( s oi N 0.01 0.00 0.01 0.1 1 10 100 1000 Frequency (kHz) FIGURE 2-14: Output Noise Voltage FIGURE 2-17: Startup from V IN Density vs. Frequency. (MCP1791). -20 -30 VR=3.3V VIN=7.0V -40 VINAC = 400 mV p-p dB) --6500 CIOIUNT==01 μ0 FmA R ( R -70 S P -80 -90 -100 -110 0.01 0.1 1 10 100 1000 Frequency (kHz) FIGURE 2-15: Power Supply Ripple FIGURE 2-18: Startup from Shutdown Rejection vs. Frequency. (MCP1791). DS22075B-page 10 © 2010 Microchip Technology Inc.

MCP1790/MCP1791 Note: Unless otherwise indicated, C = 4.7uF Ceramic (X7R), C = 10.0µF Ceramic (X7R), I = 1mA, Temperature = +25°C, OUT IN OUT V = 6.0V, R = 10kΩ To V , V = V and device is MCP1790. IN PWRGD_PULLUP OUT SHDN IN, FIGURE 2-19: Dynamic Line Response. FIGURE 2-22: Dynamic Load Response. 5.0 4.5 V)4.0 VOUT = 3.3V e (3.5 ag3.0 olt2.5 ut V2.0 VOUT = 3.0V p1.5 Out1.0 0.5 0.0 0 20 40 60 80 100 120 140 Output Current (mA) FIGURE 2-20: Dynamic Line Response. FIGURE 2-23: Short Circuit Response. 7 VOUT = 5.0V V)6 VIN = 6.3V e (5 g a4 olt V3 ut utp2 O 1 0 0 20 40 60 80 100 120 140 Output Current (mA) FIGURE 2-21: Dynamic Load Response. FIGURE 2-24: Short Circuit Response. © 2010 Microchip Technology Inc. DS22075B-page 11

MCP1790/MCP1791 Note: Unless otherwise indicated, C = 4.7uF Ceramic (X7R), C = 10.0µF Ceramic (X7R), I = 1mA, Temperature = +25°C, OUT IN OUT V = 6.0V, R = 10kΩ To V , V = V and device is MCP1790. IN PWRGD_PULLUP OUT SHDN IN, 90 µA)80 IOUT = 1 mA nt (70 e Curr5600 VOUT = 5.0V d un40 VOUT = 3.3V Gro30 p 20 u art10 St 0 0 1 2 3 4 5 6 7 Input Voltage (V) FIGURE 2-25: Startup Ground Current. DS22075B-page 12 © 2010 Microchip Technology Inc.

MCP1790/MCP1791 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table3-1 and Table3-2. TABLE 3-1: MCP1790 PIN FUNCTION TABLE Pin No. Pin No. Symbol Function SOT-223-3 DDPAK-3 1 1 V Unregulated Supply Voltage IN 2,Tab 2,Tab GND Ground Terminal 3 3 V Regulated Output Voltage OUT TABLE 3-2: MCP1791 PIN FUNCTION TABLE Pin No. Pin No. Symbol Function SOT-223-5 DDPAK-5 1 1 SHDN Shutdown Input 2 2 V Unregulated Supply Voltage IN 3 3 GND Ground Terminal 4 4 V Regulated Output Voltage OUT 5 5 PWRGD Power Good Open-Drain Output Tab Tab — Connected to Ground — — N/C No connection 3.1 Input Voltage Supply (V ) 3.4 Shutdown (SHDN) IN Connect the unregulated or regulated input voltage The SHDN pin is an active-low input signal that turns source to V . If the input voltage source is located the regulator output voltage on and off. When the IN several inches away from the regulator or the input SHDN input is at a logic-high level, the regulator output source is a battery, it is recommended that an input voltage is enabled. When the SHDN input is pulled to a capacitor is used. A typical input capacitance value of logic-low level, the regulator output voltage is disabled. 1µF to 10µF should be sufficient for most applications. When the SHDN input is pulled low, the PWRGD output The type of capacitor used can be ceramic, tantalum or signal also goes low and the regulator enters a low aluminum electrolytic. The low ESR characteristics of quiescent current shutdown state where the typical qui- the ceramic will yield better noise and PSRR escent current is 10µA. The SHDN pin is bonded to V IN performance at high-frequency. in the 3-pin versions of the regulator. See Table4-1. 3.2 Ground (GND) 3.5 Power Good Output (PWRGD) Tie GND to the negative side of the output and the The PWRGD pin is an open-drain output signal that is negative side of the input capacitor. Only the regulator used to indicate when the regulator output voltage is bias current flows out of this pin; there is no high within 90% (typically) of its nominal regulation value. current. The regulator output regulation is referenced to The PWRGD threshold has a typical hysteresis value this pin. Minimize voltage drops between this pin and of 2%. The typical PWRGD delay time due to V OUT the negative side of the load. rising above 90% +3% (maximum hysteresis) is 30µs. The typical PWRGD delay time due to V falling OUT 3.3 Regulated Output Voltage (V ) below 90% is 235µs. These delay times are internally OUT fixed. The V pin is the regulated output voltage of the IN regulator. A minimum output capacitance of 1.0µF 3.6 Exposed Pad (EP) tantalum, 1.0µF electrolytic, or 4.7µF ceramic is required for stability. The MCP1790 is stable with The DDPAK package has an exposed tab on the ceramic, tantalum, and electrolytic capacitors. See package. A heat sink may be mounted to the tab to aid Section4.7 “Output Capacitor” for output capacitor in the removal of heat from the package during selection guidance. operation. The exposed tab or pad of all of the available packages is at the ground potential of the regulator. © 2010 Microchip Technology Inc. DS22075B-page 13

MCP1790/MCP1791 4.0 DEVICE OVERVIEW 4.4 External Protection The MCP1790/MCP1791 are high input voltage 4.4.1 TRANSIENT VOLTAGE regulators capable of providing up to 70mA of current PROTECTION (LOAD DUMP) at output voltages up to 5.0V. The devices have an input voltage operating range from 6.0V to 30V, 48V The regulator is capable of withstanding a 48V absolute max. The MCP1790 devices are 3-pin devices (43.5V±10) load dump transient for a duration of consisting of V , V and GND. The MCP1791 500ms and a repetition rate of 30 seconds IN OUT devices have 5 or more pins which add Shutdown and (ES-XW7T-1A278-AC, Ford Motor Company, Test Power-Good functions to the MCP1790 device. Pulse G Loaded). While not necessary, good design practice dictates 4.1 Startup adding an external transient suppressor, between VBB and ground, with a low value resistor in series with the In the start phase, the device must see at least 6.0V to battery supply and the V pin, to limit currents and volt- IN initiate operation during power up. In the Power-down ages due to electrical transients. Because of the regu- mode, the VIN monitor will be turned off. lator startup current, the resistor value should be less than (V -6V)/200mA. For a 12V battery voltage, BAT 4.2 Thermal Shutdown the resistor value should be less than 30 ohms. The regulator has a thermal shutdown. If the thermal 4.4.2 REVERSE BATTERY PROTECTION protection circuit detects an over temperature condition, typically 157°C junction temperature, the An external reverse battery blocking diode may be regulator will shut down. The device will recover from used to provide polarity protection. the thermal shutdown when the junction temperature drops to 137°C (typical). 4.3 Regulator Output Voltage The MCP1790/MCP1791 regulators are available in fixed output voltage configurations. The standard output voltages are 3.0V, 3.3V, and 5.0V. VIN T1 T2 Soft Start e - onitoringmperatur RVefoeltraegnece en Error Amplifier T1 MTe T2 Temp + Sensor Short Circuit VOUT Logical Block Protection en 510k VIN 490k Delay SHDN Monitoring VOUT Delay PWRGD Monitoring VIN GND FIGURE 4-1: MCP1790/MCP1791 Block Diagram. DS22075B-page 14 © 2010 Microchip Technology Inc.

MCP1790/MCP1791 4.5 Shutdown (SHDN) 4.6 Low Voltage Shutdown The MCP1791 has a Shutdown (SHDN) input signal The MCP1790/MCP1791 incorporates a Low Voltage that enables or disables the regulator output voltage. Shutdown circuit that turns off the output of the When the SHDN input signal is greater than 2.40V, the regulator whenever the input voltage, V , is below the IN regulator output voltage is enabled. Note that the specified turn off voltage, V . When the input voltage OFF regulator output may still be disabled by the (V ) drops below the differential needed to provide B undervoltage lockout incorporated within the V stable regulation, the output voltage (V ) shall track IN REG circuitry. the input down to approximately +4.00V. The regulator will turn off the output at this point. The value of the SHDN signal to put the regulator into Shutdown mode is ≤ 0.8V. The SHDN pin is pulled low The output will turn on when V rises above the V IN ON by an internal resistor. If the SHDN pin is left floating, value specified in the data sheet. This feature is the internal pull-down resistor will put the regulator into independent of the Shutdown input signal (SHDN) that shutdown mode. is provided for external regulator control. If the SHDN input signal is active (LOW), then the output of the When the SHDN input signal is pulled to a logic-low, the regulator shall be disabled regardless of input voltage. PWRGD output signal will also go low and the regulator will enter a low quiescent current state where the TABLE 4-1: SHUTDOWN LOGIC typical quiescent current is 10µA. There is a short time delay (approximately 400ns) when the SHDN input V SHDN V IN OUT signal transitions from high-to-low to prevent signal noise from disabling the regulator. The SHDN pin will < VOFF L OFF ignore low-going pulses that are up to 400ns in pulse < V H OFF OFF width. If the SHDN input is pulled low for more than > V L OFF ON 400ns, the regulator will enter Shutdown mode. This > V H ON small bit of filtering helps to reject any system noise ON spikes on the SHDN input signal. 4.7 Output Capacitor On the rising edge of the SHDN input, the shutdown circuitry will have a 100µs delay before allowing the The MCP1790/MCP1791 requires a minimum output regulator output to turn on. This delay helps to reject capacitance of 1µF tantalum or electrolytic any false turn-on signals or noise on the SHDN input capacitance. The minimum value for ceramic signal. After the 100µs delay, the regulator will start capacitors is 4.7µF. The regulator is stable for all three charging the output capacitor as the regulator output types of capacitors from 4.7µF to 1000µF (see voltage rises from 0V to its final regulated value. The Figure4-3). The MCP1790/MCP1791 regulator may charging current will be limited by the short circuit be used with a 1µF ceramic output capacitor if a current value of the device. If the SHDN input signal is 0.300Ω resistor is placed in series with the capacitor. pulled low during the 100µs delay period, the timer will The low ESR and corresponding pole of the ceramic be reset and the delay time will start over again on the capacitor causes the instability below 4.7µF. next rising edge of the SHDN input. The total time from The Equivalent Series Resistance (ESR) of the output the SHDN input going high (turn-on) to the regulator capacitor must be no greater than 3 ohms. The output output being in regulation shall typically be 200µs capacitor should be located as close to the regulator (100µs + 100µs) for a C = 1.0µF. LOAD output as is practical. Ceramic materials X7R and X5R have low temperature coefficients and are TOR CLOAD CHARGING TIME recommended because of their size, cost and environmental robustness qualities. 400ns (typ) 100µs 100µs SHDN VOUT CLOAD = 1.0µF FIGURE 4-2: Shutdown Input Timing Diagram. © 2010 Microchip Technology Inc. DS22075B-page 15

MCP1790/MCP1791 4.8 Output Current and Current The 5.0V regulator has an overload current limiting of Limiting approximately 120mA. If VREG is lower than 3.5V, IOUT will start to fold back and decrease along with V REG The MCP1790/MCP1791 devices are tested and until IOUT is less than 105mA and VREG is near 0 volts. ensured to supply a minimum of 70mA of output The 3.3V regulator has an overload current limiting of current. approximately 130mA. If V is lower than 2.5V, I REG OUT The MCP1790/MCP1791 also incorporate an output will start to fold back and decrease along with V REG current limit foldback. When the regulator is in an until IOUT is less than 99mA and VREG is near 0 volts. overcurrent condition, V will decrease with OUT increasing load. When V falls below 30% (typical) OUT of V , the output current will start to fold back. The R output current will fold back to less than 100mA (typical) when V is near 0 volts. OUT ESR Curves 10 Instable Stable only 1 with Tantalum or Electrolytic cap. Stable ] with m Tantalum, h Instable Electrolytic and o Ceramic cap. [ 0.1 R S E 0.01 Instable 0.001 0.1 1 10 100 1000 Load Capacitor [uF] FIGURE 4-3: ESR Curves for Load Capacitor Selection. DS22075B-page 16 © 2010 Microchip Technology Inc.

MCP1790/MCP1791 4.9 Power Good Output (PWRGD) The MCP1791 has an open-drain Power Good (PWRGD) output signal capable of sinking a minimum VPWRGD_TH of 5.0mA of current while maintaining a PWRGD output voltage of 0.4V or less. VOUT VPWRGD_HYS TPG As the output voltage of the LDO rises, the PWRGD output will be held low until the output voltage has 30µs exceeded the power good threshold (V ) level VON by an amount equal to the power good PhWysRtGerDe_sTiHs value TVDET_PWRGD ((V ), typically 2% of V . Once this threshold 235µs PWRGD_HYS R has been exceeded, the power good output signal will PWRGD be pulled high by an external pull-up resistor, indicating that the output voltage is stable and within regulation VOL limits. If the output voltage of the LDO falls below the power FIGURE 4-4: Power Good Timing. good threshold (V ) level, the power good PWRGD_TH output will transition low. The power good circuitry has a 235µs delay when detecting a falling output voltage, C = 1.0ΜF LOAD which helps to increase noise immunity of the power good output and avoid false triggering of the power good output during fast output transients. See VIN Figure4-4 for power good timing characteristics. TOR When the LDO is put into Shutdown mode using the 100µs 100µs SHDN input, the power good output is pulled low within 400ns typical, indicating that the output voltage will be out of regulation. The timing diagram for the power SHDN TPG good output when using the shutdown input is shown in Figure4-5. The PWRGD output may be pulled up to either V or IN V . When pulled to V , the PWRGD output will OUT OUT VOUT sink very little current during shutdown. When PWRGD is pulled up to V , the PWRGD output will sink current IN during shutdown. That is because V is 0 during OUT shutdown while V is still active. When the PWRGD IN output is pulled to V , the PWRGD output signal will PWRGD IN track V at startup until the threshold of the PWRGD IN circuitry has been reached and the PWRGD circuitry pulls the signal back low. Therefore, when pulling FIGURE 4-5: Power Good Timing from PWRGD to V instead of V , the designer must be Shutdown. IN OUT aware of the PWRGD signal going high while the input voltage is rising at startup. Pulling PWRGD to V OUT removes the startup pulse. © 2010 Microchip Technology Inc. DS22075B-page 17

MCP1790/MCP1791 5.0 APPLICATION CIRCUITS/ EQUATION 5-2: ISSUES T = P × Rθ +T J(MAX) TOTAL JA AMAX 5.1 Typical Application T = Maximum continuous junction J(MAX) temperature The MCP1790/MCP1791 is most commonly used as a voltage regulator. It is a high voltage input capability PTOTAL = Total device power dissipation and thermal protection make it ideal for automotive and Rθ = Thermal resistance from junction JA 24V industrial applications. to ambient T = Maximum ambient temperature AMAX The maximum power dissipation capability for a MCP1791 package can be calculated given the junction-to- ambient thermal resistance and the maximum ambient 1 2 3 4 5 PWRGD temperature for the application. The following equation VIN 5 1N4002 10kΩ VOUT can be used to determine the package maximum + + internal power dissipation. 24VDC 1CµINF COUT 5V@70mA 4.7µF Ceramic Ceramic EQUATION 5-3: FIGURE 5-1: Typical Application. PD(MAX) = (---T---J---(--M----A---X--R-)---θ–-----T----A---(--M----A---X---)--)- JA 5.1.1 APPLICATION INPUT CONDITIONS PD(MAX) = Maximum device power dissipation Package Type = SOT-223-5 T = Maximum continuous junction J(MAX) Input Voltage Range = 8V to 24V temperature VIN maximum = 24V TA(MAX) = Maximum ambient temperature VOUT typical = 5.0V RθJA = Thermal resistance from junction I = 70mA maximum to ambient OUT 5.2 Power Calculations EQUATION 5-4: 5.2.1 POWER DISSIPATION TJ(RISE) = PTOTAL× RθJA The internal power dissipation of the MCP1790/ T = Rise in device junction MCP1791 is a function of input voltage, output voltage J(RISE) temperature over the ambient and output current. The power dissipation, as a result temperature of the quiescent current draw, is so low, it is insignificant (70.0µA x V ). The following equation P = Total device power dissipation IN TOTAL can be used to calculate the internal power dissipation Rθ = Thermal resistance from JA of the LDO. junction-to-ambient EQUATION 5-1: PLDO = (VIN(MAX))–VOUT(MIN))× IOUT(MAX)) EQUATION 5-5: P = LDO Pass device internal power LDO T = T +T dissipation J J(RISE) A V = Maximum input voltage T = Junction Temperature IN(MAX) J V = LDO minimum output voltage T = Rise in device junction OUT(MIN) J(RISE) temperature over the ambient temperature The maximum continuous operating junction temperature specified for the MCP1790/MCP1791 is T = Ambient temperature A +125°C. To estimate the internal junction temperature of the MCP1790/MCP1791, the total internal power dissipation is multiplied by the thermal resistance from junction to ambient (Rθ ). The thermal resistance JA from junction to ambient for the SOT-223-5 package is estimated at 62°C/W. DS22075B-page 18 © 2010 Microchip Technology Inc.

MCP1790/MCP1791 5.3 Power Dissipation Example 5.3.1.2 Junction Temperature Estimate Internal power dissipation, junction temperature rise, To estimate the internal junction temperature, the junction temperature and maximum power dissipation calculated temperature rise is added to the ambient or are calculated in the following example. The power offset temperature. For this example, the worst-case dissipation, as a result of ground current, is small junction temperature is estimated below. enough to be neglected. T = T + T J JRISE A(MAX) 5.3.1 POWER DISSIPATION EXAMPLE T = 99.2°C J Package: 5.3.1.3 Maximum Package Power Package Type = SOT-223-5 Dissipation at +40°C Ambient Input Voltage: Temperature VIN = 8V to 24V SOT-223-5 (62°C/Watt = RθJA) LDO Output Voltages and Currents: P = (125°C - 40°C) / 62°C/W D(MAX) VOUT = 5.0V PD(MAX) = 1.371 Watts IOUT = 50mA DDPAK-5 (32°C/Watt = RθJA) Maximum Ambient Temperature: P = (125°C - 40°C) / 32°C/W D(MAX) TA(MAX) = +40°C PD(MAX) = 2.656 Watts Internal Power Dissipation: Internal Power dissipation is the product of the LDO 5.4 Pulsed Load Applications output current times the voltage across the LDO For some applications, there are pulsed load current (V to V ). IN OUT events that may exceed the specified 70mA maximum P = (V - V ) x I LDO(MAX) IN(MAX) OUT(MIN) OUT(MAX) specification of the MCP1790/MCP1791. The internal PLDO = (24V - (0.98 x 5.0V)) x 50mA current foldback feature of the MCP1790/MCP1791 will P = 955 milli-Watts prevent high peak load demands from causing LDO non-recoverable damage. The Current Foldback 5.3.1.1 Device Junction Temperature Rise feature of the device will limit the output voltage and output current during pulsed applications. As the The internal junction temperature rise is a function of current rises above the foldback current threshold, the internal power dissipation and the thermal resistance output voltage will decrease. from junction to ambient for the application. The thermal resistance from junction to ambient (Rθ ) is JA derived from an EIA/JEDEC standard for measuring thermal resistance for small surface mount packages. The EIA/JEDEC specification is JESD51-7, “High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages”. The standard describes the test method and board specifications for measuring the thermal resistance from junction to ambient. The actual thermal resistance for a particular application can vary depending on many factors, such as copper area and thickness. Refer to AN792, “A Method to Determine How Much Power a SOT23 Can Dissipate in an Application”, (DS00792), for more information regarding this subject. T = P x Rq J(RISE) TOTAL JA TJRISE = 955 milli-Watts x 62°C/Watt TJRISE = 59.2°C © 2010 Microchip Technology Inc. DS22075B-page 19

MCP1790/MCP1791 6.0 PACKAGING INFORMATION 6.1 Package Marking Information 3-Lead DDPAK (MCP1790) Example: XXXXXXXXX MCP1790 XXXXXXXXX 50EEB^e^3 YYWWNNN 1005256 1 2 3 1 2 3 3-Lead SOT-223 (MCP1790) Example: XXXXXXX 179050 XXXYYWW EDB1005 NNN 256 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. DS22075B-page 20 © 2010 Microchip Technology Inc.

MCP1790/MCP1791 6.1 Package Marking Information (Continued) 5-Lead DDPAK (Fixed) (MCP1791) Example: XXXXXXXXX MCP1791 XXXXXXXXX 50EET^e^3 YYWWNNN 1005256 1 2 3 4 5 1 2 3 4 5 5-Lead SOT-223 (MCP1791) Example: XXXXXXX 179150 XXXYYWW EDC1005 NNN 256 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2010 Microchip Technology Inc. DS22075B-page 21

MCP1790/MCP1791 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:17)(cid:18)(cid:8)(cid:19)(cid:20)(cid:20)(cid:9)(cid:21)(cid:22)(cid:23) (cid:24)(cid:25)(cid:12)(cid:5)(cid:26) 0(cid:10)(cid:9)(cid:2) (cid:11)(cid:14)(cid:2)#(cid:10)" (cid:2)(cid:8)&(cid:9)(cid:9)(cid:14)(cid:15) (cid:2)(cid:12)(cid:28)(cid:8)1(cid:28)(cid:17)(cid:14)(cid:2)$(cid:9)(cid:28)/(cid:7)(cid:15)(cid:17)"2(cid:2)(cid:12)(cid:16)(cid:14)(cid:28)"(cid:14)(cid:2)"(cid:14)(cid:14)(cid:2) (cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)3(cid:28)(cid:8)1(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)(cid:31)(cid:7)(cid:8)(cid:28) (cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28) (cid:14)$(cid:2)(cid:28) (cid:2) (cid:11) (cid:12)-44///(cid:20)#(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)#4(cid:12)(cid:28)(cid:8)1(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) E E1 L1 D1 D H 1 N b e BOTTOMVIEW TOPVIEW b1 CHAMFER OPTIONAL A C2 φ A1 c L 5(cid:15)(cid:7) " (cid:19)6!7%(cid:22) (cid:21)(cid:7)#(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:2)8(cid:7)#(cid:7) " (cid:6)(cid:19)6 69(cid:6) (cid:6)(cid:25): 6&#;(cid:14)(cid:9)(cid:2)(cid:10)(cid:31)(cid:2)3(cid:7)(cid:15)" 6 * 3(cid:7) (cid:8)(cid:11) (cid:14) (cid:20)(cid:29)(cid:4)(cid:4)(cid:2),(cid:22)! 9.(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)7(cid:14)(cid:7)(cid:17)(cid:11) (cid:25) (cid:20)(cid:29)<(cid:4) = (cid:20)(cid:29)(cid:24)(cid:4) (cid:22) (cid:28)(cid:15)$(cid:10)(cid:31)(cid:31)(cid:2)(cid:2)(cid:30) (cid:25)(cid:29) (cid:20)(cid:4)(cid:4)(cid:4) = (cid:20)(cid:4)(cid:29)(cid:4) 9.(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)$ (cid:11) % (cid:20)*?(cid:4) = (cid:20)(cid:23)(cid:3)(cid:4) %’(cid:12)(cid:10)"(cid:14)$(cid:2)3(cid:28)$(cid:2)>(cid:7)$ (cid:11) %(cid:29) (cid:20)(cid:3)(cid:23)( = = (cid:6)(cid:10)(cid:16)$(cid:14)$(cid:2)3(cid:28)(cid:8)1(cid:28)(cid:17)(cid:14)(cid:2)8(cid:14)(cid:15)(cid:17) (cid:11) (cid:21) (cid:20)**(cid:4) = (cid:20)*?(cid:4) 9.(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:15)(cid:17) (cid:11) 7 (cid:20)((cid:23)(cid:24) = (cid:20)<(cid:3)( %’(cid:12)(cid:10)"(cid:14)$(cid:2)3(cid:28)$(cid:2)8(cid:14)(cid:15)(cid:17) (cid:11) (cid:21)(cid:29) (cid:20)(cid:3)(cid:5)(cid:4) = = 8(cid:14)(cid:28)$(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)1(cid:15)(cid:14)"" (cid:8) (cid:20)(cid:4)(cid:29)(cid:23) = (cid:20)(cid:4)(cid:3)(cid:24) 3(cid:28)$(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)1(cid:15)(cid:14)"" !(cid:3) (cid:20)(cid:4)(cid:23)( = (cid:20)(cid:4)<( 8(cid:10)/(cid:14)(cid:9)(cid:2)8(cid:14)(cid:28)$(cid:2)>(cid:7)$ (cid:11) ; (cid:20)(cid:4)(cid:3)(cid:4) = (cid:20)(cid:4)*(cid:24) 5(cid:12)(cid:12)(cid:14)(cid:9)(cid:2)8(cid:14)(cid:28)$(cid:2)>(cid:7)$ (cid:11) ;(cid:29) (cid:20)(cid:4)(cid:23)( = (cid:20)(cid:4)(cid:5)(cid:4) 0(cid:10)(cid:10) (cid:2)8(cid:14)(cid:15)(cid:17) (cid:11) 8 (cid:20)(cid:4)<? = (cid:20)(cid:29)(cid:29)(cid:4) 3(cid:28)$(cid:2)8(cid:14)(cid:15)(cid:17) (cid:11) 8(cid:29) = = (cid:20)(cid:4)<(cid:5) 0(cid:10)(cid:10) (cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)@ = ?@ (cid:24)(cid:25)(cid:12)(cid:5)(cid:11)(cid:26) (cid:29)(cid:20) (cid:30)(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)(cid:31)(cid:7)(cid:8)(cid:28)(cid:15) (cid:2)!(cid:11)(cid:28)(cid:9)(cid:28)(cid:8) (cid:14)(cid:9)(cid:7)" (cid:7)(cid:8)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7)#(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)"(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)$(cid:2)%(cid:2)$(cid:10)(cid:2)(cid:15)(cid:10) (cid:2)(cid:7)(cid:15)(cid:8)(cid:16)&$(cid:14)(cid:2)#(cid:10)(cid:16)$(cid:2)(cid:31)(cid:16)(cid:28)"(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10) (cid:9)&"(cid:7)(cid:10)(cid:15)"(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)$(cid:2)(cid:31)(cid:16)(cid:28)"(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10) (cid:9)&"(cid:7)(cid:10)(cid:15)"(cid:2)"(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10) (cid:2)(cid:14)’(cid:8)(cid:14)(cid:14)$(cid:2)(cid:20)(cid:4)(cid:4)()(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)"(cid:7)$(cid:14)(cid:20) *(cid:20) (cid:21)(cid:7)#(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)$(cid:2) (cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6)%(cid:2)+(cid:29)(cid:23)(cid:20)((cid:6)(cid:20) ,(cid:22)!- ,(cid:28)"(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)#(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14) (cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)’(cid:28)(cid:8) (cid:2).(cid:28)(cid:16)&(cid:14)(cid:2)"(cid:11)(cid:10)/(cid:15)(cid:2)/(cid:7) (cid:11)(cid:10)& (cid:2) (cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)"(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)/(cid:7)(cid:15)(cid:17)!(cid:4)(cid:23)(cid:27)(cid:4)(cid:29)(cid:29), DS22075B-page 22 © 2010 Microchip Technology Inc.

MCP1790/MCP1791 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:27)(cid:28)(cid:6)(cid:10)(cid:10)(cid:8)(cid:29)(cid:30)(cid:12)(cid:10)(cid:13)(cid:31)(cid:5)(cid:8) !(cid:6)(cid:31)(cid:11)(cid:13)(cid:11)(cid:12)(cid:25)!(cid:8)(cid:15)(cid:20)(cid:17)(cid:18)(cid:8)(cid:19)(cid:27)(cid:29) (cid:3)""(cid:2)(cid:23) (cid:24)(cid:25)(cid:12)(cid:5)(cid:26) 0(cid:10)(cid:9)(cid:2) (cid:11)(cid:14)(cid:2)#(cid:10)" (cid:2)(cid:8)&(cid:9)(cid:9)(cid:14)(cid:15) (cid:2)(cid:12)(cid:28)(cid:8)1(cid:28)(cid:17)(cid:14)(cid:2)$(cid:9)(cid:28)/(cid:7)(cid:15)(cid:17)"2(cid:2)(cid:12)(cid:16)(cid:14)(cid:28)"(cid:14)(cid:2)"(cid:14)(cid:14)(cid:2) (cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)3(cid:28)(cid:8)1(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)(cid:31)(cid:7)(cid:8)(cid:28) (cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28) (cid:14)$(cid:2)(cid:28) (cid:2) (cid:11) (cid:12)-44///(cid:20)#(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)#4(cid:12)(cid:28)(cid:8)1(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D b2 E1 E 1 2 3 e e1 A A2 φ c b A1 L 5(cid:15)(cid:7) " (cid:6)(cid:19)88(cid:19)(cid:6)%(cid:13)%(cid:26)(cid:22) (cid:21)(cid:7)#(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:2)8(cid:7)#(cid:7) " (cid:6)(cid:19)6 69(cid:6) (cid:6)(cid:25): 6&#;(cid:14)(cid:9)(cid:2)(cid:10)(cid:31)(cid:2)8(cid:14)(cid:28)$" 6 * 8(cid:14)(cid:28)$(cid:2)3(cid:7) (cid:8)(cid:11) (cid:14) (cid:3)(cid:20)*(cid:4)(cid:2),(cid:22)! 9& "(cid:7)$(cid:14)(cid:2)8(cid:14)(cid:28)$(cid:2)3(cid:7) (cid:8)(cid:11) (cid:14)(cid:29) (cid:23)(cid:20)<(cid:4)(cid:2),(cid:22)! 9.(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)7(cid:14)(cid:7)(cid:17)(cid:11) (cid:25) = = (cid:29)(cid:20)?(cid:4) (cid:22) (cid:28)(cid:15)$(cid:10)(cid:31)(cid:31) (cid:25)(cid:29) (cid:4)(cid:20)(cid:4)(cid:3) = (cid:4)(cid:20)(cid:29)(cid:4) (cid:6)(cid:10)(cid:16)$(cid:14)$(cid:2)3(cid:28)(cid:8)1(cid:28)(cid:17)(cid:14)(cid:2)7(cid:14)(cid:7)(cid:17)(cid:11) (cid:25)(cid:3) (cid:29)(cid:20)((cid:4) (cid:29)(cid:20)<(cid:4) (cid:29)(cid:20)(cid:5)(cid:4) 9.(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)$ (cid:11) % <(cid:20)(cid:5)(cid:4) (cid:5)(cid:20)(cid:4)(cid:4) (cid:5)(cid:20)*(cid:4) (cid:6)(cid:10)(cid:16)$(cid:14)$(cid:2)3(cid:28)(cid:8)1(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)$ (cid:11) %(cid:29) *(cid:20)*(cid:4) *(cid:20)((cid:4) *(cid:20)(cid:5)(cid:4) 9.(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:15)(cid:17) (cid:11) (cid:21) <(cid:20)*(cid:4) <(cid:20)((cid:4) <(cid:20)(cid:5)(cid:4) 8(cid:14)(cid:28)$(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)1(cid:15)(cid:14)"" (cid:8) (cid:4)(cid:20)(cid:3)* (cid:4)(cid:20)*(cid:4) (cid:4)(cid:20)*( 8(cid:14)(cid:28)$(cid:2)>(cid:7)$ (cid:11) ; (cid:4)(cid:20)<(cid:4) (cid:4)(cid:20)(cid:5)< (cid:4)(cid:20)?(cid:23) (cid:13)(cid:28);(cid:2)8(cid:14)(cid:28)$(cid:2)>(cid:7)$ (cid:11) ;(cid:3) (cid:3)(cid:20)(cid:24)(cid:4) *(cid:20)(cid:4)(cid:4) *(cid:20)(cid:29)(cid:4) 0(cid:10)(cid:10) (cid:2)8(cid:14)(cid:15)(cid:17) (cid:11) 8 (cid:4)(cid:20)(cid:5)( = = 8(cid:14)(cid:28)$(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)@ = (cid:29)(cid:4)@ (cid:24)(cid:25)(cid:12)(cid:5)(cid:11)(cid:26) (cid:29)(cid:20) (cid:21)(cid:7)#(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)"(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)$(cid:2)%(cid:29)(cid:2)$(cid:10)(cid:2)(cid:15)(cid:10) (cid:2)(cid:7)(cid:15)(cid:8)(cid:16)&$(cid:14)(cid:2)#(cid:10)(cid:16)$(cid:2)(cid:31)(cid:16)(cid:28)"(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10) (cid:9)&"(cid:7)(cid:10)(cid:15)"(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)$(cid:2)(cid:31)(cid:16)(cid:28)"(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10) (cid:9)&"(cid:7)(cid:10)(cid:15)"(cid:2)"(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10) (cid:2)(cid:14)’(cid:8)(cid:14)(cid:14)$(cid:2)(cid:4)(cid:20)(cid:29)(cid:3)(cid:5)(cid:2)##(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)"(cid:7)$(cid:14)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7)#(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)$(cid:2) (cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6)%(cid:2)+(cid:29)(cid:23)(cid:20)((cid:6)(cid:20) ,(cid:22)!- ,(cid:28)"(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)#(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14) (cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)’(cid:28)(cid:8) (cid:2).(cid:28)(cid:16)&(cid:14)(cid:2)"(cid:11)(cid:10)/(cid:15)(cid:2)/(cid:7) (cid:11)(cid:10)& (cid:2) (cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)"(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)/(cid:7)(cid:15)(cid:17)!(cid:4)(cid:23)(cid:27)(cid:4)*(cid:3), © 2010 Microchip Technology Inc. DS22075B-page 23

MCP1790/MCP1791 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:27)(cid:28)(cid:6)(cid:10)(cid:10)(cid:8)(cid:29)(cid:30)(cid:12)(cid:10)(cid:13)(cid:31)(cid:5)(cid:8) !(cid:6)(cid:31)(cid:11)(cid:13)(cid:11)(cid:12)(cid:25)!(cid:8)(cid:15)(cid:20)(cid:17)(cid:18)(cid:8)(cid:19)(cid:27)(cid:29) (cid:3)""(cid:2)(cid:23) (cid:24)(cid:25)(cid:12)(cid:5)(cid:26) 0(cid:10)(cid:9)(cid:2) (cid:11)(cid:14)(cid:2)#(cid:10)" (cid:2)(cid:8)&(cid:9)(cid:9)(cid:14)(cid:15) (cid:2)(cid:12)(cid:28)(cid:8)1(cid:28)(cid:17)(cid:14)(cid:2)$(cid:9)(cid:28)/(cid:7)(cid:15)(cid:17)"2(cid:2)(cid:12)(cid:16)(cid:14)(cid:28)"(cid:14)(cid:2)"(cid:14)(cid:14)(cid:2) (cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)3(cid:28)(cid:8)1(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)(cid:31)(cid:7)(cid:8)(cid:28) (cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28) (cid:14)$(cid:2)(cid:28) (cid:2) (cid:11) (cid:12)-44///(cid:20)#(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)#4(cid:12)(cid:28)(cid:8)1(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) DS22075B-page 24 © 2010 Microchip Technology Inc.

MCP1790/MCP1791 #(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16) (cid:18)(cid:8)(cid:19)(cid:20)(cid:20)(cid:9)(cid:21)(cid:22)(cid:23) (cid:24)(cid:25)(cid:12)(cid:5)(cid:26) 0(cid:10)(cid:9)(cid:2) (cid:11)(cid:14)(cid:2)#(cid:10)" (cid:2)(cid:8)&(cid:9)(cid:9)(cid:14)(cid:15) (cid:2)(cid:12)(cid:28)(cid:8)1(cid:28)(cid:17)(cid:14)(cid:2)$(cid:9)(cid:28)/(cid:7)(cid:15)(cid:17)"2(cid:2)(cid:12)(cid:16)(cid:14)(cid:28)"(cid:14)(cid:2)"(cid:14)(cid:14)(cid:2) (cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)3(cid:28)(cid:8)1(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)(cid:31)(cid:7)(cid:8)(cid:28) (cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28) (cid:14)$(cid:2)(cid:28) (cid:2) (cid:11) (cid:12)-44///(cid:20)#(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)#4(cid:12)(cid:28)(cid:8)1(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) E E1 L1 D1 D H 1 N b e BOTTOMVIEW TOPVIEW CHAMFER OPTIONAL A C2 φ A1 c L 5(cid:15)(cid:7) " (cid:19)6!7%(cid:22) (cid:21)(cid:7)#(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:2)8(cid:7)#(cid:7) " (cid:6)(cid:19)6 69(cid:6) (cid:6)(cid:25): 6&#;(cid:14)(cid:9)(cid:2)(cid:10)(cid:31)(cid:2)3(cid:7)(cid:15)" 6 ( 3(cid:7) (cid:8)(cid:11) (cid:14) (cid:20)(cid:4)<(cid:5)(cid:2),(cid:22)! 9.(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)7(cid:14)(cid:7)(cid:17)(cid:11) (cid:25) (cid:20)(cid:29)<(cid:4) = (cid:20)(cid:29)(cid:24)(cid:4) (cid:22) (cid:28)(cid:15)$(cid:10)(cid:31)(cid:31)(cid:2)(cid:2)(cid:30) (cid:25)(cid:29) (cid:20)(cid:4)(cid:4)(cid:4) = (cid:20)(cid:4)(cid:29)(cid:4) 9.(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)$ (cid:11) % (cid:20)*?(cid:4) = (cid:20)(cid:23)(cid:3)(cid:4) %’(cid:12)(cid:10)"(cid:14)$(cid:2)3(cid:28)$(cid:2)>(cid:7)$ (cid:11) %(cid:29) (cid:20)(cid:3)(cid:23)( = = (cid:6)(cid:10)(cid:16)$(cid:14)$(cid:2)3(cid:28)(cid:8)1(cid:28)(cid:17)(cid:14)(cid:2)8(cid:14)(cid:15)(cid:17) (cid:11) (cid:21) (cid:20)**(cid:4) = (cid:20)*?(cid:4) 9.(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:15)(cid:17) (cid:11) 7 (cid:20)((cid:23)(cid:24) = (cid:20)<(cid:3)( %’(cid:12)(cid:10)"(cid:14)$(cid:2)3(cid:28)$(cid:2)8(cid:14)(cid:15)(cid:17) (cid:11) (cid:21)(cid:29) (cid:20)(cid:3)(cid:5)(cid:4) = = 8(cid:14)(cid:28)$(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)1(cid:15)(cid:14)"" (cid:8) (cid:20)(cid:4)(cid:29)(cid:23) = (cid:20)(cid:4)(cid:3)(cid:24) 3(cid:28)$(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)1(cid:15)(cid:14)"" !(cid:3) (cid:20)(cid:4)(cid:23)( = (cid:20)(cid:4)<( 8(cid:14)(cid:28)$(cid:2)>(cid:7)$ (cid:11) ; (cid:20)(cid:4)(cid:3)(cid:4) = (cid:20)(cid:4)*(cid:24) 0(cid:10)(cid:10) (cid:2)8(cid:14)(cid:15)(cid:17) (cid:11) 8 (cid:20)(cid:4)<? = (cid:20)(cid:29)(cid:29)(cid:4) 3(cid:28)$(cid:2)8(cid:14)(cid:15)(cid:17) (cid:11) 8(cid:29) = = (cid:20)(cid:4)<(cid:5) 0(cid:10)(cid:10) (cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)@ = ?@ (cid:24)(cid:25)(cid:12)(cid:5)(cid:11)(cid:26) (cid:29)(cid:20) (cid:30)(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)(cid:31)(cid:7)(cid:8)(cid:28)(cid:15) (cid:2)!(cid:11)(cid:28)(cid:9)(cid:28)(cid:8) (cid:14)(cid:9)(cid:7)" (cid:7)(cid:8)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7)#(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)"(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)$(cid:2)%(cid:2)$(cid:10)(cid:2)(cid:15)(cid:10) (cid:2)(cid:7)(cid:15)(cid:8)(cid:16)&$(cid:14)(cid:2)#(cid:10)(cid:16)$(cid:2)(cid:31)(cid:16)(cid:28)"(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10) (cid:9)&"(cid:7)(cid:10)(cid:15)"(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)$(cid:2)(cid:31)(cid:16)(cid:28)"(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10) (cid:9)&"(cid:7)(cid:10)(cid:15)"(cid:2)"(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10) (cid:2)(cid:14)’(cid:8)(cid:14)(cid:14)$(cid:2)(cid:20)(cid:4)(cid:4)()(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)"(cid:7)$(cid:14)(cid:20) *(cid:20) (cid:21)(cid:7)#(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)$(cid:2) (cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6)%(cid:2)+(cid:29)(cid:23)(cid:20)((cid:6)(cid:20) ,(cid:22)!- ,(cid:28)"(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)#(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14) (cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)’(cid:28)(cid:8) (cid:2).(cid:28)(cid:16)&(cid:14)(cid:2)"(cid:11)(cid:10)/(cid:15)(cid:2)/(cid:7) (cid:11)(cid:10)& (cid:2) (cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)"(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)/(cid:7)(cid:15)(cid:17)!(cid:4)(cid:23)(cid:27)(cid:4)(cid:29)(cid:3), © 2010 Microchip Technology Inc. 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MCP1790/MCP1791 #(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:27)(cid:28)(cid:6)(cid:10)(cid:10)(cid:8)(cid:29)(cid:30)(cid:12)(cid:10)(cid:13)(cid:31)(cid:5)(cid:8) !(cid:6)(cid:31)(cid:11)(cid:13)(cid:11)(cid:12)(cid:25)!(cid:8)(cid:15)(cid:20)$(cid:18)(cid:8)(cid:19)(cid:27)(cid:29) (cid:3)""(cid:2)(cid:23) (cid:24)(cid:25)(cid:12)(cid:5)(cid:26) 0(cid:10)(cid:9)(cid:2) (cid:11)(cid:14)(cid:2)#(cid:10)" (cid:2)(cid:8)&(cid:9)(cid:9)(cid:14)(cid:15) (cid:2)(cid:12)(cid:28)(cid:8)1(cid:28)(cid:17)(cid:14)(cid:2)$(cid:9)(cid:28)/(cid:7)(cid:15)(cid:17)"2(cid:2)(cid:12)(cid:16)(cid:14)(cid:28)"(cid:14)(cid:2)"(cid:14)(cid:14)(cid:2) (cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)3(cid:28)(cid:8)1(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)(cid:31)(cid:7)(cid:8)(cid:28) (cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28) (cid:14)$(cid:2)(cid:28) (cid:2) (cid:11) (cid:12)-44///(cid:20)#(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)#4(cid:12)(cid:28)(cid:8)1(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D b2 E1 E 1 2 3 4 N e e1 A A2 φ c b A1 L 5(cid:15)(cid:7) " (cid:6)(cid:19)88(cid:19)(cid:6)%(cid:13)%(cid:26)(cid:22) (cid:21)(cid:7)#(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:2)8(cid:7)#(cid:7) " (cid:6)(cid:19)6 69(cid:6) (cid:6)(cid:25): 6&#;(cid:14)(cid:9)(cid:2)(cid:10)(cid:31)(cid:2)8(cid:14)(cid:28)$" 6 ( 8(cid:14)(cid:28)$(cid:2)3(cid:7) (cid:8)(cid:11) (cid:14) (cid:29)(cid:20)(cid:3)(cid:5)(cid:2),(cid:22)! 9& "(cid:7)$(cid:14)(cid:2)8(cid:14)(cid:28)$(cid:2)3(cid:7) (cid:8)(cid:11) (cid:14)(cid:29) ((cid:20)(cid:4)?(cid:2),(cid:22)! 9.(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)7(cid:14)(cid:7)(cid:17)(cid:11) (cid:25) = = (cid:29)(cid:20)?(cid:4) (cid:22) (cid:28)(cid:15)$(cid:10)(cid:31)(cid:31) (cid:25)(cid:29) (cid:4)(cid:20)(cid:4)(cid:3) (cid:4)(cid:20)(cid:4)< (cid:4)(cid:20)(cid:29)(cid:4) (cid:6)(cid:10)(cid:16)$(cid:14)$(cid:2)3(cid:28)(cid:8)1(cid:28)(cid:17)(cid:14)(cid:2)7(cid:14)(cid:7)(cid:17)(cid:11) (cid:25)(cid:3) (cid:29)(cid:20)(( (cid:29)(cid:20)<(cid:4) (cid:29)(cid:20)<( 9.(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)$ (cid:11) % <(cid:20)?< (cid:5)(cid:20)(cid:4)(cid:4) (cid:5)(cid:20)(cid:3)< (cid:6)(cid:10)(cid:16)$(cid:14)$(cid:2)3(cid:28)(cid:8)1(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)$ (cid:11) %(cid:29) *(cid:20)(cid:23)( *(cid:20)((cid:4) *(cid:20)(( 9.(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:15)(cid:17) (cid:11) (cid:21) <(cid:20)(cid:23)( <(cid:20)((cid:4) <(cid:20)(( 8(cid:14)(cid:28)$(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)1(cid:15)(cid:14)"" (cid:8) (cid:4)(cid:20)(cid:3)(cid:23) (cid:4)(cid:20)(cid:3)? (cid:4)(cid:20)*(cid:3) 8(cid:14)(cid:28)$(cid:2)>(cid:7)$ (cid:11) ; (cid:4)(cid:20)(cid:23)(cid:29) (cid:4)(cid:20)(cid:23)((cid:5) (cid:4)(cid:20)((cid:29) (cid:13)(cid:28);(cid:2)8(cid:14)(cid:28)$(cid:2)>(cid:7)$ (cid:11) ;(cid:3) (cid:3)(cid:20)(cid:24)( *(cid:20)(cid:4)(cid:4) *(cid:20)(cid:4)( 0(cid:10)(cid:10) (cid:2)8(cid:14)(cid:15)(cid:17) (cid:11) 8 (cid:4)(cid:20)(cid:24)(cid:29) = (cid:29)(cid:20)(cid:29)(cid:23) 8(cid:14)(cid:28)$(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)@ (cid:23)@ ?@ (cid:24)(cid:25)(cid:12)(cid:5)(cid:11)(cid:26) (cid:29)(cid:20) (cid:21)(cid:7)#(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)"(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)$(cid:2)%(cid:29)(cid:2)$(cid:10)(cid:2)(cid:15)(cid:10) (cid:2)(cid:7)(cid:15)(cid:8)(cid:16)&$(cid:14)(cid:2)#(cid:10)(cid:16)$(cid:2)(cid:31)(cid:16)(cid:28)"(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10) (cid:9)&"(cid:7)(cid:10)(cid:15)"(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)$(cid:2)(cid:31)(cid:16)(cid:28)"(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10) (cid:9)&"(cid:7)(cid:10)(cid:15)"(cid:2)"(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10) (cid:2)(cid:14)’(cid:8)(cid:14)(cid:14)$(cid:2)(cid:4)(cid:20)(cid:29)(cid:3)(cid:5)(cid:2)##(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)"(cid:7)$(cid:14)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7)#(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)$(cid:2) (cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6)%(cid:2)+(cid:29)(cid:23)(cid:20)((cid:6)(cid:20) ,(cid:22)!- ,(cid:28)"(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)#(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14) (cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)’(cid:28)(cid:8) (cid:2).(cid:28)(cid:16)&(cid:14)(cid:2)"(cid:11)(cid:10)/(cid:15)(cid:2)/(cid:7) (cid:11)(cid:10)& (cid:2) (cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)"(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)/(cid:7)(cid:15)(cid:17)!(cid:4)(cid:23)(cid:27)(cid:29)*(cid:5), DS22075B-page 26 © 2010 Microchip Technology Inc.

MCP1790/MCP1791 #(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:27)(cid:28)(cid:6)(cid:10)(cid:10)(cid:8)(cid:29)(cid:30)(cid:12)(cid:10)(cid:13)(cid:31)(cid:5)(cid:8) !(cid:6)(cid:31)(cid:11)(cid:13)(cid:11)(cid:12)(cid:25)!(cid:8)(cid:15)(cid:20)$(cid:18)(cid:8)(cid:19)(cid:27)(cid:29) (cid:3)""(cid:2)(cid:23) (cid:24)(cid:25)(cid:12)(cid:5)(cid:26) 0(cid:10)(cid:9)(cid:2) (cid:11)(cid:14)(cid:2)#(cid:10)" (cid:2)(cid:8)&(cid:9)(cid:9)(cid:14)(cid:15) (cid:2)(cid:12)(cid:28)(cid:8)1(cid:28)(cid:17)(cid:14)(cid:2)$(cid:9)(cid:28)/(cid:7)(cid:15)(cid:17)"2(cid:2)(cid:12)(cid:16)(cid:14)(cid:28)"(cid:14)(cid:2)"(cid:14)(cid:14)(cid:2) (cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)3(cid:28)(cid:8)1(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)(cid:31)(cid:7)(cid:8)(cid:28) (cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28) (cid:14)$(cid:2)(cid:28) (cid:2) (cid:11) (cid:12)-44///(cid:20)#(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)#4(cid:12)(cid:28)(cid:8)1(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) © 2010 Microchip Technology Inc. DS22075B-page 27

MCP1790/MCP1791 NOTES: DS22075B-page 28 © 2010 Microchip Technology Inc.

MCP1790/MCP1791 APPENDIX A: REVISION HISTORY Revision B (September 2010) The following is the list of modifications: • Updated the Features section. • Removed conditions for the Output Voltage Regulation parameter in the AC/DC Characteristics table. • Updated the symbol used for the Storage Temperature Range parameter in the TEMPERATURE SPECIFICATIONS table. Revision A (March 2008) • Original Release of this Document. © 2010 Microchip Technology Inc. DS22075B-page 29

MCP1790/MCP1791 NOTES: DS22075B-page 30 © 2010 Microchip Technology Inc.

MCP1790/MCP1791 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. XX X X X/ XX Examples: a) MCP1790-3002E/EB:3.0V LDO Regulator, Device Output Feature Tolerance Temp. Package 3LD DDPAK Voltage Code b) MCP1790-3302E/EB:3.3V LDO Regulator, 3LD DDPAK c) MCP1790-5002E/EB:5.0V LDO Regulator, Device: MCP1790: 70mA High Voltage Regulator MCP1790T: 70mA High Voltage Regulator 3LD DDPAK Tape and Reel d) MCP1790-3002E/DB:3.0V LDO Regulator, MCP1791: 70mA High Voltage Regulator 3LD SOT-223 MCP1791T: 70mA High Voltage Regulator e) MCP1790-3302E/DB:3.3V LDO Regulator, Tape and Reel 3LD SOT-223 f) MCP1790-5002E/DB:5.0V LDO Regulator, Output Voltage *: 30 = 3.0V “Standard” 3LD SOT-223 33 = 3.3V “Standard” 50 = 5.0V “Standard” *Contact factory for other output voltage options a) MCP1791-3002E/ET:3.0V LDO Regulator Extra Feature Code: 0 = Fixed 5LD DDPAK b) MCP1791-3302E/ET 3.3V LDO Regulator 5LD DDPAK Tolerance: 2 = 2.5% (Standard) c) MCP1791-5002E/ET:5.0V LDO Regulator 5LD DDPAK Temperature: E = -40°C to +125°C d) MCP1791-3002E/DC3.0V LDO Regulator 5LD SOT-223 Package Type: EB = Plastic, DDPAK, 3-lead e) MCP1791-3302E/DC3.3V LDO Regulator ET = Plastic, DDPAK, 5-lead 5LD SOT-223 DB = Plastic Transistor Outline, SOT-223, 3-lead f) MCP1791-5002E/DC5.0V LDO Regulator DC = Plastic Transistor Outline, SOT-223, 5-lead 5LD SOT-223 © 2010 Microchip Technology Inc. DS22075B-page 31

MCP1790/MCP1791 NOTES: DS22075B-page 32 © 2010 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. PIC32 logo, rfPIC and UNI/O are registered trademarks of MICROCHIP MAKES NO REPRESENTATIONS OR Microchip Technology Incorporated in the U.S.A. and other WARRANTIES OF ANY KIND WHETHER EXPRESS OR countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MXDEV, MXLAB, SEEVAL and The Embedded Control QUALITY, PERFORMANCE, MERCHANTABILITY OR Solutions Company are registered trademarks of Microchip FITNESS FOR PURPOSE. Microchip disclaims all liability Technology Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, CodeGuard, devices in life support and/or safety applications is entirely at dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, the buyer’s risk, and the buyer agrees to defend, indemnify and ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial hold harmless Microchip from any and all damages, claims, Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified suits, or expenses resulting from such use. No licenses are logo, MPLIB, MPLINK, mTouch, Omniscient Code conveyed, implicitly or otherwise, under any Microchip Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, intellectual property rights. PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2010, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-60932-511-4 Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2010 Microchip Technology Inc. DS22075B-page 33

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