MCP1726 1A, Low-Voltage, Low Quiescent Current LDO Regulator Features: Description: • 1A Output Current Capability The MCP1726 is a 1A Low Dropout (LDO) linear • Input Operating Voltage Range: 2.3V to 6.0V regulator that provides high current and low output voltages in a very small package. The MCP1726 • Adjustable Output Voltage Range: 0.8V to 5.0V comes in fixed or adjustable output voltage versions, • Standard Fixed Output Voltages: with an output voltage range of 0.8V to 5.0V. The 1A - 0.8V, 1.2V, 1.8V, 2.5V, 3.0V, 3.3V, 5.0V output current capability and low output voltage • Low Dropout Voltage: 220mV typical at 1A capability make the MCP1726 a good choice for new • Typical Output Voltage Tolerance: ±0.5% sub-1.8V output voltage LDO applications that have • Stable with 1.0µF Ceramic Output Capacitor high current demands. • Fast Response to Load Transients The MCP1726 is stable using ceramic output • Low Supply Current: 140µA (typical) capacitors that inherently provide lower output noise and reduce the size and cost of the entire regulator • Low Shutdown Supply Current: 0.1µA (typical) solution. Only 1µF of output capacitance is needed to • Adjustable Delay on Power Good Output stabilize the LDO. • Short-Circuit Current Limiting and Using CMOS construction, the quiescent current Overtemperature Protection consumed by the MCP1726 is typically less than • 3x3 DFN-8 and SOIC-8 Package Options 140µA over the entire input voltage range, making it attractive for portable computing applications that Applications: demand high output current. When the MCP1726 is shut down, the quiescent current is reduced to less • High-Speed Driver Chipset Power than 0.1µA. • Networking Backplane Cards The scaled-down output voltage is internally monitored • Notebook Computers and a Power Good (PWRGD) output is provided when • Network Interface Cards the output is within 92% of regulation (typical). An • Palmtop Computers external capacitor can be used on the C pin to DELAY • 2.5V to 1.XV Regulators adjust the delay from 1ms to 300ms. The overtemperature and short-circuit current limiting provide additional protection for the LDO during system fault conditions. Package Types MCP1726-ADJ MCP1726-xx MCP1726-ADJ MCP1726-xx SOIC SOIC 3x3 DFN 3x3 DFN VIN 1 8 VOUT VIN 1 8 VOUT VIN 1 8 VOUT VIN 1 8 VOUT VIN 2 7 ADJ VIN 2 7 VOUT VIN 2 EP 7 ADJ VIN 2 EP 7 VOUT SHDN 3 6 CDELAY SHDN 3 6 CDELAY SHDN 3 9 6 CDELAY SHDN 3 9 6 CDELAY GND 4 5 PWRGD GND 4 5 PWRGD GND 4 5 PWRGD GND 4 5 PWRGD  2005-2014 Microchip Technology Inc. DS20001936D-page 1

MCP1726 Typical Application MCP1726 Fixed Output Voltage VIN=2.3V to 2.8V 1 VIN VOUT 8 VOUT=1.8V @ 1A 2 V V 7 C1 IN OUT C2 4.7µF 1µF 3 SHDN C 6 DELAY R 1 4 GND PWRGD 5 100k C On 3 1000pF Off PWRGD MCP1726 Adjustable Output Voltage VIN=2.3V to 2.8V 1 VIN VOUT 8 VOUT=1.2V @ 1A R 1 2 VIN ADJ 7 40k C1 C2 4.7µF 1µF 3 SHDN C 6 DELAY R 3 4 GND PWRGD 5 100k On R C 2 Off 10300pF 20k PWRGD DS20001936D-page 2  2005-2014 Microchip Technology Inc.

MCP1726 Functional Block Diagram PMOS VIN VOUT Undervoltage Lockout (UVLO) I SNS Cf Rf SHDN ADJ Driver w/ Limit + and SHDN EA Overtemperature – Sensing SHDN V REF V IN SHDN Reference Soft-Start PWRGD Comp T DELAY GND 92% of V REF C DELAY  2005-2014 Microchip Technology Inc. DS20001936D-page 3

MCP1726 1.0 ELECTRICAL † Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is CHARACTERISTICS a stress rating only and functional operation of the device at those or any other conditions above those indicated in the Absolute Maximum Ratings † operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods VIN....................................................................................6.5V may affect device reliability. Maximum Voltage on Any Pin..(GND–0.3V) to (V +0.3)V DD Maximum Junction Temperature, T ...........................+150°C J Maximum Power Dissipation.........Internally-Limited (Note6) Storage Temperature.....................................-65°C to +150°C DC CHARACTERISTICS Electrical Specifications: Unless otherwise noted, V =(V +0.5V) or 2.3V, whichever is greater, I =1mA, IN R OUT C =C =4.7µF (X7R Ceramic), T =+25°C. Boldface type applies for junction temperatures, T (Note7), of -40°C to +125°C. IN OUT A J Parameters Sym. Min. Typ. Max. Units Conditions Input Operating Voltage V 2.3 6.0 V Note1 IN Input Quiescent Current I — 140 220 µA I =0mA, V =V +0.5V, q L IN R V =0.8V to 5.0V OUT Input Quiescent Current for I — 0.1 3 µA SHDN=GND SHDN SHDN Mode Maximum Output Current I 1 — — A V =2.3V to 6.0V (Note1) OUT IN Line Regulation V / — 0.05 0.3 %/V (V +0.5)VV 6V OUT R IN (V xV ) OUT IN Load Regulation V /V -1.5 ±0.5 1.5 % I =1mA to 1A, OUT OUT OUT V =(V +0.6)V (Note4) IN R Output Short-Circuit Current I — 1.7 — A V =(V +0.5)V, OUT_SC IN R R <0.1, Peak Current LOAD Adjust Pin Characteristics Adjust Pin Reference Voltage V 0.402 0.410 0.418 V V =2.3V to V =6.0V, ADJ IN IN I =1mA OUT Adjust Pin Leakage Current I -10 ±0.01 +10 nA V =6.0V, V =0Vto6V ADJ IN ADJ Adjust Temperature Coefficient TCV — 40 — ppm/°C Note3 OUT Fixed-Output Characteristics Voltage Regulation V V –2.5% V ±0.5% V +2.5% V Note2 OUT R R R Dropout Characteristics Dropout Voltage V –V — 220 500 mV I =1A, V =2.3V IN OUT OUT IN(MIN) (Note5) Note 1: The minimum V must meet two conditions: V 2.3V and V V +2.5%V . IN IN IN R DROPOUT 2: V is the nominal regulator output voltage for the fixed cases. V =1.2V, 1.8V, etc. V is the desired set point output R R R voltage for the adjustable cases. V =V x((R /R )+1). See Figure4-1. R ADJ 1 2 3: TCV =(V –V )x106/(V xTemperature). V is the highest voltage measured over the OUT OUT-HIGH OUT-LOW R OUT-HIGH temperature range. V is the lowest voltage measured over the temperature range. OUT-LOW 4: Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is tested over a load range from 1mA to the maximum specified output current. 5: Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its nominal value that was measured with an input voltage of V =V +0.5V. IN R 6: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air. (i.e., T , T ,  ). Exceeding the maximum allowable power A J JA dissipation will cause the device operating junction temperature to exceed the maximum 150°C rating. Sustained junction temperatures above 125°C can impact device reliability. 7: The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the desired junction temperature. The test time is small enough such that the rise in the junction temperature over the ambient temperature is not significant. DS20001936D-page 4  2005-2014 Microchip Technology Inc.

MCP1726 DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise noted, V =(V +0.5V) or 2.3V, whichever is greater, I =1mA, IN R OUT C =C =4.7µF (X7R Ceramic), T =+25°C. Boldface type applies for junction temperatures, T (Note7), of -40°C to +125°C. IN OUT A J Parameters Sym. Min. Typ. Max. Units Conditions Power Good Characteristics Input Voltage Operating Range V 1.0 — 6.0 V T =+25°C PWRGD_VIN A for Valid PWRGD 1.2 — 6.0 T =-40°C to +125°C A I =100µA SINK PWRGD Threshold Voltage PWRGD_THF 88 92 96 % V <2.5V, Falling Edge OUT (Referenced to V ) OUT 89 92 95 % V >2.5V, Falling Edge OUT PWRGD_THR 89 94 98 % V <2.5V, Rising Edge OUT 90 93 96 % V >2.5V, Rising Edge OUT PWRGD Output Voltage Low V — 0.2 0.4 V I =1.2mA PWRGD_L PWRGD SINK PWRGD Leakage P — 0.1 — µA V =V =6.0V WRGD_LK PWRGD IN PWRGD Time Delay T — 200 — µs C =OPEN PG DELAY 10 30 55 ms C =0.01µF DELAY — 300 — ms C =0.1µF DELAY Detect Threshold to PWRGD T — 170 — µs VDET-PWRGD Active Time Delay Shutdown Input Logic-High Input V 45 — — %V V =2.3V to 6.0V SHDN-HIGH IN IN Logic-Low Input V — — 15 %V V =2.3V to 6.0V SHDN-LOW IN IN SHDN Input Leakage Current SHDN -0.1 ±0.001 +0.1 µA V =6V, SHDN=V , ILK IN IN SHDN=GND AC Performance Output Delay from SHDN T 100 µs SHDN=GND to V OR IN V =GND to 95% V OUT R Output Noise e — 2.0 — µV/Hz I =200mA, f=1kHz, N OUT C =1µF (X7R Ceramic), OUT V =2.5V OUT Power Supply Ripple Rejection PSRR — 54 — dB f=100Hz, C =10µF, OUT Ratio I =100mA, OUT V =30mV pk-pk, INAC C =0µF IN Thermal Shutdown Temperature T — 150 — °C I =100µA, SD OUT V =1.8V, V =2.8V OUT IN Thermal Shutdown Hysteresis T — 10 — °C I =100µA, SD OUT V =1.8V, V =2.8V OUT IN Note 1: The minimum V must meet two conditions: V 2.3V and V V +2.5%V . IN IN IN R DROPOUT 2: V is the nominal regulator output voltage for the fixed cases. V =1.2V, 1.8V, etc. V is the desired set point output R R R voltage for the adjustable cases. V =V x((R /R )+1). See Figure4-1. R ADJ 1 2 3: TCV =(V –V )x106/(V xTemperature). V is the highest voltage measured over the OUT OUT-HIGH OUT-LOW R OUT-HIGH temperature range. V is the lowest voltage measured over the temperature range. OUT-LOW 4: Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is tested over a load range from 1mA to the maximum specified output current. 5: Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its nominal value that was measured with an input voltage of V =V +0.5V. IN R 6: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air. (i.e., T , T ,  ). Exceeding the maximum allowable power A J JA dissipation will cause the device operating junction temperature to exceed the maximum 150°C rating. Sustained junction temperatures above 125°C can impact device reliability. 7: The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the desired junction temperature. The test time is small enough such that the rise in the junction temperature over the ambient temperature is not significant.  2005-2014 Microchip Technology Inc. DS20001936D-page 5

MCP1726 TEMPERATURE SPECIFICATIONS Electrical Specifications: Unless otherwise indicated, all limits apply for V =2.3V to 6.0V. IN Parameters Sym. Min. Typ. Max. Units Conditions Temperature Ranges Operating Junction Temperature Range T -40 — +125 °C Steady State J Maximum Junction Temperature T — — +150 °C Transient J Storage Temperature Range T -65 — +150 °C A Thermal Package Resistances Thermal Resistance, 8L 3x3 DFN  — 64 — °C/W 4-Layer JC51-5 JA Standard Board with Vias  — 12 — JC Thermal Resistance, 8L SOIC  — 163 — °C/W 4-Layer JC51-7 JA Standard Board  — 42 — JC DS20001936D-page 6  2005-2014 Microchip Technology Inc.

MCP1726 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, V =V +0.5V, I =1mA and T =+25°C. IN OUT OUT A 180 0.05 Quiescent Current (µA) 111111112345670000000 VIORU T= = 1 0.2 +mV1 2A(A5°dCj.+)25°C -40ºC Line Regulation (%/V) -00000.....00000112340 IOUT = I5O0U0T m= 1AI0O0UI TOm U=TA 1=A 1 mA VINV R= =2 .13.V2 Vto ( A6.d0jV.) 100 -0.02 2.3 2.8 3.3 3.8 4.3 4.8 5.3 5.8 40 25 10 5 20 35 50 65 80 95 10 25 - - - 1 1 Input Voltage (V) Temperature (°C) FIGURE 2-1: Quiescent Current vs. Input FIGURE 2-4: Line Regulation vs. Voltage (1.2V Adjustable). Temperature (1.2V Adjustable). 300 0.70 280 VR = 1.2V (Adj.) VR = 5.0V Current (µA)222202460000 VIN = 3.3V gulation (%) 000...456000 VR = 1.8V VR = 3.3V und 180 VIN = 2.5V d Re 0.30 VR = 0.8V Gro114600 Loa 0.20 VIN = VR + 0.6V (or 2.3V) IOUT = 1 mA to 1A 120 0.10 0 200 400 600 800 1000 0 5 0 5 0 5 0 5 0 5 0 5 4 2 1 2 3 5 6 8 9 1 2 - - - 1 1 Load Current (mA) Temperature (°C) FIGURE 2-2: Ground Current vs. Load FIGURE 2-5: Load Regulation vs. Current (1.2V Adjustable). Temperature. 160 411.00 µA) 150 VIORU T= = 1 0.2 mV A(Adj.) mV) 410.50 IOUT = 1 mA ent Current ( 111234000 VIN = 5.0VVIN = 2.5V VIN = 3.3V Pin Voltage ( 440190..5000 VIN = 6.0V VIN = 2.3V sc st uie 110 dju 409.00 Q A 100 408.50 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 4 2 1 2 3 5 6 8 9 1 2 4 2 1 2 3 5 6 8 9 1 2 - - - 1 1 - - - 1 1 Temperature (°C) Temperature (°C) FIGURE 2-3: Quiescent Current vs. FIGURE 2-6: Adjust Pin Voltage vs. Junction Temperature (1.2V Adjustable). Temperature.  2005-2014 Microchip Technology Inc. DS20001936D-page 7

MCP1726 Note: Unless otherwise indicated, V =V +0.5V, I =1mA and T =+25°C. IN OUT OUT A 250 180 oltage (mV) 111222570250505 Adjustable VersiVonOUT = 5.0V Current (µA) 111145670000 VIOOUUTT = = 0 0 m.8AV +12+59°0C°C ut V 100 VOUT = 2.5V ent 130 +25°C Dropo 5705 Quiesc 111200 -40°C 25 100 0 3 6 9 2 5 8 1 4 7 0 3 6 9 0 200 400 600 800 1000 2. 2. 2. 3. 3. 3. 4. 4. 4. 5. 5. 5. 5. Output Current (mA) Input Voltage (V) FIGURE 2-7: Dropout Voltage vs. Output FIGURE 2-10: Quiescent Current vs. Input Current (Adjustable Version). Voltage (0.8V Fixed). 270 800 V) 260 AIOdUTju =s t1aAble Version A) 700 VIOOUUTT = = 03 .m3VA opout Voltage (m 222221234500000 VOUT V=O 5UT.0 =V2.5V VOUT = 3.3V escent Current (µ 234560000000000 +125°+C25°C Dr 200 Qui 100 -40°C 190 0 0 5 0 5 0 5 0 5 0 5 0 5 -4 -2 -1 2 3 5 6 8 9 11 12 2.3 2.62.9 3.23.53.84.14.44.75.05.35.65.9 Temperature (°C) Input Voltage (V) FIGURE 2-8: Dropout Voltage vs. FIGURE 2-11: Quiescent Current vs. Input Temperature (Adjustable Version). Voltage (3.3V Fixed). ms) 32 332400 VIN = 2.3V for 0.8V device e Delay ( 2380 VIN =2.3V VIN =3.0V ent (µA) 223680000 er Good Tim 222246 VIN =5.5V Ground Curr 112226802400000 VOUT =3.3VVOUT =0.8V ow CDELAY = 10 nF 140 P 20 120 0 5 0 5 0 5 0 5 0 5 0 5 4 2 1 2 3 5 6 8 9 1 2 0 200 400 600 800 1000 - - - 1 1 Temperature (°C) Load Current (mA) FIGURE 2-9: Power Good (PWRGD) FIGURE 2-12: Ground Current vs. Load Time Delay vs. Temperature. Current. DS20001936D-page 8  2005-2014 Microchip Technology Inc.

MCP1726 Note: Unless otherwise indicated, V =V +0.5V, I =1mA and T =+25°C. IN OUT OUT A 170 0.025 IOUT = 0 mA VOUT = 3.3V µA) 160 VIN = 2.3V for 0.8V Device V) 0.02 IOUT =1A Current ( 114500 VOUT =3.3V ation (%/ 0.00.1051 IOUT =50I0O UmT A=100 mA escent 112300 VOUT =0.8V e Regul 0.0050 Qui 110 Lin -0.005 IOUT =1 mA 100 0 5 0 5 0 5 0 5 0 5 0 5 -0.01 -4 -2 -1 2 3 5 6 8 9 11 12 40 25 10 5 20 35 50 65 80 95 10 25 - - - 1 1 Temperature (°C) Temperature (°C) FIGURE 2-13: Quiescent Current vs. FIGURE 2-16: Line Regulation vs. Temperature. Temperature (3.3V Fixed). 100 0.60 90 0.55 80 %) 0.50 VOUT =1.8V 70 n ( 0.45 nA) 60 VIN =6.0V atio 0.40 VOUT =0.8V (SHDN 4500 VIN =3.3V Regul 00..3305 VOUT =1.2V I 30 VIN =2.3V ad 0.25 20 o 0.20 L IOUT = 1 mA to 1000 mA 10 0.15 VIN = 2.3V 0 0.10 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 4 2 1 2 3 5 6 8 9 1 2 4 2 1 2 3 5 6 8 9 1 2 - - - 1 1 - - - 1 1 Temperature (°C) Temperature (°C) FIGURE 2-14: I vs. Temperature. FIGURE 2-17: Load Regulation vs. SHDN Temperature (V <2.5V Fixed). OUT 0.015 -0.20 V) 0.01 IOUT =1.0A %) --00..3205 egulation (%/ -00-..000.0005510 IOUT =500 mA IOUT =10 mA Regulation ( ----0000....54430505 VOUT =5.0V VOUT =3.3V VOUT =2.5V Line R -0-.00.1052 IOUT =100 mA VOUT = 0.8V Load ----0000....76650505 IVOIUNT = = V 1O UmTA + t0o. 61V0 00 mA -0.025 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 4 2 1 2 3 5 6 8 9 1 2 4 2 1 2 3 5 6 8 9 1 2 - - - 1 1 - - - 1 1 Temperature (°C) Temperature (°C) FIGURE 2-15: Line Regulation vs. FIGURE 2-18: Load Regulation vs. Temperature (0.8V Fixed). Temperature (V 2.5V Fixed). OUT  2005-2014 Microchip Technology Inc. DS20001936D-page 9

MCP1726 Note: Unless otherwise indicated, V =V +0.5V, I =1mA and T =+25°C. IN OUT OUT A 250 10 225 VOUT =2.5V (Adj) mV) 200 IOUT = 200 mA e ( 175 Hz) 1 pout Voltag 11170255050 VOUT =5.0V VOUT =2.5V Noise (µV(cid:151) 0.1 VIOOUUTT = = 100.80V m (FAixed) Dro 50 COUT =1 µF 25 C = 10 µF IN 0 0.01 0 200 400 600 800 1000 0.01 0.1 1 10 100 1000 Load Current (mA) Frequency (kHz) FIGURE 2-19: Dropout Voltage vs. Load FIGURE 2-22: Output Noise Voltage Current. Density vs. Frequency. 270 80 V) 260 IOUT = 1A 70 VOVUINT == 12..25VV m 250 60 Voltage ( 222234000 VOUT =5.0V R (dB) 4500 out 210 VOUT =3.3V PSR 30 Drop 129000 VOUT =2.5V 1200 CCOINU =T =01 µ0F µF 180 0 IOUT = 100 mA 0 5 0 5 0 5 0 5 0 5 0 5 4 2 1 2 3 5 6 8 9 1 2 0.01 0.1 1 10 100 1000 - - - 1 1 Temperature (°C) Frequency (kHz) FIGURE 2-20: Dropout Voltage vs. FIGURE 2-23: Power Supply Ripple Temperature. Rejection (PSRR) vs. Frequency (V =1.2V OUT Adjustable). 1.7 90 ent (A) 11..56 7800 VOVUINT == 12..25VV Circuit Curr 111...234 PSRR (dB) 34560000 ort 20 COUT =22 µF Sh 11..01 VOUT =1.2V (Fixed) 100 CIOIUNT == 01 0µ0F mA 2.3 2.6 2.9 3.2 3.5 3.8 4.1 4.4 4.7 5.0 5.3 5.6 5.9 0.01 0.1 1 10 100 1000 Input Voltage (V) Frequency (kHz) FIGURE 2-21: Short-Circuit Current vs. FIGURE 2-24: Power Supply Ripple Input Voltage. Rejection (PSRR) vs. Frequency (V =1.2V OUT Adjustable). DS20001936D-page 10  2005-2014 Microchip Technology Inc.

MCP1726 Note: Unless otherwise indicated, V =V +0.5V, I =1mA and T =+25°C. IN OUT OUT A 80 VOUT = 2.5V 70 VIN = 3.3V 60 R (dB) 4500 VOUT PWRGD R S 30 P 20 COUT =10 µF 10 CIN = 0 µF SHDN IOUT = 100 mA 0 0.01 0.1 1 10 100 1000 Frequency (kHz) FIGURE 2-25: Power Supply Ripple FIGURE 2-28: 2.5V (Adjustable) Start-Up Rejection (PSRR) vs. Frequency (V =2.5V from Shutdown. OUT Fixed). 80 VOUT = 2.5V 70 VIN = 3.3V 60 V OUT B) 50 d R ( 40 PWRGD R S 30 P 20 COUT =22 µF 10 CIOIUNT == 0 1 0µ0F mA VIN 0 0.01 0.1 1 10 100 1000 Frequency (kHz) FIGURE 2-26: Power Supply Ripple FIGURE 2-29: Power Good (PWRGD) Rejection (PSRR) vs. Frequency (V =2.5V Timing with C of 1000pF. OUT BYPASS Fixed). V OUT V OUT PWRGD PWRGD V V IN IN FIGURE 2-27: 2.5V (Adjustable) Start-Up FIGURE 2-30: Power Good (PWRGD) from VIN. Timing with CBYPASS of 0.01µF.  2005-2014 Microchip Technology Inc. DS20001936D-page 11

MCP1726 Note: Unless otherwise indicated, V =V +0.5V, I =1mA and T =+25°C. IN OUT OUT A 3.3V V V OUT IN 2.3V C = 47µF IN C = 10µF OUT VOUT IOUT C = 1µF IN V C = 10µF IN OUT I = 100mA OUT FIGURE 2-31: Dynamic Line Response FIGURE 2-33: Dynamic Load Response (1.2V Fixed). (2.5V Fixed, 10mA to 1000mA). 4.5V V OUT V 3.5V IN C = 47µF IN C = 10µF OUT VOUT IOUT C = 1µF IN V C = 10µF IN OUT I = 100mA OUT FIGURE 2-32: Dynamic Line Response FIGURE 2-34: Dynamic Load Response (2.5V Fixed). (2.5V Fixed, 100mA to 1000mA). DS20001936D-page 12  2005-2014 Microchip Technology Inc.

MCP1726 3.0 PIN DESCRIPTION The descriptions of the pins are listed in Table3-1. TABLE 3-1: PIN FUNCTION TABLE Fixed Output Adjustable Output Name Description 3x3 DFN SOIC 3x3 DFN SOIC 1 1 1 1 V Input Voltage Supply IN 2 2 2 2 V Input Voltage Supply IN 3 3 3 3 SHDN Shutdown Control Input (active-low) 4 4 4 4 GND Ground 5 5 5 5 PWRGD Power Good Output 6 6 6 6 C Power Good Delay Set-Point Input DELAY — — 7 7 ADJ Output Voltage Sense Input (adjustable version) 7 7 — — V Regulated Output Voltage OUT 8 8 8 8 V Regulated Output Voltage OUT 9 — 9 — EP Exposed Pad 3.1 Input Voltage Supply (V ) 3.5 Power Good Delay Set-Point Input IN (C ) Connect the unregulated or regulated input voltage DELAY source to V . If the input voltage source is located IN The C input sets the power-up delay time for the DELAY several inches away from the LDO or the input source PWRGD output. By connecting an external capacitor is a battery, it is recommended that an input capacitor from the C pin to ground, the delay times for the DELAY be used. A typical input capacitance value of 1µF to PWRGD output can be adjusted from 200µs (no 10µF should be sufficient for most applications. capacitance) to 300ms (0.1µF capacitor). This allows 3.2 Shutdown Control Input (SHDN) for the optimal setting of the system reset time. The SHDN input is used to turn the LDO output voltage 3.6 Output Voltage Sense Input (ADJ) on and off. When the SHDN input is at a logic-high level, the LDO output voltage is enabled. When the The output voltage adjust pin (ADJ) for the adjustable output voltage version of the MCP1726 allows the user SHDN input is pulled to a logic-low level, the LDO output voltage is disabled. When the SHDN input is to set the output voltage of the LDO by using two pulled low, the PWRGD output also goes low and the external resistors. The adjust pin voltage is 0.41V LDO enters a low quiescent current shutdown state (typical). where the typical quiescent current is 0.1µA. 3.7 Regulated Output Voltage (V ) OUT 3.3 Ground (GND) The V pin(s) is the regulated output voltage of the OUT Connect the GND pin of the LDO to a quiet circuit LDO. A minimum output capacitance of 1.0µF is ground. This will help the LDO power supply rejection required for LDO stability. The MCP1726 is stable with ratio and noise performance. The ground pin of the ceramic, tantalum and aluminum-electrolytic LDO only conducts the quiescent current of the LDO capacitors. See Section4.3 “Output Capacitor” for (typically 140µA), so a heavy trace is not required. output capacitor selection guidance. 3.4 Power Good Output (PWRGD) 3.8 Exposed Pad (EP) The PWRGD output is an open-drain output used to The 3x3 DFN package has an exposed pad on the indicate when the LDO output voltage is within 92% bottom of the package. This pad should be soldered to (typically) of its nominal regulation value. The PWRGD the Printed Circuit Board (PCB) to aid in the removal of output has a typical hysteresis value of 2% for the heat from the package during operation. The exposed adjustable voltage version and for voltage outputs less pad is at the ground potential of the LDO. than 2.5V. For fixed output voltage versions greater than 2.5V, the hysteresis is 0.7%. The PWRGD output is delayed on power-up by 200µs (typical, no capacitance on the C pin). This delay time is DELAY controlled by the C pin. DELAY  2005-2014 Microchip Technology Inc. DS20001936D-page 13

MCP1726 4.0 DEVICE OVERVIEW 4.2 Output Current and Current Limiting The MCP1726 is a high output current, Low Dropout (LDO) voltage regulator with an adjustable delay The MCP1726 LDO is tested and ensured to supply a power-good output and shutdown control input. The minimum of 1A of output current. The MCP1726 has no low dropout voltage of 220mV at 1A of current makes minimum output load, so the output load current can go it ideal for battery-powered applications. Unlike other to 0mA and the LDO will continue to regulate the high output current LDOs, the MCP1726 only draws output voltage to within tolerance. 220µA of quiescent current at full load. The MCP1726 also incorporates an output current limit. If the output voltage falls below 0.7V due to an overload 4.1 LDO Output Voltage condition (usually represents a shorted load condition), The MCP1726 LDO is available with either a fixed the output current is limited to 1.7A (typical). If the output voltage or an adjustable output voltage. The overload condition is a soft overload, the MCP1726 will allowable output voltage range is 0.8V to 5.5V for both supply higher load currents of up to 3A. The MCP1726 versions. should not be operated in this condition continuously as it may result in failure of the device. However, this does 4.1.1 ADJUSTABLE INPUT allow for device usage in applications that have higher pulsed load currents having an average output current The adjustable version of the MCP1726 uses the ADJ value of 1A or less. pin (pin 7) to get the output voltage feedback for output voltage regulation. This allows the user to set the Output overload conditions may also result in an output voltage of the device with two external resistors. overtemperature shutdown of the device. If the junction The nominal voltage for ADJ is 0.41V. temperature rises above 150°C, the LDO will shut down the output voltage. See Section4.9 Figure4-1 shows the adjustable version of the “Overtemperature Protection” for more information MCP1726. Resistors R and R form the resistor 1 2 on overtemperature shutdown. divider network necessary to set the output voltage. With this configuration, the equation for setting V is: OUT 4.3 Output Capacitor EQUATION 4-1: The MCP1726 requires a minimum output capacitance R +R of 1µF for output voltage stability. Ceramic capacitors V = V ----1--------------2- OUT ADJ R  are recommended because of their size, cost and 2 environmental robustness qualities. V = LDO Output Voltage OUT Aluminum-electrolytic and tantalum capacitors can be VADJ = ADJ Pin Voltage (typically 0.41V) used on the LDO output as well. The Equivalent Series Resistance (ESR) of the electrolytic output capacitor must be no greater than 2. The output capacitor MCP1726-ADJ should be located as close to the LDO output as is VIN VOUT practical. Ceramic materials X7R and X5R have low 4C.71µF 123 VSVIIHNNDN CDVEAOLDUAYJT 678 R1 1C2µF ta0ec8mc0ep5pe ctraaabptulaerc eiEt oSrc Rohe arfsfai cnaignee nE tsSre Rqa uonifrd e5 d0.a mrAe t.ywpeiclla l w1itµhFin Xt7hRe 4 GND PWRGD 5 On Larger LDO output capacitors can be used with the Off 1000pCF3 R2 MCP1726 to improve dynamic performance and power supply ripple rejection performance. A maximum of 22µF is recommended. Aluminum-electrolytic capacitors are not recommended for low-temperature FIGURE 4-1: Typical Adjustable Output applications of <-25°C. Voltage Application Circuit. The range of allowable resistance values for resistor R 2 is 10kΩ to 200kΩ. Solving the equation for R yields 1 the following equation: EQUATION 4-2: V –V  OUT ADJ R = R -------------------------------- 1 2 V  ADJ V = LDO Output Voltage OUT V = ADJ Pin Voltage (typically 0.41V) ADJ DS20001936D-page 14  2005-2014 Microchip Technology Inc.

MCP1726 4.4 Input Capacitor The power good output is an open-drain output that can be pulled up to any voltage that is equal to or less than Low input source impedance is necessary for the LDO the LDO input voltage. This output is capable of sinking output to operate properly. When operating from 1.2mA (V <0.4V maximum). PWRGD batteries or in applications with long lead length (>10 inches) between the input source and the LDO, some input capacitance is recommended. A minimum of 1.0µF to 4.7µF is recommended for most applications. VPWRGD_TH For applications that have output step load requirements, the input capacitance of the LDO is very VOUT important. The input capacitance provides the LDO TPG with a good local low-impedance source to pull the transient currents from in order to respond quickly to VOH the output load step. For good step response TVDET_PWRGD performance, the input capacitor should be of equivalent (or higher) value than the output capacitor. PWRGD The capacitor should be placed as close to the input of the LDO as is practical. Larger input capacitors will also VOL help reduce any high-frequency noise on the input and output of the LDO and reduce the effects of any inductance that exists between the input source FIGURE 4-2: Power Good Timing. voltage and the input capacitance of the LDO. 4.5 Power Good Output (PWRGD) The PWRGD output is used to indicate when the output VIN TOR voltage of the LDO is within 92% (typical value, see the DC Characteristics table for Min/Max specs) of its 70ms 30ms nominal regulation value. As the output voltage of the LDO rises, the PWRGD SHDN TPG output will be held low until the output voltage has exceeded the power good threshold plus the hysteresis value. Once this threshold has been exceeded, the power good time delay is started (shown as T in the PG DC Characteristics table). The power good time delay VOUT is adjustable via the C pin of the LDO (see DELAY Section4.6 “C Input”). By placing a capacitor DELAY from the C pin to ground, the power good time DELAY delay can be adjusted from 200µs (no capacitance) to PWRGD 300ms (0.1µF capacitor). After the time delay period, the PWRGD output will go high, indicating that the output voltage is stable and within regulation limits. FIGURE 4-3: Power Good Timing from If the output voltage of the LDO falls below the power Shutdown. good threshold, the power good output will transition low. The power good circuitry has a 170µs delay when detecting a falling output voltage, which helps to 4.6 CDELAY Input increase noise immunity of the power good output and The C input is used to provide the power-up delay avoid false triggering of the power good output during DELAY timing for the power good output, as discussed in the fast output transients. See Figure4-2 for power good previous section. By adding a capacitor from the timing characteristics. C pin to ground, the PWRGD power-up time DELAY When the LDO is put into Shutdown mode using the delay can be adjusted from 200µs (no capacitance on SHDN input, the power good output is pulled low C ) to 300ms (0.1µF of capacitance on C ). DELAY DELAY immediately, indicating that the output voltage will be See the DC Characteristics table for C timing DELAY out of regulation. The timing diagram for the power tolerances. good output when using the shutdown input is shown in Figure4-3.  2005-2014 Microchip Technology Inc. DS20001936D-page 15

MCP1726 Once the power good threshold (rising) has been reached, the CDELAY pin charges the external capacitor TOR to 1.5V (typical; this level can vary between 1.4V and 400ns (typical) 1.75V across the input voltage range of the part). The 70µs 30µs PWRGD output will transition high when the C pin DELAY voltage has charged to 0.42V. If the output falls below the power good threshold limit during the charging time SHDN between 0.0V and 0.42V on the C pin, the DELAY C pin voltage will be pulled to ground, thus DELAY resetting the timer. The C pin will be held low until DELAY the output voltage of the LDO has once again risen above the power good rising threshold. A timing VOUT diagram showing C , PWRGD and V is shown DELAY OUT in Figure4-4. FIGURE 4-5: Shutdown Input Timing Diagram. 4.8 Dropout Voltage and Undervoltage VOUT VPWRGD_TH Lockout Dropout voltage is defined as the input-to-output 1.5V (typical) voltage differential at which the output voltage drops TPG CDELAY 2% below the nominal value that was measured with a 0V CDELAY Threshold (0.42V) VR+0.5V differential applied. The MCP1726 LDO has a very low dropout voltage specification of 220mV (typical) at 1A of output current. See the DC Characteristics table for maximum dropout voltage specifications. The MCP1726 LDO operates across an input voltage PWRGD range of 2.3V to 6.0V and incorporates input Undervoltage Lockout (UVLO) circuitry that keeps the FIGURE 4-4: CDELAY and PWRGD Timing LDO output voltage off until the input voltage reaches a Diagram. minimum of 2.18V (typical) on the rising edge of the input voltage. As the input voltage falls, the LDO output 4.7 Shutdown Input (SHDN) will remain on until the input voltage level reaches 2.04V (typical). The SHDN input is an active-low input signal that turns the LDO on and off. The SHDN threshold is a percentage Since the MCP1726 LDO Undervoltage Lockout of the input voltage. The typical value of this shutdown activates at 2.04V as the input voltage is falling, the threshold is 30% of V , with minimum and maximum dropout voltage specification does not apply for output IN limits over the entire operating temperature range of 45% voltages that are less than 1.9V. and 15%, respectively. For high-current applications, voltage drops across the The SHDN input will ignore low-going pulses (pulses PCB traces must be taken into account. The trace meant to shut down the LDO) that are up to 400ns in resistances can cause significant voltage drops pulse width. If the shutdown input is pulled low for more between the input voltage source and the LDO. For than 400ns, the LDO will enter Shutdown mode. This applications with input voltages near 2.3V, these PCB small bit of filtering helps reject any system noise spikes trace voltage drops can sometimes lower the input on the shutdown input signal. voltage enough to trigger a shutdown due to On the rising edge of the SHDN input, the shutdown undervoltage lockout. circuitry has a 30µs delay before allowing the LDO output to turn on. This delay helps to reject any false turn-on signals or noise on the SHDN input signal. After the 30µs delay, the LDO output enters its soft-start period as it rises from 0V to its final regulation value. If the SHDN input signal is pulled low during the 30µs delay period, the timer will be reset and the delay time will start over again on the next rising edge of the SHDN input. The total time from the SHDN input going high (turn-on) to the LDO output being in regulation is typically 100µs. See Figure4-5 for a timing diagram of the SHDN input. DS20001936D-page 16  2005-2014 Microchip Technology Inc.

MCP1726 4.9 Overtemperature Protection The MCP1726 LDO has temperature-sensing circuitry to prevent the junction temperature from exceeding approximately 150°C. If the LDO junction temperature does reach 150°C, the LDO output will be turned off until the junction temperature cools to approximately 140°C, at which point the LDO output will automatically resume normal operation. If the internal power dissipation continues to be excessive, the device will shut off again. The junction temperature of the die is a function of power dissipation, ambient temperature and package thermal resistance. See Section5.0 “Application Circuits/Issues” for more information on LDO power dissipation and junction temperature.  2005-2014 Microchip Technology Inc. DS20001936D-page 17

MCP1726 5.0 APPLICATION CIRCUITS/ In addition to the LDO pass element power dissipation, ISSUES there is power dissipation within the MCP1726 as a result of quiescent or ground current. The power dissipation as a result of the ground current can be 5.1 Typical Application calculated using the following equation: The MCP1726 is used for applications that require high EQUATION 5-2: LDO output current and a power good output. P = V I IGND INMAX VIN MCP1726-2.5 P = Power dissipation due to the quiescent VIN=3.3V VOUT=2.5V @ 1A I(GND) 1 VIN VOUT 8 current of the LDO 1C01µF 23 SVHINDN CDVEOLUAYT 67 10Rk1 1C02µF VIN(MIAVXIN) == MCuarxriemnut mflo iwnpinugt ivno tlthaeg eVIN pin with no On 4 GND PWRGD 5 LDO output current (LDO quiescent Off C3 current) 1000pF The total power dissipated within the MCP1726 is the sum of the power dissipated in the LDO pass device and the P term. Because of the CMOS I(GND) PWRGD construction, the typical I for the MCP1726 is GND 140µA. Operating at a maximum of 3.63V results in a FIGURE 5-1: Typical Application Circuit. power dissipation of 0.51mW. For most applications, this is small compared to the LDO pass device power 5.1.1 APPLICATION CONDITIONS dissipation and can be neglected. The maximum continuous operating junction Package Type = 8-Lead 3x3 DFN temperature specified for the MCP1726 is +125°C. To Input Voltage Range = 3.3V±10% estimate the internal junction temperature of the V maximum = 3.63V MCP1726, the total internal power dissipation is IN V minimum = 2.97V multiplied by the thermal resistance from junction to IN ambient (R ) of the device. The thermal resistance V typical = 2.5V JA OUT from junction to ambient for the 3x3 DFN package is IOUT = 1.0A maximum estimated at 64°C/W. 5.2 Power Calculations EQUATION 5-3: 5.2.1 POWER DISSIPATION TJMAX = PTOTALRJA+TAMAX The internal power dissipation within the MCP1726 is a T = Maximum continuous junction function of input voltage, output voltage, output current J(MAX) temperature and quiescent current. The following equation can be used to calculate the internal power dissipation for the PTOTAL = Total device power dissipation LDO. R = Thermal resistance from JA junction-to-ambient EQUATION 5-1: T = Maximum ambient temperature A(MAX) P = V –V I LDO INMAX OUTMIN OUTMAX P = LDO Pass device internal power LDO dissipation V = Maximum input voltage IN(MAX) V = LDO minimum output voltage OUT(MIN) DS20001936D-page 18  2005-2014 Microchip Technology Inc.

MCP1726 The maximum power dissipation capability for a 5.3 Typical Application package can be calculated given the junction-to-ambient thermal resistance and the Internal power dissipation, junction temperature rise, maximum ambient temperature for the application. The junction temperature and maximum power dissipation following equation can be used to determine the are calculated in the following example. The power package maximum internal power dissipation. dissipation as a result of ground current is small enough to be neglected. EQUATION 5-4: 5.3.1 POWER DISSIPATION EXAMPLE T –T  P = -------J----M----A---X---------------A-----M----A---X------ DMAX R Package JA Package Type = 3x3 DFN P = Maximum device power dissipation D(MAX) Input Voltage T = Maximum continuous junction J(MAX) V = 3.3V±10% temperature IN LDO Output Voltage and Current T = Maximum ambient temperature A(MAX) V = 2.5V R = Thermal resistance from OUT JA junction-to-ambient IOUT = 1.0A Maximum Ambient Temperature EQUATION 5-5: TA(MAX) = 70°C T = P R Internal Power Dissipation JRISE DMAX JA P = [V –V ]xI LDO(MAX) IN(MAX) OUT(MIN) OUT(MAX) T = Rise in device junction temperature P = [(3.3Vx1.1)–(0.975x2.5V)] J(RISE) LDO over the ambient temperature x1.0A P = Maximum device power dissipation P = 1.192W D(MAX) LDO RJA = Thermal resistance from Device Junction Temperature Rise junction-to-ambient The internal junction temperature rise is a function of internal power dissipation and the thermal resistance EQUATION 5-6: from junction to ambient for the application. The TJ = TJRISE+TA thermal resistance from junction to ambient (RJA) is derived from an EIA/JEDEC standard for measuring thermal resistance for small surface-mount packages. T = Junction temperature J The EIA/JEDEC specification is JESD51-7 “High T = Rise in device junction temperature J(RISE) Effective Thermal Conductivity Test Board for Leaded over the ambient temperature Surface-Mount Packages”. The standard describes the TA = Ambient temperature test method and board specifications for measuring the thermal resistance from junction to ambient. The actual thermal resistance for a particular application can vary depending on many factors, such as copper area and thickness. Refer to AN792, “A Method to Determine How Much Power a SOT23 Can Dissipate in an Application” (DS00792), for more information regarding this subject. T = P xR J(RISE) TOTAL JA TJ(RISE) = 1.192Wx 64.0°C/W TJ(RISE) = 76.3°C  2005-2014 Microchip Technology Inc. DS20001936D-page 19

MCP1726 Junction Temperature Estimate To estimate the internal junction temperature, the calculated temperature rise is added to the ambient or offset temperature. For this example, the worst-case junction temperature is estimated below. T = T +T J JRISE A(MAX) T = 76.3°C+70.0°C J T = 146.3°C J As can be seen from the result, this application will be operating above the maximum operating junction temperature of 125°C. The PCB layout for this application is very important, as it has a significant impact on the junction-to-ambient thermal resistance (R ) of the 3x3 DFN package, which is very important JA in this application. Maximum Package Power Dissipation at 70°C Ambient Temperature 3x3 DFN (64°C/W R ) JA P = (125°C–70°C)/64°C/W D(MAX) P = 0.86W D(MAX) 8LD SOIC (163°C/W R ) JA P = (125°C–70°C)/163°C/W D(MAX) P = 0.337W D(MAX) From this table you can see the difference in maximum allowable power dissipation between the 3x3 DFN package and the 8-pin SOIC package. This difference is due to the exposed metal tab on the bottom of the DFN package. The exposed tab of the DFN package provides a very good thermal path from the die of the LDO to the PCB. The PCB then acts like a heat sink, providing more area to distribute the heat generated by the LDO. When the PCB heat sink area is used, the R should be replaced by R plus R , where JA JC HS R is the PCB copper area heat sink thermal HS resistance. This will allow for higher maximum power dissipation compared to the free-air power dissipation calculated using R . JA DS20001936D-page 20  2005-2014 Microchip Technology Inc.

MCP1726 6.0 PACKAGING INFORMATION 6.1 Package Marking Information 8-Lead DFN (3x3x0.9 mm) Example Voltage Code Option CAAA 0.8V CAAA E438 256 1.2V CAAB 1.8V CAAC 2.5V CAAD 3.0V CAAE 3.3V CAAF 5.0V CAAG Adj AADJ 8-Lead SOIC (3.90 mm) Example 1726ADJE SNe^3^1438 256 NNN Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC® designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2005-2014 Microchip Technology Inc. DS20001936D-page 21

MCP1726 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20001936D-page 22  2005-2014 Microchip Technology Inc.

MCP1726 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2005-2014 Microchip Technology Inc. DS20001936D-page 23

MCP1726 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20001936D-page 24  2005-2014 Microchip Technology Inc.

MCP1726 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2005-2014 Microchip Technology Inc. DS20001936D-page 25

MCP1726 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20001936D-page 26  2005-2014 Microchip Technology Inc.

MCP1726 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:10)(cid:8)(cid:17)(cid:18)(cid:12)(cid:10)(cid:13)(cid:19)(cid:5)(cid:8)(cid:20)(cid:15)(cid:21)(cid:22)(cid:8)(cid:23)(cid:8)(cid:21)(cid:6)(cid:24)(cid:24)(cid:25)(cid:26)(cid:27)(cid:8)(cid:28)(cid:29)(cid:30)(cid:31)(cid:8)(cid:16)(cid:16)(cid:8) (cid:25)(cid:7)!(cid:8)"(cid:15)(cid:17)#$% (cid:21)(cid:25)(cid:12)(cid:5)& (cid:30)(cid:10)(cid:9)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2)!(cid:10)"(cid:31)(cid:2)(cid:8)#(cid:9)(cid:9)(cid:14)(cid:15)(cid:31)(cid:2)(cid:12)(cid:28)(cid:8)$(cid:28)(cid:17)(cid:14)(cid:2)%(cid:9)(cid:28)&(cid:7)(cid:15)(cid:17)"’(cid:2)(cid:12)(cid:16)(cid:14)(cid:28)"(cid:14)(cid:2)"(cid:14)(cid:14)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)((cid:28)(cid:8)$(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7))(cid:7)(cid:8)(cid:28)(cid:31)(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)(cid:31)(cid:14)%(cid:2)(cid:28)(cid:31)(cid:2) (cid:11)(cid:31)(cid:31)(cid:12)*++&&&(cid:20)!(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)!+(cid:12)(cid:28)(cid:8)$(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)  2005-2014 Microchip Technology Inc. DS20001936D-page 27

MCP1726 NOTES: DS20001936D-page 28  2005-2014 Microchip Technology Inc.

MCP1726 APPENDIX A: REVISION HISTORY Revision D (September 2014) The following is the list of modifications: 1. Corrected the typical output voltage tolerance in the Features section to match the stated value in the DC Characteristics table. 2. Corrected illustrations of package markings in Section6.0, Packaging Information. 3. Minor typographical changes. Revision C (August 2007) The following is the list of modifications: 1. Added 3.0V option to Section6.1, Package Marking Information. 2. Updated package outline drawings. 3. Added 3.0V option to Product Identification System (PIS) section. Revision B (March 2005) The following is the list of modifications: 1. Replaced 3x3 DFN package diagram. 2. Emphasized (bolded) a few specifications of Section1.0, Electrical Characteristics in the DC Characteristics table. Revision A (February 2005) • Original Release of this Document.  2005-2014 Microchip Technology Inc. DS20001936D-page 29

MCP1726 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X -XXX X X XX Examples: a) MCP1726-0802E/MF: 0.80V, 1A LDO, 8LD Device Tape & Voltage Tolerance Temperature Package DFN Package Reel Output Range b) MCP1726T-1202E/MF:Tape and Reel, 1.20V, 1A LDO, 8LD Device: MCP1726: 1A, Low Quiescent Current LDO Regulator DFN Package c) MCP1726-3002E/MF: 3.00V, 1A LDO, 8LD Tape & Reel Option: T = Tape and Reel DFN Package Blank = Tube d) MCP1726T-3302E/MF:Tape and Reel, 3.30V, 1A LDO, 8LD Standard Output 080 = 0.80V DFN Package Voltage*: 120 = 1.20V e) MCP1726-1802E/SN: 1.80V, 1A LDO, 8LD 180 = 1.80V 250 = 2.50V SOIC Package 300 = 3.00V f) MCP1726T-2502E/SN:Tape and Reel, 330 = 3.30V 2.50V, 1A LDO, 8LD 500 = 5.00V SOIC Package ADJ = Adjustable Voltage Version g) MCP1726-5002E/SN: 5.00V, 1A LDO, 8LD * Custom output voltages available upon request. Contact your SOIC Package local Microchip sales office for more information. h) MCP1726T-ADJE/SN: Tape and Reel, Adjustable, 1A LDO, Tolerance: 2 = 2.0% 8LD SOIC Package Temperature E = -40 to +125C Note1: Tape and Reel identifier only appears in the Range: catalog part number description. This identi- fier is used for ordering purposes and is not printed on the device package. Check with Package*: SN = Plastic Small Outline – Narrow, 3.90mm Body, 8-Lead your Microchip Sales Office for package (SOIC) availability with the Tape and Reel option. MF = Plastic Dual Flat, No Lead Package – 3x3x0.9mm Body, 8-Lead (DFN) *Both packages are Lead Free DS20001936D-page 30  2005-2014 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, ensure that your application meets with your specifications. LANCheck, MediaLB, MOST, MOST logo, MPLAB, MICROCHIP MAKES NO REPRESENTATIONS OR OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, WARRANTIES OF ANY KIND WHETHER EXPRESS OR SST, SST Logo, SuperFlash and UNI/O are registered IMPLIED, WRITTEN OR ORAL, STATUTORY OR trademarks of Microchip Technology Incorporated in the OTHERWISE, RELATED TO THE INFORMATION, U.S.A. and other countries. INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR The Embedded Control Solutions Company and mTouch are FITNESS FOR PURPOSE. Microchip disclaims all liability registered trademarks of Microchip Technology Incorporated arising from this information and its use. Use of Microchip in the U.S.A. devices in life support and/or safety applications is entirely at Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, the buyer’s risk, and the buyer agrees to defend, indemnify and CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit hold harmless Microchip from any and all damages, claims, Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, suits, or expenses resulting from such use. No licenses are KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo, conveyed, implicitly or otherwise, under any Microchip MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code intellectual property rights. Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2005-2014, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-63276-576-5 QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures == ISO/TS 16949 == are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2005-2014 Microchip Technology Inc. DS20001936D-page 31

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: MCP1726-0802E/SN MCP1726-1802E/MF MCP1726-0802E/MF MCP1726-1802E/SN MCP1726T-1802E/SN MCP1726T-0802E/SN MCP1726T-2502E/MF MCP1726T-0802E/MF MCP1726T-1802E/MF MCP1726T-3302E/MF MCP1726T-5002E/MF MCP1726T-1202E/MF MCP1726T-3302E/SN MCP1726-2502E/MF MCP1726T-2502E/SN MCP1726T-1202E/SN MCP1726T-5002E/SN MCP1726-3302E/MF MCP1726-1202E/MF MCP1726-1202E/SN MCP1726-5002E/MF MCP1726-2502E/SN MCP1726-5002E/SN MCP1726-3302E/SN MCP1726-ADJE/MF MCP1726-ADJE/SN MCP1726T-ADJE/MF MCP1726T-ADJE/SN