Freescale Semiconductor Document Number: MCF5485EC Data Sheet Rev. 4, 12/2007 MCF548x ® MCF548x ColdFire Microprocessor TEPBGA–388 27mmx27mm Supports MCF5480, MCF5481, MCF5482, MCF5483, MCF5484, and MCF5485 Features list: endpoints, interrupt, bulk, or isochronous • ColdFire V4e Core – 4-Kbytes of shared endpoint FIFO RAM and 1 Kbyte – Limited superscalar V4 ColdFire processor core of endpoint descriptor RAM – Up to 200MHz peak internal core frequency (308 MIPS – Integrated physical layer interface [Dhrystone 2.1] @ 200 MHz) – Up to four programmable serial controllers (PSCs) each – Harvard architecture with separate 512-byte receive and transmit FIFOs for – 32-Kbyte instruction cache UART, USART, modem, codec, and IrDA 1.1 interfaces – 32-Kbyte data cache – I2C peripheral interface – Memory Management Unit (MMU) – Two FlexCAN controller area network 2.0B controllers – Separate, 32-entry, fully-associative instruction and each with 16 message buffers data translation lookahead buffers – DMA Serial Peripheral Interface (DSPI) – Floating point unit (FPU) • Optional Cryptography accelerator module – Double-precision conforms to IEE-754 standard – Execution units for: – Eight floating point registers – DES/3DES block cipher • Internal master bus (XLB) arbiter – AES block cipher – High performance split address and data transactions – RC4 stream cipher – Support for various parking modes – MD5/SHA-1/SHA-256/HMAC hashing • 32-bit double data rate (DDR) synchronous DRAM – Random Number Generator (SDRAM) controller • 32-Kbyte system SRAM – 66–133 MHz operation – Arbitration mechanism shares bandwidth between – Supports DDR and SDR DRAM internal bus masters – Built-in initialization and refresh • System integration unit (SIU) – Up to four chip selects enabling up to one GB of external – Interrupt controller memory – Watchdog timer • Version 2.2 peripheral component interconnect (PCI) bus – Two 32-bit slice timers alarm and interrupt generation – 32-bit target and initiator operation – Up to four 32-bit general-purpose timers, compare, and – Support for up to five external PCI masters PWM capability – 33–66 MHz operation with PCI bus to XLB divider – GPIO ports multiplexed with peripheral pins ratios of 1:1, 1:2, and 1:4 • Debug and test features • Flexible multi-function external bus (FlexBus) – ColdFire background debug mode (BDM) port – Provides a glueless interface to boot flash/ROM, – JTAG/ IEEE 1149.1 test access port SRAM, and peripheral devices • PLL and clock generator – Up to six chip selects – 30 to 66.67 MHz input frequency range – 33 – 66 MHz operation • Operating Voltages • Communications I/O subsystem – 1.5V internal logic – Intelligent 16 channel DMA controller – 2.5V DDR SDRAM bus I/O – Up to two 10/100 Mbps fast Ethernet controllers (FECs) – 3.3V PCI, FlexBus, and all other I/O each with separate 2-Kbyte receive and transmit FIFOs • Estimated power consumption – Universal serial bus (USB) version 2.0 device controller – Less than 1.5W (388 PBGA) – Support for one control and six programmable ©Freescale Semiconductor, Inc., 2007. All rights reserved.

Table of Contents 1 Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Figure15.DDR Clock Timing Diagram. . . . . . . . . . . . . . . . . . . . 18 2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Figure16.DDR Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.1 Operating Temperatures. . . . . . . . . . . . . . . . . . . . . . . . .4 Figure17.DDR Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Figure18.PCI Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Figure19.MII Receive Signal Timing Diagram. . . . . . . . . . . . . . 23 4 Hardware Design Considerations. . . . . . . . . . . . . . . . . . . . . . .6 Figure20.MII Transmit Signal Timing Diagram . . . . . . . . . . . . . 23 4.1 PLL Power Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Figure21.MII Async Inputs Timing Diagram . . . . . . . . . . . . . . . 24 4.2 Supply Voltage Sequencing and Separation Cautions . .6 Figure22.MII Serial Management Channel TIming Diagram. . . 24 4.3 General USB Layout Guidelines. . . . . . . . . . . . . . . . . . .8 Figure23.I2C Input/Output Timings. . . . . . . . . . . . . . . . . . . . . . 26 4.4 USB Power Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Figure24.Test Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . 27 5 Output Driver Capability and Loading. . . . . . . . . . . . . . . . . . .10 Figure25.Boundary Scan (JTAG) Timing . . . . . . . . . . . . . . . . . 27 6 PLL Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Figure26.Test Access Port Timing . . . . . . . . . . . . . . . . . . . . . . 27 7 Reset Timing Specifications. . . . . . . . . . . . . . . . . . . . . . . . . .12 Figure27.TRST Timing Debug AC Timing Specifications. . . . . 27 8 FlexBus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Figure28.Real-Time Trace AC Timing. . . . . . . . . . . . . . . . . . . . 28 8.1 FlexBus AC Timing Characteristics. . . . . . . . . . . . . . . .13 Figure29.BDM Serial Port AC Timing. . . . . . . . . . . . . . . . . . . . 28 9 SDRAM Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Figure30.DSPI Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.1 SDR SDRAM AC Timing Characteristics . . . . . . . . . . .15 Figure31.388-pin BGA Case Outline. . . . . . . . . . . . . . . . . . . . . 31 9.2 DDR SDRAM AC Timing Characteristics . . . . . . . . . . .18 List of Tables 10 PCI Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 11 Fast Ethernet AC Timing Specifications. . . . . . . . . . . . . . . . .22 Table1. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . 4 11.1 MII/7-WIRE Interface Timing Specs . . . . . . . . . . . . . . .22 Table2. Operating Temperatures . . . . . . . . . . . . . . . . . . . . . . . . 4 11.2 MII Transmit Signal Timing . . . . . . . . . . . . . . . . . . . . . .23 Table3. Thermal Resistance. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 11.3 MII Async Inputs Signal Timing (CRS, COL) . . . . . . . .24 Table4. DC Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . 5 11.4 MII Serial Management Channel Timing (MDIO,MDC).24 Table5. USB Filter Circuit Values. . . . . . . . . . . . . . . . . . . . . . . . 9 12 General Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . .25 Table6. I/O Driver Capability . . . . . . . . . . . . . . . . . . . . . . . . . . 10 13 I2C Input/Output Timing Specifications. . . . . . . . . . . . . . . . . .25 Table7. Clock Timing Specifications. . . . . . . . . . . . . . . . . . . . . 11 14 JTAG and Boundary Scan Timing. . . . . . . . . . . . . . . . . . . . . .26 Table8. MCF548x Divide Ratio Encodings. . . . . . . . . . . . . . . . 11 15 DSPI Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . .29 Table9. Reset Timing Specifications . . . . . . . . . . . . . . . . . . . . 12 16 Timer Module AC Timing Specifications. . . . . . . . . . . . . . . . .29 Table10.FlexBus AC Timing Specifications. . . . . . . . . . . . . . . . 13 17 Case Drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Table11.SDR Timing Specifications . . . . . . . . . . . . . . . . . . . . . 16 18 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Table12.DDR Clock Crossover Specifications . . . . . . . . . . . . . 18 Table13.DDR Timing Specifications . . . . . . . . . . . . . . . . . . . . . 18 List of Figures Table14.PCI Timing Specifications . . . . . . . . . . . . . . . . . . . . . . 21 Figure1.MCF548X Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 3 Table15.MII Receive Signal Timing. . . . . . . . . . . . . . . . . . . . . . 23 Figure2.System PLL V Power Filter. . . . . . . . . . . . . . . . . . . . 6 Table16.MII Transmit Signal Timing . . . . . . . . . . . . . . . . . . . . . 23 DD Figure3.Supply Voltage Sequencing and Separation Cautions . 7 Table17.MII Transmit Signal Timing . . . . . . . . . . . . . . . . . . . . . 24 Figure4.Preferred VBUS Connections. . . . . . . . . . . . . . . . . . . . 8 Table18.MII Serial Management Channel Signal Timing . . . . . 24 Figure5.Alternate VBUS Connections . . . . . . . . . . . . . . . . . . . . 8 Table19.General AC Timing Specifications. . . . . . . . . . . . . . . . 25 Figure6.USB V Power Filter. . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table20.I2C Input Timing Specifications between DD Figure7.USBRBIAS Connection. . . . . . . . . . . . . . . . . . . . . . . . 10 SCL and SDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure8.Input Clock Timing Diagram . . . . . . . . . . . . . . . . . . . . 11 Table21. I2C Output Timing Specifications between Figure9.CLKIN, Internal Bus, and Core Clock Ratios . . . . . . . 11 SCL and SDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure10.Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table22.JTAG and Boundary Scan Timing. . . . . . . . . . . . . . . . 26 Figure11.FlexBus Read Timing . . . . . . . . . . . . . . . . . . . . . . . . 14 Table23.Debug AC Timing Specifications. . . . . . . . . . . . . . . . . 28 Figure12.FlexBus Write Timing . . . . . . . . . . . . . . . . . . . . . . . . 15 Table24.DSPI Modules AC Timing Specifications. . . . . . . . . . . 29 Figure13.SDR Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table25.Timer Module AC Timing Specifications . . . . . . . . . . . 29 Figure14.SDR Read Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 17 MCF548x ColdFire® Microprocessor, Rev. 4 2 Freescale Semiconductor

DDR SDRAM FlexBus ColdFire V4e Core PLL Interface Interface FPU, MMU EMAC 32K D-cache XL Bus Memory FlexBus 32K I-Cache Arbiter Controller Controller XL Bus s Unit Interrupt Master/Slave ort emon Controller Interface & P SystIntegrati WaTticmhedrog CArcycpetloegraratoprh**y* CPonCtIr 2o.l2ler erface nt Slice pto W O I rts Timers x 2 Cry R/ CI I/ Po GP 32K System XL Bus P & Timers x 4 SRAM Read/Write e ve s erfac Sla Bu DMA Read DMA Write nt O I FlexCAN Multi-Channel DMA PCI Interface Perpheral I/ x 2 Master Bus Interface C&o FmIFmOBsus & FIFOs I/O SubsysCommunica USB 2.0 temtion DSPI I2C PSC x 4 FEC1 FEC2** s DEVICE* USB 2.0 Perpheral Communications I/O Interface & Ports PHY* Figure1. MCF548X Block Diagram MCF548x ColdFire® Microprocessor, Rev. 4 Freescale Semiconductor 3

Maximum Ratings 1 Maximum Ratings Table1 lists maximum and minimum ratings for supply and operating voltages and storage temperature. Operating outside of these ranges may cause erratic behavior or damage to the processor. Table1. Absolute Maximum Ratings Rating Symbol Value Units External (I/O pads) supply voltage (3.3-V power pins) EV –0.3 to +4.0 V DD Internal logic supply voltage IV –0.5 to +2.0 V DD Memory (I/O pads) supply voltage (2.5-V power pins) SD V –0.3 to +4.0 SDR Memory V DD –0.3 to +2.8 DDR Memory PLL supply voltage PLL V –0.5 to +2.0 V DD Internal logic supply voltage, input voltage level V –0.5 to +3.6 V in Storage temperature range T –55 to +150 oC stg 2 Thermal Characteristics 2.1 Operating Temperatures Table2 lists junction and ambient operating temperatures. Table2. Operating Temperatures Characteristic Symbol Value Units Maximum operating junction temperature T 105 oC j Maximum operating ambient temperature T <851 oC Amax Minimum operating ambient temperature T –40 oC Amin 1 This published maximum operating ambient temperature should be used only as a system design guideline. All device operating parameters are guaranteed only when the junction temperature lies within the specified range. MCF548x ColdFire® Microprocessor, Rev. 4 4 Freescale Semiconductor

DC Electrical Specifications 2.2 Thermal Resistance Table3 lists thermal resistance values. Table3. Thermal Resistance Characteristic Symbol Value Unit 324 pin TEPBGA — Junction to ambient, natural Four layer board (2s2p) θ 20–221,2 °C/W JMA convection 388 pin TEPBGA — Junction to ambient, natural Four layer board (2s2p) θ 191,2 °C/W JMA convection Junction to ambient (@200 ft/min) Four layer board (2s2p) θ 161,2 °C/W JMA Junction to board — θ 113 °C/W JB Junction to case — θ 74 °C/W JC Junction to top of package Natural convection Ψ 21,5 °C/W jt 1 θ and Ψ parameters are simulated in accordance with EIA/JESD Standard 51-2 for natural convection. Freescale JA jt recommends the use of θ and power dissipation specifications in the system design to prevent device junction JA temperatures from exceeding the rated specification. System designers should be aware that device junction temperatures can be significantly influenced by board layout and surrounding devices. Conformance to the device junction temperature specification can be verified by physical measurement in the customer’s system using the Ψ jt parameter, the device power dissipation, and the method described in EIA/JESD Standard 51-2. 2 Per JEDEC JESD51-6 with the board horizontal. 3 Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 4 Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 5 Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. 3 DC Electrical Specifications Table4 lists DC electrical operating temperatures. This table is based on an operating voltage of EV =3.3 V ± 0.3 V DD DC DC and IV of 1.5 ± 0.07 V . DD DC Table4. DC Electrical Specifications Characteristic Symbol Min Max Units External (I/O pads) operation voltage range EV 3.0 3.6 V DD Memory (I/O pads) operation voltage range (DDR Memory) SD V 2.30 2.70 V DD Internal logic operation voltage range1 IV 1.43 1.58 V DD PLL Analog operation voltage range1 PLL V 1.43 1.58 V DD USB oscillator operation voltage range USB_OSV 3.0 3.6 V DD USB digital logic operation voltage range USBV 3.0 3.6 V DD USB PHY operation voltage range USB_PHYV 3.0 3.6 V DD USB oscillator analog operation voltage range USB_OSCAV 1.43 1.58 V DD MCF548x ColdFire® Microprocessor, Rev. 4 Freescale Semiconductor 5

Hardware Design Considerations Table4. DC Electrical Specifications (continued) Characteristic Symbol Min Max Units USB PLL operation voltage range USB_PLLV 1.43 1.58 V DD Input high voltage SSTL 3.3V/2.5V2 V V + 0.3 SD V + 0.3 V IH REF DD Input low voltage SSTL 3.3V/2.5V2 V V - 0.3 V - 0.3 V IL SS REF Input high voltage 3.3V I/O pins V 0.7 x EV EV + 0.3 V IH DD DD Input low voltage 3.3V I/O pins V V - 0.3 0.35 x EV V IL SS DD Output high voltage I =8 mA, 16 mA,24 mA V 2.4 — V OH OH Output low voltage I =8 mA, 16 mA,24 mA5 V — 0.5 V OL OL Capacitance 3, V =0 V, f=1 MHz C — TBD pF in IN Input leakage current I –1.0 1.0 μA in 1 IV and PLL V should be at the same voltage. PLL V should have a filtered input. Please see Figure2 for an DD DD DD example circuit. There are three PLL V inputs. A filter circuit should used on each PLL V input. DD DD 2 This specification is guaranteed by design and is not 100% tested. 3 Capacitance C is periodically sampled rather than 100% tested. IN 4 Hardware Design Considerations 4.1 PLL Power Filtering To further enhance noise isolation, an external filter is strongly recommended for PLL analog V pins. The filter shown in DD Figure2 should be connected between the board V and the PLL V pins. The resistor and capacitors should be placed as DD DD close to the dedicated PLL V pin as possible. DD 10 Ω Board V PLL V Pin DD DD 10 µF 0.1 µF GND Figure2. System PLL V Power Filter DD 4.2 Supply Voltage Sequencing and Separation Cautions Figure3 shows situations in sequencing the I/O V (EV ), SDRAM V (SD V ), PLL V (PLL V ), and Core V DD DD DD DD DD DD DD (IV ). DD MCF548x ColdFire® Microprocessor, Rev. 4 6 Freescale Semiconductor

Hardware Design Considerations 3.3V EVDD, SD VDD (3.3V) e g Supplies Stable a olt 2.5V SD V (2.5V) V DD y pl p u er S 1.5V 1 IVDD, PLL VDD w o P C D 2 0 Time NOTES: 1. IVDD should not exceed EVDD or SD VDD by more than 0.4V at any time, including power-up. 2. Recommended that IVDD/PLL VDD should track EVDD/SD VDD up to 0.9V, then separate for completion of ramps. 3. Input voltage must not be greater than the supply voltage (EVDD, SD VDD, IVDD, or PLL VDD) by more than 0.5V at any time, including during power-up. 4. Use 1 microsecond or slower rise time for all supplies. Figure3. Supply Voltage Sequencing and Separation Cautions The relationship between SD V and EV is non-critical during power-up and power-down sequences. SD V (2.5V or DD DD DD 3.3V) and EV are specified relative to IV . DD DD 4.2.1 Power Up Sequence If EV /SD V are powered up with the IV at 0V, the sense circuits in the I/O pads cause all pad output drivers connected DD DD DD to the EV /SD V to be in a high impedance state. There is no limit to how long after EV /SD V powers up before IV DD DD DD DD DD must power up. IV should not lead the EV , SD V , or PLL V by more than 0.4V during power ramp up or there is DD DD DD DD high current in the internal ESD protection diodes. The rise times on the power supplies should be slower than 1 microsecond to avoid turning on the internal ESD protection clamp diodes. The recommended power up sequence is as follows: 1. Use 1 microsecond or slower rise time for all supplies. 2. IV /PLL V and EV /SD V should track up to 0.9V, then separate for the completion of ramps with EV /SD DD DD DD DD DD V going to the higher external voltages. One way to accomplish this is to use a low drop-out voltage regulator. DD 4.2.2 Power Down Sequence If IV PLL V are powered down first, sense circuits in the I/O pads cause all output drivers to be in a high impedance state. DD DD There is no limit on how long after IV and PLL V power down before EV or SD V must power down. IV should DD DD DD DD DD not lag EV , SD V , or PLL V going low by more than 0.4V during power down or there is undesired high current in the DD DD DD ESD protection diodes. There are no requirements for the fall times of the power supplies. The recommended power down sequence is as follows: 1. Drop IV /PLL V to 0V DD DD 2. Drop EV /SD V supplies DD DD MCF548x ColdFire® Microprocessor, Rev. 4 Freescale Semiconductor 7

Hardware Design Considerations 4.3 General USB Layout Guidelines 4.3.1 USB D+ and D- High-Speed Traces 1. High speed clock and the USBD+ and USBD- differential pair should be routed first. 2. Route USBD+ and USBD- signals on the top layer of the board. 3. The trace width and spacing of the USBD+ and USBD- signals should be such that the differential impedance is 90Ω. 4. Route traces over continuous planes (power and ground)—they should not pass over any power/ground plane slots or anti-etch. When placing connectors, make sure the ground plane clear-outs around each pin have ground continuity between all pins. 5. Maintain the parallelism (skew matched) between USBD+ and USBD-. These traces should be the same overall length. 6. Do not route USBD+ and USBD- traces under oscillators or parallel to clock traces and/or data buses. Minimize the lengths of high speed signals that run parallel to the USBD+ and USBD- pair. Maintain a minimum 50mil spacing to clock signals. 7. Keep USBD+ and USBD- traces as short as possible. 8. Route USBD+, USBD-, and USBVBUS signals with a minimum amount of vias and corners. Use 45° turns. 9. Stubs should be avoided as much as possible. If they cannot be avoided, stubs should be no greater than 200mils. 4.3.2 USB VBUS Traces Connecting the USBVBUS pin directly to the 5V VBUS signal from the USB connector can cause long-term reliability problems in the ESD network of the processor. Therefore, use of an external voltage divider for VBUS is recommended. Figure4 and Figure5 depict possible connections for VBUS. Point A, marked in each figure, is where a 5V version of VBUS should connect. Point B, marked in each figure, is where a 3.3V version of VBUS should connect to the USBVBUS pin on the device. MCF548x (5V) (3.3V) A 8.2k B 50k 20k 50k Figure4. Preferred VBUS Connections MCF548x (5V) (3.3V) A 50k B 50k 50k Figure5. Alternate VBUS Connections 4.3.3 USB Receptacle Connections It is recommended to connect the shield and the ground pin of the B USB receptacle for upstream ports to the board ground plane. The ground pin of the A USB receptacles for downstream ports should also be connected to the board ground plane, but industry practice varies widely on the connection of the shield of the A USB receptacles to other system grounds. Take precautions for control of ground loops between hosts and self-powered USB devices through the cable shield. MCF548x ColdFire® Microprocessor, Rev. 4 8 Freescale Semiconductor

Hardware Design Considerations 4.4 USB Power Filtering To minimize noise, an external filter is required for each of the USB power pins. The filter shown in Figure6 should be connected between the board EV or IV and each of the USB V pins. DD DD DD • The resistor and capacitors should be placed as close to the dedicated USB V pin as possible. DD • A separate filter circuit should be included for each USB V pin, a total of five circuits. DD • All traces should be as low impedance as possible, especially ground pins to the ground plane. • The filter for USB_PHYVDD to VSS should be connected to the power and ground planes, respectively, not fingers of the planes. • In addition to keeping the filter components for the USB_PLLVDD as close as practical to the body of the processor as previously mentioned, special care should be taken to avoid coupling switching power supply noise or digital switching noise onto the portion of that supply between the filter and the processor. • The capacitors for C2 in the table below should be rated X5R or better due to temperature performance. R1 Board EV /IV USB V Pin DD DD DD C1 C2 GND Figure6. USB V Power Filter DD NOTE In addition to the above filter circuitry, a 0.01 F capacitor is also recommended in parallel with those shown. Table5 lists the resistor values and supply voltages to be used in the circuit for each of the USB V pins. DD Table5. USB Filter Circuit Values USB V Pin Nominal Voltage R1 (Ω) C1 (μF) C2 (μF) DD USBVDD 3.3V 10 10 0.1 (Bias generator supply) USB_PHYVDD 3.3V 0 10 0.1 (Main transceiver supply) USB_PLLVDD 1.5V 10 1 0.1 (PLL supply) USB_OSCVDD 3.3V 0 10 0.1 (Oscillator supply) USB_OSCAVDD 1.5V 0 10 0.1 (Oscillator analog supply) MCF548x ColdFire® Microprocessor, Rev. 4 Freescale Semiconductor 9

Output Driver Capability and Loading 4.4.1 Bias Resistor The USBRBIAS resistor should be placed as close to the dedicated USB 2.0 pins as possible. The tolerance should be ±1%. USBRBIAS 9.1kΩ Figure7. USBRBIAS Connection 5 Output Driver Capability and Loading Table6 lists values for drive capability and output loading. Table6. I/O Driver Capability1 Drive Output Signal Capability Load (C ) L SDRAMC (SDADDR[12:0], SDDATA[31:0], RAS, CAS, SDDM[3:0], 24 mA 15 pF SDWE, SDBA[1:0] SDRAMC DQS and clocks (SDDQS[3:0], SDRDQS, SDCLK[1:0], 24 mA 15 pF SDCLK[1:0], SDCKE) SDRAMC chip selects (SDCS[3:0]) 24 mA 15 pF FlexBus (AD[31:0], FBCS[5:0], ALE, R/W, BE/BWE[3:0], OE) 16 mA 30 pF FEC (EnMDIO, EnMDC, EnTXEN, EnTXD[3:0], EnTXER 8 mA 15 pF Timer (TOUT[3:0]) 8 mA 50 pF FlexCAN (CANTX) 8 mA 30 pF DACK[1:0] 8 mA 30 pF PSC (PSCnTXD[3:0], PSCnRTS/PSCnFSYNC, 8 mA 30 pF DSPI (DSPISOUT, DSPICS0/SS, DSPICS[2:3], DSPICS5/PCSS) 24 mA 50 pF PCI (PCIAD[31:0], PCIBG[4:1], PCIBG0/PCIREQOUT, PCIDEVSEL, 16 mA 50 pF PCICXBE[3:0], PCIFRM, PCIPERR, PCIRESET, PCISERR, PCISTOP, PCIPAR, PCITRDY, PCIIRDY I2C (SCL, SDA) 8 mA 50 pF BDM (PSTCLK, PSTDDATA[7:0], DSO/TDO, 8 mA 25 pF RSTO 8 mA 50 pF 1 The device’s pads have balanced sink and source current. The drive capability is the same as the sink capability. MCF548x ColdFire® Microprocessor, Rev. 4 10 Freescale Semiconductor

PLL Timing Specifications 6 PLL Timing Specifications The specifications in Table7 are for the CLKIN pin. Table7. Clock Timing Specifications Num Characteristic Min Max Units C1 Cycle time 20 40 ns C2 Rise time (20% of Vdd to 80% of vdd) — 2 ns C3 Fall time (80% of Vdd to 20% of Vdd) — 2 ns C4 Duty cycle (at 50% of Vdd) 40 60 % C1 CLKIN C4 C4 C2 C3 Figure8. Input Clock Timing Diagram Table8 shows the supported PLL encodings. Table8. MCF548x Divide Ratio Encodings Internal XLB, SDRAM Bus, Clock CLKIN—PCI and FlexBus Core Frequency Range AD[12:8]1 and PSTCLK Frequency Ratio Frequency Range (MHz) (MHz) Range (MHz) 00011 1:2 41.67–50.0 83.33–100 166.66–200 00101 1:2 25.0–41.67 50.0–83.332 100.0–166.66 01111 1:4 25.0 100 200 1 All other values of AD[12:8] are reserved. 2 DDR memories typically have a minimum speed of 83MHz. Some vendors specifiy down to 75MHz. Check with the memory component specifications to verify. Figure9 correlates CLKIN, internal bus, and core clock frequencies for the 1x–4x multipliers. CLKIN Internal Clock Core Clock 2x 2x 25.0 50.0 50.0 100.0 100.0 200.0 4x 2x 25.0 100.0 200.0 25 40 50 60 70 30 40 50 60 70 80 90 100 60 70 80 90100110120130140150160170180190200 CLKIN (MHz) Internal Clock (MHz) Core Clock (MHz) Figure9. CLKIN, Internal Bus, and Core Clock Ratios MCF548x ColdFire® Microprocessor, Rev. 4 Freescale Semiconductor 11

Reset Timing Specifications 7 Reset Timing Specifications Table9 lists specifications for the reset timing parameters shown in Figure10 Table9. Reset Timing Specifications 50 MHz CLKIN Num Characteristic Units Min Max R11 Valid to CLKIN (setup) 8 — ns R2 CLKIN to invalid (hold) 1.0 — ns R3 RSTI to invalid (hold) 1.0 — ns RSTI pulse duration 5 — CLKIN cycles 1 RSTI and FlexBus data lines are synchronized internally. Setup and hold times must be met only if recognition on a particular clock is required. Figure10 shows reset timing for the values in Table9. CLKIN R1 RSTI R2 Mode Select FlexBus R1 R3 NOTE: Mode selects are registered on the rising clock edge before the cycle in which RSTI is recognized as being negated. Figure10. Reset Timing 8 FlexBus A multi-function external bus interface called FlexBus is provided on the MCF5482 with basic functionality to interface to slave-only devices up to a maximum bus frequency of 66 MHz. It can be directly connected to asynchronous or synchronous devices such as external boot ROMs, flash memories, gate-array logic, or other simple target (slave) devices with little or no additional circuitry. For asynchronous devices, a simple chip-select based interface can be used. The FlexBus interface has six general purpose chip-selects (FBCS[5:0]). Chip-select FBCS0 can be dedicated to boot ROM access and can be programmed to be byte (8 bits), word (16 bits), or longword (32 bits) wide. Control signal timing is compatible with common ROM / flash memories. MCF548x ColdFire® Microprocessor, Rev. 4 12 Freescale Semiconductor

FlexBus 8.1 FlexBus AC Timing Characteristics The following timing numbers indicate when data is latched or driven onto the external bus, relative to the system clock. Table10. FlexBus AC Timing Specifications Num Characteristic Min Max Unit Notes Frequency of Operation 25 50 Mhz 1 FB1 Clock Period (CLKIN) 20 40 ns 2 FB2 Address, Data, and Control Output Valid (AD[31:0], FBCS[5:0], — 7.0 ns 3 R/W, ALE, TSIZ[1:0], BE/BWE[3:0], OE, and TBST) FB3 Address, Data, and Control Output Hold ((AD[31:0], FBCS[5:0], 1 — ns 3, 4 R/W, ALE, TSIZ[1:0], BE/BWE[3:0], OE, and TBST) FB4 Data Input Setup 3.5 — ns FB5 Data Input Hold 0 — ns FB6 Transfer Acknowledge (TA) Input Setup 4 — ns FB7 Transfer Acknowledge (TA) Input Hold 0 — ns FB8 Address Output Valid (PCIAD[31:0]) — 7.0 ns 5 FB9 Address Output Hold (PCIAD[31:0]) 0 — ns 5 1 The frequency of operation is the same as the PCI frequency of operation. The MCF548X supports a single external reference clock (CLKIN). This signal defines the frequency of operation for FlexBus and PCI. 2 Max cycle rate is determined by CLKIN and how the user has the system PLL configured. 3 Timing for chip selects only applies to the FBCS[5:0] signals. Please see Section9.2, “DDR SDRAM AC Timing Characteristics” for SDCS[3:0] timing. 4 The FlexBus supports programming an extension of the address hold. Please consult the MCF548X specification manual for more information. 5 These specs are used when the PCIAD[31:0] signals are configured as 32-bit, non-muxed FlexBus address signals. MCF548x ColdFire® Microprocessor, Rev. 4 Freescale Semiconductor 13

FlexBus CLKIN FB1 FB3 AD[X:0] A[X:0] FB2 FB5 AD[31:Y] A[31:Y] DATA R/W FB4 ALE TSIZ[1:0] TSIZ[1:0] FBCSn, BE/BWEn FB7 OE FB6 TA Figure11. FlexBus Read Timing MCF548x ColdFire® Microprocessor, Rev. 4 14 Freescale Semiconductor

SDRAM Bus CLKIN FB1 FB3 AD[X:0] A[X:0] FB2 FB3 AD[31:Y] A[31:Y] DATA R/W ALE TSIZ[1:0] TSIZ[1:0] FBCSn, BE/BWEn FB7 OE FB6 TA Figure12. FlexBus Write Timing 9 SDRAM Bus The SDRAM controller supports accesses to main SDRAM memory from any internal master. It supports standard SDRAM or double data rate (DDR) SDRAM, but it does not support both at the same time. The SDRAM controller uses SSTL2 and SSTL3 I/O drivers. Both SSTL drive modes are programmable for Class I or Class II drive strength. 9.1 SDR SDRAM AC Timing Characteristics The following timing numbers indicate when data is latched or driven onto the external bus, relative to the memory bus clock, when operating in SDR mode on write cycles and relative to SDR_DQS on read cycles. The MCF548x SDRAM controller is a DDR controller that has an SDR mode. Because it is designed to support DDR, a DQS pulse must be supplied to the MCF548x for each data beat of an SDR read. The MCF548x accomplishes this by asserting a signal called SDR_DQS during read cycles. Care must be taken during board design to adhere to the following guidelines and specs with regard to the SDR_DQS signal and its usage. MCF548x ColdFire® Microprocessor, Rev. 4 Freescale Semiconductor 15

SDRAM Bus Table11. SDR Timing Specifications Symbol Characteristic Min Max Unit Notes Frequency of Operation 0 133 Mhz 1 SD1 Clock Period (t ) 7.52 12 ns 2 CK SD2 Clock Skew (t ) TBD SK SD3 Pulse Width High (t ) 0.45 0.55 SDCLK 3 CKH SD4 Pulse Width Low (t ) 0.45 0.55 SDCLK 4 CKL SD5 Address, CKE, CAS, RAS, WE, BA, CS - Output Valid (t ) 0.5×SDCLK+ ns CMV 1.0ns SD6 Address, CKE, CAS, RAS, WE, BA, CS - Output Hold (t ) 2.0 ns CMH SD7 SDRDQS Output Valid (t ) Self timed ns 5 DQSOV SD8 SDDQS[3:0] input setup relative to SDCLK (t ) 0.25×SDCLK 0.40×SDCLK ns 6 DQSIS SD9 SDDQS[3:0] input hold relative to SDCLK (t ) Does not apply. 0.5 SDCLK fixed width. 7 DQSIH SD10 Data Input Setup relative to SDCLK (reference only) (t ) 0.25×SDCLK ns 8 DIS SD11 Data Input Hold relative to SDCLK (reference only) (t ) 1.0 ns DIH SD12 Data and Data Mask Output Valid (t ) 0.75×SDCLK ns DV +0.500ns SD13 Data and Data Mask Output Hold (t ) 1.5 ns DH 1 The frequency of operation is 2x or 4x the CLKIN frequency of operation. The MCF548X supports a single external reference clock (CLKIN). This signal defines the frequency of operation for FlexBus and PCI, but SDRAM clock operates at the same frequency as the internal bus clock. Please see the PLL chapter of the MCF548X Reference Manual for more information on setting the SDRAM clock rate. 2 SDCLK is one SDRAM clock in (ns). 3 Pulse width high plus pulse width low cannot exceed min and max clock period. 4 Pulse width high plus pulse width low cannot exceed min and max clock period. 5 SDR_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This is a guideline only. Subtle variation from this guideline is expected. SDR_DQS only pulses during a read cycle and one pulse occurs for each data beat. 6 SDR_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This spec is a guideline only. Subtle variation from this guideline is expected. SDR_DQS only pulses during a read cycle and one pulse occurs for each data beat. 7 The SDR_DQS pulse is designed to be 0.5 clock in width. The timing of the rising edge is most important. The falling edge does not affect the memory controller. 8 Because a read cycle in SDR mode uses the DQS circuit within the MCF548X, it is most critical that the data valid window be centered 1/4 clk after the rising edge of DQS. Ensuring that this happens results in successful SDR reads. The input setup spec is provided as guidance. MCF548x ColdFire® Microprocessor, Rev. 4 16 Freescale Semiconductor

SDRAM Bus SD2 SD1 SD3 SDCLK0 SD2 SD4 SDCLK1 SD6 SDCSn,SDWE, CMD RAS, CAS SD5 SDADDR, ROW COL SDBA[1:0] SD12 SDDM SD13 SDDATA WD1 WD2 WD3 WD4 Figure13. SDR Write Timing SD2 SD1 SDCLK0 SD2 SDCLK1 SD6 SDCSn,SDWE, CMD RAS, CAS 3/4 MCLK SD5 Reference SDADDR, ROW COL SDBA[1:0] tDQS SDDM SD7 SDRQS (Measured at Output Pin) Board Delay SD9 SDDQS (Measured at Input Pin) Board Delay SD8 Delayed SDCLK SD10 SDDATA form WD1 WD2 WD3 WD4 Memories NOTE: Data driven from memories relative SD11 to delayed memory clock. Figure14. SDR Read Timing MCF548x ColdFire® Microprocessor, Rev. 4 Freescale Semiconductor 17

SDRAM Bus 9.2 DDR SDRAM AC Timing Characteristics When using the DDR SDRAM controller, the following timing numbers must be followed to properly latch or drive data onto the memory bus. All timing numbers are relative to the four DQS byte lanes. Table12shows the DDR clock crossover specifications. Table12. DDR Clock Crossover Specifications Symbol Characteristic Min Max Unit V Clock output mid-point voltage 1.05 1.45 V MP V Clock output voltage level –0.3 SD_VDD + 0.3 V OUT V Clock output differential voltage (peak to peak swing) 0.7 SD_VDD + 0.6 V ID V Clock crossing point voltage1 1.05 1.45 V IX 1 The clock crossover voltage is only guaranteed when using the highest drive strength option for the SDCLK[1:0] and SDCLK[1:0] signals. SDCLK V IX VMP VID V IX SDCLK Figure15. DDR Clock Timing Diagram Table13. DDR Timing Specifications Symbol Characteristic Min Max Unit Notes Frequency of Operation 501 133 MHz 2 DD1 Clock Period (t ) 7.52 12 ns 3 CK DD2 Pulse Width High (t ) 0.45 0.55 SDCLK 4 CKH DD3 Pulse Width Low (t ) 0.45 0.55 SDCLK 5 CKL DD4 Address, SDCKE, CAS, RAS, WE, SDBA, SDCS—Output — 0.5×SDCLK ns 6 Valid (t ) +1.0 ns CMV DD5 Address, SDCKE, CAS, RAS, WE, SDBA, SDCS—Output Hold 2.0 — ns (t ) CMH DD6 Write Command to first DQS Latching Transition (t ) — 1.25 SDCLK DQSS DD7 Data and Data Mask Output Setup (DQ−>DQS) Relative to 1.0 — ns 7 DQS (DDR Write Mode) (t ) 8 QS DD8 Data and Data Mask Output Hold (DQS−>DQ) Relative to DQS 1.0 — ns 9 (DDR Write Mode) (t ) QH DD9 Input Data Skew Relative to DQS (Input Setup) (t ) 1 ns 10 IS DD10 Input Data Hold Relative to DQS (t ) 0.25×SDCLK — ns 11 IH +0.5ns DD11 DQS falling edge to SDCLK rising (output setup time) (t ) 0.5 — ns DSS DD12 DQS falling edge from SDCLK rising (output hold time) (t ) 0.5 — ns DSH MCF548x ColdFire® Microprocessor, Rev. 4 18 Freescale Semiconductor

SDRAM Bus Table13. DDR Timing Specifications (continued) Symbol Characteristic Min Max Unit Notes DD13 DQS input read preamble width (t ) 0.9 1.1 SDCLK RPRE DD14 DQS input read postamble width (t ) 0.4 0.6 SDCLK RPST DD15 DQS output write preamble width (t ) 0.25 — SDCLK WPRE DD16 DQS output write postamble width (t ) 0.4 0.6 SDCLK WPST 1 DDR memories typically have a minimum speed specification of 83 MHz. Check memory component specifications to verify. 2 The frequency of operation is 2x or 4x the CLKIN frequency of operation. The MCF548X supports a single external reference clock (CLKIN). This signal defines the frequency of operation for FlexBus and PCI, but SDRAM clock operates at the same frequency as the internal bus clock. Please see the reset configuration signals description in the “Signal Descriptions” chapter within the MCF548x Reference Manual. 3 SDCLK is one memory clock in (ns). 4 Pulse width high plus pulse width low cannot exceed max clock period. 5 Pulse width high plus pulse width low cannot exceed max clock period. 6 Command output valid should be 1/2 the memory bus clock (SDCLK) plus some minor adjustments for process, temperature, and voltage variations. 7 This specification relates to the required input setup time of today’s DDR memories. SDDATA[31:24] is relative to SDDQS3, SDDATA[23:16] is relative to SDDQS2, SDDATA[15:8] is relative to SDDQS1, and SDDATA[7:0] is relative SDDQS0. 8 The first data beat is valid before the first rising edge of SDDQS and after the SDDQS write preamble. The remaining data beats is valid for each subsequent SDDQS edge. 9 This specification relates to the required hold time of today’s DDR memories. SDDATA[31:24] is relative to SDDQS3, SDDATA[23:16] is relative to SDDQS2, SDDATA[15:8] is relative to SDDQS1, and SDDATA[7:0] is relative SDDQS0. 10Data input skew is derived from each SDDQS clock edge. It begins with a SDDQS transition and ends when the last data line becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing or other factors). 11Data input hold is derived from each SDDQS clock edge. It begins with a SDDQS transition and ends when the first data line becomes invalid. MCF548x ColdFire® Microprocessor, Rev. 4 Freescale Semiconductor 19

SDRAM Bus DD1 DD2 SDCLK0 DD3 SDCLK1 SDCLK0 SDCLK1 DD5 SDCSn,SDWE, CMD RAS, CAS DD4 DD6 SDADDR, ROW COL SDBA[1:0] DD7 SDDM DD8 SDDQS DD7 SDDATA WD1 WD2 WD3 WD4 DD8 Figure16. DDR Write Timing MCF548x ColdFire® Microprocessor, Rev. 4 20 Freescale Semiconductor

PCI Bus DD1 DD2 SDCLK0 DD3 SDCLK1 SDCLK0 SDCLK1 DD5 CL=2 SDCSn,SDWE, CMD RAS, CAS DD4 CL=2.5 SDADDR, ROW COL SDBA[1:0] DD9 DQS Read DQS Read Preamble Postamble SDDQS DD10 SDDATA WD1 WD2 WD3 WD4 DQS Read DQS Read Preamble Postamble SDDQS WD1 WD2 WD3 WD4 SDDATA Figure17. DDR Read Timing 10 PCI Bus The PCI bus on the MCF548x is PCI 2.2 compliant. The following timing numbers are mostly from the PCI 2.2 spec. Please refer to the PCI 2.2 spec for a more detailed timing analysis. Table14. PCI Timing Specifications Num Characteristic Min Max Unit Notes Frequency of Operation 25 50 MHz 1 P1 Clock Period (t ) 20 40 ns 2 CK P2 Address, Data, and Command (33< PCI ≤ 50 Mhz)—Input Setup (t ) 3.0 — ns IS P3 Address, Data, and Command (0 < PCI ≤ 33 Mhz)—Input Setup (t ) 7.0 — ns IS P4 Address, Data, and Command (33–50 Mhz)—Output Valid (t ) — 6.0 ns 3 DV P5 Address, Data, and Command (0–33 Mhz) - Output Valid (t ) — 11.0 ns DV P6 PCI signals (0–50 Mhz) - Output Hold (t ) 0 — ns 4 DH MCF548x ColdFire® Microprocessor, Rev. 4 Freescale Semiconductor 21

Fast Ethernet AC Timing Specifications Table14. PCI Timing Specifications (continued) Num Characteristic Min Max Unit Notes P7 PCI signals (0–50 Mhz) - Input Hold (t ) 0 — ns 5 IH P8 PCI REQ/GNT (33 < PCI ≤ 50Mhz) - Output valid (t ) — 6 ns 6 DV P9 PCI REQ/GNT (0 < PCI ≤ 33Mhz) - Output valid (t ) — 12 ns DV P10 PCI REQ/GNT (33 < PCI ≤ 50Mhz) - Input Setup (t ) — 5 ns IS P11 PCI REQ (0 < PCI ≤ 33Mhz) - Input Setup (t ) 12 — ns IS P12 PCI GNT (0 < PCI ≤ 33Mhz) - Input Setup (t ) 10 — ns IS 1 Please see the reset configuration signals description in the “Signal Descriptions” chapter within the MCF548x Reference Manual. Also specific guidelines may need to be followed when operating the system PLL below certain frequencies. 2 Max cycle rate is determined by CLKIN and how the user has the system PLL configured. 3 All signals defined as PCI bused signals. Does not include PTP (point-to-point) signals. 4 PCI 2.2 spec does not require an output hold time. Although the MCF548X may provide a slight amount of hold, it is not required or guaranteed. 5 PCI 2.2 spec requires zero input hold. 6 These signals are defined at PTP (Point-to-point) in the PCI 2.2 spec. P1 CLKIN P4 P6 Output Output Valid Valid/Hold P2 Input Input Valid Setup/Hold P7 Figure18. PCI Timing 11 Fast Ethernet AC Timing Specifications 11.1 MII/7-WIRE Interface Timing Specs The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing specs/constraints for the EMAC_10_100 I/O signals. The following timing specs meet the requirements for MII and 7-Wire style interfaces for a range of transceiver devices. If this interface is to be used with a specific transceiver device the timing specs may be altered to match that specific transceiver. MCF548x ColdFire® Microprocessor, Rev. 4 22 Freescale Semiconductor

Fast Ethernet AC Timing Specifications Table15. MII Receive Signal Timing Num Characteristic Min Max Unit M1 RXD[3:0], RXDV, RXER to RXCLK setup 5 — ns M2 RXCLK to RXD[3:0], RXDV, RXER hold 5 — ns M3 RXCLK pulse width high 35% 65% RXCLK period M4 RXCLK pulse width low 35% 65% RXCLK period M3 RXCLK (Input) M1 M4 RXD[3:0] (Inputs) RXDV, RXER M2 Figure19. MII Receive Signal Timing Diagram 11.2 MII Transmit Signal Timing Table16. MII Transmit Signal Timing Num Characteristic Min Max Unit M5 TXCLK to TXD[3:0], TXEN, TXER invalid 0 — ns M6 TXCLK to TXD[3:0], TXEN, TXER valid — 25 ns M7 TXCLK pulse width high 35% 65% TXCLK period M8 TXCLK pulse width low 35% 65% TXCLK period M7 TXCLK (Input) M5 M8 TXD[3:0] (Outputs) TXEN, TXER M6 Figure20. MII Transmit Signal Timing Diagram MCF548x ColdFire® Microprocessor, Rev. 4 Freescale Semiconductor 23

Fast Ethernet AC Timing Specifications 11.3 MII Async Inputs Signal Timing (CRS, COL) Table17. MII Transmit Signal Timing Num Characteristic Min Max Unit M9 CRS, COL minimum pulse width 1.5 — TX_CLK period CRS, COL M9 Figure21. MII Async Inputs Timing Diagram 11.4 MII Serial Management Channel Timing (MDIO,MDC) Table18. MII Serial Management Channel Signal Timing Num Characteristic Min Max Unit M10 MDC falling edge to MDIO output invalid 0 — ns (min prop delay) M11 MDC falling edge to MDIO output valid — 25 ns (max prop delay) M12 MDIO (input) to MDC rising edge setup 10 — ns M13 MDIO (input) to MDC rising edge hold 0 — ns M14 MDC pulse width high 40% 60% MDC period M15 MDC pulse width low 40% 60% MDC period M14 M15 MDC (Output) M10 MDIO (Output) M12 M11 MDIO (Input) M13 Figure22. MII Serial Management Channel TIming Diagram MCF548x ColdFire® Microprocessor, Rev. 4 24 Freescale Semiconductor

General Timing Specifications 12 General Timing Specifications Table19 lists timing specifications for the GPIO, PSC, FlexCAN, DREQ, DACK, and external interrupts. Table19. General AC Timing Specifications Name Characteristic Min Max Unit G1 CLKIN high to signal output valid — 2 PSTCLK G2 CLKIN high to signal invalid (output hold) 0 — ns G3 Signal input pulse width 2 — PSTCLK 2 13 I C Input/Output Timing Specifications Table20 lists specifications for the I2C input timing parameters shown in Figure23. Table20. I2C Input Timing Specifications between SCL and SDA Num Characteristic Min Max Units I1 Start condition hold time 2 — Bus clocks I2 Clock low period 8 — Bus clocks I3 SCL/SDA rise time (V =0.5 V to V =2.4 V) — 1 mS IL IH I4 Data hold time 0 — ns I5 SCL/SDA fall time (V =2.4 V to V =0.5 V) — 1 mS IH IL I6 Clock high time 4 — Bus clocks I7 Data setup time 0 — ns I8 Start condition setup time (for repeated start condition only) 2 — Bus clocks I9 Stop condition setup time 2 — Bus clocks Table21 lists specifications for the I2C output timing parameters shown in Figure23. Table21. I2C Output Timing Specifications between SCL and SDA Num Characteristic Min Max Units I11 Start condition hold time 6 — Bus clocks I2 1 Clock low period 10 — Bus clocks I3 2 SCL/SDA rise time (V =0.5 V to V =2.4 V) — — µS IL IH I4 1 Data hold time 7 — Bus clocks I5 3 SCL/SDA fall time (V =2.4 V to V =0.5 V) — 3 ns IH IL I6 1 Clock high time 10 — Bus clocks I7 1 Data setup time 2 — Bus clocks I8 1 Start condition setup time (for repeated start 20 — Bus clocks condition only) I9 1 Stop condition setup time 10 — Bus clocks MCF548x ColdFire® Microprocessor, Rev. 4 Freescale Semiconductor 25

JTAG and Boundary Scan Timing 1 Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum frequency (IFDR=0x20) results in minimum output timings as shown in Table21. The I2C interface is designed to scale the actual data transition time to move it to the middle of the SCL low period. The actual position is affected by the prescale and division values programmed into the IFDR; however, the numbers given in Table21 are minimum values. 2 Because SCL and SDA are open-collector-type outputs, which the processor can only actively drive low, the time SCL or SDA take to reach a high level depends on external signal capacitance and pull-up resistor values. 3 Specified at a nominal 50-pF load. Figure23 shows timing for the values in Table20 and Table21. I2 I6 I5 SCL I1 I7 I3 I4 I8 I9 SDA Figure23. I2C Input/Output Timings 14 JTAG and Boundary Scan Timing Table22. JTAG and Boundary Scan Timing Num Characteristics1 Symbol Min Max Unit J1 TCLK Frequency of Operation f DC 10 MHz JCYC J2 TCLK Cycle Period t 2 — t JCYC CK J3 TCLK Clock Pulse Width t 15.15 — ns JCW J4 TCLK Rise and Fall Times t 0.0 3.0 ns JCRF J5 Boundary Scan Input Data Setup Time to TCLK Rise t 5.0 — ns BSDST J6 Boundary Scan Input Data Hold Time after TCLK Rise t 24.0 — ns BSDHT J7 TCLK Low to Boundary Scan Output Data Valid t 0.0 15.0 ns BSDV J8 TCLK Low to Boundary Scan Output High Z t 0.0 15.0 ns BSDZ J9 TMS, TDI Input Data Setup Time to TCLK Rise t 5.0 — ns TAPBST J10 TMS, TDI Input Data Hold Time after TCLK Rise t 10.0 — ns TAPBHT J11 TCLK Low to TDO Data Valid t 0.0 20.0 ns TDODV J12 TCLK Low to TDO High Z t 0.0 15.0 ns TDODZ J13 TRST Assert Time t 100.0 — ns TRSTAT J14 TRST Setup Time (Negation) to TCLK High t 10.0 — ns TRSTST 1 MTMOD is expected to be a static signal. Hence, it is not associated with any timing MCF548x ColdFire® Microprocessor, Rev. 4 26 Freescale Semiconductor

JTAG and Boundary Scan Timing J2 J3 J3 V TCLK (Input) IH V IL J4 J4 Figure24. Test Clock Input Timing TCLK V VIH IL 5 6 Data Inputs Input Data Valid 7 Data Outputs Output Data Valid 8 Data Outputs 7 Data Outputs Output Data Valid Figure25. Boundary Scan (JTAG) Timing TCLK V VIH IL 9 10 TDI, TMS, BKPT Input Data Valid 11 TDO Output Data Valid 12 TDO 11 TDO Output Data Valid Figure26. Test Access Port Timing TCLK 14 TRST 13 Figure27. TRST Timing Debug AC Timing Specifications MCF548x ColdFire® Microprocessor, Rev. 4 Freescale Semiconductor 27

JTAG and Boundary Scan Timing Table23 lists specifications for the debug AC timing parameters shown in Figure29. Table23. Debug AC Timing Specifications 50 MHz Num Characteristic Units Min Max D1 PSTDDATA to PSTCLK setup 4.5 — ns D2 PSTCLK to PSTDDATA hold 4.5 — ns D3 DSI-to-DSCLK setup 1 — PSTCLKs D4 1 DSCLK-to-DSO hold 4 — PSTCLKs D5 DSCLK cycle time 5 — PSTCLKs 1 DSCLK and DSI are synchronized internally. D4 is measured from the synchronized DSCLK input relative to the rising edge of CLKOUT. Figure28 shows real-time trace timing for the values in Table23. PSTCLK D1 D2 PSTDDATA[7:0] Figure28. Real-Time Trace AC Timing Figure29 shows BDM serial port AC timing for the values in Table23. D5 DSCLK D3 DSI Current Next D4 DSO Past Current Figure29. BDM Serial Port AC Timing MCF548x ColdFire® Microprocessor, Rev. 4 28 Freescale Semiconductor

DSPI Electrical Specifications 15 DSPI Electrical Specifications Table24 lists DSPI timings. Table24. DSPI Modules AC Timing Specifications Name Characteristic Min Max Unit DS1 DSPI_CS[3:0] to DSPI_CLK 1 × tck 510 × tck ns DS2 DSPI_CLK high to DSPI_DOUT valid. — 12 ns DS3 DSPI_CLK high to DSPI_DOUT invalid. (Output hold) 2 — ns DS4 DSPI_DIN to DSPI_CLK (Input setup) 10 — ns DS5 DSPI_DIN to DSPI_CLK (Input hold) 10 — ns The values in Table24 correspond to Figure30. DSPI_CS[3:0] DS1 DSPI_CLK DS2 DSPI_DOUT DS3 DS4 DS5 DSPI_DIN Figure30. DSPI Timing 16 Timer Module AC Timing Specifications Table25 lists timer module AC timings. Table25. Timer Module AC Timing Specifications 0–50 MHz Name Characteristic Unit Min Max T1 TIN0 / TIN1 / TIN2 / TIN3 cycle time 3 — PSTCLK T2 TIN0 / TIN1 / TIN2 / TIN3 pulse width 1 — PSTCLK MCF548x ColdFire® Microprocessor, Rev. 4 Freescale Semiconductor 29

Case Drawing 17 Case Drawing MCF548x ColdFire® Microprocessor, Rev. 4 30 Freescale Semiconductor

Case Drawing Figure31. 388-pin BGA Case Outline MCF548x ColdFire® Microprocessor, Rev. 4 Freescale Semiconductor 31

Revision History 18 Revision History Revision Date Substantive Changes Number 2.2 August 29, 2005 Table7: Changed C1 minimum spec from 15.15ns to 20ns and maximum spec from 33.3ns to 40ns. 2.3 August 30, 2005 Table22: Changed J11 maximum from 15ns to 20ns. 2.4 December 14, 2005 Table9: Changed heading maximum from 66MHz to 50MHz. Table10: Changed frequency of operation maximum from 66MHz to 50MHz and corresponding FB1 minimum from 15.15ns to 20ns. Table10: Changed FB1 maximum from 33.33ns to 40ns. Table14: Changed frequency of operation maximum from 66MHz to 50MHz and corresponding FB1 minimum from 15.15ns to 20ns. Table14: Changed FB1 maximum from 33.33ns to 40ns. Table14: Changed various entry descriptions from “(33 < PCI ≤ 66Mhz)” to (33< PCI ≤ 50 Mhz) Table23: Changed heading maximum from 66MHz to 50MHz. Table25: Changed heading maximum from 66MHz to 50MHz. 3 February 20, 2007 Table4: Updated DC electrical specifications, V and V . IL IH Table6: Changed FlexBus output load from 20pF to 30pF. Added Section4.3, “General USB Layout Guidelines.” 4 December 4, 2007 Figure2: Changed resistor value from 10W to 10Ω Figure3: Changed note 1 in from “IVDD should not exceed EVDD, SD VDD or PLL VDD by more than 0.4V...” to “IVDD should not exceed EVDD or SD VDD by more than 0.4V...” Table3: Updated thermal information for θ , θ , and θ JMA JB JC Table4: Added input leakage current spec. Table6: Added footnote regarding pads having balanced source & sink current. Table9: Added RSTI pulse duration spec. Added features list, pinout drawing, block diagram, and case outline. MCF548x ColdFire® Microprocessor, Rev. 4 32 Freescale Semiconductor

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: N XP: MCF5482CVR166 MCF5480CVR166 MCF5483CVR166 MCF5481CVR166 MCF5484CVR200 MCF5485CVR200 MCF5480CZP166 MCF5482CZP166 MCF5484CZP200 MCF5485CZP200