Freescale Semiconductor Document Number: QFN_Addendum Rev. 0, 07/2014 Addendum Addendum for New QFN Package Migration This addendum provides the changes to the 98A case outline numbers for products covered in this book. Case outlines were changed because of the migration from gold wire to copper wire in some packages. See the table below for the old (gold wire) package versus the new (copper wire) package. To view the new drawing, go to Freescale.com and search on the new 98A package number for your device. For more information about QFN package use, see EB806: Electrical Connection Recommendations for the Exposed Pad on QFN and DFN Packages. ©Freescale Semiconductor, Inc., 2014. All rights reserved.

Original (gold wire) Current (copper wire) Part Number Package Description package document number package document number MC68HC908JW32 48 QFN 98ARH99048A 98ASA00466D MC9S08AC16 MC9S908AC60 MC9S08AC128 MC9S08AW60 MC9S08GB60A MC9S08GT16A MC9S08JM16 MC9S08JM60 MC9S08LL16 MC9S08QE128 MC9S08QE32 MC9S08RG60 MCF51CN128 MC9RS08LA8 48 QFN 98ARL10606D 98ASA00466D MC9S08GT16A 32 QFN 98ARH99035A 98ASA00473D MC9S908QE32 32 QFN 98ARE10566D 98ASA00473D MC9S908QE8 32 QFN 98ASA00071D 98ASA00736D MC9S08JS16 24 QFN 98ARL10608D 98ASA00734D MC9S08QB8 MC9S08QG8 24 QFN 98ARL10605D 98ASA00474D MC9S08SH8 24 QFN 98ARE10714D 98ASA00474D MC9RS08KB12 24 QFN 98ASA00087D 98ASA00602D MC9S08QG8 16 QFN 98ARE10614D 98ASA00671D MC9RS08KB12 8 DFN 98ARL10557D 98ASA00672D MC9S08QG8 MC9RS08KA2 6 DFN 98ARL10602D 98ASA00735D Addendum for New QFN Package Migration, Rev. 0 2 Freescale Semiconductor

Freescale Semiconductor MC9S08SH8 Rev. 3.1, 05/2012 MC9S08SH8 Datasheet This is the MC9S08SH8 datasheet set consisting of the following files: • MC9S08SH8 Datasheet Addendum, Rev 1 • MC9S08SH8 Datasheet, Rev 3 ©Freescale Semiconductor, Inc., 2012. All rights reserved.

Freescale Semiconductor MC9S08SH8AD Rev. 1, 05/2012 Datasheet Addendum MC9S08SH8 Datasheet Addendum This addendum describes corrections or updates to the Table of Contents MC9S08SH8 Datasheet, file named as MC9S08SH8. 1 Addendum for Revision 3.0. . . . . . . . . . . . . . . . . . 2 2 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Please check our website at http://www.freescale.com/, for the latest updates. The current version available of the MC9S08SH8 Datasheet is Revision 3.0. ©Freescale Semiconductor, Inc., 2012. All rights reserved.

Addendum for Revision 3.0 1 Addendum for Revision 3.0 Table1. MC9S08SH8 Rev 3.0 Addendum Location Description Section “Control Timing” for In “Control Timing” table, changed minimum value of “'Internal low power oscillator period” Appendix A ”Electrical parameter from 800 µs to 700 µs. This value is under 5V VDD, -40 oC to 125 oC temperature Characteristics” range condition. 2 Revision History Table 2 provides a revision history for this document. Table2. Revision History Table Rev. Number Substantive Changes Date of Release 1.0 Initial release. Changed minimum value of “'Internal low power oscillator period” 05/2012 parameter from 800 µs to 700 µs, in “Control Timing” table. MC9S08SH8AD, Rev. 1 2 Freescale Semiconductor

How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Information in this document is provided solely to enable system and Japan software implementers to use Freescale Semiconductor products. There are 0120 191014 or +81 3 5437 9125 no express or implied copyright licenses granted hereunder to design or support.japan@freescale.com fabricate any integrated circuits or integrated circuits based on the information in this document. Asia/Pacific: Freescale Semiconductor China Ltd. Freescale Semiconductor reserves the right to make changes without further Exchange Building 23F notice to any products herein. Freescale Semiconductor makes no warranty, No. 118 Jianguo Road representation or guarantee regarding the suitability of its products for any Chaoyang District particular purpose, nor does Freescale Semiconductor assume any liability Beijing 100022 arising out of the application or use of any product or circuit, and specifically China disclaims any and all liability, including without limitation consequential or +86 10 5879 8000 incidental damages. “Typical” parameters that may be provided in Freescale support.asia@freescale.com Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating For Literature Requests Only: parameters, including “Typicals”, must be validated for each customer Freescale Semiconductor Literature Distribution Center application by customer’s technical experts. Freescale Semiconductor does 1-800-441-2447 or 303-675-2140 not convey any license under its patent rights nor the rights of others. Fax: 303-675-2150 Freescale Semiconductor products are not designed, intended, or authorized LDCForFreescaleSemiconductor@hibbertgroup.com for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners.© Freescale Semiconductor, Inc. 2012. All rights reserved. MC9S08SH8AD Rev. 1 05/2012

a MC9S08SH8 MC9S08SH4 Data Sheet HCS08 Microcontrollers MC9S08SH8 Rev. 3 6/2008 freescale.com

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MC9S08SH8 Features 8-Bit HCS08 Central Processor Unit (CPU) Peripherals • 40-MHz HCS08 CPU (central processor unit) • ADC — 12-channel, 10-bit resolution, 2.5μs • HC08instructionsetwithaddedBGNDinstruction conversion time, automatic compare function, temperature sensor, internal bandgap reference • Support for up to 32 interrupt/reset sources channel; runs in stop3 On-Chip Memory • ACMP — Analog comparator with selectable • FLASH read/program/erase over full operating interrupt on rising, falling, or either edge of voltage and temperature comparator output; compare option to fixed • Random-access memory (RAM) internalbandgapreferencevoltage;outputcanbe optionally routed to TPM module; runs in stop3 Power-Saving Modes • SCI — Full duplex non-return to zero (NRZ); LIN • Two very low power stop modes master extended break generation; LIN slave • Reduced power wait mode extendedbreakdetection;wakeuponactiveedge • Very low power real time interrupt for use in run, • SPI — Full-duplex or single-wire bidirectional; wait, and stop Double-buffered transmit and receive; Master or Slave mode; MSB-first or LSB-first shifting Clock Source Options • IIC—Upto100kbpswithmaximumbusloading; • Oscillator (XOSC) — Loop-control Pierce Multi-master operation; Programmable slave oscillator; Crystal or ceramic resonator range of address; Interrupt driven byte-by-byte data 31.25kHz to 38.4kHz or 1 MHz to 16MHz transfer; supports broadcast mode and 10-bit • Internal Clock Source (ICS) — Internal clock addressing source module containing a frequency-locked • MTIM—8-bitmodulocounterwith8-bitprescaler loop (FLL) controlled by internal or external and overflow interrupt reference;precisiontrimmingofinternalreference allows 0.2% resolution and 2% deviation over • TPMx — Two 2-channel timer pwm modules temperature and voltage; supports bus (TPM1, TPM2); Selectable input capture, output frequencies from 2MHz to 20MHz. compare, or buffered edge- or center-aligned PWM on each channel System Protection • RTC—(Real-timecounter)8-bitmoduluscounter • Watchdog computer operating properly (COP) with binary or decimal based prescaler; External reset with opti/n to run from dedicated 1-kHz clock source for precise time base, time-of-day, internal clock source or bus clock calendar or task scheduling functions; Free • Low-voltage detection with reset or interrupt; running on-chip low power oscillator (1kHz) for selectable trip points cyclicwake-upwithoutexternalcomponents,runs • Illegalopcode detection withreset in all MCU modes • Illegaladdress detection withreset Input/Output • FLASH block protect • 17 general purpose I/O pins (GPIOs) and 1 output-only pin Development Support • 8 interrupt pins with selectable polarity • Single-wire background debug interface • GangedoutputoptionforPTB[5:2]andPTC[3:0]; • Breakpoint capability to allow single breakpoint allowssinglewritetochangestateofmultiplepins setting during in-circuit debugging (pluss two more breakpoints in on-chip debug module) • Hysteresis and configurable pull up device on all input pins; Configurable slew rate and drive • On-chip,in-circuitemulation(ICE)debugmodule strength on all output pins. containing two comparators and nine trigger modes. Eight deep FIFO for storing Package Options change-of-flow address and event-only data. • 24-QFN,20-TSSOP,20-SOIC,20-PDIP, Debug module supports both tag and force 16-TSSOP,8-SOIC breakpoints.

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MC9S08SH8 Data Sheet Covers MC9S08SH8 MC9S08SH4 MC9S08SH8 Rev. 3 6/2008 Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. ©Freescale Semiconductor, Inc., 2007-2008. All rights reserved.

Revision History Toprovidethemostup-to-dateinformation,therevisionofourdocumentsontheWorldWideWebwillbe the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ The following revision history table summarizes changes contained in this document. Revision Revision Description of Changes Number Date 0.01 3/08/2006 Initial review copy Updated Electricals and incorporated revisions from Project sync issues: 2394, 1 11/2007 2600, 2601, and 2764. Corrected SPI module to be version 3. Incorporated fixes for Project Sync issues: 2394, 2600, 2601, 2764, 3237, and 3279; as well as, ADC Temperature 2 3/2008 Sensor issues 3331 and 3335. Adjusted Features page leading and fixed minor grammatical errors. Added 20-SOIC package option for the C temp only. Cor- rected package drawing number for 24-QFN. 3 6/2008 Added ICS over Termperature graph to Electricals. Resolved final TBDs. ©Freescale Semiconductor, Inc., 2007-2008. All rights reserved. ® This product incorporates SuperFlash Technology licensed from SST. MC9S08SH8MCUSeriesDataSheet,Rev.3 6 Freescale Semiconductor

List of Chapters Chapter 1 Device Overview......................................................................19 Chapter 2 Pins and Connections.............................................................23 Chapter 3 Modes of Operation.................................................................31 Chapter 4 Memory.....................................................................................37 Chapter 5 Resets, Interrupts, and General System Control..................59 Chapter 6 Parallel Input/Output Control..................................................75 Chapter 7 Central Processor Unit (S08CPUV2)......................................93 Chapter 8 Analog Comparator 5-V (S08ACMPV2)................................113 Chapter 9 Analog-to-Digital Converter (S08ADCV1)............................121 Chapter 10 Internal Clock Source (S08ICSV2)........................................149 Chapter 11 Inter-Integrated Circuit (S08IICV2).......................................163 Chapter 12 Modulo Timer (S08MTIMV1)..................................................183 Chapter 13 Real-Time Counter (S08RTCV1)...........................................193 Chapter 14 Serial Communications Interface (S08SCIV4).....................203 Chapter 15 Serial Peripheral Interface (S08SPIV3) ................................223 Chapter 16 Timer Pulse-Width Modulator (S08TPMV3).........................239 Chapter 17 Development Support ...........................................................267 Appendix A Electrical Characteristics......................................................289 Appendix B Ordering Information and Mechanical Drawings................319 MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 7

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Contents Section Number Title Page Chapter 1 Device Overview 1.1 Devices in the MC9S08SH8 Series .................................................................................................19 1.2 MCU Block Diagram ......................................................................................................................20 1.3 System Clock Distribution ..............................................................................................................22 Chapter 2 Pins and Connections 2.1 Device Pin Assignment ...................................................................................................................23 2.2 Recommended System Connections ...............................................................................................24 2.2.1 Power ................................................................................................................................25 2.2.2 Oscillator (XOSC) ............................................................................................................26 2.2.3 RESET ..............................................................................................................................26 2.2.4 Background / Mode Select (BKGD/MS) ..........................................................................27 2.2.5 General-Purpose I/O and Peripheral Ports ........................................................................27 Chapter 3 Modes of Operation 3.1 Introduction .....................................................................................................................................31 3.2 Features ...........................................................................................................................................31 3.3 Run Mode ........................................................................................................................................31 3.4 Active Background Mode ................................................................................................................31 3.5 Wait Mode .......................................................................................................................................32 3.6 Stop Modes ......................................................................................................................................32 3.6.1 Stop3 Mode .......................................................................................................................33 3.6.2 Stop2 Mode .......................................................................................................................34 3.6.3 On-Chip Peripheral Modules in Stop Modes ....................................................................34 Chapter 4 Memory 4.1 MC9S08SH8 Memory Map ............................................................................................................37 4.2 Reset and Interrupt Vector Assignments .........................................................................................38 4.3 Register Addresses and Bit Assignments ........................................................................................39 4.4 RAM ................................................................................................................................................46 4.5 FLASH ............................................................................................................................................46 4.5.1 Features .............................................................................................................................47 4.5.2 Program and Erase Times .................................................................................................47 MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 9

Section Number Title Page 4.5.3 Program and Erase Command Execution .........................................................................48 4.5.4 Burst Program Execution ..................................................................................................49 4.5.5 Access Errors ....................................................................................................................51 4.5.6 FLASH Block Protection ..................................................................................................51 4.5.7 Vector Redirection ............................................................................................................52 4.6 Security ............................................................................................................................................52 4.7 FLASH Registers and Control Bits .................................................................................................53 4.7.1 FLASH Clock Divider Register (FCDIV) ........................................................................54 4.7.2 FLASH Options Register (FOPT and NVOPT)................................................................55 4.7.3 FLASH Configuration Register (FCNFG) ........................................................................56 4.7.4 FLASH Protection Register (FPROT and NVPROT) .......................................................56 4.7.5 FLASH Status Register (FSTAT) ......................................................................................57 4.7.6 FLASH Command Register (FCMD) ...............................................................................58 Chapter 5 Resets, Interrupts, and General System Control 5.1 Introduction .....................................................................................................................................59 5.2 Features ...........................................................................................................................................59 5.3 MCU Reset ......................................................................................................................................59 5.4 Computer Operating Properly (COP) Watchdog .............................................................................60 5.5 Interrupts .........................................................................................................................................61 5.5.1 Interrupt Stack Frame .......................................................................................................62 5.5.2 External Interrupt Request Pin (IRQ) ...............................................................................63 5.5.3 Interrupt Vectors, Sources, and Local Masks ....................................................................63 5.6 Low-Voltage Detect (LVD) System ................................................................................................65 5.6.1 Power-On Reset Operation ...............................................................................................65 5.6.2 Low-Voltage Detection (LVD) Reset Operation ...............................................................65 5.6.3 Low-Voltage Warning (LVW) Interrupt Operation ...........................................................65 5.7 Reset, Interrupt, and System Control Registers and Control Bits ...................................................65 5.7.1 Interrupt Pin Request Status and Control Register (IRQSC) ............................................66 5.7.2 System Reset Status Register (SRS) .................................................................................67 5.7.3 System Background Debug Force Reset Register (SBDFR) ............................................68 5.7.4 System Options Register 1 (SOPT1) ................................................................................69 5.7.5 System Options Register 2 (SOPT2) ................................................................................70 5.7.6 System Device Identification Register (SDIDH, SDIDL) ................................................71 5.7.7 System Power Management Status and Control 1 Register (SPMSC1) ...........................72 5.7.8 System Power Management Status and Control 2 Register (SPMSC2) ...........................73 Chapter 6 Parallel Input/Output Control 6.1 Port Data and Data Direction ..........................................................................................................75 6.2 Pull-up, Slew Rate, and Drive Strength ...........................................................................................76 MC9S08SH8MCUSeriesDataSheet,Rev.3 10 Freescale Semiconductor

Section Number Title Page 6.3 Ganged Output ................................................................................................................................77 6.4 Pin Interrupts ...................................................................................................................................78 6.4.1 Edge Only Sensitivity .......................................................................................................78 6.4.2 Edge and Level Sensitivity ................................................................................................78 6.4.3 Pull-up/Pull-down Resistors .............................................................................................79 6.4.4 Pin Interrupt Initialization .................................................................................................79 6.5 Pin Behavior in Stop Modes ............................................................................................................79 6.6 Parallel I/O and Pin Control Registers ............................................................................................79 6.6.1 Port A Registers ................................................................................................................80 6.6.2 Port B Registers ................................................................................................................85 6.6.3 Port C Registers ................................................................................................................89 Chapter 7 Central Processor Unit (S08CPUV2) 7.1 Introduction .....................................................................................................................................93 7.1.1 Features .............................................................................................................................93 7.2 Programmer’s Model and CPU Registers .......................................................................................94 7.2.1 Accumulator (A) ...............................................................................................................94 7.2.2 Index Register (H:X) .........................................................................................................94 7.2.3 Stack Pointer (SP) .............................................................................................................95 7.2.4 Program Counter (PC) ......................................................................................................95 7.2.5 Condition Code Register (CCR) .......................................................................................95 7.3 Addressing Modes ...........................................................................................................................97 7.3.1 Inherent Addressing Mode (INH) .....................................................................................97 7.3.2 Relative Addressing Mode (REL) .....................................................................................97 7.3.3 Immediate Addressing Mode (IMM) ................................................................................97 7.3.4 Direct Addressing Mode (DIR) ........................................................................................97 7.3.5 Extended Addressing Mode (EXT) ..................................................................................98 7.3.6 Indexed Addressing Mode ................................................................................................98 7.4 Special Operations ...........................................................................................................................99 7.4.1 Reset Sequence .................................................................................................................99 7.4.2 Interrupt Sequence ............................................................................................................99 7.4.3 Wait Mode Operation ......................................................................................................100 7.4.4 Stop Mode Operation ......................................................................................................100 7.4.5 BGND Instruction ...........................................................................................................101 7.5 HCS08 Instruction Set Summary ..................................................................................................102 Chapter 8 Analog Comparator 5-V (S08ACMPV2) 8.1 Introduction ...................................................................................................................................113 8.1.1 ACMP Configuration Information ..................................................................................113 8.1.2 ACMP in Stop3 Mode .....................................................................................................113 MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 11

Section Number Title Page 8.1.3 ACMP/TPM Configuration Information .........................................................................113 8.1.4 Features ...........................................................................................................................115 8.1.5 Modes of Operation ........................................................................................................115 8.1.6 Block Diagram ................................................................................................................115 8.2 External Signal Description ..........................................................................................................117 8.3 Memory Map ................................................................................................................................117 8.3.1 Register Descriptions ......................................................................................................117 8.4 Functional Description ..................................................................................................................119 Chapter 9 Analog-to-Digital Converter (S08ADCV1) 9.1 Introduction ...................................................................................................................................121 9.1.1 Channel Assignments......................................................................................................121 9.1.2 Alternate Clock ...............................................................................................................122 9.1.3 Hardware Trigger ............................................................................................................122 9.1.4 Temperature Sensor ........................................................................................................122 9.1.5 Features ...........................................................................................................................125 9.1.6 Block Diagram ................................................................................................................125 9.2 External Signal Description ..........................................................................................................126 9.2.1 Analog Power (V ) ..................................................................................................127 DDAD 9.2.2 Analog Ground (V ) .................................................................................................127 SSAD 9.2.3 Voltage Reference High (V ) ...................................................................................127 REFH 9.2.4 Voltage Reference Low (V ) .....................................................................................127 REFL 9.2.5 Analog Channel Inputs (ADx) ........................................................................................127 9.3 Register Definition ........................................................................................................................127 9.3.1 Status and Control Register 1 (ADCSC1) ......................................................................127 9.3.2 Status and Control Register 2 (ADCSC2) ......................................................................129 9.3.3 Data Result High Register (ADCRH) .............................................................................130 9.3.4 Data Result Low Register (ADCRL) ..............................................................................130 9.3.5 Compare Value High Register (ADCCVH) ....................................................................131 9.3.6 Compare Value Low Register (ADCCVL) .....................................................................131 9.3.7 Configuration Register (ADCCFG) ................................................................................131 9.3.8 Pin Control 1 Register (APCTL1) ..................................................................................133 9.3.9 Pin Control 2 Register (APCTL2) ..................................................................................134 9.3.10 Pin Control 3 Register (APCTL3) ..................................................................................135 9.4 Functional Description ..................................................................................................................136 9.4.1 Clock Select and Divide Control ....................................................................................136 9.4.2 Input Select and Pin Control ...........................................................................................137 9.4.3 Hardware Trigger ............................................................................................................137 9.4.4 Conversion Control .........................................................................................................137 9.4.5 Automatic Compare Function .........................................................................................140 9.4.6 MCU Wait Mode Operation ............................................................................................140 MC9S08SH8MCUSeriesDataSheet,Rev.3 12 Freescale Semiconductor

Section Number Title Page 9.4.7 MCU Stop3 Mode Operation ..........................................................................................140 9.4.8 MCU Stop1 and Stop2 Mode Operation .........................................................................141 9.5 Initialization Information ..............................................................................................................141 9.5.1 ADC Module Initialization Example .............................................................................141 9.6 Application Information ................................................................................................................143 9.6.1 External Pins and Routing ..............................................................................................143 9.6.2 Sources of Error ..............................................................................................................145 Chapter 10 Internal Clock Source (S08ICSV2) 10.1 Introduction ...................................................................................................................................149 10.1.1 Module Configuration .....................................................................................................149 10.1.2 Features ...........................................................................................................................151 10.1.3 Block Diagram ................................................................................................................151 10.1.4 Modes of Operation ........................................................................................................152 10.2 External Signal Description ..........................................................................................................153 10.3 Register Definition ........................................................................................................................153 10.3.1 ICS Control Register 1 (ICSC1) .....................................................................................154 10.3.2 ICS Control Register 2 (ICSC2) .....................................................................................155 10.3.3 ICS Trim Register (ICSTRM) .........................................................................................156 10.3.4 ICS Status and Control (ICSSC) .....................................................................................156 10.4 Functional Description ..................................................................................................................157 10.4.1 Operational Modes ..........................................................................................................157 10.4.2 Mode Switching ..............................................................................................................159 10.4.3 Bus Frequency Divider ...................................................................................................160 10.4.4 Low Power Bit Usage .....................................................................................................160 10.4.5 Internal Reference Clock ................................................................................................160 10.4.6 Optional External Reference Clock ................................................................................160 10.4.7 Fixed Frequency Clock ...................................................................................................161 Chapter 11 Inter-Integrated Circuit (S08IICV2) 11.1 Introduction ...................................................................................................................................163 11.1.1 Module Configuration .....................................................................................................163 11.1.2 Features ...........................................................................................................................165 11.1.3 Modes of Operation ........................................................................................................165 11.1.4 Block Diagram ................................................................................................................166 11.2 External Signal Description ..........................................................................................................166 11.2.1 SCL — Serial Clock Line ...............................................................................................166 11.2.2 SDA — Serial Data Line ................................................................................................166 11.3 Register Definition ........................................................................................................................166 11.3.1 IIC Address Register (IICA) ...........................................................................................167 MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 13

Section Number Title Page 11.3.2 IIC Frequency Divider Register (IICF) ...........................................................................167 11.3.3 IIC Control Register (IICC1) ..........................................................................................170 11.3.4 IIC Status Register (IICS) ...............................................................................................171 11.3.5 IIC Data I/O Register (IICD) ..........................................................................................172 11.3.6 IIC Control Register 2 (IICC2) .......................................................................................172 11.4 Functional Description ..................................................................................................................173 11.4.1 IIC Protocol .....................................................................................................................173 11.4.2 10-bit Address .................................................................................................................177 11.4.3 General Call Address ......................................................................................................178 11.5 Resets ............................................................................................................................................178 11.6 Interrupts .......................................................................................................................................178 11.6.1 Byte Transfer Interrupt ....................................................................................................178 11.6.2 Address Detect Interrupt .................................................................................................178 11.6.3 Arbitration Lost Interrupt ................................................................................................178 11.7 Initialization/Application Information ..........................................................................................180 Chapter 12 Modulo Timer (S08MTIMV1) 12.1 Introduction ...................................................................................................................................183 12.1.1 MTIM Configuration Information ..................................................................................183 12.1.2 Features ...........................................................................................................................185 12.1.3 Modes of Operation ........................................................................................................185 12.1.4 Block Diagram ................................................................................................................186 12.2 External Signal Description ..........................................................................................................186 12.3 Register Definition ........................................................................................................................187 12.3.1 MTIM Status and Control Register (MTIMSC) .............................................................188 12.3.2 MTIM Clock Configuration Register (MTIMCLK) .......................................................189 12.3.3 MTIM Counter Register (MTIMCNT) ...........................................................................190 12.3.4 MTIM Modulo Register (MTIMMOD) ..........................................................................190 12.4 Functional Description ..................................................................................................................191 12.4.1 MTIM Operation Example .............................................................................................192 Chapter 13 Real-Time Counter (S08RTCV1) 13.1 Introduction ...................................................................................................................................193 13.1.1 Features ...........................................................................................................................195 13.1.2 Modes of Operation ........................................................................................................195 13.1.3 Block Diagram ................................................................................................................196 13.2 External Signal Description ..........................................................................................................196 13.3 Register Definition ........................................................................................................................196 13.3.1 RTC Status and Control Register (RTCSC) ....................................................................197 13.3.2 RTC Counter Register (RTCCNT) ..................................................................................198 MC9S08SH8MCUSeriesDataSheet,Rev.3 14 Freescale Semiconductor

Section Number Title Page 13.3.3 RTC Modulo Register (RTCMOD) ................................................................................198 13.4 Functional Description ..................................................................................................................198 13.4.1 RTC Operation Example .................................................................................................199 13.5 Initialization/Application Information ..........................................................................................200 Chapter 14 Serial Communications Interface (S08SCIV4) 14.1 Introduction ...................................................................................................................................203 14.1.1 Features ...........................................................................................................................205 14.1.2 Modes of Operation ........................................................................................................205 14.1.3 Block Diagram ................................................................................................................206 14.2 Register Definition ........................................................................................................................208 14.2.1 SCI Baud Rate Registers (SCIxBDH, SCIxBDL) ..........................................................208 14.2.2 SCI Control Register 1 (SCIxC1) ...................................................................................209 14.2.3 SCI Control Register 2 (SCIxC2) ...................................................................................210 14.2.4 SCI Status Register 1 (SCIxS1) ......................................................................................211 14.2.5 SCI Status Register 2 (SCIxS2) ......................................................................................213 14.2.6 SCI Control Register 3 (SCIxC3) ...................................................................................214 14.2.7 SCI Data Register (SCIxD) .............................................................................................215 14.3 Functional Description ..................................................................................................................215 14.3.1 Baud Rate Generation .....................................................................................................215 14.3.2 Transmitter Functional Description ................................................................................216 14.3.3 Receiver Functional Description .....................................................................................217 14.3.4 Interrupts and Status Flags ..............................................................................................219 14.3.5 Additional SCI Functions ...............................................................................................220 Chapter 15 Serial Peripheral Interface (S08SPIV3) 15.1 Introduction ...................................................................................................................................223 15.1.1 Features ...........................................................................................................................225 15.1.2 Block Diagrams ..............................................................................................................225 15.1.3 SPI Baud Rate Generation ..............................................................................................227 15.2 External Signal Description ..........................................................................................................228 15.2.1 SPSCK — SPI Serial Clock ............................................................................................228 15.2.2 MOSI — Master Data Out, Slave Data In ......................................................................228 15.2.3 MISO — Master Data In, Slave Data Out ......................................................................228 15.2.4 SS — Slave Select ...........................................................................................................228 15.3 Modes of Operation .......................................................................................................................229 15.3.1 SPI in Stop Modes ..........................................................................................................229 15.4 Register Definition ........................................................................................................................229 15.4.1 SPI Control Register 1 (SPIC1) ......................................................................................229 15.4.2 SPI Control Register 2 (SPIC2) ......................................................................................230 MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 15

Section Number Title Page 15.4.3 SPI Baud Rate Register (SPIBR) ....................................................................................231 15.4.4 SPI Status Register (SPIS) ..............................................................................................232 15.4.5 SPI Data Register (SPID) ................................................................................................233 15.5 Functional Description ..................................................................................................................234 15.5.1 SPI Clock Formats ..........................................................................................................234 15.5.2 SPI Interrupts ..................................................................................................................237 15.5.3 Mode Fault Detection .....................................................................................................237 Chapter 16 Timer Pulse-Width Modulator (S08TPMV3) 16.1 Introduction ...................................................................................................................................239 16.1.1 ACMP/TPM Configuration Information .........................................................................239 16.1.2 TPM Configuration Information .....................................................................................239 16.1.3 Features ...........................................................................................................................241 16.1.4 Modes of Operation ........................................................................................................241 16.1.5 Block Diagram ................................................................................................................242 16.2 Signal Description .........................................................................................................................244 16.2.1 Detailed Signal Descriptions...........................................................................................244 16.3 Register Definition ........................................................................................................................248 16.3.1 TPM Status and Control Register (TPMxSC) ................................................................248 16.3.2 TPM-Counter Registers (TPMxCNTH:TPMxCNTL) ....................................................249 16.3.3 TPM Counter Modulo Registers (TPMxMODH:TPMxMODL) ....................................250 16.3.4 TPM Channel n Status and Control Register (TPMxCnSC) ..........................................251 16.3.5 TPM Channel Value Registers (TPMxCnVH:TPMxCnVL) ..........................................253 16.4 Functional Description ..................................................................................................................254 16.4.1 Counter ............................................................................................................................255 16.4.2 Channel Mode Selection .................................................................................................256 16.5 Reset Overview .............................................................................................................................260 16.5.1 General ............................................................................................................................260 16.5.2 Description of Reset Operation .......................................................................................260 16.6 Interrupts .......................................................................................................................................260 16.6.1 General ............................................................................................................................260 16.6.2 Description of Interrupt Operation ..................................................................................260 16.7 The Differences from TPM v2 to TPM v3 ....................................................................................262 Chapter 17 Development Support 17.1 Introduction ...................................................................................................................................267 17.1.1 Forcing Active Background ............................................................................................267 17.1.2 Features ...........................................................................................................................268 17.2 Background Debug Controller (BDC) ..........................................................................................268 17.2.1 BKGD Pin Description ...................................................................................................269 MC9S08SH8MCUSeriesDataSheet,Rev.3 16 Freescale Semiconductor

Section Number Title Page 17.2.2 Communication Details ..................................................................................................270 17.2.3 BDC Commands .............................................................................................................274 17.2.4 BDC Hardware Breakpoint .............................................................................................276 17.3 On-Chip Debug System (DBG) ....................................................................................................277 17.3.1 Comparators A and B......................................................................................................277 17.3.2 Bus Capture Information and FIFO Operation ...............................................................277 17.3.3 Change-of-Flow Information ..........................................................................................278 17.3.4 Tag vs. Force Breakpoints and Triggers .........................................................................278 17.3.5 Trigger Modes .................................................................................................................279 17.3.6 Hardware Breakpoints ....................................................................................................281 17.4 Register Definition ........................................................................................................................281 17.4.1 BDC Registers and Control Bits .....................................................................................281 17.4.2 System Background Debug Force Reset Register (SBDFR) ..........................................283 17.4.3 DBG Registers and Control Bits .....................................................................................284 Appendix A Electrical Characteristics A.1 Introduction ...................................................................................................................................289 A.2 Parameter Classification ................................................................................................................289 A.3 Absolute Maximum Ratings ..........................................................................................................289 A.4 Thermal Characteristics .................................................................................................................291 A.5 ESD Protection and Latch-Up Immunity ......................................................................................293 A.6 DC Characteristics .........................................................................................................................294 A.7 Supply Current Characteristics ......................................................................................................298 A.8 External Oscillator (XOSC) Characteristics .................................................................................301 A.9 Internal Clock Source (ICS) Characteristics .................................................................................303 A.10 Analog Comparator (ACMP) Electricals ......................................................................................305 A.11 ADC Characteristics ......................................................................................................................306 A.12 AC Characteristics .........................................................................................................................309 A.12.1 Control Timing ...............................................................................................................309 A.12.2 TPM/MTIM Module Timing ..........................................................................................311 A.12.3 SPI ...................................................................................................................................312 A.13 FLASH Specifications ...................................................................................................................315 A.14 EMC Performance .........................................................................................................................316 A.14.1 Radiated Emissions .........................................................................................................316 A.14.2 Conducted Transient Susceptibility ................................................................................316 Appendix B Ordering Information and Mechanical Drawings B.1 Ordering Information ....................................................................................................................319 B.1.1 Device Numbering Scheme ............................................................................................319 B.2 Mechanical Drawings ....................................................................................................................320 MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 17

None

Chapter 1 Device Overview The MC9S08SH8 members of the low-cost, high-performance HCS08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced HCS08 core and are available with a variety of modules, memory sizes, memory types, and package types. 1.1 Devices in the MC9S08SH8 Series Table 1-1 summarizes the feature set available in the MC9S08SH8 series of MCUs. Table1-1. MC9S08SH8 Feattures by MCU and Package Feature 9S08SH8 9S08SH4 FLASH size (bytes) 8192 4096 RAM size (bytes) 512 256 Pin quantity 24 20 16 8 24 20 16 8 ACMP yes ADC channels 12 12 8 4 12 12 8 4 DBG yes ICS yes yes yes yes1 yes yes yes yes1 IIC yes MTIM yes Pin Interrupts 8 8 8 4 8 8 8 4 Pin I/O2 17 17 13 5 17 17 13 5 RTC yes SCI yes yes yes no yes yes yes no SPI yes yes yes no yes yes yes no TPM1 channels 2 2 2 1 2 2 2 1 TPM2 channels 2 2 2 1 2 2 2 1 XOSC yes yes yes no yes yes yes no 1 FBE and FEE modes are not available in 8-pin packages. 2 Port I/O count does not include the output-only PTA4/ACMPO/BKGD/MS. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 19

Chapter1 Device Overview 1.2 MCU Block Diagram The block diagram inFigure1-1 shows the structure of the MC9S08SH8 MCU. BKGD/MS IRQ HCS08 CORE DEBUG MODULE (DBG) CPU BDC 8-BIT MODULO TIMER TCLK HCS08 SYSTEM CONTROL MODULE (MTIM) PTA5/IRQ/TCLK/RESET PTA4/ACMPO/BKGD/MS RESETS AND INTERRUPTS A MODES OF OPERATION SCL T PTA3/PAI3/SCL/ADP3 POWER MANAGEMENT IIC MODULE (IIC) SDA POR PTA2/PAI2/SDA/ADP2 COP IRQ LVD SS PTA1/PIA1/TPM2CH0/ADP1/ACMP– PTA0/PIA0/TPM1CH0/ADP0/ACMP+ MISO SERIAL PERIPHERAL MOSI INTERFACE MODULE (SPI) USER FLASH SPSCK (MC9S08SH8 =8,192 BYTES) PTB7/SCL/EXTAL (MC9S08SH4 =4096 BYTES) PTB6/SDA/XTAL SERIAL COMMUNICATIONS RxD SEE NOTE 1 INTERFACE MODULE (SCI) TxD PTB5/TPM1CH1/SS USER RAM (MC9S08SH8 =512 BYTES) TCLK T B PTB4/TPM2CH1/MISO (MC9S08SH4 =256 BYTES) 16-BIT TIMER/PWM TPM1CH0 OR PTB3/PIB3/MOSI/ADP7 P MODULE (TPM1) TPM1CH1 PTB2/PIB2/SPSCK/ADP6 REAL-TIME COUNTER (RTC) TCLK PTB1/PIB1/TxD/ADP5 16-BIT TIMER/PWM TPM2CH0 PTB0/PIB0/RxD/ADP4 40-MHz INTERNAL CLOCK SOURCE (ICS) MODULE (TPM2) TPM2CH1 SEE NOTE 1, 2 PTC3/ADP11 LOW31-P.2O5W kHEzR t oO S38C.I4L LkHATzOR EXTAL T C PTC2/ADP10 R 1 MHz to 16 MHz XTAL O PTC1/TPM1CH1/ADP9 (XOSC) P PTC0/TPM1CH0/ADP8 ACMPO SEE NOTE3 ANALOG COMPARATOR ACMP– (ACMP) ACMP+ V DD VOLTAGE REGULATOR VSS 10-BIT ADP11-ADP0 ANALOG-TO-DIGITAL V CONVERTER (ADC) DDA V SSA VREFH NOTES V REFL = Pin can be enabled as part of the ganged output drive feature NOTE1: Port B not available on 8-pinpackages NOTE2: Port C not available on 8-pin or 16-pin packages NOTE 3: V /V and V /V , are double bonded to V and V respectively. DDA REFH SSA REFL DD SS Figure1-1. MC9S08SH8 Block Diagram MC9S08SH8MCUSeriesDataSheet,Rev.3 20 Freescale Semiconductor

Chapter1 Device Overview Table1-2 provides the functional version of the on-chip modules Table1-2. Module Versions Module Version Analog Comparator (5V) (ACMP) 2 Analog-to-Digital Converter (ADC) 1 Central Processor Unit (CPU) 2 Inter-Integrated Circuit (IIC) 2 Internal Clock Source (ICS) 2 Serial Peripheral Interface (SPI) 3 Serial Communications Interface (SCI) 4 Modulo Timer (MTIM) 1 Real-Time Counter (RTC) 1 Timer Pulse Width Modulator (TPM) 3 MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 21

Chapter1 Device Overview 1.3 System Clock Distribution Figure1-2showsasimplifiedclockconnectiondiagram.SomemodulesintheMCUhaveselectableclock inputs as shown. The clock inputs to the modules indicate the clock(s) that are used to drive the module function. The following defines the clocks used in this MCU: • BUSCLK — The frequency of the bus is always half of ICSOUT. • ICSOUT — Primary output of the ICS and is twice the bus frequency. • ICSLCLK—DevelopmenttoolscanselectthisclocksourcetospeedupBDCcommunicationsin systems where the bus clock is configured to run at a very slow frequency. • ICSERCLK — External reference clock can be selected as the RTC clock source and as the alternate clock for the ADC module. • ICSIRCLK — Internal reference clock can be selected as the RTC clock source. • ICSFFCLK — Fixed frequency clock can be selected as clock source for the TPM1, TPM2 and MTIM modules. • LPOCLK—Independent1-kHzclocksourcethatcanbeselectedastheclocksourcefortheCOP and RTC modules. • TCLK—ExternalinputclocksourceforTPM1,TPM2andMTIMandisreferencedasTPMCLK in TPM chapters. TCLK 1 kHZ LPOCLK RTC COP TPM1 TPM2 MTIM SCI SPI LPO ICSERCLK ICSIRCLK ICS ICSFFCLK ÷ FFCLK* 2 SYNC* ICSOUT ÷ BUSCLK 2 ICSLCLK XOSC CPU BDC ADC IIC FLASH ADC has min and max FLASH has frequency EXTAL XTAL frequency requirements. requirementsforprogram See the ADC chapter anderaseoperation.See * The fixed frequency clock (FFCLK) is internally andelectricalsappendix the electricals appendix synchronizedtothebusclockandmustnotexceedonehalf for details. for details. of the bus clock frequency. Figure1-2. System Clock Distribution Diagram MC9S08SH8MCUSeriesDataSheet,Rev.3 22 Freescale Semiconductor

Chapter 2 Pins and Connections This section describes signals that connect to package pins. It includes pinout diagrams, recommended system connections, and detailed discussions of signals. 2.1 Device Pin Assignment Figure2-1 -Figure2-4 shows the pin assignments for the MC9S08SH8 devices. + P M C A 0/ P D A Pin 1 indicator BKGD/MS K/RESET PM1CH0 4/ACMPO/ 5/IRQ/TCL 0/PIA0/T TA TA C C C TA P P N N N P 2423 22 21 20 19 V DD 1 18 PTA1/PIA1/TPM2CH0/ADP1/ACMP– NC 2 17 PTA2/PIA2/SDA/ADP2 VSS 3 16 PTA3/PIA3/SCL/ADP3 PTB7/SCL/EXTAL 4 15 PTB0/PIB0/RxD/ADP4 PTB6/SDA/XTAL 5 14 PTB1/PIB1/TxD/ADP5 PTB5/TPM1CH1/SS 6 13 PTB2/PIB2/SPSCK/ADP6 7 8 9 10 11 12 O 1 0 9 8 7 MIS DP1 DP1 ADP ADP ADP H1/ 3/A 2/A H1/ H0/ SI/ C C C C C O 2 T T M 1 M M P P P M 3/ P T P B PTB4/T PTC1/ PTC0/T PTB3/PI Figure2-1.24-Pin QFN MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 23

Chapter2 Pins and Connections PTA5/IRQ/TCLK/RESET 1 20 PTA0/PIA0/TPM1CH0/ADP0/ACMP+ PTA4/ACMPO/BKGD/MS 2 19 PTA1/PIA1/TPM2CH0/ADP1/ACMP- VDD 3 18 PTA2/PIA2/SDA/ADP2 VSS 4 17 PTA3/PIA3/SCL/ADP3 PTB7/SCL/EXTAL 5 16 PTB0/PIB0/RxD/ADP4 PTB6/SDA/XTAL 6 15 PTB1/PIB1/TxD/ADP5 PTB5/TPM1CH1/SS 7 14 PTB2/PIB2/SPSCK/ADP6 PTB4/TPM2CH1/MISO 8 13 PTB3/PIB3/MOSI/ADP7 PTC3/ADP11 9 12 PTC0/TPM1CH0/ADP8 PTC2/ADP10 10 11 PTC1/TPM1CH1/ADP9 Figure2-2. 20-PinPDIP, SOIC, and TSSOP PTA5/IRQ/TCLK/RESET 1 16 PTA0/PIA0/TPM1CH0/ADP0/ACMP+ PTA4/ACMPO/BKGD/MS 2 15 PTA1/PIA1/TPM2CH0/ADP1/ACMP- VDD 3 14 PTA2/PIA2/SDA/ADP2 VSS 4 13 PTA3/PIA3/SCL/ADP3 PTB7/SCL/EXTAL 5 12 PTB0/PIB0/RxD/ADP4 PTB6/SDA/XTAL 6 11 PTB1/PIB1/TxD/ADP5 PTB5/TPM1CH1/SS 7 10 PTB2/PIB2/SPSCK/ADP6 PTB4/TPM2CH1/MISO 8 9 PTB3/PIB3/MOSI/ADP7 Figure2-3. 16-Pin TSSOP PTA5/IRQ/TCLK/RESET 1 8 PTA0/PIA0/TPM1CH0/ADP0/ACMP+ PTA4/ACMPO/BKGD/MS 2 7 PTA1/PIA1/TPM2CH0/ADP1/ACMP- VDD 3 6 PTA2/PIA2/SDA/ADP2 VSS 4 5 PTA3/PIA3/SCL/ADP3 Figure2-4. 8-PinSOIC 2.2 Recommended System Connections Figure2-5 shows pin connections that are common to MC9S08SH8 application systems. MC9S08SH8MCUSeriesDataSheet,Rev.3 24 Freescale Semiconductor

Chapter2 Pins and Connections BACKGROUND HEADER MC9S08SH8 BKGD/MS V DD V PTA0/PIA0/TPM1CH0/ADP0/ACMP+ DD PORT PTA1/PIA1/TPM2CH0/ADP1/ACMP- 4.7 kΩ–10 kΩ A PTA2/PIA2/SDA/ADP2 RESET PTA3/PIA3/SCL/ADP3 PTA4/ACMPO/BKGD/MS OPTIONAL 0.1μF PTA5/IRQ/TCLK/RESET MANUAL RESET PTB0/PIB0/RxD/ADP4 PTB1/PIB1/TxD/ADP5 PTC0/TPM1CH0/ADP8 PTB2/PIB2/SPSCK/ADP6 PTC1/TPM1CH1/ADP9 PORT PORT PTB3/PIB3/MOSI/ADP7 PTC2/ADP10 C B PTB4/TPM2CH1/MISO PTC3/ADP11 PTB5/TPM1CH1/SS PTB6/SDA/XTAL PTB7/SCL/EXTAL SYSTEM V POWER DD R + CBLK + CBY F RS 5 V 10μF 0.1μF V C1 X1 C2 SS NOTE 1 NOTES: 1. External crystal circuit not required if using the internal clock option. 2. RESETpincanonlybeusedtoresetintousermode,youcannotenterBDMusingRESET pin. BDM can be entered by holding MS low during POR or writing a 1 to BDFR in SBDFR with MS low after issuing BDM command. 3. RC filter onRESET pin recommended for noisy environments. Figure2-5. Basic System Connections 2.2.1 Power V and V are the primary power supply pins for the MCU. This voltage source supplies power to all DD SS I/O buffer circuitry, ACMP and ADC modules, and to an internal voltage regulator. The internal voltage regulator provides regulated lower-voltage source to the CPU and other internal circuitry of the MCU. Typically, application systems have two separate capacitors across the power pins. In this case, there shouldbeabulkelectrolyticcapacitor,suchasa10-μFtantalumcapacitor,toprovidebulkchargestorage for the overall system and a 0.1-μF ceramic bypass capacitor located as near to the MCU power pins as practical to suppress high-frequency noise. Each pin must have a bypass capacitor for best noise suppression. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 25

Chapter2 Pins and Connections 2.2.2 Oscillator (XOSC) Immediately after reset, the MCU uses an internally generated clock provided by the clock source generator (ICS) module. For more information on the ICS, seeChapter10, “Internal Clock Source (S08ICSV2).” The oscillator (XOSC) in this MCU is a Pierce oscillator that can accommodate a crystal or ceramic resonator.Ratherthanacrystalorceramicresonator,anexternaloscillatorcanbeconnectedtotheEXTAL input pin. Refer toFigure2-5 for the following discussion. R (when used) and R should be low-inductance S F resistorssuchascarboncompositionresistors.Wire-woundresistors,andsomemetalfilmresistors,have toomuchinductance.C1andC2normallyshouldbehigh-qualityceramiccapacitorsthatarespecifically designed for high-frequency applications. R isusedtoprovideabiaspathtokeeptheEXTALinputinitslinearrangeduringcrystalstartup;itsvalue F isnotgenerallycritical.Typicalsystemsuse1MΩto10MΩ.Highervaluesaresensitivetohumidityand lower values reduce gain and (in extreme cases) could prevent startup. C1andC2aretypicallyinthe5-pFto25-pFrangeandarechosentomatchtherequirementsofaspecific crystal or resonator. Be sure to take into account printed circuit board (PCB) capacitance and MCU pin capacitance when selecting C1 and C2. The crystal manufacturer typically specifies a load capacitance which is the series combination of C1 and C2 (which are usually the same size). As a first-order approximation, use 10pF as an estimate of combined pin and PCB capacitance for each oscillator pin (EXTAL and XTAL). 2.2.3 RESET After a power-on reset (POR), the PTA5/IRQ/TCLK/RESET pin defaults to a general-purpose I/O port pin, PTA5. Setting RSTPE in SOPT1 configures the pin to be the RESET pin with an open-drain drive containing an internal pull-up device. After configured as RESET, the pin will remain RESET until the nextPOR.TheRESETpinwhenenabledcanbeusedtoresettheMCUfromanexternalsourcewhenthe pin is driven low. Internalpower-onresetandlow-voltageresetcircuitrytypicallymakeexternalresetcircuitryunnecessary. This pin is normally connected to the standard 6-pin background debug connector so a development systemcandirectlyresettheMCUsystem.Ifdesired,amanualexternalresetcanbeaddedbysupplying a simple switch to ground (pull reset pin low to force a reset). Wheneveranynon-PORresetisinitiated(whetherfromanexternalsignalorfromaninternalsystem),the RESETpinifenabledisdrivenlowforabout66buscycles.Theresetcircuitrydecodesthecauseofreset and records it by setting a corresponding bit in the system reset status register (SRS). NOTE This pin does not contain a clamp diode to V and should not be driven DD above V . DD MC9S08SH8MCUSeriesDataSheet,Rev.3 26 Freescale Semiconductor

Chapter2 Pins and Connections The voltage measured on the internally pulled upRESET pin will not be pulledtoV .TheinternalgatesconnectedtothispinarepulledtoV .If DD DD theRESETpinisrequiredtodrivetoaV levelanexternalpullupshould DD be used. NOTE InEMC-sensitiveapplications,anexternalRCfilterisrecommendedonthe RESET. See Figure2-5 for an example. 2.2.4 Background / Mode Select (BKGD/MS) Duringapower-on-reset(POR)orbackgrounddebugforcereset(seeSection5.7.3,“SystemBackground Debug Force Reset Register (SBDFR),” for more information), the PTA4/ACMPO/BKGD/MS pin functions as a mode select pin. Immediately after any reset, the pin functions as the background pin and canbeusedforbackgrounddebugcommunication.WhenenabledastheBKGD/MSpin(BKGDPE=1), an internal pullup device is automatically enabled. ThebackgrounddebugcommunicationfunctionisenabledwhenBKGDPEinSOPT1isset.BKGDPEis set following any reset of the MCU and must be cleared to use the PTA4/ACMPO/BKGD/MS pin’s alternative pin function. If nothing is connected to this pin, the MCU will enter normal operating mode at the rising edge of the internal reset after a POR or force BDC reset. If a debug system is connected to the 6-pin standard background debug header, it can hold BKGD/MS low during a POR or immediately after issuing a background debug force reset, which will force the MCU to active background mode. TheBKGDpinisusedprimarilyforbackgrounddebugcontroller(BDC)communicationsusingacustom protocol that uses 16 clock cycles of the target MCU’s BDC clock per bit time. The target MCU’s BDC clock could be as fast as the maximum bus clock rate, so there must never be any significant capacitance connected to the BKGD/MS pin that could interfere with background serial communications. Although the BKGD pin is a pseudo open-drain pin, the background debug communication protocol provides brief, actively driven, high speedup pulses to ensure fast rise times. Small capacitances from cablesandtheabsolutevalueoftheinternalpullupdeviceplayalmostnoroleindeterminingriseandfall times on the BKGD pin. 2.2.5 General-Purpose I/O and Peripheral Ports TheMC9S08SH8seriesofMCUssupportupto17general-purposeI/Opinsand1output-onlypin,which are shared with on-chip peripheral functions (timers, serial I/O, ADC, etc). When a port pin is configured as a general-purpose output or a peripheral uses the port pin as an output, software can select one of two drive strengths and enable or disable slew rate control. When a port pin is configured as a general-purpose input or a peripheral uses the port pin as an input, software can enable a pull-updevice.Immediatelyafterreset,allofthesepinsareconfiguredashigh-impedancegeneral-purpose inputs with internal pull-up devices disabled. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 27

Chapter2 Pins and Connections Whenanon-chipperipheralsystemiscontrollingapin,datadirectioncontrolbitsstilldeterminewhatis read from port data registers even though the peripheral module controls the pin direction by controlling theenableforthepin’soutputbuffer.Forinformationaboutcontrollingthesepinsasgeneral-purposeI/O pins, seeChapter6, “Parallel Input/Output Control.” TheMC9S08SH8devicescontainagangedoutputdrivefeaturethatallowsasafeandreliablemethodof allowing pins to be tied together externally to produce a higher output current drive. See Section 6.3, “Ganged Output” for more information for configuring the port pins for ganged output drive. NOTE Toavoidextracurrentdrainfromfloatinginputpins,theresetinitialization routine in the application program should either enable on-chip pull-up devicesorchangethedirectionofunusedpinstooutputssotheydonotfloat. When using the 8-pin devices, the user must either enable on-chip pullup devicesorchangethedirectionofnon-bondedoutportBandportCpinsto outputs so the pins do not float. When using the 16-pin devices, the user must either enable on-chip pullup devicesorchangethedirectionofnon-bondedoutportCpinstooutputsso the pins do not float. MC9S08SH8MCUSeriesDataSheet,Rev.3 28 Freescale Semiconductor

Chapter2 Pins and Connections Table2-1. Pin Availability by Package Pin-Count Priority Pin Number Lowest Highest 24-pin 20-pin 16-pin 8-pin Port Pin Alt 1 Alt 2 Alt 3 Alt 4 Alt5 1 3 3 3 VDD 2 — — — 3 4 4 4 VSS 4 5 5 — PTB7 SCL1 EXTAL 5 6 6 — PTB6 SDA1 XTAL 6 7 7 — PTB5 TPM1CH12 SS PTC03 7 8 8 — PTB4 TPM2CH1 MISO PTC03 8 9 — — PTC3 PTC03 ADP11 9 10 — — PTC2 PTC03 ADP10 10 11 — — PTC1 TPM1CH12 PTC03 ADP9 11 12 — — PTC0 TPM1CH02 PTC03 ADP8 12 13 9 — PTB3 PIB3 MOSI PTC03 ADP7 13 14 10 — PTB2 PIB2 SPSCK PTC03 ADP6 14 15 11 — PTB1 PIB1 TxD ADP5 15 16 12 — PTB0 PIB0 RxD ADP4 16 17 13 5 PTA3 PIA3 SCL1 ADP3 17 18 14 6 PTA2 PIA2 SDA1 ADP2 18 19 15 7 PTA1 PIA1 TPM2CH0 ADP14 ACMP–4 19 20 16 8 PTA0 PIA0 TPM1CH02 ADP04 ACMP+4 20 — — — 21 — — — 22 — — — 23 1 1 1 PTA55 IRQ TCLK RESET 24 2 2 2 PTA4 ACMPO BKGD MS 1 IIC pins can be repositioned using IICPS in SOPT2, default reset locations are on PTA2 and PTA3. 2 TPM1CHx pins can be repositioned using TPM1PS in SOPT2, default reset locations are on PTA0 and PTB5. 3 This port pin is part of the ganged output feature. When pin is enabled for ganged output, it will have priority over alldigitalmodules.Theoutputdata,drivestrengthandslew-ratecontrolofthisportpinwillfollowtheconfiguration for the PTC0 pin, even in 16-pin packages where PTC0 doesn’t bond out. Ganged output not available in 8-pin packages. 4 If ACMP and ADC are both enabled, both will have access to the pin. 5 Pin is open-drain when configured as output driving high. Pin does not contain a clamp diode to V and should DD not be driven above V . The voltage measured on the internally pulled upRESET will not be pulled to V . The DD DD internal gates connected to this pin are pulled to V . DD MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 29

Chapter2 Pins and Connections MC9S08SH8MCUSeriesDataSheet,Rev.3 30 Freescale Semiconductor

Chapter 3 Modes of Operation 3.1 Introduction The operating modes of the MC9S08SH8 are described in this chapter. Entry into each mode, exit from each mode, and functionality while in each of the modes are described. 3.2 Features • Active background mode for code development • Wait mode — CPU shuts down to conserve power; system clocks are running and full regulation is maintained • Stop modes — System clocks are stopped and voltage regulator is in standby — Stop3 — All internal circuits are powered for fast recovery — Stop2 — Partial power down of internal circuits, RAM content is retained 3.3 Run Mode ThisisthenormaloperatingmodefortheMC9S08SH8.ThismodeisselectedupontheMCUexitingreset iftheBKGD/MSpinishigh.Inthismode,theCPUexecutescodefrominternalmemorywithexecution beginning at the address fetched from memory at 0xFFFE–0xFFFF after reset. 3.4 Active Background Mode The active background mode functions are managed through the background debug controller (BDC) in the HCS08 core. The BDC, together with the on-chip debug module (DBG), provide the means for analyzing MCU operation during software development. Active background mode is entered in any of the following ways: • When the BKGD/MS pin is low during POR or immediately after issuing a background debug force reset (seeSection 5.7.3, “System Background Debug Force Reset Register (SBDFR)”) • When a BACKGROUND command is received through the BKGD/MS pin • When a BGND instruction is executed • When encountering a BDC breakpoint • When encountering a DBG breakpoint Afterenteringactivebackgroundmode,theCPUisheldinasuspendedstatewaitingforserialbackground commands rather than executing instructions from the user application program. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 31

Chapter3 Modes of Operation Background commands are of two types: • Non-intrusive commands, defined as commands that can be issued while the user program is running.Non-intrusivecommandscanbeissuedthroughtheBKGD/MSpinwhiletheMCUisin run mode; non-intrusive commands can also be executed when the MCU is in the active background mode. Non-intrusive commands include: — Memory access commands — Memory-access-with-status commands — BDC register access commands — The BACKGROUND command • Activebackgroundcommands,whichcanonlybeexecutedwhiletheMCUisinactivebackground mode. Active background commands include commands to: — Read or write CPU registers — Trace one user program instruction at a time — Leave active background mode to return to the user application program (GO) TheactivebackgroundmodeisusedtoprogramabootloaderoruserapplicationprogramintotheFLASH program memory before the MCU is operated in run mode for the first time. When the MC9S08SH8 is shipped from the Freescale Semiconductor factory, the FLASH program memory is erased by default unless specifically noted so there is no program that could be executed in run mode until the FLASH memory is initially programmed. The active background mode can also be used to erase and reprogram the FLASH memory after it has been previously programmed. For additional information about the active background mode, refer to the Development Support chapter. 3.5 Wait Mode WaitmodeisenteredbyexecutingaWAITinstruction.UponexecutionoftheWAITinstruction,theCPU enters a low-power state in which it is not clocked. The I bit in CCR is cleared when the CPU enters the wait mode, enabling interrupts. When an interrupt request occurs, the CPU exits the wait mode and resumes processing, beginning with the stacking operations leading to the interrupt service routine. While the MCU is in wait mode, there are some restrictions on which background debug commands can be used. Only the BACKGROUND command and memory-access-with-status commands are available whentheMCUisinwaitmode.Thememory-access-with-statuscommandsdonotallowmemoryaccess, but they report an error indicating that the MCU is in either stop or wait mode. The BACKGROUND command can be used to wake the MCU from wait mode and enter active background mode. 3.6 Stop Modes One of two stop modes is entered upon execution of a STOP instruction when STOPE in SOPT1. In any stop mode, the bus and CPU clocks are halted. The ICS module can be configured to leave the reference clocks running. SeeChapter10, “Internal Clock Source (S08ICSV2),” for more information. MC9S08SH8MCUSeriesDataSheet,Rev.3 32 Freescale Semiconductor

Chapter3 Modes of Operation Table3-1showsallofthecontrolbitsthataffectstopmodeselectionandthemodeselectedundervarious conditions. The selected mode is entered following the execution of a STOP instruction. Table3-1. Stop Mode Selection STOPE ENBDM1 LVDE LVDSE PPDC Stop Mode 0 x x x Stop modes disabled; illegal opcode reset if STOP instruction executed 1 1 x x Stop3 with BDM enabled2 1 0 Bothbitsmustbe1 0 Stop3 with voltage regulator active 1 0 Either bit a 0 0 Stop3 1 0 Either bit a 0 1 Stop2 1 ENBDMislocatedintheBDCSCR,whichisonlyaccessiblethroughBDCcommands,seeSection17.4.1.1,“BDCStatusand Control Register (BDCSCR)”. 2 When in Stop3 mode with BDM enabled, The S will be near R levels because internal clocks are enabled. IDD IDD 3.6.1 Stop3 Mode Stop3 mode is entered by executing a STOP instruction under the conditions as shown in Table 3-1. The states of all of the internal registers and logic, RAM contents, and I/O pin states are maintained. Stop3canbeexitedbyassertingRESETifenabled,orbyaninterruptfromoneofthefollowingsources: the real-time counter (RTC), LVD system, ACMP, ADC,SCI, IRQ, or any pin interrupts. Ifstop3isexitedbymeansoftheRESETpin,thentheMCUisresetandoperationwillresumeaftertaking the reset vector. Exit by means of one of the internal interrupt sources results in the MCU taking the appropriate interrupt vector. 3.6.1.1 LVD Enabled in Stop Mode TheLVDsystemiscapableofgeneratingeitheraninterruptoraresetwhenthesupplyvoltagedropsbelow theLVDvoltage.ForconfiguringtheLVDsystemforinterruptorreset,referto5.6,“Low-VoltageDetect (LVD) System”. If the LVD is enabled in stop (LVDE and LVDSE bits in SPMSC1 both set) at the time the CPU executes a STOP instruction, then the voltage regulator remains active during stop mode. For the ADC to operate in stop mode, the LVD must be enabled when entering stop3. FortheACMPtooperateinstopmodewithcomparetointernalbandgapoption,theLVDmustbeenabled when entering stop3. 3.6.1.2 Active BDM Enabled in Stop Mode Entry into the active background mode from run mode is enabled if ENBDM in BDCSCR is set. This register is described inChapter17, “Development Support.” If ENBDM is set when the CPU executes a STOP instruction, the system clocks to the background debug logic remain active when the MCU enters stopmode.Becauseofthis,backgrounddebugcommunicationremainspossible.Inaddition,thevoltage regulator does not enter its low-power standby state but maintains full internal regulation. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 33

Chapter3 Modes of Operation Most background commands are not available in stop mode. The memory-access-with-status commands do not allow memory access, but they report an error indicating that the MCU is in either stop or wait mode. The BACKGROUND command can be used to wake the MCU from stop and enter active background mode if the ENBDM bit is set. After entering background debug mode, all background commands are available. 3.6.2 Stop2 Mode Stop2modeisenteredbyexecutingaSTOPinstructionundertheconditionsasshowninTable 3-1.Most oftheinternalcircuitryoftheMCUispoweredoffinstop2withtheexceptionoftheRAM.Uponentering stop2, all I/O pin control signals are latched so that the pins retain their states during stop2. Exit from stop2 is performed by asserting the wake-up pin (PTA5/IRQ/TCLK/RESET) on the MCU. In addition, the real-time counter (RTC) can wake the MCU from stop2, if enabled. Upon wake-up from stop2 mode, the MCU starts up as from a power-on reset (POR): • All module control and status registers are reset • TheLVDresetfunctionisenabledandtheMCUremainsintheresetstateifV isbelowtheLVD DD trip point (low trip point selected due to POR) • The CPU takes the reset vector Inadditiontotheabove,uponwakingupfromstop2,thePPDFbitinSPMSC2isset.Thisflagisusedto directusercodetogotoastop2recoveryroutine.PPDFremainssetandtheI/Opinstatesremainlatched until a 1 is written to PPDACK in SPMSC2. TomaintainI/Ostatesforpinsthatwereconfiguredasgeneral-purposeI/Obeforeenteringstop2,theuser must restore the contents of the I/O port registers, which have been saved in RAM, to the port registers before writing to the PPDACK bit. If the port registers are not restored from RAM before writing to PPDACK, then the pins will switch to their reset states when PPDACK is written. For pins that were configured as peripheral I/O, the user must reconfigure the peripheral module that interfaces to the pin before writing to the PPDACK bit. If the peripheral module is not enabled before writing to PPDACK, the pins will be controlled by their associated port control registers when the I/O latches are opened. 3.6.3 On-Chip Peripheral Modules in Stop Modes WhentheMCUentersanystopmode,systemclockstotheinternalperipheralmodulesarestopped.Even in the exception case (ENBDM=1), where clocks to the background debug logic continue to operate, clocks to the peripheral systems are halted to reduce power consumption. Refer to Section 3.6.2, “Stop2 Mode,” andSection 3.6.1, “Stop3 Mode,” for specific information on system behavior in stop modes. MC9S08SH8MCUSeriesDataSheet,Rev.3 34 Freescale Semiconductor

Chapter3 Modes of Operation Table3-2. Stop Mode Behavior Mode Peripheral Stop2 Stop3 CPU Off Standby RAM Standby Standby FLASH Off Standby Parallel Port Registers Off Standby ADC Off Optionally On1 ACMP Off Optionally On2 BDM Off3 Optionally On ICS Off Optionally On4 IIC Off Standby LVD/LVW Off5 Optionally On MTIM Off Standby RTC Optionally On Optionally On SCI Off Standby SPI Off Standby TPM Off Standby Voltage Regulator Standby Optionally On6 XOSC Off Optionally On7 I/O Pins States Held States Held 1 Requires the asynchronous ADC clock and LVD to be enabled, else in standby. 2 RequirestheLVDtobeenabledwhencomparetointernalbangapreference option is enabled. 3 If ENBDM is set when entering stop2, the MCU will actually enter stop3.. 4 IRCLKEN and IREFSTEN set in ICSC1, else in standby. 5 If LVDSE is set when entering stop2, the MCU will actually enter stop3.. 6 Voltage regulator will be on if BDM is enabled or if LVD is enabled when entering stop3. 7 ERCLKENandEREFSTENsetinICSC2,elseinstandby.Forhighfrequency range (RANGE in ICSC2 set) requires the LVD to also be enabled in stop3. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 35

Chapter3 Modes of Operation MC9S08SH8MCUSeriesDataSheet,Rev.3 36 Freescale Semiconductor

Chapter 4 Memory 4.1 MC9S08SH8 Memory Map AsshowninFigure4-1,on-chipmemoryintheMC9S08SH8seriesofMCUsconsistsofRAM,FLASH program memory for nonvolatile data storage, and I/O and control/status registers. The registers are divided into three groups: • Direct-page registers (0x0000 through 0x007F) • High-page registers (0x1800 through 0x185F) • Nonvolatile registers (0xFFB0 through 0xFFBF) 0x0000 0x0000 DIRECT PAGE REGISTERS DIRECT PAGE REGISTERS 0x007F 0x007F 0x0080 0x0080 RAM RAM 256 BYTES 0x017F 512 BYTES 0x0180 RESERVED 0x027F 0x027F 256 BYTES 0x0280 UNIMPLEMENTED 0x0280 UNIMPLEMENTED 0x17FF 5504 BYTES 0x17FF 5504 BYTES 0x1800 0x1800 HIGH PAGE REGISTERS HIGH PAGE REGISTERS 0x185F 0x185F 0x1860 0x1860 UNIMPLEMENTED UNIMPLEMENTED 51,104 BYTES 51,104 BYTES 0xDFFF 0xDFFF 0xE000 0xE000 RESERVED FLASH 4096 BYTES 0xEFFF 8192 BYTES 0xF000 FLASH 4096 BYTES 0xFFFF 0xFFFF MC9S08SH8 MC9S08SH4 Figure4-1. MC9S08SH8 Memory Map MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 37

Chapter4 Memory 4.2 Reset and Interrupt Vector Assignments Table4-1showsaddressassignmentsforresetandinterruptvectors.Thevectornamesshowninthistable are the labels used in the Freescale Semiconductor provided equate file for the MC9S08SH8. Table4-1. Reset and Interrupt Vectors Address Vector Vector Name (High/Low) 0xFFC0:0xFFC1 Reserved — 0xFFC2:0xFFC3 ACMP Vacmp 0xFFC4:0xFFC5 Reserved — 0xFFC6:0xFFC7 Reserved — 0xFFC8:0xFFC9 Reserved — 0xFFCA:0xFFCB MTIM Overflow Vmtim 0xFFCC:0xFFCD RTC Vrtc 0xFFCE:0xFFCF IIC Viic 0xFFD0:0xFFD1 ADC Conversion Vadc 0xFFD2:0xFFD3 Reserved — 0xFFD4:0xFFD5 Port B Pin Interrupt Vportb 0xFFD6:0xFFD7 Port A Pin Interrupt Vporta 0xFFD8:0xFFD9 Reserved — 0xFFDA:0xFFDB SCI Transmit Vscitx 0xFFDC:0xFFDD SCI Receive Vscirx 0xFFDE:0xFFDF SCI Error Vscierr 0xFFE0:0xFFE1 SPI Vspi 0xFFE2:0xFFE3 TPM2 Overflow Vtpm2ovf 0xFFE4:0xFFE5 TPM2 Channel 1 Vtpm2ch1 0xFFE6:0xFFE7 TPM2 Channel 0 Vtpm2ch0 0xFFE8:0xFFE9 TPM1 Overflow Vtpm1ovf 0xFFEA:0xFFEB Reserved — 0xFFEC:0xFFED Reserved — 0xFFEE:0xFFEF Reserved — 0xFFF0:0xFFF1 Reserved — 0xFFF2:0xFFF3 TPM1 Channel 1 Vtpm1ch1 0xFFF4:0xFFF5 TPM1 Channel 0 Vtpm1ch0 0xFFF6:0xFFF7 Reserved — 0xFFF8:0xFFF9 Low Voltage Detect Vlvd 0xFFFA:0xFFFB IRQ Virq 0xFFFC:0xFFFD SWI Vswi 0xFFFE:0xFFFF Reset Vreset MC9S08SH8MCUSeriesDataSheet,Rev.3 38 Freescale Semiconductor

Chapter4 Memory 4.3 Register Addresses and Bit Assignments The registers in the MC9S08SH8 are divided into these groups: • Direct-pageregistersarelocatedinthefirst128locationsinthememorymap;theseareaccessible with efficient direct addressing mode instructions. • High-page registers are used much less often, so they are located above 0x1800 in the memory map. This leaves more room in the direct page for more frequently used registers and RAM. • The nonvolatile register area consists of a block of 16locations in FLASH memory at 0xFFB0–0xFFBF. Nonvolatile register locations include: — NVPROT and NVOPT are loaded into working registers at reset — An 8-byte backdoor comparison key that optionally allows a user to gain controlled access to secure memory Because the nonvolatile register locations are FLASH memory, they must be erased and programmed like other FLASH memory locations. Direct-pageregisterscanbeaccessedwithefficientdirectaddressingmodeinstructions.Bitmanipulation instructions can be used to access any bit in any direct-page register. Table4-2 is a summary of all user-accessible direct-page registers and control bits. The direct page registers in Table 4-2 can use the more efficient direct addressing mode, which requires onlythelowerbyteoftheaddress.Becauseofthis,thelowerbyteoftheaddressincolumnoneisshown in bold text. InTable4-3 andTable4-4, the whole address in column one is shown in bold. In Table4-2, Table4-3, andTable4-4, the register names in column two are shown in bold to set them apart from the bit names to the right. Cells that are not associated with named bits are shaded. A shaded cell with a 0 indicates this unused bit always reads as a 0. Shaded cells with dashes indicate unused or reserved bit locations that could read as 1s or 0s. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 39

Chapter4 Memory Table4-2. Direct-Page Register Summary (Sheet 1 of 3) Register Address Bit 7 6 5 4 3 2 1 Bit 0 Name 0x0000 PTAD 0 0 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0 0x0001 PTADD 0 0 PTADD5 PTADD4 PTADD3 PTADD2 PTADD1 PTADD0 0x0002 PTBD PTBD7 PTBD6 PTBD5 PTBD4 PTBD3 PTBD2 PTBD1 PTBD0 0x0003 PTBDD PTBDD7 PTBDD6 PTBDD5 PTBDD4 PTBDD3 PTBDD2 PTBDD1 PTBDD0 0x0004 PTCD 0 0 0 0 PTCD3 PTCD2 PTCD1 PTCD0 0x0005 PTCDD 0 0 0 0 PTCDD3 PTCDD2 PTCDD1 PTCDD0 0x0006– — — — — — — — — Reserved 0x000D — — — — — — — — 0x000E ACMPSC ACME ACBGS ACF ACIE ACO ACOPE ACMOD1 ACMOD0 0x000F Reserved — — — — — — — — 0x0010 ADSC1 COCO AIEN ADCO ADCH 0x0011 ADSC2 ADACT ADTRG ACFE ACFGT — — — — 0x0012 ADRH 0 0 0 0 0 0 ADR9 ADR8 0x0013 ADRL ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 0x0014 ADCVH 0 0 0 0 0 0 ADCV9 ADCV8 0x0015 ADCVL ADCV7 ADCV6 ADCV5 ADCV4 ADCV3 ADCV2 ADCV1 ADCV0 0x0016 ADCFG ADLPC ADIV ADLSMP MODE ADICLK 0x0017 APCTL1 ADPC7 ADPC6 ADPC5 ADPC4 ADPC3 ADPC2 ADPC1 ADPC0 0x0018 APCTL2 0 0 0 0 ADPC11 ADPC10 ADPC9 ADPC8 0x0019 Reserved — — — — — — — — 0x001A IRQSC 0 IRQPDD IRQEDG IRQPE IRQF IRQACK IRQIE IRQMOD 0x001B Reserved — — — — — — — — 0x001C MTIMSC TOF TOIE TRST TSTP 0 0 0 0 0x001D MTIMCLK 0 0 CLKS PS 0x001E MTIMCNT CNT 0x001F MTIMMOD MOD 0x0020 TPM1SC TOF TOIE CPWMS CLKSB CLKSA PS2 PS1 PS0 0x0021 TPM1CNTH Bit 15 14 13 12 11 10 9 Bit 8 0x0022 TPM1CNTL Bit 7 6 5 4 3 2 1 Bit 0 0x0023 TPM1MODH Bit 15 14 13 12 11 10 9 Bit 8 0x0024 TPM1MODL Bit 7 6 5 4 3 2 1 Bit 0 0x0025 TPM1C0SC CH0F CH0IE MS0B MS0A ELS0B ELS0A 0 0 0x0026 TPM1C0VH Bit 15 14 13 12 11 10 9 Bit 8 0x0027 TPM1C0VL Bit 7 6 5 4 3 2 1 Bit 0 0x0028 TPM1C1SC CH1F CH1IE MS1B MS1A ELS1B ELS1A 0 0 0x0029 TPM1C1VH Bit 15 14 13 12 11 10 9 Bit 8 0x002A TPM1C1VL Bit 7 6 5 4 3 2 1 Bit 0 0x002B– — — — — — — — — Reserved 0x0037 — — — — — — — — MC9S08SH8MCUSeriesDataSheet,Rev.3 40 Freescale Semiconductor

Chapter4 Memory Table4-2. Direct-Page Register Summary (Sheet 2 of 3) Register Address Bit 7 6 5 4 3 2 1 Bit 0 Name 0x0038 SCIBDH LBKDIE RXEDGIE 0 SBR12 SBR11 SBR10 SBR9 SBR8 0x0039 SCIBDL SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 0x003A SCIC1 LOOPS SCISWAI RSRC M WAKE ILT PE PT 0x003B SCIC2 TIE TCIE RIE ILIE TE RE RWU SBK 0x003C SCIS1 TDRE TC RDRF IDLE OR NF FE PF 0x003D SCIS2 LBKDIF RXEDGIF 0 RXINV RWUID BRK13 LBKDE RAF 0x003E SCIC3 R8 T8 TXDIR TXINV ORIE NEIE FEIE PEIE 0x003F SCID Bit 7 6 5 4 3 2 1 Bit 0 0x0040– — — — — — — — — Reserved 0x0047 — — — — — — — — 0x0048 ICSC1 CLKS RDIV IREFS IRCLKEN IREFSTEN 0x0049 ICSC2 BDIV RANGE HGO LP EREFS ERCLKEN EREFSTEN 0x004A ICSTRM TRIM 0x004B ICSSC 0 0 0 IREFST CLKST OSCINIT FTRIM 0x004C– — — — — — — — — Reserved 0x004F — — — — — — — — 0x0050 SPIC1 SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE 0x0051 SPIC2 0 0 0 MODFEN BIDIROE 0 SPISWAI SPC0 0x0052 SPIBR 0 SPPR2 SPPR1 SPPR0 0 SPR2 SPR1 SPR0 0x0053 SPIS SPRF 0 SPTEF MODF 0 0 0 0 0x0054 Reserved 0 0 0 0 0 0 0 0 0x0055 SPID Bit 7 6 5 4 3 2 1 Bit 0 0x0056– — — — — — — — — Reserved 0x0057 — — — — — — — — 0x0058 IICA AD7 AD6 AD5 AD4 AD3 AD2 AD1 0 0x0059 IICF MULT ICR 0x005A IICC1 IICEN IICIE MST TX TXAK RSTA 0 0 0x005B IICS TCF IAAS BUSY ARBL 0 SRW IICIF RXAK 0x005C IICD DATA 0x005D IICC2 GCAEN ADEXT 0 0 0 AD10 AD9 AD8 0x005E– — — — — — — — — Reserved 0x005F — — — — — — — — 0x0060 TPM2SC TOF TOIE CPWMS CLKSB CLKSA PS2 PS1 PS0 0x0061 TPM2CNTH Bit 15 14 13 12 11 10 9 Bit 8 0x0062 TPM2CNTL Bit 7 6 5 4 3 2 1 Bit 0 0x0063 TPM2MODH Bit 15 14 13 12 11 10 9 Bit 8 0x0064 TPM2MODL Bit 7 6 5 4 3 2 1 Bit 0 0x0065 TPM2C0SC CH0F CH0IE MS0B MS0A ELS0B ELS0A 0 0 0x0066 TPM2C0VH Bit 15 14 13 12 11 10 9 Bit 8 0x0067 TPM2C0VL Bit 7 6 5 4 3 2 1 Bit 0 MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 41

Chapter4 Memory Table4-2. Direct-Page Register Summary (Sheet 3 of 3) Register Address Bit 7 6 5 4 3 2 1 Bit 0 Name 0x0068 TPM2C1SC CH1F CH1IE MS1B MS1A ELS1B ELS1A 0 0 0x0069 TPM2C1VH Bit 15 14 13 12 11 10 9 Bit 8 0x006A TPM2C1VL Bit 7 6 5 4 3 2 1 Bit 0 0x006B Reserved — — — — — — — — 0x006C RTCSC RTIF RTCLKS RTIE RTCPS 0x006D RTCCNT RTCCNT 0x006E RTCMOD RTCMOD 0x006F - — — — — — — — — Reserved 0x007F — — — — — — — — MC9S08SH8MCUSeriesDataSheet,Rev.3 42 Freescale Semiconductor

Chapter4 Memory High-pageregisters,showninTable4-3,areaccessedmuchlessoftenthanotherI/Oandcontrolregisters so they have been located outside the direct addressable memory space, starting at 0x1800. Table4-3. High-Page Register Summary (Sheet 1 of 2) Address Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x1800 SRS POR PIN COP ILOP ILAD 0 LVD 0 0x1801 SBDFR 0 0 0 0 0 0 0 BDFR 0x1802 SOPT1 COPT STOPE 0 0 IICPS BKGDPE RSTPE 0x1803 SOPT2 COPCLKS COPW 0 ACIC 0 0 T1CH1PS T1CH0PS 0x1804– — — — — — — — — Reserved 0x1805 — — — — — — — — 0x1806 SDIDH 0 — — — ID11 ID10 ID9 ID8 0x1807 SDIDL ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 0x1808 Reserved — — — — — — — — 0x1809 SPMSC1 LVWF LVWACK LVWIE LVDRE LVDSE LVDE 0 BGBE 0x180A SPMSC2 0 0 LVDV LVWV PPDF PPDACK — PPDC 0x180B– — — — — — — — — Reserved 0x180F — — — — — — — — 0x1810 DBGCAH Bit 15 14 13 12 11 10 9 Bit 8 0x1811 DBGCAL Bit 7 6 5 4 3 2 1 Bit 0 0x1812 DBGCBH Bit 15 14 13 12 11 10 9 Bit 8 0x1813 DBGCBL Bit 7 6 5 4 3 2 1 Bit 0 0x1814 DBGFH Bit 15 14 13 12 11 10 9 Bit 8 0x1815 DBGFL Bit 7 6 5 4 3 2 1 Bit 0 0x1816 DBGC DBGEN ARM TAG BRKEN RWA RWAEN RWB RWBEN 0x1817 DBGT TRGSEL BEGIN 0 0 TRG3 TRG2 TRG1 TRG0 0x1818 DBGS AF BF ARMF 0 CNT3 CNT2 CNT1 CNT0 0x1819– — — — — — — — — Reserved 0x181F — — — — — — — — 0x1820 FCDIV DIVLD PRDIV8 DIV 0x1821 FOPT KEYEN FNORED 0 0 0 0 SEC 0x1822 Reserved — — — — — — — — 0x1823 FCNFG 0 0 KEYACC 0 0 0 0 0 0x1824 FPROT FPS FPDIS 0x1825 FSTAT FCBEF FCCF FPVIOL FACCERR 0 FBLANK 0 0 0x1826 FCMD FCMD 0x1827– — — — — — — — — Reserved 0x183F — — — — — — — — 0x1840 PTAPE 0 0 PTAPE5 PTAPE4 PTAPE3 PTAPE2 PTAPE1 PTAPE0 0x1841 PTASE 0 0 — PTASE4 PTASE3 PTASE2 PTASE1 PTASE0 0x1842 PTADS 0 0 — PTADS4 PTADS3 PTADS2 PTADS1 PTADS0 0x1843 Reserved — — — — — — — — 0x1844 PTASC 0 0 0 0 PTAIF PTAACK PTAIE PTAMOD MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 43

Chapter4 Memory Table4-3. High-Page Register Summary (Sheet 2 of 2) Address Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x1845 PTAPS 0 0 0 PTAPS4 PTAPS3 PTAPS2 PTAPS1 PTAPS0 0x1846 PTAES 0 0 0 PTAES4 PTAES3 PTAES2 PTAES1 PTAES0 0x1847 Reserved — — — — — — — — 0x1848 PTBPE PTBPE7 PTBPE6 PTBPE5 PTBPE4 PTBPE3 PTBPE2 PTBPE1 PTBPE0 0x1849 PTBSE PTBSE7 PTBSE6 PTBSE5 PTBSE4 PTBSE3 PTBSE2 PTBSE1 PTBSE0 0x184A PTBDS PTBDS7 PTBDS6 PTBDS5 PTBDS4 PTBDS3 PTBDS2 PTBDS1 PTBDS0 0x184B Reserved — — — — — — — — 0x184C PTBSC 0 0 0 0 PTBIF PTBACK PTBIE PTBMOD 0x184D PTBPS 0 0 0 0 PTBPS3 PTBPS2 PTBPS1 PTBPS0 0x184E PTBES 0 0 0 0 PTBES3 PTBES2 PTBES1 PTBES0 0x184F Reserved — — — — — — — — 0x1850 PTCPE 0 0 0 0 PTCPE3 PTCPE2 PTCPE1 PTCPE0 0x1851 PTCSE 0 0 0 0 PTCSE3 PTCSE2 PTCSE1 PTCSE0 0x1852 PTCDS 0 0 0 0 PTCDS3 PTCDS2 PTCDS1 PTCDS0 0x1853 GNGC GNGPS7 GNGPS6 GNGPS5 GNGPS4 GNGPS3 GNGPS2 GNGPS1 GNGEN 0x1854– — — — — — — — — Reserved 0x185F — — — — — — — — MC9S08SH8MCUSeriesDataSheet,Rev.3 44 Freescale Semiconductor

Chapter4 Memory Nonvolatile FLASH registers, shown inTable 4-4, are located in the FLASH memory. These registers include an 8-byte backdoor key, NVBACKKEY, which can be used to gain access to secure memory resources.Duringresetevents,thecontentsofNVPROTandNVOPTinthenonvolatileregisterareaofthe FLASHmemoryaretransferredintocorrespondingFPROTandFOPTworkingregistersinthehigh-page registers to control security and block protection options. Table4-4. Nonvolatile Register Summary Address Register Name Bit 7 6 5 4 3 2 1 Bit 0 0xFFAE Reserved for 0 0 0 0 0 0 0 FTRIM storage of FTRIM 0xFFAF Reserved for storage of TRIM ICSTRIM 0xFFB0 – NVBACKKEY 8-Byte Comparison Key 0xFFB7 0xFFB8 – Reserved — — — — — — — — 0xFFBC — — — — — — — — 0xFFBD NVPROT FPS FPDIS 0xFFBE Reserved — — — — — — — — 0xFFBF NVOPT KEYEN FNORED 0 0 0 0 SEC Provided the key enable (KEYEN) bit is 1, the 8-byte comparison key can be used to temporarily disengagememorysecurity.Thiskeymechanismcanbeaccessedonlythroughusercoderunninginsecure memory.(Asecuritykeycannotbeentereddirectlythroughbackgrounddebugcommands.)Thissecurity key can be disabled completely by programming the KEYEN bit to 0. If the security key is disabled, the onlywaytodisengagesecurityisbymasserasingtheFLASHifneeded(normallythroughthebackground debuginterface)andverifyingthatFLASHisblank.Toavoidreturningtosecuremodeafterthenextreset, program the security bits (SEC) to the unsecured state (1:0). MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 45

Chapter4 Memory 4.4 RAM The MC9S08SH8 includes static RAM. The locations in RAM below 0x0100 can be accessed using the more efficient direct addressing mode, and any single bit in this area can be accessed with the bit manipulation instructions (BCLR, BSET, BRCLR, and BRSET). Locating the most frequently accessed program variables in this area of RAM is preferred. The RAM retains data when the MCU is in low-power wait, stop2, or stop3 mode. At power-on the contentsofRAMareuninitialized.RAMdataisunaffectedbyanyresetprovidedthatthesupplyvoltage does not drop below the minimum value for RAM retention (V ). RAM For compatibility with M68HC05 MCUs, the HCS08 resets the stack pointer to 0x00FF. In the MC9S08SH8, it is usually best to reinitialize the stack pointer to the top of the RAM so the direct page RAMcanbeusedforfrequentlyaccessedRAMvariablesandbit-addressableprogramvariables.Include thefollowing2-instructionsequenceinyourresetinitializationroutine(whereRamLastisequatedtothe highest address of the RAM in the Freescale Semiconductor-provided equate file). LDHX #RamLast+1 ;point one past RAM TXS ;SP<-(H:X-1) Whensecurityisenabled,theRAMisconsideredasecurememoryresourceandisnotaccessiblethrough BDM or through code executing from non-secure memory. See Section 4.6, “Security”, for a detailed description of the security feature. 4.5 FLASH The FLASH memory is intended primarily for program storage. In-circuit programming allows the operating program to be loaded into the FLASH memory after final assembly of the application product. Itispossibletoprogramtheentirearraythroughthesingle-wirebackgrounddebuginterface.Becauseno special voltages are needed for FLASH erase and programming operations, in-application programming isalsopossiblethroughothersoftware-controlledcommunicationpaths.Foramoredetaileddiscussionof in-circuit and in-application programming, refer to theHCS08 Family Reference Manual, Volume I, Freescale Semiconductor document order number HCS08RMv1/D. MC9S08SH8MCUSeriesDataSheet,Rev.3 46 Freescale Semiconductor

Chapter4 Memory 4.5.1 Features Features of the FLASH memory include: • FLASH size — MC9S08SH8: 8,192 bytes (16 pages of 512 bytes each) — MC9S08SH4: 4,096 bytes (8 pages of 512 bytes each) • Single power supply program and erase • Command interface for fast program and erase operation • Up to 100,000 program/erase cycles at typical voltage and temperature • Flexible block protection • Security feature for FLASH and RAM • Auto power-down for low-frequency read accesses 4.5.2 Program and Erase Times Beforeanyprogramorerasecommandcanbeaccepted,theFLASHclockdividerregister(FCDIV)must be written to set the internal clock for the FLASH module to a frequency (f ) between 150kHz and FCLK 200kHz(seeSection4.7.1,“FLASHClockDividerRegister(FCDIV)”).Thisregistercanbewrittenonly once,sonormallythiswriteisdoneduringresetinitialization.FCDIVcannotbewritteniftheaccesserror flag, FACCERR in FSTAT, is set. The user must ensure that FACCERR is not set before writing to the FCDIV register. One period of the resulting clock (1/f ) is used by the command processor to time FCLK program and erase pulses. An integer number of these timing pulses are used by the command processor to complete a program or erase command. Table4-5showsprogramanderasetimes.ThebusclockfrequencyandFCDIVdeterminethefrequency ofFCLK(f ).ThetimeforonecycleofFCLKist =1/f .Thetimesareshownasanumber FCLK FCLK FCLK of cycles of FCLK and as an absolute time for the case where t = 5μs. Program and erase times FCLK shownincludeoverheadforthecommandstatemachineandenablinganddisablingofprogramanderase voltages. Table4-5. Program and Erase Times Parameter Cycles of FCLK Time if FCLK=200kHz Byte program 9 45μs Byte program (burst) 4 20μs1 Page erase 4000 20ms Mass erase 20,000 100ms 1 Excluding start/end overhead MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 47

Chapter4 Memory 4.5.3 Program and Erase Command Execution Thestepsforexecutinganyofthecommandsarelistedbelow.TheFCDIVregistermustbeinitializedand any error flags cleared before beginning command execution. The command execution steps are: 1. Write a data value to an address in the FLASH array. The address and data information from this write is latched into the FLASH interface. This write is a required first step in any command sequence. For erase and blank check commands, the value of the data is not important. For page erasecommands,theaddressmaybeanyaddressinthe512-bytepageofFLASHtobeerased.For mass erase and blank check commands, the address can be any address in the FLASH memory. Whole pages of 512bytes are the smallest block of FLASH that may be erased. NOTE Do not program any byte in the FLASH more than once after a successful erase operation. Reprogramming bits to a byte that is already programmed is not allowed without first erasing the page in which the byte resides or masserasingtheentireFLASHmemory.Programmingwithoutfirsterasing may disturb data stored in the FLASH. 2. WritethecommandcodeforthedesiredcommandtoFCMD.Thefivevalidcommandsareblank check (0x05), byte program (0x20), burst program (0x25), page erase (0x40), and mass erase (0x41). The command code is latched into the command buffer. 3. Write a 1 to the FCBEF bit in FSTAT to clear FCBEF and launch the command (including its address and data information). Apartialcommandsequencecanbeabortedmanuallybywritinga0toFCBEFanytimeafterthewriteto the memory array and before writing the 1 that clears FCBEF and launches the complete command. Aborting a command in this way sets the FACCERR access error flag, which must be cleared before starting a new command. Astrictlymonitoredproceduremustbeobeyedorthecommandwillnotbeaccepted.Thisminimizesthe possibility of any unintended changes to the FLASH memory contents. The command complete flag (FCCF) indicates when a command is complete. The command sequence must be completed by clearing FCBEF to launch the command.Figure4-2 is a flowchart for executing all of the commands except for burst programming. The FCDIV register must be initialized before using any FLASH commands. This must be done only once following a reset. MC9S08SH8MCUSeriesDataSheet,Rev.3 48 Freescale Semiconductor

Chapter4 Memory WRITE TO FCDIV (Note 1) Note 1: Required only once after reset. FLASH PROGRAM AND ERASE FLOW START 0 FACCERR ? 1 CLEAR ERROR WRITE TO FLASH TO BUFFER ADDRESS AND DATA WRITE COMMAND TO FCMD WRITE 1 TO FCBEF Note 2: Wait at least four bus cycles TO LAUNCH COMMAND before checking FCBEF or FCCF. AND CLEAR FCBEF (Note 2) FPVIOL OR YES ERROR EXIT FACCERR ? NO 0 FCCF ? 1 DONE Figure4-2. FLASH Program and Erase Flowchart 4.5.4 Burst Program Execution The burst program command is used to program sequential bytes of data in less time than would be required using the standard program command. This is possible because the high voltage to the FLASH array does not need to be disabled between program operations. Ordinarily, when a program or erase command is issued, an internal charge pump associated with the FLASH memory must be enabled to supplyhighvoltagetothearray.Uponcompletionofthecommand,thechargepumpisturnedoff.When aburstprogramcommandisissued,thechargepumpisenabledandthenremainsenabledaftercompletion of the burst program operation if these two conditions are met: • The next burst program command has been queued before the current program operation has completed. • The next sequential address selects a byte on the same physical row as the current byte being programmed. A row of FLASH memory consists of 64 bytes. A byte within a row is selected by addresses A5 through A0. A new row begins when addresses A5 through A0 are all zero. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 49

Chapter4 Memory The first byte of a series of sequential bytes being programmed in burst mode will take the same amount of time to program as a byte programmed in standard mode. Subsequent bytes will program in the burst program time provided that the conditions above are met. In the case the next sequential address is the beginningofanewrow,theprogramtimeforthatbytewillbethestandardtimeinsteadofthebursttime. This is because the high voltage to the array must be disabled and then enabled again. If a new burst command has not been queued before the current command completes, then the charge pump will be disabled and high voltage removed from the array. Note 1: Required only once after reset. WRITE TO FCDIV (Note 1) FLASH BURST START PROGRAM FLOW 0 FACCERR ? 1 CLEAR ERROR 0 FCBEF ? 1 WRITE TO FLASH TO BUFFER ADDRESS AND DATA WRITE COMMAND (0x25) TO FCMD WRITE 1 TO FCBEF Note 2: Wait at least four bus cycles before TO LAUNCH COMMAND checking FCBEF or FCCF. AND CLEAR FCBEF (Note 2) FPVIO OR YES ERROR EXIT FACCERR ? NO YES NEW BURST COMMAND ? NO 0 FCCF ? 1 DONE Figure4-3. FLASH Burst Program Flowchart MC9S08SH8MCUSeriesDataSheet,Rev.3 50 Freescale Semiconductor

Chapter4 Memory 4.5.5 Access Errors An access error occurs whenever the command execution protocol is violated. Any of the following specific actions will cause the access error flag (FACCERR) in FSTAT to be set. FACCERRmustbeclearedbywritinga1toFACCERRinFSTATbeforeanycommandcanbeprocessed. • Writing to a FLASH address before the internal FLASH clock frequency has been set by writing to the FCDIV register • WritingtoaFLASHaddresswhileFCBEFisnotset(Anewcommandcannotbestarteduntilthe command buffer is empty.) • WritingasecondtimetoaFLASHaddressbeforelaunchingthepreviouscommand(Thereisonly one write to FLASH for every command.) • WritingasecondtimetoFCMDbeforelaunchingthepreviouscommand(Thereisonlyonewrite to FCMD for every command.) • Writing to any FLASH control register other than FCMD after writing to a FLASH address • Writing any command code other than the five allowed codes (0x05, 0x20, 0x25, 0x40, or 0x41) to FCMD • WritinganyFLASHcontrolregisterotherthanthewritetoFSTAT(toclearFCBEFandlaunchthe command) after writing the command to FCMD • The MCU enters stop mode while a program or erase command is in progress (The command is aborted.) • Writingthebyteprogram,burstprogram,orpageerasecommandcode(0x20,0x25,or0x40)with a background debug command while the MCU is secured (The background debug controller can only do blank check and mass erase commands when the MCU is secure.) • Writing 0 to FCBEF to cancel a partial command 4.5.6 FLASH Block Protection The block protection feature prevents the protected region of FLASH from program or erase changes. Block protection is controlled through the FLASH protection register (FPROT). When enabled, block protectionbeginsatany512byteboundarybelowthelastaddressofFLASH,0xFFFF.(SeeSection4.7.4, “FLASH Protection Register (FPROT and NVPROT)”). After exit from reset, FPROT is loaded with the contents of the NVPROT location, which is in the nonvolatile register block of the FLASH memory. FPROT cannot be changed directly from application softwaresoarunawayprogramcannotaltertheblockprotectionsettings.BecauseNVPROTiswithinthe last512bytesofFLASH,ifanyamountofmemoryisprotected,NVPROTisitselfprotectedandcannot be altered (intentionally or unintentionally) by the application software. FPROT can be written through background debug commands, which allows a way to erase and reprogram a protected FLASH memory. TheblockprotectionmechanismisillustratedinFigure4-4.TheFPSbitsareusedastheupperbitsofthe lastaddressofunprotectedmemory.ThisaddressisformedbyconcatenatingFPS7:FPS1withlogic1bits asshown.Forexample,toprotectthelast1536bytesofmemory(addresses0xFA00through0xFFFF),the FPS bits must be set to 1111 100, which results in the value 0xF9FF as the last address of unprotected memory.InadditiontoprogrammingtheFPSbitstotheappropriatevalue,FPDIS(bit0ofNVPROT)must MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 51

Chapter4 Memory beprogrammedtologic0toenableblockprotection.Thereforethevalue0xF8mustbeprogrammedinto NVPROT to protect addresses 0xFA00 through 0xFFFF. FPS7 FPS6 FPS5 FPS4 FPS3 FPS2 FPS1 1 1 1 1 1 1 1 1 1 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Figure4-4. Block Protection Mechanism OneuseforblockprotectionistoblockprotectanareaofFLASHmemoryforabootloaderprogram.This bootloader program then can be used to erase the rest of the FLASH memory and reprogram it. Because the bootloader is protected, it remains intact even if MCU power is lost in the middle of an erase and reprogram operation. 4.5.7 Vector Redirection Whenever any block protection is enabled, the reset and interrupt vectors will be protected. Vector redirectionallowsuserstomodifyinterruptvectorinformationwithoutunprotectingbootloaderandreset vector space. Vector redirection is enabled by programming the FNORED bit in the NVOPT register locatedataddress0xFFBFtozero.Forredirectiontooccur,atleastsomeportionbutnotalloftheFLASH memorymustbeblockprotectedbyprogrammingtheNVPROTregisterlocatedataddress0xFFBD.All of the interrupt vectors (memory locations 0xFFC0–0xFFFD) are redirected, though the reset vector (0xFFFE:FFFF) is not. Forexample,if512bytesofFLASHareprotected,theprotectedaddressregionisfrom0xFE00through 0xFFFF.Theinterruptvectors(0xFFC0–0xFFFD)areredirectedtothelocations0xFDC0–0xFDFD.Now, ifanSPIinterruptistakenforinstance,thevaluesinthelocations0xFDE0:FDE1areusedforthevector instead of the values in the locations 0xFFE0:FFE1. This allows the user to reprogram the unprotected portion of the FLASH with new program code including new interrupt vector values while leaving the protected area, which includes the default vector locations, unchanged. 4.6 Security The MC9S08SH8 includes circuitry to prevent unauthorized access to the contents of FLASH and RAM memory. When security is engaged, FLASH and RAM are considered secure resources. Direct-page registers, high-page registers, and the background debug controller are considered unsecured resources. Programs executing within secure memory have normal access to any MCU memory locations and resources. Attempts to access a secure memory location with a program executing from an unsecured memoryspaceorthroughthebackgrounddebuginterfaceareblocked(writesareignoredandreadsreturn all 0s). Security is engaged or disengaged based on the state of two nonvolatile register bits (SEC01:SEC00) in theFOPTregister.Duringreset,thecontentsofthenonvolatilelocationNVOPTarecopiedfromFLASH intotheworkingFOPTregisterinhigh-pageregisterspace.Auserengagessecuritybyprogrammingthe NVOPT location which can be done at the same time the FLASH memory is programmed. The 1:0 state disengagessecurityandtheotherthreecombinationsengagesecurity.Noticetheerasedstate(1:1)makes MC9S08SH8MCUSeriesDataSheet,Rev.3 52 Freescale Semiconductor

Chapter4 Memory theMCUsecure.Duringdevelopment,whenevertheFLASHiserased,itisgoodpracticetoimmediately program the SEC00 bit to 0 in NVOPT so SEC01:SEC00=1:0. This would allow the MCU to remain unsecured after a subsequent reset. The on-chip debug module cannot be enabled while the MCU is secure. The separate background debug controller can still be used for background memory access commands of unsecured resources. A user can choose to allow or disallow a security unlocking mechanism through an 8-byte backdoor securitykey.IfthenonvolatileKEYENbitinNVOPT/FOPTis0,thebackdoorkeyisdisabledandthere isnowaytodisengagesecuritywithoutcompletelyerasingallFLASHlocations.IfKEYENis1,asecure user program can temporarily disengage security by: 1. Writing1toKEYACCintheFCNFGregister.ThismakestheFLASHmoduleinterpretwritesto the backdoor comparison key locations (NVBACKKEY through NVBACKKEY+7) as values to be compared against the key rather than as the first step in a FLASH program or erase command. 2. Writing the user-entered key values to the NVBACKKEY through NVBACKKEY+7 locations. These writes must be done in order starting with the value for NVBACKKEY and ending with NVBACKKEY+7.STHXshouldnotbeusedforthesewritesbecausethesewritescannotbedone on adjacent bus cycles. User software normally would get the key codes from outside the MCU system through a communication interface such as a serial I/O. 3. Writing 0 to KEYACC in the FCNFG register. If the 8-byte key that was just written matches the key stored in the FLASH locations, SEC01:SEC00 are automatically changed to 1:0 and security will be disengaged until the next reset. Thesecuritykeycanbewrittenonlyfromsecurememory(eitherRAMorFLASH),soitcannotbeentered through background commands without the cooperation of a secure user program. Thebackdoorcomparisonkey(NVBACKKEYthroughNVBACKKEY+7)islocatedinFLASHmemory locations in the nonvolatile register space so users can program these locations exactly as they would programanyotherFLASHmemorylocation.Thenonvolatileregistersareinthesame512-byteblockof FLASHastheresetandinterruptvectors,soblockprotectingthatspacealsoblockprotectsthebackdoor comparisonkey.Blockprotectscannotbechangedfromuserapplicationprograms,soifthevectorspace is block protected, the backdoor security key mechanism cannot permanently change the block protect, security settings, or the backdoor key. Security can always be disengaged through the background debug interface by taking these steps: 1. Disable any block protections by writing FPROT. FPROT can be written only with background debug commands, not from application software. 2. Mass erase FLASH if necessary. 3. BlankcheckFLASH.ProvidedFLASHiscompletelyerased,securityisdisengageduntilthenext reset. To avoid returning to secure mode after the next reset, program NVOPT so SEC01:SEC00=1:0. 4.7 FLASH Registers and Control Bits The FLASH module has nine 8-bit registers in the high-page register space, two locations (NVOPT, NVPROT) in the nonvolatile register space in FLASH memory are copied into corresponding high-page MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 53

Chapter4 Memory control registers (FOPT, FPROT) at reset. There is also an 8-byte comparison key in FLASH memory. RefertoTable4-3andTable4-4fortheabsoluteaddressassignmentsforallFLASHregisters.Thissection refers to registers and control bits only by their names. A Freescale Semiconductor-provided equate or header file normally is used to translate these names into the appropriate absolute addresses. 4.7.1 FLASH Clock Divider Register (FCDIV) Bit7ofthisregisterisaread-onlyflag.Bits6:0maybereadatanytimebutcanbewrittenonlyonetime. Beforeanyeraseorprogrammingoperationsarepossible,writetothisregistertosetthefrequencyofthe clock for the nonvolatile memory system within acceptable limits. 7 6 5 4 3 2 1 0 R DIVLD PRDIV8 DIV W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure4-5. FLASH Clock Divider Register (FCDIV) Table4-6. FCDIV Register Field Descriptions Field Description 7 DivisorLoadedStatusFlag—Whenset,thisread-onlystatusflagindicatesthattheFCDIVregisterhasbeen DIVLD writtensincereset.Resetclearsthisbitandthefirstwritetothisregistercausesthisbittobecomesetregardless of the data written. 0 FCDIV has not been written since reset; erase and program operations disabled for FLASH. 1 FCDIV has been written since reset; erase and program operations enabled for FLASH. 6 Prescale (Divide) FLASH Clock by 8 PRDIV8 0 Clock input to the FLASH clock divider is the bus rate clock. 1 Clock input to the FLASH clock divider is the bus rate clock divided by8. 5:0 DivisorforFLASHClockDivider—TheFLASHclockdividerdividesthebusrateclock(orthebusrateclock DIV divided by 8 if PRDIV8=1) by the value in the 6-bit DIV field plus one. The resulting frequency of the internal FLASH clock must fall within the range of 200kHz to 150kHz for proper FLASH operations. Program/Erase timing pulses are one cycle of this internal FLASH clock which corresponds to a range of 5μs to 6.7μs. The automated programming logic uses an integer number of these pulses to complete an erase or program operation. SeeEquation4-1 andEquation4-2. if PRDIV8=0 — f = f ÷ (DIV + 1) Eqn.4-1 FCLK Bus if PRDIV8=1 — f = f ÷ (8× (DIV + 1)) Eqn.4-2 FCLK Bus Table4-7 shows the appropriate values for PRDIV8 and DIV for selected bus frequencies. MC9S08SH8MCUSeriesDataSheet,Rev.3 54 Freescale Semiconductor

Chapter4 Memory Table4-7. FLASH Clock Divider Settings PRDIV8 DIV Program/Erase Timing Pulse f f Bus (Binary) (Decimal) FCLK (5μs Min, 6.7 μs Max) 20 MHz 1 12 192.3 kHz 5.2μs 10 MHz 0 49 200 kHz 5μs 8 MHz 0 39 200 kHz 5μs 4 MHz 0 19 200 kHz 5μs 2 MHz 0 9 200 kHz 5μs 1 MHz 0 4 200 kHz 5μs 200 kHz 0 0 200 kHz 5μs 150 kHz 0 0 150 kHz 6.7μs 4.7.2 FLASH Options Register (FOPT and NVOPT) During reset, the contents of the nonvolatile location NVOPT are copied from FLASH into FOPT. To change the value in this register, erase and reprogram the NVOPT location in FLASH memory as usual and then issue a new MCU reset. 7 6 5 4 3 2 1 0 R KEYEN FNORED 0 0 0 0 SEC01 SEC00 W Reset This register is loaded from nonvolatile location NVOPT during reset. = Unimplemented or Reserved Figure4-6. FLASH Options Register (FOPT) Table4-8. FOPT Register Field Descriptions Field Description 7 Backdoor Key Mechanism Enable — When this bit is 0, the backdoor key mechanism cannot be used to KEYEN disengage security. The backdoor key mechanism is accessible only from user (secured) firmware. BDM commandscannotbeusedtowritekeycomparisonvaluesthatwouldunlockthebackdoorkey.Formoredetailed information about the backdoor key mechanism, refer toSection 4.6, “Security.” 0 No backdoor key access allowed. 1 If user firmware writes an 8-byte value that matches the nonvolatile backdoor key (NVBACKKEY through NVBACKKEY+7 in that order), security is temporarily disengaged until the next MCU reset. 6 Vector Redirection Disable — When this bit is 1, then vector redirection is disabled. FNORED 0 Vector redirection enabled. 1 Vector redirection disabled. 1:0 SecurityStateCode—This2-bitfielddeterminesthesecuritystateoftheMCUasshowninTable4-9.When SEC0[1:0] the MCU is secure, the contents of RAM and FLASH memory cannot be accessed by instructions from any unsecured source including the background debug interface. SEC01:SEC00 changes to 1:0 after successful backdoor key entry or a successful blank check of FLASH. For more detailed information about security, refer toSection 4.6, “Security.” MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 55

Chapter4 Memory Table4-9. Security States1 SEC01:SEC00 Description 0:0 secure 0:1 secure 1:0 unsecured 1:1 secure 1 SEC01:SEC00changesto1:0aftersuccessfulbackdoor key entry or a successful blank check of FLASH. 4.7.3 FLASH Configuration Register (FCNFG 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 KEYACC W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure4-7. FLASH Configuration Register (FCNFG Table4-10. FCNFG Register Field Descriptions Field Description 5 Enable Writing of Access Key — This bit enables writing of the backdoor comparison key. For more detailed KEYACC information about the backdoor key mechanism, refer toSection 4.6, “Security.” 0 Writes to 0xFFB0–0xFFB7 are interpreted as the start of a FLASH programming or erase command. 1 Writes to NVBACKKEY (0xFFB0–0xFFB7) are interpreted as comparison key writes. 4.7.4 FLASH Protection Register (FPROT and NVPROT) Duringreset,thecontentsofthenonvolatilelocationNVPROTarecopiedfromFLASHintoFPROT.This registercanbereadatanytime.IfFPDIS=0,protectioncanbeincreased(thatis,asmallervalueofFPS can be written). If FPDIS = 1, writes do not change protection. 7 6 5 4 3 2 1 0 R FPS(1) FPDIS(1) W Reset This register is loaded from nonvolatile location NVPROT during reset. 1 Background commands can be used to change the contents of these bits in FPROT. Figure4-8. FLASH Protection Register (FPROT) MC9S08SH8MCUSeriesDataSheet,Rev.3 56 Freescale Semiconductor

Chapter4 Memory Table4-11. FPROT Register Field Descriptions Field Description 7:1 FLASHProtectSelectBits—WhenFPDIS=0,this7-bitfielddeterminestheendingaddressofunprotected FPS FLASH locations at the high address end of the FLASH. Protected FLASH locations cannot be erased or programmed. 0 FLASH Protection Disable FPDIS 0 FLASH block specified by FPS[7:1] is block protected (program and erase not allowed). 1 No FLASH block is protected. 4.7.5 FLASH Status Register (FSTAT) 7 6 5 4 3 2 1 0 R FCCF 0 FBLANK 0 0 FCBEF FPVIOL FACCERR W Reset 1 1 0 0 0 0 0 0 = Unimplemented or Reserved Figure4-9. FLASH Status Register (FSTAT) Table4-12. FSTAT Register Field Descriptions Field Description 7 FLASHCommandBufferEmptyFlag—TheFCBEFbitisusedtolaunchcommands.Italsoindicatesthatthe FCBEF command buffer is empty so that a new command sequence can be executed when performing burst programming. The FCBEF bit is cleared by writing a 1 to it or when a burst program command is transferred to the array for programming. Only burst program commands can be buffered. 0 Command buffer is full (not ready for additional commands). 1 A new burst program command can be written to the command buffer. 6 FLASH Command Complete Flag — FCCF is set automatically when the command buffer is empty and no FCCF command is being processed. FCCF is cleared automatically when a new command is started (by writing 1 to FCBEF to register a command). Writing to FCCF has no meaning or effect. 0 Command in progress 1 All commands complete 5 ProtectionViolationFlag—FPVIOLissetautomaticallywhenacommandiswrittenthatattemptstoeraseor FPVIOL program a location in a protected block (the erroneous command is ignored). FPVIOL is cleared by writing a 1 to FPVIOL. 0 No protection violation. 1 An attempt was made to erase or program a protected location. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 57

Chapter4 Memory Table4-12. FSTAT Register Field Descriptions (continued) Field Description 4 AccessErrorFlag—FACCERRissetautomaticallywhenthepropercommandsequenceisnotobeyedexactly FACCERR (theerroneouscommandisignored),ifaprogramoreraseoperationisattemptedbeforetheFCDIVregisterhas beeninitialized,oriftheMCUentersstopwhileacommandwasinprogress.Foramoredetaileddiscussionof theexactactionsthatareconsideredaccesserrors,seeSection4.5.5,“AccessErrors.”FACCERRisclearedby writing a 1 to FACCERR. Writing a 0 to FACCERR has no meaning or effect. 0 No access error. 1 An access error has occurred. 2 FLASHVerifie asAllBlank(erased)Flag—FBLANKissetautomaticallyattheconclusionofablankcheck FBLANK commandiftheentireFLASHarraywasverifiedtobeerased.FBLANKisclearedbyclearingFCBEFtowritea new valid command. Writing to FBLANK has no meaning or effect. 0 After a blank check command is completed and FCCF=1, FBLANK=0 indicates the FLASH array is not completely erased. 1 After a blank check command is completed and FCCF=1, FBLANK=1 indicates the FLASH array is completely erased (all 0xFF). 4.7.6 FLASH Command Register (FCMD) OnlyfivecommandcodesarerecognizedinnormalusermodesasshowninTable4-13.RefertoSection 4.5.3, “Program and Erase Command Execution,” for a detailed discussion of FLASH programming and erase operations. 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W FCMD Reset 0 0 0 0 0 0 0 0 Figure4-10. FLASH Command Register (FCMD) Table4-13. FLASH Commands Command FCMD Equate File Label Blank check 0x05 mBlank Byte program 0x20 mByteProg Byte program — burst mode 0x25 mBurstProg Page erase (512 bytes/page) 0x40 mPageErase Mass erase (all FLASH) 0x41 mMassErase All other command codes are illegal and generate an access error. It is not necessary to perform a blank check command after a mass erase operation. Only blank check is required as part of the security unlocking mechanism. MC9S08SH8MCUSeriesDataSheet,Rev.3 58 Freescale Semiconductor

Chapter 5 Resets, Interrupts, and General System Control 5.1 Introduction Thissectiondiscussesbasicresetandinterruptmechanismsandthevarioussourcesofresetandinterrupt intheMC9S08SH8.Someinterruptsourcesfromperipheralmodulesarediscussedingreaterdetailwithin othersectionsofthisdatasheet.Thissectiongathersbasicinformationaboutallresetandinterruptsources in one place for easy reference. A few reset and interrupt sources, including the computer operating properly (COP) watchdog are not part of on-chip peripheral systems with their own chapters. 5.2 Features Reset and interrupt features include: • Multiple sources of reset for flexible system configuration and reliable operation • Reset status register (SRS) to indicate source of most recent reset • Separate interrupt vector for each module (reduces polling overhead) (see Table5-2) 5.3 MCU Reset ResettingtheMCUprovidesawaytostartprocessingfromaknownsetofinitialconditions.Duringreset, most control and status registers are forced to initial values and the program counter is loaded from the reset vector (0xFFFE:0xFFFF). On-chip peripheral modules are disabled and I/O pins are initially configured as general-purpose high-impedance inputs with pull-up devices disabled. The I bit in the condition code register (CCR) is set to block maskable interrupts so the user program has a chance to initialize the stack pointer (SP) and system control settings. SP is forced to 0x00FF at reset. The MC9S08SH8 has the following sources for reset: • Power-on reset (POR) • External pin reset (PIN) - enabled using RSTPE in SOPT1 • Low-voltage detect (LVD) • Computer operating properly (COP) timer • Illegal opcode detect (ILOP) • Illegal address detect (ILAD) • Background debug forced reset Each of these sources, with the exception of the background debug forced reset, has an associated bit in the system reset status register (SRS). MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 59

Chapter5 Resets, Interrupts, and General System Control 5.4 Computer Operating Properly (COP) Watchdog The COP watchdog is intended to force a system reset when the application software fails to execute as expected. To prevent a system reset from the COP timer (when it is enabled), application software must resettheCOPcounterperiodically.IftheapplicationprogramgetslostandfailstoresettheCOPcounter before it times out, a system reset is generated to force the system back to a known starting point. After any reset, the COP watchdog is enabled (see Section 5.7.4, “System Options Register 1 (SOPT1),” for additional information). If the COP watchdog is not used in an application, it can be disabled by clearing COPT bits in SOPT1. TheCOPcounterisresetbywriting0x0055and0x00AA(inthisorder)totheaddressofSRSduringthe selectedtimeoutperiod.Writesdonotaffectthedataintheread-onlySRS.Assoonasthewritesequence isdone,theCOPtimeoutperiodisrestarted.Iftheprogramfailstodothisduringthetime-outperiod,the MCU will reset. Also, if any value other than 0x0055 or 0x00AA is written to SRS, the MCU is immediately reset. The COPCLKS bit in SOPT2 (seeSection 5.7.5, “System Options Register 2 (SOPT2),” for additional information)selectstheclocksourceusedfortheCOPtimer.Theclocksourceoptionsareeitherthebus clock or an internal 1-kHz clock source. With each clock source, there are three associated time-outs controlledbytheCOPTbitsinSOPT1.Table5-1summariesthecontrolfunctionsoftheCOPCLKSand COPTbits.TheCOPwatchdogdefaultstooperationfromthe1-kHzclocksourceandthelongesttime-out (210 cycles). Table5-1. COP Configuration Option Control Bits COP Window1 Opens Clock Source COP Overfl w Count (COPW = 1) COPCLKS COPT[1:0] N/A 0:0 N/A N/A COP is disabled 0 0:1 1 kHz N/A 25cycles (32 ms2) 0 1:0 1 kHz N/A 28 cycles (256 ms1) 0 1:1 1 kHz N/A 210 cycles (1.024 s1) 1 0:1 Bus 6144 cycles 213cycles 1 1:0 Bus 49,152 cycles 216cycles 1 1:1 Bus 196,608 cycles 218cycles 1 WindowedCOPoperationrequirestheusertocleartheCOPtimerinthelast25%oftheselectedtimeoutperiod.Thiscolumn displays the minimun number of clock counts required before the COP timer can be reset hen in windowed COP mode (COPW=1). 2 Values shown in in miliseconds based on t =1ms. See t in the appendixSection A.12.1, “Control Timing” for the LPO LPO tolerance of this value. When the bus clock source is selected, windowed COP operation is available by setting COPW in the SOPT2register.Inthismode,writestotheSRSregistertocleartheCOPtimermustoccurinthelast25% of the selected timeout period. A premature write immediately resets the MCU. When the 1-kHz clock source is selected, windowed COP operation is not available. MC9S08SH8MCUSeriesDataSheet,Rev.3 60 Freescale Semiconductor

Chapter5 Resets, Interrupts, and General System Control TheCOPcounterisinitializedbythefirstwritestotheSOPT1andSOPT2registersafteranysystemreset. SubsequentwritestoSOPT1andSOPT2havenoeffectonCOPoperation.Eveniftheapplicationwilluse the reset default settings of COPT, COPCLKS, and COPW bits, the user should write to the write-once SOPT1andSOPT2registersduringresetinitializationtolockinthesettings.Thiswillpreventaccidental changes if the application program gets lost. ThewritetoSRSthatservices(clears)theCOPcountershouldnotbeplacedinaninterruptserviceroutine (ISR) because the ISR could continue to be executed periodically even if the main application program fails. Ifthebusclocksourceisselected,theCOPcounterdoesnotincrementwhiletheMCUisinbackground debug mode or while the system is in stop mode. The COP counter resumes when the MCU exits background debug mode or stop mode. If the 1-kHz clock source is selected, the COP counter is re-initialized to zero upon entry to either background debug mode or stop mode and begins from zero upon exit from background debug mode or stop mode. 5.5 Interrupts InterruptsprovideawaytosavethecurrentCPUstatusandregisters,executeaninterruptserviceroutine (ISR), and then restore the CPU status so processing resumes where it left off before the interrupt. Other thanthesoftwareinterrupt(SWI),whichisaprograminstruction,interruptsarecausedbyhardwareevents such as an edge on the IRQ pin or a timer-overflow event. The debug module can also generate an SWI under certain circumstances. Ifaneventoccursinanenabledinterruptsource,anassociatedread-onlystatusflagwillbecomeset.The CPUwillnotrespondunlessthelocalinterruptenableisa1toenabletheinterruptandtheIbitintheCCR is 0 to allow interrupts. The global interrupt mask (I bit) in the CCR is initially set after reset which preventsallmaskableinterruptsources.Theuserprograminitializesthestackpointerandperformsother system setup before clearing the I bit to allow the CPU to respond to interrupts. WhentheCPUreceivesaqualifiedinterruptrequest,itcompletesthecurrentinstructionbeforeresponding totheinterrupt.Theinterruptsequenceobeysthesamecycle-by-cyclesequenceastheSWIinstructionand consists of: • Saving the CPU registers on the stack • Setting the I bit in the CCR to mask further interrupts • Fetching the interrupt vector for the highest-priority interrupt that is currently pending • Filling the instruction queue with the first three bytes of program information starting from the address fetched from the interrupt vector locations WhiletheCPUisrespondingtotheinterrupt,theIbitisautomaticallysettoavoidthepossibilityofanother interruptinterruptingtheISRitself(thisiscallednestingofinterrupts).Normally,theIbitisrestoredto0 whentheCCRisrestoredfromthevaluestackedonentrytotheISR.Inrarecases,theIbitcanbecleared inside an ISR (after clearing the status flag that generated the interrupt) so that other interrupts can be servicedwithoutwaitingforthefirstserviceroutinetofinish.Thispracticeisnotrecommendedforanyone MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 61

Chapter5 Resets, Interrupts, and General System Control otherthanthemostexperiencedprogrammersbecauseitcanleadtosubtleprogramerrorsthataredifficult to debug. Theinterruptserviceroutineendswithareturn-from-interrupt(RTI)instructionwhichrestorestheCCR, A, X, and PC registers to their pre-interrupt values by reading the previously saved information from the stack. NOTE For compatibility with M68HC08 devices, the H register is not automatically saved and restored. It is good programming practice to push Hontothestackatthestartoftheinterruptserviceroutine(ISR)andrestore it immediately before the RTI that is used to return from the ISR. IfmorethanoneinterruptispendingwhentheIbitiscleared,thehighestprioritysourceisservicedfirst (seeTable5-2). 5.5.1 Interrupt Stack Frame Figure5-1 shows the contents and organization of a stack frame. Before the interrupt, the stack pointer (SP)pointsatthenextavailablebytelocationonthestack.ThecurrentvaluesofCPUregistersarestored onthestackstartingwiththelow-orderbyteoftheprogramcounter(PCL)andendingwiththeCCR.After stacking,theSPpointsatthenextavailablelocationonthestackwhichistheaddressthatisonelessthan theaddresswheretheCCRwassaved.ThePCvaluethatisstackedistheaddressoftheinstructioninthe main program that would have executed next if the interrupt had not occurred. UNSTACKING TOWARD LOWER ADDRESSES ORDER 7 0 SP AFTER INTERRUPT STACKING 5 1 CONDITION CODE REGISTER 4 2 ACCUMULATOR 3 3 INDEX REGISTER (LOW BYTE X)* 2 4 PROGRAM COUNTER HIGH SP BEFORE 1 5 PROGRAM COUNTER LOW THE INTERRUPT STACKING TOWARD HIGHER ADDRESSES ORDER * High byte (H) of index register is not automatically stacked. Figure5-1. Interrupt Stack Frame WhenanRTIinstructionisexecuted,thesevaluesarerecoveredfromthestackinreverseorder.Aspartof the RTI sequence, the CPU fills the instruction pipeline by reading three bytes of program information, starting from the PC address recovered from the stack. MC9S08SH8MCUSeriesDataSheet,Rev.3 62 Freescale Semiconductor

Chapter5 Resets, Interrupts, and General System Control The status flag corresponding to the interrupt source must be acknowledged (cleared) before returning from the ISR. Typically, the flag is cleared at the beginning of the ISR so that if another interrupt is generatedbythissamesource,itwillberegisteredsoitcanbeservicedaftercompletionofthecurrentISR. 5.5.2 External Interrupt Request Pin (IRQ) ExternalinterruptsaremanagedbytheIRQstatusandcontrolregister,IRQSC.WhentheIRQfunctionis enabled,synchronouslogicmonitorsthepinforedge-onlyoredge-and-levelevents.WhentheMCUisin stopmodeandsystemclocksareshutdown,aseparateasynchronouspathisusedsotheIRQ(ifenabled) can wake the MCU. 5.5.2.1 Pin Configuration Option TheIRQpinenable(IRQPE)controlbitinIRQSCmustbe1inorderfortheIRQpintoactastheinterrupt request (IRQ) input. As an IRQ input, the user can choose the polarity of edges or levels detected (IRQEDG), whether the pin detects edges-only or edges and levels (IRQMOD), and whether an event causes an interrupt or only sets the IRQF flag which can be polled by software. TheIRQpin,whenenabled,defaultstouseaninternalpulldevice(IRQPDD=0),thedeviceisapull-up orpull-downdependingonthepolaritychosen.Iftheuserdesirestouseanexternalpull-uporpull-down, the IRQPDD can be written to a 1 to turn off the internal device. BIHandBILinstructionsmaybeusedtodetectthelevelontheIRQpinwhenthepinisconfiguredtoact as the IRQ input. NOTE This pin does not contain a clamp diode to V and should not be driven DD above V . DD ThevoltagemeasuredontheinternallypulledupIRQpinwillnotbepulled to V . The internal gates connected to this pin are pulled to V . If the DD DD IRQpinisrequiredtodrivetoaV levelanexternalpullupshouldbeused. DD 5.5.2.2 Edge and Level Sensitivity The IRQMOD control bit reconfigures the detection logic so it detects edge events and pin levels. In the edgeandleveldetectionmode,theIRQFstatusflagbecomessetwhenanedgeisdetected(whentheIRQ pin changes from the deasserted to the asserted level), but the flag is continuously set (and cannot be cleared) as long as the IRQ pin remains at the asserted level. 5.5.3 Interrupt Vectors, Sources, and Local Masks Table5-2 provides a summary of all interrupt sources. Higher-priority sources are located toward the bottom of the table. The high-order byte of the address for the interrupt service routine is located at the first address in the vector address column, and the low-order byte of the address for the interrupt service routine is located at the next higher address. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 63

Chapter5 Resets, Interrupts, and General System Control When an interrupt condition occurs, an associated flag bit becomes set. If the associated local interrupt enable is 1, an interrupt request is sent to the CPU. Within the CPU, if the global interrupt mask (I bit in the CCR) is 0, the CPU will finish the current instruction; stack the PCL, PCH, X, A, and CCR CPU registers; set the I bit; and then fetch the interrupt vector for the highest priority pending interrupt. Processing then continues in the interrupt service routine. Table5-2. Vector Summary Vector Vector Address Vector Module Source Enable Description Priority Number (High/Low) Name 31 0xFFC0/0xFFC1 — — — — — Lowest 30 0xFFC2/0xFFC3 Vacmp ACMP ACF ACIE Analog comparator 29 0xFFC4/0xFFC5 — — — — — 28 0xFFC6/0xFFC7 — — — — — 27 0xFFC8/0xFFC9 — — — — — 26 0xFFCA/0xFFCB Vmtim MTIM TOF TOIE MTIM overflow 25 0xFFCC/0xFFCD Vrtc RTC RTIF RTIE Real-time interrupt 24 0xFFCE/0xFFCF Viic IIC IICIF IICIE IIC control 23 0xFFD0/0xFFD1 Vadc ADC COCO AIEN ADC 22 0xFFD2/0xFFD3 — — — — — 21 0xFFD4/0xFFD5 Vportb Port B PTBIF PTBIE Port B Pins 20 0xFFD6/0xFFD7 Vporta Port A PTAIF PTAIE Port A Pins 19 0xFFD8/0xFFD9 — — — — — 18 0xFFDA/0xFFDB Vscitx SCI TDRE, TC TIE, TCIE SCI transmit 17 0xFFDC/0xFFDD Vscirx SCI IDLE, RDRF, ILIE, RIE, LDBKDIF, SCI receive LBKDIE, RXEDGIE RXEDGIF 16 0xFFDE/0xFFDF Vscierr SCI OR, NF, ORIE, NFIE, SCI error FE, PF FEIE, PFIE 15 0xFFE0/0xFFE1 Vspi SPI SPIF, MODF, SPIE, SPIE, SPTIE SPI SPTEF 14 0xFFE2/0xFFE3 Vtpm2ovf TPM2 TOF TOIE TPM2 overflow 13 0xFFE4/0xFFE5 Vtpm2ch1 TPM2 CH1F CH1IE TPM2 channel 1 12 0xFFE6/0xFFE7 Vtpm2ch0 TPM2 CH0F CH0IE TPM2 channel 0 11 0xFFE8/0xFFE9 Vtpm1ovf TPM1 TOF TOIE TPM1 overflow 10 0xFFEA/0xFFEB — — — — — 9 0xFFEC/0xFFED — — — — — 8 0xFFEE/0xFFEF — — — — — 7 0xFFF0/0xFFF1 — — — — — 6 0xFFF2/0xFFF3 Vtpm1ch1 TPM1 CH1F CH1IE TPM1 channel 1 5 0xFFF4/0xFFF5 Vtpm1ch0 TPM1 CH0F CH0IE TPM1 channel 0 4 0xFFF6/0xFFF7 — — — — — 3 0xFFF8/0xFFF9 Vlvd System LVWF LVWIE Low-voltage warning control 2 0xFFFA/0xFFFB Virq IRQ IRQF IRQIE IRQ pin 1 0xFFFC/0xFFFD Vswi Core SWI Instruction — Software interrupt 0 0xFFFE/0xFFFF Vreset System COP, COPT Watchdog timer control LVD, LVDRE Low-voltage detect RESET pin, — External pin Highest Illegal opcode, — Illegal opcode Illegal address — Illegal address MC9S08SH8MCUSeriesDataSheet,Rev.3 64 Freescale Semiconductor

Chapter5 Resets, Interrupts, and General System Control 5.6 Low-Voltage Detect (LVD) System TheMC9S08SH8includesasystemtoprotectagainstlowvoltageconditionsinordertoprotectmemory contents and control MCU system states during supply voltage variations. The system is comprised of a power-on reset (POR) circuit and a LVD circuit with trip voltages for warning and detection. The LVD circuitisenabledwhenLVDEinSPMSC1issetto1.TheLVDisdisableduponenteringanyofthestop modes unless LVDSE is set in SPMSC1. If LVDSE and LVDE are both set, then the MCU cannot enter stop2, and the current consumption in stop3 with the LVD enabled will be higher. 5.6.1 Power-On Reset Operation When power is initially applied to the MCU, or when the supply voltage drops below the power-on reset rearm voltage level, V , the POR circuit will cause a reset condition. As the supply voltage rises, the POR LVD circuit will hold the MCU in reset until the supply has risen above the low voltage detection low threshold, V . Both the POR bit and the LVD bit in SRS are set following a POR. LVDL 5.6.2 Low-Voltage Detection (LVD) Reset Operation The LVD can be configured to generate a reset upon detection of a low voltage condition by setting LVDREto1.ThelowvoltagedetectionthresholdisdeterminedbytheLVDVbit.AfteranLVDresethas occurred, the LVD system will hold the MCU in reset until the supply voltage has risen above the low voltagedetectionthreshold.TheLVDbitintheSRSregisterissetfollowingeitheranLVDresetorPOR. 5.6.3 Low-Voltage Warning (LVW) Interrupt Operation The LVD system has a low voltage warning flag to indicate to the user that the supply voltage is approaching the low voltage condition. When a low voltage warning condition is detected and is configuredforinterruptoperation(LVWIEsetto1),LVWFinSPMSC1willbesetandanLVWinterrupt request will occur. 5.7 Reset, Interrupt, and System Control Registers and Control Bits One8-bitregisterinthedirectpageregisterspaceandeight8-bitregistersinthehigh-pageregisterspace are related to reset and interrupt systems. Refer toTable4-2 andTable4-3 inChapter4, “Memory,” of this data sheet for the absolute address assignments for all registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. SomecontrolbitsintheSOPT1andSPMSC2registersarerelatedtomodesofoperation.Althoughbrief descriptions of these bits are provided here, the related functions are discussed in greater detail in Chapter3, “Modes of Operation.” MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 65

Chapter5 Resets, Interrupts, and General System Control 5.7.1 Interrupt Pin Request Status and Control Register (IRQSC) This direct page register includes status and control bits, which are used to configure the IRQ function, report status, and acknowledge IRQ events. 7 6 5 4 3 2 1 0 R 0 IRQF 0 IRQPDD IRQEDG IRQPE IRQIE IRQMOD W IRQACK Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure5-2. Interrupt Request Status and Control Register (IRQSC) Table5-3. IRQSC Register Field Descriptions Field Description 6 InterruptRequest(IRQ)PullDeviceDisable—Thisread/writecontrolbitisusedtodisabletheinternalpullup IRQPDD device when the IRQ pin is enabled (IRQPE = 1) allowing for an external device to be used. 0 IRQ pull device enabled if IRQPE = 1. 1 IRQ pull device disabled if IRQPE = 1. 5 Interrupt Request (IRQ) Edge Select — This read/write control bit is used to select the polarity of edges or IRQEDG levels on the IRQ pin that cause IRQF to be set. The IRQMOD control bit determines whether the IRQ pin is sensitivetobothedgesandlevelsoronlyedges.WhentheIRQpinisenabledastheIRQinputandisconfigured to detect rising edges. When IRQEDG = 1 and the internal pull device is enabled, the pull-up device is reconfigured as an optional pull-down device. 0 IRQ is falling edge or falling edge/low-level sensitive. 1 IRQ is rising edge or rising edge/high-level sensitive. 4 IRQPinEnable—Thisread/writecontrolbitenablestheIRQpinfunction.WhenthisbitissettheIRQpincan IRQPE be used as an interrupt request. 0 IRQ pin function is disabled. 1 IRQ pin function is enabled. 3 IRQ Flag — This read-only status bit indicates when an interrupt request event has occurred. IRQF 0 No IRQ request. 1 IRQ event detected. 2 IRQAcknowledge—Thiswrite-onlybitisusedtoacknowledgeinterruptrequestevents(write1toclearIRQF). IRQACK Writing0hasnomeaningoreffect.Readsalwaysreturn0.Ifedge-and-leveldetectionisselected(IRQMOD=1), IRQF cannot be cleared while the IRQ pin remains at its asserted level. 1 IRQ Interrupt Enable — This read/write control bit determines whether IRQ events generate an interrupt IRQIE request. 0 Interrupt request when IRQF set is disabled (use polling). 1 Interrupt requested whenever IRQF=1. 0 IRQ Detection Mode — This read/write control bit selects either edge-only detection or edge-and-level IRQMOD detection. The IRQEDG control bit determines the polarity of edges and levels that are detected as interrupt request events. SeeSection 5.5.2.2, “Edge and Level Sensitivity,” for more details. 0 IRQ event on falling edges or rising edges only. 1 IRQ event on falling edges and low levels or on rising edges and high levels. MC9S08SH8MCUSeriesDataSheet,Rev.3 66 Freescale Semiconductor

Chapter5 Resets, Interrupts, and General System Control 5.7.2 System Reset Status Register (SRS) Thishighpageregisterincludesread-onlystatusflagstoindicatethesourceofthemostrecentreset.When adebughostforcesresetbywriting1toBDFRintheSBDFRregister,noneofthestatusbitsinSRSwill beset.WritinganyvaluetothisregisteraddresscausesaCOPresetwhentheCOPisenabledexceptthe values 0x55 and 0xAA. Writing a 0x55-0xAA sequence to this address clears the COP watchdog timer without affecting the contents of this register. The reset state of these bits depends on what caused the MCU to reset. 7 6 5 4 3 2 1 0 R POR PIN COP ILOP ILAD 0 LVD 0 W Writing 0x55, 0xAA to SRS address clears COP watchdog timer. POR: 1 0 0 0 0 0 1 0 LVR: u(1) 0 0 0 0 0 1 0 Any other 0 Note(2) Note(2) Note(2) Note(2) 0 0 0 reset: 1 u = unaffected 2 Any of these reset sources that are active at the time of reset entry will cause the corresponding bit(s) to be set; bits corresponding to sources that are not active at the time of reset entry will be cleared. Figure5-3. System Reset Status (SRS) Table5-4. SRS Register Field Descriptions Field Description 7 Power-OnReset—Resetwascausedbythepower-ondetectionlogic.Becausetheinternalsupplyvoltagewas POR rampingupatthetime,thelow-voltagereset(LVD)statusbitisalsosettoindicatethattheresetoccurredwhile the internal supply was below the LVD threshold. 0 Reset not caused by POR. 1 POR caused reset. 6 External Reset Pin — Reset was caused by an active-low level on the external reset pin. PIN 0 Reset not caused by external reset pin. 1 Reset came from external reset pin. 5 ComputerOperatingProperly(COP)Watchdog—ResetwascausedbytheCOPwatchdogtimertimingout. COP This reset source can be blocked byCOPT bits = 0:0.. 0 Reset not caused by COP timeout. 1 Reset caused by COP timeout. 4 IllegalOpcode—Resetwascausedbyanattempttoexecuteanunimplementedorillegalopcode.TheSTOP ILOP instructionisconsideredillegalifstopisdisabledbySTOPE=0intheSOPTregister.TheBGNDinstructionis considered illegal if active background mode is disabled by ENBDM=0 in the BDCSC register. 0 Reset not caused by an illegal opcode. 1 Reset caused by an illegal opcode. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 67

Chapter5 Resets, Interrupts, and General System Control Table5-4. SRS Register Field Descriptions Field Description 3 IllegalAddress—Resetwascausedbyanattempttoaccesseitherdataoraninstructionatanunimplemented ILAD memory address. 0 Reset not caused by an illegal address 1 Reset caused by an illegal address 1 LowVoltageDetect—IftheLVDREbitissetandthesupplydropsbelowtheLVDtripvoltage,anLVDresetwill LVD occur. This bit is also set by POR. 0 Reset not caused by LVD trip or POR. 1 Reset caused by LVD trip or POR. 5.7.3 System Background Debug Force Reset Register (SBDFR) This high page register contains a single write-only control bit. A serial background command such as WRITE_BYTEmustbeusedtowritetoSBDFR.Attemptstowritethisregisterfromauserprogramare ignored. Reads always return 0x00. 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W BDFR1 Reset: 0 0 0 0 0 0 0 0 = Unimplemented or Reserved 1 BDFR is writable only through serial background debug commands, not from user programs. Figure5-4. System Background Debug Force Reset Register (SBDFR) Table5-5. SBDFR Register Field Descriptions Field Description 0 BackgroundDebugForceReset—AserialbackgroundcommandsuchasWRITE_BYTEcanbeusedtoallow BDFR an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot be written from a user program. MC9S08SH8MCUSeriesDataSheet,Rev.3 68 Freescale Semiconductor

Chapter5 Resets, Interrupts, and General System Control 5.7.4 System Options Register 1 (SOPT1) Thishighpageregisterisawrite-onceregistersoonlythefirstwriteafterresetishonored.Itcanberead at any time. Any subsequent attempt to write to SOPT1 (intentionally or unintentionally) is ignored to avoid accidental changes to these sensitive settings. SOPT1 should be written during the user’s reset initialization program to set the desired controls even if the desired settings are the same as the reset settings. 1 7 6 5 4 3 2 1 0 R 0 COPT STOPE IICPS BKGDPE RSTPE W Reset: 1 1 0 0 0 0 1 u2 POR: 1 1 0 0 0 0 1 0 LVR: 1 1 0 0 0 0 1 u = Unimplemented or Reserved Figure5-5. System Options Register 1 (SOPT1) 1 Bit 4 is reserved, writes change the value, but will have no effect on this MCU. 2 u = unaffected Table5-6. SOPT1 Register Field Descriptions Field Description 7:6 COP Watchdog Timeout — These write-once bits select the timeout period of the COP. COPT along with COPT[1:0] COPCLKS in SOPT2 defines the COP timeout period. SeeTable5-1. 5 Stop Mode Enable — This write-once bit is used to enable stop mode. If stop mode is disabled and a user STOPE program attempts to execute a STOP instruction, an illegal opcode reset is forced. 0 Stop mode disabled. 1 Stop mode enabled. 2 IIC Pin Select— This bit selects the location of the SDA and SCL pins of the IIC module. IICPS 0 SDA on PTA2, SCL on PTA3. 1 SDA on PTB6, SCL on PTB7. 1 Background Debug Mode Pin Enable — This write-once bit when set enables the PTA4/ACMPO/BKGD/MS BKGDPE pin to function as BKGD/MS. When clear, the pin functions as one of its output-only alternative functions. This pin defaults to the BKGD/MS function following any MCU reset. 0 PTA4/ACMPO/BKGD/MS pin functions as PTA4 or ACMPO. 1 PTA4/ACMPO/BKGD/MS pin functions as BKGD/MS. 0 RESET Pin Enable — This write-once bit when set enables the PTA5/IRQ/TCLK/RESET pin to function as RSTPE RESET.Whenclear,thepinfunctionsasoneofitsalternativefunctions.Thispindefaultstoageneral-purpose inputportfunctionfollowingaPORreset.WhenconfiguredasRESET,thepinwillbeunaffectedbyLVRorother internal resets. When RSTPE is set, an internal pullup device is enabled onRESET. 0 PTA5/IRQ/TCLK/RESET pin functions as PTA5, IRQ or TCLK. 1 PTA5/IRQ/TCLK/RESET pin functions asRESET. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 69

Chapter5 Resets, Interrupts, and General System Control 5.7.5 System Options Register 2 (SOPT2) This high page register contains bits to configure MCU specific features on the MC9S08SH8 devices. 7 6 5 4 3 2 1 0 R 0 0 0 COPCLKS1 COPW1 ACIC T1CH1PS T1CH0PS W Reset: 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure5-6. System Options Register 2 (SOPT2) 1 This bit can be written only one time after reset. Additional writes are ignored. Table5-7. SOPT2 Register Field Descriptions Field Description 7 COP Watchdog Clock Select— This write-once bit selects the clock source of the COP watchdog. COPCLKS 0 Internal 1-kHz clock is source to COP. 1 Bus clock is source to COP. 6 COPWindow—Thiswrite-oncebitselectstheCOPoperationmode.Whenset,the0x55-0xAAwritesequence COPW to the SRS register must occur in the last 25% of the selected period. Any write to the SRS register during the first 75% of the selected period will reset the MCU. 0 Normal COP operation 1 Window COP operation (only if COPCLKS = 1) 4 AnalogComparatortoInputCaptureEnable—ThisbitconnectstheoutputofACMPtoTPM1inputchannel0. ACIC 0 ACMP output not connected to TPM1 input channel 0. 1 ACMP output connected to TPM1 input channel 0. 1 TPM1CH1 Pin Select— Thisselects the location of the TPM1CH1 pin of the TPM1 module. T1CH1PS 0 TPM1CH1 on PTB5. 1 TPM1CH1 on PTC1. 0 TPM1CH0 Pin Select— This bit selects the location of the TPM1CH0 pin of the TPM1 module. T1CH0PS 0 TPM1CH0 on PTA0. 1 TPM1CH0 on PTC0. MC9S08SH8MCUSeriesDataSheet,Rev.3 70 Freescale Semiconductor

Chapter5 Resets, Interrupts, and General System Control 5.7.6 System Device Identification Register (SDIDH, SDIDL These high page read-only registers are included so host development systems can identify the HCS08 derivativeandrevisionnumber.Thisallowsthedevelopmentsoftwaretorecognizewherespecificmemory blocks, registers, and control bits are located in a target MCU. 7 6 5 4 3 2 1 0 R 0 ID11 ID10 ID9 ID8 W Reset: 01 — — — 0 0 0 0 = Unimplemented or Reserved 1 - Bit 7 is a mask option tie off that is used internally to determine that the device is a MC9S08SH8. Figure5-7. System Device Identification Register — High (SDIDH Table5-8. SDIDH Register Field Descriptions Field Description 7 Bit 7 will read as a 0 for the MC9S08SH8 devices; writes have no effect. 6:4 Bits 6:4 are reserved. Reading these bits will result in an indeterminate value; writes have no effect. Reserved 3:0 Part Identification Numbe — Each derivative in the HCS08 Family has a unique identification number. The ID[11:8] MC9S08SH8 is hard coded to the value 0x014. See also ID bits inTable5-9. 7 6 5 4 3 2 1 0 R ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 W Reset: 0 0 0 1 0 1 0 0 = Unimplemented or Reserved Figure5-8. System Device Identification Register — L w (SDIDL) Table5-9. SDIDL Register Field Descriptions Field Description 7:0 Part Identification Numbe — Each derivative in the HCS08 Family has a unique identification number. The ID[7:0] MC9S08SH8 is hard coded to the value 0x014. See also ID bits inTable5-8. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 71

Chapter5 Resets, Interrupts, and General System Control 5.7.7 System Power Management Status and Control 1 Register (SPMSC1) This high page register contains status and control bits to support the low voltage detect function, and to enable the bandgap voltage reference for use by the ADC module. 7 6 5 4 3 2 1 0 R LVWF1 0 0 LVWIE LVDRE LVDSE LVDE BGBE W LVWACK Reset: 0 0 0 1 1 1 0 0 = Unimplemented or Reserved 1 LVWF will be set in the case when V transitions below the trip point or after reset and V is already below V Supply Supply LVW Figure5-9. System Power Management Status and Control 1 Register (SPMSC1) Table5-10. SPMSC1 Register Field Descriptions Field Description 7 Low-Voltage Warning Flag — The LVWF bit indicates the low voltage warning status. LVWF 0 Low voltage warning is not present. 1 Low voltage warning is present or was present. 6 Low-Voltage Warning Acknowledge — The LVWF bit indicates the low voltage warning status.Writing a 1 to LVWACK LVWACK clears LVWF to a 0 if a low voltage warning is not present. 5 Low-Voltage Warning Interrupt Enable — This bit enables hardware interrupt requests for LVWF. LVWIE 0 Hardware interrupt disabled (use polling). 1 Request a hardware interrupt when LVWF = 1. 4 Low-Voltage Detect Reset Enable — This write-once bit enables LVD events to generate a hardware reset LVDRE (provided LVDE = 1). 0 LVD events do not generate hardware resets. 1 Force an MCU reset when an enabled low-voltage detect event occurs. 3 Low-Voltage Detect Stop Enable — Provided LVDE = 1, thiscontrol bit determines whether the low-voltage LVDSE detect function operates when the MCU is in stop mode. 0 Low-voltage detect disabled during stop mode. 1 Low-voltage detect enabled during stop mode. 2 Low-VoltageDetectEnable—Thiswrite-oncebitenableslow-voltagedetectlogicandqualifiestheoperation LVDE of other bits in this register. 0 LVD logic disabled. 1 LVD logic enabled. 0 BandgapBufferEnable—Thisbitenablesaninternalbufferforthebandgapvoltagereferenceforusebythe BGBE ADC module on one of its internal channels or ACMP on its ACMP+ input. 0 Bandgap buffer disabled. 1 Bandgap buffer enabled. MC9S08SH8MCUSeriesDataSheet,Rev.3 72 Freescale Semiconductor

Chapter5 Resets, Interrupts, and General System Control 5.7.8 System Power Management Status and Control 2 Register (SPMSC2) Thisregisterisusedtoreportthestatusofthelowvoltagewarningfunction,andtoconfigurethestopmode behavior of the MCU. 7 6 5 4 3 2 1 0 R 0 0 PPDF 0 0 LVDV1 LVWV PPDC2 W PPDACK Power-on Reset: 0 0 0 0 0 0 0 0 LVD Reset: 0 0 u u 0 0 0 0 Any other Reset: 0 0 u u 0 0 0 0 = Unimplemented or Reserved u = Unaffected by reset 1 This bit can be written only one time after power-on reset. Additional writes are ignored. 2 This bit can be written only one time after reset. Additional writes are ignored. Figure5-10. System Power Management Status and Control 2 Register (SPMSC2) Table5-11. SPMSC2 Register Field Descriptions Field Description 5 Low-VoltageDetectVoltageSelect—Thiswrite-oncebitselectsthelowvoltagedetect(LVD)trippointsetting. LVDV It also selects the warning voltage range. SeeTable5-12. 4 Low-VoltageWarningVoltageSelect—Thisbitselectsthelowvoltagewarning(LVW)trippointvoltage.See LVWV Table5-12. 3 Partial Power Down Flag — This read-only status bit indicates that the MCU has recovered from stop2 mode. PPDF 0 MCU has not recovered from stop2 mode. 1 MCU recovered from stop2 mode. 2 Partial Power Down Acknowledge — Writing a 1 to PPDACK clears the PPDF bit PPDACK 0 Partial Power Down Control — This write-once bit controls whether stop2 or stop3 mode is selected. PPDC 0 Stop3 mode enabled. 1 Stop2, partial power down, mode enabled. Table5-12. LVD and LVW trip point typical values1 LVDV:LVWV LVW Trip Point LVD Trip Point 0:0 V = 2.74 V V = 2.56 V LVW0 LVD0 0:1 V = 2.92 V LVW1 1:0 V = 4.3 V V = 4.0 V LVW2 LVD1 1:1 V = 4.6 V LVW3 1 See Electrical Characteristics appendix for minimum and maximum values. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 73

Chapter5 Resets, Interrupts, and General System Control MC9S08SH8MCUSeriesDataSheet,Rev.3 74 Freescale Semiconductor

Chapter 6 Parallel Input/Output Control This section explains software controls related to parallel input/output (I/O) and pin control. The MC9S08SH8hasthreeparallelI/Oportswhichincludeatotalof17I/Opinsandoneoutput-onlypin.See Chapter2, “Pins and Connections,” for more information about pin assignments and external hardware considerations of these pins. Manyofthesepinsaresharedwithon-chipperipheralssuchastimersystems,communicationsystems,or pin interrupts as shown inTable2-1. The peripheral modules have priority over the general-purpose I/O functions so that when a peripheral is enabled, the I/O functions associated with the shared pins are disabled. After reset, the shared peripheral functions are disabled and the pins are configured as inputs (PTxDDn=0). The pin control functions for each pin are configured as follows: slew ratedisabled (PTxSEn =0), low drive strength selected (PTxDSn = 0), and internal pull-ups disabled (PTxPEn = 0). NOTE Not all general-purpose I/O pins are available on all packages. To avoid extra current drain from floating input pins, the user’s reset initialization routine in the application program must either enable on-chip pull-up devices or change the direction of unconnected pins to outputs so the pins do not float. 6.1 Port Data and Data Direction Reading and writing of parallel I/Os are performed through the port data registers. The direction, either inputoroutput,iscontrolledthroughtheportdatadirectionregisters.TheparallelI/Oportfunctionforan individual pin is illustrated in the block diagram shown in Figure6-1. The data direction control bit (PTxDDn) determines whether the output buffer for the associated pin is enabled,andalsocontrolsthesourceforportdataregisterreads.Theinputbufferfortheassociatedpinis always enabled unless the pin is enabled as an analog function or is an output-only pin. Whenashareddigitalfunctionisenabledforapin,theoutputbufferiscontrolledbythesharedfunction. However,thedatadirectionregisterbitwillcontinuetocontrolthesourceforreadsoftheportdataregister. Whenasharedanalogfunctionisenabledforapin,boththeinputandoutputbuffersaredisabled.Avalue of 0 is read for any port data bit where the bit is an input (PTxDDn = 0) and the input buffer is disabled. In general, whenever a pin is shared with both an alternate digital function and an analog function, the analog function has priority such that if both the digital and analog functions are enabled, the analog function controls the pin. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 75

Chapter6 Parallel Input/Output Control Itisagoodprogrammingpracticetowritetotheportdataregisterbeforechangingthedirectionofaport pin to become an output. This ensures that the pin will not be driven momentarily with an old data value that happened to be in the port data register. PTxDDn D Q Output Enable PTxDn D Q Output Data 1 Port Read Data 0 Synchronizer Input Data BUSCLK Figure6-1. Parallel I/O Block Diagram 6.2 Pull-up, Slew Rate, and Drive Strength AssociatedwiththeparallelI/Oportsisasetofregisterslocatedinthehighpageregisterspacethatoperate independentlyoftheparallelI/Oregisters.Theseregistersareusedtocontrolpull-ups,slewrate,anddrive strength for the pins. Aninternalpull-updevicecanbeenabledforeachportpinbysettingthecorrespondingbitinthepull-up enableregister(PTxPEn).Thepull-updeviceisdisabledifthepinisconfiguredasanoutputbytheparallel I/O control logic or any shared peripheral function regardless of the state of the corresponding pull-up enable register bit. The pull-up device is also disabled if the pin is controlled by an analog function. Slewratecontrolcanbeenabledforeachportpinbysettingthecorrespondingbitintheslewratecontrol register(PTxSEn).Whenenabled,slewcontrollimitstherateatwhichanoutputcantransitioninorderto reduce EMC emissions. Slew rate control has no effect on pins that are configured as inputs. An output pin can be selected to have high output drive strength by setting the corresponding bit in the drive strength select register (PTxDSn). When high drive is selected, a pin is capable of sourcing and sinkinggreatercurrent.EventhougheveryI/Opincanbeselectedashighdrive,theusermustensurethat thetotalcurrentsourceandsinklimitsfortheMCUarenotexceeded.Drivestrengthselectionisintended toaffecttheDCbehaviorofI/Opins.However,theACbehaviorisalsoaffected.Highdriveallowsapin to drive a greater load with the same switching speed as a low drive enabled pin into a smaller load. Because of this, the EMC emissions may be affected by enabling pins as high drive. MC9S08SH8MCUSeriesDataSheet,Rev.3 76 Freescale Semiconductor

Chapter6 Parallel Input/Output Control 6.3 Ganged Output The MC9S08SH8 devices contain a feature that allows for up to eight port pins to be tied together externally to allow higher output current drive. The ganged output drive control register (GNGC) is a write-onceregisterthatisusedtoenabledthegangedoutputfeatureandselectwhichportpinswillbeused as ganged outputs. The GNGEN bit in GNGC enables ganged output. The GNGPS[7:1] bits are used to select which pin will be part of the ganged output. When GNGEN is set, any pin that is enabled as a ganged output will be automatically configured as an output and follow the data, drive strength and slew rate control of PTC0. The ganged output drive pin mapping is shown in Table 6-1. NOTE See the DC characteristics in the electrical section for maximum Port I/O currents allowed for this MCU. Whenapinisenabledasgangedoutput,thisfeaturewillhavepriorityover any digital module. An enabled analog function will have priority over the ganged output pin. SeeTable 2-1 for information on pin priority. . Table6-1. Ganged Output Pin Enable GNGC Register Bits GNGPS7 GNGPS6 GNGPS5 GNGPS4 GNGPS3 GNGPS2 GNGPS1 GNGEN1 Port Pin2 PTB5 PTB4 PTB3 PTB2 PTC3 PTC2 PTC1 PTC0 Data Direction Control Pin is automatically configured as output when pin is enabled as ganged output. Data Control PTCD0 in PTCD controls data value of output DriveStrength Control PTCDS0 in PTCDS controls drive stength of output Slew Rate Control PTCSE0 in PTCSE controls slew rate of output 1 Ganged output not available on 8-pin packages. PTC3-PTC0 not available on 16-pin packages, however PTC0 control registers are still used to control ganged output. 2 When GNGEN = 1, PTC0 is forced to an output, regardless of the value in PTCDD0 in PTCDD. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 77

Chapter6 Parallel Input/Output Control 6.4 Pin Interrupts PortA[3:0]andportB[3:0]pinscanbeconfiguredasexternalinterruptinputsandasanexternalmeansof waking the MCU from stop3 or wait low-power modes. The block diagram forthe pin interrupts is shown Figure6-2. PTxACK BUSCLK 1 VDD RESET PTxIF PIxn 0S PTxPS0 DCLRQ SYNCHRONIZER CK PTxES0 PORT STOP STOP BYPASS PTx INTERRUPT FF INTERRUPT 1 REQUEST PIxn 0 S PTxPSn PTxMOD PTxIE PTxESn Figure6-2.Pin Interrupt Block Diagram Writing to the PTxPSn bits in the port interrupt pin enable register (PTxPS) independently enables or disableseachportpininterrupt.Eachportcanbeconfiguredasedgesensitiveoredgeandlevelsensitive based on the PTxMOD bit in the port interrupt status and control register (PTxSC). Edge sensitivity can besoftwareprogrammedtobeeitherfallingorrising;thelevelcanbeeitherloworhigh.Thepolarityof the edge or edge and level sensitivity is selected using the PTxESn bits in the port interrupt edge select register (PTxES). Synchronouslogicisusedtodetectedges.Priortodetectinganedge,enabledpininterruptinputsmustbe atthedeassertedlogiclevel.Afallingedgeisdetectedwhenanenabledportinputsignalisseenasalogic 1 (the deasserted level) during one bus cycle and then a logic0 (the asserted level) during the next cycle. Arisingedgeisdetectedwhentheinputsignalisseenasalogic0duringonebuscycleandthenalogic1 during the next cycle. 6.4.1 Edge Only Sensitivity AvalidedgeonanenabledpininterruptwillsetPTxIFinPTxSC.IfPTxIEinPTxSCisset,aninterrupt request will be presented to the CPU. Clearing of PTxIF is accomplished by writing a 1 to PTxACK in PTxSC. 6.4.2 Edge and Level Sensitivity A valid edge or level on an enabledpininterrupt will set PTxIF in PTxSC. If PTxIE in PTxSC is set, an interrupt request will be presented to the CPU. Clearing of PTxIF is accomplished by writing a 1 to PTxACK in PTxSC provided all enabledpin interrupt inputs are at their deasserted levels. PTxIF will remain set if any enabledpininterrupt is asserted while attempting to clear by writing a 1 to PTxACK. MC9S08SH8MCUSeriesDataSheet,Rev.3 78 Freescale Semiconductor

Chapter6 Parallel Input/Output Control 6.4.3 Pull-up/Pull-down Resistors Thepininterruptscanbeconfiguredtouseaninternalpull-up/pull-downresistorusingtheassociatedI/O portpull-upenableregister.Ifaninternalresistorisenabled,thePTxESregisterisusedtoselectwhether the resistor is a pull-up (PTxESn = 0) or a pull-down (PTxESn = 1). 6.4.4 Pin Interrupt Initialization Whenapininterruptisfirstenabled,itispossibletogetafalseinterruptflag.Topreventafalseinterrupt request during pin interrupt initialization, the user should do the following: 1. Mask interrupts by clearing PTxIE in PTxSC. 2. Select the pin polarity by setting the appropriate PTxESn bits in PTxES. 3. If using internal pull-up/pull-down device, configure the associated pull enable bits in PTxPE. 4. Enable the interrupt pins by setting the appropriate PTxPSn bits in PTxPS. 5. Write to PTxACK in PTxSC to clear any false interrupts. 6. Set PTxIE in PTxSC to enable interrupts. 6.5 Pin Behavior in Stop Modes Pin behavior following execution of a STOP instruction depends on the stop mode that is entered. An explanation of pin behavior for the various stop modes follows: • Stop2 mode is a partial power-down mode, whereby I/O latches are maintained in their state as beforetheSTOPinstructionwasexecuted.CPUregisterstatusandthestateofI/Oregistersshould besavedinRAMbeforetheSTOPinstructionisexecutedtoplacetheMCUinstop2mode.Upon recoveryfromstop2mode,beforeaccessinganyI/O,theusershouldexaminethestateofthePPDF bitintheSPMSC2register.IfthePPDFbitis0,I/Omustbeinitializedasifapoweronresethad occurred.IfthePPDFbitis1,I/OdatapreviouslystoredinRAM,beforetheSTOPinstructionwas executed, peripherals may require being initialized and restored to their pre-stop condition. The usermustthenwritea1tothePPDACKbitintheSPMSC2register.AccesstoI/Oisnowpermitted again in the user application program. • In stop3 mode, all I/O is maintained because internal logic circuity stays powered up. Upon recovery, normal I/O function is available to the user. 6.6 Parallel I/O and Pin Control Registers This section provides information about the registers associated with the parallel I/O ports. The data and datadirectionregistersarelocatedinpagezeroofthememorymap.Thepullup,slewrate,drivestrength, and interrupt control registers are located in the high page section of the memory map. RefertotablesinChapter4,“Memory,”fortheabsoluteaddressassignmentsforallparallelI/Oandtheir pin control registers. This section refers to registers and control bits only by their names. A Freescale Semiconductor-provided equate or header file normally is used to translate these names into the appropriate absolute addresses. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 79

Chapter6 Parallel Input/Output Control 6.6.1 Port A Registers Port A is controlled by the registers listed below. The pins PTA4 and PTA5 are unique. PTA4 is output-only, so the control bits for the input function will nothaveanyeffectonthispin.PTA5,whenconfiguredasanoutput,isopendrainwithlowdrivestrength. NOTE This PTA5 pin does not contain a clamp diode to V and should not be DD driven above V . DD WhentheinternalpullupdeviceisenabledonPTA5whenusedasaninput or open drain output the voltage measured on PTA5 will not be pulled to V .TheinternalgatesconnectedtothispinarepulledtoV .IfthePTA5 DD DD pin is required to drive to a V level an external pullup should be used. DD 6.6.1.1 Port A Data Register (PTAD) 7 6 5 4 3 2 1 0 R 0 0 PTAD5 PTAD41 PTAD3 PTAD2 PTAD1 PTAD0 W Reset: 0 0 0 0 0 0 0 0 Figure6-3. Port A Data Register (PTAD) 1 Reads of bit PTAD4 always return the contents of PTAD4, regardless of the value stored in bit PTADD4. Table6-2. PTAD Register Field Descriptions Field Description Port A Data Register Bits — For port A pins that are inputs, reads return the logic level on the pin. For port A 5:0 pins that are configured as outputs, reads return the last value written to this register. PTAD[5:0] Writes are latched into all bits of this register. For port A pins that are configured as outputs, the logic level is driven out the corresponding MCU pin. ResetforcesPTADtoall0s,butthese0sarenotdrivenoutthecorrespondingpinsbecauseresetalsoconfigures all port pins as high-impedance inputs with pull-ups/pull-downs disabled. MC9S08SH8MCUSeriesDataSheet,Rev.3 80 Freescale Semiconductor

Chapter6 Parallel Input/Output Control 6.6.1.2 Port A Data Direction Register (PTADD) 7 6 5 4 3 2 1 0 R 0 0 PTADD5 PTADD41 PTADD3 PTADD2 PTADD1 PTADD0 W Reset: 0 0 0 0 0 0 0 0 Figure6-4. Port A Data Direction Register (PTADD) 1 PTADD4 has no effect on the output-only PTA4 pin. Table6-3. PTADD Register Field Descriptions Field Description DataDirectionforPortABits—Theseread/writebitscontrolthedirectionofportApinsandwhatisreadfor 5:0 PTAD reads. PTADD[5:0] 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port A bit n and PTAD reads return the contents of PTADn. 6.6.1.3 Port A Pull Enable Register (PTAPE) 7 6 5 4 3 2 1 0 R 0 0 PTAPE51 PTAPE42 PTAPE3 PTAPE2 PTAPE1 PTAPE0 W Reset: 0 0 0 0 0 0 0 0 Figure6-5. Internal Pull Enable for Port A Register (PTAPE) 1 PTAPE5 can be used to pullup PTA5 when configured as open drain output pin, however pullup will not pull pin all the way to V . An external pullup should be used if applications requires PTA5 to be driven to V . DD DD 2 PTAPE4 has no effect on the output-only PTA4 pin. Table6-4. PTAPE Register Field Descriptions Field Description InternalPullEnableforPortABits—Eachofthesecontrolbitsdeterminesiftheinternalpull-uporpull-down 5:0 device is enabled for the associated PTA pin. For port A pins (except for PTA5) that are configured as outputs, PTAPE[5:0] these bits have no effect and the internal pull devices are disabled. 0 Internal pull-up/pull-down device disabled for port A bit n. 1 Internal pull-up/pull-down device enabled for port A bit n. NOTE Pull-down devices only apply when using pin interrupt functions, when corresponding edge select and pin select functions are configured. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 81

Chapter6 Parallel Input/Output Control 6.6.1.4 Port A Slew Rate Enable Register (PTASE) 7 6 5 4 3 2 1 0 R 0 0 R PTASE4 PTASE3 PTASE2 PTASE1 PTASE0 W Reset: 0 0 0 0 0 0 0 0 Figure6-6. Slew Rate Enable for Port A Register (PTASE) Table6-5. PTASE Register Field Descriptions Field Description 5 Reserved Bits — These bits are unused on this MCU, writes have no affect and could read as 1s or 0s. Reserved OutputSlewRateEnableforPortABits—Eachofthesecontrolbitsdeterminesiftheoutputslewratecontrol 4:0 is enabled for the associated PTA pin. For port A pins that are configured as inputs, these bits have no effect. PTASE[4:0] 0 Output slew rate control disabled for port A bit n. 1 Output slew rate control enabled for port A bit n. 6.6.1.5 Port A Drive Strength Selection Register (PTADS) 7 6 5 4 3 2 1 0 R 0 0 R PTADS4 PTADS3 PTADS2 PTADS1 PTADS0 W Reset: 0 0 0 0 0 0 0 0 Figure6-7. Drive Strength Selection for Port A Register (PTADS) Table6-6. PTADS Register Field Descriptions Field Description 5 Reserved Bits — These bits are unused on this MCU, writes have no affect and could read as 1s or 0s. Reserved Output Drive Strength Selection for Port A Bits — Each of these control bits selects between low and high 4:0 output drive for the associated PTA pin. For port A pins that are configured as inputs, these bits have no effect. PTADS[4:0] 0 Low output drive strength selected for port A bit n. 1 High output drive strength selected for port A bit n. MC9S08SH8MCUSeriesDataSheet,Rev.3 82 Freescale Semiconductor

Chapter6 Parallel Input/Output Control 6.6.1.6 Port A Interrupt Status and Control Register (PTASC) 7 6 5 4 3 2 1 0 R 0 0 0 0 PTAIF 0 PTAIE PTAMOD W PTAACK Reset: 0 0 0 0 0 0 0 0 Figure6-8. Port A Interrupt Status and Control Register (PTASC) Table6-7. PTASC Register Field Descriptions Field Description 3 Port A Interrupt Flag — PTAIF indicates when a port A interrupt is detected. Writes have no effect on PTAIF. PTAIF 0 No port A interrupt detected. 1 Port A interrupt detected. 2 Port A Interrupt Acknowledge — Writing a 1 to PTAACK is part of the flag clearing mechanism. PTAACK PTAACK always reads as 0. 1 Port A Interrupt Enable — PTAIE determines whether a port A interrupt is requested. PTAIE 0 Port A interrupt request not enabled. 1 Port A interrupt request enabled. 0 Port A Detection Mode — PTAMOD (along with the PTAES bits) controls the detection mode of the port A PTAMOD interrupt pins. 0 Port A pins detect edges only. 1 Port A pins detect both edges and levels. 6.6.1.7 Port A Interrupt Pin Select Register (PTAPS) 7 6 5 4 3 2 1 0 R 0 0 0 0 PTAPS3 PTAPS2 PTAPS1 PTAPS0 W Reset: 0 0 0 0 0 0 0 0 Figure6-9. Port A Interrupt Pin Select Register (PTAPS) Table6-8. PTAPS Register Field Descriptions Field Description 3:0 Port A Interrupt Pin Selects — Each of the PTAPSn bits enable the corresponding port A interrupt pin. PTAPS[3:0] 0 Pin not enabled as interrupt. 1 Pin enabled as interrupt. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 83

Chapter6 Parallel Input/Output Control 6.6.1.8 Port A Interrupt Edge Select Register (PTAES) 7 6 5 4 3 2 1 0 R 0 0 0 0 PTAES3 PTAES2 PTAES1 PTAES0 W Reset: 0 0 0 0 0 0 0 0 Figure6-10. Port A Edge Select Register (PTAES) Table6-9. PTAES Register Field Descriptions Field Description 3:0 Port A Edge Selects — Each of the PTAESn bits serves a dual purpose by selecting the polarity of the active PTAES[3:0] interrupt edge as well as selecting a pull-up or pull-down device if enabled. 0 Apull-updeviceisconnectedtotheassociatedpinanddetectsfallingedge/lowlevelforinterruptgeneration. 1 A pull-down device is connected to the associated pin and detects rising edge/high level for interrupt generation. MC9S08SH8MCUSeriesDataSheet,Rev.3 84 Freescale Semiconductor

Chapter6 Parallel Input/Output Control 6.6.2 Port B Registers Port B is controlled by the registers listed below. 6.6.2.1 Port B Data Register (PTBD) 7 6 5 4 3 2 1 0 R PTBD7 PTBD6 PTBD5 PTBD4 PTBD3 PTBD2 PTBD1 PTBD0 W Reset: 0 0 0 0 0 0 0 0 Figure6-11. Port B Data Register (PTBD) Table6-10. PTBD Register Field Descriptions Field Description 7:0 Port B Data Register Bits — For port B pins that are inputs, reads return the logic level on the pin. For port B PTBD[7:0] pins that are configured as outputs, reads return the last value written to this register. Writes are latched into all bits of this register. For port B pins that are configured as outputs, the logic level is driven out the corresponding MCU pin. ResetforcesPTBDtoall0s,butthese0sarenotdrivenoutthecorrespondingpinsbecauseresetalsoconfigures all port pins as high-impedance inputs with pull-ups/pull-downs disabled. 6.6.2.2 Port B Data Direction Register (PTBDD) 7 6 5 4 3 2 1 0 R PTBDD7 PTBDD6 PTBDD5 PTBDD4 PTBDD3 PTBDD2 PTBDD1 PTBDD0 W Reset: 0 0 0 0 0 0 0 0 Figure6-12. Port B Data Direction Register (PTBDD) Table6-11. PTBDD Register Field Descriptions Field Description 7:0 DataDirectionforPortBBits—Theseread/writebitscontrolthedirectionofportBpinsandwhatisreadfor PTBDD[7:0] PTBD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port B bit n and PTBD reads return the contents of PTBDn. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 85

Chapter6 Parallel Input/Output Control 6.6.2.3 Port B Pull Enable Register (PTBPE) 7 6 5 4 3 2 1 0 R PTBPE7 PTBPE6 PTBPE5 PTBPE4 PTBPE3 PTBPE2 PTBPE1 PTBPE0 W Reset: 0 0 0 0 0 0 0 0 Figure6-13. Internal Pull Enable for Port B Register (PTBPE) Table6-12. PTBPE Register Field Descriptions Field Description 7:0 InternalPullEnableforPortBBits—Eachofthesecontrolbitsdeterminesiftheinternalpull-uporpull-down PTBPE[7:0] deviceisenabledfortheassociatedPTBpin.ForportBpinsthatareconfiguredasoutputs,thesebitshaveno effect and the internal pull devices are disabled. 0 Internal pull-up/pull-down device disabled for port B bit n. 1 Internal pull-up/pull-down device enabled for port B bit n. NOTE Pull-down devices only apply when using pin interrupt functions, when corresponding edge select and pin select functions are configured. 6.6.2.4 Port B Slew Rate Enable Register (PTBSE) 7 6 5 4 3 2 1 0 R PTBSE7 PTBSE6 PTBSE5 PTBSE4 PTBSE3 PTBSE2 PTBSE1 PTBSE0 W Reset: 0 0 0 0 0 0 0 0 Figure6-14. Slew Rate Enable for Port B Register (PTBSE) Table6-13. PTBSE Register Field Descriptions Field Description 7:0 OutputSlewRateEnableforPortBBits—Eachofthesecontrolbitsdeterminesiftheoutputslewratecontrol PTBSE[7:0] is enabled for the associated PTB pin. For port B pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for port B bit n. 1 Output slew rate control enabled for port B bit n. MC9S08SH8MCUSeriesDataSheet,Rev.3 86 Freescale Semiconductor

Chapter6 Parallel Input/Output Control 6.6.2.5 Port B Drive Strength Selection Register (PTBDS) 7 6 5 4 3 2 1 0 R PTBDS7 PTBDS6 PTBDS5 PTBDS4 PTBDS3 PTBDS2 PTBDS1 PTBDS0 W Reset: 0 0 0 0 0 0 0 0 Figure6-15. Drive Strength Selection for Port B Register (PTBDS) Table6-14. PTBDS Register Field Descriptions Field Description 7:0 Output Drive Strength Selection for Port B Bits — Each of these control bits selects between low and high PTBDS[7:0] output drive for the associated PTB pin. For port B pins that are configured as inputs, these bits have no effect. 0 Low output drive strength selected for port B bit n. 1 High output drive strength selected for port B bit n. 6.6.2.6 Port B Interrupt Status and Control Register (PTBSC) 7 6 5 4 3 2 1 0 R 0 0 0 0 PTBIF 0 PTBIE PTBMOD W PTBACK Reset: 0 0 0 0 0 0 0 0 Figure6-16. Port B Interrupt Status and Control Register (PTBSC) Table6-15. PTBSC Register Field Descriptions Field Description 3 Port B Interrupt Flag — PTBIF indicates when a Port B interrupt is detected. Writes have no effect on PTBIF. PTBIF 0 No Port B interrupt detected. 1 Port B interrupt detected. 2 Port B Interrupt Acknowledge — Writing a 1 to PTBACK is part of the flag clearing mechanism. PTBACK PTBACK always reads as 0. 1 Port B Interrupt Enable — PTBIE determines whether a port B interrupt is requested. PTBIE 0 Port B interrupt request not enabled. 1 Port B interrupt request enabled. 0 Port B Detection Mode — PTBMOD (along with the PTBES bits) controls the detection mode of the port B PTBMOD interrupt pins. 0 Port B pins detect edges only. 1 Port B pins detect both edges and levels. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 87

Chapter6 Parallel Input/Output Control 6.6.2.7 Port B Interrupt Pin Select Register (PTBPS) 7 6 5 4 3 2 1 0 R 0 0 0 0 PTBPS3 PTBPS2 PTBPS1 PTBPS0 W Reset: 0 0 0 0 0 0 0 0 Figure6-17. Port B Interrupt Pin Select Register (PTBPS) Table6-16. PTBPS Register Field Descriptions Field Description 3:0 Port B Interrupt Pin Selects — Each of the PTBPSn bits enable the corresponding port B interrupt pin. PTBPS[3:0] 0 Pin not enabled as interrupt. 1 Pin enabled as interrupt. 6.6.2.8 Port B Interrupt Edge Select Register (PTBES) 7 6 5 4 3 2 1 0 R 0 0 0 0 PTBES3 PTBES2 PTBES1 PTBES0 W Reset: 0 0 0 0 0 0 0 0 Figure6-18. Port B Edge Select Register (PTBES) Table6-17. PTBES Register Field Descriptions Field Description 3:0 Port B Edge Selects — Each of the PTBESn bits serves a dual purpose by selecting the polarity of the active PTBES[3:0] interrupt edge as well as selecting a pull-up or pull-down device if enabled. 0 Apull-updeviceisconnectedtotheassociatedpinanddetectsfallingedge/lowlevelforinterruptgeneration. 1 A pull-down device is connected to the associated pin and detects rising edge/high level for interrupt generation. MC9S08SH8MCUSeriesDataSheet,Rev.3 88 Freescale Semiconductor

Chapter6 Parallel Input/Output Control 6.6.3 Port C Registers Port C is controlled by the registers listed below. 6.6.3.1 Port C Data Register (PTCD) 7 6 5 4 3 2 1 0 R 0 0 0 0 PTCD3 PTCD2 PTCD1 PTCD0 W Reset: 0 0 0 0 0 0 0 0 Figure6-19. Port C Data Register (PTCD) Table6-18. PTCD Register Field Descriptions Field Description 3:0 Port C Data Register Bits — For port C pins that are inputs, reads return the logic level on the pin. For port C PTCD[3:0] pins that are configured as outputs, reads return the last value written to this register. Writes are latched into all bits of this register. For port C pins that are configured as outputs, the logic level is driven out the corresponding MCU pin. Reset forces PTCD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins as high-impedance inputs with pull-ups disabled. 6.6.3.2 Port C Data Direction Register (PTCDD) 7 6 5 4 3 2 1 0 R 0 0 0 0 PTCDD3 PTCDD2 PTCDD1 PTCDD0 W Reset: 0 0 0 0 0 0 0 0 Figure6-20. Port C Data Direction Register (PTCDD) Table6-19. PTCDD Register Field Descriptions Field Description 3:0 DataDirectionforPortCBits—Theseread/writebitscontrolthedirectionofportCpinsandwhatisreadfor PTCDD[3:0] PTCD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port C bit n and PTCD reads return the contents of PTCDn. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 89

Chapter6 Parallel Input/Output Control 6.6.3.3 Port C Pull Enable Register (PTCPE) 7 6 5 4 3 2 1 0 R 0 0 0 0 PTCPE3 PTCPE2 PTCPE1 PTCPE0 W Reset: 0 0 0 0 0 0 0 0 Figure6-21. Internal Pull Enable for Port C Register (PTCPE) Table6-20. PTCPE Register Field Descriptions Field Description 3:0 Internal Pull Enable for Port C Bits — Each of these control bits determines if the internal pull-up device is PTCPE[3:0] enabledfortheassociatedPTCpin.ForportCpinsthatareconfiguredasoutputs,thesebitshavenoeffectand the internal pull devices are disabled. 0 Internal pull-up device disabled for port C bit n. 1 Internal pull-up device enabled for port C bit n. 6.6.3.4 Port C Slew Rate Enable Register (PTCSE) 7 6 5 4 3 2 1 0 R 0 0 0 0 PTCSE3 PTCSE2 PTCSE1 PTCSE0 W Reset: 0 0 0 0 0 0 0 0 Figure6-22. Slew Rate Enable for Port C Register (PTCSE) Table6-21. PTCSE Register Field Descriptions Field Description 3:0 OutputSlewRateEnableforPortCBits—Eachofthesecontrolbitsdeterminesiftheoutputslewratecontrol PTCSE[3:0] is enabled for the associated PTC pin. For port C pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for port C bit n. 1 Output slew rate control enabled for port C bit n. MC9S08SH8MCUSeriesDataSheet,Rev.3 90 Freescale Semiconductor

Chapter6 Parallel Input/Output Control 6.6.3.5 Port C Drive Strength Selection Register (PTCDS) 7 6 5 4 3 2 1 0 R 0 0 0 0 PTCDS3 PTCDS2 PTCDS1 PTCDS0 W Reset: 0 0 0 0 0 0 0 0 Figure6-23. Drive Strength Selection for Port C Register (PTCDS) Table6-22. PTCDS Register Field Descriptions Field Description 3:0 Output Drive Strength Selection for Port C Bits — Each of these control bits selects between low and high PTCDS[3:0] output drive for the associated PTC pin. For port C pins that are configured as inputs, these bits have no effect. 0 Low output drive strength selected for port C bit n. 1 High output drive strength selected for port C bit n. 6.6.3.6 Ganged Output Drive Control Register (GNGC) 7 6 5 4 3 2 1 0 R GNGPS7 GNGPS6 GNGPS5 GNGPS4 GNGPS3 GNGPS2 GNGPS1 GNGEN W Reset: 0 0 0 0 0 0 0 0 Figure6-24. Ganged Output Drive Control Register (GNGC) Table6-23.GNGC Register Field Descriptions Field Description 7:1 Ganged Output Pin Select Bits— These write-once control bits selects whether the associated pin (see GNGP[7:1] Table6-1forpinsavailable)isenabledforgangedoutput.WhenGNGEN=1,allenabledgangedoutputpinswill be controlled by the data, drive strength and slew rate settings for PTCO. 0 Associated pin is not part of the ganged output drive. 1 Assoicated pin is part of the ganged output drive. Requires GNGEN = 1. 0 GangedOutputDriveEnableBit—Thiswrite-oncecontrolbitselectswhetherthegangedoutputdrivefeature GNGEN is enabled. 0 Ganged output drive disabled. 1 Ganged output drive enabled. PTC0 forced to output regardless of the value of PTCDD0 in PTCDD. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 91

Chapter6 Parallel Input/Output Control MC9S08SH8MCUSeriesDataSheet,Rev.3 92 Freescale Semiconductor

Chapter 7 Central Processor Unit (S08CPUV2) 7.1 Introduction This section provides summary information about the registers, addressing modes, and instruction set of the CPU of the HCS08 Family. For a more detailed discussion, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMV1/D. The HCS08 CPU is fully source- and object-code-compatible with the M68HC08 CPU. Several instructionsandenhancedaddressingmodeswereaddedtoimproveCcompilerefficiencyandtosupport anewbackgrounddebugsystemwhichreplacesthemonitormodeofearlierM68HC08microcontrollers (MCU). 7.1.1 Features Features of the HCS08 CPU include: • Object code fully upward-compatible with M68HC05 and M68HC08 Families • All registers and memory are mapped to a single 64-Kbyte address space • 16-bit stack pointer (any size stack anywhere in 64-Kbyte address space) • 16-bit index register (H:X) with powerful indexed addressing modes • 8-bit accumulator (A) • Many instructions treat X as a second general-purpose 8-bit register • Seven addressing modes: — Inherent — Operands in internal registers — Relative — 8-bit signed offset to branch destination — Immediate — Operand in next object code byte(s) — Direct — Operand in memory at 0x0000–0x00FF — Extended — Operand anywhere in 64-Kbyte address space — Indexed relative to H:X — Five submodes including auto increment — Indexed relative to SP — Improves C efficiency dramatically • Memory-to-memory data move instructions with four address mode combinations • Overflow, half-carry, negative, zero, and carry condition codes support conditional branching on the results of signed, unsigned, and binary-coded decimal (BCD) operations • Efficient bit manipulation instructions • Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions • STOP and WAIT instructions to invoke low-power operating modes MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 93

Chapter7 Central Processor Unit (S08CPUV2) 7.2 Programmer’s Model and CPU Registers Figure7-1 shows the five CPU registers. CPU registers are not part of the memory map. 7 0 ACCUMULATOR A 16-BIT INDEX REGISTER H:X H INDEX REGISTER (HIGH) INDEX REGISTER (LOW) X 15 8 7 0 STACK POINTER SP 15 0 PROGRAM COUNTER PC 7 0 CONDITION CODE REGISTER V 1 1 H I N Z C CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure7-1. CPU Registers 7.2.1 Accumulator (A) The A accumulator is a general-purpose 8-bit register. One operand input to the arithmetic logic unit (ALU)isconnectedtotheaccumulatorandtheALUresultsareoftenstoredintotheAaccumulatorafter arithmeticandlogicaloperations.Theaccumulatorcanbeloadedfrommemoryusingvariousaddressing modes to specify the address where the loaded data comes from, or the contents of A can be stored to memory using various addressing modes to specify the address where data from A will be stored. Reset has no effect on the contents of the A accumulator. 7.2.2 Index Register (H:X) This16-bitregisterisactuallytwoseparate8-bitregisters(HandX),whichoftenworktogetherasa16-bit addresspointerwhereHholdstheupperbyteofanaddressandXholdsthelowerbyteoftheaddress.All indexed addressing mode instructions use the full 16-bit value in H:X as an index reference pointer; however, for compatibility with the earlier M68HC05 Family, some instructions operate only on the low-order 8-bit half (X). Many instructions treat X as a second general-purpose 8-bit register that can be used to hold 8-bit data values.Xcanbecleared,incremented,decremented,complemented,negated,shifted,orrotated.Transfer instructionsallowdatatobetransferredfromAortransferredtoAwherearithmeticandlogicaloperations can then be performed. ForcompatibilitywiththeearlierM68HC05Family,Hisforcedto0x00duringreset.Resethasnoeffect on the contents of X. MC9S08SH8MCUSeriesDataSheet,Rev.3 94 Freescale Semiconductor

Chapter7 Central Processor Unit (S08CPUV2) 7.2.3 Stack Pointer (SP) This 16-bit address pointer register points at the next available location on the automatic last-in-first-out (LIFO) stack. The stack may be located anywhere in the 64-Kbyte address space that has RAM and can beanysizeuptotheamountofavailableRAM.Thestackisusedtoautomaticallysavethereturnaddress for subroutine calls, the return address and CPU registers during interrupts, and for local variables. The AIS(addimmediatetostackpointer)instructionaddsan8-bitsignedimmediatevaluetoSP.Thisismost often used to allocate or deallocate space for local variables on the stack. SP is forced to 0x00FF at reset for compatibility with the earlier M68HC05 Family. HCS08 programs normally change the value in SP to the address of the last location (highest address) in on-chip RAM during reset initialization to free up direct page RAM (from the end of the on-chip registers to 0x00FF). The RSP (reset stack pointer) instruction was included for compatibility with the M68HC05 Family and is seldom used in new HCS08 programs because it only affects the low-order half of the stack pointer. 7.2.4 Program Counter (PC) Theprogramcounterisa16-bitregisterthatcontainstheaddressofthenextinstructionoroperandtobe fetched. During normal program execution, the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, interrupt, and return operations load the program counter with an address other than that of the next sequential location. This is called a change-of-flow. During reset, the program counter is loaded with the reset vector that is located at 0xFFFE and 0xFFFF. The vector stored there is the address of the first instruction that will be executed after exiting the reset state. 7.2.5 Condition Code Register (CCR) The 8-bit condition code register contains the interrupt mask (I) and five flags that indicate the results of theinstructionjustexecuted.Bits6and5aresetpermanentlyto1.Thefollowingparagraphsdescribethe functions of the condition code bits in general terms. For a more detailed explanation of how each instruction sets the CCR bits, refer to theHCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMv1. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 95

Chapter7 Central Processor Unit (S08CPUV2) 7 0 CONDITION CODE REGISTER V 1 1 H I N Z C CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure7-2. Condition Code Register Table7-1. CCR Register Field Descriptions Field Description 7 Two’sComplementOverfl wFlag—TheCPUsetstheoverflowflagwhenatwo’scomplementoverflowoccurs. V The signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag. 0 No overflow 1 Overflow 4 Half-CarryFlag—TheCPUsetsthehalf-carryflagwhenacarryoccursbetweenaccumulatorbits3and4during H an add-without-carry (ADD) or add-with-carry (ADC) operation. The half-carry flag is required for binary-coded decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and C condition code bits to automatically add a correction value to the result from a previous ADD or ADC on BCD operands to correct the result to a valid BCD value. 0 No carry between bits 3 and 4 1 Carry between bits 3 and 4 3 Interrupt Mask Bit — When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts I are enabled when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set automaticallyaftertheCPUregistersaresavedonthestack,butbeforethefirstinstructionoftheinterruptservice routine is executed. Interrupts are not recognized at the instruction boundary after any instruction that clears I (CLI or TAP). This ensuresthatthenextinstructionafteraCLIorTAPwillalwaysbeexecutedwithoutthepossibilityofanintervening interrupt, provided I was set. 0 Interrupts enabled 1 Interrupts disabled 2 Negative Flag — The CPU sets the negative flag when an arithmetic operation, logic operation, or data N manipulationproducesanegativeresult,settingbit7oftheresult.Simplyloadingorstoringan8-bitor16-bitvalue causes N to be set if the most significant bit of the loaded or stored value was 1. 0 Non-negative result 1 Negative result 1 Zero Flag — The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation Z produces a result of 0x00 or 0x0000. Simply loading or storing an 8-bit or 16-bit value causes Z to be set if the loaded or stored value was all 0s. 0 Non-zero result 1 Zero result 0 Carry/BorrowFlag—TheCPUsetsthecarry/borrowflagwhenanadditionoperationproducesacarryoutofbit C 7oftheaccumulatororwhenasubtractionoperationrequiresaborrow.Someinstructions—suchasbittestand branch, shift, and rotate — also clear or set the carry/borrow flag. 0 No carry out of bit 7 1 Carry out of bit 7 MC9S08SH8MCUSeriesDataSheet,Rev.3 96 Freescale Semiconductor

Chapter7 Central Processor Unit (S08CPUV2) 7.3 Addressing Modes AddressingmodesdefinethewaytheCPUaccessesoperandsanddata.IntheHCS08,allmemory,status andcontrolregisters,andinput/output(I/O)portsshareasingle64-Kbytelinearaddressspacesoa16-bit binary address can uniquely identify any memory location. This arrangement means that the same instructionsthataccessvariablesinRAMcanalsobeusedtoaccessI/Oandcontrolregistersornonvolatile program space. Someinstructionsusemorethanoneaddressingmode.Forinstance,moveinstructionsuseoneaddressing mode to specify the source operand and a second addressing mode to specify the destination address. InstructionssuchasBRCLR,BRSET,CBEQ,andDBNZuseoneaddressingmodetospecifythelocation of an operand for a test and then use relative addressing mode to specify the branch destination address whenthetestedconditionistrue.ForBRCLR,BRSET,CBEQ,andDBNZ,theaddressingmodelistedin the instruction set tables is the addressing mode needed to access the operand to be tested, and relative addressing mode is implied for the branch destination. 7.3.1 Inherent Addressing Mode (INH) In this addressing mode, operands needed to complete the instruction (if any) are located within CPU registers so the CPU does not need to access memory to get any operands. 7.3.2 Relative Addressing Mode (REL) Relativeaddressingmodeisusedtospecifythedestinationlocationforbranchinstructions.Asigned8-bit offsetvalueislocatedinthememorylocationimmediatelyfollowingtheopcode.Duringexecution,ifthe branch condition is true, the signed offset is sign-extended to a 16-bit value and is added to the current contents of the program counter, which causes program execution to continue at the branch destination address. 7.3.3 Immediate Addressing Mode (IMM) In immediate addressing mode, the operand needed to complete the instruction is included in the object codeimmediatelyfollowingtheinstructionopcodeinmemory.Inthecaseofa16-bitimmediateoperand, the high-order byte is located in the next memory location after the opcode, and the low-order byte is located in the next memory location after that. 7.3.4 Direct Addressing Mode (DIR) Indirectaddressingmode,theinstructionincludesthelow-ordereightbitsofanaddressinthedirectpage (0x0000–0x00FF).Duringexecutiona16-bitaddressisformedbyconcatenatinganimplied0x00forthe high-order half of the address and the direct address from the instruction to get the 16-bit address where thedesiredoperandislocated.Thisisfasterandmorememoryefficientthanspecifyingacomplete16-bit address for the operand. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 97

Chapter7 Central Processor Unit (S08CPUV2) 7.3.5 Extended Addressing Mode (EXT) In extended addressing mode, the full 16-bit address of the operand is located in the next two bytes of program memory after the opcode (high byte first). 7.3.6 Indexed Addressing Mode Indexedaddressingmodehassevenvariationsincludingfivethatusethe16-bitH:Xindexregisterpairand two that use the stack pointer as the base reference. 7.3.6.1 Indexed, No Offset (IX) Thisvariationofindexedaddressingusesthe16-bitvalueintheH:Xindexregisterpairastheaddressof the operand needed to complete the instruction. 7.3.6.2 Indexed, No Offset with Post Increment (IX+) Thisvariationofindexedaddressingusesthe16-bitvalueintheH:Xindexregisterpairastheaddressof the operand needed to complete the instruction. The index register pair is then incremented (H:X=H:X+0x0001) after the operand has been fetched. This addressing mode is only used for MOV and CBEQ instructions. 7.3.6.3 Indexed, 8-Bit Offset (IX1) Thisvariationofindexedaddressingusesthe16-bitvalueintheH:Xindexregisterpairplusanunsigned 8-bit offset included in the instruction as the address of the operand needed to complete the instruction. 7.3.6.4 Indexed, 8-Bit Offset with Post Increment (IX1+) Thisvariationofindexedaddressingusesthe16-bitvalueintheH:Xindexregisterpairplusanunsigned 8-bit offset included in the instruction as the address of the operand needed to complete the instruction. Theindexregisterpairisthenincremented(H:X=H:X+0x0001)aftertheoperandhasbeenfetched.This addressing mode is used only for the CBEQ instruction. 7.3.6.5 Indexed, 16-Bit Offset (IX2) Thisvariationofindexedaddressingusesthe16-bitvalueintheH:Xindexregisterpairplusa16-bitoffset included in the instruction as the address of the operand needed to complete the instruction. 7.3.6.6 SP-Relative, 8-Bit Offset (SP1) Thisvariationofindexedaddressingusesthe16-bitvalueinthestackpointer(SP)plusanunsigned8-bit offset included in the instruction as the address of the operand needed to complete the instruction. MC9S08SH8MCUSeriesDataSheet,Rev.3 98 Freescale Semiconductor

Chapter7 Central Processor Unit (S08CPUV2) 7.3.6.7 SP-Relative, 16-Bit Offset (SP2) This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus a 16-bit offset included in the instruction as the address of the operand needed to complete the instruction. 7.4 Special Operations The CPU performs a few special operations that are similar to instructions but do not have opcodes like otherCPUinstructions.Inaddition,afewinstructionssuchasSTOPandWAITdirectlyaffectotherMCU circuitry. This section provides additional information about these operations. 7.4.1 Reset Sequence Reset can be caused by a power-on-reset (POR) event, internal conditions such as the COP (computer operating properly) watchdog, or by assertion of an external active-low reset pin. When a reset event occurs, the CPU immediately stops whatever it is doing (the MCU does not wait for an instruction boundary before responding to a reset event). For a more detailed discussion about how the MCU recognizes resets and determines the source, refer to theResets, Interrupts, and System Configuration chapter. Thereseteventisconsideredconcludedwhenthesequencetodeterminewhethertheresetcamefroman internalsourceisdoneandwhentheresetpinisnolongerasserted.Attheconclusionofaresetevent,the CPU performs a 6-cycle sequence to fetch the reset vector from 0xFFFE and 0xFFFF and to fill the instruction queue in preparation for execution of the first program instruction. 7.4.2 Interrupt Sequence When an interrupt is requested, the CPU completes the current instruction before responding to the interrupt.Atthispoint,theprogramcounterispointingatthestartofthenextinstruction,whichiswhere the CPU should return after servicing the interrupt. The CPU responds to an interrupt by performing the samesequenceofoperationsasforasoftwareinterrupt(SWI)instruction,excepttheaddressusedforthe vector fetch is determined by the highest priority interrupt that is pending when the interrupt sequence started. The CPU sequence for an interrupt is: 1. Store the contents of PCL, PCH, X, A, and CCR on the stack, in that order. 2. Set the I bit in the CCR. 3. Fetch the high-order half of the interrupt vector. 4. Fetch the low-order half of the interrupt vector. 5. Delay for one free bus cycle. 6. Fetch three bytes of program information starting at the address indicated by the interrupt vector to fill the instruction queue in preparation for execution of the first instruction in the interrupt service routine. After the CCR contents are pushed onto the stack, the I bit in the CCR is set to prevent other interrupts while in the interrupt service routine. Although it is possible to clear the I bit with an instruction in the MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 99

Chapter7 Central Processor Unit (S08CPUV2) interrupt service routine, this would allow nesting of interrupts (which is not recommended because it leads to programs that are difficult to debug and maintain). ForcompatibilitywiththeearlierM68HC05MCUs,thehigh-orderhalfoftheH:Xindexregisterpair(H) is not saved on the stack as part of the interrupt sequence. The user must use a PSHH instruction at the beginning of the service routine to save H and then use a PULH instruction just before the RTI that ends theinterruptserviceroutine.ItisnotnecessarytosaveHifyouarecertainthattheinterruptserviceroutine does not use any instructions or auto-increment addressing modes that might change the value of H. The software interrupt (SWI) instruction is like a hardware interrupt except that it is not masked by the global I bit in the CCR and it is associated with an instruction opcode within the program so it is not asynchronous to program execution. 7.4.3 Wait Mode Operation The WAIT instruction enables interrupts by clearing the I bit in the CCR. It then halts the clocks to the CPU to reduce overall power consumption while the CPU is waiting for the interrupt or reset event that willwaketheCPUfromwaitmode.Whenaninterruptorreseteventoccurs,theCPUclockswillresume and the interrupt or reset event will be processed normally. IfaserialBACKGROUNDcommandisissuedtotheMCUthroughthebackgrounddebuginterfacewhile theCPUisinwaitmode,CPUclockswillresumeandtheCPUwillenteractivebackgroundmodewhere otherserialbackgroundcommandscanbeprocessed.Thisensuresthatahostdevelopmentsystemcanstill gain access to a target MCU even if it is in wait mode. 7.4.4 Stop Mode Operation Usually, all system clocks, including the crystal oscillator (when used), are halted during stop mode to minimize power consumption. In such systems, external circuitry is needed to control the time spent in stop mode and to issue a signal to wake up the target MCU when it is time to resume processing. Unlike the earlier M68HC05 and M68HC08 MCUs, the HCS08 can be configured to keep a minimum set of clocks running in stop mode. This optionally allows an internal periodic signal to wake the target MCU fromstop mode. When a host debug system is connected to the background debug pin (BKGD) and the ENBDM control bithasbeensetbyaserialcommandthroughthebackgroundinterface(orbecausetheMCUwasresetinto activebackgroundmode),theoscillatorisforcedtoremainactivewhentheMCUentersstopmode.Inthis case,ifaserialBACKGROUNDcommandisissuedtotheMCUthroughthebackgrounddebuginterface whiletheCPUisinstopmode,CPUclockswillresumeandtheCPUwillenteractivebackgroundmode whereotherserialbackgroundcommandscanbeprocessed.Thisensuresthatahostdevelopmentsystem can still gain access to a target MCU even if it is in stop mode. RecoveryfromstopmodedependsontheparticularHCS08andwhethertheoscillatorwasstoppedinstop mode. Refer to theModes of Operationchapter for more details. MC9S08SH8MCUSeriesDataSheet,Rev.3 100 Freescale Semiconductor

Chapter7 Central Processor Unit (S08CPUV2) 7.4.5 BGND Instruction The BGND instruction is new to the HCS08 compared to the M68HC08. BGND would not be used in normal user programs because it forces the CPU to stop processing user instructions and enter the active background mode. The only way to resume execution of the user program is through reset or by a host debug system issuing a GO, TRACE1, or TAGGO serial command through the background debug interface. Software-based breakpoints can be set by replacing an opcode at the desired breakpoint address with the BGNDopcode.Whentheprogramreachesthisbreakpointaddress,theCPUisforcedtoactivebackground mode rather than continuing the user program. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 101

Chapter7 Central Processor Unit (S08CPUV2) 7.5 HCS08 Instruction Set Summary Table7-2 provides a summary of the HCS08 instruction set in all possible addressing modes. The table shows operand construction, execution time in internal bus clock cycles, and cycle-by-cycle details for each addressing mode variation of each instruction. Table7-2. Instruction Set Summary (Sheet 1 of 9) s Affect SFoourrmce Operation AddresMode Object Code Cycles CyDce-btayi-lCsyc V1 1onH CCI NR Z C ADC #opr8i IMM A9 ii 2 pp ADC opr8a DIR B9 dd 3 rpp ADC opr16a EXT C9 hh ll 4 prpp ADC oprx16,X Add with Carry IX2 D9 ee ff 4 prpp ↕ 1 1 ↕ – ↕ ↕ ↕ ADC oprx8,X A← (A) + (M) + (C) IX1 E9 ff 3 rpp ADC ,X IX F9 3 rfp ADC oprx16,SP SP2 9E D9 ee ff 5 pprpp ADC oprx8,SP SP1 9E E9 ff 4 prpp ADD #opr8i IMM AB ii 2 pp ADD opr8a DIR BB dd 3 rpp ADD opr16a EXT CB hh ll 4 prpp ADD oprx16,X Add without Carry IX2 DB ee ff 4 prpp ↕ 1 1 ↕ – ↕ ↕ ↕ ADD oprx8,X A← (A) + (M) IX1 EB ff 3 rpp ADD ,X IX FB 3 rfp ADD oprx16,SP SP2 9E DB ee ff 5 pprpp ADD oprx8,SP SP1 9E EB ff 4 prpp Add Immediate Value (Signed) to AIS #opr8i StackPointer IMM A7 ii 2 pp – 1 1 – – – – – SP← (SP) + (M) Add Immediate Value (Signed) to AIX #opr8i IndexRegister (H:X) IMM AF ii 2 pp – 1 1 – – – – – H:X← (H:X) + (M) AND #opr8i IMM A4 ii 2 pp AND opr8a DIR B4 dd 3 rpp AND opr16a EXT C4 hh ll 4 prpp AND oprx16,X Logical AND IX2 D4 ee ff 4 prpp 0 1 1 – –↕ ↕ – AND oprx8,X A← (A) & (M) IX1 E4 ff 3 rpp AND ,X IX F4 3 rfp AND oprx16,SP SP2 9E D4 ee ff 5 pprpp AND oprx8,SP SP1 9E E4 ff 4 prpp ASL opr8a Arithmetic Shift Left DIR 38 dd 5 rfwpp ASLA INH 48 1 p ASLX INH 58 1 p C 0 ↕ 1 1 – –↕ ↕ ↕ ASL oprx8,X IX1 68 ff 5 rfwpp b7 b0 ASL ,X IX 78 4 rfwp ASL oprx8,SP (Same as LSL) SP1 9E 68 ff 6 prfwpp ASR opr8a DIR 37 dd 5 rfwpp ASRA Arithmetic Shift Right INH 47 1 p ASRX INH 57 1 p ↕ 1 1 – –↕ ↕ ↕ ASR oprx8,X C IX1 67 ff 5 rfwpp ASR ,X b7 b0 IX 77 4 rfwp ASR oprx8,SP SP1 9E 67 ff 6 prfwpp MC9S08SH8MCUSeriesDataSheet,Rev.3 102 Freescale Semiconductor

Chapter7 Central Processor Unit (S08CPUV2) Table7-2. Instruction Set Summary (Sheet 2 of 9) s Affect SFoourrmce Operation AddresMode Object Code Cycles CyDce-btayi-lCsyc V1 1onH CCI NR Z C Branch if Carry Bit Clear BCC rel REL 24 rr 3 ppp – 1 1 – – – – – (if C = 0) DIR (b0) 11 dd 5 rfwpp DIR (b1) 13 dd 5 rfwpp DIR (b2) 15 dd 5 rfwpp Clear Bit n in Memory DIR (b3) 17 dd 5 rfwpp BCLR n,opr8a – 1 1 – – – – – (Mn← 0) DIR (b4) 19 dd 5 rfwpp DIR (b5) 1B dd 5 rfwpp DIR (b6) 1D dd 5 rfwpp DIR (b7) 1F dd 5 rfwpp Branch if Carry Bit Set (if C = 1) BCS rel REL 25 rr 3 ppp – 1 1 – – – – – (Same as BLO) BEQ rel Branch if Equal (if Z = 1) REL 27 rr 3 ppp – 1 1 – – – – – Branch if Greater Than or Equal To BGE rel REL 90 rr 3 ppp – 1 1 – – – – – (if N ⊕ V=0) (Signed) Enter active background if ENBDM=1 BGND Waits for and processes BDM commands INH 82 5+ fp...ppp – 1 1 – – – – – until GO, TRACE1, or TAGGO Branch if Greater Than (if Z| (N ⊕ V)=0) BGT rel REL 92 rr 3 ppp – 1 1 – – – – – (Signed) BHCC rel Branch if Half Carry Bit Clear (if H = 0) REL 28 rr 3 ppp – 1 1 – – – – – BHCS rel Branch if Half Carry Bit Set (if H = 1) REL 29 rr 3 ppp – 1 1 – – – – – BHI rel Branch if Higher (if C | Z = 0) REL 22 rr 3 ppp – 1 1 – – – – – Branch if Higher or Same (if C = 0) BHS rel REL 24 rr 3 ppp – 1 1 – – – – – (Same as BCC) BIHrel Branch if IRQ Pin High (if IRQ pin = 1) REL 2F rr 3 ppp – 1 1 – – – – – BIL rel Branch if IRQ Pin Low (if IRQ pin = 0) REL 2E rr 3 ppp – 1 1 – – – – – BIT #opr8i IMM A5 ii 2 pp BIT opr8a DIR B5 dd 3 rpp BIT opr16a EXT C5 hh ll 4 prpp Bit Test BIT oprx16,X IX2 D5 ee ff 4 prpp (A) & (M) 0 1 1 – –↕ ↕ – BIT oprx8,X IX1 E5 ff 3 rpp (CCR Updated but Operands Not Changed) BIT ,X IX F5 3 rfp BIT oprx16,SP SP2 9E D5 ee ff 5 pprpp BIT oprx8,SP SP1 9E E5 ff 4 prpp Branch if Less Than or Equal To BLE rel REL 93 rr 3 ppp – 1 1 – – – – – (if Z| (N⊕V) = 1) (Signed) BLO rel Branch if Lower (if C = 1) (Same as BCS) REL 25 rr 3 ppp – 1 1 – – – – – BLS rel Branch if Lower or Same (if C | Z = 1) REL 23 rr 3 ppp – 1 1 – – – – – BLTrel Branch if Less Than (if N ⊕ V =1) (Signed) REL 91 rr 3 ppp – 1 1 – – – – – BMC rel Branch if Interrupt Mask Clear (if I = 0) REL 2C rr 3 ppp – 1 1 – – – – – BMI rel Branch if Minus (if N = 1) REL 2B rr 3 ppp – 1 1 – – – – – BMS rel Branch if Interrupt Mask Set (if I = 1) REL 2D rr 3 ppp – 1 1 – – – – – BNE rel Branch if Not Equal (if Z = 0) REL 26 rr 3 ppp – 1 1 – – – – – MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 103

Chapter7 Central Processor Unit (S08CPUV2) Table7-2. Instruction Set Summary (Sheet 3 of 9) s Affect SFoourrmce Operation AddresMode Object Code Cycles CyDce-btayi-lCsyc V1 1onH CCI NR Z C BPL rel Branch if Plus (if N = 0) REL 2A rr 3 ppp – 1 1 – – – – – BRA rel Branch Always (if I = 1) REL 20 rr 3 ppp – 1 1 – – – – – DIR (b0) 01 dd rr 5 rpppp DIR (b1) 03 dd rr 5 rpppp DIR (b2) 05 dd rr 5 rpppp DIR (b3) 07 dd rr 5 rpppp BRCLR n,opr8a,rel Branch if Bitn inMemory Clear (if (Mn) = 0) – 1 1 – – – –↕ DIR (b4) 09 dd rr 5 rpppp DIR (b5) 0B dd rr 5 rpppp DIR (b6) 0D dd rr 5 rpppp DIR (b7) 0F dd rr 5 rpppp BRN rel Branch Never (if I = 0) REL 21 rr 3 ppp – 1 1 – – – – – DIR (b0) 00 dd rr 5 rpppp DIR (b1) 02 dd rr 5 rpppp DIR (b2) 04 dd rr 5 rpppp DIR (b3) 06 dd rr 5 rpppp BRSET n,opr8a,rel Branch if Bitn inMemory Set (if (Mn) = 1) – 1 1 – – – –↕ DIR (b4) 08 dd rr 5 rpppp DIR (b5) 0A dd rr 5 rpppp DIR (b6) 0C dd rr 5 rpppp DIR (b7) 0E dd rr 5 rpppp DIR (b0) 10 dd 5 rfwpp DIR (b1) 12 dd 5 rfwpp DIR (b2) 14 dd 5 rfwpp DIR (b3) 16 dd 5 rfwpp BSET n,opr8a Set Bitnin Memory (Mn← 1) – 1 1 – – – – – DIR (b4) 18 dd 5 rfwpp DIR (b5) 1A dd 5 rfwpp DIR (b6) 1C dd 5 rfwpp DIR (b7) 1E dd 5 rfwpp Branch to Subroutine PC←(PC) + $0002 BSR rel push (PCL); SP← (SP) – $0001 REL AD rr 5 ssppp – 1 1 – – – – – push (PCH); SP← (SP) – $0001 PC← (PC) +rel CBEQ opr8a,rel Compare and... Branch if (A) = (M) DIR 31 dd rr 5 rpppp CBEQA #opr8i,rel Branch if (A) = (M) IMM 41 ii rr 4 pppp CBEQX #opr8i,rel Branch if (X) = (M) IMM 51 ii rr 4 pppp – 1 1 – – – – – CBEQ oprx8,X+,rel Branch if (A) = (M) IX1+ 61 ff rr 5 rpppp CBEQ ,X+,rel Branch if (A) = (M) IX+ 71 rr 5 rfppp CBEQoprx8,SP,rel Branch if (A) = (M) SP1 9E 61 ff rr 6 prpppp CLC Clear Carry Bit (C← 0) INH 98 1 p – 1 1 – – – – 0 CLI Clear Interrupt Mask Bit (I← 0) INH 9A 1 p – 1 1 – 0 – – – CLR opr8a Clear M← $00 DIR 3F dd 5 rfwpp CLRA A← $00 INH 4F 1 p CLRX X← $00 INH 5F 1 p CLRH H← $00 INH 8C 1 p 0 1 1 – – 0 1 – CLR oprx8,X M← $00 IX1 6F ff 5 rfwpp CLR ,X M← $00 IX 7F 4 rfwp CLR oprx8,SP M← $00 SP1 9E 6F ff 6 prfwpp MC9S08SH8MCUSeriesDataSheet,Rev.3 104 Freescale Semiconductor

Chapter7 Central Processor Unit (S08CPUV2) Table7-2. Instruction Set Summary (Sheet 4 of 9) s Affect SFoourrmce Operation AddresMode Object Code Cycles CyDce-btayi-lCsyc V1 1onH CCI NR Z C CMP #opr8i IMM A1 ii 2 pp CMP opr8a DIR B1 dd 3 rpp CMP opr16a EXT C1 hh ll 4 prpp Compare Accumulator with Memory CMP oprx16,X IX2 D1 ee ff 4 prpp A – M ↕ 1 1 – –↕ ↕ ↕ CMP oprx8,X IX1 E1 ff 3 rpp (CCR Updated But Operands Not Changed) CMP ,X IX F1 3 rfp CMP oprx16,SP SP2 9E D1 ee ff 5 pprpp CMP oprx8,SP SP1 9E E1 ff 4 prpp COM opr8a Complement M← (M)= $FF – (M) DIR 33 dd 5 rfwpp COMA (One’s Complement) A← (A) = $FF – (A) INH 43 1 p COMX X← (X) = $FF – (X) INH 53 1 p 0 1 1 – –↕ ↕ 1 COM oprx8,X M← (M) = $FF – (M) IX1 63 ff 5 rfwpp COM ,X M← (M) = $FF – (M) IX 73 4 rfwp COM oprx8,SP M← (M) = $FF – (M) SP1 9E 63 ff 6 prfwpp CPHXopr16a EXT 3E hh ll 6 prrfpp Compare IndexRegister (H:X) withMemory CPHX #opr16i IMM 65 jj kk 3 ppp (H:X) – (M:M + $0001) ↕ 1 1 – –↕ ↕ ↕ CPHXopr8a DIR 75 dd 5 rrfpp (CCR Updated But Operands Not Changed) CPHX oprx8,SP SP1 9E F3 ff 6 prrfpp CPX #opr8i IMM A3 ii 2 pp CPX opr8a DIR B3 dd 3 rpp CPX opr16a Compare X (Index Register Low) with EXT C3 hh ll 4 prpp CPX oprx16,X Memory IX2 D3 ee ff 4 prpp ↕ 1 1 – –↕ ↕ ↕ CPX oprx8,X X – M IX1 E3 ff 3 rpp CPX ,X (CCR Updated But Operands Not Changed) IX F3 3 rfp CPX oprx16,SP SP2 9E D3 ee ff 5 pprpp CPX oprx8,SP SP1 9E E3 ff 4 prpp Decimal Adjust Accumulator DAA INH 72 1 p U 1 1 – –↕ ↕ ↕ After ADD or ADC of BCD Values DBNZ opr8a,rel DIR 3B dd rr 7 rfwpppp DBNZA rel INH 4B rr 4 fppp Decrement A, X, or M and Branch if Not Zero DBNZX rel INH 5B rr 4 fppp (if (result)≠0) – 1 1 – – – – – DBNZ oprx8,X,rel IX1 6B ff rr 7 rfwpppp DBNZX Affects X Not H DBNZ ,X,rel IX 7B rr 6 rfwppp DBNZ oprx8,SP,rel SP1 9E 6B ff rr 8 prfwpppp DEC opr8a Decrement M← (M) – $01 DIR 3A dd 5 rfwpp DECA A← (A) – $01 INH 4A 1 p DECX X← (X) – $01 INH 5A 1 p ↕ 1 1 – –↕ ↕ – DEC oprx8,X M← (M) – $01 IX1 6A ff 5 rfwpp DEC ,X M← (M) – $01 IX 7A 4 rfwp DEC oprx8,SP M← (M) – $01 SP1 9E 6A ff 6 prfwpp Divide DIV INH 52 6 fffffp – 1 1 – – –↕ ↕ A← (H:A)÷(X); H← Remainder EOR #opr8i Exclusive OR Memory with Accumulator IMM A8 ii 2 pp EOR opr8a A← (A⊕ M) DIR B8 dd 3 rpp EOR opr16a EXT C8 hh ll 4 prpp EOR oprx16,X IX2 D8 ee ff 4 prpp 0 1 1 – –↕ ↕ – EOR oprx8,X IX1 E8 ff 3 rpp EOR ,X IX F8 3 rfp EOR oprx16,SP SP2 9E D8 ee ff 5 pprpp EOR oprx8,SP SP1 9E E8 ff 4 prpp MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 105

Chapter7 Central Processor Unit (S08CPUV2) Table7-2. Instruction Set Summary (Sheet 5 of 9) s Affect SFoourrmce Operation AddresMode Object Code Cycles CyDce-btayi-lCsyc V1 1onH CCI NR Z C INC opr8a Increment M← (M) + $01 DIR 3C dd 5 rfwpp INCA A← (A) + $01 INH 4C 1 p INCX X← (X) + $01 INH 5C 1 p ↕ 1 1 – –↕ ↕ – INC oprx8,X M← (M) + $01 IX1 6C ff 5 rfwpp INC ,X M← (M) + $01 IX 7C 4 rfwp INC oprx8,SP M← (M) + $01 SP1 9E 6C ff 6 prfwpp JMP opr8a DIR BC dd 3 ppp JMP opr16a EXT CC hh ll 4 pppp Jump JMP oprx16,X IX2 DC ee ff 4 pppp – 1 1 – – – – – PC← Jump Address JMP oprx8,X IX1 EC ff 3 ppp JMP ,X IX FC 3 ppp JSR opr8a Jump to Subroutine DIR BD dd 5 ssppp JSR opr16a PC← (PC) +n (n = 1, 2, or 3) EXT CD hh ll 6 pssppp JSR oprx16,X Push (PCL); SP← (SP) – $0001 IX2 DD ee ff 6 pssppp – 1 1 – – – – – JSR oprx8,X Push (PCH); SP← (SP) – $0001 IX1 ED ff 5 ssppp JSR ,X PC← Unconditional Address IX FD 5 ssppp LDA #opr8i IMM A6 ii 2 pp LDA opr8a DIR B6 dd 3 rpp LDA opr16a EXT C6 hh ll 4 prpp LDA oprx16,X Load Accumulator from Memory IX2 D6 ee ff 4 prpp 0 1 1 – –↕ ↕ – LDA oprx8,X A← (M) IX1 E6 ff 3 rpp LDA ,X IX F6 3 rfp LDA oprx16,SP SP2 9E D6 ee ff 5 pprpp LDA oprx8,SP SP1 9E E6 ff 4 prpp LDHX #opr16i IMM 45 jj kk 3 ppp LDHX opr8a DIR 55 dd 4 rrpp LDHX opr16a EXT 32 hh ll 5 prrpp Load Index Register (H:X) LDHX ,X IX 9E AE 5 prrfp 0 1 1 – –↕ ↕ – H:X← (M:M+ $0001) LDHX oprx16,X IX2 9E BE ee ff 6 pprrpp LDHX oprx8,X IX1 9E CE ff 5 prrpp LDHX oprx8,SP SP1 9E FE ff 5 prrpp LDX #opr8i IMM AE ii 2 pp LDX opr8a DIR BE dd 3 rpp LDX opr16a EXT CE hh ll 4 prpp LDX oprx16,X Load X (Index Register Low) from Memory IX2 DE ee ff 4 prpp 0 1 1 – –↕ ↕ – LDX oprx8,X X← (M) IX1 EE ff 3 rpp LDX ,X IX FE 3 rfp LDX oprx16,SP SP2 9E DE ee ff 5 pprpp LDX oprx8,SP SP1 9E EE ff 4 prpp LSL opr8a Logical Shift Left DIR 38 dd 5 rfwpp LSLA INH 48 1 p LSLX C 0 INH 58 1 p ↕ 1 1 – –↕ ↕ ↕ LSL oprx8,X IX1 68 ff 5 rfwpp b7 b0 LSL ,X IX 78 4 rfwp LSL oprx8,SP (Same as ASL) SP1 9E 68 ff 6 prfwpp LSR opr8a DIR 34 dd 5 rfwpp Logical Shift Right LSRA INH 44 1 p LSRX INH 54 1 p ↕ 1 1 – – 0↕ ↕ LSR oprx8,X 0 C IX1 64 ff 5 rfwpp LSR ,X b7 b0 IX 74 4 rfwp LSR oprx8,SP SP1 9E 64 ff 6 prfwpp MC9S08SH8MCUSeriesDataSheet,Rev.3 106 Freescale Semiconductor

Chapter7 Central Processor Unit (S08CPUV2) Table7-2. Instruction Set Summary (Sheet 6 of 9) s Affect SFoourrmce Operation AddresMode Object Code Cycles CyDce-btayi-lCsyc V1 1onH CCI NR Z C MOVopr8a,opr8a Move DIR/DIR 4E dd dd 5 rpwpp MOV opr8a,X+ (M) ←(M) DIR/IX+ 5E dd 5 rfwpp destination source 0 1 1 – –↕ ↕ – MOV #opr8i,opr8a In IX+/DIR and DIR/IX+ Modes, IMM/DIR 6E ii dd 4 pwpp MOV ,X+,opr8a H:X← (H:X) + $0001 IX+/DIR 7E dd 5 rfwpp Unsigned multiply MUL INH 42 5 ffffp – 1 1 0 – – – 0 X:A← (X)× (A) NEG opr8a Negate M← – (M) = $00 – (M) DIR 30 dd 5 rfwpp NEGA (Two’s Complement) A← – (A) = $00 – (A) INH 40 1 p NEGX X← – (X) = $00 – (X) INH 50 1 p ↕ 1 1 – –↕ ↕ ↕ NEG oprx8,X M← – (M) = $00 – (M) IX1 60 ff 5 rfwpp NEG ,X M← – (M) = $00 – (M) IX 70 4 rfwp NEG oprx8,SP M← – (M) = $00 – (M) SP1 9E 60 ff 6 prfwpp NOP No Operation — Uses 1 Bus Cycle INH 9D 1 p – 1 1 – – – – – Nibble Swap Accumulator NSA INH 62 1 p – 1 1 – – – – – A← (A[3:0]:A[7:4]) ORA #opr8i IMM AA ii 2 pp ORA opr8a DIR BA dd 3 rpp ORA opr16a EXT CA hh ll 4 prpp ORA oprx16,X Inclusive ORAccumulator andMemory IX2 DA ee ff 4 prpp 0 1 1 – –↕ ↕ – ORA oprx8,X A← (A) | (M) IX1 EA ff 3 rpp ORA ,X IX FA 3 rfp ORA oprx16,SP SP2 9E DA ee ff 5 pprpp ORA oprx8,SP SP1 9E EA ff 4 prpp Push Accumulator onto Stack PSHA INH 87 2 sp – 1 1 – – – – – Push (A); SP←(SP) – $0001 Push H (Index Register High) onto Stack PSHH INH 8B 2 sp – 1 1 – – – – – Push (H); SP←(SP) – $0001 Push X (Index Register Low) onto Stack PSHX INH 89 2 sp – 1 1 – – – – – Push (X); SP←(SP) – $0001 Pull Accumulator from Stack PULA INH 86 3 ufp – 1 1 – – – – – SP←(SP +$0001); Pull (A) Pull H (Index Register High) from Stack PULH INH 8A 3 ufp – 1 1 – – – – – SP←(SP +$0001); Pull (H) Pull X (Index Register Low) from Stack PULX INH 88 3 ufp – 1 1 – – – – – SP←(SP +$0001); Pull (X) ROL opr8a Rotate Left through Carry DIR 39 dd 5 rfwpp ROLA INH 49 1 p ROLX INH 59 1 p ROL oprx8,X C IX1 69 ff 5 rfwpp ↕ 1 1 – –↕ ↕ ↕ ROL ,X b7 b0 IX 79 4 rfwp ROL oprx8,SP SP1 9E 69 ff 6 prfwpp ROR opr8a Rotate Right through Carry DIR 36 dd 5 rfwpp RORA INH 46 1 p RORX INH 56 1 p ROR oprx8,X C IX1 66 ff 5 rfwpp ↕ 1 1 – –↕ ↕ ↕ ROR ,X b7 b0 IX 76 4 rfwp ROR oprx8,SP SP1 9E 66 ff 6 prfwpp MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 107

Chapter7 Central Processor Unit (S08CPUV2) Table7-2. Instruction Set Summary (Sheet 7 of 9) s Affect SFoourrmce Operation AddresMode Object Code Cycles CyDce-btayi-lCsyc V1 1onH CCI NR Z C Reset Stack Pointer (Low Byte) RSP SPL← $FF INH 9C 1 p – 1 1 – – – – – (High Byte Not Affected) Return from Interrupt SP← (SP) + $0001; Pull (CCR) SP← (SP) + $0001; Pull (A) RTI INH 80 9 uuuuufppp ↕ 1 1 ↕ ↕ ↕ ↕ ↕ SP← (SP) + $0001; Pull (X) SP← (SP) + $0001; Pull (PCH) SP← (SP) + $0001; Pull (PCL) Return from Subroutine RTS SP← SP + $0001;Pull (PCH) INH 81 5 ufppp – 1 1 – – – – – SP← SP + $0001; Pull (PCL) SBC #opr8i IMM A2 ii 2 pp SBC opr8a DIR B2 dd 3 rpp SBC opr16a EXT C2 hh ll 4 prpp SBC oprx16,X Subtract with Carry IX2 D2 ee ff 4 prpp ↕ 1 1 – –↕ ↕ ↕ SBC oprx8,X A← (A) – (M) – (C) IX1 E2 ff 3 rpp SBC ,X IX F2 3 rfp SBC oprx16,SP SP2 9E D2 ee ff 5 pprpp SBC oprx8,SP SP1 9E E2 ff 4 prpp Set Carry Bit SEC INH 99 1 p – 1 1 – – – – 1 (C← 1) Set Interrupt Mask Bit SEI INH 9B 1 p – 1 1 – 1 – – – (I← 1) STA opr8a DIR B7 dd 3 wpp STA opr16a EXT C7 hh ll 4 pwpp STA oprx16,X IX2 D7 ee ff 4 pwpp Store Accumulator in Memory STA oprx8,X IX1 E7 ff 3 wpp 0 1 1 – –↕ ↕ – M←(A) STA ,X IX F7 2 wp STA oprx16,SP SP2 9E D7 ee ff 5 ppwpp STA oprx8,SP SP1 9E E7 ff 4 pwpp STHXopr8a DIR 35 dd 4 wwpp Store H:X (Index Reg.) STHXopr16a EXT 96 hh ll 5 pwwpp 0 1 1 – –↕ ↕ – (M:M + $0001)← (H:X) STHX oprx8,SP SP1 9E FF ff 5 pwwpp Enable Interrupts: Stop Processing STOP Refer to MCU Documentation INH 8E 2 fp... – 1 1 – 0 – – – I bit← 0; Stop Processing STX opr8a DIR BF dd 3 wpp STX opr16a EXT CF hh ll 4 pwpp STX oprx16,X Store X (Low 8 Bits of Index Register) IX2 DF ee ff 4 pwpp STX oprx8,X in Memory IX1 EF ff 3 wpp 0 1 1 – – ↕ ↕ – STX ,X M←(X) IX FF 2 wp STX oprx16,SP SP2 9E DF ee ff 5 ppwpp STX oprx8,SP SP1 9E EF ff 4 pwpp MC9S08SH8MCUSeriesDataSheet,Rev.3 108 Freescale Semiconductor

Chapter7 Central Processor Unit (S08CPUV2) Table7-2. Instruction Set Summary (Sheet 8 of 9) s Affect SFoourrmce Operation AddresMode Object Code Cycles CyDce-btayi-lCsyc V1 1onH CCI NR Z C SUB #opr8i IMM A0 ii 2 pp SUB opr8a DIR B0 dd 3 rpp SUB opr16a EXT C0 hh ll 4 prpp SUB oprx16,X Subtract IX2 D0 ee ff 4 prpp ↕ 1 1 – –↕ ↕ ↕ SUB oprx8,X A← (A) – (M) IX1 E0 ff 3 rpp SUB ,X IX F0 3 rfp SUB oprx16,SP SP2 9E D0 ee ff 5 pprpp SUB oprx8,SP SP1 9E E0 ff 4 prpp Software Interrupt PC← (PC) + $0001 Push (PCL); SP← (SP) – $0001 Push (PCH); SP← (SP) – $0001 Push (X); SP← (SP) – $0001 SWI INH 83 11 sssssvvfppp – 1 1 – 1 – – – Push (A); SP← (SP) – $0001 Push (CCR); SP← (SP) – $0001 I← 1; PCH← Interrupt Vector High Byte PCL← Interrupt Vector Low Byte Transfer Accumulator to CCR TAP INH 84 1 p ↕ 1 1 ↕ ↕ ↕ ↕ ↕ CCR← (A) Transfer Accumulator to X (Index Register TAX Low) INH 97 1 p – 1 1 – – – – – X← (A) Transfer CCR to Accumulator TPA INH 85 1 p – 1 1 – – – – – A← (CCR) TST opr8a Test for Negative or Zero (M) – $00 DIR 3D dd 4 rfpp TSTA (A) – $00 INH 4D 1 p TSTX (X) – $00 INH 5D 1 p 0 1 1 – –↕ ↕ – TST oprx8,X (M) – $00 IX1 6D ff 4 rfpp TST ,X (M) – $00 IX 7D 3 rfp TST oprx8,SP (M) – $00 SP1 9E 6D ff 5 prfpp Transfer SP to Index Reg. TSX INH 95 2 fp – 1 1 – – – – – H:X← (SP) + $0001 Transfer X (Index Reg. Low) to Accumulator TXA INH 9F 1 p – 1 1 – – – – – A← (X) MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 109

Chapter7 Central Processor Unit (S08CPUV2) Table7-2. Instruction Set Summary (Sheet 9 of 9) s Affect SFoourrmce Operation AddresMode Object Code Cycles CyDce-btayi-lCsyc V1 1onH CCI NR Z C Transfer Index Reg. to SP TXS INH 94 2 fp – 1 1 – – – – – SP← (H:X) – $0001 Enable Interrupts; Wait for Interrupt WAIT INH 8F 2+ fp... – 1 1 – 0 – – – I bit← 0; Halt CPU Source Form: Everything in the source forms columns, except expressions in italic characters, is literal information which must appear in the assembly source file exactly as shown. The initial 3- to 5-letter mnemonic and the characters (#, ( ) and +) are always a literal characters. n Any label or expression that evaluates to a single integer in the range 0-7. opr8i Any label or expression that evaluates to an 8-bit immediate value. opr16i Any label or expression that evaluates to a 16-bit immediate value. opr8a Any label or expression that evaluates to an 8-bit direct-page address ($00xx). opr16a Any label or expression that evaluates to a 16-bit address. oprx8 Any label or expression that evaluates to an unsigned 8-bit value, used for indexed addressing. oprx16 Any label or expression that evaluates to a 16-bit value, used for indexed addressing. rel Any label or expression that refers to an address that is within –128 to +127 locations from the start of the next instruction. Operation Symbols: Addressing Modes: A Accumulator DIR Direct addressing mode CCR Condition code register EXT Extended addressing mode H Index register high byte IMM Immediate addressing mode M Memory location INH Inherent addressing mode n Any bit IX Indexed, no offset addressing mode opr Operand (one or two bytes) IX1 Indexed, 8-bit offset addressing mode PC Program counter IX2 Indexed, 16-bit offset addressing mode PCH Program counter high byte IX+ Indexed, no offset, post increment addressing mode PCL Program counter low byte IX1+ Indexed, 8-bit offset, post increment addressing mode rel Relative program counter offset byte REL Relative addressing mode SP Stack pointer SP1 Stack pointer, 8-bit offset addressing mode SPL Stack pointer low byte SP2 Stack pointer 16-bit offset addressing mode X Index register low byte Cycle-by-Cycle Codes: & Logical AND f Free cycle. This indicates a cycle where the CPU | Logical OR ⊕ does not require use of the system buses. An f Logical EXCLUSIVE OR cycle is always one cycle of the system bus clock ( ) Contents of + Add and is always a read cycle. p Program fetch; read from next consecutive – Subtract, Negation (two’s complement) × Multiply location in program memory ÷ Divide r Read 8-bit operand s Push (write) one byte onto stack # Immediate value ← Loaded with u Pop (read) one byte from stack v Read vector from $FFxx (high byte first) : Concatenated with w Write 8-bit operand CCR Bits: CCR Effects: V Overflow bit ↕ Set or cleared H Half-carry bit – Not affected I Interrupt mask U Undefined N Negative bit Z Zero bit C Carry/borrow bit MC9S08SH8MCUSeriesDataSheet,Rev.3 110 Freescale Semiconductor

Chapter7 Central Processor Unit (S08CPUV2) Table7-3. Opcode Map (Sheet 1 of 2) Bit-Manipulation Branch Read-Modify-Write Control Register/Memory 00 5 10 5 20 3 30 5 40 1 50 1 60 5 70 4 80 9 90 3 A0 2 B0 3 C0 4 D0 4 E0 3 F0 3 BRSET0 BSET0 BRA NEG NEGA NEGX NEG NEG RTI BGE SUB SUB SUB SUB SUB SUB 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 REL 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 01 5 11 5 21 3 31 5 41 4 51 4 61 5 71 5 81 6 91 3 A1 2 B1 3 C1 4 D1 4 E1 3 F1 3 BRCLR0 BCLR0 BRN CBEQ CBEQA CBEQX CBEQ CBEQ RTS BLT CMP CMP CMP CMP CMP CMP 3 DIR 2 DIR 2 REL 3 DIR 3 IMM 3 IMM 3 IX1+ 2 IX+ 1 INH 2 REL 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 02 5 12 5 22 3 32 5 42 5 52 6 62 1 72 1 82 5+ 92 3 A2 2 B2 3 C2 4 D2 4 E2 3 F2 3 BRSET1 BSET1 BHI LDHX MUL DIV NSA DAA BGND BGT SBC SBC SBC SBC SBC SBC 3 DIR 2 DIR 2 REL 3 EXT 1 INH 1 INH 1 INH 1 INH 1 INH 2 REL 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 03 5 13 5 23 3 33 5 43 1 53 1 63 5 73 4 83 11 93 3 A3 2 B3 3 C3 4 D3 4 E3 3 F3 3 BRCLR1 BCLR1 BLS COM COMA COMX COM COM SWI BLE CPX CPX CPX CPX CPX CPX 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 REL 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 04 5 14 5 24 3 34 5 44 1 54 1 64 5 74 4 84 1 94 2 A4 2 B4 3 C4 4 D4 4 E4 3 F4 3 BRSET2 BSET2 BCC LSR LSRA LSRX LSR LSR TAP TXS AND AND AND AND AND AND 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 05 5 15 5 25 3 35 4 45 3 55 4 65 3 75 5 85 1 95 2 A5 2 B5 3 C5 4 D5 4 E5 3 F5 3 BRCLR2 BCLR2 BCS STHX LDHX LDHX CPHX CPHX TPA TSX BIT BIT BIT BIT BIT BIT 3 DIR 2 DIR 2 REL 2 DIR 3 IMM 2 DIR 3 IMM 2 DIR 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 06 5 16 5 26 3 36 5 46 1 56 1 66 5 76 4 86 3 96 5 A6 2 B6 3 C6 4 D6 4 E6 3 F6 3 BRSET3 BSET3 BNE ROR RORA RORX ROR ROR PULA STHX LDA LDA LDA LDA LDA LDA 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 3 EXT 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 07 5 17 5 27 3 37 5 47 1 57 1 67 5 77 4 87 2 97 1 A7 2 B7 3 C7 4 D7 4 E7 3 F7 2 BRCLR3 BCLR3 BEQ ASR ASRA ASRX ASR ASR PSHA TAX AIS STA STA STA STA STA 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 08 5 18 5 28 3 38 5 48 1 58 1 68 5 78 4 88 3 98 1 A8 2 B8 3 C8 4 D8 4 E8 3 F8 3 BRSET4 BSET4 BHCC LSL LSLA LSLX LSL LSL PULX CLC EOR EOR EOR EOR EOR EOR 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 09 5 19 5 29 3 39 5 49 1 59 1 69 5 79 4 89 2 99 1 A9 2 B9 3 C9 4 D9 4 E9 3 F9 3 BRCLR4 BCLR4 BHCS ROL ROLA ROLX ROL ROL PSHX SEC ADC ADC ADC ADC ADC ADC 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 0A 5 1A 5 2A 3 3A 5 4A 1 5A 1 6A 5 7A 4 8A 3 9A 1 AA 2 BA 3 CA 4 DA 4 EA 3 FA 3 BRSET5 BSET5 BPL DEC DECA DECX DEC DEC PULH CLI ORA ORA ORA ORA ORA ORA 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 0B 5 1B 5 2B 3 3B 7 4B 4 5B 4 6B 7 7B 6 8B 2 9B 1 AB 2 BB 3 CB 4 DB 4 EB 3 FB 3 BRCLR5 BCLR5 BMI DBNZ DBNZA DBNZX DBNZ DBNZ PSHH SEI ADD ADD ADD ADD ADD ADD 3 DIR 2 DIR 2 REL 3 DIR 2 INH 2 INH 3 IX1 2 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 0C 5 1C 5 2C 3 3C 5 4C 1 5C 1 6C 5 7C 4 8C 1 9C 1 BC 3 CC 4 DC 4 EC 3 FC 3 BRSET6 BSET6 BMC INC INCA INCX INC INC CLRH RSP JMP JMP JMP JMP JMP 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 1 INH 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 0D 5 1D 5 2D 3 3D 4 4D 1 5D 1 6D 4 7D 3 9D 1 AD 5 BD 5 CD 6 DD 6 ED 5 FD 5 BRCLR6 BCLR6 BMS TST TSTA TSTX TST TST NOP BSR JSR JSR JSR JSR JSR 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 REL 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 0E 5 1E 5 2E 3 3E 6 4E 5 5E 5 6E 4 7E 5 8E 2+ 9E AE 2 BE 3 CE 4 DE 4 EE 3 FE 3 BRSET7 BSET7 BIL CPHX MOV MOV MOV MOV STOP Page 2 LDX LDX LDX LDX LDX LDX 3 DIR 2 DIR 2 REL 3 EXT 3 DD 2 DIX+ 3 IMD 2 IX+D 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 0F 5 1F 5 2F 3 3F 5 4F 1 5F 1 6F 5 7F 4 8F 2+ 9F 1 AF 2 BF 3 CF 4 DF 4 EF 3 FF 2 BRCLR7 BCLR7 BIH CLR CLRA CLRX CLR CLR WAIT TXA AIX STX STX STX STX STX 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX INH Inherent REL Relative SP1 Stack Pointer, 8-Bit Offset IMM Immediate IX Indexed, No Offset SP2 Stack Pointer, 16-Bit Offset DIR Direct IX1 Indexed, 8-Bit Offset IX+ Indexed, No Offset with EXT Extended IX2 Indexed, 16-Bit Offset Post Increment DD DIR to DIR IMD IMM to DIR IX1+ Indexed, 1-Byte Offset with IX+D IX+ to DIR DIX+ DIR to IX+ Post Increment Opcode in Hexadecimal F0 3 HCS08 Cycles SUB Instruction Mnemonic Number of Bytes 1 IX Addressing Mode MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 111

Chapter7 Central Processor Unit (S08CPUV2) Table7-3. Opcode Map (Sheet 2 of 2) Bit-Manipulation Branch Read-Modify-Write Control Register/Memory 9E60 6 9ED0 5 9EE0 4 NEG SUB SUB 3 SP1 4 SP2 3 SP1 9E61 6 9ED1 5 9EE1 4 CBEQ CMP CMP 4 SP1 4 SP2 3 SP1 9ED2 5 9EE2 4 SBC SBC 4 SP2 3 SP1 9E63 6 9ED3 5 9EE3 4 9EF3 6 COM CPX CPX CPHX 3 SP1 4 SP2 3 SP1 3 SP1 9E64 6 9ED4 5 9EE4 4 LSR AND AND 3 SP1 4 SP2 3 SP1 9ED5 5 9EE5 4 BIT BIT 4 SP2 3 SP1 9E66 6 9ED6 5 9EE6 4 ROR LDA LDA 3 SP1 4 SP2 3 SP1 9E67 6 9ED7 5 9EE7 4 ASR STA STA 3 SP1 4 SP2 3 SP1 9E68 6 9ED8 5 9EE8 4 LSL EOR EOR 3 SP1 4 SP2 3 SP1 9E69 6 9ED9 5 9EE9 4 ROL ADC ADC 3 SP1 4 SP2 3 SP1 9E6A 6 9EDA 5 9EEA 4 DEC ORA ORA 3 SP1 4 SP2 3 SP1 9E6B 8 9EDB 5 9EEB 4 DBNZ ADD ADD 4 SP1 4 SP2 3 SP1 9E6C 6 INC 3 SP1 9E6D 5 TST 3 SP1 9EAE 5 9EBE 6 9ECE 5 9EDE 5 9EEE 4 9EFE 5 LDHX LDHX LDHX LDX LDX LDHX 2 IX 4 IX2 3 IX1 4 SP2 3 SP1 3 SP1 9E6F 6 9EDF 5 9EEF 4 9EFF 5 CLR STX STX STHX 3 SP1 4 SP2 3 SP1 3 SP1 INH Inherent REL Relative SP1 Stack Pointer, 8-Bit Offset IMM Immediate IX Indexed, No Offset SP2 Stack Pointer, 16-Bit Offset DIR Direct IX1 Indexed, 8-Bit Offset IX+ Indexed, No Offset with EXT Extended IX2 Indexed, 16-Bit Offset Post Increment DD DIR to DIR IMD IMM to DIR IX1+ Indexed, 1-Byte Offset with IX+D IX+ to DIR DIX+ DIR to IX+ Post Increment Note: All Sheet 2 Opcodes are Preceded by the Page 2 Prebyte (9E) Prebyte (9E) and Opcode in Hexadecimal 9E60 6 HCS08 Cycles NEG Instruction Mnemonic Number of Bytes 3 SP1 Addressing Mode MC9S08SH8MCUSeriesDataSheet,Rev.3 112 Freescale Semiconductor

Chapter 8 Analog Comparator 5-V (S08ACMPV2) 8.1 Introduction Theanalogcomparatormodule(ACMP)providesacircuitforcomparingtwoanaloginputvoltagesorfor comparingoneanaloginputvoltagetoaninternalreferencevoltage.Thecomparatorcircuitisdesignedto operate across the full range of the supply voltage (rail-to-rail operation). Figure8-1 shows the MC9S08SH8 block diagram with the ACMP highlighted. 8.1.1 ACMP Configuration In ormation WhenusingthebandgapreferencevoltageforinputtoACMP+,theusermustenablethebandgapbuffer by setting BGBE =1 in SPMSC1 seeSection5.7.7, “System Power Management Status and Control 1 Register (SPMSC1)”. For value of bandgap voltage reference seeSectionA.6, “DC Characteristics”. 8.1.2 ACMP in Stop3 Mode S08ACMPV2continuestooperateinstop3modeifenabled.IfACOPEisenabled,comparatoroutputwill operate as in the normal operating mode and will control ACMPO pin. The MCU is brought out of stop when a compare event occurs and ACIE is enabled; ACF flag sets accordingly. 8.1.3 ACMP/TPM Configuration In ormation The ACMP module can be configured to connect the output of the analog comparator to TPM1 input capturechannel0bysettingACICinSOPT2.WithACICset,theTPM1CH0pinisnotavailableexternally regardless of the configuration of the TPM1 module for channel 0. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 113

Chapter8 Analog Comparator 5-V (S08ACMPV2) BKGD/MS IRQ HCS08 CORE DEBUG MODULE (DBG) CPU BDC 8-BIT MODULO TIMER TCLK HCS08 SYSTEM CONTROL MODULE (MTIM) PTA5/IRQ/TCLK/RESET PTA4/ACMPO/BKGD/MS RESETS AND INTERRUPTS A MODES OF OPERATION SCL T PTA3/PAI3/SCL/ADP3 POWER MANAGEMENT IIC MODULE (IIC) SDA POR PTA2/PAI2/SDA/ADP2 COP IRQ LVD SS PTA1/PIA1/TPM2CH0/ADP1/ACMP– PTA0/PIA0/TPM1CH0/ADP0/ACMP+ MISO SERIAL PERIPHERAL MOSI INTERFACE MODULE (SPI) USER FLASH SPSCK (MC9S08SH8 =8,192 BYTES) PTB7/SCL/EXTAL (MC9S08SH4 =4096 BYTES) PTB6/SDA/XTAL SERIAL COMMUNICATIONS RxD SEE NOTE 1 INTERFACE MODULE (SCI) TxD PTB5/TPM1CH1/SS USER RAM (MC9S08SH8 =512 BYTES) TCLK T B PTB4/TPM2CH1/MISO (MC9S08SH4 =256 BYTES) 16-BIT TIMER/PWM TPM1CH0 OR PTB3/PIB3/MOSI/ADP7 P MODULE (TPM1) TPM1CH1 PTB2/PIB2/SPSCK/ADP6 REAL-TIME COUNTER (RTC) TCLK PTB1/PIB1/TxD/ADP5 16-BIT TIMER/PWM TPM2CH0 PTB0/PIB0/RxD/ADP4 40-MHz INTERNAL CLOCK SOURCE (ICS) MODULE (TPM2) TPM2CH1 SEE NOTE 1, 2 PTC3/ADP11 LOW31-P.2O5W kHEzR t oO S38C.I4L LkHATzOR EXTAL T C PTC2/ADP10 R 1 MHz to 16 MHz XTAL O PTC1/TPM1CH1/ADP9 (XOSC) P PTC0/TPM1CH0/ADP8 ACMPO SEE NOTE3 ANALOG COMPARATOR ACMP– (ACMP) ACMP+ V DD VOLTAGE REGULATOR VSS 10-BIT ADP11-ADP0 ANALOG-TO-DIGITAL V CONVERTER (ADC) DDA V SSA VREFH NOTES V REFL = Pin can be enabled as part of the ganged output drive feature NOTE1: Port B not available on 8-pinpackages NOTE2: Port C not available on 8-pin or 16-pin packages NOTE 3: V /V and V /V , are double bonded to V and V respectively. DDA REFH SSA REFL DD SS Figure8-1.MC9S08SH8 Block Diagram Highlighting theACMP Module MC9S08SH8MCUSeriesDataSheet,Rev.3 114 Freescale Semiconductor

Chapter 8 Analog Comparator (S08ACMPV2) 8.1.4 Features The ACMP has the following features: • Full rail to rail supply operation. • Selectable interrupt on rising edge, falling edge, or either rising or falling edges of comparator output. • Option to compare to fixed internal bandgap reference voltage. • Option to allow comparator output to be visible on a pin, ACMPO. • Can operate in stop3 mode 8.1.5 Modes of Operation This section defines the ACMP operation in wait, stop and background debug modes. 8.1.5.1 ACMP in Wait Mode The ACMP continues to run in wait mode if enabled before executing the WAIT instruction. Therefore, the ACMP can be used to bring the MCU out of wait mode if the ACMP interrupt, ACIE is enabled. For lowest possible current consumption, the ACMP should be disabled by software if not required as an interrupt source during wait mode. 8.1.5.2 ACMP in Stop Modes 8.1.5.2.1 Stop3 Mode Operation The ACMP continues to operate in Stop3 mode if enabled and compare operation remains active. If ACOPEisenabled,comparatoroutputoperatesasinthenormaloperatingmodeandcomparatoroutputis placed onto the external pin. The MCU is brought out of stop when a compare event occurs and ACIE is enabled; ACF flag sets accordingly. If stop is exited with a reset, the ACMP will be put into its reset state. 8.1.5.2.2 Stop2 and Stop1 Mode Operation DuringeitherStop2andStop1mode,theACMPmodulewillbefullypowereddown.Uponwake-upfrom Stop2 or Stop1 mode, the ACMP module will be in the reset state. 8.1.5.3 ACMP in Active Background Mode When the microcontroller is in active background mode, the ACMP will continue to operate normally. 8.1.6 Block Diagram The block diagram for the Analog Comparator module is shown Figure8-2. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 115

Chapter 8 Analog Comparator (S08ACMPV2) Internal Bus Internal Reference ACMP INTERRUPT ACIE REQUEST ACBGS Status & Control ACME ACF Register ACOPE D F O C M A ACMP+ AC set + Interrupt Control - ACMP- Comparator ACMPO Figure8-2. Analog Comparator 5V (ACMP5) Block Diagram MC9S08SH8MCUSeriesDataSheet,Rev.3 116 Freescale Semiconductor

Chapter 8 Analog Comparator (S08ACMPV2) 8.2 External Signal Description TheACMPhastwoanaloginputpins,ACMP+andACMP-andonedigitaloutputpinACMPO.Eachof these pins can accept an input voltage that varies across the full operating voltage range of the MCU. As showninFigure8-2,theACMP-pinisconnectedtotheinvertinginputofthecomparator,andtheACMP+ pin is connected to the comparator non-inverting input if ACBGS is a 0. As shown in Figure8-2, the ACMPO pin can be enabled to drive an external pin. The signal properties of ACMP are shown in Table8-1. Table8-1. Signal Properties Signal Function I/O ACMP- Inverting analog input to the ACMP. I (Minus input) ACMP+ Non-inverting analog input to the ACMP. I (Positive input) ACMPO Digital output of the ACMP. O 8.3 Memory Map 8.3.1 Register Descriptions The ACMP includes one register: • An 8-bit status and control register Refertothedirect-pageregistersummaryinthememorysectionofthisdatasheetfortheabsoluteaddress assignments for all ACMP registers.This section refers to registers and control bits only by their names . SomeMCUsmayhavemorethanoneACMP,soregisternamesincludeplaceholdercharacterstoidentify which ACMP is being referenced. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 117

Chapter 8 Analog Comparator (S08ACMPV2) 8.3.1.1 ACMP Status and Control Register (ACMPSC) ACMPSC contains the status flag and control bits which are used to enable and configure the ACMP. 7 6 5 4 3 2 1 0 R ACO ACME ACBGS ACF ACIE ACOPE ACMOD W Reset: 0 0 0 0 0 0 0 0 = Unimplemented Figure8-3. ACMP Status and Control Register Table8-2. ACMP Status and Control Register Field Descriptions Field Description 7 Analog Comparator Module Enable — ACME enables the ACMP module. ACME 0 ACMP not enabled 1 ACMP is enabled 6 Analog Comparator Bandgap Select — ACBGS is used to select between the bandgap reference voltage or ACBGS the ACMP+ pin as the input to the non-inverting input of the analog comparatorr. 0 External pin ACMP+ selected as non-inverting input to comparator 1 Internal reference select as non-inverting input to comparator Note: refer to this chapter introduction to verify if any other config bits are necessary to enable the bandgap reference in the chip level. 5 AnalogComparatorFlag—ACFissetwhenacompareeventoccurs.CompareeventsaredefinedbyACMOD. ACF ACF is cleared by writing a one to ACF. 0 Compare event has not occured 1 Compare event has occured 4 Analog Comparator Interrupt Enable — ACIE enables the interrupt from the ACMP. When ACIE is set, an ACIE interupt will be asserted when ACF is set. 0 Interrupt disabled 1 Interrupt enabled 3 AnalogComparatorOutput—ReadingACOwillreturnthecurrentvalueoftheanalogcomparatoroutput.ACO ACO is reset to a 0 and will read as a 0 when the ACMP is disabled (ACME = 0). 2 AnalogComparatorOutputPinEnable—ACOPEisusedtoenablethecomparatoroutputtobeplacedonto ACOPE the external pin, ACMPO. 0 Analog comparator output not available on ACMPO 1 Analog comparator output is driven out on ACMPO 1:0 Analog Comparator Mode — ACMOD selects the type of compare event which sets ACF. ACMOD 00 Encoding 0 — Comparator output falling edge 01 Encoding 1 — Comparator output rising edge 10 Encoding 2 — Comparator output falling edge 11 Encoding 3 — Comparator output rising or falling edge MC9S08SH8MCUSeriesDataSheet,Rev.3 118 Freescale Semiconductor

Chapter 8 Analog Comparator (S08ACMPV2) 8.4 Functional Description TheanalogcomparatorcanbeusedtocomparetwoanaloginputvoltagesappliedtoACMP+andACMP-; oritcanbeusedtocompareananaloginputvoltageappliedtoACMP-withaninternalbandgapreference voltage. ACBGS is used to select between the bandgap reference voltage or the ACMP+ pin as the input tothenon-invertinginputoftheanalogcomparator.Thecomparatoroutputishighwhenthenon-inverting inputisgreaterthantheinvertinginput,andislowwhenthenon-invertinginputislessthantheinverting input.ACMODisusedtoselecttheconditionwhichwillcauseACFtobeset.ACFcanbesetonarising edgeofthecomparatoroutput,afallingedgeofthecomparatoroutput,oreitherarisingorafallingedge (toggle).ThecomparatoroutputcanbereaddirectlythroughACO.Thecomparatoroutputcanbedriven onto the ACMPO pin using ACOPE. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 119

Chapter 8 Analog Comparator (S08ACMPV2) MC9S08SH8MCUSeriesDataSheet,Rev.3 120 Freescale Semiconductor

Chapter 9 Analog-to-Digital Converter (S08ADCV1) 9.1 Introduction The10-bitanalog-to-digitalconverter(ADC)isasuccessiveapproximationADCdesignedforoperation within an integrated microcontroller system-on-chip. NOTE The MC9S08SH8 Family of devices do not include stop1 mode. TheADCchannelassignments,alternateclockfunction,andhardwaretriggerfunctionareconfiguredas described below for the MC9S08SH8 family of devices. 9.1.1 Channel Assignments The ADC channel assignments for the MC9S08SH8 devices are shown in Table9-1. Reserved channels convert to an unknown value. Table9-1. ADC Channel Assignment ADCH Channel Input ADCH Channel Input 00000 AD0 PTA0/ADP0 10000 AD16 V SS 00001 AD1 PTA1/ADP1 10001 AD17 V SS 00010 AD2 PTA2/ADP2 10010 AD18 V SS 00011 AD3 PTA3/ADP3 10011 AD19 V SS 00100 AD4 PTB0/ADP4 10100 AD20 V SS 00101 AD5 PTB1/ADP5 10101 AD21 Reserved 00110 AD6 PTB2/ADP6 10110 AD22 Reserved 00111 AD7 PTB3/ADP7 10111 AD23 Reserved 01000 AD8 PTC0/ADP8 11000 AD24 Reserved 01001 AD9 PTC1/ADP9 11001 AD25 Reserved 01010 AD10 PTC2/ADP10 11010 AD26 Temperature Sensor1 01011 AD11 PTC3/ADP11 11011 AD27 Internal Bandgap2 01100 AD12 V 11100 - Reserved SS 01101 AD13 V 11101 V V SS REFH DD 01110 AD14 V 11110 V V SS REFL SS 01111 AD15 V 11111 ModuleDisabled None SS 1 For information, seeSection9.1.4, “Temperature Sensor”. 2 Requires BGBE =1 in SPMSC1 seeSection5.7.8, “System Power Management Status and Control 2 Register (SPMSC2)”. For value of bandgap voltage reference seeSectionA.6, “DC Characteristics”. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 121

Chapter9 Analog-to-Digital Converter (S08ADCV1) 9.1.2 Alternate Clock The ADC module is capable of performing conversions using the MCU bus clock, the bus clock divided bytwo,thelocalasynchronousclock(ADACK)withinthemodule,orthealternateclock,ALTCLK.The alternate clock for the MC9S08SH8 MCU devices is the external reference clock (ICSERCLK). TheselectedclocksourcemustrunatafrequencysuchthattheADCconversionclock(ADCK)runsata frequency within its specified range (f ) after being divided down from the ALTCLK input as ADCK determined by the ADIV bits. ALTCLKisactivewhiletheMCUisinwaitmodeprovidedtheconditionsdescribedabovearemet.This allows ALTCLK to be used as the conversion clock source for the ADC while the MCU is in wait mode. ALTCLK cannot be used as the ADC conversion clock source while the MCU is in either stop2 or stop3. 9.1.3 Hardware Trigger The ADC hardware trigger, ADHWT, is the output from the real time counter (RTC). The RTC counter can be clocked by either ICSERCLK, ICSIRCLK or a nominal 1 kHz clock source. The period of the RTC is determined by the input clock frequency, the RTCPS bits, and the RTCMOD register. When the ADC hardware trigger is enabled, a conversion is initiated upon an RTC counter overflow. The RTIE does not have to be set for RTC to cause a hardware trigger. The RTC can be configured to cause a hardware trigger in MCU run, wait, and stop3. 9.1.4 Temperature Sensor To use the on-chip temperature sensor, the user must perform the following: • Configure ADC for long sample with a maximum of 1 MHz clock • Convert the bandgap voltage reference channel (AD27) — By converting the digital value of the bandgap voltage reference channel using the value of V the user can determine V . For value of bandgap voltage, seeSectionA.6, “DC BG DD Characteristics”. • Convert the temperature sensor channel (AD26) — By using the calculated value of V , convert the digital value of AD26 into a voltage, V DD TEMP Equation9-1providesanapproximatetransferfunctionoftheon-chiptemperaturesensorforV =5.0V, DD Temp = 25°C, using the ADC1 at f = 1.0MHz and configured for long sample. ADCK Temp = 25 - ( (V -V ) /m) Eqn.9-1 C TEMP TEMP25 where: — V is the voltage of the temperature sensor channel at the ambient temperature. TEMP — V is the voltage of the temperature sensor channel at 25°C. TEMP25 — m is the hot or cold voltage versus temperature slope in V/°C. For temperature calculations, use the V and m values in the data sheet. TEMP25 MC9S08SH8MCUSeriesDataSheet,Rev.3 122 Freescale Semiconductor

Chapter9 Analog-to-Digital Converter (S08ADCV1) In application code, the user reads the temperature sensor channel, calculates V , and compares it to TEMP V . If V is greater than V the cold slope value is applied inEquation9-1. If V is TEMP25 TEMP TEMP25 TEMP less than V the hot slope value is applied in Equation9-1. TEMP25 Calibrating at 25°C will improve accuracy to ±4.5°C. Calibration at three points, -40°C, 25°C, and 125°C will improve accuracy to ±2.5°C. Once calibration hasbeencompleted,theuserwillneedtocalculatetheslopeforbothhotandcold.Inapplicationcode,the userwouldthencalculatethetemperatureusingEquation9-1asdetailedaboveandthendetermineifthe temperatureisaboveorbelow25°C.Oncedeterminedifthetemperatureisaboveorbelow25°C,theuser can recalculate the temperature using the hot or cold slope value obtained during calibration. Figure9-1 shows the MC9S08SH8 with the ADC module highlighted. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 123

Chapter9 Analog-to-Digital Converter (S08ADCV1) BKGD/MS IRQ HCS08 CORE DEBUG MODULE (DBG) CPU BDC 8-BIT MODULO TIMER TCLK HCS08 SYSTEM CONTROL MODULE (MTIM) PTA5/IRQ/TCLK/RESET PTA4/ACMPO/BKGD/MS RESETS AND INTERRUPTS A MODES OF OPERATION SCL T PTA3/PAI3/SCL/ADP3 POWER MANAGEMENT IIC MODULE (IIC) SDA POR PTA2/PAI2/SDA/ADP2 COP IRQ LVD SS PTA1/PIA1/TPM2CH0/ADP1/ACMP– PTA0/PIA0/TPM1CH0/ADP0/ACMP+ MISO SERIAL PERIPHERAL MOSI USER FLASH INTERFACE MODULE (SPI) SPSCK (MC9S08SH8 =8,192 BYTES) PTB7/SCL/EXTAL (MC9S08SH4 =4096 BYTES) PTB6/SDA/XTAL SERIAL COMMUNICATIONS RxD SEE NOTE 1 INTERFACE MODULE (SCI) TxD PTB5/TPM1CH1/SS USER RAM (MC9S08SH8 =512 BYTES) TCLK T B PTB4/TPM2CH1/MISO (MC9S08SH4 =256 BYTES) 16-BIT TIMER/PWM TPM1CH0 OR PTB3/PIB3/MOSI/ADP7 P MODULE (TPM1) TPM1CH1 PTB2/PIB2/SPSCK/ADP6 REAL-TIME COUNTER (RTC) TCLK PTB1/PIB1/TxD/ADP5 16-BIT TIMER/PWM TPM2CH0 PTB0/PIB0/RxD/ADP4 40-MHz INTERNAL CLOCK SOURCE (ICS) MODULE (TPM2) TPM2CH1 SEE NOTE 1, 2 PTC3/ADP11 LOW-POWER OSCILLATOR EXTAL C 31.25 kHz to 38.4 kHz T PTC2/ADP10 R 1 MHz to 16 MHz XTAL O PTC1/TPM1CH1/ADP9 (XOSC) P PTC0/TPM1CH0/ADP8 ACMPO SEE NOTE3 ANALOG COMPARATOR ACMP– (ACMP) ACMP+ V DD VOLTAGE REGULATOR VSS 10-BIT ADP11-ADP0 ANALOG-TO-DIGITAL V CONVERTER (ADC) DDA V SSA VREFH NOTES V REFL = Pin can be enabled as part of the ganged output drive feature NOTE1: Port B not available on 8-pinpackages NOTE2: Port C not available on 8-pin or 16-pin packages NOTE 3: V /V and V /V , are double bonded to V and V respectively. DDA REFH SSA REFL DD SS Figure9-1.MC9S08SH8 Block Diagram Highlighting theADC Module MC9S08SH8MCUSeriesDataSheet,Rev.3 124 Freescale Semiconductor

Chapter 9 Analog-to-Digital Converter (S08ADC10V1) 9.1.5 Features Features of the ADC module include: • Linearsuccessive approximation algorithm with 10bits resolution. • Up to 28 analog inputs. • Output formatted in 10- or 8-bit right-justified format. • Singleor continuous conversion (automatic return to idle after single conversion). • Configurable sample time and conversion speed/power. • Conversion complete flag and interrupt. • Inputclock selectable from up to four sources. • Operation in wait or stop3 modes for lower noise operation. • Asynchronous clock source for lower noise operation. • Selectable asynchronous hardware conversion trigger. • Automaticcomparewithinterruptforless-than,orgreater-thanorequal-to,programmablevalue. 9.1.6 Block Diagram Figure9-2 provides a block diagram of the ADC module MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 125

Chapter 9 Analog-to-Digital Converter (S08ADC10V1) 3 Compare true ADCSC1 ADCCFG O N C ADCH AIE1 CO2 ADCO complete ADTRG MODE ADLSMP ADLPC ADIV ADICLK CloAcsky Gncen ADACK Bus Clock MCU STOP ADCK Clock ADHWT Control Sequencer Divide ÷2 AD0 initialize sample convert transfer abort ALTCLK • AIEN 1 Interrupt • • ADVIN COCO 2 SAR Converter AD27 V REFH Data Registers V REFL m u S Compare true 3 Compare Logic Value CFGT A Compare Value Registers ADCSC2 Figure9-2. ADC Block Diagram 9.2 External Signal Description TheADCmodulesupportsupto28separateanaloginputs.Italsorequiresfoursupply/reference/ground connections. Table9-2. Signal Properties Name Function AD27–AD0 Analog Channel inputs V High reference voltage REFH V Low reference voltage REFL V Analog power supply DDAD V Analog ground SSAD MC9S08SH8MCUSeriesDataSheet,Rev.3 126 Freescale Semiconductor

Chapter 9 Analog-to-Digital Converter (S08ADC10V1) 9.2.1 Analog Power (V ) DDAD The ADC analog portion usesV as its power connection. In some packages, V is connected DDAD DDAD internally to V . If externally available, connect the V pin to the same voltage potential as V . DD DDAD DD External filtering may be necessary to ensure cleanV for good results. DDAD 9.2.2 Analog Ground (V ) SSAD The ADC analog portion usesV as its ground connection. In some packages, V is connected SSAD SSAD internally to V . If externally available, connect theV pin to the same voltage potential as V . SS SSAD SS 9.2.3 Voltage Reference High (V ) REFH V isthehighreferencevoltagefortheconverter.Insomepackages,V isconnectedinternallyto REFH REFH V . If externally available, V may be connected to the same potential as V , or may be DDAD REFH DDAD drivenbyanexternalsourcethatisbetweentheminimumV specandtheV potential(V DDAD DDAD REFH must never exceed V ). DDAD 9.2.4 Voltage Reference Low (V ) REFL V isthelowreferencevoltagefortheconverter.Insomepackages,V isconnectedinternallyto REFL REFL V .If externally available, connect the V pin to the same voltage potential asV . SSAD REFL SSAD 9.2.5 Analog Channel Inputs (ADx) TheADCmodulesupportsupto28separateanaloginputs.Aninputisselectedforconversionthroughthe ADCH channel select bits. 9.3 Register Definitio These memory mapped registers control and monitor operation of the ADC: • Status and control register, ADCSC1 • Status and control register, ADCSC2 • Data result registers, ADCRH and ADCRL • Compare value registers, ADCCVH and ADCCVL • Configuration register, ADCCFG • Pin enable registers, APCTL1, APCTL2, APCTL3 9.3.1 Status and Control Register 1 (ADCSC1) ThissectiondescribesthefunctionoftheADCstatusandcontrolregister(ADCSC1).WritingADCSC1 aborts the current conversion and initiates a new conversion (if the ADCH bits are equal to a value other than all 1s). MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 127

Chapter 9 Analog-to-Digital Converter (S08ADC10V1) 7 6 5 4 3 2 1 0 R COCO AIEN ADCO ADCH W Reset: 0 0 0 1 1 1 1 1 = Unimplemented or Reserved Figure9-3. Status and Control Register (ADCSC1) Table9-3. ADCSC1 Register Field Descriptions Field Description 7 Conversion Complete Flag — The COCO flag is a read-only bit which is set each time a conversion is COCO completedwhenthecomparefunctionisdisabled(ACFE=0).Whenthecomparefunctionisenabled(ACFE= 1) the COCO flag is set upon completion of a conversion only if the compare result is true. This bit is cleared whenever ADCSC1 is written or whenever ADCRL is read. 0 Conversion not completed 1 Conversion completed 6 Interrupt Enable — AIEN is used to enable conversion complete interrupts. When COCO becomes set while AIEN AIEN is high, an interrupt is asserted. 0 Conversion complete interrupt disabled 1 Conversion complete interrupt enabled 5 Continuous Conversion Enable — ADCO is used to enable continuous conversions. ADCO 0 One conversion following a write to the ADCSC1 when software triggered operation is selected, or one conversion following assertion of ADHWT when hardware triggered operation is selected. 1 ContinuousconversionsinitiatedfollowingawritetoADCSC1whensoftwaretriggeredoperationisselected. Continuous conversions are initiated by an ADHWT event when hardware triggered operation is selected. 4:0 InputChannelSelect—TheADCHbitsforma5-bitfieldwhichisusedtoselectoneoftheinputchannels.The ADCH input channels are detailed inFigure9-4. The successive approximation converter subsystem is turned off when the channel select bits are all set to 1. This feature allows for explicit disabling of the ADC and isolation of the input channel from all sources. Terminatingcontinuousconversionsthiswaywillpreventanadditional,singleconversionfrombeingperformed. Itisnotnecessarytosetthechannelselectbitstoall1stoplacetheADCinalow-powerstatewhencontinuous conversions are not enabled because the module automatically enters a low-power state when a conversion completes. Figure9-4. Input Channel Select ADCH Input Select ADCH Input Select 00000 AD0 10000 AD16 00001 AD1 10001 AD17 00010 AD2 10010 AD18 00011 AD3 10011 AD19 00100 AD4 10100 AD20 00101 AD5 10101 AD21 00110 AD6 10110 AD22 00111 AD7 10111 AD23 MC9S08SH8MCUSeriesDataSheet,Rev.3 128 Freescale Semiconductor

Chapter 9 Analog-to-Digital Converter (S08ADC10V1) Figure9-4. Input Channel Select (continued) ADCH Input Select ADCH Input Select 01000 AD8 11000 AD24 01001 AD9 11001 AD25 01010 AD10 11010 AD26 01011 AD11 11011 AD27 01100 AD12 11100 Reserved 01101 AD13 11101 V REFH 01110 AD14 11110 V REFL 01111 AD15 11111 Module disabled 9.3.2 Status and Control Register 2 (ADCSC2) TheADCSC2registerisusedtocontrolthecomparefunction,conversiontriggerandconversionactiveof the ADC module. 7 6 5 4 3 2 1 0 R ADACT 0 0 ADTRG ACFE ACFGT R1 R1 W Reset: 0 0 0 0 0 0 0 0 = Unimplemented or Reserved 1 Bits 1 and 0 are reserved bits that must always be written to 0. Figure9-5.Status and Control Register 2 (ADCSC2) Table9-4. ADCSC2 Register Field Descriptions Field Description 7 Conversion Active — ADACT indicates that a conversion is in progress. ADACT is set when a conversion is ADACT initiated and cleared when a conversion is completed or aborted. 0 Conversion not in progress 1 Conversion in progress 6 ConversionTriggerSelect—ADTRGisusedtoselectthetypeoftriggertobeusedforinitiatingaconversion. ADTRG Two types of trigger are selectable: software trigger and hardware trigger. When software trigger is selected, a conversionisinitiatedfollowingawritetoADCSC1.Whenhardwaretriggerisselected,aconversionisinitiated following the assertion of the ADHWT input. 0 Software trigger selected 1 Hardware trigger selected MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 129

Chapter 9 Analog-to-Digital Converter (S08ADC10V1) Table9-4. ADCSC2 Register Field Descriptions (continued) Field Description 5 Compare Function Enable — ACFE is used to enable the compare function. ACFE 0 Compare function disabled 1 Compare function enabled 4 CompareFunctionGreaterThanEnable—ACFGTisusedtoconfigurethecomparefunctiontotriggerwhen ACFGT the result of the conversion of the input being monitored is greater than or equal to the compare value. The comparefunctiondefaultstotriggeringwhentheresultofthecompareoftheinputbeingmonitoredislessthan the compare value. 0 Compare triggers when input is less than compare level 1 Compare triggers when input is greater than or equal to compare level 9.3.3 Data Result High Register (ADCRH) ADCRH contains the upper two bits of the result of a 10-bit conversion. When configured for 8-bit conversions both ADR8 and ADR9 are equal to zero. ADCRH is updated each time a conversion completes except when automatic compare is enabled and the compare condition is not met. In 10-bit MODE,readingADCRHpreventstheADCfromtransferringsubsequentconversionresultsintotheresult registersuntilADCRLisread.IfADCRLisnotreaduntilafterthenextconversioniscompleted,thenthe intermediateconversionresultwillbelost.In8-bitmodethereisnointerlockingwithADCRL.Inthecase that the MODE bits are changed, any data in ADCRH becomes invalid. 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 ADR9 ADR8 W Reset: 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure9-6. Data Result High Register (ADCRH) 9.3.4 Data Result Low Register (ADCRL) ADCRL contains the lower eight bits of the result of a 10-bit conversion, and all eight bits of an 8-bit conversion.Thisregisterisupdatedeachtimeaconversioncompletesexceptwhenautomaticcompareis enabled and the compare condition is not met. In 10-bit mode, reading ADCRH prevents the ADC from transferringsubsequentconversionresultsintotheresultregistersuntilADCRLisread.IfADCRLisnot read until the after next conversion is completed, then the intermediate conversion results will be lost. In 8-bit mode, there is no interlocking with ADCRH. In the case that the MODE bits are changed, any data in ADCRL becomes invalid. MC9S08SH8MCUSeriesDataSheet,Rev.3 130 Freescale Semiconductor

Chapter 9 Analog-to-Digital Converter (S08ADC10V1) 7 6 5 4 3 2 1 0 R ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 W Reset: 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure9-7. Data Result Low Register (ADCRL) 9.3.5 Compare Value High Register (ADCCVH) This register holds the upper two bits of the 10-bit compare value. These bits are compared to the upper twobitsoftheresultfollowingaconversionin10-bitmodewhenthecomparefunctionisenabled.In8-bit operation, ADCCVH is not used during compare. 7 6 5 4 3 2 1 0 R 0 0 0 0 ADCV9 ADCV8 W Reset: 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure9-8. Compare Value High Register (ADCCVH) 9.3.6 Compare Value Low Register (ADCCVL) This register holds the lower 8 bits of the 10-bit compare value, or all 8 bits of the 8-bit compare value. BitsADCV7:ADCV0arecomparedtothelower8bitsoftheresultfollowingaconversionineither10-bit or 8-bit mode. 7 6 5 4 3 2 1 0 R ADCV7 ADCV6 ADCV5 ADCV4 ADCV3 ADCV2 ADCV1 ADCV0 W Reset: 0 0 0 0 0 0 0 0 Figure9-9. Compare Value Low Register(ADCCVL) 9.3.7 Configuration Register (ADCCFG ADCCFGisusedtoselectthemodeofoperation,clocksource,clockdivide,andconfigureforlowpower or long sample time. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 131

Chapter 9 Analog-to-Digital Converter (S08ADC10V1) 7 6 5 4 3 2 1 0 R ADLPC ADIV ADLSMP MODE ADICLK W Reset: 0 0 0 0 0 0 0 0 Figure9-10. Configuration Register (ADCCFG Table9-5. ADCCFG Register Field Descriptions Field Description 7 Low Power Configuratio — ADLPC controls the speed and power configuration of the successive ADLPC approximationconverter.Thisisusedtooptimizepowerconsumptionwhenhighersampleratesarenotrequired. 0 High speed configuration 1 Low power configuration: {FC31}The power is reduced at the expense of maximum clock speed. 6:5 Clock Divide Select — ADIV select the divide ratio used by the ADC to generate the internal clock ADCK. ADIV Table9-6 shows the available clock configurations. 4 LongSampleTimeConfiguratio —ADLSMPselectsbetweenlongandshortsampletime.Thisadjuststhe ADLSMP sampleperiodtoallowhigherimpedanceinputstobeaccuratelysampledortomaximizeconversionspeedfor lower impedance inputs. Longer sample times can also be used to lower overall power consumption when continuous conversions are enabled if high conversion rates are not required. 0 Short sample time 1 Long sample time 3:2 Conversion Mode Selection — MODE bits are used to select between 10- or 8-bit operation. SeeTable9-7. MODE 1:0 Input Clock Select — ADICLK bits select the input clock source to generate the internal clock ADCK. See ADICLK Table9-8. Table9-6. Clock Divide Select ADIV Divide Ratio Clock Rate 00 1 Input clock 01 2 Input clock÷2 10 4 Input clock÷4 11 8 Input clock÷8 Table9-7. Conversion Modes MODE Mode Description 00 8-bit conversion (N=8) 01 Reserved 10 10-bit conversion (N=10) 11 Reserved MC9S08SH8MCUSeriesDataSheet,Rev.3 132 Freescale Semiconductor

Chapter 9 Analog-to-Digital Converter (S08ADC10V1) Table9-8. Input Clock Select ADICLK Selected Clock Source 00 Bus clock 01 Bus clock divided by 2 10 Alternate clock (ALTCLK) 11 Asynchronous clock (ADACK) 9.3.8 Pin Control 1 Register (APCTL1) The pin control registers are used to disable the I/O port control of MCU pins used as analog inputs. APCTL1 is used to control the pins associated with channels 0–7 of the ADC module. 7 6 5 4 3 2 1 0 R ADPC7 ADPC6 ADPC5 ADPC4 ADPC3 ADPC2 ADPC1 ADPC0 W Reset: 0 0 0 0 0 0 0 0 Figure9-11. Pin Control 1 Register (APCTL1) Table9-9. APCTL1 Register Field Descriptions Field Description 7 ADC Pin Control 7 — ADPC7 is used to control the pin associated with channel AD7. ADPC7 0 AD7 pin I/O control enabled 1 AD7 pin I/O control disabled 6 ADC Pin Control 6 — ADPC6 is used to control the pin associated with channel AD6. ADPC6 0 AD6 pin I/O control enabled 1 AD6 pin I/O control disabled 5 ADC Pin Control 5 — ADPC5 is used to control the pin associated with channel AD5. ADPC5 0 AD5 pin I/O control enabled 1 AD5 pin I/O control disabled 4 ADC Pin Control 4 — ADPC4 is used to control the pin associated with channel AD4. ADPC4 0 AD4 pin I/O control enabled 1 AD4 pin I/O control disabled 3 ADC Pin Control 3 — ADPC3 is used to control the pin associated with channel AD3. ADPC3 0 AD3 pin I/O control enabled 1 AD3 pin I/O control disabled 2 ADC Pin Control 2 — ADPC2 is used to control the pin associated with channel AD2. ADPC2 0 AD2 pin I/O control enabled 1 AD2 pin I/O control disabled MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 133

Chapter 9 Analog-to-Digital Converter (S08ADC10V1) Table9-9. APCTL1 Register Field Descriptions (continued) Field Description 1 ADC Pin Control 1 — ADPC1 is used to control the pin associated with channel AD1. ADPC1 0 AD1 pin I/O control enabled 1 AD1 pin I/O control disabled 0 ADC Pin Control 0 — ADPC0 is used to control the pin associated with channel AD0. ADPC0 0 AD0 pin I/O control enabled 1 AD0 pin I/O control disabled 9.3.9 Pin Control 2 Register (APCTL2) APCTL2 is used to control channels 8–15 of the ADC module. 7 6 5 4 3 2 1 0 R ADPC15 ADPC14 ADPC13 ADPC12 ADPC11 ADPC10 ADPC9 ADPC8 W Reset: 0 0 0 0 0 0 0 0 Figure9-12. Pin Control 2 Register (APCTL2) Table9-10. APCTL2 Register Field Descriptions Field Description 7 ADC Pin Control 15 — ADPC15 is used to control the pin associated with channel AD15. ADPC15 0 AD15 pin I/O control enabled 1 AD15 pin I/O control disabled 6 ADC Pin Control 14 — ADPC14 is used to control the pin associated with channel AD14. ADPC14 0 AD14 pin I/O control enabled 1 AD14 pin I/O control disabled 5 ADC Pin Control 13 — ADPC13 is used to control the pin associated with channel AD13. ADPC13 0 AD13 pin I/O control enabled 1 AD13 pin I/O control disabled 4 ADC Pin Control 12 — ADPC12 is used to control the pin associated with channel AD12. ADPC12 0 AD12 pin I/O control enabled 1 AD12 pin I/O control disabled 3 ADC Pin Control 11 — ADPC11 is used to control the pin associated with channel AD11. ADPC11 0 AD11 pin I/O control enabled 1 AD11 pin I/O control disabled 2 ADC Pin Control 10 — ADPC10 is used to control the pin associated with channel AD10. ADPC10 0 AD10 pin I/O control enabled 1 AD10 pin I/O control disabled MC9S08SH8MCUSeriesDataSheet,Rev.3 134 Freescale Semiconductor

Chapter 9 Analog-to-Digital Converter (S08ADC10V1) Table9-10. APCTL2 Register Field Descriptions (continued) Field Description 1 ADC Pin Control 9 — ADPC9 is used to control the pin associated with channel AD9. ADPC9 0 AD9 pin I/O control enabled 1 AD9 pin I/O control disabled 0 ADC Pin Control 8— ADPC8 is used to control the pin associated with channel AD8. ADPC8 0 AD8 pin I/O control enabled 1 AD8 pin I/O control disabled 9.3.10 Pin Control 3 Register (APCTL3) APCTL3 is used to control channels 16–23 of the ADC module. 7 6 5 4 3 2 1 0 R ADPC23 ADPC22 ADPC21 ADPC20 ADPC19 ADPC18 ADPC17 ADPC16 W Reset: 0 0 0 0 0 0 0 0 Figure9-13. Pin Control 3 Register (APCTL3) Table9-11. APCTL3 Register Field Descriptions Field Description 7 ADC Pin Control 23 — ADPC23 is used to control the pin associated with channel AD23. ADPC23 0 AD23 pin I/O control enabled 1 AD23 pin I/O control disabled 6 ADC Pin Control 22 — ADPC22 is used to control the pin associated with channel AD22. ADPC22 0 AD22 pin I/O control enabled 1 AD22 pin I/O control disabled 5 ADC Pin Control 21 — ADPC21 is used to control the pin associated with channel AD21. ADPC21 0 AD21 pin I/O control enabled 1 AD21 pin I/O control disabled 4 ADC Pin Control 20 — ADPC20 is used to control the pin associated with channel AD20. ADPC20 0 AD20 pin I/O control enabled 1 AD20 pin I/O control disabled 3 ADC Pin Control 19 — ADPC19 is used to control the pin associated with channel AD19. ADPC19 0 AD19 pin I/O control enabled 1 AD19 pin I/O control disabled 2 ADC Pin Control 18 — ADPC18 is used to control the pin associated with channel AD18. ADPC18 0 AD18 pin I/O control enabled 1 AD18 pin I/O control disabled MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 135

Chapter 9 Analog-to-Digital Converter (S08ADC10V1) Table9-11. APCTL3 Register Field Descriptions (continued) Field Description 1 ADC Pin Control 17 — ADPC17 is used to control the pin associated with channel AD17. ADPC17 0 AD17 pin I/O control enabled 1 AD17 pin I/O control disabled 0 ADC Pin Control 16 — ADPC16 is used to control the pin associated with channel AD16. ADPC16 0 AD16 pin I/O control enabled 1 AD16 pin I/O control disabled 9.4 Functional Description TheADCmoduleisdisabledduringresetorwhentheADCHbitsareallhigh.Themoduleisidlewhena conversion has completed and another conversion has not been initiated. When idle, the module is in its lowest power state. The ADC can perform an analog-to-digital conversion on any of the software selectable channels. The selectedchannelvoltageisconvertedbyasuccessiveapproximationalgorithmintoan11-bitdigitalresult. In 8-bit mode, the selected channel voltage is converted by a successive approximation algorithm into a 9-bit digital result. When the conversion is completed, the result is placed in the data registers (ADCRH and ADCRL).In 10-bitmode,theresultisroundedto10bitsandplacedinADCRHandADCRL.In8-bitmode,theresult is rounded to 8 bits and placed in ADCRL. The conversion complete flag (COCO) is then set and an interrupt is generated if the conversion complete interrupt has been enabled (AIEN = 1). The ADC module has the capability of automatically comparing the result of a conversion with the contents of its compare registers. The compare function is enabled by setting the ACFE bit and operates in conjunction with any of the conversion modes and configurations. 9.4.1 Clock Select and Divide Control One of four clock sources can be selected as the clock source for the ADC module. This clock source is then divided by a configurable value to generate the input clock to the converter (ADCK). The clock is selected from one of the following sources by means of the ADICLK bits. • The bus clock, which is equal to the frequency at which software is executed. This is the default selection following reset. • Thebusclockdividedby2.Forhigherbusclockrates,thisallowsamaximumdivideby16ofthe bus clock. • ALTCLK, as defined for this MCU (See module section introduction). • Theasynchronousclock(ADACK)–ThisclockisgeneratedfromaclocksourcewithintheADC module.WhenselectedastheclocksourcethisclockremainsactivewhiletheMCUisinwaitor stop3 mode and allows conversions in these modes for lower noise operation. Whicheverclockisselected,itsfrequencymustfallwithinthespecifiedfrequencyrangeforADCK.Ifthe availableclocksaretooslow,theADCwillnotperformaccordingtospecifications.Iftheavailableclocks MC9S08SH8MCUSeriesDataSheet,Rev.3 136 Freescale Semiconductor

Chapter 9 Analog-to-Digital Converter (S08ADC10V1) are too fast, then the clock must be divided to the appropriate frequency. This divider is specified by the ADIV bits and can be divide-by 1, 2, 4, or 8. 9.4.2 Input Select and Pin Control Thepincontrolregisters(APCTL3,APCTL2,andAPCTL1)areusedtodisabletheI/Oportcontrolofthe pinsusedasanaloginputs.Whenapincontrolregisterbitisset,thefollowingconditionsareforcedforthe associated MCU pin: • The output buffer is forced to its high impedance state. • The input buffer is disabled. A read of the I/O port returns a zero for any pin with its input buffer disabled. • The pullup is disabled. 9.4.3 Hardware Trigger The ADC module has a selectable asynchronous hardware conversion trigger, ADHWT, that is enabled whentheADTRGbitisset.ThissourceisnotavailableonallMCUs.Consultthemoduleintroductionfor information on the ADHWT source specific to this MCU. WhenADHWTsourceisavailableandhardwaretriggerisenabled(ADTRG=1),aconversionisinitiated ontherisingedgeofADHWT.Ifaconversionisinprogresswhenarisingedgeoccurs,therisingedgeis ignored.Incontinuousconvertconfiguration,onlytheinitialrisingedgetolaunchcontinuousconversions isobserved.Thehardwaretriggerfunctionoperatesinconjunctionwithanyoftheconversionmodesand configurations. 9.4.4 Conversion Control Conversions can be performed in either 10-bit mode or 8-bit mode as determined by the MODE bits. Conversionscanbeinitiatedbyeitherasoftwareorhardwaretrigger.Inaddition,theADCmodulecanbe configuredforlowpoweroperation,longsampletime,continuousconversion,andautomaticcompareof the conversion result to a software determined compare value. 9.4.4.1 Initiating Conversions A conversion is initiated: • Following a write to ADCSC1 (with ADCH bits not all 1s) if software triggered operation is selected. • Following a hardware trigger (ADHWT) event if hardware triggered operation is selected. • Following the transfer of the result to the data registers when continuous conversion is enabled. Ifcontinuousconversionsareenabledanewconversionisautomaticallyinitiatedafterthecompletionof the current conversion. In software triggered operation, continuous conversions begin after ADCSC1 is writtenandcontinueuntilaborted.Inhardwaretriggeredoperation,continuousconversionsbeginaftera hardware trigger event and continue until aborted. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 137

Chapter 9 Analog-to-Digital Converter (S08ADC10V1) 9.4.4.2 Completing Conversions A conversion is completed when the result of the conversion is transferred into the data result registers, ADCRHandADCRL.ThisisindicatedbythesettingofCOCO.AninterruptisgeneratedifAIENishigh at the time that COCO is set. A blocking mechanism prevents a new result from overwriting previous data in ADCRH and ADCRL if thepreviousdataisintheprocessofbeingreadwhilein10-bitMODE(theADCRHregisterhasbeenread buttheADCRLregisterhasnot).Whenblockingisactive,thedatatransferisblocked,COCOisnotset, and the new result is lost. In the case of single conversions with the compare function enabled and the compare condition false, blocking has no effect and ADC operation is terminated. In all other cases of operation,whenadatatransferisblocked,anotherconversionisinitiatedregardlessofthestateofADCO (single or continuous conversions enabled). If single conversions are enabled, the blocking mechanism could result in several discarded conversions and excess power consumption. To avoid this issue, the data registers must not be read after initiating a single conversion until the conversion completes. 9.4.4.3 Aborting Conversions Any conversion in progress will be aborted when: • A write to ADCSC1 occurs (the current conversion will be aborted and a new conversion will be initiated, if ADCH are not all 1s). • A write to ADCSC2, ADCCFG, ADCCVH, or ADCCVL occurs. This indicates a mode of operation change has occurred and the current conversion is therefore invalid. • The MCU is reset. • The MCU enters stop mode with ADACK not enabled. Whenaconversionisaborted,thecontentsofthedataregisters,ADCRHandADCRL,arenotalteredbut continuetobethevaluestransferredafterthecompletionofthelastsuccessfulconversion.Inthecasethat the conversion was aborted by a reset, ADCRH and ADCRL return to their reset states. 9.4.4.4 Power Control The ADC module remains in its idle state until a conversion is initiated.If ADACK is selected as the conversion clock source, the ADACK clock generator is also enabled. PowerconsumptionwhenactivecanbereducedbysettingADLPC.Thisresultsinalowermaximumvalue for f (see the electrical specifications). ADCK 9.4.4.5 Total Conversion Time The total conversion time depends on the sample time (as determined by ADLSMP), the MCU bus frequency,theconversionmode(8-bitor10-bit),andthefrequencyoftheconversionclock(f ).After ADCK the module becomes active, sampling of the input begins. ADLSMP is used to select between short and long sample times.When sampling is complete, the converter is isolated from the input channel and a successiveapproximationalgorithmisperformedtodeterminethedigitalvalueoftheanalogsignal.The MC9S08SH8MCUSeriesDataSheet,Rev.3 138 Freescale Semiconductor

Chapter 9 Analog-to-Digital Converter (S08ADC10V1) result of the conversion is transferred to ADCRH and ADCRL upon completion of the conversion algorithm. If the bus frequency is less than the f frequency, precise sample time for continuous conversions ADCK cannotbeguaranteedwhenshortsampleisenabled(ADLSMP=0).Ifthebusfrequencyislessthan1/11th ofthef frequency,precisesampletimeforcontinuousconversionscannotbeguaranteedwhenlong ADCK sample is enabled (ADLSMP=1). The maximum total conversion time for different conditions is summarized in Table9-12. Table9-12. Total Conversion Time vs. Control Conditions Conversion Type ADICLK ADLSMP Max Total Conversion Time Single or first continuous 8-bit 0x, 10 0 20 ADCK cycles + 5 bus clock cycles Single or first continuous 10-bit 0x, 10 0 23 ADCK cycles + 5 bus clock cycles Single or first continuous 8-bit 0x, 10 1 40 ADCK cycles + 5 bus clock cycles Single or first continuous 10-bit 0x, 10 1 43 ADCK cycles + 5 bus clock cycles Single or first continuous 8-bit 11 0 5μs + 20 ADCK + 5 bus clock cycles Single or first continuous 10-bit 11 0 5μs + 23 ADCK + 5 bus clock cycles Single or first continuous 8-bit 11 1 5μs + 40 ADCK + 5 bus clock cycles Single or first continuous 10-bit 11 1 5μs + 43 ADCK + 5 bus clock cycles Subsequent continuous 8-bit; xx 0 17 ADCK cycles f > f BUS ADCK Subsequent continuous 10-bit; xx 0 20 ADCK cycles f > f BUS ADCK Subsequent continuous 8-bit; xx 1 37 ADCK cycles f > f /11 BUS ADCK Subsequent continuous 10-bit; xx 1 40 ADCK cycles f > f /11 BUS ADCK Themaximumtotalconversiontimeisdeterminedbytheclocksourcechosenandthedivideratioselected. TheclocksourceisselectablebytheADICLKbits,andthedivideratioisspecifiedbytheADIVbits.For example,in10-bitmode,withthebusclockselectedastheinputclocksource,theinputclockdivide-by-1 ratio selected, and a bus frequency of 8 MHz, then the conversion time for a single conversion is: 23 ADCK cyc 5 bus cyc Conversion time = + = 3.5 μs 8 MHz/1 8 MHz Number of bus cycles = 3.5 μs x 8 MHz = 28 cycles NOTE The ADCK frequency must be between f minimum and f ADCK ADCK maximum to meet ADC specifications. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 139

Chapter 9 Analog-to-Digital Converter (S08ADC10V1) 9.4.5 Automatic Compare Function The compare function can be configured to check for either an upper limit or lower limit. After the input is sampled and converted, the result is added to the two’s complement of the compare value (ADCCVH andADCCVL).Whencomparingtoanupperlimit(ACFGT=1),iftheresultisgreater-thanorequal-to thecomparevalue,COCOisset.Whencomparingtoalowerlimit(ACFGT=0),iftheresultislessthan thecomparevalue,COCOisset.Thevaluegeneratedbytheadditionoftheconversionresultandthetwo’s complement of the compare value is transferred to ADCRH and ADCRL. Upon completion of a conversion while the compare function is enabled, if the compare condition is not true,COCOisnotsetandnodataistransferredtotheresultregisters.AnADCinterruptisgeneratedupon the setting of COCO if the ADC interrupt is enabled (AIEN = 1). NOTE Thecomparefunctioncanbeusedtomonitorthevoltageonachannelwhile theMCUisineitherwaitorstop3mode.TheADCinterruptwillwakethe MCU when the compare condition is met. 9.4.6 MCU Wait Mode Operation The WAIT instruction puts the MCU in a lower power-consumption standby mode from which recovery is very fast because the clock sources remain active. If a conversion is in progress when the MCU enters waitmode,itcontinuesuntilcompletion.ConversionscanbeinitiatedwhiletheMCUisinwaitmodeby means of the hardware trigger or if continuous conversions are enabled. Thebusclock,busclockdividedbytwo,andADACKareavailableasconversionclocksourceswhilein wait mode. The use of ALTCLK as the conversion clock source in wait is dependent on the definition of ALTCLK for this MCU. Consult the module introduction for information on ALTCLK specific to this MCU. AconversioncompleteeventsetstheCOCOandgeneratesanADCinterrupttowaketheMCUfromwait mode if the ADC interrupt is enabled (AIEN = 1). 9.4.7 MCU Stop3 Mode Operation The STOP instruction is used to put the MCU in a low power-consumption standby mode during which most or all clock sources on the MCU are disabled. 9.4.7.1 Stop3 Mode With ADACK Disabled Iftheasynchronousclock,ADACK,isnotselectedastheconversionclock,executingaSTOPinstruction aborts the current conversion and places the ADC in its idle state. The contents of ADCRH and ADCRL areunaffectedbystop3mode.Afterexitingfromstop3mode,asoftwareorhardwaretriggerisrequiredto resume conversions. MC9S08SH8MCUSeriesDataSheet,Rev.3 140 Freescale Semiconductor

Chapter 9 Analog-to-Digital Converter (S08ADC10V1) 9.4.7.2 Stop3 Mode With ADACK Enabled If ADACK is selected as the conversion clock, the ADC continues operation during stop3 mode. For guaranteedADCoperation,theMCU’svoltageregulatormustremainactiveduringstop3mode.Consult the module introduction for configuration information for this MCU. IfaconversionisinprogresswhentheMCUentersstop3mode,itcontinuesuntilcompletion.Conversions can be initiated while the MCU is in stop3 mode by means of the hardware trigger or if continuous conversions are enabled. AconversioncompleteeventsetstheCOCOandgeneratesanADCinterrupttowaketheMCUfromstop3 mode if the ADC interrupt is enabled (AIEN = 1). NOTE ItispossiblefortheADCmoduletowakethesystemfromlowpowerstop and cause the MCU to begin consuming run-level currents without generating a system level interrupt. To prevent this scenario, software should ensure that the data transfer blocking mechanism (discussed in Section9.4.4.2, “Completing Conversions) is cleared when entering stop3 and continuing ADC conversions. 9.4.8 MCU Stop1 and Stop2 Mode Operation TheADCmoduleisautomaticallydisabledwhentheMCUenterseitherstop1orstop2mode.Allmodule registers contain their reset values following exit from stop1 or stop2. Therefore the module must be re-enabled and re-configured following exit from stop1 or stop2. 9.5 Initialization Information This section gives an example which provides some basic direction on how a user would initialize and configure the ADC module. The user has the flexibility of choosing between configuring the module for 8-bitor10-bitresolution,singleorcontinuousconversion,andapolledorinterruptapproach,amongmany other options. Refer toTable9-6,Table9-7, andTable9-8 for information used in this example. NOTE Hexadecimalvaluesdesignatedbyapreceding0x,binaryvaluesdesignated by a preceding %, and decimal values have no preceding character. 9.5.1 ADC Module Initialization Example 9.5.1.1 Initialization Sequence Before the ADC module can be used to complete conversions, an initialization procedure must be performed. A typical sequence is as follows: 1. Update the configuration register (ADCCFG) to select the input clock source and the divide ratio usedtogeneratetheinternalclock,ADCK.Thisregisterisalsousedforselectingsampletimeand low-power configuration. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 141

Chapter 9 Analog-to-Digital Converter (S08ADC10V1) 2. Update status and control register 2 (ADCSC2) to select the conversion trigger (hardware or software) and compare function options, if enabled. 3. Update status and control register 1 (ADCSC1) to select whether conversions will be continuous orcompletedonlyonce,andtoenableordisableconversioncompleteinterrupts.Theinputchannel on which conversions will be performed is also selected here. 9.5.1.2 Pseudo — Code Example In this example, the ADC module will be set up with interrupts enabled to perform a single 10-bit conversionatlowpowerwithalongsampletimeoninputchannel1,wheretheinternalADCKclockwill be derived from the bus clock divided by 1. ADCCFG = 0x98 (%10011000) Bit 7 ADLPC 1 Configures for low power (lowers maximum clock speed) Bit 6:5 ADIV 00 Sets the ADCK to the input clock÷ 1 Bit 4 ADLSMP 1 Configures for long sample time Bit 3:2 MODE 10 Sets mode at 10-bit conversions Bit 1:0 ADICLK 00 Selects bus clock as input clock source ADCSC2 = 0x00 (%00000000) Bit 7 ADACT 0 Flag indicates if a conversion is in progress Bit 6 ADTRG 0 Software trigger selected Bit 5 ACFE 0 Compare function disabled Bit 4 ACFGT 0 Not used in this example Bit 3:2 00 Unimplemented or reserved, always reads zero Bit 1:0 00 Reserved for Freescale’s internal use; always write zero ADCSC1 = 0x41 (%01000001) Bit 7 COCO 0 Read-only flag which is set when a conversion completes Bit 6 AIEN 1 Conversion complete interrupt enabled Bit 5 ADCO 0 One conversion only (continuous conversions disabled) Bit 4:0 ADCH 00001 Input channel 1 selected as ADC input channel ADCRH/L = 0xxx Holds results of conversion. Read high byte(ADCRH) before low byte (ADCRL) so thatconversion data cannot be overwritten with data from the next conversion. ADCCVH/L = 0xxx Holds compare value when compare function enabled APCTL1=0x02 AD1 pin I/O control disabled. All other AD pins remain general purpose I/O pins APCTL2=0x00 All other AD pins remain general purpose I/O pins MC9S08SH8MCUSeriesDataSheet,Rev.3 142 Freescale Semiconductor

Chapter 9 Analog-to-Digital Converter (S08ADC10V1) RESET INITIALIZE ADC ADCCFG = $98 ADCSC2 = $00 ADCSC1 = $41 CHECK NO COCO=1? YES READ ADCRH THEN ADCRL TO CLEAR COCO BIT CONTINUE Figure9-14. Initialization Flowchart for Example 9.6 Application Information ThissectioncontainsinformationforusingtheADCmoduleinapplications.TheADChasbeendesigned to be integrated into a microcontroller for use in embedded control applications requiring an A/D converter. 9.6.1 External Pins and Routing ThefollowingsectionsdiscusstheexternalpinsassociatedwiththeADCmoduleandhowtheyshouldbe used for best results. 9.6.1.1 Analog Supply Pins The ADC module has analog power and ground supplies (V and V ) which are available as DDAD SSAD separatepinsonsomedevices.Onotherdevices,V issharedonthesamepinastheMCUdigitalV , SSAD SS andonothers,bothV andV aresharedwiththeMCUdigitalsupplypins.Inthesecases,there SSAD DDAD are separate pads for the analog supplies which are bonded to the same pin as the corresponding digital supply so that some degree of isolation between the supplies is maintained. Whenavailableonaseparatepin,bothV andV mustbeconnectedtothesamevoltagepotential DDAD SSAD as their corresponding MCU digital supply (V and V ) and must be routed carefully for maximum DD SS noise immunity and bypass capacitors placed as near as possible to the package. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 143

Chapter 9 Analog-to-Digital Converter (S08ADC10V1) In cases where separate power supplies are used for analog and digital power, the ground connection betweenthesesuppliesmustbeattheV pin.Thisshouldbetheonlygroundconnectionbetweenthese SSAD supplies if possible. The V pin makes a good single point ground location. SSAD 9.6.1.2 Analog Reference Pins Inadditiontotheanalogsupplies,theADCmodulehasconnectionsfortworeferencevoltageinputs.The high reference is V , which may be shared on the same pin as V on some devices. The low REFH DDAD reference is V , which may be shared on the same pin as V on some devices. REFL SSAD When available on a separate pin, V may be connected to the same potential as V , or may be REFH DDAD drivenbyanexternalsourcethatisbetweentheminimumV specandtheV potential(V DDAD DDAD REFH must never exceed V ). When available on a separate pin, V must be connected to the same DDAD REFL voltage potential asV . Both V and V must be routed carefully for maximum noise SSAD REFH REFL immunity and bypass capacitors placed as near as possible to the package. ACcurrentintheformofcurrentspikesrequiredtosupplychargetothecapacitorarrayateachsuccessive approximationstepisdrawnthroughtheV andV loop.Thebestexternalcomponenttomeetthis REFH REFL currentdemandisa0.1μFcapacitorwithgoodhighfrequencycharacteristics.Thiscapacitorisconnected betweenV andV andmustbeplacedasnearaspossibletothepackagepins.Resistanceinthe REFH REFL path is not recommended because the current will cause a voltage drop which could result in conversion errors. Inductance in this path must be minimum (parasitic only). 9.6.1.3 Analog Input Pins TheexternalanaloginputsaretypicallysharedwithdigitalI/OpinsonMCUdevices.ThepinI/Ocontrol is disabled by setting the appropriate control bit in one of the pin control registers. Conversions can be performed on inputs without the associated pin control register bit set. It is recommended that the pin controlregisterbitalwaysbesetwhenusingapinasananaloginput.Thisavoidsproblemswithcontention because the output buffer will be in its high impedance state and the pullup is disabled. Also, the input bufferdrawsdccurrentwhenitsinputisnotateitherV orV .Settingthepincontrolregisterbitsfor DD SS all pins used as analog inputs should be done to achieve lowest operating current. Empirical data shows that capacitors on the analog inputs improve performance in the presence of noise orwhenthesourceimpedanceishigh.Useof0.01μFcapacitorswithgoodhigh-frequencycharacteristics issufficient.Thesecapacitorsarenotnecessaryinallcases,butwhenusedtheymustbeplacedasnearas possible to the package pins and be referenced toV . SSA For proper conversion, the input voltage must fall between V and V . If the input is equal to or REFH REFL exceedsV ,theconvertercircuitconvertsthesignalto$3FF(fullscale10-bitrepresentation)or$FF REFH (fullscale8-bitrepresentation).IftheinputisequaltoorlessthanV ,theconvertercircuitconvertsit REFL to $000. Input voltages between V and V are straight-line linear conversions. There will be a REFH REFL brief current associated with V when the sampling capacitor is charging. The input is sampled for REFL 3.5cycles of the ADCK source when ADLSMP is low, or 23.5cycles when ADLSMP is high. Forminimallossofaccuracyduetocurrentinjection,pinsadjacenttotheanaloginputpinsshouldnotbe transitioning during conversions. MC9S08SH8MCUSeriesDataSheet,Rev.3 144 Freescale Semiconductor

Chapter 9 Analog-to-Digital Converter (S08ADC10V1) 9.6.2 Sources of Error Several sources of error exist for A/D conversions. These are discussed in the following sections. 9.6.2.1 Sampling Error Forproperconversions,theinputmustbesampledlongenoughtoachievetheproperaccuracy.Giventhe maximuminputresistanceofapproximately7kΩandinputcapacitanceofapproximately5.5pF,sampling towithin1/4LSB(at10-bitresolution)canbeachievedwithintheminimumsamplewindow(3.5cycles@ 8MHz maximum ADCK frequency) provided the resistance of the external analog source (R ) is kept AS below 5kΩ. Higher source resistances or higher-accuracy sampling is possible by setting ADLSMP (to increase the sample window to 23.5 cycles) or decreasing ADCK frequency to increase sample time. 9.6.2.2 Pin Leakage Error LeakageontheI/Opinscancauseconversionerroriftheexternalanalogsourceresistance(R )ishigh. AS Ifthiserrorcannotbetoleratedbytheapplication,keepR lowerthanV / (2N*I )forlessthan AS DDAD LEAK 1/4LSB leakage error (N = 8 in 8-bit mode or 10 in 10-bit mode). 9.6.2.3 Noise-Induced Errors System noise which occurs during the sample or conversion process can affect the accuracy of the conversion. The ADC accuracy numbers are guaranteed as specified only if the following conditions are met: • There is a 0.1μF low-ESR capacitor from V to V . REFH REFL • There is a 0.1μF low-ESR capacitor from V to V . DDAD SSAD • Ifinductiveisolationisusedfromtheprimarysupply,anadditional1μFcapacitorisplacedfrom V to V . DDAD SSAD • V (and V , if connected) is connected to V at a quiet point in the ground plane. SSAD REFL SS • Operate the MCU in wait or stop3 mode before initiating (hardware triggered conversions) or immediately after initiating (hardware or software triggered conversions) the ADC conversion. — Forsoftwaretriggeredconversions,immediatelyfollowthewritetotheADCSC1withaWAIT instruction or STOP instruction. — Forstop3modeoperation,selectADACKastheclocksource.Operationinstop3reducesV DD noise but increases effective conversion time due to stop recovery. • There is no I/O switching, input or output, on the MCU during the conversion. Therearesomesituationswhereexternalsystemactivitycausesradiatedorconductednoiseemissionsor excessive V noise is coupled into the ADC. In these situations, or when the MCU cannot be placed in DD waitorstop3orI/Oactivitycannotbehalted,theserecommendedactionsmayreducetheeffectofnoise on the accuracy: • Place a 0.01μF capacitor (C ) on the selected input channel to V or V (this will AS REFL SSAD improve noise issues but will affect sample rate based on the external analog source resistance). MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 145

Chapter 9 Analog-to-Digital Converter (S08ADC10V1) • Average the result by converting the analog input many times in succession and dividing the sum of the results. Four samples are required to eliminate the effect of a 1LSB, one-time error. • Reduce the effect of synchronous noise by operating off the asynchronous clock (ADACK) and averaging. Noise that is synchronous to ADCK cannot be averaged out. 9.6.2.4 Code Width and Quantization Error The ADC quantizes the ideal straight-line transfer function into 1024 steps (in 10-bit mode). Each step ideally has the same height (1 code) and width. The width is defined as the delta between the transition pointstoonecodeandthenext.TheidealcodewidthforanNbitconverter(inthiscaseNcanbe8or10), defined as 1LSB, is: 1LSB = (VREFH - VREFL) / 2N Eqn.9-2 Thereisaninherentquantizationerrorduetothedigitizationoftheresult.For8-bitor10-bitconversions the code will transition when the voltage is at the midpoint between the points where the straight line transfer function is exactly represented by the actual transfer function. Therefore, the quantization error will be± 1/2LSB in 8- or 10-bit mode. As a consequence, however, the code width of the first ($000) conversion is only 1/2LSB and the code width of the last ($FF or $3FF) is 1.5LSB. 9.6.2.5 Linearity Errors The ADC may also exhibit non-linearity of several forms. Every effort has been made to reduce these errors but the system should be aware of them because they affect overall accuracy. These errors are: • Zero-scaleerror(E )(sometimescalledoffset)—Thiserrorisdefinedasthedifferencebetween ZS the actual code width of the first conversion and the ideal code width (1/2LSB). Note, if the first conversionis$001,thenthedifferencebetweentheactual$001codewidthanditsideal(1LSB)is used. • Full-scale error (E ) — This error is defined as the difference between the actual code width of FS thelastconversionandtheidealcodewidth(1.5LSB).Note,ifthelastconversionis$3FE,thenthe difference between the actual $3FE code width and its ideal (1LSB) is used. • Differentialnon-linearity(DNL)—Thiserrorisdefinedastheworst-casedifferencebetweenthe actual code width and the ideal code width for all conversions. • Integralnon-linearity(INL)—Thiserrorisdefinedasthehighest-valuethe(absolutevalueofthe) running sum of DNL achieves. More simply, this is the worst-case difference of the actual transition voltage to a given code and its corresponding ideal transition voltage, for all codes. • Totalunadjustederror(TUE)—Thiserrorisdefinedasthedifferencebetweentheactualtransfer function and the ideal straight-line transfer function, and therefore includes all forms of error. 9.6.2.6 Code Jitter, Non-Monotonicity and Missing Codes Analog-to-digital converters are susceptible to three special forms of error. These are code jitter, non-monotonicity, and missing codes. Code jitter is when, at certain points, a given input voltage converts to one of two values when sampled repeatedly. Ideally, when the input voltage is infinitesimally smaller than the transition voltage, the MC9S08SH8MCUSeriesDataSheet,Rev.3 146 Freescale Semiconductor

Chapter 9 Analog-to-Digital Converter (S08ADC10V1) converteryieldsthelowercode(andvice-versa).However,evenverysmallamountsofsystemnoisecan cause the converter to be indeterminate (between two codes) for a range of input voltages around the transitionvoltage.Thisrangeisnormallyaround 1/2LSBandwillincreasewithnoise.Thiserrormaybe reducedbyrepeatedlysamplingtheinputandaveragingtheresult.Additionallythetechniquesdiscussed inSection9.6.2.3 will reduce this error. Non-monotonicity is defined as when, except for code jitter, the converter converts to a lower code for a higher input voltage. Missing codes are those values which are never converted for any input value. In 8-bit or 10-bit mode, the ADC is guaranteed to be monotonic and to have no missing codes. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 147

Chapter 9 Analog-to-Digital Converter (S08ADC10V1) MC9S08SH8MCUSeriesDataSheet,Rev.3 148 Freescale Semiconductor

Chapter 10 Internal Clock Source (S08ICSV2) 10.1 Introduction Theinternalclocksource(ICS)moduleprovidesclocksourcechoicesfortheMCU.Themodulecontains a frequency-locked loop (FLL) as a clock source that is controllable by either an internal or an external reference clock. The module can provide this FLL clock or either of the internal or external reference clocks as a source for the MCU system clock. There are also signals provided to control a low power oscillator(XOSC)moduletoallowtheuseofanexternalcrystal/resonatorastheexternalreferenceclock. Whicheverclocksourceischosen,itispassedthroughareducedbusdivider(BDIV)whichallowsalower final output clock frequency to be derived. The bus frequency will be one-half of the ICSOUT frequency. 10.1.1 Module Configuratio Whentheinternalreferenceisenabledinstopmode(IREFSTEN=1),thevoltageregulatormustalsobe enabled in stop mode by setting the LVDE and LVDSE bits in the SPMSC1 register. Figure10-1 shows the MC9S08SH8 block diagram with the ICS highlighted. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 149

Chapter10 Internal Clock Source (S08ICSV2) BKGD/MS IRQ HCS08 CORE DEBUG MODULE (DBG) CPU BDC 8-BIT MODULO TIMER TCLK HCS08 SYSTEM CONTROL MODULE (MTIM) PTA5/IRQ/TCLK/RESET RESETS AND INTERRUPTS PTA4/ACMPO/BKGD/MS MODES OF OPERATION SCL T A PTA3/PAI3/SCL/ADP3 POWER MANAGEMENT IIC MODULE (IIC) SDA POR PTA2/PAI2/SDA/ADP2 COP IRQ LVD PTA1/PIA1/TPM2CH0/ADP1/ACMP– SS PTA0/PIA0/TPM1CH0/ADP0/ACMP+ MISO SERIAL PERIPHERAL MOSI USER FLASH INTERFACE MODULE (SPI) (MC9S08SH8 =8,192 BYTES) SPSCK PTB7/SCL/EXTAL (MC9S08SH4 =4096 BYTES) PTB6/SDA/XTAL SERIAL COMMUNICATIONS RxD SEE NOTE 1 INTERFACE MODULE (SCI) TxD USER RAM PTB5/TPM1CH1/SS (MC9S08SH8 =512 BYTES) TCLK T B PTB4/TPM2CH1/MISO (MC9S08SH4 =256 BYTES) 16-BIT TIMER/PWM TPM1CH0 OR PTB3/PIB3/MOSI/ADP7 P MODULE (TPM1) TPM1CH1 PTB2/PIB2/SPSCK/ADP6 REAL-TIME COUNTER (RTC) TCLK PTB1/PIB1/TxD/ADP5 40-MHz INTERNAL CLOCK 16-BIT TIMER/PWM TPM2CH0 PTB0/PIB0/RxD/ADP4 SOURCE (ICS) MODULE (TPM2) TPM2CH1 SEE NOTE 1, 2 LOW-POWER OSCILLATOR EXTAL C PTC3/ADP11 31.25 kHz to 38.4 kHz T PTC2/ADP10 1 MHz to 16 MHz R XTAL O PTC1/TPM1CH1/ADP9 (XOSC) P PTC0/TPM1CH0/ADP8 ACMPO SEE NOTE3 ANALOG COMPARATOR ACMP– (ACMP) ACMP+ V DD VOLTAGE REGULATOR VSS 10-BIT ADP11-ADP0 ANALOG-TO-DIGITAL V CONVERTER (ADC) DDA V SSA VREFH NOTES V REFL = Pin can be enabled as part of the ganged output drive feature NOTE1: Port B not available on 8-pinpackages NOTE2: Port C not available on 8-pin or 16-pin packages NOTE 3: V /V and V /V , are double bonded to V and V respectively. DDA REFH SSA REFL DD SS Figure10-1.MC9S08SH8 Block Diagram Highlighting theICS Module MC9S08SH8MCUSeriesDataSheet,Rev.3 150 Freescale Semiconductor

Chapter 10 Internal Clock Source (S08ICSV2) 10.1.2 Features KeyfeaturesoftheICSmodulefollow.Fordevicespecificinformation,refertotheICSCharacteristicsin the Electricals section of the documentation. • Frequency-locked loop (FLL) is trimmable for accuracy — 0.2% resolution using internal 32kHz reference — 2% deviation over voltage and temperature using internal 32kHz reference • Internal or external reference clocks up to 5MHz can be used to control the FLL — 3 bit select for reference divider is provided • Internal reference clock has 9 trim bits available • Internal or external reference clocks can be selected as the clock source for the MCU • Whichever clock is selected as the source can be divided down — 2 bit select for clock divider is provided – Allowable dividers are: 1, 2, 4, 8 – BDC clock is provided as a constant divide by 2 of the DCO output • Control signals for a low power oscillator as the external reference clock are provided — HGO, RANGE, EREFS, ERCLKEN, EREFSTEN • FLL Engaged Internal mode is automatically selected out of reset 10.1.3 Block Diagram Figure10-2 is the ICS block diagram. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 151

Chapter 10 Internal Clock Source (S08ICSV2) Optional External Reference Clock Source Block ICSERCLK RANGE EREFS ERCLKEN HGO EREFSTEN IRCLKEN ICSIRCLK IREFSTEN CLKS BDIV / 2n ICSOUT Internal n=0-3 Reference LP Clock DCOOUT IREFS 9 DCO / 2 ICSLCLK TRIM ICSFFCLK 9 / 2n RDIV_CLK Filter n=0-7 FLL RDIV Internal Clock Source Block Figure10-2. Internal Clock Source (ICS) Block Diagram 10.1.4 Modes of Operation There are seven modes of operation for the ICS: FEI, FEE, FBI, FBILP, FBE, FBELP, and stop. 10.1.4.1 FLL Engaged Internal (FEI) InFLLengagedinternalmode,whichisthedefaultmode,theICSsuppliesaclockderivedfromtheFLL which is controlled by the internal reference clock. The BDC clock is supplied from the FLL. 10.1.4.2 FLL Engaged External (FEE) InFLLengagedexternalmode,theICSsuppliesaclockderivedfromtheFLLwhichiscontrolledbyan external reference clock. The BDC clock is supplied from the FLL. 10.1.4.3 FLL Bypassed Internal (FBI) In FLL bypassed internal mode, the FLL is enabled and controlled by the internal reference clock, but is bypassed.TheICSsuppliesaclockderivedfromtheinternalreferenceclock.TheBDCclockissupplied from the FLL. MC9S08SH8MCUSeriesDataSheet,Rev.3 152 Freescale Semiconductor

Chapter 10 Internal Clock Source (S08ICSV2) 10.1.4.4 FLL Bypassed Internal Low Power (FBILP) InFLLbypassedinternallowpowermode,theFLLisdisabledandbypassed,andtheICSsuppliesaclock derived from the internal reference clock. The BDC clock is not available. 10.1.4.5 FLL Bypassed External (FBE) In FLL bypassed external mode, the FLL is enabled and controlled by an external reference clock, but is bypassed.TheICSsuppliesaclockderivedfromtheexternalreferenceclock.Theexternalreferenceclock canbeanexternalcrystal/resonatorsuppliedbyanOSCcontrolledbytheICS,oritcanbeanotherexternal clock source. The BDC clock is supplied from the FLL. 10.1.4.6 FLL Bypassed External Low Power (FBELP) InFLLbypassedexternallowpowermode,theFLLisdisabledandbypassed,andtheICSsuppliesaclock derivedfromtheexternalreferenceclock.Theexternalreferenceclockcanbeanexternalcrystal/resonator supplied by an OSC controlled by the ICS, or it can be another external clock source. The BDC clock is not available. 10.1.4.7 Stop (STOP) InstopmodetheFLLisdisabledandtheinternalorexternalreferenceclockscanbeselectedtobeenabled or disabled. The BDC clock is not available and the ICS does not provide an MCU clock source. 10.2 External Signal Description There are no ICS signals that connect off chip. 10.3 Register Definitio Figure10-1 is a summary of ICS registers. Table10-1. ICS Register Summary Name 7 6 5 4 3 2 1 0 R ICSC1 CLKS RDIV IREFS IRCLKEN IREFSTEN W R ICSC2 BDIV RANGE HGO LP EREFS ERCLKEN EREFSTEN W R ICSTRM TRIM W R 0 0 0 IREFST CLKST OSCINIT ICSSC FTRIM W MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 153

Chapter 10 Internal Clock Source (S08ICSV2) 10.3.1 ICS Control Register 1 (ICSC1) 7 6 5 4 3 2 1 0 R CLKS RDIV IREFS IRCLKEN IREFSTEN W Reset: 0 0 0 0 0 1 0 0 Figure10-3. ICS Control Register 1 (ICSC1) Table10-2. ICS Control Register 1 Field Descriptions Field Description 7:6 Clock Source Select — Selects the clock source that controls the bus frequency. The actual bus frequency CLKS depends on the value of the BDIV bits. 00 Output of FLL is selected. 01 Internal reference clock is selected. 10 External reference clock is selected. 11 Reserved, defaults to 00. 5:3 Reference Divider — Selects the amount to divide down the FLL reference clock selected by the IREFS bits. RDIV Resulting frequency must be in the range 31.25 kHz to 39.0625 kHz. 000 Encoding 0 — Divides reference clock by 1 (reset default) 001 Encoding 1 — Divides reference clock by 2 010 Encoding 2 — Divides reference clock by 4 011 Encoding 3 — Divides reference clock by 8 100 Encoding 4 — Divides reference clock by 16 101 Encoding 5 — Divides reference clock by 32 110 Encoding 6 — Divides reference clock by 64 111 Encoding 7 — Divides reference clock by 128 2 Internal Reference Select — The IREFS bit selects the reference clock source for the FLL. IREFS 1 Internal reference clock selected 0 External reference clock selected 1 Internal Reference Clock Enable — The IRCLKEN bit enables the internal reference clock for use as IRCLKEN ICSIRCLK. 1 ICSIRCLK active 0 ICSIRCLK inactive 0 Internal Reference Stop Enable — The IREFSTEN bit controls whether or not the internal reference clock IREFSTEN remains enabled when the ICS enters stop mode. 1 InternalreferenceclockstaysenabledinstopifIRCLKENissetorifICSisinFEI,FBI,orFBILPmodebefore entering stop 0 Internal reference clock is disabled in stop MC9S08SH8MCUSeriesDataSheet,Rev.3 154 Freescale Semiconductor

Chapter 10 Internal Clock Source (S08ICSV2) 10.3.2 ICS Control Register 2 (ICSC2) 7 6 5 4 3 2 1 0 R BDIV RANGE HGO LP EREFS ERCLKEN EREFSTEN W Reset: 0 1 0 0 0 0 0 0 Figure10-4. ICS Control Register 2 (ICSC2) Table10-3. ICS Control Register 2 Field Descriptions Field Description 7:6 BusFrequencyDivider—SelectstheamounttodividedowntheclocksourceselectedbytheCLKSbits.This BDIV controls the bus frequency. 00 Encoding 0 — Divides selected clock by 1 01 Encoding 1 — Divides selected clock by 2 (reset default) 10 Encoding 2 — Divides selected clock by 4 11 Encoding 3 — Divides selected clock by 8 5 Frequency Range Select — Selects the frequency range for the external oscillator. RANGE 1 High frequency range selected for the external oscillator 0 Low frequency range selected for the external oscillator 4 High Gain Oscillator Select — The HGO bit controls the external oscillator mode of operation. HGO 1 Configure external oscillator for high gain operation 0 Configure external oscillator for low power operation 3 Low Power Select — The LP bit controls whether the FLL is disabled in FLL bypassed modes. LP 1 FLL is disabled in bypass modes unless BDM is active 0 FLL is not disabled in bypass mode 2 External Reference Select — The EREFS bit selects the source for the external reference clock. EREFS 1 Oscillator requested 0 External Clock Source requested 1 External Reference Enable — The ERCLKEN bit enables the external reference clock for use as ICSERCLK. ERCLKEN 1 ICSERCLK active 0 ICSERCLK inactive 0 External Reference Stop Enable — The EREFSTEN bit controls whether or not the external reference clock EREFSTEN remains enabled when the ICS enters stop mode. 1 External reference clock stays enabled in stop if ERCLKEN is set or if ICS is in FEE, FBE, or FBELP mode before entering stop 0 External reference clock is disabled in stop MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 155

Chapter 10 Internal Clock Source (S08ICSV2) 10.3.3 ICS Trim Register (ICSTRM) 7 6 5 4 3 2 1 0 R TRIM W POR: 1 0 0 0 0 0 0 0 Reset: U U U U U U U U Figure10-5. ICS Trim Register (ICSTRM) Table10-4. ICS Trim Register Field Descriptions Field Description 7:0 ICS Trim Setting — The TRIM bits control the internal reference clock frequency by controlling the internal TRIM reference clock period. The bits’ effect are binary weighted (i.e., bit 1 will adjust twice as much as bit 0). IncreasingthebinaryvalueinTRIMwillincreasetheperiod,anddecreasingthevaluewilldecreasetheperiod. An additional fine trim bit is available in ICSSC as the FTRIM bit. 10.3.4 ICS Status and Control (ICSSC) 7 6 5 4 3 2 1 0 R 0 0 0 IREFST CLKST OSCINIT FTRIM W POR: 0 0 0 1 0 0 0 0 Reset: 0 0 0 1 0 0 0 U Figure10-6. ICS Status and Control Register (ICSSC) Table10-5. ICS Status and Control Register Field Descriptions Field Description 7:5 Reserved, should be cleared. 4 InternalReferenceStatus—TheIREFSTbitindicatesthecurrentsourceforthereferenceclock.TheIREFST IREFST bit does not update immediately after a write to the IREFS bit due to internal synchronization between clock domains. 0 Source of reference clock is external clock. 1 Source of reference clock is internal clock. 3-2 Clock Mode Status — The CLKST bits indicate the current clock mode. The CLKST bits don’t update CLKST immediately after a write to the CLKS bits due to internal synchronization between clock domains. 00 Output of FLL is selected. 01 FLL Bypassed, Internal reference clock is selected. 10 FLL Bypassed, External reference clock is selected. 11 Reserved. MC9S08SH8MCUSeriesDataSheet,Rev.3 156 Freescale Semiconductor

Chapter 10 Internal Clock Source (S08ICSV2) Table10-5. ICS Status and Control Register Field Descriptions (continued) Field Description 1 OSCInitialization—IftheexternalreferenceclockisselectedbyERCLKENorbytheICSbeinginFEE,FBE, or FBELP mode, and if EREFS is set, then this bit is set after the initialization cycles of the external oscillator clock have completed. This bit is only cleared when either ERCLKEN or EREFS are cleared. 0 ICS Fine Trim — The FTRIM bit controls the smallest adjustment of the internal reference clock frequency. Setting FTRIM will increase the period and clearing FTRIM will decrease the period by the smallest amount possible. 10.4 Functional Description 10.4.1 Operational Modes IREFS=1 CLKS=00 FLL Engaged IREFS=0 Internal (FEI) IREFS=1 CLKS=10 CLKS=01 BDM Enabled BDM Enabled or LP =0 or LP=0 FLL Bypassed FLL Bypassed FLL Bypassed FLL Bypassed External Low Internal Low External (FBE) Internal (FBI) Power(FBELP) Power(FBILP) IREFS=0 IREFS=1 CLKS=10 CLKS=01 BDM Disabled BDM Disabled and LP=1 FLL Engaged and LP=1 External (FEE) IREFS=0 CLKS=00 Returns to state that was active Entered from any state Stop before MCU entered stop, unless when MCU enters stop RESET occurs while in stop. Figure10-7. Clock Switching Modes ThesevenstatesoftheICSareshownasastatediagramandaredescribedbelow.Thearrowsindicatethe allowed movements between the states. 10.4.1.1 FLL Engaged Internal (FEI) FLL engaged internal (FEI) is the default mode of operation and is entered when all the following conditions occur: MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 157

Chapter 10 Internal Clock Source (S08ICSV2) • CLKS bits are written to 00 • IREFS bit is written to 1 • RDIV bits are written to divide trimmed reference clock to be within the range of 31.25 kHz to 39.0625 kHz. InFLLengagedinternalmode,theICSOUTclockisderivedfromtheFLLclock,whichiscontrolledby theinternalreferenceclock.TheFLLloopwilllockthefrequencyto1024timesthereferencefrequency, as selected by the RDIV bits. The ICSLCLK is available for BDC communications, and the internal reference clock is enabled. 10.4.1.2 FLL Engaged External (FEE) The FLL engaged external (FEE) mode is entered when all the following conditions occur: • CLKS bits are written to 00 • IREFS bit is written to 0 • RDIVbitsarewrittentodividereferenceclocktobewithintherangeof31.25kHzto39.0625kHz InFLLengagedexternalmode,theICSOUTclockisderivedfromtheFLLclockwhichiscontrolledby theexternalreferenceclock.TheFLLloopwilllockthefrequencyto1024timesthereferencefrequency, as selected by the RDIV bits. The ICSLCLK is available for BDC communications, and the external reference clock is enabled. 10.4.1.3 FLL Bypassed Internal (FBI) The FLL bypassed internal (FBI) mode is entered when all the following conditions occur: • CLKS bits are written to 01 • IREFS bit is written to 1. • BDM mode is active or LP bit is written to 0 InFLLbypassedinternalmode,theICSOUTclockisderivedfromtheinternalreferenceclock.TheFLL clockiscontrolledbytheinternalreferenceclock,andtheFLLloopwilllocktheFLLfrequencyto1024 times the reference frequency, as selected by the RDIV bits. The ICSLCLK will be available for BDC communications, and the internal reference clock is enabled. 10.4.1.4 FLL Bypassed Internal Low Power (FBILP) The FLL bypassed internal low power (FBILP) mode is entered when all the following conditions occur: • CLKS bits are written to 01 • IREFS bit is written to 1. • BDM mode is not active and LP bit is written to 1 InFLLbypassedinternallowpowermode,theICSOUTclockisderivedfromtheinternalreferenceclock andtheFLLisdisabled.TheICSLCLKwillbenotbeavailableforBDCcommunications,andtheinternal reference clock is enabled. MC9S08SH8MCUSeriesDataSheet,Rev.3 158 Freescale Semiconductor

Chapter 10 Internal Clock Source (S08ICSV2) 10.4.1.5 FLL Bypassed External (FBE) The FLL bypassed external (FBE) mode is entered when all the following conditions occur: • CLKS bits are written to 10. • IREFS bit is written to 0. • BDM mode is active or LP bit is written to 0. InFLLbypassedexternalmode,theICSOUTclockisderivedfromtheexternalreferenceclock.TheFLL clockiscontrolledbytheexternalreferenceclock,andtheFLLloopwilllocktheFLLfrequencyto1024 times the reference frequency, as selected by the RDIV bits, so that the ICSLCLK will be available for BDC communications, and the external reference clock is enabled. 10.4.1.6 FLL Bypassed External Low Power (FBELP) TheFLLbypassedexternallowpower(FBELP)modeisenteredwhenallthefollowingconditionsoccur: • CLKS bits are written to 10. • IREFS bit is written to 0. • BDM mode is not active and LP bit is written to 1. InFLLbypassedexternallowpowermode,theICSOUTclockisderivedfromtheexternalreferenceclock and the FLL is disabled. The ICSLCLK will be not be available for BDC communications. The external reference clock is enabled. 10.4.1.7 Stop StopmodeisenteredwhenevertheMCUentersaSTOPstate.Inthismode,allICSclocksignalsarestatic except in the following cases: ICSIRCLK will be active in stop mode when all the following conditions occur: • IRCLKEN bit is written to 1 • IREFSTEN bit is written to 1 ICSERCLK will be active in stop mode when all the following conditions occur: • ERCLKEN bit is written to 1 • EREFSTEN bit is written to 1 10.4.2 Mode Switching WhenswitchingbetweenFLLengagedinternal(FEI)andFLLengagedexternal(FEE)modestheIREFS bit can be changed at anytime, but the RDIV bits must be changed simultaneously so that the resulting frequencystaysintherangeof31.25kHzto39.0625kHz.AfterachangeintheIREFSvaluetheFLLwill beginlockingagainafterafewfullcyclesoftheresultingdividedreferencefrequency.Thecompletionof the switch is shown by the IREFST bit. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 159

Chapter 10 Internal Clock Source (S08ICSV2) TheCLKSbitscanalsobechangedatanytime,buttheRDIVbitsmustbechangedsimultaneouslysothat the resulting frequency stays in the range of 31.25 kHz to 39.0625 kHz. The actual switch to the newly selected clock will not occur until after a few full cycles of the new clock. If the newly selected clock is not available, the previous clock will remain selected. 10.4.3 Bus Frequency Divider The BDIV bits can be changed at anytime and the actual switch to the new frequency will occur immediately. 10.4.4 Low Power Bit Usage Thelowpowerbit(LP)isprovidedtoallowtheFLLtobedisabledandthusconservepowerwhenitisnot being used. However, in some applications it may be desirable to enable the FLL and allow it to lock for maximum accuracy before switching to an FLL engaged mode. Do this by writing the LP bit to 0. 10.4.5 Internal Reference Clock WhenIRCLKENissettheinternalreferenceclocksignalwillbepresentedasICSIRCLK,whichcanbe used as an additional clock source. The ICSIRCLK frequency can be re-targeted by trimming the period oftheinternalreferenceclock.ThiscanbedonebywritinganewvaluetotheTRIMbitsintheICSTRM register. Writing a larger value will slow down the ICSIRCLK frequency, and writing a smaller value to the ICSTRM register will speed up the ICSIRCLK frequency. The TRIM bits will effect the ICSOUT frequency if the ICS is in FLL engaged internal (FEI), FLL bypassed internal (FBI), or FLL bypassed internal low power (FBILP) mode. The TRIM and FTRIM value will not be affected by a reset. UntilICSIRCLKistrimmed,programminglowreferencedivider(RDIV)factorsmayresultinICSOUT frequencies that exceed the maximum chip-level frequency and violate the chip-level clock timing specifications (see theDevice Overview chapter). If IREFSTEN is set and the IRCLKEN bit is written to 1, the internal reference clock will keep running during stop mode in order to provide a fast recovery upon exiting stop. AllMCUdevicesarefactoryprogrammedwithatrimvalueinareservedmemorylocation.Thisvaluecan be copied to the ICSTRM register during reset initialization. The factory trim value does not include the FTRIM bit. For finer precision, the user can trim the internal oscillator in the application and set the FTRIM bit accordingly. 10.4.6 Optional External Reference Clock The ICS module can support an external reference clock with frequencies between 31.25 kHz to 5 MHz in all modes. When the ERCLKEN is set, the external reference clock signal will be presented as ICSERCLK, which can be used as an additional clock source. When IREFS = 1, the external reference clockwillnotbeusedbytheFLLandwillonlybeusedasICSERCLK.Inthesemodes,thefrequencycan be equal to the maximum frequency the chip-level timing specifications will support (see the Device Overview chapter). MC9S08SH8MCUSeriesDataSheet,Rev.3 160 Freescale Semiconductor

Chapter 10 Internal Clock Source (S08ICSV2) IfEREFSTENissetandtheERCLKENbitiswrittento1,theexternalreferenceclockwillkeeprunning during stop mode in order to provide a fast recovery upon exiting stop. 10.4.7 Fixed Frequency Clock TheICSpresentsthedividedFLLreferenceclockasICSFFCLKforuseasanadditionalclocksourcefor peripheral modules. The ICS provides an output signal (ICSFFE) which indicates when the ICS is providingICSOUTfrequenciesfourtimesorgreaterthanthedividedFLLreferenceclock(ICSFFCLK). In FLL Engaged mode (FEI and FEE) this is always true and ICSFFE is always high. In ICS Bypass modes, ICSFFE will get asserted for the following combinations of BDIV and RDIV values: • BDIV=00 (divide by 1), RDIV≥ 010 • BDIV=01 (divide by 2), RDIV≥ 011 • BDIV=10 (divide by 4), RDIV≥ 100 • BDIV=11 (divide by 8), RDIV≥ 101 MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 161

Chapter 10 Internal Clock Source (S08ICSV2) MC9S08SH8MCUSeriesDataSheet,Rev.3 162 Freescale Semiconductor

Chapter 11 Inter-Integrated Circuit (S08IICV2) 11.1 Introduction Theinter-integratedcircuit(IIC)providesamethodofcommunicationbetweenanumberofdevices.The interface is designed to operate up to 100kbps with maximum bus loading and timing. The device is capable of operating at higher baud rates, up to a maximum of clock/20, with reduced bus loading. The maximum communication length and the number of devices that can be connected are limited by a maximum bus capacitance of 400 pF. NOTE TheSDAandSCLshouldnotbedrivenaboveV .Thesepinsarepsuedo DD open-drain containing a protection diode to V . DD 11.1.1 Module Configuratio TheIICmodulepins,SDAandSCLcanberepositionedundersoftwarecontrolusingIICPSinSOPT1as asshowninTable11-1.IICPSinSOPT1selectswhichgeneral-purposeI/OportsareassociatedwithIIC operation. Table11-1. IIC Position Options IICPS in SOPT1 Port Pin for SDA Port Pin for SCL 0 (default) PTA2 PTA3 1 PTB6 PTB7 Figure11-1 shows the MC9S08SH8 block diagram with the IIC module highlighted. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 163

Chapter11 Inter-Integrated Circuit (S08IICV2) BKGD/MS IRQ HCS08 CORE DEBUG MODULE (DBG) CPU BDC 8-BIT MODULO TIMER TCLK HCS08 SYSTEM CONTROL MODULE (MTIM) PTA5/IRQ/TCLK/RESET PTA4/ACMPO/BKGD/MS RESETS AND INTERRUPTS A MODES OF OPERATION SCL T PTA3/PAI3/SCL/ADP3 POWER MANAGEMENT IIC MODULE (IIC) SDA POR PTA2/PAI2/SDA/ADP2 COP IRQ LVD SS PTA1/PIA1/TPM2CH0/ADP1/ACMP– PTA0/PIA0/TPM1CH0/ADP0/ACMP+ MISO SERIAL PERIPHERAL MOSI INTERFACE MODULE (SPI) USER FLASH SPSCK (MC9S08SH8 =8,192 BYTES) PTB7/SCL/EXTAL (MC9S08SH4 =4096 BYTES) PTB6/SDA/XTAL SERIAL COMMUNICATIONS RxD SEE NOTE 1 INTERFACE MODULE (SCI) TxD PTB5/TPM1CH1/SS USER RAM (MC9S08SH8 =512 BYTES) TCLK T B PTB4/TPM2CH1/MISO (MC9S08SH4 =256 BYTES) 16-BIT TIMER/PWM TPM1CH0 OR PTB3/PIB3/MOSI/ADP7 P MODULE (TPM1) TPM1CH1 PTB2/PIB2/SPSCK/ADP6 REAL-TIME COUNTER (RTC) TCLK PTB1/PIB1/TxD/ADP5 16-BIT TIMER/PWM TPM2CH0 PTB0/PIB0/RxD/ADP4 40-MHz INTERNAL CLOCK SOURCE (ICS) MODULE (TPM2) TPM2CH1 SEE NOTE 1, 2 PTC3/ADP11 LOW31-P.2O5W kHEzR t oO S38C.I4L LkHATzOR EXTAL T C PTC2/ADP10 R 1 MHz to 16 MHz XTAL O PTC1/TPM1CH1/ADP9 (XOSC) P PTC0/TPM1CH0/ADP8 ACMPO SEE NOTE3 ANALOG COMPARATOR ACMP– (ACMP) ACMP+ V DD VOLTAGE REGULATOR VSS 10-BIT ADP11-ADP0 ANALOG-TO-DIGITAL V CONVERTER (ADC) DDA V SSA VREFH NOTES V REFL = Pin can be enabled as part of the ganged output drive feature NOTE1: Port B not available on 8-pinpackages NOTE2: Port C not available on 8-pin or 16-pin packages NOTE 3: V /V and V /V , are double bonded to V and V respectively. DDA REFH SSA REFL DD SS Figure11-1.MC9S08SH8 Block Diagram Highlighting theIIC Module MC9S08SH8MCUSeriesDataSheet,Rev.3 164 Freescale Semiconductor

Chapter 11 Inter-Integrated Circuit (S08IICV2) 11.1.2 Features The IIC includes these distinctive features: • Compatible with IIC bus standard • Multi-master operation • Software programmable for one of 64 different serial clock frequencies • Software selectable acknowledge bit • Interrupt driven byte-by-byte data transfer • Arbitration lost interrupt with automatic mode switching from master to slave • Calling address identification interrupt • Start and stop signal generation/detection • Repeated start signal generation • Acknowledge bit generation/detection • Bus busy detection • General call recognition • 10-bit address extension 11.1.3 Modes of Operation A brief description of the IIC in the various MCU modes is given here. • Run mode — This is the basic mode of operation. To conserve power in this mode, disable the module. • Wait mode — The module continues to operate while the MCU is in wait mode and can provide a wake-up interrupt. • Stop mode — The IIC is inactive in stop3 mode for reduced power consumption. The stop instruction does not affect IIC register states. Stop2 resets the register contents. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 165

Chapter 11 Inter-Integrated Circuit (S08IICV2) 11.1.4 Block Diagram Figure11-2 is a block diagram of the IIC. Address Data Bus Interrupt ADDR_DECODE DATA_MUX CTRL_REG FREQ_REG ADDR_REG STATUS_REG DATA_REG Input Sync In/Out Start Data Stop Shift Arbitration Register Control Clock Control Address Compare SCL SDA Figure11-2. IIC Functional Block Diagram 11.2 External Signal Description This section describes each user-accessible pin signal. 11.2.1 SCL — Serial Clock Line The bidirectional SCL is the serial clock line of the IIC system. 11.2.2 SDA — Serial Data Line The bidirectional SDA is the serial data line of the IIC system. 11.3 Register Definitio This section consists of the IIC register descriptions in address order. MC9S08SH8MCUSeriesDataSheet,Rev.3 166 Freescale Semiconductor

Chapter 11 Inter-Integrated Circuit (S08IICV2) Refertothedirect-pageregistersummaryinthememorychapterofthisdocumentfortheabsoluteaddress assignments for all IIC registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 11.3.1 IIC Address Register (IICA) 7 6 5 4 3 2 1 0 R 0 AD7 AD6 AD5 AD4 AD3 AD2 AD1 W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure11-3. IIC Address Register (IICA) Table11-2. IICA Field Descriptions Field Description 7–1 SlaveAddress.TheAD[7:1]fieldcontainstheslaveaddresstobeusedbytheIICmodule.Thisfieldisusedon AD[7:1] the 7-bit address scheme and the lower seven bits of the 10-bit address scheme. 11.3.2 IIC Frequency Divider Register (IICF) 7 6 5 4 3 2 1 0 R MULT ICR W Reset 0 0 0 0 0 0 0 0 Figure11-4. IIC Frequency Divider Register (IICF) MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 167

Chapter 11 Inter-Integrated Circuit (S08IICV2) Table11-3. IICF Field Descriptions Field Description 7–6 IIC Multiplier Factor. The MULT bits define the multiplier factor, mul. This factor, along with the SCL divider, MULT generates the IIC baud rate. The multiplier factor mul as defined by the MULT bits is provided below. 00 mul = 01 01 mul = 02 10 mul = 04 11 Reserved 5–0 IICClockRate.TheICRbitsareusedtoprescalethebusclockforbitrateselection.ThesebitsandtheMULT ICR bits determine the IIC baud rate, the SDA hold time, the SCL Start hold time, and the SCL Stop hold time. Table11-5 provides the SCL divider and hold values for corresponding values of the ICR. The SCL divider multiplied by multiplier factor mul generates IIC baud rate. bus speed (Hz) IIC baud rate = --------------------------------------------- Eqn.11-1 mul×SCLdivider SDA hold time is the delay from the falling edge of SCL (IIC clock) to the changing of SDA (IIC data). SDA hold time = bus period (s)× mul× SDA hold value Eqn.11-2 SCLstartholdtimeisthedelayfromthefallingedgeofSDA(IICdata)whileSCLishigh(Startcondition)tothe falling edge of SCL (IIC clock). SCL Start hold time = bus period (s)× mul × SCL Start hold value Eqn.11-3 SCL stop hold time is the delay from the rising edge of SCL (IIC clock) to the rising edge of SDA SDA (IIC data) while SCL is high (Stop condition). SCL Stop hold time = bus period (s)× mul× SCL Stop hold value Eqn.11-4 Forexample,ifthebusspeedis8MHz,thetablebelowshowsthepossibleholdtimevalueswithdifferent ICR and MULT selections to achieve an IIC baud rate of 100kbps. Table11-4. Hold Time Values for 8 MHz Bus Speed Hold Times (μs) MULT ICR SDA SCL Start SCL Stop 0x2 0x00 3.500 3.000 5.500 0x1 0x07 2.500 4.000 5.250 0x1 0x0B 2.250 4.000 5.250 0x0 0x14 2.125 4.250 5.125 0x0 0x18 1.125 4.750 5.125 MC9S08SH8MCUSeriesDataSheet,Rev.3 168 Freescale Semiconductor

Chapter 11 Inter-Integrated Circuit (S08IICV2) Table11-5. IIC Divider and Hold Values SCL Hold SDA Hold SCL Hold SCL Hold ICR SCL SDA Hold ICR SCL SDAHold (Start) (Stop) (Start) (Stop) (hex) Divider Value (hex) Divider Value Value Value Value Value 00 20 7 6 11 20 160 17 78 81 01 22 7 7 12 21 192 17 94 97 02 24 8 8 13 22 224 33 110 113 03 26 8 9 14 23 256 33 126 129 04 28 9 10 15 24 288 49 142 145 05 30 9 11 16 25 320 49 158 161 06 34 10 13 18 26 384 65 190 193 07 40 10 16 21 27 480 65 238 241 08 28 7 10 15 28 320 33 158 161 09 32 7 12 17 29 384 33 190 193 0A 36 9 14 19 2A 448 65 222 225 0B 40 9 16 21 2B 512 65 254 257 0C 44 11 18 23 2C 576 97 286 289 0D 48 11 20 25 2D 640 97 318 321 0E 56 13 24 29 2E 768 129 382 385 0F 68 13 30 35 2F 960 129 478 481 10 48 9 18 25 30 640 65 318 321 11 56 9 22 29 31 768 65 382 385 12 64 13 26 33 32 896 129 446 449 13 72 13 30 37 33 1024 129 510 513 14 80 17 34 41 34 1152 193 574 577 15 88 17 38 45 35 1280 193 638 641 16 104 21 46 53 36 1536 257 766 769 17 128 21 58 65 37 1920 257 958 961 18 80 9 38 41 38 1280 129 638 641 19 96 9 46 49 39 1536 129 766 769 1A 112 17 54 57 3A 1792 257 894 897 1B 128 17 62 65 3B 2048 257 1022 1025 1C 144 25 70 73 3C 2304 385 1150 1153 1D 160 25 78 81 3D 2560 385 1278 1281 1E 192 33 94 97 3E 3072 513 1534 1537 1F 240 33 118 121 3F 3840 513 1918 1921 MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 169

Chapter 11 Inter-Integrated Circuit (S08IICV2) 11.3.3 IIC Control Register (IICC1) 7 6 5 4 3 2 1 0 R 0 0 0 IICEN IICIE MST TX TXAK W RSTA Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure11-5. IIC Control Register (IICC1) Table11-6. IICC1 Field Descriptions Field Description 7 IIC Enable. The IICEN bit determines whether the IIC module is enabled. IICEN 0 IIC is not enabled 1 IIC is enabled 6 IIC Interrupt Enable. The IICIE bit determines whether an IIC interrupt is requested. IICIE 0 IIC interrupt request not enabled 1 IIC interrupt request enabled 5 Master Mode Select. The MST bit changes from a 0 to a 1 when a start signal is generated on the bus and MST master mode is selected. When this bit changes from a 1 to a 0 a stop signal is generated and the mode of operation changes from master to slave. 0 Slave mode 1 Master mode 4 Transmit Mode Select. The TX bit selects the direction of master and slave transfers. In master mode, this bit TX should be set according to the type of transfer required. Therefore, for address cycles, this bit is always high. When addressed as a slave, this bit should be set by software according to the SRW bit in the status register. 0 Receive 1 Transmit 3 Transmit Acknowledge Enable. This bit specifies the value driven onto the SDA during data acknowledge TXAK cycles for master and slave receivers. 0 An acknowledge signal is sent out to the bus after receiving one data byte 1 No acknowledge signal response is sent 2 Repeat start. Writing a 1 to this bit generates a repeated start condition provided it is the current master. This RSTA bit is always read as cleared. Attempting a repeat at the wrong time results in loss of arbitration. MC9S08SH8MCUSeriesDataSheet,Rev.3 170 Freescale Semiconductor

Chapter 11 Inter-Integrated Circuit (S08IICV2) 11.3.4 IIC Status Register (IICS) 7 6 5 4 3 2 1 0 R TCF BUSY 0 SRW RXAK IAAS ARBL IICIF W Reset 1 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure11-6. IIC Status Register (IICS) Table11-7. IICS Field Descriptions Field Description 7 Transfer Complete Flag. This bit is set on the completion of a byte transfer. This bit is only valid during or TCF immediatelyfollowingatransfertotheIICmoduleorfromtheIICmodule.TheTCFbitisclearedbyreadingthe IICD register in receive mode or writing to the IICD in transmit mode. 0 Transfer in progress 1 Transfer complete 6 Addressed as a Slave. The IAAS bit is set when the calling address matches the programmed slave address IAAS or when the GCAEN bit is set and a general call is received. Writing the IICC register clears this bit. 0 Not addressed 1 Addressed as a slave 5 Bus Busy. The BUSY bit indicates the status of the bus regardless of slave or master mode. The BUSY bit is BUSY set when a start signal is detected and cleared when a stop signal is detected. 0 Bus is idle 1 Bus is busy 4 ArbitrationLost.Thisbitissetbyhardwarewhenthearbitrationprocedureislost.TheARBLbitmustbecleared ARBL by software by writing a 1 to it. 0 Standard bus operation 1 Loss of arbitration 2 SlaveRead/Write.Whenaddressedasaslave,theSRWbitindicatesthevalueoftheR/Wcommandbitofthe SRW calling address sent to the master. 0 Slave receive, master writing to slave 1 Slave transmit, master reading from slave 1 IIC Interrupt Flag. The IICIF bit is set when an interrupt is pending. This bit must be cleared by software, by IICIF writing a 1 to it in the interrupt routine. One of the following events can set the IICIF bit: • One byte transfer completes • Match of slave address to calling address • Arbitration lost 0 No interrupt pending 1 Interrupt pending 0 ReceiveAcknowledge.WhentheRXAKbitislow,itindicatesanacknowledgesignalhasbeenreceivedafter RXAK thecompletionofonebyteofdatatransmissiononthebus.IftheRXAKbitishighitmeansthatnoacknowledge signal is detected. 0 Acknowledge received 1 No acknowledge received MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 171

Chapter 11 Inter-Integrated Circuit (S08IICV2) 11.3.5 IIC Data I/O Register (IICD) 7 6 5 4 3 2 1 0 R DATA W Reset 0 0 0 0 0 0 0 0 Figure11-7. IIC Data I/O Register (IICD) Table11-8. IICD Field Descriptions Field Description 7–0 Data—Inmastertransmitmode,whendataiswrittentotheIICD,adatatransferisinitiated.Themostsignificant DATA bit is sent first. In master receive mode, reading this register initiates receiving of the next byte of data. NOTE When transitioning out of master receive mode, the IIC mode should be switched before reading the IICD register to prevent an inadvertent initiation of a master receive data transfer. In slave mode, the same functions are available after an address match has occurred. The TX bit in IICC must correctly reflect the desired direction of transfer in master and slave modes for thetransmissiontobegin.Forinstance,iftheIICisconfiguredformastertransmitbutamasterreceiveis desired, reading the IICD does not initiate the receive. Reading the IICD returns the last byte received while the IIC is configured in master receive or slave receive modes. The IICD does not reflect every byte transmitted on the IIC bus, nor can software verify that a byte has been written to the IICD correctly by reading it back. Inmastertransmitmode,thefirstbyteofdatawrittentoIICDfollowingassertionofMSTisusedforthe addresstransferandshouldcompriseofthecallingaddress(inbit7tobit1)concatenatedwiththerequired R/W bit (in position bit 0). 11.3.6 IIC Control Register 2 (IICC2) 7 6 5 4 3 2 1 0 R 0 0 0 GCAEN ADEXT AD10 AD9 AD8 W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure11-8. IIC Control Register (IICC2) MC9S08SH8MCUSeriesDataSheet,Rev.3 172 Freescale Semiconductor

Chapter 11 Inter-Integrated Circuit (S08IICV2) Table11-9. IICC2 Field Descriptions Field Description 7 General Call Address Enable. The GCAEN bit enables or disables general call address. GCAEN 0 General call address is disabled 1 General call address is enabled 6 Address Extension. The ADEXT bit controls the number of bits used for the slave address. ADEXT 0 7-bit address scheme 1 10-bit address scheme 2–0 Slave Address. The AD[10:8] field contains the upper three bits of the slave address in the 10-bit address AD[10:8] scheme. This field is only valid when the ADEXT bit is set. 11.4 Functional Description This section provides a complete functional description of the IIC module. 11.4.1 IIC Protocol TheIICbussystemusesaserialdataline(SDA)andaserialclockline(SCL)fordatatransfer.Alldevices connectedtoitmusthaveopendrainoropencollectoroutputs.AlogicANDfunctionisexercisedonboth lines with external pull-up resistors. The value of these resistors is system dependent. Normally, a standard communication is composed of four parts: • Start signal • Slave address transmission • Data transfer • Stop signal ThestopsignalshouldnotbeconfusedwiththeCPUstopinstruction.TheIICbussystemcommunication is described briefly in the following sections and illustrated in Figure11-9. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 173

Chapter 11 Inter-Integrated Circuit (S08IICV2) msb lsb msb lsb SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 SDA AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W XXX D7 D6 D5 D4 D3 D2 D1 D0 Start Calling Address Read/ Ack Data Byte No Stop Signal Write Bit Ack Signal Bit msb lsb msb lsb SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 SDA AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W XX AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W Start Calling Address Read/ Ack Repeated New Calling Address Read/ No Stop Signal Write Bit Start Write Ack Signal Signal Bit Figure11-9. IIC Bus Transmission Signals 11.4.1.1 Start Signal When the bus is free, no master device is engaging the bus (SCL and SDA lines are at logical high), a master may initiate communication by sending a start signal. As shown in Figure11-9, a start signal is definedasahigh-to-lowtransitionofSDAwhileSCLishigh.Thissignaldenotesthebeginningofanew data transfer (each data transfer may contain several bytes of data) and brings all slaves out of their idle states. 11.4.1.2 Slave Address Transmission The first byte of data transferred immediately after the start signal is the slave address transmitted by the master. This is a seven-bit calling address followed by a R/W bit. The R/W bit tells the slave the desired direction of data transfer. 1 = Read transfer, the slave transmits data to the master. 0 = Write transfer, the master transmits data to the slave. Onlytheslavewithacallingaddressthatmatchestheonetransmittedbythemasterrespondsbysending back an acknowledge bit. This is done by pulling the SDA low at the ninth clock (see Figure11-9). Notwoslavesinthesystemmayhavethesameaddress.IftheIICmoduleisthemaster,itmustnottransmit anaddressequaltoitsownslaveaddress.TheIICcannotbemasterandslaveatthesametime.However, ifarbitrationislostduringanaddresscycle,theIICrevertstoslavemodeandoperatescorrectlyevenifit is being addressed by another master. MC9S08SH8MCUSeriesDataSheet,Rev.3 174 Freescale Semiconductor

Chapter 11 Inter-Integrated Circuit (S08IICV2) 11.4.1.3 Data Transfer Before successful slave addressing is achieved, the data transfer can proceed byte-by-byte in a direction specified by the R/W bit sent by the calling master. Alltransfersthatcomeafteranaddresscyclearereferredtoasdatatransfers,eveniftheycarrysub-address information for the slave device Each data byte is 8 bits long. Data may be changed only while SCL is low and must be held stable while SCL is high as shown in Figure11-9. There is one clock pulse on SCL for each data bit, the msb being transferred first. Each data byte is followed by a 9th (acknowledge) bit, which is signalled from the receivingdevice.AnacknowledgeissignalledbypullingtheSDAlowattheninthclock.Insummary,one complete data transfer needs nine clock pulses. Iftheslavereceiverdoesnotacknowledgethemasterintheninthbittime,theSDAlinemustbelefthigh by the slave. The master interprets the failed acknowledge as an unsuccessful data transfer. Ifthemasterreceiverdoesnotacknowledgetheslavetransmitterafteradatabytetransmission,theslave interprets this as an end of data transfer and releases the SDA line. In either case, the data transfer is aborted and the master does one of two things: • Relinquishes the bus by generating a stop signal. • Commences a new calling by generating a repeated start signal. 11.4.1.4 Stop Signal The master can terminate the communication by generating a stop signal to free the bus. However, the master may generate a start signal followed by a calling command without generating a stop signal first. This is called repeated start. A stop signal is defined as a low-to-high transition of SDA while SCL at logical 1 (seeFigure11-9). The master can generate a stop even if the slave has generated an acknowledge at which point the slave must release the bus. 11.4.1.5 Repeated Start Signal As shown inFigure11-9, a repeated start signal is a start signal generated without first generating a stop signal to terminate the communication. This is used by the master to communicate with another slave or with the same slave in different mode (transmit/receive mode) without releasing the bus. 11.4.1.6 Arbitration Procedure The IIC bus is a true multi-master bus that allows more than one master to be connected on it. If two or moremasterstrytocontrolthebusatthesametime,aclocksynchronizationproceduredeterminesthebus clock,forwhichthelowperiodisequaltothelongestclocklowperiodandthehighisequaltotheshortest oneamongthemasters.Therelativepriorityofthecontendingmastersisdeterminedbyadataarbitration procedure,abusmasterlosesarbitrationifittransmitslogic1whileanothermastertransmitslogic0.The losing masters immediately switch over to slave receive mode and stop driving SDA output. In this case, MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 175

Chapter 11 Inter-Integrated Circuit (S08IICV2) thetransitionfrommastertoslavemodedoesnotgenerateastopcondition.Meanwhile,astatusbitisset by hardware to indicate loss of arbitration. 11.4.1.7 Clock Synchronization Becausewire-ANDlogicisperformedontheSCLline,ahigh-to-lowtransitionontheSCLlineaffectsall thedevicesconnectedonthebus.Thedevicesstartcountingtheirlowperiodandafteradevice’sclockhas gone low, it holds the SCL line low until the clock high state is reached. However, the change of low to highinthisdeviceclockmaynotchangethestateoftheSCLlineifanotherdeviceclockisstillwithinits low period. Therefore, synchronized clock SCL is held low by the device with the longest low period. Devices with shorter low periods enter a high wait state during this time (seeFigure11-10). When all devices concerned have counted off their low period, the synchronized clock SCL line is released and pulledhigh.ThereisthennodifferencebetweenthedeviceclocksandthestateoftheSCLlineandallthe devices start counting their high periods. The first device to complete its high period pulls the SCL line low again. Delay Start Counting High Period SCL1 SCL2 SCL Internal Counter Reset Figure11-10. IIC Clock Synchronization 11.4.1.8 Handshaking Theclocksynchronizationmechanismcanbeusedasahandshakeindatatransfer.Slavedevicesmayhold theSCLlowaftercompletionofonebytetransfer(9bits).Insuchacase,ithaltsthebusclockandforces the master clock into wait states until the slave releases the SCL line. 11.4.1.9 Clock Stretching Theclocksynchronizationmechanismcanbeusedbyslavestoslowdownthebitrateofatransfer.After the master has driven SCL low the slave can drive SCL low for the required period and then release it. If theslaveSCLlowperiodisgreaterthanthemasterSCLlowperiodthentheresultingSCLbussignallow period is stretched. MC9S08SH8MCUSeriesDataSheet,Rev.3 176 Freescale Semiconductor

Chapter 11 Inter-Integrated Circuit (S08IICV2) 11.4.2 10-bit Address For10-bitaddressing,0x11110isusedforthefirst5bitsofthefirstaddressbyte.Variouscombinationsof read/write formats are possible within a transfer that includes 10-bit addressing. 11.4.2.1 Master-Transmitter Addresses a Slave-Receiver The transfer direction is not changed (seeTable11-10). When a 10-bit address follows a start condition, each slave compares the first seven bits of the first byte of the slave address (11110XX) with its own address and tests whether the eighth bit (R/W direction bit) is 0. More than one device can find a match and generate an acknowledge (A1). Then, each slave that finds a match compares the eight bits of the second byte of the slave address with its own address. Only one slave finds a match and generates an acknowledge(A2).Thematchingslaveremainsaddressedbythemasteruntilitreceivesastopcondition (P) or a repeated start condition (Sr) followed by a different slave address. Slave Address 1st 7 bits R/W Slave Address 2nd byte S A1 A2 Data A ... Data A/A P 11110 + AD10 + AD9 0 AD[8:1] Table11-10. Master-Transmitter Addresses Slave-Receiver with a 10-bit Address After the master-transmitter has sent the first byte of the 10-bit address, the slave-receiver sees an IIC interrupt. Software must ensure the contents of IICD are ignored and not treated as valid data for this interrupt. 11.4.2.2 Master-Receiver Addresses a Slave-Transmitter The transfer direction is changed after the second R/W bit (seeTable11-11). Up to and including acknowledge bit A2, the procedure is the same as that described for a master-transmitter addressing a slave-receiver. After the repeated start condition (Sr), a matching slave remembers that it was addressed before. This slave then checks whether the first seven bits of the first byte of the slave address following Srarethesameastheywereafterthestartcondition(S)andtestswhethertheeighth(R/W)bitis1.Ifthere isamatch,theslaveconsidersthatithasbeenaddressedasatransmitterandgeneratesacknowledgeA3. Theslave-transmitterremainsaddresseduntilitreceivesastopcondition(P)orarepeatedstartcondition (Sr) followed by a different slave address. Afterarepeatedstartcondition(Sr),allotherslavedevicesalsocomparethefirstsevenbitsofthefirstbyte of the slave address with their own addresses and test the eighth (R/W) bit. However, none of them are addressedbecauseR/W=1(for10-bitdevices)orthe11110XXslaveaddress(for7-bitdevices)doesnot match. Slave Address Slave Address Slave Address R/W R/W S 1st 7 bits A1 2nd byte A2 Sr 1st 7 bits A3 Data A ... Data A P 11110 + AD10 + AD9 0 AD[8:1] 11110+AD10+AD9 1 Table11-11. Master-Receiver Addresses a Slave-Transmitter with a 10-bit Address After the master-receiver has sent the first byte of the 10-bit address, the slave-transmitter sees an IIC interrupt. Software must ensure the contents of IICD are ignored and not treated as valid data for this interrupt. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 177

Chapter 11 Inter-Integrated Circuit (S08IICV2) 11.4.3 General Call Address Generalcallscanberequestedin7-bitaddressor10-bitaddress.IftheGCAENbitisset,theIICmatches thegeneralcalladdressaswellasitsownslaveaddress.WhentheIICrespondstoageneralcall,itactsas aslave-receiverandtheIAASbitissetaftertheaddresscycle.SoftwaremustreadtheIICDregisterafter thefirstbytetransfertodeterminewhethertheaddressmatchesisitsownslaveaddressorageneralcall. Ifthevalueis00,thematchisageneralcall.IftheGCAENbitisclear,theIICignoresanydatasupplied from a general call address by not issuing an acknowledgement. 11.5 Resets The IIC is disabled after reset. The IIC cannot cause an MCU reset. 11.6 Interrupts The IIC generates a single interrupt. AninterruptfromtheIICisgeneratedwhenanyoftheeventsinTable11-12occur,providedtheIICIEbit isset.TheinterruptisdrivenbybitIICIF(oftheIICstatusregister)andmaskedwithbitIICIE(oftheIIC controlregister).TheIICIFbitmustbeclearedbysoftwarebywritinga1toitintheinterruptroutine.You can determine the interrupt type by reading the status register. Table11-12. Interrupt Summary Interrupt Source Status Flag Local Enable Complete 1-byte transfer TCF IICIF IICIE Match of received calling address IAAS IICIF IICIE Arbitration Lost ARBL IICIF IICIE 11.6.1 Byte Transfer Interrupt TheTCF(transfercompleteflag)bitissetatthefallingedgeoftheninthclocktoindicatethecompletion of byte transfer. 11.6.2 Address Detect Interrupt When the calling address matches the programmed slave address (IIC address register) or when the GCAEN bit is set and a general call is received, the IAAS bit in the status register is set. The CPU is interrupted,providedtheIICIEisset.TheCPUmustchecktheSRWbitandsetitsTxmodeaccordingly. 11.6.3 Arbitration Lost Interrupt TheIICisatruemulti-masterbusthatallowsmorethanonemastertobeconnectedonit.Iftwoormore masterstrytocontrolthebusatthesametime,therelativepriorityofthecontendingmastersisdetermined by a data arbitration procedure. The IIC module asserts this interrupt when it loses the data arbitration process and the ARBL bit in the status register is set. MC9S08SH8MCUSeriesDataSheet,Rev.3 178 Freescale Semiconductor

Chapter 11 Inter-Integrated Circuit (S08IICV2) Arbitration is lost in the following circumstances: • SDA sampled as a low when the master drives a high during an address or data transmit cycle. • SDAsampledasalowwhenthemasterdrivesahighduringtheacknowledgebitofadatareceive cycle. • A start cycle is attempted when the bus is busy. • A repeated start cycle is requested in slave mode. • A stop condition is detected when the master did not request it. This bit must be cleared by software writing a 1 to it. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 179

Chapter 11 Inter-Integrated Circuit (S08IICV2) 11.7 Initialization/Application Information Module Initialization (Slave) 1. Write: IICC2 — to enable or disable general call — to select 10-bit or 7-bit addressing mode 2. Write: IICA — to set the slave address 3. Write: IICC1 — to enable IIC and interrupts 4. Initialize RAM variables (IICEN = 1 and IICIE = 1) for transmit data 5. Initialize RAM variables used to achieve the routine shown inFigure11-12 Module Initialization (Master) 1. Write: IICF — to set the IIC baud rate (example provided in this chapter) 2. Write: IICC1 — to enable IIC and interrupts 3. Initialize RAM variables (IICEN = 1 and IICIE = 1) for transmit data 4. Initialize RAM variables used to achieve the routine shown inFigure11-12 5. Write: IICC1 — to enable TX 6. Write: IICC1 — to enable MST (master mode) 7. Write: IICD — with the address of the target slave. (The lsb of this byte determines whether the communication is master receive or transmit.) Module Use TheroutineshowninFigure11-12canhandlebothmasterandslaveIICoperations.Forslaveoperation,an incoming IIC message that contains the proper address begins IIC communication. For master operation, communication must be initiated by writing to the IICD register. Register Model IICA AD[7:1] 0 When addressed as a slave (in slave mode), the module responds to this address IICF MULT ICR Baud rate = BUSCLK / (2 x MULT x (SCL DIVIDER)) IICC1 IICEN IICIE MST TX TXAK RSTA 0 0 Module configuration IICS TCF IAAS BUSY ARBL 0 SRW IICIF RXAK Module status flags IICD DATA Data register; Write to transmit IIC data read to read IIC data IICC2 GCAEN ADEXT 0 0 0 AD10 AD9 AD8 Address configuration Figure11-11. IIC Module Quick Start MC9S08SH8MCUSeriesDataSheet,Rev.3 180 Freescale Semiconductor

Chapter 11 Inter-Integrated Circuit (S08IICV2) Clear IICIF Y Master N Mode ? TX Tx/Rx RX Y Arbitration Lost ? ? N Last Byte Transmitted Y Clear ARBL ? N RXAK=0 N Byte tLoa Bset Read Y N IAAS=1 Y IAAS=1 ? ? ? ? Y N Y N Address Transfer Data Transfer See Note 1 See Note 2 Y Y AdEdnr dC oyfcle Y Byte2 tnod B Lea sRtead (Read) SRW=1 TX/RX RX (Mast?er Rx) ? ? ? N N N(Write) TX Write Next Generate Set TX Y ACK from Set TXACK =1 Stop Signal Receiver Byte to IICD Mode (MST = 0) ? N Read Data Write Data Tx Next from IICD to IICD Byte and Store Switch to Set RX Switch to Rx Mode Mode Rx Mode Generate Read Data Dummy Read Dummy Read Dummy Read Stop Signal from IICD from IICD from IICD from IICD (MST = 0) and Store RTI NOTES: 1. If general call is enabled, a check must be done to determine whether the received address was a general call address (0x00). If the received address was a general call address, then the general call must be handled by user software. 2. When10-bitaddressingisusedtoaddressaslave,theslaveseesaninterruptfollowingthefirstbyteoftheextendedaddress.Usersoftwaremustensurethatfor this interrupt, the contents of IICD are ignored and not treated as a valid data transfer Figure11-12. Typical IIC Interrupt Routine MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 181

Chapter 11 Inter-Integrated Circuit (S08IICV2) MC9S08SH8MCUSeriesDataSheet,Rev.3 182 Freescale Semiconductor

Chapter 12 Modulo Timer (S08MTIMV1) 12.1 Introduction The MTIM is a simple 8-bit timer with several software selectable clock sources and a programmable interrupt. ThecentralcomponentoftheMTIMisthe8-bitcounter,whichcanoperateasafree-runningcounterora modulocounter.Atimeroverflowinterruptcanbeenabledtogenerateperiodicinterruptsfortime-based software loops. Figure12-1 shows the MC9S08SH8 block diagram with the MTIMmodulehighlighted. 12.1.1 MTIM Configuration In ormation TheexternalclockfortheMTIMmodule,TCLK,isselectedbysettingCLKS=1:1or1:0inMTIMCLK, which selects the TCLK pin input. The TCLK input on PTA0 can be enabled as external clock inputs to both MTIM and TPM modules simultaneously. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 183

Chapter12 Modulo Timer (S08MTIMV1) BKGD/MS IRQ HCS08 CORE DEBUG MODULE (DBG) CPU BDC 8-BIT MODULO TIMER TCLK HCS08 SYSTEM CONTROL MODULE (MTIM) PTA5/IRQ/TCLK/RESET PTA4/ACMPO/BKGD/MS RESETS AND INTERRUPTS A MODES OF OPERATION SCL T PTA3/PAI3/SCL/ADP3 POWER MANAGEMENT IIC MODULE (IIC) SDA POR PTA2/PAI2/SDA/ADP2 COP IRQ LVD SS PTA1/PIA1/TPM2CH0/ADP1/ACMP– PTA0/PIA0/TPM1CH0/ADP0/ACMP+ MISO SERIAL PERIPHERAL MOSI INTERFACE MODULE (SPI) USER FLASH SPSCK (MC9S08SH8 =8,192 BYTES) PTB7/SCL/EXTAL (MC9S08SH4 =4096 BYTES) PTB6/SDA/XTAL SERIAL COMMUNICATIONS RxD SEE NOTE 1 INTERFACE MODULE (SCI) TxD PTB5/TPM1CH1/SS USER RAM (MC9S08SH8 =512 BYTES) TCLK T B PTB4/TPM2CH1/MISO (MC9S08SH4 =256 BYTES) 16-BIT TIMER/PWM TPM1CH0 OR PTB3/PIB3/MOSI/ADP7 P MODULE (TPM1) TPM1CH1 PTB2/PIB2/SPSCK/ADP6 REAL-TIME COUNTER (RTC) TCLK PTB1/PIB1/TxD/ADP5 16-BIT TIMER/PWM TPM2CH0 PTB0/PIB0/RxD/ADP4 40-MHz INTERNAL CLOCK SOURCE (ICS) MODULE (TPM2) TPM2CH1 SEE NOTE 1, 2 PTC3/ADP11 LOW31-P.2O5W kHEzR t oO S38C.I4L LkHATzOR EXTAL T C PTC2/ADP10 R 1 MHz to 16 MHz XTAL O PTC1/TPM1CH1/ADP9 (XOSC) P PTC0/TPM1CH0/ADP8 ACMPO SEE NOTE3 ANALOG COMPARATOR ACMP– (ACMP) ACMP+ V DD VOLTAGE REGULATOR VSS 10-BIT ADP11-ADP0 ANALOG-TO-DIGITAL V CONVERTER (ADC) DDA V SSA VREFH NOTES V REFL = Pin can be enabled as part of the ganged output drive feature NOTE1: Port B not available on 8-pinpackages NOTE2: Port C not available on 8-pin or 16-pin packages NOTE 3: V /V and V /V , are double bonded to V and V respectively. DDA REFH SSA REFL DD SS Figure12-1.MC9S08SH8 Block Diagram Highlighting theMTIM Module MC9S08SH8MCUSeriesDataSheet,Rev.3 184 Freescale Semiconductor

Chapter 12 Modulo Timer (S08MTIMV1) 12.1.2 Features Timer system features include: • 8-bit up-counter — Free-running or 8-bit modulo limit — Software controllable interrupt on overflow — Counter reset bit (TRST) — Counter stop bit (TSTP) • Four software selectable clock sources for input to prescaler: — System bus clock — rising edge — Fixed frequency clock (XCLK) — rising edge — External clock source on the TCLK pin — rising edge — External clock source on the TCLK pin — falling edge • Nine selectable clock prescale values: — Clock source divide by 1, 2, 4, 8, 16, 32, 64, 128, or 256 12.1.3 Modes of Operation This section defines the MTIM’s operation in stop, wait and background debug modes. 12.1.3.1 MTIM in Wait Mode TheMTIMcontinuestoruninwaitmodeifenabledbeforeexecutingtheWAITinstruction.Therefore,the MTIMcanbeusedtobringtheMCUoutofwaitmodeifthetimeroverflowinterruptisenabled.Forlowest possible current consumption, the MTIM should be stopped by software if not needed as an interrupt source during wait mode. 12.1.3.2 MTIM in Stop Modes TheMTIMisdisabledinallstopmodes,regardlessofthesettingsbeforeexecutingtheSTOPinstruction. Therefore, the MTIM cannot be used as a wake up source from stop modes. Waking from stop1 and stop2 modes, the MTIM will be put into its reset state. If stop3 is exited with a reset, the MTIM will be put into its reset state. If stop3 is exited with an interrupt, the MTIM continues from the state it was in when stop3 was entered. If the counter was active upon entering stop3, the count will resume from the current value. 12.1.3.3 MTIM in Active Background Mode The MTIM suspends all counting until the microcontroller returns to normal user operating mode. CountingresumesfromthesuspendedvalueaslongasanMTIMresetdidnotoccur(TRSTwrittentoa1 or MTIMMOD written). MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 185

Chapter 12 Modulo Timer (S08MTIMV1) 12.1.4 Block Diagram The block diagram for the modulo timer module is shown Figure12-2. BUSCLK CLOCK PRESCALE 8-BIT COUNTER TRST XCLK SOURCE ANDSELECT (MTIMCNT) TSTP TCLK SYNC SELECT DIVIDE BY 8-BIT COMPARATOR CLKS PS MTIM INTERRUPT REQUEST 8-BIT MODULO TOIE TOF (MTIMMOD) REG set_tof_pulse Figure12-2. Modulo Timer (MTIM) Block Diagram 12.2 External Signal Description The MTIM includes one external signal, TCLK, used to input an external clock when selected as the MTIM clock source. The signal properties of TCLK are shown in Table12-1. Table12-1. Signal Properties Signal Function I/O TCLK External clock source input into MTIM I TheTCLKinputmustbesynchronizedbythebusclock.Also,variationsindutycycleandclockjittermust be accommodated. Therefore, the TCLK signal must be limited to one-fourth of the bus frequency. The TCLK pin can be muxed with a general-purpose port pin. See the Pins and Connections chapter for the pin location and priority of this function. MC9S08SH8MCUSeriesDataSheet,Rev.3 186 Freescale Semiconductor

Chapter 12 Modulo Timer (S08MTIMV1) 12.3 Register Definitio Figure12-3 is a summary of MTIM registers. Name 7 6 5 4 3 2 1 0 R TOF 0 0 0 0 0 MTIMSC TOIE TSTP W TRST R 0 0 MTIMCLK CLKS PS W R COUNT MTIMCNT W R MTIMMOD MOD W Figure12-3.MTIM Register Summary Each MTIM includes four registers: • An 8-bit status and control register • An 8-bit clock configuration register • An 8-bit counter register • An 8-bit modulo register Refertothedirect-pageregistersummaryintheMemorychapterofthisdatasheetfortheabsoluteaddress assignmentsforallMTIMregisters.Thissectionreferstoregistersandcontrolbitsonlybytheirnamesand relative address offsets. SomeMCUsmayhavemorethanoneMTIM,soregisternamesincludeplaceholdercharacterstoidentify which MTIM is being referenced. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 187

Chapter 12 Modulo Timer (S08MTIMV1) 12.3.1 MTIM Status and Control Register (MTIMSC) MTIMSCcontainstheoverflowstatusflagandcontrolbitswhichareusedtoconfiguretheinterruptenable, reset the counter, and stop the counter. 7 6 5 4 3 2 1 0 R TOF 0 0 0 0 0 TOIE TSTP W TRST Reset: 0 0 0 1 0 0 0 0 Figure12-4. MTIM Status and Control Register Table12-2. MTIM Status and Control Register Field Descriptions Field Description 7 MTIMOverfl wFlag—Thisread-onlybitissetwhentheMTIMcounterregisteroverflowsto$00afterreaching TOF the value in the MTIM modulo register. Clear TOF by reading the MTIMSC register while TOF is set, then writing a0toTOF.TOFisalsoclearedwhenTRSTiswrittentoa1orwhenanyvalueiswrittentotheMTIMMODregister. 0 MTIM counter has not reached the overflow value in the MTIM modulo register. 1 MTIM counter has reached the overflow value in the MTIM modulo register. 6 MTIMOverfl wInterruptEnable—Thisread/writebitenablesMTIMoverflowinterrupts.IfTOIEisset,thenan TOIE interruptisgeneratedwhenTOF=1.ResetclearsTOIE.DonotsetTOIEifTOF=1.ClearTOFfirst,thensetTOIE. 0 TOF interrupts are disabled. Use software polling. 1 TOF interrupts are enabled. 5 MTIMCounterReset—Whena1iswrittentothiswrite-onlybit,theMTIMcounterregisterresetsto$00andTOF TRST is cleared. Reading this bit always returns 0. 0 No effect. MTIM counter remains at current state. 1 MTIM counter is reset to $00. 4 MTIMCounterStop—Whenset,thisread/writebitstopstheMTIMcounteratitscurrentvalue.Countingresumes TSTP from the current value when TSTP is cleared. Reset sets TSTP to prevent the MTIM from counting. 0 MTIM counter is active. 1 MTIM counter is stopped. 3:0 Unused register bits, always read 0. MC9S08SH8MCUSeriesDataSheet,Rev.3 188 Freescale Semiconductor

Chapter 12 Modulo Timer (S08MTIMV1) 12.3.2 MTIM Clock Configuration Register (MTIMCLK MTIMCLK contains the clock select bits (CLKS) and the prescaler select bits (PS). 7 6 5 4 3 2 1 0 R 0 0 CLKS PS W Reset: 0 0 0 0 0 0 0 0 Figure12-5. MTIM Clock Configuration Registe Table12-3. MTIM Clock Configuration Register Field Descriptio Field Description 7:6 Unused register bits, always read 0. 5:4 Clock Source Select — These two read/write bits select one of four different clock sources as the input to the CLKS MTIM prescaler. Changing the clock source while the counter is active does not clear the counter. The count continues with the new clock source. Reset clears CLKS to 000. 00 Encoding 0. Bus clock (BUSCLK) 01 Encoding 1. Fixed-frequency clock (XCLK) 10 Encoding 3. External source (TCLK pin), falling edge 11 Encoding 4. External source (TCLK pin), rising edge All other encodings default to the bus clock (BUSCLK). 3:0 Clock Source Prescaler — These four read/write bits select one of nine outputs from the 8-bit prescaler. PS Changingtheprescalervaluewhilethecounterisactivedoesnotclearthecounter.Thecountcontinueswiththe new prescaler value. Reset clears PS to 0000. 0000 Encoding 0. MTIM clock source÷ 1 0001 Encoding 1. MTIM clock source÷ 2 0010 Encoding 2. MTIM clock source÷ 4 0011 Encoding 3. MTIM clock source÷ 8 0100 Encoding 4. MTIM clock source÷ 16 0101 Encoding 5. MTIM clock source÷ 32 0110 Encoding 6. MTIM clock source÷ 64 0111 Encoding 7. MTIM clock source÷ 128 1000 Encoding 8. MTIM clock source÷ 256 All other encodings default to MTIM clock source÷ 256. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 189

Chapter 12 Modulo Timer (S08MTIMV1) 12.3.3 MTIM Counter Register (MTIMCNT) MTIMCNT is the read-only value of the current MTIM count of the 8-bit counter. 7 6 5 4 3 2 1 0 R COUNT W Reset: 0 0 0 0 0 0 0 0 Figure12-6. MTIM Counter Register Table12-4. MTIM Counter Register Field Description Field Description 7:0 MTIMCount—Theseeightread-onlybitscontainthecurrentvalueofthe8-bitcounter.Writeshavenoeffectto COUNT this register. Reset clears the count to $00. 12.3.4 MTIM Modulo Register (MTIMMOD) 7 6 5 4 3 2 1 0 R MOD W Reset: 0 0 0 0 0 0 0 0 Figure12-7. MTIM Modulo Register Table12-5.MTIM Modulo Register Field Descriptions Field Description 7:0 MTIMModulo—Theseeightread/writebitscontainthemodulovalueusedtoresetthecountandsetTOF.Avalue MOD of$00putstheMTIMinfree-runningmode.WritingtoMTIMMODresetstheCOUNTto$00andclearsTOF.Reset sets the modulo to $00. MC9S08SH8MCUSeriesDataSheet,Rev.3 190 Freescale Semiconductor

Chapter 12 Modulo Timer (S08MTIMV1) 12.4 Functional Description TheMTIMiscomposedofamain8-bitup-counterwithan8-bitmoduloregister,aclocksourceselector, andaprescalerblockwithnineselectablevalues.Themodulealsocontainssoftwareselectableinterrupt logic. TheMTIMcounter(MTIMCNT)hasthreemodesofoperation:stopped,free-running,andmodulo.Outof reset, the counter is stopped. If the counter is started without writing a new value to the modulo register, thenthecounterwillbeinfree-runningmode.Thecounterisinmodulomodewhenavalueotherthan$00 is in the modulo register while the counter is running. AfteranyMCUreset,thecounterisstoppedandresetto$00,andthemodulusissetto$00.Thebusclock is selected as the default clock source and the prescale value is divide by 1. To start the MTIM in free-running mode, simply write to the MTIM status and control register (MTIMSC) and clear the MTIM stop bit (TSTP). Fourclocksourcesaresoftwareselectable:theinternalbusclock,thefixedfrequencyclock(XCLK),and anexternalclockontheTCLKpin,selectableasincrementingoneitherrisingorfallingedges.TheMTIM clockselectbits(CLKS1:CLKS0)inMTIMSCareusedtoselectthedesiredclocksource.Ifthecounteris active (TSTP = 0) when a new clock source is selected, the counter will continue counting from the previous value using the new clock source. Nine prescale values are software selectable: clock source divided by 1, 2, 4, 8, 16, 32, 64, 128, or 256. The prescaler select bits (PS[3:0]) inMTIMSC select the desired prescale value. If the counter is active (TSTP=0)whenanewprescalervalueisselected,thecounterwillcontinuecountingfromtheprevious value using the new prescaler value. The MTIM modulo register (MTIMMOD) allows the overflow compare value to be set to any value from $01 to $FF. Reset clears the modulo value to $00, which results in a free running counter. Whenthecounterisactive(TSTP=0),thecounterincrementsattheselectedrateuntilthecountmatches the modulo value. When these values match, the counter overflows to $00 and continues counting. The MTIMoverflowflag(TOF)issetwheneverthecounteroverflows.Theflagsetsonthetransitionfromthe modulovalueto$00.WritingtoMTIMMODwhilethecounterisactiveresetsthecounterto$00andclears TOF. Clearing TOF is a two-step process. The first step is to read the MTIMSC register while TOF is set. The second step is to write a 0 to TOF. If another overflow occurs between the first and second steps, the clearingprocessisresetandTOFwillremainsetafterthesecondstepisperformed.Thiswillpreventthe secondoccurrencefrombeingmissed.TOFisalsoclearedwhena1iswrittentoTRSTorwhenanyvalue is written to theMTIMMOD register. The MTIM allows for an optional interrupt to be generated whenever TOF is set. To enable the MTIM overflowinterrupt,settheMTIMoverflowinterruptenablebit(TOIE)in MTIMSC.TOIEshouldneverbe written to a 1 while TOF = 1. Instead, TOF should be cleared first, then the TOIE can be set to 1. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 191

Chapter 12 Modulo Timer (S08MTIMV1) 12.4.1 MTIM Operation Example This section shows an example of the MTIM operation as the counter reaches a matching value from the modulo register. selected clock source MTIM clock (PS=%0010) MTIMCNT $A7 $A8 $A9 $AA $00 $01 TOF MTIMMOD: $AA Figure12-8. MTIM counter overfl w example In the example ofFigure12-8, the selected clock source could be any of the five possible choices. The prescalerissettoPS=%0010ordivide-by-4.ThemodulovalueintheMTIMMODregisterissetto$AA. When the counter,MTIMCNT, reaches the modulo value of $AA, the counter overflows to $00 and continuescounting.Thetimeroverflowflag,TOF,setswhenthecountervaluechangesfrom$AAto$00. An MTIM overflow interrupt is generated when TOF is set, if TOIE = 1. MC9S08SH8MCUSeriesDataSheet,Rev.3 192 Freescale Semiconductor

Chapter 13 Real-Time Counter (S08RTCV1) 13.1 Introduction The RTC module consists of one 8-bit counter, one 8-bit comparator, several binary-based and decimal-based prescaler dividers, two clock sources, and one programmable periodic interrupt. This modulecanbeusedfortime-of-day,calendaroranytaskschedulingfunctions.Itcanalsoserveasacyclic wake up from low power modes without the need of external components. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 193

Chapter13 Real-Time Counter (S08RTCV1) BKGD/MS IRQ HCS08 CORE DEBUG MODULE (DBG) CPU BDC 8-BIT MODULO TIMER TCLK HCS08 SYSTEM CONTROL MODULE (MTIM) PTA5/IRQ/TCLK/RESET PTA4/ACMPO/BKGD/MS RESETS AND INTERRUPTS A MODES OF OPERATION SCL T PTA3/PAI3/SCL/ADP3 POWER MANAGEMENT IIC MODULE (IIC) SDA POR PTA2/PAI2/SDA/ADP2 COP IRQ LVD SS PTA1/PIA1/TPM2CH0/ADP1/ACMP– PTA0/PIA0/TPM1CH0/ADP0/ACMP+ MISO SERIAL PERIPHERAL MOSI INTERFACE MODULE (SPI) USER FLASH SPSCK (MC9S08SH8 =8,192 BYTES) PTB7/SCL/EXTAL (MC9S08SH4 =4096 BYTES) PTB6/SDA/XTAL SERIAL COMMUNICATIONS RxD SEE NOTE 1 INTERFACE MODULE (SCI) TxD PTB5/TPM1CH1/SS USER RAM (MC9S08SH8 =512 BYTES) TCLK T B PTB4/TPM2CH1/MISO (MC9S08SH4 =256 BYTES) 16-BIT TIMER/PWM TPM1CH0 OR PTB3/PIB3/MOSI/ADP7 P MODULE (TPM1) TPM1CH1 PTB2/PIB2/SPSCK/ADP6 REAL-TIME COUNTER (RTC) TCLK PTB1/PIB1/TxD/ADP5 16-BIT TIMER/PWM TPM2CH0 PTB0/PIB0/RxD/ADP4 40-MHz INTERNAL CLOCK SOURCE (ICS) MODULE (TPM2) TPM2CH1 SEE NOTE 1, 2 PTC3/ADP11 LOW31-P.2O5W kHEzR t oO S38C.I4L LkHATzOR EXTAL T C PTC2/ADP10 R 1 MHz to 16 MHz XTAL O PTC1/TPM1CH1/ADP9 (XOSC) P PTC0/TPM1CH0/ADP8 ACMPO SEE NOTE3 ANALOG COMPARATOR ACMP– (ACMP) ACMP+ V DD VOLTAGE REGULATOR VSS 10-BIT ADP11-ADP0 ANALOG-TO-DIGITAL V CONVERTER (ADC) DDA V SSA VREFH NOTES V REFL = Pin can be enabled as part of the ganged output drive feature NOTE1: Port B not available on 8-pinpackages NOTE2: Port C not available on 8-pin or 16-pin packages NOTE 3: V /V and V /V , are double bonded to V and V respectively. DDA REFH SSA REFL DD SS Figure13-1.MC9S08SH8 Block Diagram Highlighting theRTC Module MC9S08SH8MCUSeriesDataSheet,Rev.3 194 Freescale Semiconductor

Chapter 13 Real-Time Counter (S08RTCV1) 13.1.1 Features Features of the RTC module include: • 8-bit up-counter — 8-bit modulo match limit — Software controllable periodic interrupt on match • Three software selectable clock sources for input to prescaler with selectable binary-based and decimal-based divider values — 1-kHz internal low-power oscillator (LPO) — External clock (ERCLK) — 32-kHz internal clock (IRCLK) 13.1.2 Modes of Operation This section defines the operation in stop, wait and background debug modes. 13.1.2.1 Wait Mode TheRTCcontinuestoruninwaitmodeifenabledbeforeexecutingtheappropriateinstruction.Therefore, the RTC can bring the MCU out of wait mode if the real-time interrupt is enabled. For lowest possible current consumption, the RTC should be stopped by software if not needed as an interrupt source during wait mode. 13.1.2.2 Stop Modes The RTC continues to run in stop2 or stop3 mode if the RTC is enabled before executing the STOP instruction.Therefore,theRTCcanbringtheMCUoutofstopmodeswithnoexternalcomponents,ifthe real-time interrupt is enabled. The LPO clock can be used in stop2 and stop3 modes. ERCLK and IRCLK clocks are only available in stop3 mode. Power consumption is lower when all clock sources are disabled, but in that case, the real-time interrupt cannot wake up the MCU from stop modes. 13.1.2.3 Active Background Mode TheRTCsuspendsallcountingduringactivebackgroundmodeuntilthemicrocontrollerreturnstonormal useroperatingmode.CountingresumesfromthesuspendedvalueaslongastheRTCMODregisterisnot written and the RTCPS and RTCLKS bits are not altered. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 195

Chapter 13 Real-Time Counter (S08RTCV1) 13.1.3 Block Diagram The block diagram for the RTC module is shown in Figure13-2. LPO Clock Source ERCLK Select IRCLK V 8-Bit Modulo DD (RTCMOD) RTCLKS Background D Q RTIF RTC Mode Interrupt Request RTCLKS[0] RTCPS 8-Bit Comparator E R RTC RTIE Write 1 to Prescaler Clock 8-Bit Counter RTIF Divide-By (RTCCNT) Figure13-2. Real-Time Counter (RTC) Block Diagram 13.2 External Signal Description The RTC does not include any off-chip signals. 13.3 Register Definitio The RTC includes a status and control register, an 8-bit counter register, and an 8-bit modulo register. Refertothedirect-pageregistersummaryinthememorysectionofthisdocumentfortheabsoluteaddress assignmentsforallRTCregisters.Thissectionreferstoregistersandcontrolbitsonlybytheirnamesand relative address offsets. Table13-1 is a summary of RTC registers. Table13-1.RTC Register Summary Name 7 6 5 4 3 2 1 0 R RTCSC RTIF RTCLKS RTIE RTCPS W R RTCCNT RTCCNT W R RTCMOD RTCMOD W MC9S08SH8MCUSeriesDataSheet,Rev.3 196 Freescale Semiconductor

Chapter 13 Real-Time Counter (S08RTCV1) 13.3.1 RTC Status and Control Register (RTCSC) RTCSC contains the real-time interrupt status flag (RTIF), the clock select bits (RTCLKS), the real-time interrupt enable bit (RTIE), and the prescaler select bits (RTCPS). 7 6 5 4 3 2 1 0 R RTIF RTCLKS RTIE RTCPS W Reset: 0 0 0 0 0 0 0 0 Figure13-3. RTC Status and Control Register (RTCSC) Table13-2. RTCSC Field Descriptions Field Description 7 Real-TimeInterruptFlagThisstatusbitindicatestheRTCcounterregisterreachedthevalueintheRTCmodulo RTIF register.Writingalogic0hasnoeffect.Writingalogic1clearsthebitandthereal-timeinterruptrequest.Reset clears RTIF. 0 RTC counter has not reached the value in the RTC modulo register. 1 RTC counter has reached the value in the RTC modulo register. 6–5 Real-Time Clock Source Select. These two read/write bits select the clock source input to the RTC prescaler. RTCLKS ChangingtheclocksourceclearstheprescalerandRTCCNTcounters.Whenselectingaclocksource,ensure that the clock source is properly enabled (if applicable) to ensure correct operation of the RTC. Reset clears RTCLKS. 00 Real-time clock source is the 1-kHz low power oscillator (LPO) 01 Real-time clock source is the external clock (ERCLK) 1x Real-time clock source is the internal clock (IRCLK) 4 Real-Time Interrupt Enable. This read/write bit enables real-time interrupts. If RTIE is set, then an interrupt is RTIE generated when RTIF is set. Reset clears RTIE. 0 Real-time interrupt requests are disabled. Use software polling. 1 Real-time interrupt requests are enabled. 3–0 Real-Time Clock Prescaler Select. These four read/write bits select binary-based or decimal-based divide-by RTCPS values for the clock source. SeeTable13-3. Changing the prescaler value clears the prescaler and RTCCNT counters. Reset clears RTCPS. Table13-3. RTC Prescaler Divide-by values RTCPS RTCLKS[0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 Off 23 25 26 27 28 29 210 1 2 22 10 24 102 5x102 103 1 Off 210 211 212 213 214 215 216 103 2x103 5x103 104 2x104 5x104 105 2x105 MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 197

Chapter 13 Real-Time Counter (S08RTCV1) 13.3.2 RTC Counter Register (RTCCNT) RTCCNT is the read-only value of the current RTC count of the 8-bit counter. 7 6 5 4 3 2 1 0 R RTCCNT W Reset: 0 0 0 0 0 0 0 0 Figure13-4. RTC Counter Register (RTCCNT) Table13-4. RTCCNT Field Descriptions Field Description 7:0 RTCCount.Theseeightread-onlybitscontainthecurrentvalueofthe8-bitcounter.Writeshavenoeffecttothis RTCCNT register. Reset, writing to RTCMOD, or writing different values to RTCLKS and RTCPS clear the count to 0x00. 13.3.3 RTC Modulo Register (RTCMOD) 7 6 5 4 3 2 1 0 R RTCMOD W Reset: 0 0 0 0 0 0 0 0 Figure13-5. RTC Modulo Register (RTCMOD) Table13-5. RTCMOD Field Descriptions Field Description 7:0 RTCModulo.Theseeightread/writebitscontainthemodulovalueusedtoresetthecountto0x00uponacompare RTCMOD match and set the RTIF status bit. A value of 0x00 sets the RTIF bit on each rising edge of the prescaler output. Writing to RTCMOD resets the prescaler and the RTCCNT counters to 0x00. Reset sets the modulo to 0x00. 13.4 Functional Description The RTC is composed of a main 8-bit up-counter with an 8-bit modulo register, a clock source selector, and a prescaler block with binary-based and decimal-based selectable values. The module also contains software selectable interrupt logic. AfteranyMCUreset,thecounterisstoppedandresetto0x00,themodulusregisterissetto0x00,andthe prescaler is off. The 1-kHz internal oscillator clock is selected as the default clock source. To start the prescaler, write any value other than zero to the prescaler select bits (RTCPS). Three clock sources are software selectable: the low power oscillator clock (LPO), the external clock (ERCLK),andtheinternalclock(IRCLK).TheRTCclockselectbits(RTCLKS)selectthedesiredclock source. Ifa different value is written toRTCLKS, the prescaler and RTCCNT counters are reset to 0x00. MC9S08SH8MCUSeriesDataSheet,Rev.3 198 Freescale Semiconductor

Chapter 13 Real-Time Counter (S08RTCV1) RTCPSandtheRTCLKS[0]bitselectthedesireddivide-byvalue.IfadifferentvalueiswrittentoRTCPS, theprescalerandRTCCNTcountersareresetto0x00.Table13-6showsdifferentprescalerperiodvalues. Table13-6. Prescaler Period 1-kHz Internal Clock 1-MHz External Clock 32-kHz Internal Clock 32-kHz Internal Clock RTCPS (RTCLKS = 00) (RTCLKS = 01) (RTCLKS = 10) (RTCLKS = 11) 0000 Off Off Off Off 0001 8 ms 1.024 ms 250μs 32 ms 0010 32 ms 2.048 ms 1 ms 64 ms 0011 64 ms 4.096 ms 2 ms 128 ms 0100 128 ms 8.192 ms 4 ms 256 ms 0101 256 ms 16.4 ms 8 ms 512 ms 0110 512 ms 32.8 ms 16 ms 1.024 s 0111 1.024 s 65.5 ms 32 ms 2.048 s 1000 1 ms 1 ms 31.25μs 31.25 ms 1001 2 ms 2 ms 62.5μs 62.5 ms 1010 4 ms 5 ms 125μs 156.25 ms 1011 10 ms 10 ms 312.5μs 312.5 ms 1100 16 ms 20 ms 0.5 ms 0.625 s 1101 0.1 s 50 ms 3.125 ms 1.5625 s 1110 0.5 s 0.1 s 15.625 ms 3.125 s 1111 1 s 0.2 s 31.25 ms 6.25 s TheRTCmoduloregister(RTCMOD)allowsthecomparevaluetobesettoanyvaluefrom0x00to0xFF. Whenthecounterisactive,thecounterincrementsattheselectedrateuntilthecountmatchesthemodulo value.Whenthesevaluesmatch,thecounterresetsto0x00andcontinuescounting.Thereal-timeinterrupt flag (RTIF) is set when a match occurs. The flag sets on the transition from the modulo value to 0x00. Writing toRTCMOD resets the prescaler and the RTCCNT counters to 0x00. The RTC allows for an interrupt to be generated when RTIF is set. To enable the real-time interrupt, set the real-time interrupt enable bit (RTIE) inRTCSC. RTIF is cleared by writing a 1 to RTIF. 13.4.1 RTC Operation Example This section shows an example of the RTC operation as the counter reaches a matching value from the modulo register. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 199

Chapter 13 Real-Time Counter (S08RTCV1) Internal 1-kHz Clock Source RTC Clock (RTCPS=0xA) RTCCNT 0x52 0x53 0x54 0x55 0x00 0x01 RTIF RTCMOD 0x55 Figure13-6. RTC Counter Overfl w Example IntheexampleofFigure13-6,theselectedclocksourceisthe1-kHzinternaloscillatorclocksource.The prescaler(RTCPS)issetto0xAordivide-by-4.ThemodulovalueintheRTCMODregisterissetto0x55. When the counter, RTCCNT, reaches the modulo value of 0x55, the counter overflows to 0x00 and continuescounting.Thereal-timeinterruptflag,RTIF,setswhenthecountervaluechangesfrom0x55to 0x00. A real-time interrupt is generated when RTIF is set, if RTIE is set. 13.5 Initialization/Application Information Thissectionprovidesexamplecodetogivesomebasicdirectiontoauseronhowtoinitializeandconfigure the RTC module. The example software is implemented in C language. The example below shows how to implement time of day with the RTC using the 1-kHz clock source to achieve the lowest possible power consumption. Because the 1-kHz clock source is not as accurate as a crystal, software can be added for any adjustments. For accuracy without adjustments at the expense of additionalpowerconsumption,theexternalclock(ERCLK)ortheinternalclock(IRCLK)canbeselected with appropriate prescaler and modulo values. /* Initialize the elapsed time counters */ Seconds = 0; Minutes = 0; Hours = 0; Days=0; /* Configure RTC to interrupt every 1 second from 1-kHz clock source */ RTCMOD.byte = 0x00; RTCSC.byte = 0x1F; /********************************************************************** Function Name : RTC_ISR Notes : Interrupt service routine for RTC module. **********************************************************************/ MC9S08SH8MCUSeriesDataSheet,Rev.3 200 Freescale Semiconductor

Chapter 13 Real-Time Counter (S08RTCV1) #pragma TRAP_PROC void RTC_ISR(void) { /* Clear the interrupt flag */ RTCSC.byte = RTCSC.byte | 0x80; /* RTC interrupts every 1 Second */ Seconds++; /* 60 seconds in a minute */ if (Seconds > 59){ Minutes++; Seconds = 0; } /* 60 minutes in an hour */ if (Minutes > 59){ Hours++; Minutes = 0; } /* 24 hours in a day */ if (Hours > 23){ Days ++; Hours = 0; } } MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 201

Chapter 13 Real-Time Counter (S08RTCV1) MC9S08SH8MCUSeriesDataSheet,Rev.3 202 Freescale Semiconductor

Chapter 14 Serial Communications Interface (S08SCIV4) 14.1 Introduction Figure14-1 shows the MC9S08SH8 block diagram with the SCI module highlighted. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 203

Chapter14 Serial Communications Interface (S08SCIV4) BKGD/MS IRQ HCS08 CORE DEBUG MODULE (DBG) CPU BDC 8-BIT MODULO TIMER TCLK HCS08 SYSTEM CONTROL MODULE (MTIM) PTA5/IRQ/TCLK/RESET PTA4/ACMPO/BKGD/MS RESETS AND INTERRUPTS A MODES OF OPERATION SCL T PTA3/PAI3/SCL/ADP3 POWER MANAGEMENT IIC MODULE (IIC) SDA POR PTA2/PAI2/SDA/ADP2 COP IRQ LVD SS PTA1/PIA1/TPM2CH0/ADP1/ACMP– PTA0/PIA0/TPM1CH0/ADP0/ACMP+ MISO SERIAL PERIPHERAL MOSI INTERFACE MODULE (SPI) USER FLASH SPSCK (MC9S08SH8 =8,192 BYTES) PTB7/SCL/EXTAL (MC9S08SH4 =4096 BYTES) PTB6/SDA/XTAL SERIAL COMMUNICATIONS RxD SEE NOTE 1 INTERFACE MODULE (SCI) TxD PTB5/TPM1CH1/SS USER RAM (MC9S08SH8 =512 BYTES) TCLK T B PTB4/TPM2CH1/MISO (MC9S08SH4 =256 BYTES) 16-BIT TIMER/PWM TPM1CH0 OR PTB3/PIB3/MOSI/ADP7 P MODULE (TPM1) TPM1CH1 PTB2/PIB2/SPSCK/ADP6 REAL-TIME COUNTER (RTC) TCLK PTB1/PIB1/TxD/ADP5 16-BIT TIMER/PWM TPM2CH0 PTB0/PIB0/RxD/ADP4 40-MHz INTERNAL CLOCK SOURCE (ICS) MODULE (TPM2) TPM2CH1 SEE NOTE 1, 2 PTC3/ADP11 LOW31-P.2O5W kHEzR t oO S38C.I4L LkHATzOR EXTAL T C PTC2/ADP10 R 1 MHz to 16 MHz XTAL O PTC1/TPM1CH1/ADP9 (XOSC) P PTC0/TPM1CH0/ADP8 ACMPO SEE NOTE3 ANALOG COMPARATOR ACMP– (ACMP) ACMP+ V DD VOLTAGE REGULATOR VSS 10-BIT ADP11-ADP0 ANALOG-TO-DIGITAL V CONVERTER (ADC) DDA V SSA VREFH NOTES V REFL = Pin can be enabled as part of the ganged output drive feature NOTE1: Port B not available on 8-pinpackages NOTE2: Port C not available on 8-pin or 16-pin packages NOTE 3: V /V and V /V , are double bonded to V and V respectively. DDA REFH SSA REFL DD SS Figure14-1.MC9S08SH8 Block Diagram Highlighting theSCI Module MC9S08SH8MCUSeriesDataSheet,Rev.3 204 Freescale Semiconductor

Chapter 14 Serial Communications Interface (S08SCIV4) 14.1.1 Features Features of SCI module include: • Full-duplex, standard non-return-to-zero (NRZ) format • Double-buffered transmitter and receiver with separate enables • Programmable baud rates (13-bit modulo divider) • Interrupt-driven or polled operation: — Transmit data register empty and transmission complete — Receive data register full — Receive overrun, parity error, framing error, and noise error — Idle receiver detect — Active edge on receive pin — Break detect supporting LIN • Hardware parity generation and checking • Programmable 8-bit or 9-bit character length • Receiver wakeup by idle-line or address-mark • Optional 13-bit break character generation / 11-bit break character detection • Selectable transmitter output polarity 14.1.2 Modes of Operation SeeSection14.3, “Functional Description,” For details concerning SCI operation in these modes: • 8- and 9-bit data modes • Stop mode operation • Loop mode • Single-wire mode MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 205

Chapter 14 Serial Communications Interface (S08SCIV4) 14.1.3 Block Diagram Figure14-2 shows the transmitter portion of the SCI. INTERNAL BUS (WRITE-ONLY) LOOPS SCID – Tx BUFFER RSRC LOOP TO RECEIVE 11-BIT TRANSMIT SHIFT REGISTER CONTROL DATA IN M P RT O A T T S S TO TxD PIN 1× BAUD H 8 7 6 5 4 3 2 1 0 L RATE CLOCK B SHIFT DIRECTION S L TXINV D s) PE PTA8RITY D FROM SCIx SHIFT ENABLE REAMBLE (ALL 1 BREAK (ALL 0s) PT GENERATION OA P L SCI CONTROLS TxD TE SBK TO TxD TRANSMIT CONTROL TxD DIRECTION PIN LOGIC TXDIR BRK13 TDRE TIE Tx INTERRUPT TC REQUEST TCIE Figure14-2. SCI Transmitter Block Diagram MC9S08SH8MCUSeriesDataSheet,Rev.3 206 Freescale Semiconductor

Chapter 14 Serial Communications Interface (S08SCIV4) Figure14-3 shows the receiver portion of the SCI. INTERNAL BUS (READ-ONLY) 16× BAUD DIVIDE RATE CLOCK SCID – Rx BUFFER BY 16 FROM TRANSMITTER 11-BIT RECEIVE SHIFT REGISTER LOOPS SINGLE-WIRE M OP B ART RSRC LOOP CONTROL ST LS ST LBKDE H 8 7 6 5 4 3 2 1 0 L FROM RxD PIN s RXINV DATA RECOVERY ALL 1 MSB SHIFT DIRECTION WAKE WAKEUP RWU RWUID LOGIC ILT ACTIVE EDGE DETECT RDRF RIE IDLE ILIE Rx INTERRUPT REQUEST LBKDIF LBKDIE RXEDGIF RXEDGIE OR ORIE FE FEIE ERROR INTERRUPT REQUEST NF NEIE PE PARITY PF CHECKING PT PEIE Figure14-3. SCI Receiver Block Diagram MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 207

Chapter 14 Serial Communications Interface (S08SCIV4) 14.2 Register Definitio The SCI has eight 8-bit registers to control baud rate, select SCI options, report SCI status, and for transmit/receive data. Refertothedirect-pageregistersummaryintheMemorychapterofthisdatasheetfortheabsoluteaddress assignments for all SCI registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 14.2.1 SCI Baud Rate Registers (SCIxBDH, SCIxBDL) ThispairofregisterscontrolstheprescaledivisorforSCIbaudrategeneration.Toupdatethe13-bitbaud ratesetting[SBR12:SBR0],firstwritetoSCIxBDHtobufferthehighhalfofthenewvalueandthenwrite to SCIxBDL. The working value in SCIxBDH does not change until SCIxBDL is written. SCIxBDLisresettoanon-zerovalue,soafterresetthebaudrategeneratorremainsdisableduntilthefirst time the receiver or transmitter is enabled (RE or TE bits in SCIxC2 are written to 1). 7 6 5 4 3 2 1 0 R 0 LBKDIE RXEDGIE SBR12 SBR11 SBR10 SBR9 SBR8 W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure14-4. SCI Baud Rate Register (SCIxBDH) Table14-1. SCIxBDH Field Descriptions Field Description 7 LIN Break Detect Interrupt Enable (for LBKDIF) LBKDIE 0 Hardware interrupts from LBKDIF disabled (use polling). 1 Hardware interrupt requested when LBKDIFflag is 1. 6 RxD Input Active Edge Interrupt Enable (for RXEDGIF) RXEDGIE 0 Hardware interrupts from RXEDGIF disabled (use polling). 1 Hardware interrupt requested when RXEDGIF flag is 1. 4:0 Baud Rate Modulo Divisor — The 13 bits in SBR[12:0] are referred to collectively as BR, and they set the SBR[12:8] modulo divide rate for the SCI baud rate generator. When BR=0, the SCI baud rate generator is disabled to reduce supply current. When BR=1 to 8191, the SCI baud rate=BUSCLK/(16×BR). See also BR bits in Table14-2. MC9S08SH8MCUSeriesDataSheet,Rev.3 208 Freescale Semiconductor

Chapter 14 Serial Communications Interface (S08SCIV4) 7 6 5 4 3 2 1 0 R SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 W Reset 0 0 0 0 0 1 0 0 Figure14-5. SCI Baud Rate Register (SCIxBDL) Table14-2. SCIxBDL Field Descriptions Field Description 7:0 Baud Rate Modulo Divisor — These 13 bits in SBR[12:0] are referred to collectively as BR, and they set the SBR[7:0] modulo divide rate for the SCI baud rate generator. When BR=0, the SCI baud rate generator is disabled to reduce supply current. When BR=1 to 8191, the SCI baud rate=BUSCLK/(16×BR). See also BR bits in Table14-1. 14.2.2 SCI Control Register 1 (SCIxC1) This read/write register is used to control various optional features of the SCI system. 7 6 5 4 3 2 1 0 R LOOPS SCISWAI RSRC M WAKE ILT PE PT W Reset 0 0 0 0 0 0 0 0 Figure14-6. SCI Control Register 1 (SCIxC1) Table14-3. SCIxC1 Field Descriptions Field Description 7 Loop Mode Select — Selects between loop back modes and normal 2-pin full-duplex modes. When LOOPS LOOPS=1, the transmitter output is internally connected to the receiver input. 0 Normal operation — RxD and TxD use separate pins. 1 Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input. (See RSRC bit.) RxD pin is not used by SCI. 6 SCI Stops in Wait Mode SCISWAI 0 SCIclockscontinuetoruninwaitmodesotheSCIcanbethesourceofaninterruptthatwakesuptheCPU. 1 SCI clocks freeze while CPU is in wait mode. 5 Receiver Source Select — This bit has no meaning or effect unless the LOOPS bit is set to 1. When RSRC LOOPS=1, the receiver input is internally connected to the TxD pin and RSRC determines whether this connection is also connected to the transmitter output. 0 Provided LOOPS=1, RSRC=0 selects internal loop back mode and the SCI does not use the RxD pins. 1 Single-wire SCI mode where the TxD pin is connected to the transmitter output and receiver input. 4 9-Bit or 8-Bit Mode Select M 0 Normal — start + 8 data bits (LSB first) + stop. 1 Receiver and transmitter use 9-bit data characters start + 8 data bits (LSB first) + 9th data bit + stop. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 209

Chapter 14 Serial Communications Interface (S08SCIV4) Table14-3. SCIxC1 Field Descriptions (continued) Field Description 3 Receiver Wakeup Method Select — Refer toSection14.3.3.2, “Receiver Wakeup Operation” for more WAKE information. 0 Idle-line wakeup. 1 Address-mark wakeup. 2 Idle Line Type Select — Setting this bit to 1 ensures that the stop bit and logic1 bits at the end of a character ILT do not count toward the 10 or 11 bit times of logic high level needed by the idle line detection logic. Refer to Section14.3.3.2.1, “Idle-Line Wakeup” for more information. 0 Idle character bit count starts after start bit. 1 Idle character bit count starts after stop bit. 1 ParityEnable—Enableshardwareparitygenerationandchecking.Whenparityisenabled,themostsignificant PE bit (MSB) of the data character (eighth or ninth data bit) is treated as the parity bit. 0 No hardware parity generation or checking. 1 Parity enabled. 0 ParityType—Providedparityisenabled(PE=1),thisbitselectsevenoroddparity.Oddparitymeansthetotal PT number of 1s in the data character, including the parity bit, is odd. Even parity means the total number of 1s in the data character, including the parity bit, is even. 0 Even parity. 1 Odd parity. 14.2.3 SCI Control Register 2 (SCIxC2) This register can be read or written at any time. 7 6 5 4 3 2 1 0 R TIE TCIE RIE ILIE TE RE RWU SBK W Reset 0 0 0 0 0 0 0 0 Figure14-7. SCI Control Register 2 (SCIxC2) Table14-4. SCIxC2 Field Descriptions Field Description 7 Transmit Interrupt Enable (for TDRE) TIE 0 Hardware interrupts from TDRE disabled (use polling). 1 Hardware interrupt requested when TDRE flag is 1. 6 Transmission Complete Interrupt Enable (for TC) TCIE 0 Hardware interrupts from TC disabled (use polling). 1 Hardware interrupt requested when TC flag is 1. 5 Receiver Interrupt Enable (for RDRF) RIE 0 Hardware interrupts from RDRF disabled (use polling). 1 Hardware interrupt requested when RDRF flag is 1. 4 Idle Line Interrupt Enable (for IDLE) ILIE 0 Hardware interrupts from IDLE disabled (use polling). 1 Hardware interrupt requested when IDLE flag is 1. MC9S08SH8MCUSeriesDataSheet,Rev.3 210 Freescale Semiconductor

Chapter 14 Serial Communications Interface (S08SCIV4) Table14-4. SCIxC2 Field Descriptions (continued) Field Description 3 Transmitter Enable TE 0 Transmitter off. 1 Transmitter on. TE must be 1 in order to use the SCI transmitter. When TE=1, the SCI forces the TxD pin to act as an output for the SCI system. When the SCI is configured for single-wire operation (LOOPS=RSRC=1), TXDIR controls the direction of traffic on the single SCI communication line (TxD pin). TEalsocanbeusedtoqueueanidlecharacterbywritingTE=0thenTE=1whileatransmissionisinprogress. Refer toSection14.3.2.1, “Send Break and Queued Idle” for more details. WhenTEiswrittento0,thetransmitterkeepscontroloftheportTxDpinuntilanydata,queuedidle,orqueued break character finishes transmitting before allowing the pin to revert to a general-purpose I/O pin. 2 Receiver Enable — When the SCI receiver is off, the RxD pin reverts to being a general-purpose port I/O pin. RE If LOOPS=1 the RxD pin reverts to being a general-purpose I/O pin even if RE=1. 0 Receiver off. 1 Receiver on. 1 Receiver Wakeup Control — This bit can be written to 1 to place the SCI receiver in a standby state where it RWU waits for automatic hardware detection of a selected wakeup condition. The wakeup condition is either an idle linebetweenmessages(WAKE=0,idle-linewakeup),oralogic1inthemostsignificantdatabitinacharacter (WAKE=1, address-mark wakeup). Application software sets RWU and (normally) a selected hardware condition automatically clears RWU. Refer toSection14.3.3.2, “Receiver Wakeup Operation” for more details. 0 Normal SCI receiver operation. 1 SCI receiver in standby waiting for wakeup condition. 0 SendBreak—Writinga1andthena0toSBKqueuesabreakcharacterinthetransmitdatastream.Additional SBK break characters of 10 or 11(13 or 14 if BRK13 = 1) bit times of logic 0 are queued as long as SBK=1. Depending on the timing of the set and clear of SBK relative to the information currently being transmitted, a secondbreakcharactermaybequeuedbeforesoftwareclearsSBK.RefertoSection14.3.2.1,“SendBreakand Queued Idle” for more details. 0 Normal transmitter operation. 1 Queue break character(s) to be sent. 14.2.4 SCI Status Register 1 (SCIxS1) Thisregisterhaseightread-onlystatusflags.Writeshavenoeffect.Specialsoftwaresequences(whichdo not involve writing to this register) are used to clear these status flags. 7 6 5 4 3 2 1 0 R TDRE TC RDRF IDLE OR NF FE PF W Reset 1 1 0 0 0 0 0 0 = Unimplemented or Reserved Figure14-8. SCI Status Register 1 (SCIxS1) MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 211

Chapter 14 Serial Communications Interface (S08SCIV4) Table14-5. SCIxS1 Field Descriptions Field Description 7 TransmitDataRegisterEmptyFlag—TDREissetoutofresetandwhenatransmitdatavaluetransfersfrom TDRE thetransmitdatabuffertothetransmitshifter,leavingroomforanewcharacterinthebuffer.ToclearTDRE,read SCIxS1 with TDRE=1 and then write to the SCI data register (SCIxD). 0 Transmit data register (buffer) full. 1 Transmit data register (buffer) empty. 6 Transmission Complete Flag — TC is set out of reset and when TDRE=1 and no data, preamble, or break TC character is being transmitted. 0 Transmitter active (sending data, a preamble, or a break). 1 Transmitter idle (transmission activity complete). TC is cleared automatically by reading SCIxS1 with TC=1 and then doing one of the following three things: • Write to the SCI data register (SCIxD) to transmit new data • Queue a preamble by changing TE from 0 to 1 • Queue a break character by writing 1 to SBK in SCIxC2 5 ReceiveDataRegisterFullFlag—RDRFbecomessetwhenacharactertransfersfromthereceiveshifterinto RDRF the receive data register (SCIxD). To clear RDRF, read SCIxS1 with RDRF = 1 and then read the SCI data register (SCIxD). 0 Receive data register empty. 1 Receive data register full. 4 Idle Line Flag — IDLE is set when the SCI receive line becomes idle for a full character time after a period of IDLE activity. When ILT=0, the receiver starts counting idle bit times after the start bit. So if the receive character is all 1s, these bit times and the stop bit time count toward the full character time of logic high (10 or 11 bit times dependingontheMcontrolbit)neededforthereceivertodetectanidleline.WhenILT=1,thereceiverdoesn’t start counting idle bit times until after the stop bit. So the stop bit and any logic high bit times at the end of the previouscharacterdonotcounttowardthefullcharactertimeoflogichighneededforthereceivertodetectan idle line. To clear IDLE, read SCIxS1 with IDLE=1 and then read the SCI data register (SCIxD). After IDLE has been cleared,itcannotbecomesetagainuntilafteranewcharacterhasbeenreceivedandRDRFhasbeenset.IDLE will get set only once even if the receive line remains idle for an extended period. 0 No idle line detected. 1 Idle line was detected. 3 ReceiverOverrunFlag—ORissetwhenanewserialcharacterisreadytobetransferredtothereceivedata OR register (buffer), but the previously received character has not been read from SCIxD yet. In this case, the new character(andallassociatederrorinformation)islostbecausethereisnoroomtomoveitintoSCIxD.Toclear OR, read SCIxS1 with OR=1 and then read the SCI data register (SCIxD). 0 No overrun. 1 Receive overrun (new SCI data lost). 2 NoiseFlag—Theadvancedsamplingtechniqueusedinthereceivertakessevensamplesduringthestartbit NF andthreesamplesineachdatabitandthestopbit.Ifanyofthesesamplesdisagreeswiththerestofthesamples within any bit time in the frame, the flag NF will be set at the same time as the flag RDRF gets set for the character. To clear NF, read SCIxS1 and then read the SCI data register (SCIxD). 0 No noise detected. 1 Noise detected in the received character in SCIxD. MC9S08SH8MCUSeriesDataSheet,Rev.3 212 Freescale Semiconductor

Chapter 14 Serial Communications Interface (S08SCIV4) Table14-5. SCIxS1 Field Descriptions (continued) Field Description 1 FramingErrorFlag—FEissetatthesametimeasRDRFwhenthereceiverdetectsalogic0wherethestop FE bit was expected. This suggests the receiver was not properly aligned to a character frame. To clear FE, read SCIxS1 with FE=1 and then read the SCI data register (SCIxD). 0 No framing error detected. This does not guarantee the framing is correct. 1 Framing error. 0 Parity Error Flag — PF is set at the same time as RDRF when parity is enabled (PE=1) and the parity bit in PF the received character does not agree with the expected parity value. To clear PF, read SCIxS1 and then read the SCI data register (SCIxD). 0 No parity error. 1 Parity error. 14.2.5 SCI Status Register 2 (SCIxS2) This register has one read-only status flag. 7 6 5 4 3 2 1 0 R 0 RAF LBKDIF RXEDGIF RXINV RWUID BRK13 LBKDE W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure14-9. SCI Status Register 2 (SCIxS2) Table14-6. SCIxS2 Field Descriptions Field Description 7 LINBreakDetectInterruptFlag—LBKDIFissetwhentheLINbreakdetectcircuitryisenabledandaLINbreak LBKDIF character is detected. LBKDIF is cleared by writing a “1” to it. 0 No LIN break character has been detected. 1 LIN break character has been detected. 6 RxD Pin Active Edge Interrupt Flag — RXEDGIF is set when an active edge (falling if RXINV = 0, rising if RXEDGIF RXINV=1) on the RxD pin occurs. RXEDGIF is cleared by writing a “1” to it. 0 No active edge on the receive pin has occurred. 1 An active edge on the receive pin has occurred. 4 Receive Data Inversion — Setting this bit reverses the polarity of the received data input. RXINV1 0 Receive data not inverted 1 Receive data inverted 3 ReceiveWakeUpIdleDetect—RWUIDcontrolswhethertheidlecharacterthatwakesupthereceiversetsthe RWUID IDLE bit. 0 During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. 1 During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. 2 BreakCharacterGenerationLength—BRK13isusedtoselectalongertransmittedbreakcharacterlength. BRK13 Detection of a framing error is not affected by the state of this bit. 0 Break character is transmitted with length of 10 bit times (11 if M = 1) 1 Break character is transmitted with length of 13 bit times (14 if M = 1) MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 213

Chapter 14 Serial Communications Interface (S08SCIV4) Table14-6. SCIxS2 Field Descriptions (continued) Field Description 1 LIN Break Detection Enable— LBKDE is used to select a longer break character detection length. While LBKDE LBKDE is set, framing error (FE) and receive data register full (RDRF) flags are prevented from setting. 0 Break character is detected at length of 10 bit times (11 if M = 1). 1 Break character is detected at length of 11 bit times (12 if M = 1). 0 ReceiverActiveFlag—RAFissetwhentheSCIreceiverdetectsthebeginningofavalidstartbit,andRAFis RAF cleared automatically when the receiver detects an idle line. This status flag can be used to check whether an SCI character is being received before instructing the MCU to go to stop mode. 0 SCI receiver idle waiting for a start bit. 1 SCI receiver active (RxD input not idle). 1 Setting RXINV inverts the RxD input for all cases: data bits, start and stop bits, break, and idle. WhenusinganinternaloscillatorinaLINsystem,itisnecessarytoraisethebreakdetectionthresholdby one bit time. Under the worst case timing conditions allowed in LIN, it is possible that a 0x00 data charactercanappeartobe10.26bittimeslongataslavewhichisrunning14%fasterthanthemaster.This would trigger normal break detection circuitry which is designed to detect a 10 bit break symbol. When theLBKDEbitisset,framingerrorsareinhibitedandthebreakdetectionthresholdchangesfrom10bits to 11 bits, preventing false detection of a 0x00 data character as a LIN break symbol. 14.2.6 SCI Control Register 3 (SCIxC3) 7 6 5 4 3 2 1 0 R R8 T8 TXDIR TXINV ORIE NEIE FEIE PEIE W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure14-10. SCI Control Register 3 (SCIxC3) Table14-7. SCIxC3 Field Descriptions Field Description 7 Ninth Data Bit for Receiver — When the SCI is configured for 9-bit data (M=1), R8 can be thought of as a R8 ninthreceivedatabittotheleftoftheMSBofthebuffereddataintheSCIxDregister.Whenreading9-bitdata, read R8 before reading SCIxD because reading SCIxD completes automatic flag clearing sequences which could allow R8 and SCIxD to be overwritten with new data. 6 NinthDataBitforTransmitter—WhentheSCIisconfiguredfor9-bitdata(M=1),T8maybethoughtofasa T8 ninthtransmitdatabittotheleftoftheMSBofthedataintheSCIxDregister.Whenwriting9-bitdata,theentire 9-bit value is transferred to the SCI shift register after SCIxD is written so T8 should be written (if it needs to change from its previous value) before SCIxD is written. If T8 does not need to change in the new value (such as when it is used to generate mark or space parity), it need not be written each time SCIxD is written. 5 TxD Pin Direction in Single-Wire Mode — When the SCI is configured for single-wire half-duplex operation TXDIR (LOOPS=RSRC=1), this bit determines the direction of data at the TxD pin. 0 TxD pin is an input in single-wire mode. 1 TxD pin is an output in single-wire mode. MC9S08SH8MCUSeriesDataSheet,Rev.3 214 Freescale Semiconductor

Chapter 14 Serial Communications Interface (S08SCIV4) Table14-7. SCIxC3 Field Descriptions (continued) Field Description 4 Transmit Data Inversion — Setting this bit reverses the polarity of the transmitted data output. TXINV1 0 Transmit data not inverted 1 Transmit data inverted 3 Overrun Interrupt Enable — This bit enables the overrun flag (OR) to generate hardware interrupt requests. ORIE 0 OR interrupts disabled (use polling). 1 Hardware interrupt requested when OR=1. 2 Noise Error Interrupt Enable — This bit enables the noise flag (NF) to generate hardware interrupt requests. NEIE 0 NF interrupts disabled (use polling). 1 Hardware interrupt requested when NF=1. 1 Framing Error Interrupt Enable — This bit enables the framing error flag (FE) to generate hardware interrupt FEIE requests. 0 FE interrupts disabled (use polling). 1 Hardware interrupt requested when FE=1. 0 Parity Error Interrupt Enable — This bit enables the parity error flag (PF) to generate hardware interrupt PEIE requests. 0 PF interrupts disabled (use polling). 1 Hardware interrupt requested when PF=1. 1 Setting TXINV inverts the TxD output for all cases: data bits, start and stop bits, break, and idle. 14.2.7 SCI Data Register (SCIxD) This register is actually two separate registers. Reads return the contents of the read-only receive data buffer and writes go to the write-only transmit data buffer. Reads and writes of this register are also involved in the automatic flag clearing mechanisms for the SCI status flags. 7 6 5 4 3 2 1 0 R R7 R6 R5 R4 R3 R2 R1 R0 W T7 T6 T5 T4 T3 T2 T1 T0 Reset 0 0 0 0 0 0 0 0 Figure14-11. SCI Data Register (SCIxD) 14.3 Functional Description The SCI allows full-duplex, asynchronous, NRZ serial communication among the MCU and remote devices,includingotherMCUs.TheSCIcomprisesabaudrategenerator,transmitter,andreceiverblock. Thetransmitterandreceiveroperateindependently,althoughtheyusethesamebaudrategenerator.During normaloperation,theMCUmonitorsthestatusoftheSCI,writesthedatatobetransmitted,andprocesses received data. The following describes each of the blocks of the SCI. 14.3.1 Baud Rate Generation As shown inFigure14-12, the clock source for the SCI baud rate generator is the bus-rate clock. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 215

Chapter 14 Serial Communications Interface (S08SCIV4) MODULO DIVIDE BY (1 THROUGH 8191) DIVIDE BY BUSCLK SBR12:SBR0 16 Tx BAUD RATE Rx SAMPLING CLOCK BAUD RATE GENERATOR (16× BAUD RATE) OFF IF [SBR12:SBR0] =0 BUSCLK BAUD RATE = [SBR12:SBR0]× 16 Figure14-12. SCI Baud Rate Generation SCI communications require the transmitter and receiver (which typically derive baud rates from independentclocksources)tousethesamebaudrate.Allowedtoleranceonthisbaudfrequencydepends onthedetailsofhowthereceiversynchronizestotheleadingedgeofthestartbitandhowbitsamplingis performed. TheMCUresynchronizestobitboundariesoneveryhigh-to-lowtransition,butintheworstcase,thereare no such transitions in the full 10- or 11-bit time character frame so any mismatch in baud rate is accumulated for the whole character time. For a Freescale Semiconductor SCI system whose bus frequencyisdrivenbyacrystal,theallowedbaudratemismatchisabout 4.5percentfor8-bitdataformat and about 4 percent for 9-bit data format. Although baud rate modulo divider settings do not always produce baud rates that exactly match standard rates, it is normally possible to get within a few percent, which is acceptable for reliable communications. 14.3.2 Transmitter Functional Description This section describes the overall block diagram for the SCI transmitter, as well as specialized functions for sending break and idle characters. The transmitter block diagram is shown in Figure14-2. Thetransmitteroutput(TxD)idlestatedefaultstologichigh(TXINV=0followingreset).Thetransmitter outputisinvertedbysettingTXINV=1.ThetransmitterisenabledbysettingtheTEbitinSCIxC2.This queuesapreamblecharacterthatisonefullcharacterframeoftheidlestate.Thetransmitterthenremains idleuntildataisavailableinthetransmitdatabuffer.Programsstoredataintothetransmitdatabufferby writing to the SCI data register (SCIxD). The central element of the SCI transmitter is the transmit shift register that is either 10 or 11 bits long depending on the setting in the M control bit. For the remainder of this section, we will assume M=0, selectingthenormal8-bitdatamode.In8-bitdatamode,theshiftregisterholdsastartbit,eightdatabits, and a stop bit. When the transmit shift register is available for a new SCI character, the value waiting in thetransmitdataregisteristransferredtotheshiftregister(synchronizedwiththebaudrateclock)andthe transmit data register empty (TDRE) status flag is set to indicate another character may be written to the transmit data buffer at SCIxD. If no new character is waiting in the transmit data buffer after a stop bit is shifted out the TxD pin, the transmitter sets the transmit complete flag and enters an idle mode, with TxD high, waiting for more characters to transmit. MC9S08SH8MCUSeriesDataSheet,Rev.3 216 Freescale Semiconductor

Chapter 14 Serial Communications Interface (S08SCIV4) Writing0toTEdoesnotimmediatelyreleasethepintobeageneral-purposeI/Opin.Anytransmitactivity that is in progress must first be completed. This includes data characters in progress, queued idle characters, and queued break characters. 14.3.2.1 Send Break and Queued Idle The SBK control bit in SCIxC2 is used to send break characters which were originally used to gain the attention of old teletype receivers. Break characters are a full character time of logic 0 (10 bit times including the start and stop bits). A longer break of 13 bit times can be enabled by setting BRK13 = 1. Normally, a program would wait for TDRE to become set to indicate the last character of a message has moved to the transmit shifter, then write 1 and then write 0 to the SBK bit. This action queues a break charactertobesentassoonastheshifterisavailable.IfSBKisstill1whenthequeuedbreakmovesinto theshifter(synchronizedtothebaudrateclock),anadditionalbreakcharacterisqueued.Ifthereceiving deviceisanotherFreescaleSemiconductorSCI,thebreakcharacterswillbereceivedas0sinalleightdata bits and a framing error (FE=1) occurs. Whenidle-linewakeupisused,afullcharactertimeofidle(logic1)isneededbetweenmessagestowake up any sleeping receivers. Normally, a program would wait for TDRE to become set to indicate the last characterofamessagehasmovedtothetransmitshifter,thenwrite0andthenwrite1totheTEbit.This actionqueuesanidlecharactertobesentassoonastheshifterisavailable.Aslongasthecharacterinthe shifterdoesnotfinishwhileTE=0,theSCItransmitterneveractuallyreleasescontroloftheTxDpin.If there is a possibility of the shifter finishing while TE =0, set the general-purpose I/O controls so the pin thatissharedwithTxDisanoutputdrivingalogic1.ThisensuresthattheTxDlinewilllooklikeanormal idle line even if the SCI loses control of the port pin between writing 0 and then 1 to TE. The length of the break character is affected by the BRK13 and M bits as shown below. Table14-8. Break Character Length BRK13 M Break Character Length 0 0 10 bit times 0 1 11 bit times 1 0 13 bit times 1 1 14 bit times 14.3.3 Receiver Functional Description In this section, the receiver block diagram (Figure14-3) is used as a guide for the overall receiver functionaldescription.Next,thedatasamplingtechniqueusedtoreconstructreceiverdataisdescribedin more detail. Finally, two variations of the receiver wakeup function are explained. The receiver input is inverted by setting RXINV = 1. The receiver is enabled by setting the RE bit in SCIxC2. Character frames consist of a start bit of logic 0, eight (or nine) data bits (LSB first), and a stop bitoflogic1.Forinformationabout9-bitdatamode,refertoSection14.3.5.1,“8-and9-BitDataModes.” For the remainder of this discussion, we assume the SCI is configured for normal 8-bit data mode. Afterreceivingthestopbitintothereceiveshifter,andprovidedthereceivedataregisterisnotalreadyfull, thedatacharacteristransferredtothereceivedataregisterandthereceivedataregisterfull(RDRF)status MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 217

Chapter 14 Serial Communications Interface (S08SCIV4) flagisset.IfRDRFwasalreadysetindicatingthereceivedataregister(buffer)wasalreadyfull,theoverrun (OR) status flag is set and the new data is lost. Because the SCI receiver is double-buffered, the program hasonefullcharactertimeafterRDRFissetbeforethedatainthereceivedatabuffermustbereadtoavoid a receiver overrun. Whenaprogramdetectsthatthereceivedataregisterisfull(RDRF=1),itgetsthedatafromthereceive data register by reading SCIxD. The RDRF flag is cleared automatically by a 2-step sequence which is normally satisfied in the course of the user’s program that handles receive data. Refer to Section14.3.4, “Interrupts and Status Flags” for more details about flag clearing. 14.3.3.1 Data Sampling Technique TheSCIreceiverusesa16×baudrateclockforsampling.Thereceiverstartsbytakinglogiclevelsamples at 16 times the baud rate to search for a falling edge on the RxD serial data input pin. A falling edge is defined as a logic 0 sample after three consecutive logic 1 samples. The 16× baud rate clock is used to dividethebittimeinto16segmentslabeledRT1throughRT16.Whenafallingedgeislocated,threemore samples are taken at RT3, RT5, and RT7 to make sure this was a real start bit and not merely noise. If at least two of these three samples are 0, the receiver assumes it is synchronized to a receive character. The receiver then samples each bit time, including the start and stop bits, at RT8, RT9, and RT10 to determinethelogiclevelforthatbit.Thelogiclevelisinterpretedtobethatofthemajorityofthesamples takenduringthebittime.Inthecaseofthestartbit,thebitisassumedtobe0ifatleasttwoofthesamples at RT3, RT5, and RT7 are 0 even if one or all of the samples taken at RT8, RT9, and RT10 are 1s. If any sample in any bit time (including the start and stop bits) in a character frame fails to agree with the logic level for that bit, the noise flag (NF) will be set when the received character is transferred to the receive data buffer. Thefallingedgedetectionlogiccontinuouslylooksforfallingedges,andifanedgeisdetected,thesample clock is resynchronized to bit times. This improves the reliability of the receiver in the presence of noise or mismatched baud rates. It does not improve worst case analysis because some characters do not have any extra falling edges anywhere in the character frame. Inthecaseofaframingerror,providedthereceivedcharacterwasnotabreakcharacter,thesamplinglogic that searches for a falling edge is filled with three logic 1 samples so that a new start bit can be detected almost immediately. Inthecaseofaframingerror,thereceiverisinhibitedfromreceivinganynewcharactersuntiltheframing error flag is cleared. The receive shift register continues to function, but a complete character cannot transfer to the receive data buffer if FE is still set. 14.3.3.2 Receiver Wakeup Operation Receiver wakeup is a hardware mechanism that allows an SCI receiver to ignore the characters in a message that is intended for a different SCI receiver. In such a system, all receivers evaluate the first character(s) of each message, and as soon as they determine the message is intended for a different receiver, they write logic 1 to the receiver wake up (RWU) control bit in SCIxC2. When RWU bit is set, thestatusflagsassociatedwiththereceiver(withtheexceptionoftheidlebit,IDLE,whenRWUIDbitis set) are inhibited from setting, thus eliminating the software overhead for handling the unimportant MC9S08SH8MCUSeriesDataSheet,Rev.3 218 Freescale Semiconductor

Chapter 14 Serial Communications Interface (S08SCIV4) message characters. At the end of a message, or at the beginning of the next message, all receivers automatically force RWU to 0 so all receivers wake up in time to look at the first character(s) of the next message. 14.3.3.2.1 Idle-Line Wakeup When WAKE = 0, the receiver is configured for idle-line wakeup. In this mode, RWU is cleared automaticallywhenthereceiverdetectsafullcharactertimeoftheidle-linelevel.TheMcontrolbitselects 8-bitor9-bitdatamodethatdetermineshowmanybittimesofidleareneededtoconstituteafullcharacter time (10 or 11 bit times because of the start and stop bits). WhenRWUisoneandRWUIDiszero,theidleconditionthatwakesupthereceiverdoesnotsettheIDLE flag. The receiver wakes up and waits for the first data character of the next message which will set the RDRF flag and generate an interrupt if enabled. When RWUID is one, any idle condition sets the IDLE flag and generates an interrupt if enabled, regardless of whether RWU is zero or one. The idle-line type (ILT) control bit selects one of two ways to detect an idle line. When ILT = 0, the idle bit counter starts after the start bit so the stop bit and any logic 1s at the end of a character count toward thefullcharactertimeofidle.WhenILT=1,theidlebitcounterdoesnotstartuntilafterastopbittime, so the idle detection is not affected by the data in the last character of the previous message. 14.3.3.2.2 Address-Mark Wakeup When WAKE = 1, the receiver is configured for address-mark wakeup. In this mode, RWU is cleared automaticallywhenthereceiverdetectsalogic1inthemostsignificantbitofareceivedcharacter(eighth bit in M = 0 mode and ninth bit in M = 1 mode). Address-mark wakeup allows messages to contain idle characters but requires that the MSB be reserved foruseinaddressframes.Thelogic1MSBofanaddressframeclearstheRWUbitbeforethestopbitis received and sets the RDRF flag.In this case the character with the MSB set is received even though the receiver was sleeping during most of this character time. 14.3.4 Interrupts and Status Flags TheSCIsystemhasthreeseparateinterruptvectorstoreducetheamountofsoftwareneededtoisolatethe cause of the interrupt. One interrupt vector is associated with the transmitter for TDRE and TC events. AnotherinterruptvectorisassociatedwiththereceiverforRDRF,IDLE,RXEDGIFandLBKDIFevents, andathirdvectorisusedforOR,NF,FE,andPFerrorconditions.Eachoftheseteninterruptsourcescan be separately masked by local interrupt enable masks. The flags can still be polled by software when the local masks are cleared to disable generation of hardware interrupt requests. TheSCItransmitterhastwostatusflagsthatoptionallycangeneratehardwareinterruptrequests.Transmit data register empty (TDRE) indicates when there is room in the transmit data buffer to write another transmit character to SCIxD. If the transmit interrupt enable (TIE) bit is set, a hardware interrupt will be requested whenever TDRE=1. Transmit complete (TC) indicates that the transmitter is finished transmittingalldata,preamble,andbreakcharactersandisidlewithTxDattheinactivelevel.Thisflagis often used in systems with modems to determine when it is safe to turn off the modem. If the transmit complete interrupt enable (TCIE) bit is set, a hardware interrupt will be requested whenever TC=1. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 219

Chapter 14 Serial Communications Interface (S08SCIV4) Insteadofhardwareinterrupts,softwarepollingmaybeusedtomonitortheTDREandTCstatusflagsif the corresponding TIE or TCIE local interrupt masks are 0s. Whenaprogramdetectsthatthereceivedataregisterisfull(RDRF=1),itgetsthedatafromthereceive data register by reading SCIxD. The RDRF flag is cleared by reading SCIxS1 while RDRF=1 and then reading SCIxD. When polling is used, this sequence is naturally satisfied in the normal course of the user program. If hardwareinterruptsareused,SCIxS1mustbereadintheinterruptserviceroutine(ISR).Normally,thisis done in the ISR anyway to check for receive errors, so the sequence is automatically satisfied. TheIDLEstatusflagincludeslogicthatpreventsitfromgettingsetrepeatedlywhentheRxDlineremains idleforanextendedperiodoftime.IDLEisclearedbyreadingSCIxS1whileIDLE=1andthenreading SCIxD.AfterIDLEhasbeencleared,itcannotbecomesetagainuntilthereceiverhasreceivedatleastone new character and has set RDRF. IftheassociatederrorwasdetectedinthereceivedcharacterthatcausedRDRFtobeset,theerrorflags— noiseflag(NF),framingerror(FE),andparityerrorflag(PF)—getsetatthesametimeasRDRF.These flags are not set in overrun cases. If RDRF was already set when a new character is ready to be transferred from the receive shifter to the receivedatabuffer,theoverrun(OR)flaggetssetinsteadthedataalongwithanyassociatedNF,FE,orPF condition is lost. At any time, an active edge on the RxD serial data input pin causes the RXEDGIF flag to set. The RXEDGIFflagisclearedbywritinga“1”toit.Thisfunctiondoesdependonthereceiverbeingenabled (RE = 1). 14.3.5 Additional SCI Functions The following sections describe additional SCI functions. 14.3.5.1 8- and 9-Bit Data Modes The SCI system (transmitter and receiver) can be configured to operate in 9-bit data mode by setting the M control bit in SCIxC1. In 9-bit mode, there is a ninth data bit to the left of the MSB of the SCI data register. For the transmit data buffer, this bit is stored in T8 in SCIxC3. For the receiver, the ninth bit is held in R8 in SCIxC3. For coherent writes to the transmit data buffer, write to the T8 bit before writing to SCIxD. Ifthebitvaluetobetransmittedastheninthbitofanewcharacteristhesameasforthepreviouscharacter, it is not necessary to write to T8 again. When data is transferred from the transmit data buffer to the transmit shifter, the value in T8 is copied at the same time data is transferred from SCIxD to the shifter. 9-bitdatamodetypicallyisusedinconjunctionwithparitytoalloweightbitsofdataplustheparityinthe ninth bit. Or it is used with address-mark wakeup so the ninth data bit can serve as the wakeup bit. In custom protocols, the ninth bit can also serve as a software-controlled marker. MC9S08SH8MCUSeriesDataSheet,Rev.3 220 Freescale Semiconductor

Chapter 14 Serial Communications Interface (S08SCIV4) 14.3.5.2 Stop Mode Operation During all stop modes, clocks to the SCI module are halted. Instop1andstop2modes,allSCIregisterdataislostandmustbere-initializeduponrecoveryfromthese two stop modes. No SCI module registers are affected in stop3 mode. Thereceiveinputactiveedgedetectcircuitisstillactiveinstop3mode,butnotinstop2..Anactiveedge on the receive input brings the CPU out of stop3 mode if the interrupt is not masked (RXEDGIE = 1). Note, because the clocks are halted, the SCI module will resume operation upon exit from stop (only in stop3mode).Softwareshouldensurestopmodeisnotenteredwhilethereisacharacterbeingtransmitted out of or received into the SCI module. 14.3.5.3 Loop Mode When LOOPS=1, the RSRC bit in the same register chooses between loop mode (RSRC=0) or single-wire mode (RSRC=1). Loop mode is sometimes used to check software, independent of connectionsintheexternalsystem,tohelpisolatesystemproblems.Inthismode,thetransmitteroutputis internally connected to the receiver input and the RxD pin is not used by the SCI, so it reverts to a general-purpose port I/O pin. 14.3.5.4 Single-Wire Operation When LOOPS=1, the RSRC bit in the same register chooses between loop mode (RSRC=0) or single-wire mode (RSRC=1). Single-wire mode is used to implement a half-duplex serial connection. ThereceiverisinternallyconnectedtothetransmitteroutputandtotheTxDpin.TheRxDpinisnotused and reverts to a general-purpose port I/O pin. Insingle-wiremode,theTXDIRbitinSCIxC3controlsthedirectionofserialdataontheTxDpin.When TXDIR=0, the TxD pin is an input to the SCI receiver and the transmitter is temporarily disconnected fromtheTxDpinsoanexternaldevicecansendserialdatatothereceiver.WhenTXDIR=1,theTxDpin is an output driven by the transmitter. In single-wire mode, the internal loop back connection from the transmitter to the receiver causes the receiver to receive characters that are sent out by the transmitter. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 221

Chapter 14 Serial Communications Interface (S08SCIV4) MC9S08SH8MCUSeriesDataSheet,Rev.3 222 Freescale Semiconductor

Chapter 15 Serial Peripheral Interface (S08SPIV3) 15.1 Introduction Figure15-1 shows the MC9S08SH8 block diagram with the SPI module highlighted. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 223

Chapter15 Serial Peripheral Interface (S08SPIV3) BKGD/MS IRQ HCS08 CORE DEBUG MODULE (DBG) CPU BDC 8-BIT MODULO TIMER TCLK HCS08 SYSTEM CONTROL MODULE (MTIM) PTA5/IRQ/TCLK/RESET PTA4/ACMPO/BKGD/MS RESETS AND INTERRUPTS A MODES OF OPERATION SCL T PTA3/PAI3/SCL/ADP3 POWER MANAGEMENT IIC MODULE (IIC) SDA POR PTA2/PAI2/SDA/ADP2 COP IRQ LVD SS PTA1/PIA1/TPM2CH0/ADP1/ACMP– PTA0/PIA0/TPM1CH0/ADP0/ACMP+ MISO SERIAL PERIPHERAL MOSI INTERFACE MODULE (SPI) USER FLASH SPSCK (MC9S08SH8 =8,192 BYTES) PTB7/SCL/EXTAL (MC9S08SH4 =4096 BYTES) PTB6/SDA/XTAL SERIAL COMMUNICATIONS RxD SEE NOTE 1 INTERFACE MODULE (SCI) TxD PTB5/TPM1CH1/SS USER RAM (MC9S08SH8 =512 BYTES) TCLK T B PTB4/TPM2CH1/MISO (MC9S08SH4 =256 BYTES) 16-BIT TIMER/PWM TPM1CH0 OR PTB3/PIB3/MOSI/ADP7 P MODULE (TPM1) TPM1CH1 PTB2/PIB2/SPSCK/ADP6 REAL-TIME COUNTER (RTC) TCLK PTB1/PIB1/TxD/ADP5 16-BIT TIMER/PWM TPM2CH0 PTB0/PIB0/RxD/ADP4 40-MHz INTERNAL CLOCK SOURCE (ICS) MODULE (TPM2) TPM2CH1 SEE NOTE 1, 2 PTC3/ADP11 LOW31-P.2O5W kHEzR t oO S38C.I4L LkHATzOR EXTAL T C PTC2/ADP10 R 1 MHz to 16 MHz XTAL O PTC1/TPM1CH1/ADP9 (XOSC) P PTC0/TPM1CH0/ADP8 ACMPO SEE NOTE3 ANALOG COMPARATOR ACMP– (ACMP) ACMP+ V DD VOLTAGE REGULATOR VSS 10-BIT ADP11-ADP0 ANALOG-TO-DIGITAL V CONVERTER (ADC) DDA V SSA VREFH NOTES V REFL = Pin can be enabled as part of the ganged output drive feature NOTE1: Port B not available on 8-pinpackages NOTE2: Port C not available on 8-pin or 16-pin packages NOTE 3: V /V and V /V , are double bonded to V and V respectively. DDA REFH SSA REFL DD SS Figure15-1.MC9S08SH8 Block Diagram Highlighting theSPI Module MC9S08SH8MCUSeriesDataSheet,Rev.3 224 Freescale Semiconductor

Chapter 15 Serial Peripheral Interface (S08SPIV3) 15.1.1 Features Features of the SPI module include: • Master or slave mode operation • Full-duplex or single-wire bidirectional option • Programmable transmit bit rate • Double-buffered transmit and receive • Serial clock phase and polarity options • Slave select output • Selectable MSB-first or LSB-first shifting 15.1.2 Block Diagrams ThissectionincludesblockdiagramsshowingSPIsystemconnections,theinternalorganizationoftheSPI module, and the SPI clock dividers that control the master mode bit rate. 15.1.2.1 SPI System Block Diagram Figure15-2 shows the SPI modules of two MCUs connected in a master-slave arrangement. The master deviceinitiatesallSPIdatatransfers.Duringatransfer,themastershiftsdataout(ontheMOSIpin)tothe slave while simultaneously shifting data in (on the MISO pin) from the slave. The transfer effectively exchangesthedatathatwasintheSPIshiftregistersofthetwoSPIsystems.TheSPSCKsignalisaclock output from the master and an input to the slave. The slave device must be selected by a low level on the slaveselectinput(SSpin).Inthissystem,themasterdevicehasconfigureditsSSpinasanoptionalslave select output. MASTER SLAVE MOSI MOSI SPI SHIFTER SPI SHIFTER 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 MISO MISO SPSCK SPSCK CLOCK GENERATOR SS SS Figure15-2. SPI System Connections MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 225

Chapter 15 Serial Peripheral Interface (S08SPIV3) The most common uses of the SPI system include connecting simple shift registers for adding input or output ports or connecting small peripheral devices such as serial A/D or D/A converters. Although Figure15-2showsasystemwheredataisexchangedbetweentwoMCUs,manypracticalsystemsinvolve simplerconnectionswheredataisunidirectionallytransferredfromthemasterMCUtoaslaveorfroma slave to the master MCU. 15.1.2.2 SPI Module Block Diagram Figure15-3isablockdiagramoftheSPImodule.ThecentralelementoftheSPIistheSPIshiftregister. Data is written to the double-buffered transmitter (write to SPID) and gets transferred to the SPI shift register at the start of a data transfer. After shifting in a byte of data, the data is transferred into the double-buffered receiver where it can be read (read from SPID). Pin multiplexing logic controls connections between MCU pins and the SPI module. WhentheSPIisconfiguredasamaster,theclockoutputisroutedtotheSPSCKpin,theshifteroutputis routed to MOSI, and the shifter input is routed from the MISO pin. When the SPI is configured as a slave, the SPSCK pin is routed to the clock input of the SPI, the shifter output is routed to MISO, and the shifter input is routed from the MOSI pin. IntheexternalSPIsystem,simplyconnectallSPSCKpinstoeachother,allMISOpinstogether,andall MOSI pins together. Peripheral devices often use slightly different names for these pins. MC9S08SH8MCUSeriesDataSheet,Rev.3 226 Freescale Semiconductor

Chapter 15 Serial Peripheral Interface (S08SPIV3) PIN CONTROL M MOSI SPE S (MOMI) Tx BUFFER (WRITE SPID) ENABLE SPI SYSTEM M MISO SHIFT SPI SHIFT REGISTER SHIFT S (SISO) OUT IN SPC0 Rx BUFFER (READ SPID) BIDIROE SHIFT SHIFT Rx BUFFER Tx BUFFER LSBFE DIRECTION CLOCK FULL EMPTY MASTER CLOCK M BUS RATE SPIBR CLOCK SPSCK CLOCK CLOCK GENERATOR LOGIC SLAVE CLOCK S MASTER/SLAVE MASTER/ MSTR MODE SELECT SLAVE MODFEN SSOE MODE FAULT SS DETECTION SPRF SPTEF SPTIE SPI INTERRUPT MODF REQUEST SPIE Figure15-3. SPI Module Block Diagram 15.1.3 SPI Baud Rate Generation As shown inFigure15-4, the clock source for the SPI baud rate generator is the bus clock. The three prescale bits (SPPR2:SPPR1:SPPR0) choose a prescale divisor of 1, 2, 3, 4, 5, 6, 7, or 8. The three rate select bits (SPR2:SPR1:SPR0) divide the output of the prescaler stage by 2, 4, 8, 16, 32, 64, 128, or 256 to get the internal SPI master mode bit-rate clock. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 227

Chapter 15 Serial Peripheral Interface (S08SPIV3) PRESCALER CLOCK RATE DIVIDER DIVIDE BY DIVIDE BY MASTER BUS CLOCK SPI 1, 2, 3, 4, 5, 6, 7, or 8 2, 4, 8, 16, 32, 64, 128, or 256 BIT RATE SPPR2:SPPR1:SPPR0 SPR2:SPR1:SPR0 Figure15-4. SPI Baud Rate Generation 15.2 External Signal Description TheSPIoptionallysharesfourportpins.ThefunctionofthesepinsdependsonthesettingsofSPIcontrol bits.WhentheSPIisdisabled(SPE=0),thesefourpinsreverttobeinggeneral-purposeportI/Opinsthat are not controlled by the SPI. 15.2.1 SPSCK — SPI Serial Clock WhentheSPIisenabledasaslave,thispinistheserialclockinput.WhentheSPIisenabledasamaster, this pin is the serial clock output. 15.2.2 MOSI — Master Data Out, Slave Data In When the SPI is enabled as a master and SPI pin control zero (SPC0) is 0 (not bidirectional mode), this pin is the serial data output. When the SPI is enabled as a slave and SPC0=0, this pin is the serial data input.IfSPC0=1toselectsingle-wirebidirectionalmode,andmastermodeisselected,thispinbecomes thebidirectionaldataI/Opin(MOMI).Also,thebidirectionalmodeoutputenablebitdetermineswhether the pin acts as an input (BIDIROE=0) or an output (BIDIROE=1). If SPC0=1 and slave mode is selected, this pin is not used by the SPI and reverts to being a general-purpose port I/O pin. 15.2.3 MISO — Master Data In, Slave Data Out When the SPI is enabled as a master and SPI pin control zero (SPC0) is 0 (not bidirectional mode), this pin is the serial data input. When the SPI is enabled as a slave and SPC0=0, this pin is the serial data output.IfSPC0=1toselectsingle-wirebidirectionalmode,andslavemodeisselected,thispinbecomes thebidirectionaldataI/Opin(SISO)andthebidirectionalmodeoutputenablebitdetermineswhetherthe pinactsasaninput(BIDIROE=0)oranoutput(BIDIROE=1).IfSPC0=1andmastermodeisselected, this pin is not used by the SPI and reverts to being a general-purpose port I/O pin. 15.2.4 SS — Slave Select WhentheSPIisenabledasaslave,thispinisthelow-trueslaveselectinput.WhentheSPIisenabledas amasterandmodefaultenableisoff(MODFEN=0),thispinisnotusedbytheSPIandrevertstobeing a general-purpose port I/O pin. When the SPI is enabled as a master and MODFEN=1, the slave select outputenablebitdetermineswhetherthispinactsasthemodefaultinput(SSOE=0)orastheslaveselect output (SSOE=1). MC9S08SH8MCUSeriesDataSheet,Rev.3 228 Freescale Semiconductor

Chapter 15 Serial Peripheral Interface (S08SPIV3) 15.3 Modes of Operation 15.3.1 SPI in Stop Modes The SPI is disabled in all stop modes, regardless of the settings before executing the STOP instruction. Duringeitherstop1orstop2mode,theSPImodulewillbefullypowereddown.Uponwake-upfromstop1 orstop2mode,theSPImodulewillbeintheresetstate.Duringstop3mode,clockstotheSPImoduleare halted. No registers are affected. If stop3 is exited with a reset, the SPI will be put into its reset state. If stop3 is exited with an interrupt, the SPI continues from the state it was in when stop3 was entered. 15.4 Register Definitio The SPI has five 8-bit registers to select SPI options, control baud rate, report SPI status, and for transmit/receive data. Refertothedirect-pageregistersummaryintheMemorychapterofthisdatasheetfortheabsoluteaddress assignmentsforallSPIregisters.Thissectionreferstoregistersandcontrolbitsonlybytheirnames,and a Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 15.4.1 SPI Control Register 1 (SPIC1) This read/write register includes the SPI enable control, interrupt enables, and configuration options. 7 6 5 4 3 2 1 0 R SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE W Reset 0 0 0 0 0 1 0 0 Figure15-5. SPI Control Register 1 (SPIC1) Table15-1. SPIC1 Field Descriptions Field Description 7 SPI Interrupt Enable (for SPRF and MODF) — This is the interrupt enable for SPI receive buffer full (SPRF) SPIE and mode fault (MODF) events. 0 Interrupts from SPRF and MODF inhibited (use polling) 1 When SPRF or MODF is 1, request a hardware interrupt 6 SPISystemEnable—DisablingtheSPIhaltsanytransferthatisinprogress,clearsdatabuffers,andinitializes SPE internal state machines. SPRF is cleared and SPTEF is set to indicate the SPI transmit data buffer is empty. 0 SPI system inactive 1 SPI system enabled 5 SPI Transmit Interrupt Enable — This is the interrupt enable bit for SPI transmit buffer empty (SPTEF). SPTIE 0 Interrupts from SPTEF inhibited (use polling) 1 When SPTEF is 1, hardware interrupt requested MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 229

Chapter 15 Serial Peripheral Interface (S08SPIV3) Table15-1. SPIC1 Field Descriptions (continued) Field Description 4 Master/Slave Mode Select MSTR 0 SPI module configured as a slave SPI device 1 SPI module configured as a master SPI device 3 ClockPolarity—ThisbiteffectivelyplacesaninverterinserieswiththeclocksignalfromamasterSPIortoa CPOL slave SPI device. Refer toSection15.5.1, “SPI Clock Formats” for more details. 0 Active-high SPI clock (idles low) 1 Active-low SPI clock (idles high) 2 Clock Phase — This bit selects one of two clock formats for different kinds of synchronous serial peripheral CPHA devices. Refer toSection15.5.1, “SPI Clock Formats” for more details. 0 First edge on SPSCK occurs at the middle of the first cycle of an 8-cycle data transfer 1 First edge on SPSCK occurs at the start of the first cycle of an 8-cycle data transfer 1 Slave Select Output Enable — This bit is used in combination with the mode fault enable (MODFEN) bit in SSOE SPCR2andthemaster/slave(MSTR)controlbittodeterminethefunctionoftheSSpinasshowninTable15-2. 0 LSB First (Shifter Direction) LSBFE 0 SPI serial data transfers start with most significant bit 1 SPI serial data transfers start with least significant bit Table15-2.SS Pin Function MODFEN SSOE Master Mode Slave Mode 0 0 General-purpose I/O (not SPI) Slave select input 0 1 General-purpose I/O (not SPI) Slave select input 1 0 SS input for mode fault Slave select input 1 1 AutomaticSS output Slave select input NOTE EnsurethattheSPIshouldnotbedisabled(SPE=0)atthesametimeasabitchangetotheCPHAbit.These changes should be performed as separate operations or unexpected behavior may occur. 15.4.2 SPI Control Register 2 (SPIC2) This read/write register is used to control optional features of the SPI system. Bits 7, 6, 5, and 2 are not implemented and always read 0. 7 6 5 4 3 2 1 0 R 0 0 0 0 MODFEN BIDIROE SPISWAI SPC0 W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure15-6. SPI Control Register 2 (SPIC2) MC9S08SH8MCUSeriesDataSheet,Rev.3 230 Freescale Semiconductor

Chapter 15 Serial Peripheral Interface (S08SPIV3) Table15-3. SPIC2 Register Field Descriptions Field Description 4 MasterMode-FaultFunctionEnable—WhentheSPIisconfiguredforslavemode,thisbithasnomeaningor MODFEN effect. (TheSS pin is the slave select input.) In master mode, this bit determines how theSS pin is used (refer toTable15-2 for more details). 0 Mode fault function disabled, masterSS pin reverts to general-purpose I/O not controlled by SPI 1 Mode fault function enabled, masterSS pin acts as the mode fault input or the slave select output 3 Bidirectional Mode Output Enable — When bidirectional mode is enabled by SPI pin control 0 (SPC0)=1, BIDIROE BIDIROE determines whether the SPI data output driver is enabled to the single bidirectional SPI I/O pin. Depending on whether the SPI is configured as a master or a slave, it uses either the MOSI (MOMI) or MISO (SISO) pin, respectively, as the single SPI data I/O pin. When SPC0=0, BIDIROE has no meaning or effect. 0 Output driver disabled so SPI data I/O pin acts as an input 1 SPI I/O pin enabled as an output 1 SPI Stop in Wait Mode SPISWAI 0 SPI clocks continue to operate in wait mode 1 SPI clocks stop when the MCU enters wait mode 0 SPIPinControl0—TheSPC0bitchoosessingle-wirebidirectionalmode.IfMSTR=0(slavemode),theSPI SPC0 uses the MISO (SISO) pin for bidirectional SPI data transfers. If MSTR=1 (master mode), the SPI uses the MOSI(MOMI)pinforbidirectionalSPIdatatransfers.WhenSPC0=1,BIDIROEisusedtoenableordisablethe output driver for the single bidirectional SPI I/O pin. 0 SPI uses separate pins for data input and data output 1 SPI configured for single-wire bidirectional operation 15.4.3 SPI Baud Rate Register (SPIBR) ThisregisterisusedtosettheprescalerandbitratedivisorforanSPImaster.Thisregistermaybereador written at any time. 7 6 5 4 3 2 1 0 R 0 0 SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure15-7. SPI Baud Rate Register (SPIBR) Table15-4. SPIBR Register Field Descriptions Field Description 6:4 SPIBaudRatePrescaleDivisor—This3-bitfieldselectsoneofeightdivisorsfortheSPIbaudrateprescaler SPPR[2:0] asshowninTable15-5.Theinputtothisprescaleristhebusrateclock(BUSCLK).Theoutputofthisprescaler drives the input of the SPI baud rate divider (seeFigure15-4). 2:0 SPIBaudRateDivisor—This3-bitfieldselectsoneofeightdivisorsfortheSPIbaudratedividerasshownin SPR[2:0] Table15-6.TheinputtothisdividercomesfromtheSPIbaudrateprescaler(seeFigure15-4).Theoutputofthis divider is the SPI bit rate clock for master mode. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 231

Chapter 15 Serial Peripheral Interface (S08SPIV3) Table15-5. SPI Baud Rate Prescaler Divisor SPPR2:SPPR1:SPPR0 Prescaler Divisor 0:0:0 1 0:0:1 2 0:1:0 3 0:1:1 4 1:0:0 5 1:0:1 6 1:1:0 7 1:1:1 8 Table15-6. SPI Baud Rate Divisor SPR2:SPR1:SPR0 Rate Divisor 0:0:0 2 0:0:1 4 0:1:0 8 0:1:1 16 1:0:0 32 1:0:1 64 1:1:0 128 1:1:1 256 15.4.4 SPI Status Register (SPIS) Thisregisterhasthreeread-onlystatusbits.Bits6,3,2,1,and0arenotimplementedandalwaysread0. Writes have no meaning or effect. 7 6 5 4 3 2 1 0 R SPRF 0 SPTEF MODF 0 0 0 0 W Reset 0 0 1 0 0 0 0 0 = Unimplemented or Reserved Figure15-8. SPI Status Register (SPIS) MC9S08SH8MCUSeriesDataSheet,Rev.3 232 Freescale Semiconductor

Chapter 15 Serial Peripheral Interface (S08SPIV3) Table15-7. SPIS Register Field Descriptions Field Description 7 SPIReadBufferFullFlag—SPRFissetatthecompletionofanSPItransfertoindicatethatreceiveddatamay SPRF bereadfromtheSPIdataregister(SPID).SPRFisclearedbyreadingSPRFwhileitisset,thenreadingtheSPI data register. 0 No data available in the receive data buffer 1 Data available in the receive data buffer 5 SPITransmitBufferEmptyFlag—Thisbitissetwhenthereisroominthetransmitdatabuffer.Itisclearedby SPTEF readingSPISwithSPTEFset,followedbywritingadatavaluetothetransmitbufferatSPID.SPISmustberead withSPTEF=1beforewritingdatatoSPIDortheSPIDwritewillbeignored.SPTEFgeneratesanSPTEFCPU interruptrequestiftheSPTIEbitintheSPIC1isalsoset.SPTEFisautomaticallysetwhenadatabytetransfers fromthetransmitbufferintothetransmitshiftregister.ForanidleSPI(nodatainthetransmitbufferortheshift register and no transfer in progress), data written to SPID is transferred to the shifter almost immediately so SPTEFissetwithintwobuscyclesallowingasecond8-bitdatavaluetobequeuedintothetransmitbuffer.After completion of the transfer of the value in the shift register, the queued value from the transmit buffer will automatically move to the shifter and SPTEF will be set to indicate there is room for new data in the transmit buffer. If no new data is waiting in the transmit buffer, SPTEF simply remains set and no data moves from the buffer to the shifter. 0 SPI transmit buffer not empty 1 SPI transmit buffer empty 4 Master Mode Fault Flag — MODF is set if the SPI is configured as a master and the slave select input goes MODF low,indicatingsomeotherSPIdeviceisalsoconfiguredasamaster.TheSSpinactsasamodefaulterrorinput only when MSTR=1, MODFEN=1, and SSOE=0; otherwise, MODF will never be set. MODF is cleared by reading MODF while it is 1, then writing to SPI control register 1 (SPIC1). 0 No mode fault error 1 Mode fault error detected 15.4.5 SPI Data Register (SPID) 7 6 5 4 3 2 1 0 R Bit 7 6 5 4 3 2 1 Bit 0 W Reset 0 0 0 0 0 0 0 0 Figure15-9. SPI Data Register (SPID) Readsofthisregisterreturnthedatareadfromthereceivedatabuffer.Writestothisregisterwritedatato the transmit data buffer. When the SPI is configured as a master, writing data to the transmit data buffer initiates an SPI transfer. Data should not be written to the transmit data buffer unless the SPI transmit buffer empty flag (SPTEF) is set, indicating there is room in the transmit buffer to queue a new transmit byte. DatamaybereadfromSPIDanytimeafterSPRFissetandbeforeanothertransferisfinished.Failureto read the data out of the receive data buffer before a new transfer ends causes a receive overrun condition and the data from the new transfer is lost. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 233

Chapter 15 Serial Peripheral Interface (S08SPIV3) 15.5 Functional Description An SPI transfer is initiated by checking for the SPI transmit buffer empty flag (SPTEF=1) and then writingabyteofdatatotheSPIdataregister(SPID)inthemasterSPIdevice.WhentheSPIshiftregister isavailable,thisbyteofdataismovedfromthetransmitdatabuffertotheshifter,SPTEFissettoindicate thereisroominthebuffertoqueueanothertransmitcharacterifdesired,andtheSPIserialtransferstarts. DuringtheSPItransfer,dataissampled(read)ontheMISOpinatoneSPSCKedgeandshifted,changing thebitvalueontheMOSIpin,one-halfSPSCKcyclelater.AftereightSPSCKcycles,thedatathatwasin theshiftregisterofthemasterhasbeenshiftedouttheMOSIpintotheslavewhileeightbitsofdatawere shiftedintheMISOpinintothemaster’sshiftregister.Attheendofthistransfer,thereceiveddatabyteis moved from the shifter into the receive data buffer and SPRF is set to indicate the data can be read by reading SPID. If another byte of data is waiting in the transmit buffer at the end of a transfer, it is moved into the shifter, SPTEF is set, and a new transfer is started. Normally, SPI data is transferred most significant bit (MSB) first. If the least significant bit first enable (LSBFE) bit is set, SPI data is shifted LSB first. When the SPI is configured as a slave, its SS pin must be driven low before a transfer starts and SS must stay low throughout the transfer. If a clock format where CPHA=0 is selected, SS must be driven to a logic1betweensuccessivetransfers.IfCPHA=1,SSmayremainlowbetweensuccessivetransfers.See Section15.5.1, “SPI Clock Formats” for more details. Because the transmitter and receiver are double buffered, a second byte, in addition to the byte currently being shifted out, can be queued into the transmit data buffer, and a previously received character can be in the receive data buffer while a new character is being shifted in. The SPTEF flag indicates when the transmit buffer has room for a new character. The SPRF flag indicates when a received character is available in the receive data buffer. The received character must be read out of the receive buffer (read SPID) before the next transfer is finished or a receive overrun error results. In the case of a receive overrun, the new data is lost because the receive buffer still held the previous character and was not ready to accept the new data. There is no indication for such an overrun condition so the application system designer must ensure that previous data has been read from the receive buffer before a new transfer is initiated. 15.5.1 SPI Clock Formats To accommodate a wide variety of synchronous serial peripherals from different manufacturers, the SPI system has a clock polarity (CPOL) bit and a clock phase (CPHA) control bit to select one of four clock formats for data transfers. CPOL selectively inserts an inverter in series with the clock. CPHA chooses between two different clock phase relationships between the clock and data. Figure15-10 shows the clock formats when CPHA = 1. At the top of the figure, the eight bit times are shownforreferencewithbit1startingatthefirstSPSCKedgeandbit8endingone-halfSPSCKcycleafter the sixteenth SPSCK edge. The MSB first and LSB first lines show the order of SPI data bits depending onthesettinginLSBFE.BothvariationsofSPSCKpolarityareshown,butonlyoneofthesewaveforms appliesforaspecifictransfer,dependingonthevalueinCPOL.TheSAMPLEINwaveformappliestothe MOSI input of a slave or the MISO input of a master. The MOSI waveform applies to the MOSI output MC9S08SH8MCUSeriesDataSheet,Rev.3 234 Freescale Semiconductor

Chapter 15 Serial Peripheral Interface (S08SPIV3) pin from a master and the MISOwaveform applies to the MISO output from a slave. The SS OUT waveformappliestotheslaveselectoutputfromamaster(providedMODFENandSSOE=1).Themaster SS output goes to active low one-half SPSCK cycle before the start of the transfer and goes back high at the end of the eighth bit time of the transfer. The SSIN waveform applies to the slave select input of a slave. BIT TIME # (REFERENCE) 1 2 ... 6 7 8 SPSCK (CPOL=0) SPSCK (CPOL=1) SAMPLE IN (MISO OR MOSI) MOSI (MASTER OUT) MSB FIRST BIT 7 BIT 6 ... BIT 2 BIT 1 BIT 0 LSB FIRST BIT 0 BIT 1 ... BIT 5 BIT 6 BIT 7 MISO (SLAVE OUT) SS OUT (MASTER) SS IN (SLAVE) Figure15-10. SPI Clock Formats (CPHA = 1) WhenCPHA=1,theslavebeginstodriveitsMISOoutputwhenSSgoestoactivelow,butthedataisnot defined until the first SPSCK edge. The first SPSCK edge shifts the first bit of data from the shifter onto the MOSI output of the master and the MISO output of the slave. The next SPSCK edge causes both the master and the slave to sample the data bit values on their MISO and MOSI inputs, respectively. At the thirdSPSCKedge,theSPIshiftershiftsonebitpositionwhichshiftsinthebitvaluethatwasjustsampled, andshiftstheseconddatabitvalueouttheotherendoftheshiftertotheMOSIandMISOoutputsofthe master and slave, respectively. When CHPA=1, the slave’s SS input is not required to go to its inactive high level between transfers. Figure15-11 shows the clock formats when CPHA = 0. At the top of the figure, the eight bit times are shownforreferencewithbit1startingastheslaveisselected(SSINgoeslow),andbit8endsatthelast SPSCKedge.TheMSBfirstandLSBfirstlinesshowtheorderofSPIdatabitsdependingonthesetting MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 235

Chapter 15 Serial Peripheral Interface (S08SPIV3) in LSBFE. Both variations of SPSCK polarity are shown, but only one of these waveforms applies for a specifictransfer,dependingonthevalueinCPOL.TheSAMPLEINwaveformappliestotheMOSIinput of a slave or the MISO input of a master. The MOSIwaveform applies to the MOSI output pin from a masterandtheMISOwaveformappliestotheMISOoutputfromaslave.TheSSOUTwaveformapplies totheslaveselectoutputfromamaster(providedMODFENandSSOE=1).Themaster SSoutputgoes toactivelowatthestartofthefirstbittimeofthetransferandgoesbackhighone-halfSPSCKcycleafter the end of the eighth bit time of the transfer. The SSIN waveform applies to the slave select input of a slave. BIT TIME # (REFERENCE) 1 2 ... 6 7 8 SPSCK (CPOL=0) SPSCK (CPOL=1) SAMPLE IN (MISO OR MOSI) MOSI (MASTER OUT) MSB FIRST BIT 7 BIT 6 ... BIT 2 BIT 1 BIT 0 LSB FIRST BIT 0 BIT 1 ... BIT 5 BIT 6 BIT 7 MISO (SLAVE OUT) SS OUT (MASTER) SS IN (SLAVE) Figure15-11. SPI Clock Formats (CPHA = 0) When CPHA=0, the slave begins to drive its MISO output with the first data bit value (MSB or LSB dependingonLSBFE)whenSSgoestoactivelow.ThefirstSPSCKedgecausesboththemasterandthe slave to sample the data bit values on their MISO and MOSI inputs, respectively. At the second SPSCK edge,theSPIshiftershiftsonebitpositionwhichshiftsinthebitvaluethatwasjustsampledandshiftsthe second data bit value out the other end of the shifter to the MOSI and MISO outputs of the master and slave, respectively. When CPHA=0, the slave’s SS input must go to its inactive high level between transfers. MC9S08SH8MCUSeriesDataSheet,Rev.3 236 Freescale Semiconductor

Chapter 15 Serial Peripheral Interface (S08SPIV3) 15.5.2 SPI Interrupts Therearethreeflagbits,twointerruptmaskbits,andoneinterruptvectorassociatedwiththeSPIsystem. TheSPIinterruptenablemask(SPIE)enablesinterruptsfromtheSPIreceiverfullflag(SPRF)andmode fault flag (MODF). The SPI transmit interrupt enable mask (SPTIE) enables interrupts from the SPI transmitbufferemptyflag(SPTEF).Whenoneoftheflagbitsisset,andtheassociatedinterruptmaskbit isset,ahardwareinterruptrequestissenttotheCPU.Iftheinterruptmaskbitsarecleared,softwarecan poll the associated flag bits instead of using interrupts. The SPI interrupt service routine (ISR) should checktheflagbitstodeterminewhateventcausedtheinterrupt.Theserviceroutineshouldalsoclearthe flag bit(s) before returning from the ISR (usually near the beginning of the ISR). 15.5.3 Mode Fault Detection A mode fault occurs and the mode fault flag (MODF) becomes set when a master SPI device detects an error on theSS pin (provided theSS pin is configured as the mode fault input signal). TheSS pin is configured to be the mode fault input signal when MSTR=1, mode fault enable is set (MODFEN=1), and slave select output enable is clear (SSOE=0). ThemodefaultdetectionfeaturecanbeusedinasystemwheremorethanoneSPIdevicemightbecome amasteratthesametime.Theerrorisdetectedwhenamaster’sSSpinislow,indicatingthatsomeother SPIdeviceistryingtoaddressthismasterasifitwereaslave.Thiscouldindicateaharmfuloutputdriver conflict,sothemodefaultlogicisdesignedtodisableallSPIoutputdriverswhensuchanerrorisdetected. When a mode fault is detected, MODF is set and MSTR is cleared to change the SPI configuration back to slave mode. The output drivers on the SPSCK, MOSI, and MISO (if not bidirectional mode) are disabled. MODF is cleared by reading it while it is set, then writing to the SPI control register 1 (SPIC1). User software should verify the error condition has been corrected before changing the SPI back to master mode. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 237

Chapter 15 Serial Peripheral Interface (S08SPIV3) MC9S08SH8MCUSeriesDataSheet,Rev.3 238 Freescale Semiconductor

Chapter 16 Timer Pulse-Width Modulator (S08TPMV3) 16.1 Introduction The TPM uses one input/output (I/O) pin per channel, TPMxCHn where x is the TPM number (for example, 1 or 2) and n is the channel number (for example, 0–1). The TPM shares its I/O pins with general-purpose I/O port pins (refer to thePins and Connections chapter for more information). All MC9S08SH8 MCUs have two TPM modules. The number of channels available depends on the pin quantity of the package, as shown in Table 16-1: Table16-1. MC9S08SH8 Features by MCU and Package Feature MC9S08SH8/4 Pin quantity 20 16 8 TPM1 channels 2 2 11 TPM2 channels 2 2 11 1 The8-pindevicedoesnothaveTPM1orTPM2channel 1 bonded out, but those timer channels are available to the user to use as software compares. Figure16-1 shows the MC9S08SH8 block diagram with the TPM modules highlighted. 16.1.1 ACMP/TPM Configuration In ormation The ACMP module can be configured to connect the ouput of the analog comparator to TPM1 input capturechannel0bysettingACICinSOPT2.WithACICset,theTPM1CH0pinisnotavailableexternally regardless of the configuration of the TPM1 module for channel 0. 16.1.2 TPM Configuration In ormation TheexternalclockfortheTPMmodules,TPMCLK,isselectedbysettingCLKS[B:A]=1:1inTPMxSC, which selects the TCLK pin input. The TCLK input on PTA0 can be enabled as external clock inputs to both TPM modules and MTIM simultaneously. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 239

Chapter16 Timer Pulse-Width Modulator (S08TPMV3) BKGD/MS IRQ HCS08 CORE DEBUG MODULE (DBG) CPU BDC 8-BIT MODULO TIMER TCLK HCS08 SYSTEM CONTROL MODULE (MTIM) PTA5/IRQ/TCLK/RESET PTA4/ACMPO/BKGD/MS RESETS AND INTERRUPTS A MODES OF OPERATION SCL T PTA3/PAI3/SCL/ADP3 POWER MANAGEMENT IIC MODULE (IIC) SDA POR PTA2/PAI2/SDA/ADP2 COP IRQ LVD SS PTA1/PIA1/TPM2CH0/ADP1/ACMP– PTA0/PIA0/TPM1CH0/ADP0/ACMP+ MISO SERIAL PERIPHERAL MOSI INTERFACE MODULE (SPI) USER FLASH SPSCK (MC9S08SH8 =8,192 BYTES) PTB7/SCL/EXTAL (MC9S08SH4 =4096 BYTES) PTB6/SDA/XTAL SERIAL COMMUNICATIONS RxD SEE NOTE 1 INTERFACE MODULE (SCI) TxD PTB5/TPM1CH1/SS USER RAM (MC9S08SH8 =512 BYTES) TCLK T B PTB4/TPM2CH1/MISO (MC9S08SH4 =256 BYTES) 16-BIT TIMER/PWM TPM1CH0 OR PTB3/PIB3/MOSI/ADP7 P MODULE (TPM1) TPM1CH1 PTB2/PIB2/SPSCK/ADP6 REAL-TIME COUNTER (RTC) TCLK PTB1/PIB1/TxD/ADP5 16-BIT TIMER/PWM TPM2CH0 PTB0/PIB0/RxD/ADP4 40-MHz INTERNAL CLOCK SOURCE (ICS) MODULE (TPM2) TPM2CH1 SEE NOTE 1, 2 PTC3/ADP11 LOW31-P.2O5W kHEzR t oO S38C.I4L LkHATzOR EXTAL T C PTC2/ADP10 R 1 MHz to 16 MHz XTAL O PTC1/TPM1CH1/ADP9 (XOSC) P PTC0/TPM1CH0/ADP8 ACMPO SEE NOTE3 ANALOG COMPARATOR ACMP– (ACMP) ACMP+ V DD VOLTAGE REGULATOR VSS 10-BIT ADP11-ADP0 ANALOG-TO-DIGITAL V CONVERTER (ADC) DDA V SSA VREFH NOTES V REFL = Pin can be enabled as part of the ganged output drive feature NOTE1: Port B not available on 8-pinpackages NOTE2: Port C not available on 8-pin or 16-pin packages NOTE 3: V /V and V /V , are double bonded to V and V respectively. DDA REFH SSA REFL DD SS Figure16-1.MC9S08SH8 Block Diagram Highlighting theTPM Modules MC9S08SH8MCUSeriesDataSheet,Rev.3 240 Freescale Semiconductor

Chapter 16 Timer/PWM Module (S08TPMV3) 16.1.3 Features The TPM includes these distinctive features: • One to eightchannels: — Each channel may be input capture, output compare, or edge-aligned PWM — Rising-Edge, falling-edge, or any-edge input capture trigger — Set, clear, or toggle output compare action — Selectable polarity on PWM outputs • Module may be configured for buffered,center-aligned pulse-width-modulation (CPWM) on all channels • Timer clock source selectable as prescaled bus clock, fixed system clock, or an external clock pin — Prescale taps for divide-by 1, 2, 4, 8, 16, 32, 64, or 128 — Fixed system clock source are synchronized to the bus clock by an on-chip synchronization circuit — External clock pin may be shared with any timer channel pin or a separated input pin • 16-bit free-running or modulo up/down count operation • Timer system enable • One interrupt per channel plus terminal count interrupt 16.1.4 Modes of Operation In general, TPM channels may be independently configured to operate in input capture, output compare, or edge-aligned PWM modes. A control bit allows the whole TPM (all channels) to switch to center-alignedPWMmode.Whencenter-alignedPWMmodeisselected,inputcapture,outputcompare, and edge-aligned PWM functions are not available on any channels of this TPM module. WhenthemicrocontrollerisinactiveBDMbackgroundorBDMforegroundmode,theTPMtemporarily suspendsallcountinguntilthemicrocontrollerreturnstonormaluseroperatingmode.Duringstopmode, all system clocks, including the main oscillator, are stopped; therefore, the TPM is effectively disabled until clocks resume. During wait mode, the TPM continues to operate normally. Provided the TPM does notneedtoproducearealtimereferenceorprovidetheinterruptsource(s)neededtowaketheMCUfrom wait mode, the user can save power by disabling TPM functions before entering wait mode. • Input capture mode WhenaselectededgeeventoccursontheassociatedMCUpin,thecurrentvalueofthe16-bittimer counter is captured into the channel value register and an interrupt flag bit is set. Rising edges, falling edges, any edge, or no edge (disable channel) may be selected as the active edge which triggers the input capture. • Output compare mode When the value in the timer counter register matches the channel value register, an interrupt flag bit is set, and a selected output action is forced on the associated MCU pin. The output compare action may be selected to force the pin to zero, force the pin to one, toggle the pin, or ignore the pin (used for software timing functions). MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 241

Chapter 16 Timer/PWM Module (S08TPMV3) • Edge-aligned PWM mode Thevalueofa16-bitmoduloregisterplus1setstheperiodofthePWMoutputsignal.Thechannel valueregistersetsthedutycycleofthePWMoutputsignal.Theusermayalsochoosethepolarity of the PWM output signal. Interrupts are available at the end of the period and at the duty-cycle transition point. This type of PWM signal is called edge-aligned because the leading edges of all PWMsignalsarealignedwiththebeginningoftheperiod,whichisthesameforallchannelswithin a TPM. • Center-aligned PWM mode Twice the value of a 16-bit modulo register sets the period of the PWM output, and the channel-value register sets the half-duty-cycle duration. The timer counter counts up until it reaches the modulo value and then counts down until it reaches zero. As the count matches the channel value register while counting down, the PWM output becomes active. When the count matchesthechannelvalueregisterwhilecountingup,thePWMoutputbecomesinactive.Thistype ofPWMsignaliscalledcenter-alignedbecausethecentersoftheactivedutycycleperiodsforall channelsarealignedwithacountvalueofzero.ThistypeofPWMisrequiredfortypesofmotors used in small appliances. This is a high-level description only. Detailed descriptions of operating modes are in later sections. 16.1.5 Block Diagram TheTPMusesoneinput/output(I/O)pinperchannel,TPMxCHn(timerchanneln)wherenisthechannel number(1-8).TheTPMsharesitsI/OpinswithgeneralpurposeI/Oportpins(refertoI/Opindescriptions in full-chip specification for the specific chip implementation). Figure16-2 shows the TPM structure. The central component of the TPM is the 16-bit counter that can operate as a free-running counter or a modulo up/down counter. The TPM counter (when operating in normal up-counting mode) provides the timing reference for the input capture, output compare, and edge-aligned PWM functions. The timer counter modulo registers, TPMxMODH:TPMxMODL, control themodulovalueofthecounter(thevalues0x0000or0xFFFFeffectivelymakethecounterfreerunning). Software can read the counter value at any time without affecting the counting sequence. Any write to either half of the TPMxCNT counter resets the counter, regardless of the data value written. MC9S08SH8MCUSeriesDataSheet,Rev.3 242 Freescale Semiconductor

Chapter 16 Timer/PWM Module (S08TPMV3) BUS CLOCK CLOCK SOURCE PRESCALE AND SELECT SELECT 1, 2, 4, 8, 16, 32, 64, FIXED SYSTEM CLOCK OFF, BUS, FIXED SYNC or 128 EXTERNAL CLOCK SYSTEM CLOCK, EXT CLKSB:CLKSA PS2:PS1:PS0 CPWMS 16-BIT COUNTER TOF INTER- COUNTER RESET RUPT TOIE LOGIC 16-BIT COMPARATOR TPMxMODH:TPMxMODL CHANNEL 0 ELS0B ELS0A PORT TPMxCH0 LOGIC 16-BIT COMPARATOR TPMxC0VH:TPMxC0VL CH0F INTER- 16-BIT LATCH RUPT LOGIC MS0B MS0A CH0IE S CHANNEL 1 ELS1B ELS1A PORT TPMxCH1 U LOGIC L B 16-BIT COMPARATOR A N TPMxC1VH:TPMxC1VL CH1F R E INTER- NT 16-BIT LATCH RUPT I LOGIC CH1IE MS1B MS1A Up to 8 channels CHANNEL 7 ELS7B ELS7A PORT TPMxCH7 LOGIC 16-BIT COMPARATOR TPMxC7VH:TPMxC7VL CH7F INTER- 16-BIT LATCH RUPT LOGIC CH7IE MS7B MS7A Figure16-2. TPM Block Diagram MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 243

Chapter 16 Timer/PWM Module (S08TPMV3) The TPM channels are programmable independently as input capture, output compare, or edge-aligned PWMchannels.Alternately,theTPMcanbeconfiguredtoproduceCPWMoutputsonallchannels.When the TPM is configured for CPWMs, the counter operates as an up/down counter; input capture, output compare, and EPWM functions are not practical. Ifachannelisconfiguredasinputcapture,aninternalpullupdevicemaybeenabledforthatchannel.The detailsofhowamoduleinteractswithpincontrolsdependsuponthechipimplementationbecausetheI/O pinsandassociatedgeneralpurposeI/Ocontrolsarenotpartofthemodule.Refertothediscussionofthe I/O port logic in a full-chip specification. Because center-aligned PWMs are usually used to drive 3-phase AC-induction motors and brushless DC motors, they are typically used in sets of three or six channels. 16.2 Signal Description Table16-2 shows the user-accessible signals for the TPM. The number of channels may be varied from onetoeight.Whenanexternalclockisincluded,itcanbesharedwiththesamepinasanyTPMchannel; however, it could be connected to a separate input pin. Refer to the I/O pin descriptions in full-chip specification for the specific chip implementation. Table16-2. Signal Properties Name Function EXTCLK1 External clock source which may be selected to drive the TPM counter. TPMxCHn2 I/O pin associated with TPM channel n 1 When preset, this signal can share any channel pin; however depending upon full-chip implementation, this signal could be connected to a separate external pin. 2 n=channel number (1 to 8) Refertodocumentationforthefull-chipfordetailsaboutresetstates,portconnections,andwhetherthere is any pullup device on these pins. TPMchannelpinscanbeassociatedwithgeneralpurposeI/Opinsandhavepassivepullupdeviceswhich can be enabled with a control bit when the TPM or general purpose I/O controls have configured the associated pin as an input. When no TPM function is enabled to use a corresponding pin, the pin reverts to being controlled by general purpose I/O controls, including the port-data and data-direction registers. Immediatelyafterreset,noTPMfunctionsareenabled,soallassociatedpinsreverttogeneralpurposeI/O control. 16.2.1 Detailed Signal Descriptions Thissectiondescribeseachuser-accessiblepinsignalindetail.AlthoughTable16-2groupedallchannel pinstogether,anyTPMpincanbesharedwiththeexternalclocksourcesignal.SinceI/Opinlogicisnot part of the TPM, refer to full-chip documentation for a specific derivative for more details about the interactionofTPMpinfunctionsandgeneralpurposeI/Ocontrolsincludingportdata,datadirection,and pullup controls. MC9S08SH8MCUSeriesDataSheet,Rev.3 244 Freescale Semiconductor

Chapter 16 Timer/PWM Module (S08TPMV3) 16.2.1.1 EXTCLK — External Clock Source Control bits in the timer status and control register allow the user to select nothing (timer disable), the bus-rateclock(thenormaldefaultsource),acrystal-relatedclock,oranexternalclockastheclockwhich drives the TPM prescaler and subsequently the 16-bit TPM counter. The external clock source is synchronizedintheTPM.Thebusclockclocksthesynchronizer;thefrequencyoftheexternalsourcemust benomorethanone-fourththefrequencyofthebus-rateclock,tomeetNyquistcriteriaandallowingfor jitter. The external clock signal shares the same pin as a channel I/O pin, so the channel pin will not be usable forchannelI/Ofunctionwhenselectedastheexternalclocksource.Itistheuser’sresponsibilitytoavoid suchsettings.Ifthispinisusedasanexternalclocksource(CLKSB:CLKSA=1:1),thechannelcanstill be used in output compare mode as a software timer (ELSnB:ELSnA = 0:0). 16.2.1.2 TPMxCHn — TPM Channel n I/O Pin(s) Each TPM channel is associated with an I/O pin on the MCU. The function of this pin depends on the channelconfiguration.TheTPMpinssharewithgeneralpurposeI/Opins,whereeachpinhasaportdata registerbit,andadatadirectioncontrolbit,andtheporthasoptionalpassivepullupswhichmaybeenabled whenever a port pin is acting as an input. TheTPMchanneldoesnotcontroltheI/Opinwhen(ELSnB:ELSnA=0:0)orwhen(CLKSB:CLKSA= 0:0)soitnormallyrevertstogeneralpurposeI/Ocontrol.WhenCPWMS=1(andELSnB:ELSnAnot= 0:0),allchannelswithintheTPMareconfiguredforcenter-alignedPWMandtheTPMxCHnpinsareall controlled by the TPM system. When CPWMS=0, the MSnB:MSnA control bits determine whether the channel is configured for input capture, output compare, or edge-aligned PWM. Whenachannelisconfiguredforinputcapture(CPWMS=0,MSnB:MSnA=0:0andELSnB:ELSnAnot = 0:0), the TPMxCHn pin is forced to act as an edge-sensitive input to the TPM. ELSnB:ELSnA control bitsdeterminewhatpolarityedgeoredgeswilltriggerinput-captureevents.Asynchronizerbasedonthe busclockisusedtosynchronizeinputedgestothebusclock.Thisimpliestheminimumpulsewidth—that canbereliablydetected—onaninputcapturepinisfourbusclockperiods(withidealclockpulsesasnear as two bus clocks can be detected). TPM uses this pin as an input capture input to override the port data and data direction controls for the same pin. When a channel is configured for output compare (CPWMS=0, MSnB:MSnA = 0:1 and ELSnB:ELSnA not=0:0),theassociateddatadirectioncontrolisoverridden,theTPMxCHnpinisconsideredanoutput controlled by the TPM, and the ELSnB:ELSnA control bits determine how the pin is controlled. The remainingthreecombinationsofELSnB:ELSnAdeterminewhethertheTPMxCHnpinistoggled,cleared, or set each time the 16-bit channel value register matches the timer counter. Whentheoutputcomparetogglemodeisinitiallyselected,thepreviousvalueonthepinisdrivenoutuntil the next output compare event—then the pin is toggled. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 245

Chapter 16 Timer/PWM Module (S08TPMV3) When a channel is configured for edge-aligned PWM (CPWMS=0, MSnB=1 and ELSnB:ELSnA not = 0:0),thedatadirectionisoverridden,theTPMxCHnpinisforcedtobeanoutputcontrolledbytheTPM, and ELSnA controls the polarity of the PWM output signal on the pin. When ELSnB:ELSnA=1:0, the TPMxCHn pin is forced high at the start of each new period (TPMxCNT=0x0000), and the pin is forced low when the channel value register matches the timer counter. When ELSnA=1, the TPMxCHn pin is forced low at the start of each new period (TPMxCNT=0x0000), and the pin is forced high when the channel value register matches the timer counter. TPMxMODH:TPMxMODL = 0x0008 TPMxCnVH:TPMxCnVL = 0x0005 TPMxCNTH:TPMxCNTL ... 0 1 2 3 4 5 6 7 8 0 1 2 ... TPMxCHn CHnF BIT TOF BIT Figure16-3. High-True Pulse of an Edge-Aligned PWM TPMxMODH:TPMxMODL = 0x0008 TPMxCnVH:TPMxCnVL = 0x0005 TPMxCNTH:TPMxCNTL ... 0 1 2 3 4 5 6 7 8 0 1 2 ... TPMxCHn CHnF BIT TOF BIT Figure16-4.Low-True Pulse of an Edge-Aligned PWM MC9S08SH8MCUSeriesDataSheet,Rev.3 246 Freescale Semiconductor

Chapter 16 Timer/PWM Module (S08TPMV3) WhentheTPMisconfiguredforcenter-alignedPWM(andELSnB:ELSnAnot=0:0),thedatadirection forallchannelsinthisTPMareoverridden,theTPMxCHnpinsareforcedtobeoutputscontrolledbythe TPM, and the ELSnA bits control the polarity of each TPMxCHn output. If ELSnB:ELSnA=1:0, the corresponding TPMxCHn pin is cleared when the timer counter is counting up, and the channel value registermatchesthetimercounter;theTPMxCHnpinissetwhenthetimercounteriscountingdown,and thechannelvalueregistermatchesthetimercounter.IfELSnA=1,thecorrespondingTPMxCHnpinisset when the timer counter is counting up and the channel value register matches the timer counter; the TPMxCHnpinisclearedwhenthetimercounteriscountingdownandthechannelvalueregistermatches the timer counter. TPMxMODH:TPMxMODL = 0x0008 TPMxCnVH:TPMxCnVL = 0x0005 TPMxCNTH:TPMxCNTL ... 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 ... TPMxCHn CHnF BIT TOF BIT Figure16-5.High-True Pulse of a Center-Aligned PWM TPMxMODH:TPMxMODL = 0x0008 TPMxCnVH:TPMxCnVL = 0x0005 TPMxCNTH:TPMxCNTL ... 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 ... TPMxCHn CHnF BIT TOF BIT Figure16-6.Low-True Pulse of a Center-Aligned PWM MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 247

Chapter 16 Timer/PWM Module (S08TPMV3) 16.3 Register Definitio Thissectionconsistsofregisterdescriptionsinaddressorder.AtypicalMCUsystemmaycontainmultiple TPMs,andeachTPMmayhaveonetoeightchannels,soregisternamesincludeplaceholdercharactersto identify which TPM and which channel is being referenced. For example, TPMxCnSC refers to timer (TPM) x, channel n. TPM1C2SC would be the status and control register for channel 2 of timer 1. 16.3.1 TPM Status and Control Register (TPMxSC) TPMxSC contains the overflow status flag and control bits used to configure the interrupt enable, TPM configuration, clock source, and prescale factor. These controls relate to all channels within this timer module. 7 6 5 4 3 2 1 0 R TOF TOIE CPWMS CLKSB CLKSA PS2 PS1 PS0 W 0 Reset 0 0 0 0 0 0 0 0 Figure16-7. TPM Status and Control Register (TPMxSC) Table16-3. TPMxSC Field Descriptions Field Description 7 Timeroverflowflag.Thisread/writeflagissetwhentheTPMcounterresetsto0x0000afterreachingthemodulo TOF value programmed in the TPM counter modulo registers. Clear TOF by reading the TPM status and control register when TOF is set and then writing a logic 0 to TOF. If another TPM overflow occurs before the clearing sequence is complete, the sequence is reset so TOF would remain set after the clear sequence was completed for the earlier TOF. This is done so a TOF interrupt request cannot be lost during the clearing sequence for a previous TOF. Reset clears TOF. Writing a logic 1 to TOF has no effect. 0 TPM counter has not reached modulo value or overflow 1 TPM counter has overflowed 6 Timeroverflowinterruptenable.Thisread/writebitenablesTPMoverflowinterrupts.IfTOIEisset,aninterruptis TOIE generated when TOF equals one. Reset clears TOIE. 0 TOF interrupts inhibited (use for software polling) 1 TOF interrupts enabled 5 Center-aligned PWM select. When present, this read/write bit selects CPWM operating mode. By default, the CPWMS TPMoperatesinup-countingmodeforinputcapture,outputcompare,andedge-alignedPWMfunctions.Setting CPWMSreconfigurestheTPMtooperateinup/downcountingmodeforCPWMfunctions.ResetclearsCPWMS. 0 All channels operate as input capture, output compare, or edge-aligned PWM mode as selected by the MSnB:MSnA control bits in each channel’s status and control register. 1 All channels operate in center-aligned PWM mode. MC9S08SH8MCUSeriesDataSheet,Rev.3 248 Freescale Semiconductor

Chapter 16 Timer/PWM Module (S08TPMV3) Table16-3. TPMxSC Field Descriptions (continued) Field Description 4–3 Clock source selects. As shown inTable16-4, this 2-bit field is used to disable the TPM system or select one of CLKS[B:A] three clock sources to drive the counter prescaler. The fixed system clock source is only meaningful in systems withaPLL-basedorFLL-basedsystemclock.WhenthereisnoPLLorFLL,thefixed-systemclocksourceisthe sameasthebusrateclock.TheexternalsourceissynchronizedtothebusclockbyTPMmodule,andthefixed system clock source (when a PLL or FLL is present) is synchronized to the bus clock by an on-chip synchronizationcircuit.WhenaPLLorFLLispresentbutnotenabled,thefixed-systemclocksourceisthesame as the bus-rate clock. 2–0 Prescale factor select. This 3-bit field selects one of 8 division factors for the TPM clock input as shown in PS[2:0] Table16-5.Thisprescalerislocatedafteranyclocksourcesynchronizationorclocksourceselectionsoitaffects the clock source selected to drive the TPM system. The new prescale factor will affect the clock source on the next system clock cycle after the new value is updated into the register bits. Table16-4. TPM-Clock-Source Selection CLKSB:CLKSA TPM Clock Source to Prescaler Input 00 No clock selected (TPM counter disable) 01 Bus rate clock 10 Fixed system clock 11 External source Table16-5. Prescale Factor Selection PS2:PS1:PS0 TPM Clock Source Divided-by 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 16.3.2 TPM-Counter Registers (TPMxCNTH:TPMxCNTL) Thetworead-onlyTPMcounterregisterscontainthehighandlowbytesofthevalueintheTPMcounter. Readingeitherbyte(TPMxCNTHorTPMxCNTL)latchesthecontentsofbothbytesintoabufferwhere they remain latched until the other half is read. This allows coherent 16-bit reads in either big-endian or little-endian order which makes this more friendly to various compiler implementations. The coherency mechanism is automatically restarted by an MCU reset or any write to the timer status/control register (TPMxSC). MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 249

Chapter 16 Timer/PWM Module (S08TPMV3) ResetclearstheTPMcounterregisters.WritinganyvaluetoTPMxCNTHorTPMxCNTLalsoclearsthe TPM counter (TPMxCNTH:TPMxCNTL) and resets the coherency mechanism, regardless of the data involved in the write. 7 6 5 4 3 2 1 0 R Bit 15 14 13 12 11 10 9 Bit 8 W Any write to TPMxCNTH clears the 16-bit counter Reset 0 0 0 0 0 0 0 0 Figure16-8. TPM Counter Register High (TPMxCNTH) 7 6 5 4 3 2 1 0 R Bit 7 6 5 4 3 2 1 Bit 0 W Any write to TPMxCNTL clears the 16-bit counter Reset 0 0 0 0 0 0 0 0 Figure16-9. TPM Counter Register Low (TPMxCNTL) WhenBDMisactive,thetimercounterisfrozen(thisisthevaluethatwillbereadbyuser);thecoherency mechanismisfrozensuchthatthebufferlatchesremaininthestatetheywereinwhentheBDMbecame active, even if one or both counter halves are read while BDM is active. This assures that if the user was inthemiddleofreadinga16-bitregisterwhenBDMbecameactive,itwillreadtheappropriatevaluefrom the other half of the 16-bit value after returning to normal execution. In BDM mode, writing any value to TPMxSC, TPMxCNTH or TPMxCNTL registers resets the read coherency mechanism of the TPMxCNTH:L registers, regardless of the data involved in the write. 16.3.3 TPM Counter Modulo Registers (TPMxMODH:TPMxMODL) The read/write TPM modulo registers contain the modulo value for the TPM counter. After the TPM counterreachesthemodulovalue,theTPMcounterresumescountingfrom0x0000atthenextclock,and theoverflowflag(TOF)becomesset.WritingtoTPMxMODHorTPMxMODLinhibitstheTOFbitand overflowinterruptsuntiltheotherbyteiswritten.ResetsetstheTPMcountermoduloregistersto0x0000 which results in a free running timer counter (modulo disabled). Writingtoeitherbyte(TPMxMODHorTPMxMODL)latchesthevalueintoabufferandtheregistersare updated with the value of their write buffer according to the value of CLKSB:CLKSA bits, so: • If (CLKSB:CLKSA = 0:0), then the registers are updated when the second byte is written • If(CLKSB:CLKSAnot=0:0),thentheregistersareupdatedafterbothbyteswerewritten,andthe TPMcounterchangesfrom(TPMxMODH:TPMxMODL-1)to(TPMxMODH:TPMxMODL).If theTPMcounterisafree-runningcounter,theupdateismadewhentheTPMcounterchangesfrom 0xFFFE to 0xFFFF The latching mechanism may be manually reset by writing to the TPMxSC address (whether BDM is active or not). MC9S08SH8MCUSeriesDataSheet,Rev.3 250 Freescale Semiconductor

Chapter 16 Timer/PWM Module (S08TPMV3) When BDM is active, the coherency mechanism is frozen (unless reset by writing to TPMxSC register) suchthatthebufferlatchesremaininthestatetheywereinwhentheBDMbecameactive,evenifoneor both halves of the modulo register are written while BDM is active. Any write to the modulo registers bypasses the buffer latches and directly writes to the modulo register while BDM is active. 7 6 5 4 3 2 1 0 R Bit 15 14 13 12 11 10 9 Bit 8 W Reset 0 0 0 0 0 0 0 0 Figure16-10. TPM Counter Modulo Register High (TPMxMODH) 7 6 5 4 3 2 1 0 R Bit 7 6 5 4 3 2 1 Bit 0 W Reset 0 0 0 0 0 0 0 0 Figure16-11. TPM Counter Modulo Register Low (TPMxMODL) ResettheTPMcounterbeforewritingtotheTPMmoduloregisterstoavoidconfusionaboutwhenthefirst counter overflow will occur. 16.3.4 TPM Channel n Status and Control Register (TPMxCnSC) TPMxCnSC contains the channel-interrupt-status flag and control bits used to configure the interrupt enable, channel configuration, and pin function. 7 6 5 4 3 2 1 0 R CHnF 0 0 CHnIE MSnB MSnA ELSnB ELSnA W 0 Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure16-12. TPM Channel n Status and Control Register (TPMxCnSC) MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 251

Chapter 16 Timer/PWM Module (S08TPMV3) Table16-6. TPMxCnSC Field Descriptions Field Description 7 Channelnflag.Whenchannelnisaninput-capturechannel,thisread/writebitissetwhenanactiveedgeoccurs CHnF onthechannelnpin.Whenchannelnisanoutputcompareoredge-aligned/center-alignedPWMchannel,CHnF issetwhenthevalueintheTPMcounterregistersmatchesthevalueintheTPMchannelnvalueregisters.When channel n is an edge-aligned/center-aligned PWM channel and the duty cycle is set to 0% or 100%, CHnF will not be set even when the value in the TPM counter registers matches the value in the TPM channel n value registers. AcorrespondinginterruptisrequestedwhenCHnFissetandinterruptsareenabled(CHnIE=1).ClearCHnFby reading TPMxCnSC while CHnF is set and then writing a logic 0 to CHnF. If another interrupt request occurs before the clearing sequence is complete, the sequence is reset so CHnF remains set after the clear sequence completedfortheearlierCHnF.ThisisdonesoaCHnFinterruptrequestcannotbelostduetoclearingaprevious CHnF. Reset clears the CHnF bit. Writing a logic 1 to CHnF has no effect. 0 No input capture or output compare event occurred on channel n 1 Input capture or output compare event on channel n 6 Channel n interrupt enable. This read/write bit enables interrupts from channel n. Reset clears CHnIE. CHnIE 0 Channel n interrupt requests disabled (use for software polling) 1 Channel n interrupt requests enabled 5 ModeselectBforTPMchanneln.WhenCPWMS=0,MSnB=1configuresTPMchannelnforedge-alignedPWM MSnB mode. Refer to the summary of channel mode and setup controls inTable16-7. 4 Mode select A for TPM channel n. When CPWMS=0 and MSnB=0, MSnA configures TPM channel n for MSnA input-capture mode or output compare mode. Refer toTable16-7 for a summary of channel mode and setup controls. Note:If the associated port pin is not stable for at least two bus clock cycles before changing to input capture mode, it is possible to get an unexpected indication of an edge trigger. 3–2 Edge/levelselectbits.DependingupontheoperatingmodeforthetimerchannelassetbyCPWMS:MSnB:MSnA ELSnB andshowninTable16-7,thesebitsselectthepolarityoftheinputedgethattriggersaninputcaptureevent,select ELSnA the level that will be driven in response to an output compare match, or select the polarity of the PWM output. SettingELSnB:ELSnAto0:0configurestherelatedtimerpinasageneralpurposeI/Opinnotrelatedtoanytimer functions.Thisfunctionistypicallyusedtotemporarilydisableaninputcapturechannelortomakethetimerpin availableasageneralpurposeI/Opinwhentheassociatedtimerchannelissetupasasoftwaretimerthatdoes not require the use of a pin. Table16-7. Mode, Edge, and Level Selection CPWMS MSnB:MSnA ELSnB:ELSnA Mode Configuratio X XX 00 Pin not used for TPM - revert to general purpose I/O or other peripheral control MC9S08SH8MCUSeriesDataSheet,Rev.3 252 Freescale Semiconductor

Chapter 16 Timer/PWM Module (S08TPMV3) Table16-7. Mode, Edge, and Level Selection CPWMS MSnB:MSnA ELSnB:ELSnA Mode Configuratio 0 00 01 Input capture Captureonrisingedge only 10 Captureonfallingedge only 11 Capture on rising or falling edge 01 01 Output compare Toggle output on compare 10 Clearoutput on compare 11 Setoutput on compare 1X 10 Edge-aligned High-true pulses (clear PWM output on compare) X1 Low-true pulses (set output on compare) 1 XX 10 Center-aligned High-true pulses (clear PWM output on compare-up) X1 Low-true pulses (set output on compare-up) 16.3.5 TPM Channel Value Registers (TPMxCnVH:TPMxCnVL) These read/write registers contain the captured TPM counter value of the input capture function or the output compare value for the output compare or PWM functions. The channel registers are cleared by reset. 7 6 5 4 3 2 1 0 R Bit 15 14 13 12 11 10 9 Bit 8 W Reset 0 0 0 0 0 0 0 0 Figure16-13. TPM Channel Value Register High (TPMxCnVH) 7 6 5 4 3 2 1 0 R Bit 7 6 5 4 3 2 1 Bit 0 W Reset 0 0 0 0 0 0 0 0 Figure16-14. TPM Channel Value Register Low (TPMxCnVL) Ininputcapturemode,readingeitherbyte(TPMxCnVHorTPMxCnVL)latchesthecontentsofbothbytes into a buffer where they remain latched until the other half is read. This latching mechanism also resets MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 253

Chapter 16 Timer/PWM Module (S08TPMV3) (becomesunlatched)whentheTPMxCnSCregisteriswritten(whetherBDMmodeisactiveornot).Any write to the channel registers will be ignored during the input capture mode. WhenBDMisactive,thecoherencymechanismisfrozen(unlessresetbywritingtoTPMxCnSCregister) suchthatthebufferlatchesremaininthestatetheywereinwhentheBDMbecameactive,evenifoneor both halves of the channel register are read while BDM is active. This assures that if the user was in the middle of reading a 16-bit register when BDM became active, it will read the appropriate value from the other half of the 16-bit value after returning to normal execution. The value read from the TPMxCnVH and TPMxCnVL registers in BDM mode is the value of these registers and not the value of their read buffer. InoutputcompareorPWMmodes,writingtoeitherbyte(TPMxCnVHorTPMxCnVL)latchesthevalue into a buffer. After both bytes are written, they are transferred as a coherent 16-bit value into the timer-channel registers according to the value of CLKSB:CLKSA bits and the selected mode, so: • If (CLKSB:CLKSA = 0:0), then the registers are updated when the second byte is written. • If(CLKSB:CLKSAnot=0:0andinoutputcomparemode)thentheregistersareupdatedafterthe secondbyteiswrittenandonthenextchangeoftheTPMcounter(endoftheprescalercounting). • If(CLKSB:CLKSAnot=0:0andinEPWMorCPWMmodes),thentheregistersareupdatedafter thebothbyteswerewritten,andtheTPMcounterchangesfrom(TPMxMODH:TPMxMODL-1) to (TPMxMODH:TPMxMODL). If the TPM counter is a free-running counter then the update is made when the TPM counter changes from 0xFFFE to 0xFFFF. The latching mechanism may be manually reset by writing to the TPMxCnSC register (whether BDM mode is active or not). This latching mechanism allows coherent 16-bit writes in either big-endian or little-endian order which is friendly to various compiler implementations. When BDM is active, the coherency mechanism is frozen such that the buffer latches remain in the state they were in when the BDM became active even if one or both halves of the channel register are written while BDM is active. Any write to the channel registers bypasses the buffer latches and directly write to thechannelregisterwhileBDMisactive.ThevalueswrittentothechannelregisterwhileBDMisactive are used for PWM & output compare operation once normal execution resumes. Writes to the channel registerswhileBDMisactivedonotinterferewithpartialcompletionofacoherencysequence.Afterthe coherencymechanismhasbeenfullyexercised,thechannelregistersareupdatedusingthebufferedvalues written (while BDM was not active) by the user. 16.4 Functional Description AllTPMfunctionsareassociatedwithacentral16-bitcounterwhichallowsflexibleselectionoftheclock source and prescale factor. There is also a 16-bit modulo register associated with the main counter. The CPWMS control bit chooses between center-aligned PWM operation for all channels in the TPM (CPWMS=1)orgeneralpurposetimingfunctions(CPWMS=0)whereeachchannelcanindependentlybe configuredtooperateininputcapture,outputcompare,oredge-alignedPWMmode.TheCPWMScontrol bit is located in the main TPM status and control register because it affects all channels within the TPM and influences the way the main counter operates. (In CPWM mode, the counter changes to an up/down mode rather than the up-counting mode used for general purpose timer functions.) MC9S08SH8MCUSeriesDataSheet,Rev.3 254 Freescale Semiconductor

Chapter 16 Timer/PWM Module (S08TPMV3) The following sections describe the main counter and each of the timer operating modes (input capture, output compare, edge-aligned PWM, and center-aligned PWM). Because details of pin operation and interrupt activity depend upon the operating mode, these topics will be covered in the associated mode explanation sections. 16.4.1 Counter All timer functions are based on the main 16-bit counter (TPMxCNTH:TPMxCNTL). This section discusses selection of the clock source, end-of-count overflow, up-counting vs. up/down counting, and manual counter reset. 16.4.1.1 Counter Clock Source The 2-bit field, CLKSB:CLKSA, in the timer status and control register (TPMxSC) selects one of three possibleclocksourcesorOFF(whicheffectivelydisablestheTPM).SeeTable 16-4.AfteranyMCUreset, CLKSB:CLKSA=0:0 so no clock source is selected, and the TPM is in a very low power state. These controlbitsmaybereadorwrittenatanytimeanddisablingthetimer(writing00totheCLKSB:CLKSA field) does not affect the values in the counter or other timer registers. Table16-8. TPM Clock Source Selection CLKSB:CLKSA TPM Clock Source to Prescaler Input 00 No clock selected (TPM counter disabled) 01 Bus rate clock 10 Fixed system clock 11 External source The bus rate clock is the main system bus clock for the MCU. This clock source requires no synchronization because it is the clock that is used for all internal MCU activities including operation of the CPU and buses. In MCUs that have no PLL and FLL or the PLL and FLL are not engaged, the fixed system clock source is the same as the bus-rate-clock source, and it does not go through a synchronizer. When a PLL or FLL ispresentandengaged,asynchronizerisrequiredbetweenthecrystaldivided-bytwoclocksourceandthe timercountersocountertransitionswillbeproperlyalignedtobus-clocktransitions.Asynchronizerwill be used at chip level to synchronize the crystal-related source clock to the bus clock. TheexternalclocksourcemaybeconnectedtoanyTPMchannelpin.Thisclocksourcealwayshastopass throughasynchronizertoassurethatcountertransitionsareproperlyalignedtobusclocktransitions.The bus-rateclockdrivesthesynchronizer;therefore,tomeetNyquistcriteriaevenwithjitter,thefrequencyof theexternalclocksourcemustnotbefasterthanthebusratedivided-byfour.Withidealclockstheexternal clock can be as fast as bus clock divided by four. WhentheexternalclocksourcesharestheTPMchannelpin,thispinshouldnotbeusedforotherchannel timing functions. For example, it would be ambiguous to configure channel 0 for input capture when the TPM channel 0 pin was also being used as the timer external clock source. (It is the user’s responsibility MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 255

Chapter 16 Timer/PWM Module (S08TPMV3) toavoidsuchsettings.)TheTPMchannelcouldstillbeusedinoutputcomparemodeforsoftwaretiming functions (pin controls set not to affect the TPM channel pin). 16.4.1.2 Counter Overfl w and Modulo Reset An interrupt flag and enable are associated with the 16-bit main counter. The flag (TOF) is a software-accessible indication that the timer counter has overflowed. The enable signal selects between software polling (TOIE=0) where no hardware interrupt is generated, or interrupt-driven operation (TOIE=1) where a static hardware interrupt is generated whenever the TOF flag is equal to one. The conditions causing TOF to become set depend on whether the TPM is configured for center-aligned PWM (CPWMS=1). In the simplest mode, there is no modulus limit and the TPM is not in CPWMS=1 mode.Inthiscase,the16-bittimercountercountsfrom0x0000through0xFFFFandoverflowsto0x0000 onthenextcountingclock.TOFbecomessetatthetransitionfrom0xFFFFto0x0000.Whenamodulus limitisset,TOFbecomessetatthetransitionfromthevaluesetinthemodulusregisterto0x0000.When the TPM is in center-aligned PWM mode (CPWMS=1), the TOF flag gets set as the counter changes direction at the end of the count value set in the modulus register (that is, at the transition from the value set in the modulus register to the next lower count value). This corresponds to the end of a PWM period (the 0x0000 count value corresponds to the center of a period). 16.4.1.3 Counting Modes Themaintimercounterhastwocountingmodes.Whencenter-alignedPWMisselected(CPWMS=1),the counter operates in up/down counting mode. Otherwise, the counter operates as a simple up counter. As an up counter, the timer counter counts from 0x0000 through its terminal count and then continues with 0x0000. The terminal count is 0xFFFF or a modulus value in TPMxMODH:TPMxMODL. Whencenter-alignedPWMoperationisspecified,thecountercountsupfrom0x0000throughitsterminal countandthendownto0x0000whereitchangesbacktoupcounting.Both0x0000andtheterminalcount valuearenormallengthcounts(onetimerclockperiodlong).Inthismode,thetimeroverflowflag(TOF) becomes set at the end of the terminal-count period (as the count changes to the next lower count value). 16.4.1.4 Manual Counter Reset The main timer counter can be manually reset at any time by writing any value to either half of TPMxCNTHorTPMxCNTL.Resettingthecounterinthismanneralsoresetsthecoherencymechanism in case only half of the counter was read before resetting the count. 16.4.2 Channel Mode Selection Provided CPWMS=0, the MSnB and MSnA control bits in the channel n status and control registers determine the basic mode of operation for the corresponding channel. Choices include input capture, output compare, and edge-aligned PWM. MC9S08SH8MCUSeriesDataSheet,Rev.3 256 Freescale Semiconductor

Chapter 16 Timer/PWM Module (S08TPMV3) 16.4.2.1 Input Capture Mode Withtheinput-capturefunction,theTPMcancapturethetimeatwhichanexternaleventoccurs.Whenan activeedgeoccursonthepinofaninput-capturechannel,theTPMlatchesthecontentsoftheTPMcounter intothechannel-valueregisters(TPMxCnVH:TPMxCnVL).Risingedges,fallingedges,oranyedgemay be chosen as the active edge that triggers an input capture. In input capture mode, the TPMxCnVH and TPMxCnVL registers are read only. When either half of the 16-bit capture register is read, the other half is latched into a buffer to support coherent 16-bit accesses in big-endian or little-endian order. The coherency sequence can be manually reset by writing to the channel status/control register (TPMxCnSC). An input capture event sets a flag bit (CHnF) which may optionally generate a CPU interrupt request. WhileinBDM,theinputcapturefunctionworksasconfiguredbytheuser.Whenanexternaleventoccurs, the TPM latches the contents of the TPM counter (which is frozen because of the BDM mode) into the channel value registers and sets the flag bit. 16.4.2.2 Output Compare Mode With the output-compare function, the TPM can generate timed pulses with programmable position, polarity,duration,andfrequency.Whenthecounterreachesthevalueinthechannel-valueregistersofan output-compare channel, the TPM can set, clear, or toggle the channel pin. Inoutputcomparemode,valuesaretransferredtothecorrespondingtimerchannelregistersonlyafterboth 8-bit halves of a 16-bit register have been written and according to the value of CLKSB:CLKSA bits, so: • If (CLKSB:CLKSA = 0:0), the registers are updated when the second byte is written • If (CLKSB:CLKSA not = 0:0), the registers are updated at the next change of the TPM counter (end of the prescaler counting) after the second byte is written. The coherency sequence can be manually reset by writing to the channel status/control register (TPMxCnSC). An output compare event sets a flag bit (CHnF) which may optionally generate a CPU-interrupt request. 16.4.2.3 Edge-Aligned PWM Mode This type of PWM output uses the normal up-counting mode of the timer counter (CPWMS=0) and can be used when other channels in the same TPM are configured for input capture or output compare functions. The period of this PWM signal is determined by the value of the modulus register (TPMxMODH:TPMxMODL) plus 1. The duty cycle is determined by the setting in the timer channel register (TPMxCnVH:TPMxCnVL). The polarity of this PWM signal is determined by the setting in the ELSnA control bit. 0% and 100% duty cycle cases are possible. The output compare value in the TPM channel registers determines the pulse width (duty cycle) of the PWMsignal(Figure16-15).Thetimebetweenthemodulusoverflowandtheoutputcompareisthepulse width.IfELSnA=0,thecounteroverflowforcesthePWMsignalhigh,andtheoutputcompareforcesthe PWMsignallow.IfELSnA=1,thecounteroverflowforcesthePWMsignallow,andtheoutputcompare forces the PWM signal high. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 257

Chapter 16 Timer/PWM Module (S08TPMV3) OVERFLOW OVERFLOW OVERFLOW PERIOD PULSE WIDTH TPMxCHn OUTPUT OUTPUT OUTPUT COMPARE COMPARE COMPARE Figure16-15. PWM Period and Pulse Width (ELSnA=0) Whenthechannelvalueregisterissetto0x0000,thedutycycleis0%.100%dutycyclecanbeachieved by setting the timer-channel register (TPMxCnVH:TPMxCnVL) to a value greater than the modulus setting. This implies that the modulus setting must be less than 0xFFFF in order to get 100% duty cycle. BecausetheTPMmaybeusedinan8-bitMCU,thesettingsinthetimerchannelregistersarebufferedto ensurecoherent16-bitupdatesandtoavoidunexpectedPWMpulsewidths.Writestoanyoftheregisters TPMxCnVHandTPMxCnVL,actuallywritetobufferregisters.Inedge-alignedPWMmode,valuesare transferredtothecorrespondingtimer-channelregistersaccordingtothevalueofCLKSB:CLKSAbits,so: • If (CLKSB:CLKSA = 0:0), the registers are updated when the second byte is written • If(CLKSB:CLKSAnot=0:0),theregistersareupdatedafterthebothbyteswerewritten,andthe TPMcounterchangesfrom(TPMxMODH:TPMxMODL-1)to(TPMxMODH:TPMxMODL).If theTPMcounterisafree-runningcounterthentheupdateismadewhentheTPMcounterchanges from 0xFFFE to 0xFFFF. 16.4.2.4 Center-Aligned PWM Mode ThistypeofPWMoutputusestheup/downcountingmodeofthetimercounter(CPWMS=1).Theoutput compare value in TPMxCnVH:TPMxCnVL determines the pulse width (duty cycle) of the PWM signal whiletheperiodisdeterminedbythevalueinTPMxMODH:TPMxMODL.TPMxMODH:TPMxMODL shouldbekeptintherangeof0x0001to0x7FFFbecausevaluesoutsidethisrangecanproduceambiguous results. ELSnA will determine the polarity of the CPWM output. pulse width = 2 x (TPMxCnVH:TPMxCnVL) period = 2 x (TPMxMODH:TPMxMODL); TPMxMODH:TPMxMODL=0x0001-0x7FFF Ifthechannel-valueregisterTPMxCnVH:TPMxCnVLiszeroornegative(bit15set),thedutycyclewill be 0%. If TPMxCnVH:TPMxCnVL is a positive value (bit 15 clear) and is greater than the (non-zero) modulus setting, the duty cycle will be 100% because the duty cycle compare will never occur. This impliestheusablerangeofperiodssetbythemodulusregisteris0x0001through0x7FFE(0x7FFFifyou donotneedtogenerate100%dutycycle).Thisisnotasignificantlimitation.Theresultingperiodwould be much longer than required for normal applications. TPMxMODH:TPMxMODL=0x0000 is a special case that should not be used with center-aligned PWM mode.WhenCPWMS=0,thiscasecorrespondstothecounterrunningfreefrom0x0000through0xFFFF, but when CPWMS=1 the counter needs a valid match to the modulus register somewhere other than at 0x0000 in order to change directions from up-counting to down-counting. MC9S08SH8MCUSeriesDataSheet,Rev.3 258 Freescale Semiconductor

Chapter 16 Timer/PWM Module (S08TPMV3) TheoutputcomparevalueintheTPMchannelregisters(times2)determinesthepulsewidth(dutycycle) of the CPWM signal (Figure16-16). If ELSnA=0, a compare occurred while counting up forces the CPWM output signal low and a compare occurred while counting down forces the output high. The counter counts up until it reaches the modulo setting in TPMxMODH:TPMxMODL, then counts down until it reaches zero. This sets the period equal to two times TPMxMODH:TPMxMODL. OUTPUT COUNT= 0 OUTPUT COUNT= COMPARE COMPARE COUNT= TPMxMODH:TPMxMODL (COUNT DOWN) (COUNT UP) TPMxMODH:TPMxMODL TPMxCHn PULSE WIDTH 2 x TPMxCnVH:TPMxCnVL PERIOD 2 x TPMxMODH:TPMxMODL Figure16-16. CPWM Period and Pulse Width (ELSnA=0) Center-alignedPWMoutputstypicallyproducelessnoisethanedge-alignedPWMsbecausefewerI/Opin transitionsarelinedupatthesamesystemclockedge.ThistypeofPWMisalsorequiredforsometypes of motor drives. Input capture, output compare, and edge-aligned PWM functions do not make sense when the counter is operatinginup/downcountingmodesothisimpliesthatallactivechannelswithinaTPMmustbeusedin CPWM mode when CPWMS=1. TheTPMmaybeusedinan8-bitMCU.Thesettingsinthetimerchannelregistersarebufferedtoensure coherent 16-bit updates and to avoid unexpected PWM pulse widths. Writes to any of the registers TPMxMODH, TPMxMODL, TPMxCnVH, and TPMxCnVL, actually write to buffer registers. Incenter-alignedPWMmode,theTPMxCnVH:Lregistersareupdatedwiththevalueoftheirwritebuffer according to the value of CLKSB:CLKSA bits, so: • If (CLKSB:CLKSA = 0:0), the registers are updated when the second byte is written • If(CLKSB:CLKSAnot=0:0),theregistersareupdatedafterthebothbyteswerewritten,andthe TPMcounterchangesfrom(TPMxMODH:TPMxMODL-1)to(TPMxMODH:TPMxMODL).If theTPMcounterisafree-runningcounter,theupdateismadewhentheTPMcounterchangesfrom 0xFFFE to 0xFFFF. When TPMxCNTH:TPMxCNTL=TPMxMODH:TPMxMODL, the TPM can optionally generate a TOF interrupt (at the end of this count). Writing to TPMxSC cancels any values written to TPMxMODH and/or TPMxMODL and resets the coherencymechanismforthemoduloregisters.WritingtoTPMxCnSCcancelsanyvalueswrittentothe channel value registers and resets the coherency mechanism for TPMxCnVH:TPMxCnVL. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 259

Chapter 16 Timer/PWM Module (S08TPMV3) 16.5 Reset Overview 16.5.1 General The TPM is reset whenever any MCU reset occurs. 16.5.2 Description of Reset Operation ResetclearstheTPMxSCregisterwhichdisablesclockstotheTPManddisablestimeroverflowinterrupts (TOIE=0). CPWMS, MSnB, MSnA, ELSnB, and ELSnA are all cleared which configures all TPM channelsforinput-captureoperationwiththeassociatedpinsdisconnectedfromI/Opinlogic(soallMCU pins related to the TPM revert to general purpose I/O pins). 16.6 Interrupts 16.6.1 General TheTPMgeneratesanoptionalinterruptforthemaincounteroverflowandaninterruptforeachchannel. The meaning of channel interrupts depends on each channel’s mode of operation. If the channel is configured for input capture, the interrupt flag is set each time the selected input capture edge is recognized.IfthechannelisconfiguredforoutputcompareorPWMmodes,theinterruptflagisseteach time the main timer counter matches the value in the 16-bit channel value register. AllTPMinterruptsarelistedinTable16-9whichshowstheinterruptname,thenameofanylocalenable thatcanblocktheinterruptrequestfromleavingtheTPMandgettingrecognizedbytheseparateinterrupt processing logic. Table16-9. Interrupt Summary Local Interrupt Source Description Enable TOF TOIE Counter overflow Seteachtimethetimercounterreachesitsterminal count (at transition to next count value which is usually 0x0000) CHnF CHnIE Channel event An input capture or output compare event took place on channel n The TPM module will provide a high-true interrupt signal. Vectors and priorities are determined at chip integrationtimeintheinterruptmodulesorefertotheuser’sguidefortheinterruptmoduleortothechip’s complete documentation for details. 16.6.2 Description of Interrupt Operation For each interrupt source in the TPM, a flag bit is set upon recognition of the interrupt condition such as timer overflow, channel-input capture, or output-compare events. This flag may be read (polled) by softwaretodeterminethattheactionhasoccurred,oranassociatedenablebit(TOIEorCHnIE)canbeset MC9S08SH8MCUSeriesDataSheet,Rev.3 260 Freescale Semiconductor

Chapter 16 Timer/PWM Module (S08TPMV3) toenablehardwareinterruptgeneration.Whiletheinterruptenablebitisset,astaticinterruptwillgenerate whenever the associated interrupt flag equals one. The user’s software must perform a sequence of steps to clear the interrupt flag before returning from the interrupt-service routine. TPM interrupt flags are cleared by a two-step process including a read of the flag bit while it is set (1) followedbyawriteofzero(0)tothebit.Ifaneweventisdetectedbetweenthesetwosteps,thesequence isresetandtheinterruptflagremainssetafterthesecondsteptoavoidthepossibilityofmissingthenew event. 16.6.2.1 Timer Overfl w Interrupt (TOF) Description The meaning and details of operation for TOF interrupts varies slightly depending upon the mode of operation of the TPM system (general purpose timing functions versus center-aligned PWM operation). The flag is cleared by the two step sequence described above. 16.6.2.1.1 Normal Case Normally TOF is set when the timer counter changes from 0xFFFF to 0x0000. When the TPM is not configuredforcenter-alignedPWM(CPWMS=0),TOFgetssetwhenthetimercounterchangesfromthe terminalcount(thevalueinthemoduloregister)to0x0000.Thiscasecorrespondstothenormalmeaning of counter overflow. 16.6.2.1.2 Center-Aligned PWM Case When CPWMS=1, TOF gets set when the timer counter changes direction from up-counting to down-counting at the end of the terminal count (the value in the modulo register). In this case the TOF corresponds to the end of a PWM period. 16.6.2.2 Channel Event Interrupt Description Themeaningofchannelinterruptsdependsonthechannel’scurrentmode(input-capture,output-compare, edge-aligned PWM, or center-aligned PWM). 16.6.2.2.1 Input Capture Events Whenachannelisconfiguredasaninputcapturechannel,theELSnB:ELSnAcontrolbitsselectnoedge (off),risingedges,fallingedgesoranyedgeastheedgewhichtriggersaninputcaptureevent.Whenthe selected edge is detected, the interrupt flag is set. The flag is cleared by the two-step sequence described inSection16.6.2, “Description of Interrupt Operation.” 16.6.2.2.2 Output Compare Events When a channel is configured as an output compare channel, the interrupt flag is set each time the main timer counter matches the 16-bit value in the channel value register. The flag is cleared by the two-step sequence describedSection16.6.2, “Description of Interrupt Operation.” MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 261

Chapter 16 Timer/PWM Module (S08TPMV3) 16.6.2.2.3 PWM End-of-Duty-Cycle Events For channels configured for PWM operation there are two possibilities. When the channel is configured foredge-alignedPWM,thechannelflaggetssetwhenthetimercountermatchesthechannelvalueregister which marks the end of the active duty cycle period. When the channel is configured for center-aligned PWM, the timer count matches the channel value register twice during each PWM cycle. In this CPWM case, the channel flag is set at the start and at the end of the active duty cycle period which are the times when the timer counter matches the channel value register. The flag is cleared by the two-step sequence describedSection16.6.2, “Description of Interrupt Operation.” 16.7 The Differences from TPM v2 to TPM v3 1. Write to TPMxCNTH:L registers (Section16.3.2, “TPM-Counter Registers (TPMxCNTH:TPMxCNTL)) [SE110-TPM case 7] Any write to TPMxCNTH or TPMxCNTL registers in TPM v3 clears the TPM counter (TPMxCNTH:L)andtheprescalercounter.Instead,intheTPMv2onlytheTPMcounteriscleared in this case. 2. Read of TPMxCNTH:L registers (Section16.3.2, “TPM-Counter Registers (TPMxCNTH:TPMxCNTL)) — In TPM v3, any read of TPMxCNTH:L registers during BDM mode returns the value of the TPM counter that is frozen. In TPM v2, if only one byte of the TPMxCNTH:L registers was read before the BDM mode became active, then any read of TPMxCNTH:L registers during BDM mode returns the latched value of TPMxCNTH:L from the read buffer instead of the frozen TPM counter value. — This read coherency mechanism is cleared in TPM v3 in BDM mode if there is a write to TPMxSC,TPMxCNTHorTPMxCNTL.Instead,intheseconditionstheTPMv2doesnotclear this read coherency mechanism. 3. Read of TPMxCnVH:L registers (Section16.3.5, “TPM Channel Value Registers (TPMxCnVH:TPMxCnVL)) — In TPM v3, any read of TPMxCnVH:L registers during BDM mode returns the value of the TPMxCnVH:L register. In TPM v2, if only one byte of the TPMxCnVH:L registers was read before the BDM mode became active, then any read of TPMxCnVH:L registers during BDM mode returns the latched value of TPMxCNTH:L from the read buffer instead of the value in the TPMxCnVH:L registers. — This read coherency mechanism is cleared in TPM v3 in BDM mode if there is a write to TPMxCnSC. Instead, in this condition the TPM v2 does not clear this read coherency mechanism. 4. Write to TPMxCnVH:L registers — Input Capture Mode (Section16.4.2.1, “Input Capture Mode) In this mode the TPM v3 does not allow the writes to TPMxCnVH:L registers. Instead, the TPM v2 allows these writes. — Output Compare Mode (Section16.4.2.2, “Output Compare Mode) MC9S08SH8MCUSeriesDataSheet,Rev.3 262 Freescale Semiconductor

Chapter 16 Timer/PWM Module (S08TPMV3) In this mode and if (CLKSB:CLKSA not = 0:0), the TPM v3 updates the TPMxCnVH:L registerswiththevalueoftheirwritebufferatthenextchangeoftheTPMcounter(endofthe prescalercounting)afterthesecondbyteiswritten.Instead,theTPMv2alwaysupdatesthese registers when their second byte is written. The following procedure can be used in the TPM v3 to verify if the TPMxCnVH:L registers wereupdatedwiththenewvaluethatwaswrittentotheseregisters(valueintheirwritebuffer). ... write the new value to TPMxCnVH:L; read TPMxCnVH and TPMxCnVL registers; while (the read value of TPMxCnVH:L is different from the new value written to TPMxCnVH:L) begin read again TPMxCnVH and TPMxCnVL; end ... Inthispoint,theTPMxCnVH:Lregisterswereupdated,sotheprogramcancontinueand,for example, write to TPMxC0SC without cancelling the previous write to TPMxCnVH:L registers. — Edge-Aligned PWM (Section16.4.2.3, “Edge-Aligned PWM Mode) In this mode and if (CLKSB:CLKSA not = 00), the TPM v3 updates the TPMxCnVH:L registerswiththevalueoftheirwritebufferafterthatthebothbyteswerewrittenandwhenthe TPMcounterchangesfrom(TPMxMODH:L-1)to(TPMxMODH:L).IftheTPMcounteris a free-running counter, then this update is made when the TPM counter changes from $FFFE to $FFFF. Instead, the TPM v2 makes this update after that the both bytes were written and when the TPM counter changes from TPMxMODH:L to $0000. — Center-Aligned PWM (Section16.4.2.4, “Center-Aligned PWM Mode) In this mode and if (CLKSB:CLKSA not = 00), the TPM v3 updates the TPMxCnVH:L registerswiththevalueoftheirwritebufferafterthatthebothbyteswerewrittenandwhenthe TPMcounterchangesfrom(TPMxMODH:L-1)to(TPMxMODH:L).IftheTPMcounteris a free-running counter, then this update is made when the TPM counter changes from $FFFE to $FFFF. Instead, the TPM v2 makes this update after that the both bytes were written and when the TPM counter changes from TPMxMODH:L to (TPMxMODH:L - 1). 5. Center-Aligned PWM (Section16.4.2.4, “Center-Aligned PWM Mode) — TPMxCnVH:L = TPMxMODH:L [SE110-TPM case 1] In this case, the TPM v3 produces 100% duty cycle. Instead, the TPM v2 produces 0% duty cycle. — TPMxCnVH:L = (TPMxMODH:L - 1) [SE110-TPM case 2] Inthiscase,theTPMv3producesalmost100%dutycycle.Instead,theTPMv2produces0% duty cycle. — TPMxCnVH:L is changed from 0x0000 to a non-zero value [SE110-TPM case 3 and 5] MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 263

Chapter 16 Timer/PWM Module (S08TPMV3) Inthiscase,theTPMv3waitsforthestartofanewPWMperiodtobeginusingthenewduty cycle setting. Instead, the TPM v2 changes the channel output at the middle of the current PWM period (when the count reaches 0x0000). — TPMxCnVH:L is changed from a non-zero value to 0x0000 [SE110-TPM case 4] In this case, the TPM v3 finishes the current PWM period using the old duty cycle setting. Instead, the TPM v2 finishes the current PWM period using the new duty cycle setting. 6. Write to TPMxMODH:L registers in BDM mode (Section16.3.3, “TPM Counter Modulo Registers (TPMxMODH:TPMxMODL)) In the TPM v3 a write to TPMxSC register in BDM mode clears the write coherency mechanism ofTPMxMODH:Lregisters.Instead,intheTPMv2thiscoherencymechanismisnotclearedwhen there is a write to TPMxSC register. 7. Update of EPWM signal when CLKSB:CLKSA = 00 IntheTPMv3ifCLKSB:CLKSA=00,thentheEPWMsignalinthechanneloutputisnotupdate (itisfrozenwhileCLKSB:CLKSA=00).Instead,intheTPMv2theEPWMsignalisupdatedat the next rising edge of bus clock after a write to TPMxCnSC register. TheFigure0-1andFigure0-2showwhentheEPWMsignalsgeneratedbyTPMv2andTPMv3 after the reset (CLKSB:CLKSA = 00) and if there is a write to TPMxCnSC register. EPWM mode TPMxMODH:TPMxMODL = 0x0007 TPMxCnVH:TPMxCnVL = 0x0005 RESET (active low) BUS CLOCK TPMxCNTH:TPMxCNTL 0 1 2 3 4 5 6 7 0 1 2 ... CLKSB:CLKSA BITS 00 01 MSnB:MSnA BITS 00 10 ELSnB:ELSnA BITS 00 10 TPMv2 TPMxCHn TPMv3 TPMxCHn CHnF BIT (in TPMv2 and TPMv3) Figure0-1.Generation of high-true EPWM signal by TPM v2 and v3 after the reset MC9S08SH8MCUSeriesDataSheet,Rev.3 264 Freescale Semiconductor

Chapter 16 Timer/PWM Module (S08TPMV3) EPWM mode TPMxMODH:TPMxMODL = 0x0007 TPMxCnVH:TPMxCnVL = 0x0005 RESET (active low) BUS CLOCK TPMxCNTH:TPMxCNTL 0 1 2 3 4 5 6 7 0 1 2 ... CLKSB:CLKSA BITS 00 01 MSnB:MSnA BITS 00 10 ELSnB:ELSnA BITS 00 01 TPMv2 TPMxCHn TPMv3 TPMxCHn CHnF BIT (in TPMv2 and TPMv3) Figure0-2.Generation of low-true EPWM signal by TPM v2 and v3 after the reset ThefollowingprocedurecanbeusedinTPMv3(whenthechannelpinisalsoaportpin)toemulate the high-true EPWM generated by TPM v2 after the reset. ... configure the channel pin as output port pin and set the output pin; configure the channel to generate the EPWM signal but keep ELSnB:ELSnA as 00; configure the other registers (TPMxMODH, TPMxMODL, TPMxCnVH, TPMxCnVL, ...); configure CLKSB:CLKSA bits (TPM v3 starts to generate the high-true EPWM signal, however TPM does not control the channel pin, so the EPWM signal is not available); wait until the TOF is set (or use the TOF interrupt); enable the channel output by configuring ELSnB:ELSnA bits (now EPWM signal is available); ... MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 265

Chapter 16 Timer/PWM Module (S08TPMV3) MC9S08SH8MCUSeriesDataSheet,Rev.3 266 Freescale Semiconductor

Chapter 17 Development Support 17.1 Introduction Development support systems in the HCS08 include the background debug controller (BDC) and the on-chip debug module (DBG). The BDC provides a single-wire debug interface to the target MCU that providesaconvenientinterfaceforprogrammingtheon-chipFLASHandothernonvolatilememories.The BDCisalsotheprimarydebuginterfacefordevelopmentandallowsnon-intrusiveaccesstomemorydata and traditional debug features such as CPU register modify, breakpoints, and single instruction trace commands. In the HCS08 Family, address and data bus signals are not available on external pins (not even in test modes).DebugisdonethroughcommandsfedintothetargetMCUviathesingle-wirebackgrounddebug interface. The debug module provides a means to selectively trigger and capture bus information so an external development system can reconstruct what happened inside the MCU on a cycle-by-cycle basis without having external access to the address and data signals. 17.1.1 Forcing Active Background The method for forcing active background mode depends on the specific HCS08 derivative. For the MC9S08SH8, you can force active background after a power-on reset by holding the BKGD pin low as the device exits the reset condition. You can also force active background by driving BKGD low immediatelyafteraserialbackgroundcommandthatwritesaonetotheBDFRbitintheSBDFRregister. Othercausesofresetincludinganexternalpinresetoraninternallygeneratederrorresetignorethestate of the BKGD pin and reset into normal user mode. If no debug pod is connected to the BKGD pin, the MCU will always reset into normal operating mode. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 267

Chapter 17 Development Support 17.1.2 Features Features of the BDC module include: • Single pin for mode selection and background communications • BDC registers are not located in the memory map • SYNC command to determine target communications rate • Non-intrusive commands for memory access • Active background mode commands for CPU register access • GO and TRACE1 commands • BACKGROUND command can wake CPU from stop or wait modes • One hardware address breakpoint built into BDC • Oscillator runs in stop mode, if BDC enabled • COP watchdog disabled while in active background mode Features of the ICE system include: • Two trigger comparators: Two address + read/write (R/W) or one full address + data + R/W • Flexible 8-word by 16-bit FIFO (first-in, first-out) buffer for capture information: — Change-of-flow addresses or — Event-only data • Two types of breakpoints: — Tag breakpoints for instruction opcodes — Force breakpoints for any address access • Nine trigger modes: — Basic: A-only, A OR B — Sequence: A then B — Full: A AND B data, A AND NOT B data — Event (store data): Event-only B, A then event-only B — Range: Inside range (A≤ address≤ B), outside range (address < A or address > B) 17.2 Background Debug Controller (BDC) AllMCUsintheHCS08Familycontainasingle-wirebackgrounddebuginterfacethatsupportsin-circuit programming of on-chip nonvolatile memory and sophisticated non-intrusive debug capabilities. Unlike debuginterfacesonearlier8-bitMCUs,thissystemdoesnotinterferewithnormalapplicationresources. It does not use any user memory or locations in the memory map and does not share any on-chip peripherals. BDC commands are divided into two groups: • ActivebackgroundmodecommandsrequirethatthetargetMCUisinactivebackgroundmode(the user program is not running). Active background mode commands allow the CPU registers to be readorwritten,andallowtheusertotraceoneuserinstructionatatime,orGOtotheuserprogram from active background mode. MC9S08SH8MCUSeriesDataSheet,Rev.3 268 Freescale Semiconductor

Chapter 17 Development Support • Non-intrusive commands can be executed at any time even while the user’s program is running. Non-intrusivecommandsallowausertoreadorwriteMCUmemorylocationsoraccessstatusand control registers within the background debug controller. Typically, a relatively simple interface pod is used to translate commands from a host computer into commandsforthecustomserialinterfacetothesingle-wirebackgrounddebugsystem.Dependingonthe developmenttoolvendor,thisinterfacepodmayuseastandardRS-232serialport,aparallelprinterport, orsomeothertypeofcommunicationssuchasauniversalserialbus(USB)tocommunicatebetweenthe hostPCandthepod.Thepodtypicallyconnectstothetargetsystemwithground,theBKGDpin,RESET, and sometimes V . An open-drain connection to reset allows the host to force a target system reset, DD which is useful to regain control of a lost target system or to control startup of a target system before the on-chip nonvolatile memory has been programmed. Sometimes V can be used to allow the pod to use DD powerfromthetargetsystemtoavoidtheneedforaseparatepowersupply.However,ifthepodispowered separately,itcanbeconnectedtoarunningtargetsystemwithoutforcingatargetsystemresetorotherwise disturbing the running application program. BKGD 1 2 GND NO CONNECT 3 4 RESET NO CONNECT 5 6 V DD Figure17-1. BDM Tool Connector 17.2.1 BKGD Pin Description BKGD is the single-wire background debug interface pin. The primary function of this pin is for bidirectionalserialcommunicationofactivebackgroundmodecommandsanddata.Duringreset,thispin is used to select between starting in active background mode or starting the user’s application program. Thispinisalsousedtorequestatimedsyncresponsepulsetoallowahostdevelopmenttooltodetermine the correct clock frequency for background debug serial communications. BDC serial communications use a custom serial protocol first introduced on the M68HC12 Family of microcontrollers.Thisprotocolassumesthehostknowsthecommunicationclockratethatisdetermined by the target BDC clock rate. All communication is initiated and controlled by the host that drives a high-to-lowedgetosignalthebeginningofeachbittime.Commandsanddataaresentmostsignificantbit first (MSB first). For a detailed description of the communications protocol, refer to Section17.2.2, “Communication Details.” IfahostisattemptingtocommunicatewithatargetMCUthathasanunknownBDCclockrate,aSYNC commandmaybesenttothetargetMCUtorequestatimedsyncresponsesignalfromwhichthehostcan determine the correct communication speed. BKGDisapseudo-open-drainpinandthereisanon-chippullupsonoexternalpullupresistorisrequired. Unliketypicalopen-drainpins,theexternalRCtimeconstantonthispin,whichisinfluencedbyexternal capacitance, plays almost no role in signal rise time. The custom protocol provides for brief, actively driven speedup pulses to force rapid rise times on this pin without risking harmful drive level conflicts. Refer toSection17.2.2, “Communication Details,” for more detail. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 269

Chapter 17 Development Support Whennodebuggerpodisconnectedtothe6-pinBDMinterfaceconnector,theinternalpulluponBKGD choosesnormaloperatingmode.WhenadebugpodisconnectedtoBKGDitispossibletoforcetheMCU into active background mode after reset. The specific conditions for forcing active background depend upon the HCS08 derivative (refer to the introduction to this Development Support section). It is not necessary to reset the target MCU to communicate with it through the background debug interface. 17.2.2 Communication Details The BDC serial interface requires the external controller to generate a falling edge on the BKGD pin to indicate the start of each bit time. The external controller provides this falling edge whether data is transmitted or received. BKGDisapseudo-open-drainpinthatcanbedriveneitherbyanexternalcontrollerorbytheMCU.Data is transferred MSB first at 16BDC clock cycles per bit (nominal speed). The interface times out if 512BDCclockcyclesoccurbetweenfallingedgesfromthehost.AnyBDCcommandthatwasinprogress when this timeout occurs is aborted without affecting the memory or operating mode of the target MCU system. The custom serial protocol requires the debug pod to know the target BDC communication clock speed. Theclockswitch(CLKSW)controlbitintheBDCstatusandcontrolregisterallowstheusertoselectthe BDC clock source. The BDC clock source can either be the bus or the alternate BDC clock source. The BKGD pin can receive a high or low level or transmit a high or low level. The following diagrams show timing for each of these cases. Interface timing is synchronous to clocks in the target BDC, but asynchronoustotheexternalhost.TheinternalBDCclocksignalisshownforreferenceincountingcycles. MC9S08SH8MCUSeriesDataSheet,Rev.3 270 Freescale Semiconductor

Chapter 17 Development Support Figure17-2showsanexternalhosttransmittingalogic1or0totheBKGDpinofatargetHCS08MCU. Thehostisasynchronoustothetargetsothereisa0-to-1cycledelayfromthehost-generatedfallingedge to where the target perceives the beginning of the bit time. Ten target BDC clock cycles later, the target sensesthebitlevelontheBKGDpin.Typically,thehostactivelydrivesthepseudo-open-drainBKGDpin duringhost-to-targettransmissionstospeeduprisingedges.BecausethetargetdoesnotdrivetheBKGD pinduringthehost-to-targettransmissionperiod,thereisnoneedtotreatthelineasanopen-drainsignal during this period. BDC CLOCK (TARGET MCU) HOST TRANSMIT 1 HOST TRANSMIT 0 10 CYCLES EARLIEST START OF NEXT BIT SYNCHRONIZATION TARGET SENSES BIT LEVEL UNCERTAINTY PERCEIVED START OF BIT TIME Figure17-2. BDC Host-to-Target Serial Bit Timing MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 271

Chapter 17 Development Support Figure17-3 shows the host receiving a logic 1 from the target HCS08 MCU. Because the host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the perceived start of the bit time in the target MCU. The host holds the BKGD pin low long enoughforthetargettorecognizeit(atleasttwotargetBDCcycles).Thehostmustreleasethelowdrive beforethetargetMCUdrivesabriefactive-highspeeduppulsesevencyclesaftertheperceivedstartofthe bit time. The host should sample the bit level about 10cycles after it started the bit time. BDC CLOCK (TARGET MCU) HOST DRIVE TO BKGD PIN HIGH-IMPEDANCE TARGET MCU SPEEDUP PULSE HIGH-IMPEDANCE HIGH-IMPEDANCE PERCEIVED START OF BIT TIME R-C RISE BKGD PIN 10 CYCLES EARLIEST START OF NEXT BIT 10 CYCLES HOST SAMPLES BKGD PIN Figure17-3. BDC Target-to-Host Serial Bit Timing (Logic 1) MC9S08SH8MCUSeriesDataSheet,Rev.3 272 Freescale Semiconductor

Chapter 17 Development Support Figure17-4 shows the host receiving a logic 0 from the target HCS08 MCU. Because the host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the start of the bit time as perceived by the target MCU. The host initiates the bit time but the targetHCS08finishesit.Becausethetargetwantsthehosttoreceivealogic0,itdrivestheBKGDpinlow for 13 BDC clock cycles, then briefly drives it high to speed up the rising edge. The host samples the bit level about 10 cycles after starting the bit time. BDC CLOCK (TARGET MCU) HOST DRIVE HIGH-IMPEDANCE TO BKGD PIN SPEEDUP TARGET MCU PULSE DRIVE AND SPEED-UP PULSE PERCEIVED START OF BIT TIME BKGD PIN 10 CYCLES EARLIEST START OF NEXT BIT 10 CYCLES HOST SAMPLES BKGD PIN Figure17-4. BDM Target-to-Host Serial Bit Timing (Logic 0) MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 273

Chapter 17 Development Support 17.2.3 BDC Commands BDC commands are sent serially from a host computer to the BKGD pin of the target HCS08 MCU. All commandsanddataaresentMSB-firstusingacustomBDCcommunicationsprotocol.Activebackground mode commands require that the target MCU is currently in the active background mode while non-intrusivecommandsmaybeissuedatanytimewhetherthetargetMCUisinactivebackgroundmode or running a user application program. Table17-1 shows all HCS08 BDC commands, a shorthand description of their coding structure, and the meaning of each command. Coding Structure Nomenclature This nomenclature is used inTable17-1 to describe the coding structure of the BDC commands. Commands begin with an 8-bit hexadecimal command code in the host-to-target direction (most significant bit first) / = separates parts of the command d = delay 16 target BDC clock cycles AAAA = a 16-bit address in the host-to-target direction RD = 8 bits of read data in the target-to-host direction WD = 8 bits of write data in the host-to-target direction RD16 = 16 bits of read data in the target-to-host direction WD16 = 16 bits of write data in the host-to-target direction SS = the contents of BDCSCR in the target-to-host direction (STATUS) CC = 8 bits of write data for BDCSCR in the host-to-target direction (CONTROL) RBKP = 16 bits of read data in the target-to-host direction (from BDCBKPT breakpoint register) WBKP = 16bitsofwritedatainthehost-to-targetdirection(forBDCBKPTbreakpointregister) MC9S08SH8MCUSeriesDataSheet,Rev.3 274 Freescale Semiconductor

Chapter 17 Development Support Table17-1. BDC Command Summary Command Active BDM/ Coding Description Mnemonic Non-intrusive Structure Request a timed reference pulse to determine SYNC Non-intrusive n/a1 target BDC communication speed Enable acknowledge protocol. Refer to ACK_ENABLE Non-intrusive D5/d Freescale document order no. HCS08RMv1/D. Disable acknowledge protocol. Refer to ACK_DISABLE Non-intrusive D6/d Freescale document order no. HCS08RMv1/D. Enter active background mode if enabled BACKGROUND Non-intrusive 90/d (ignore if ENBDM bit equals 0) READ_STATUS Non-intrusive E4/SS Read BDC status from BDCSCR WRITE_CONTROL Non-intrusive C4/CC Write BDC controls in BDCSCR READ_BYTE Non-intrusive E0/AAAA/d/RD Read a byte from target memory READ_BYTE_WS Non-intrusive E1/AAAA/d/SS/RD Read a byte and report status Re-read byte from address just read and READ_LAST Non-intrusive E8/SS/RD report status WRITE_BYTE Non-intrusive C0/AAAA/WD/d Write a byte to target memory WRITE_BYTE_WS Non-intrusive C1/AAAA/WD/d/SS Write a byte and report status READ_BKPT Non-intrusive E2/RBKP Read BDCBKPT breakpoint register WRITE_BKPT Non-intrusive C2/WBKP Write BDCBKPT breakpoint register Go to execute the user application program GO Active BDM 08/d starting at the address currently in the PC Trace 1 user instruction at the address in the TRACE1 Active BDM 10/d PC, then return to active background mode Same as GO but enable external tagging TAGGO Active BDM 18/d (HCS08 devices have no external tagging pin) READ_A Active BDM 68/d/RD Read accumulator (A) READ_CCR Active BDM 69/d/RD Read condition code register (CCR) READ_PC Active BDM 6B/d/RD16 Read program counter (PC) READ_HX Active BDM 6C/d/RD16 Read H and X register pair (H:X) READ_SP Active BDM 6F/d/RD16 Read stack pointer (SP) Increment H:X by one then read memory byte READ_NEXT Active BDM 70/d/RD located at H:X Increment H:X by one then read memory byte READ_NEXT_WS Active BDM 71/d/SS/RD located at H:X. Report status and data. WRITE_A Active BDM 48/WD/d Write accumulator (A) WRITE_CCR Active BDM 49/WD/d Write condition code register (CCR) WRITE_PC Active BDM 4B/WD16/d Write program counter (PC) WRITE_HX Active BDM 4C/WD16/d Write H and X register pair (H:X) WRITE_SP Active BDM 4F/WD16/d Write stack pointer (SP) IncrementH:Xbyone,thenwritememorybyte WRITE_NEXT Active BDM 50/WD/d located at H:X IncrementH:Xbyone,thenwritememorybyte WRITE_NEXT_WS Active BDM 51/WD/d/SS located at H:X. Also report status. 1 The SYNC command is a special operation that does not have a command code. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 275

Chapter 17 Development Support The SYNC command is unlike other BDC commands because the host does not necessarily know the correctcommunicationsspeedtouseforBDCcommunicationsuntilafterithasanalyzedtheresponseto the SYNC command. To issue a SYNC command, the host: • DrivestheBKGDpinlowforatleast128cyclesoftheslowestpossibleBDCclock(Theslowest clock is normally the reference oscillator/64 or the self-clocked rate/64.) • DrivesBKGDhighforabriefspeeduppulsetogetafastrisetime(Thisspeeduppulseistypically one cycle of the fastest clock in the system.) • Removes all drive to the BKGD pin so it reverts to high impedance • Monitors the BKGD pin for the sync response pulse Thetarget,upondetectingtheSYNCrequestfromthehost(whichisamuchlongerlowtimethanwould ever occur during normal BDC communications): • Waits for BKGD to return to a logic high • Delays 16cycles to allow the host to stop driving the high speedup pulse • Drives BKGD low for 128BDC clock cycles • Drives a 1-cycle high speedup pulse to force a fast rise time on BKGD • Removes all drive to the BKGD pin so it reverts to high impedance Thehostmeasuresthelowtimeofthis128-cyclesyncresponsepulseanddeterminesthecorrectspeedfor subsequent BDC communications. Typically, the host can determine the correct communication speed within a few percent of the actual target speed and the communication protocol can easily tolerate speed errors of several percent. 17.2.4 BDC Hardware Breakpoint The BDC includes one relatively simple hardware breakpoint that compares the CPU address bus to a 16-bitmatchvalueintheBDCBKPTregister.Thisbreakpointcangenerateaforcedbreakpointoratagged breakpoint. A forced breakpoint causes the CPU to enter active background mode at the first instruction boundary following any access to the breakpoint address. The tagged breakpoint causes the instruction opcode at the breakpoint address to be tagged so that the CPU will enter active background mode rather than executing that instruction if and when it reaches the end of the instruction queue. This implies that taggedbreakpointscanonlybeplacedattheaddressofaninstructionopcodewhileforcedbreakpointscan be set at any address. Thebreakpointenable(BKPTEN)controlbitintheBDCstatusandcontrolregister(BDCSCR)isusedto enable the breakpoint logic (BKPTEN=1). When BKPTEN=0, its default value after reset, the breakpointlogicisdisabledandnoBDCbreakpointsarerequestedregardlessofthevaluesinotherBDC breakpoint registers and control bits. The force/tag select (FTS) control bit in BDCSCR is used to select forced (FTS=1) or tagged (FTS=0) type breakpoints. Theon-chipdebugmodule(DBG)includescircuitryfortwoadditionalhardwarebreakpointsthataremore flexible than the simple breakpoint in the BDC module. MC9S08SH8MCUSeriesDataSheet,Rev.3 276 Freescale Semiconductor

Chapter 17 Development Support 17.3 On-Chip Debug System (DBG) Because HCS08 devices do not have external address and data buses, the most important functions of an in-circuitemulatorhavebeenbuiltontothechipwiththeMCU.Thedebugsystemconsistsofan8-stage FIFOthatcanstoreaddressordatabusinformation,andaflexibletriggersystemtodecidewhentocapture businformationandwhatinformationtocapture.Thesystemreliesonthesingle-wirebackgrounddebug system to access debug control registers and to read results out of the eight stage FIFO. The debug module includes control and status registers that are accessible in the user’s memory map. These registers are located in the high register space to avoid using valuable direct page memory space. Mostofthedebugmodule’sfunctionsareusedduringdevelopment,anduserprogramsrarelyaccessany of the control and status registers for the debug module. The one exception is that the debug system can provide the means to implement a form of ROM patching. This topic is discussed in greater detail in Section17.3.6, “Hardware Breakpoints.” 17.3.1 Comparators A and B Two16-bitcomparators(AandB)canoptionallybequalifiedwiththeR/Wsignalandanopcodetracking circuit.SeparatecontrolbitsallowyoutoignoreR/Wforeachcomparator.Theopcodetrackingcircuitry optionally allows you to specify that a trigger will occur only if the opcode at the specified address is actuallyexecutedasopposedtoonlybeingreadfrommemoryintotheinstructionqueue.Thecomparators are also capable of magnitude comparisons to support the inside range and outside range trigger modes. Comparators are disabled temporarily during all BDC accesses. The A comparator is always associated with the 16-bit CPU address. The B comparator compares to the CPU address or the 8-bit CPU data bus, depending on the trigger mode selected. Because the CPU data bus is separated into a read data bus and a write data bus, the RWAEN and RWA control bits have an additional purpose, in full address plus data comparisons they are used to decide which of these buses to useinthecomparatorBdatabuscomparisons.IfRWAEN=1(enabled)andRWA=0(write),theCPU’s write data bus is used. Otherwise, the CPU’s read data bus is used. Thecurrentlyselectedtriggermodedetermineswhatthedebuggerlogicdoeswhenacomparatordetects a qualified match condition. A match can cause: • Generation of a breakpoint to the CPU • Storage of data bus values into the FIFO • Starting to store change-of-flow addresses into the FIFO (begin type trace) • Stopping the storage of change-of-flow addresses into the FIFO (end type trace) 17.3.2 Bus Capture Information and FIFO Operation The usual way to use the FIFO is to setup the trigger mode and other control options, then arm the debugger. When the FIFO has filled or the debugger has stopped storing data into the FIFO, you would read the information out of it in the order it was stored into the FIFO. Status bits indicate the number of wordsofvalidinformationthatareintheFIFOasdataisstoredintoit.Ifatracerunismanuallyhaltedby writing0toARMbeforetheFIFOisfull(CNT=1:0:0:0),theinformationisshiftedbyonepositionand MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 277

Chapter 17 Development Support thehostmustperform((8–CNT)–1)dummyreadsoftheFIFOtoadvanceittothefirstsignificantentry in the FIFO. Inmosttriggermodes,theinformationstoredintheFIFOconsistsof16-bitchange-of-flowaddresses.In thesecases,readDBGFHthenDBGFLtogetonecoherentwordofinformationoutoftheFIFO.Reading DBGFL(thelow-orderbyteoftheFIFOdataport)causestheFIFOtoshiftsothenextwordofinformation isavailableattheFIFOdataport.Intheevent-onlytriggermodes(seeSection17.3.5,“TriggerModes”), 8-bitdatainformationisstoredintotheFIFO.Inthesecases,thehigh-orderhalfoftheFIFO(DBGFH)is notusedanddataisreadoutoftheFIFObysimplyreadingDBGFL.EachtimeDBGFLisread,theFIFO is shifted so the next data value is available through the FIFO data port at DBGFL. In trigger modes where the FIFO is storing change-of-flow addresses, there is a delay between CPU addressesandtheinputsideoftheFIFO.Becauseofthisdelay,ifthetriggereventitselfisachange-of-flow addressorachange-of-flowaddressappearsduringthenexttwobuscyclesafteratriggereventstartsthe FIFO,itwillnotbesavedintotheFIFO.Inthecaseofanend-trace,ifthetriggereventisachange-of-flow, it will be saved as the last change-of-flow entry for that debug run. TheFIFOcanalsobeusedtogenerateaprofileofexecutedinstructionaddresseswhenthedebuggerisnot armed. When ARM=0, reading DBGFL causes the address of the most-recently fetched opcode to be savedintheFIFO.Tousetheprofilingfeature,ahostdebuggerwouldreadaddressesoutoftheFIFOby reading DBGFH then DBGFL at regular periodic intervals. The first eight values would be discarded because they correspond to the eight DBGFL reads needed to initially fill the FIFO. Additional periodic readsofDBGFHandDBGFLreturndelayedinformationaboutexecutedinstructionssothehostdebugger can develop a profile of executed instruction addresses. 17.3.3 Change-of-Flow Information To minimize the amount of information stored in the FIFO, only information related to instructions that causeachangetothenormalsequentialexecutionofinstructionsisstored.Withknowledgeofthesource andobjectcodeprogramstoredinthetargetsystem,anexternaldebuggersystemcanreconstructthepath of execution through many instructions from the change-of-flow information stored in the FIFO. For conditional branch instructions where the branch is taken (branch condition was true), the source addressisstored(theaddressoftheconditionalbranchopcode).BecauseBRAandBRNinstructionsare not conditional, these events do not cause change-of-flow information to be stored in the FIFO. IndirectJMPandJSRinstructionsusethecurrentcontentsoftheH:Xindexregisterpairtodeterminethe destination address, so the debug system stores the run-time destination address for any indirect JMP or JSR. For interrupts, RTI, or RTS, the destination address is stored in the FIFO as change-of-flow information. 17.3.4 Tag vs. Force Breakpoints and Triggers Taggingisatermthatreferstoidentifyinganinstructionopcodeasitisfetchedintotheinstructionqueue, but not taking any other action until and unless that instruction is actually executed by the CPU. This distinction is important because any change-of-flow from a jump, branch, subroutine call, or interrupt causessomeinstructionsthathavebeenfetchedintotheinstructionqueuetobethrownawaywithoutbeing executed. MC9S08SH8MCUSeriesDataSheet,Rev.3 278 Freescale Semiconductor

Chapter 17 Development Support A force-type breakpoint waits for the current instruction to finish and then acts upon the breakpoint request. The usual action in response to a breakpoint is to go to active background mode rather than continuing to the next instruction in the user application program. Thetagvs.forceterminologyisusedintwocontextswithinthedebugmodule.Thefirstcontextrefersto breakpoint requests from the debug module to the CPU. The second refers to match signals from the comparators to the debugger control logic. When a tag-type break request is sent to the CPU, a signal is enteredintotheinstructionqueuealongwiththeopcodesothatif/whenthisopcodeeverexecutes,theCPU will effectively replace the tagged opcode with a BGND opcode so the CPU goes to active background moderatherthanexecutingthetaggedinstruction.WhentheTRGSELcontrolbitintheDBGTregisteris set to select tag-type operation, the output from comparator A or B is qualified by a block of logic in the debugmodulethattracksopcodesandonlyproducesatriggertothedebuggeriftheopcodeatthecompare addressisactuallyexecuted.Thereisseparateopcodetrackinglogicforeachcomparatorsomorethanone compare event can be tracked through the instruction queue at a time. 17.3.5 Trigger Modes Thetriggermodecontrolstheoverallbehaviorofadebugrun.The4-bitTRGfieldintheDBGTregister selectsoneofninetriggermodes.WhenTRGSEL=1intheDBGTregister,theoutputofthecomparator must propagate through an opcode tracking circuit before triggering FIFO actions. The BEGIN bit in DBGTchooseswhethertheFIFObeginsstoringdatawhenthequalifiedtriggerisdetected(begintrace), ortheFIFOstoresdatainacircularfashionfromthetimeitisarmeduntilthequalifiedtriggerisdetected (end trigger). Adebugrunisstartedbywritinga1totheARMbitintheDBGCregister,whichsetstheARMFflagand clearstheAFandBFflagsandtheCNTbitsinDBGS.Abegin-tracedebugrunendswhentheFIFOgets full.Anend-tracerunendswhentheselectedtriggereventoccurs.Anydebugruncanbestoppedmanually by writing a 0 to ARM or DBGEN in DBGC. In all trigger modes except event-only modes, the FIFO stores change-of-flow addresses. In event-only trigger modes, the FIFO stores data in the low-order eight bits of the FIFO. The BEGIN control bit is ignored in event-only trigger modes and all such debug runs are begin type traces.WhenTRGSEL=1toselectopcodefetchtriggers,itisnotnecessarytouseR/Wincomparisons because opcode tags would only apply to opcode fetches that are always read cycles. It would also be unusual to specify TRGSEL=1 while using a full mode trigger because the opcode value is normally known at a particular address. Thefollowingtriggermodedescriptionsonlystatetheprimarycomparatorconditionsthatleadtoatrigger. Either comparator can usually be further qualified with R/W by setting RWAEN (RWBEN) and the corresponding RWA (RWB) value to be matched against R/W. The signal from the comparator with optional R/W qualification is used to request a CPU breakpoint if BRKEN=1 and TAG determines whether the CPU request will be a tag request or a force request. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 279

Chapter 17 Development Support A-Only — Trigger when the address matches the value in comparator A A OR B — Trigger when the address matches either the value in comparator A or the value in comparatorB A Then B — Trigger when the address matches the value in comparator B but only after the address for another cycle matched the value in comparator A. There can be any number of cycles after the A match and before the B match. A AND B Data (Full Mode) — This is called a full mode because address, data, and R/W (optionally) mustmatchwithinthesamebuscycletocauseatriggerevent.ComparatorAchecksaddress,thelowbyte of comparator B checks data, and R/W is checked against RWA if RWAEN=1. The high-order half of comparator B is not used. Infulltriggermodesitisnotusefultospecifyatag-typeCPUbreakpoint(BRKEN=TAG=1),butifyou do, the comparator B data match is ignored for the purpose of issuing the tag request to the CPU and the CPU breakpoint is issued when the comparator A address matches. A AND NOT B Data (Full Mode) — Address must match comparator A, data must not match the low halfofcomparatorB,andR/WmustmatchRWAifRWAEN=1.Allthreeconditionsmustbemetwithin the same bus cycle to cause a trigger. Infulltriggermodesitisnotusefultospecifyatag-typeCPUbreakpoint(BRKEN=TAG=1),butifyou do, the comparator B data match is ignored for the purpose of issuing the tag request to the CPU and the CPU breakpoint is issued when the comparator A address matches. Event-Only B (Store Data) — Trigger events occur each time the address matches the value in comparator B. Trigger events cause the data to be captured into the FIFO. The debug run ends when the FIFO becomes full. AThenEvent-OnlyB(StoreData)—AftertheaddresshasmatchedthevalueincomparatorA,atrigger eventoccurseachtimetheaddressmatchesthevalueincomparatorB.Triggereventscausethedatatobe captured into the FIFO. The debug run ends when the FIFO becomes full. InsideRange(A≤Address≤B)—Atriggeroccurswhentheaddressisgreaterthanorequaltothevalue in comparator A and less than or equal to the value in comparator B at the same time. Outside Range (Address < A or Address > B) — A trigger occurs when the address is either less than the value in comparator A or greater than the value in comparator B. MC9S08SH8MCUSeriesDataSheet,Rev.3 280 Freescale Semiconductor

Chapter 17 Development Support 17.3.6 Hardware Breakpoints The BRKEN control bit in the DBGC register may be set to 1 to allow any of the trigger conditions describedinSection17.3.5,“TriggerModes,”tobeusedtogenerateahardwarebreakpointrequesttothe CPU.TAGinDBGCcontrolswhetherthebreakpointrequestwillbetreatedasatag-typebreakpointora force-typebreakpoint.Atagbreakpointcausesthecurrentopcodetobemarkedasitenterstheinstruction queue.Ifataggedopcodereachestheendofthepipe,theCPUexecutesaBGNDinstructiontogotoactive background mode rather than executing the tagged opcode. A force-type breakpoint causes the CPU to finish the current instruction and then go to active background mode. If the background mode has not been enabled (ENBDM=1) by a serial WRITE_CONTROL command through the BKGD pin, the CPU will execute an SWI instruction instead of going to active background mode. 17.4 Register Definitio This section contains the descriptions of the BDC and DBG registers and control bits. Refertothehigh-pageregistersummaryinthedeviceoverviewchapterofthisdatasheetfortheabsolute address assignments for all DBG registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 17.4.1 BDC Registers and Control Bits The BDC has two registers: • The BDC status and control register (BDCSCR) is an 8-bit register containing control and status bits for the background debug controller. • The BDC breakpoint match register (BDCBKPT) holds a 16-bit breakpoint match address. These registers are accessed with dedicated serial BDC commands and are not located in the memory space of the target MCU (so they do not have addresses and cannot be accessed by user programs). SomeofthebitsintheBDCSCRhavewritelimitations;otherwise,theseregistersmaybereadorwritten at any time. For example, the ENBDM control bit may not be written while the MCU is in active backgroundmode.(Thispreventstheambiguousconditionofthecontrolbitforbiddingactivebackground mode while the MCU is already in active background mode.) Also, the four status bits (BDMACT, WS, WSF,andDVF)areread-onlystatusindicatorsandcanneverbewrittenbytheWRITE_CONTROLserial BDC command. The clock switch (CLKSW) control bit may be read or written at any time. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 281

Chapter 17 Development Support 17.4.1.1 BDC Status and Control Register (BDCSCR) ThisregistercanbereadorwrittenbyserialBDCcommands(READ_STATUSandWRITE_CONTROL) but is not accessible to user programs because it is not located in the normal memory map of the MCU. 7 6 5 4 3 2 1 0 R BDMACT WS WSF DVF ENBDM BKPTEN FTS CLKSW W Normal 0 0 0 0 0 0 0 0 Reset Reset in 1 1 0 0 1 0 0 0 Active BDM: = Unimplemented or Reserved Figure17-5. BDC Status and Control Register (BDCSCR) Table17-2. BDCSCR Register Field Descriptions Field Description 7 Enable BDM (Permit Active Background Mode)— Typically, this bit is written to 1 by the debug host shortly ENBDM afterthebeginningofadebugsessionorwheneverthedebughostresetsthetargetandremains1untilanormal reset clears it. 0 BDM cannot be made active (non-intrusive commands still allowed) 1 BDM can be made active to allow active background mode commands 6 Background Mode Active Status — This is a read-only status bit. BDMACT 0 BDM not active (user application program running) 1 BDM active and waiting for serial commands 5 BDC Breakpoint Enable — If this bit is clear, the BDC breakpoint is disabled and the FTS (force tag select) BKPTEN control bit and BDCBKPT match register are ignored. 0 BDC breakpoint disabled 1 BDC breakpoint enabled 4 Force/Tag Select — When FTS=1, a breakpoint is requested whenever the CPU address bus matches the FTS BDCBKPT match register. When FTS=0, a match between the CPU address bus and the BDCBKPT register causes the fetched opcode to be tagged. If this tagged opcode ever reaches the end of the instruction queue, the CPU enters active background mode rather than executing the tagged opcode. 0 Tag opcode at breakpoint address and enter active background mode if CPU attempts to execute that instruction 1 Breakpoint match forces active background mode at next instruction boundary (address need not be an opcode) 3 Select Source for BDC Communications Clock — CLKSW defaults to 0, which selects the alternate BDC CLKSW clock source. 0 Alternate BDC clock source 1 MCU bus clock MC9S08SH8MCUSeriesDataSheet,Rev.3 282 Freescale Semiconductor

Chapter 17 Development Support Table17-2. BDCSCR Register Field Descriptions (continued) Field Description 2 Wait or Stop Status — When the target CPU is in wait or stop mode, most BDC commands cannot function. WS However,theBACKGROUNDcommandcanbeusedtoforcethetargetCPUoutofwaitorstopandintoactive background mode where all BDC commands work. Whenever the host forces the target MCU into active background mode, the host should issue a READ_STATUS command to check that BDMACT=1 before attempting other BDC commands. 0 TargetCPUisrunninguserapplicationcodeorinactivebackgroundmode(wasnotinwaitorstopmodewhen background became active) 1 TargetCPUisinwaitorstopmode,oraBACKGROUNDcommandwasusedtochangefromwaitorstopto active background mode 1 WaitorStopFailureStatus—ThisstatusbitissetifamemoryaccesscommandfailedduetothetargetCPU WSF executing a wait or stop instruction at or about the same time. The usual recovery strategy is to issue a BACKGROUND command to get out of wait or stop mode into active background mode, repeat the command thatfailed,thenreturntotheuserprogram.(Typically,thehostwouldrestoreCPUregistersandstackvaluesand re-execute the wait or stop instruction.) 0 Memory access did not conflict with a wait or stop instruction 1 Memory access command failed because the CPU entered wait or stop mode 0 DataValidFailureStatus—ThisstatusbitisnotusedintheMC9S08SH8becauseitdoesnothaveanyslow DVF access memory. 0 Memory access did not conflict with a slow memory access 1 Memory access command failed because CPU was not finished with a slow memory access 17.4.1.2 BDC Breakpoint Match Register (BDCBKPT) This 16-bit register holds the address for the hardware breakpoint in the BDC. The BKPTEN and FTS control bits in BDCSCR are used to enable and configure the breakpoint logic. Dedicated serial BDC commands (READ_BKPT and WRITE_BKPT) are used to read and write the BDCBKPT register but is not accessible to user programs because it is not located in the normal memory map of the MCU. BreakpointsarenormallysetwhilethetargetMCUisinactivebackgroundmodebeforerunningtheuser application program. For additional information about setup and use of the hardware breakpoint logic in the BDC, refer toSection17.2.4, “BDC Hardware Breakpoint.” 17.4.2 System Background Debug Force Reset Register (SBDFR) This register contains a single write-only control bit. A serial background mode command such as WRITE_BYTEmustbeusedtowritetoSBDFR.Attemptstowritethisregisterfromauserprogramare ignored. Reads always return 0x00. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 283

Chapter 17 Development Support 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W BDFR1 Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved 1 BDFR is writable only through serial background mode debug commands, not from user programs. Figure17-6. System Background Debug Force Reset Register (SBDFR) Table17-3. SBDFR Register Field Description Field Description 0 BackgroundDebugForceReset—AserialactivebackgroundmodecommandsuchasWRITE_BYTEallows BDFR an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot be written from a user program. 17.4.3 DBG Registers and Control Bits The debug module includes nine bytes of register space for three 16-bit registers and three 8-bit control and status registers. These registers are located in the high register space of the normal memory map so theyareaccessibletonormalapplicationprograms.Theseregistersarerarelyifeveraccessedbynormal user application programs with the possible exception of a ROM patching mechanism that uses the breakpoint logic. 17.4.3.1 Debug Comparator A High Register (DBGCAH) This register contains compare value bits for the high-order eight bits of comparator A. This register is forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1. 17.4.3.2 Debug Comparator A Low Register (DBGCAL) This register contains compare value bits for the low-order eight bits of comparator A. This register is forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1. 17.4.3.3 Debug Comparator B High Register (DBGCBH) This register contains compare value bits for the high-order eight bits of comparator B. This register is forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1. 17.4.3.4 Debug Comparator B Low Register (DBGCBL) This register contains compare value bits for the low-order eight bits of comparator B. This register is forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1. MC9S08SH8MCUSeriesDataSheet,Rev.3 284 Freescale Semiconductor

Chapter 17 Development Support 17.4.3.5 Debug FIFO High Register (DBGFH) Thisregisterprovidesread-onlyaccesstothehigh-ordereightbitsoftheFIFO.Writestothisregisterhave nomeaningoreffect.Intheevent-onlytriggermodes,theFIFOonlystoresdataintothelow-orderbyteof each FIFO word, so this register is not used and will read 0x00. ReadingDBGFHdoesnotcausetheFIFOtoshifttothenextword.Whenreading16-bitwordsoutofthe FIFO, read DBGFH before reading DBGFL because reading DBGFL causes the FIFO to advance to the next word of information. 17.4.3.6 Debug FIFO Low Register (DBGFL) Thisregisterprovidesread-onlyaccesstothelow-ordereightbitsoftheFIFO.Writestothisregisterhave no meaning or effect. Reading DBGFL causes the FIFO to shift to the next available word of information. When the debug module is operating in event-only modes, only 8-bit data is stored into the FIFO (high-order half of each FIFOwordisunused).Whenreading8-bitwordsoutoftheFIFO,simplyreadDBGFLrepeatedlytoget successive bytes of data from the FIFO. It isn’t necessary to read DBGFH in this case. DonotattempttoreaddatafromtheFIFOwhileitisstillarmed(afterarmingbutbeforetheFIFOisfilled or ARMF is cleared) because the FIFO is prevented from advancing during reads of DBGFL. This can interfere with normal sequencing of reads from the FIFO. ReadingDBGFLwhilethedebuggerisnotarmedcausestheaddressofthemost-recentlyfetchedopcode tobestoredtothelastlocationintheFIFO.ByreadingDBGFHthenDBGFLperiodically,externalhost softwarecandevelopaprofileofprogramexecution.AftereightreadsfromtheFIFO,theninthreadwill returntheinformationthatwasstoredasaresultofthefirstread.Tousetheprofilingfeature,readtheFIFO eight times without using the data to prime the sequence and then begin using the data to get a delayed pictureofwhataddresseswerebeingexecuted.TheinformationstoredintotheFIFOonreadsofDBGFL (while the FIFO is not armed) is the address of the most-recently fetched opcode. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 285

Chapter 17 Development Support 17.4.3.7 Debug Control Register (DBGC) This register can be read or written at any time. 7 6 5 4 3 2 1 0 R DBGEN ARM TAG BRKEN RWA RWAEN RWB RWBEN W Reset 0 0 0 0 0 0 0 0 Figure17-7. Debug Control Register (DBGC) Table17-4. DBGC Register Field Descriptions Field Description 7 Debug Module Enable — Used to enable the debug module. DBGEN cannot be set to 1 if the MCU is secure. DBGEN 0 DBG disabled 1 DBG enabled 6 ArmControl—ControlswhetherthedebuggeriscomparingandstoringinformationintheFIFO.Awriteisused ARM tosetthisbit(andARMF)andcompletionofadebugrunautomaticallyclearsit.Anydebugruncanbemanually stopped by writing 0 to ARM or to DBGEN. 0 Debugger not armed 1 Debugger armed 5 Tag/Force Select — Controls whether break requests to the CPU will be tag or force type requests. If TAG BRKEN=0, this bit has no meaning or effect. 0 CPU breaks requested as force type requests 1 CPU breaks requested as tag type requests 4 BreakEnable—ControlswhetheratriggereventwillgenerateabreakrequesttotheCPU.Triggereventscan BRKEN causeinformationtobestoredintheFIFOwithoutgeneratingabreakrequesttotheCPU.Foranendtrace,CPU break requests are issued to the CPU when the comparator(s) and R/W meet the trigger requirements. For a begintrace,CPUbreakrequestsareissuedwhentheFIFObecomesfull.TRGSELdoesnotaffectthetimingof CPU break requests. 0 CPU break requests not enabled 1 Triggers cause a break request to the CPU 3 R/WComparisonValueforComparatorA—WhenRWAEN=1,thisbitdetermineswhetherareadorawrite RWA access qualifies comparator A. When RWAEN=0, RWA and the R/W signal do not affect comparator A. 0 Comparator A can only match on a write cycle 1 Comparator A can only match on a read cycle 2 Enable R/W for Comparator A— Controls whether the level of R/W is considered for a comparator A match. RWAEN 0 R/W is not used in comparison A 1 R/W is used in comparison A 1 R/WComparisonValueforComparatorB—WhenRWBEN=1,thisbitdetermineswhetherareadorawrite RWB access qualifies comparator B. When RWBEN=0, RWB and the R/W signal do not affect comparator B. 0 Comparator B can match only on a write cycle 1 Comparator B can match only on a read cycle 0 Enable R/W for Comparator B — Controls whether the level of R/W is considered for a comparator B match. RWBEN 0 R/W is not used in comparison B 1 R/W is used in comparison B MC9S08SH8MCUSeriesDataSheet,Rev.3 286 Freescale Semiconductor

Chapter 17 Development Support 17.4.3.8 Debug Trigger Register (DBGT) Thisregistercanbereadanytime,butmaybewrittenonlyifARM=0,exceptbits4and5arehard-wired to 0s. 7 6 5 4 3 2 1 0 R 0 0 TRGSEL BEGIN TRG3 TRG2 TRG1 TRG0 W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure17-8. Debug Trigger Register (DBGT) Table17-5. DBGT Register Field Descriptions Field Description 7 Trigger Type — Controls whether the match outputs from comparators A and B are qualified with the opcode TRGSEL tracking logic in the debug module. If TRGSEL is set, a match signal from comparator A or B must propagate throughtheopcodetrackinglogicandatriggereventisonlysignalledtotheFIFOlogiciftheopcodeatthematch address is actually executed. 0 Trigger on access to compare address (force) 1 Trigger if opcode at compare address is executed (tag) 6 Begin/EndTriggerSelect—ControlswhethertheFIFOstartsfillingatatriggerorfillsinacircularmanneruntil BEGIN a trigger ends the capture of information. In event-only trigger modes, this bit is ignored and all debug runs are assumed to be begin traces. 0 Data stored in FIFO until trigger (end trace) 1 Trigger initiates data storage (begin trace) 3:0 Select Trigger Mode — Selects one of nine triggering modes, as described below. TRG[3:0] 0000 A-only 0001 A OR B 0010 A Then B 0011 Event-only B (store data) 0100 A then event-only B (store data) 0101 A AND B data (full mode) 0110 A AND NOT B data (full mode) 0111 Inside range: A≤ address≤ B 1000 Outside range: address < A or address > B 1001 – 1111 (No trigger) MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 287

Chapter 17 Development Support 17.4.3.9 Debug Status Register (DBGS) This is a read-only status register. 7 6 5 4 3 2 1 0 R AF BF ARMF 0 CNT3 CNT2 CNT1 CNT0 W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure17-9. Debug Status Register (DBGS) Table17-6. DBGS Register Field Descriptions Field Description 7 Trigger Match A Flag — AF is cleared at the start of a debug run and indicates whether a trigger match A AF condition was met since arming. 0 Comparator A has not matched 1 Comparator A match 6 Trigger Match B Flag — BF is cleared at the start of a debug run and indicates whether a trigger match B BF condition was met since arming. 0 Comparator B has not matched 1 Comparator B match 5 ArmFlag—WhileDBGEN=1,thisstatusbitisaread-onlyimageofARMinDBGC.Thisbitissetbywriting1 ARMF to the ARM control bit in DBGC (while DBGEN=1) and is automatically cleared at the end of a debug run. A debug run is completed when the FIFO is full (begin trace) or when a trigger event is detected (end trace). A debug run can also be ended manually by writing 0 to ARM or DBGEN in DBGC. 0 Debugger not armed 1 Debugger armed 3:0 FIFOValidCount—Thesebitsareclearedatthestartofadebugrunandindicatethenumberofwordsofvalid CNT[3:0] dataintheFIFOattheendofadebugrun.ThevalueinCNTdoesnotdecrementasdataisreadoutoftheFIFO. The external debug host is responsible for keeping track of the count as information is read out of the FIFO. 0000 Number of valid words in FIFO = No valid data 0001 Number of valid words in FIFO = 1 0010 Number of valid words in FIFO = 2 0011 Number of valid words in FIFO = 3 0100 Number of valid words in FIFO = 4 0101 Number of valid words in FIFO = 5 0110 Number of valid words in FIFO = 6 0111 Number of valid words in FIFO = 7 1000 Number of valid words in FIFO = 8 MC9S08SH8MCUSeriesDataSheet,Rev.3 288 Freescale Semiconductor

Appendix A Electrical Characteristics A.1 Introduction ThissectioncontainselectricalandtimingspecificationsfortheMC9S08SH8Seriesofmicrocontrollers available at the time of publication. A.2 Parameter Classificatio The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate: TableA-1. Parameter Classification P Those parameters are guaranteed during production testing on each individual device. Those parameters are achieved by the design characterization by measuring a statistically relevant C sample size across process variations. Those parameters are achieved by design characterization on a small sample size from typical devices T under typical conditions unless otherwise noted. All values shown in the typical column are within this category. D Those parameters are derived mainly from simulations. NOTE The classification is shown in the column labeled “C” in the parameter tables where appropriate. A.3 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in TableA-2 may affect device reliability or cause permanentdamagetothedevice.Forfunctionaloperatingconditions,refertotheremainingtablesinthis section. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 289

AppendixA Electrical Characteristics inputsaretiedtoanappropriatelogicvoltagelevel(forinstance,eitherV orV )ortheprogrammable SS DD pull-up resistor associated with the pin is enabled. TableA-2. Absolute Maximum Ratings Rating Symbol Value Unit Supply voltage V –0.3 to +5.8 V DD Maximum current into V I 120 mA DD DD Digital input voltage V –0.3 to V +0.3 V In DD Instantaneous maximum current I ± 25 mA D Single pin limit (applies to all port pins)1,2,3 Storage temperature range T –55 to 150 °C stg 1 Input must be current limited to the value specified. To determine the value of the required current-limitingresistor,calculateresistancevaluesforpositive(V )andnegative(V )clamp DD SS voltages, then use the larger of the two resistance values. 2 All functional non-supply pins are internally clamped to V and V . SS DD 3 Power supply must maintain regulation within operating V range during instantaneous and DD operating maximum current conditions. If positive injection current (V > V ) is greater than In DD I , the injection current may flow out of V and could result in external power supply going DD DD out of regulation. Ensure external V load will shunt current greater than maximum injection DD current.ThiswillbethegreatestriskwhentheMCUisnotconsumingpower.Examplesare:if no system clock is present, or if the clock rate is very low (which would reduce overall power consumption). MC9S08SH8MCUSeriesDataSheet,Rev.3 290 Freescale Semiconductor

AppendixA Electrical Characteristics A.4 Thermal Characteristics This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the MCUdesign.TotakeP intoaccountinpowercalculations,determinethedifferencebetweenactualpin I/O voltageandV orV andmultiplybythepincurrentforeachI/Opin.Exceptincasesofunusuallyhigh SS DD pin current (heavy loads), the difference between pin voltage and V or V will be very small. SS DD TableA-3. Thermal Characteristics Num C Rating Symbol Value Unit 1 — Operatingtemperaturerange(packaged) T to T L H C T –40 to 85 °C A M –40 to 125 2 Maximum junction temperature T 135 °C J Thermal resistance1,2 Single-layer board 3 D 8-pin NB SOIC 167 16-pin TSSOP 123 θ °C/W JA 20-pin PDIP 68 20-pin TSSOP 115 24-pin QFN 110 Thermal resistance1,2 Four-layer board 8-pin NB SOIC 115 4 D 16-pin TSSOP 75 °C/W 20-pin PDIP θ 49 JA 20-pin TSSOP 76 24-pin QFN 42 1 Junctiontemperatureisafunctionofdiesize,on-chippowerdissipation,packagethermalresistance,mounting site(board)temperature,ambienttemperature,airflow,powerdissipationofothercomponentsontheboard, and board thermal resistance. 2 Junction to Ambient Natural Convection MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 291

AppendixA Electrical Characteristics The average chip-junction temperature (T ) in°C can be obtained from: J T = T + (P ×θ ) Eqn.A-1 J A D JA where: T = Ambient temperature,°C A θ = Package thermal resistance, junction-to-ambient,°C/W JA P = P +P D int I/O P = I × V , Watts — chip internal power int DD DD P = Power dissipation on input and output pins — user determined I/O Formostapplications,P <<P andcanbeneglected.AnapproximaterelationshipbetweenP andT I/O int D J (if P is neglected) is: I/O P = K÷ (T + 273°C) Eqn.A-2 D J SolvingEquationA-1 andEquationA-2 for K gives: K = P × (T + 273°C) +θ × (P )2 Eqn.A-3 D A JA D whereKisaconstantpertainingtotheparticularpart.Kcanbedeterminedfromequation3bymeasuring P (at equilibrium) for a known T . Using this value of K, the values of P and T can be obtained by D A D J solvingEquationA-1 andEquationA-2 iteratively for any value of T . A MC9S08SH8MCUSeriesDataSheet,Rev.3 292 Freescale Semiconductor

AppendixA Electrical Characteristics A.5 ESD Protection and Latch-Up Immunity Althoughdamagefromelectrostaticdischarge(ESD)ismuchlesscommononthesedevicesthanonearly CMOS circuits, normal handling precautions should be used to avoid exposure to static discharge. Qualificationtestsareperformedtoensurethatthesedevicescanwithstandexposuretoreasonablelevels of static without suffering any permanent damage. All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During the device qualification ESD stresses were performed for the human body model (HBM) and the charge device model (CDM). A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. TableA-4. ESD and Latch-up Test Conditions Model Description Symbol Value Unit Human Series resistance R1 1500 Ω Body Storage capacitance C 100 pF Number of pulses per pin — 3 Latch-up Minimum input voltage limit – 2.5 V Maximum input voltage limit 7.5 V TableA-5. ESD and Latch-Up Protection Characteristics No. Rating1 Symbol Min Max Unit 1 Human body model (HBM) VHBM ±2000 — V 2 Charge device model (CDM) VCDM ±500 — V 3 Latch-up current at TA = 125°C ILAT ±100 — mA 1 Parameter is achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 293

AppendixA Electrical Characteristics A.6 DC Characteristics This section includes information about power supply requirements and I/O pin characteristics. TableA-6. DC Characteristics Num C Characteristic Symbol Condition Min Typ1 Max Unit 1 — Operating voltage V — 2.7 — 5.5 V DD C All I/O pins, 5 V, I = –4 mA V – 1.5 — — Load DD P low-drive strength 5 V, I = –2 mA V – 0.8 — — Load DD C Output high V 3 V, I = –1 mA V – 0.8 — — V OH Load DD 2 C voltage 5 V, I = –20 mA V – 1.5 — — Load DD P All I/O pins, 5 V, I = –10 mA V – 0.8 — — Load DD C high-drive strength 3 V, I = –5 mA V – 0.8 — — Load DD Outputhigh Max total I for V < V 3 C OH I OUT DD 0 — –100 mA current all ports OHT C All I/O pins 5 V, I = 4 mA — — 1.5 Load P low-drive strength 5 V, I = 2 mA — — 0.8 Load C Output low V 3 V, I = 1 mA — — 0.8 V OL Load 4 C voltage 5 V, I = 20 mA — — 1.5 Load P All I/O pins 5 V, I = 10 mA — — 0.8 Load C high-drive strength 3 V, I = 5 mA — — 0.8 Load Output low Max total I for all ports V > V 5 C OL I OUT SS 0 — 100 mA current OLT P Input high voltage; all digital inputs V 5V 0.65 x V — — V IH DD 6 C 3V 0.7 x V — — DD P Input low voltage; all digital inputs V 5V — — 0.35 x V V IL DD 7 C 3V — — 0.35 x V DD 8 C Input hysteresis V 0.06 x V mV hys DD | | 9 P Input leakage current (per pin) I V = V or V — 0.1 1 μA In In DD SS P Hi-Z (off-state) leakage current(per pin) | | input/output port pins I V = V or V , — 0.1 1 μA 10 OZ In DD SS PTB5/IRQ/TCLK/RESET, V = V or V — 0.2 2 μA In DD SS PTB6/SDA/XTAL pins Pullup or Pulldown2 resistors; when enabled 11 P I/O pins R ,R 17 37 52 kΩ PU PD C RESET3 R 17 37 52 kΩ PU D DC injection current4,5, 6, 7 Single pin limit V > V 0 — 2 mA IN DD 12 I V < V , 0 — –0.2 mA IC IN SS Total MCU limit, includes V > V 0 — 25 mA IN DD sum of all stressed pins V < V , 0 — –5 mA IN SS 13 D Input Capacitance, all pins C — — 8 pF In 14 D RAM retention voltage V — 0.6 1.0 V RAM MC9S08SH8MCUSeriesDataSheet,Rev.3 294 Freescale Semiconductor

AppendixA Electrical Characteristics TableA-6. DC Characteristics (continued) Num C Characteristic Symbol Condition Min Typ1 Max Unit 15 D POR re-arm voltage8 V 0.9 1.4 2.0 V POR 16 D POR re-arm time9 t 10 — — μs POR P Low-voltage detection threshold — high range V 17 LVD1 V falling 3.9 4.0 4.1 V DD V rising 4.0 4.1 4.2 DD P Low-voltage detection threshold — low range V 18 LVD0 V falling 2.48 2.56 2.64 V DD V rising 2.54 2.62 2.70 DD P Low-voltage warning threshold — . high range 1 V 19 LVW3 V falling 4.5 4.6 4.7 V DD V rising 4.6 4.7 4.8 DD P Low-voltage warning threshold — high range 0 V 20 LVW2 V falling 4.2 4.3 4.4 V DD V rising 4.3 4.4 4.5 DD P Low-voltage warning threshold low range 1 V 21 LVW1 V falling 2.84 2.92 3.00 V DD V rising 2.90 2.98 3.06 DD P Low-voltage warning threshold — low range 0 V 22 LVW0 V falling 2.66 2.74 2.82 V DD V rising 2.72 2.80 2.88 DD T Low-voltage inhibit reset/recover V 5 V — 100 — hys 23 mV hysteresis 3 V — 60 — 24 P Bandgap Voltage Reference10 VBG 1.18 1.20 1.21 V 1 Typical values are measured at 25°C. Characterized, not tested. 2 When IRQ or a pin interrupt is configured to detect rising edges, pulldown resistors are used in place of pullup resistors. 3 The specified resistor value is the actual value internal to the device. The pullup value may measure higher when measured externally on the pin. 4 Power supply must maintain regulation within operating V range during instantaneous and operating maximum current DD conditions.Ifpositiveinjectioncurrent(V >V )isgreaterthanI ,theinjectioncurrentmayflowoutofV andcouldresult In DD DD DD in external power supply going out of regulation. Ensure external V load will shunt current greater than maximum injection DD current.ThiswillbethegreatestriskwhentheMCUisnotconsumingpower.Examplesare:ifnosystemclockispresent,orif clock rate is very low (which would reduce overall power consumption). 5 All functional non-supply pins are internally clamped to V and V . SS DD 6 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. 7 TheRESET pin does not have a clamp diode to V . Do not drive this pin above V . DD DD 8 Maximum is highest voltage that POR will occur. 9 Simulated, not tested 10Factory trimmed at V = 5.0 V, Temp = 25°C DD MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 295

AppendixA Electrical Characteristics 2 1.0 12255˚˚CC Max 1.5V@20mA 12255˚˚CC Max 0.8V@5mA –40˚C –40˚C 0.8 1.5 ) )0.6 V V (L 1 (L O O V V0.4 0.5 0.2 0 0 0 5 10 15 20 25 0 2 4 6 8 10 I (mA) I (mA) OL OL a) V = 5V, High Drive b) V = 3V, High Drive DD DD FigureA-1.Typical V vs I , High Drive Strength OL OL 2 1.0 12255˚˚CC Max 1.5V@4mA 12255˚˚CC Max 0.8V@1mA –40˚C –40˚C 0.8 1.5 ) )0.6 V V (L 1 (L O O V V0.4 0.5 0.2 0 0 0 1 2 3 4 5 0 0.4 0.8 1.2 1.6 2.0 I (mA) I (mA) OL OL a) V = 5V, Low Drive b) V = 3V, Low Drive DD DD FigureA-2.Typical V vs I , Low Drive Strength OL OL MC9S08SH8MCUSeriesDataSheet,Rev.3 296 Freescale Semiconductor

AppendixA Electrical Characteristics 2 1.0 12255˚˚CC Max 1.5V@ –20mA 12255˚˚CC Max 0.8V@ –5mA –40˚C –40˚C 0.8 1.5 V) V) (H (H 0.6 O O V 1 V – – D D 0.4 D D V V 0.5 0.2 0 0 0 –5 –10 –15 –20 –25 0 –2 –4 –6 –8 –10 I (mA) I (mA) OH OH a) V = 5V, High Drive b) V = 3V, High Drive DD DD FigureA-3.Typical V – V vs I , High Drive Strength DD OH OH 2 1.0 12255˚˚CC Max 1.5V@ –4mA 12255˚˚CC Max 0.8V@ –1mA –40˚C –40˚C 0.8 1.5 V) V) (H (H 0.6 O O V 1 V – – D D 0.4 D D V V 0.5 0.2 0 0 0 –1 –2 –3 –4 –5 0 –0.4 –0.8 –1.2 –1.6 –2.0 I (mA) I (mA) OH OH a) V = 5V, Low Drive b) V = 3V, Low Drive DD DD FigureA-4.Typical V – V vs I , Low Drive Strength DD OH OH MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 297

AppendixA Electrical Characteristics A.7 Supply Current Characteristics This section includes information about power supply current in various operating modes. TableA-7. Supply Current Characteristics V Num C Parameter Symbol DD Typ1 Max2 Unit (V) C 3 5 1.1 1.5 Run supply current measured at 1 RI mA C (CPU clock = 4MHz, f = 2 MHz) DD 3 1 1.5 Bus P 3 5 3.9 5 Run supply current measured at 2 RI mA C (CPU clock =16MHz, f =8 MHz) DD 3 3.9 5 Bus C Run supply current4 measured at 5 7.25 7.7 3 RI mA C (CPU clock =32MHz, fBus =16 MHz) DD 3 7.15 7.6 Stop3 mode supply current C –40°C (C & M suffix ) 1.1 — P 25°C (All parts) 1.5 — 5 μA P5 85°C (C suffix only ) 9.0 26 4 P5 125°C (M suffix only) S3I 45.2 130 DD C C and M suffix –40°C 1.0 — C All parts 25°C 1.4 — 3 μA C C suffix only 85°C 7.8 19 C M suffix only 125°C 40.1 95 Stop2 mode supply current C C and M suffix –40°C 1.1 — P All parts 25°C 1.4 — 5 μA P5 C suffix only 85°C 6.8 22 5 P5 M suffix only 125°C S2I 32.7 99 DD C C and M suffix –40°C 1.0 — C All parts 25°C 1.3 — 3 μA C C suffix only 85°C 5.8 16 C M suffix only 125°C 28.3 76 5 300 500 nA 6 C RTC adder to stop2 or stop36 S23I DDRTI 3 300 500 nA 5 110 180 μA 7 C LVD adder to stop3 (LVDE = LVDSE = 1) S3I DDLVD 3 90 160 μA 8 C Adder to stop3 for oscillator enabled7 S3I 5, 5 8 μA (EREFSTEN =1) DDOSC 3 MC9S08SH8MCUSeriesDataSheet,Rev.3 298 Freescale Semiconductor

AppendixA Electrical Characteristics 1 Typicalvaluesarebasedoncharacterizationdataat25°C.SeeFigureA-5throughFigureA-7fortypicalcurves across voltage/temperature. 2 Max values in this column apply for the full operating temperature range of the device unless otherwise noted. 3 All modules except ADC active, ICS configured for FBE, and does not includeany dc loads on port pins. 4 All modules except ADC active, ICS configured for FEI, and does not include any dc loads on port pins. 5 Stop currents are tested in production for 25°C on all parts. Tests at other temperatures depend upon the part number suffix and maturity of the product. Freescale may eliminate a test insertion at a particular temperature from the production test flow once sufficient data has been collected and is approved. 6 Most customers are expected to find that auto-wakeup from stop2 or stop3 can be used instead of the higher current wait mode. 7 Valuesgivenunderthefollowingconditions:lowrangeoperation(RANGE=0)witha32.768kHzcrystalandlow power mode (HGO = 0). 10 FEI FBELP 8 ) A m 6 ( D D n I 4 u R 2 0 0 1 2 4 8 16 20 f (MHz) bus FigureA-5.Typical Run I vs. Bus Frequency (V = 5V) DD DD MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 299

AppendixA Electrical Characteristics 5 4 ) A m 3 ( D D n I 2 u R 1 0 –40 0 25 85 105 125 Temperature (˚C) FigureA-6.Typical Run I vs. Temperature (V = 5V; f = 8MHz) DD DD bus 50 STOP2 STOP3 40 ) A ( 30 D D P I O 20 T S 10 0 –40 0 25 85 105 125 Temperature (˚C) FigureA-7.Typical Stop I vs. Temperature (V = 5V) DD DD MC9S08SH8MCUSeriesDataSheet,Rev.3 300 Freescale Semiconductor

AppendixA Electrical Characteristics A.8 External Oscillator (XOSC) Characteristics TableA-8. Oscillator Electrical Specifications ( emperature Range = –40 to 125°C Ambient) Nu C Rating Symbol Min Typ1 Max Unit m Oscillator crystal or resonator (EREFS=1, ERCLKEN = 1) Low range (RANGE = 0) flo 32 — 38.4 kHz 1 C High range (RANGE = 1) FEE or FBE mode2 fhi 1 — 5 MHz High range (RANGE = 1, HGO = 1) FBELP mode fhi-hgo 1 — 16 MHz High range (RANGE = 1, HGO = 0) FBELP mode fhi-lp 1 — 8 MHz Load capacitors See crystal or resonator 2 — C1,C2 manufacturer’s recommendation. Feedback resistor 3 — Low range (32 kHz to 100 kHz) RF — 10 — MΩ High range (1 MHz to 16 MHz) — 1 — Series resistor Low range, low gain (RANGE = 0, HGO = 0) — 0 — Low range, high gain (RANGE = 0, HGO = 1) — 100 — High range, low gain (RANGE = 1, HGO = 0) — 0 — 4 — RS kΩ High range, high gain (RANGE = 1, HGO = 1) ≥ 8 MHz — 0 0 4 MHz — 0 10 1 MHz — 0 20 Crystal start-up time3 Low range, low gain (RANGE = 0, HGO = 0) t — 200 — CSTL-LP 5 T Low range, high gain (RANGE = 0, HGO = 1) tCSTL-HGO — 400 — ms High range, low gain (RANGE = 1, HGO = 0)4 t — 5 — CSTH-LP High range, high gain (RANGE = 1, HGO = 1)4 t — 20 — CSTH-HGO Square wave input clock frequency (EREFS=0, ERCLKEN = 1) 6 T FEE or FBE mode2 fextal 0.03125 — 5 MHz FBELP mode 0 — 40 MHz 1 Typical data was characterized at 5.0 V, 25°C or is recommended value. 2 The input clock source must be divided using RDIV to within the range of 31.25 kHz to 39.0625 kHz. 3 Thisparameterischaracterizedandnottestedoneachdevice.ProperPCboardlayoutproceduresmustbefollowedtoachieve specifications. 4 4 MHz crystal MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 301

AppendixA Electrical Characteristics MCU EXTAL XTAL R R S F C1 Crystal or Resonator C2 MC9S08SH8MCUSeriesDataSheet,Rev.3 302 Freescale Semiconductor

AppendixA Electrical Characteristics A.9 Internal Clock Source (ICS) Characteristics TableA-9. ICS Frequency Specification (Temperature Range = –40 to 125°C Ambient) Nu C Rating Symbol Min Typical Max Unit m Internal reference frequency - factory trimmed 1 P at V = 5 V and temperature = 25°C fint_ft — 31.25 — kHz DD 2 P Internal reference frequency - untrimmed1 fint_ut 25 36 41.66 kHz 3 P Internal reference frequency -usertrimmed fint_t 31.25 — 39.0625 kHz 4 D Internal reference startup time tirefst — 55 100 μs DCO output frequency range - untrimmed1 5 — value provided for reference: f = 1024× f fdco_ut 25.6 36.86 42.66 MHz dco_ut int_ut 6 D DCO output frequency range - trimmed fdco_t 32 — 40 MHz 7 D Rvoeltsaogluet iaonnd o tfe tmrimpemraetdu rDeC (uOs ionugt pFuTt RfrIeMq)uency at fixed Δfdco_res_t — ±0.1 ±0.2 %fdco 8 D Rvoeltsaogluet iaonnd o tfe tmrimpemraetdu rDeC (nOo ot uutspinugt fFreTqRuIeMn)cy at fixed Δfdco_res_t — ±0.2 ±0.4 %fdco 9 D Tfroetqaul ednecvyia otivoenr fvroomlta agcet uaanld t rtiemmmpeedra DtuCreO output Δfdco_t — +– 10..05 ±2 %fdco Total deviation of trimmed DCO output frequency over 10 D fixed voltage and temperature range of 0°C to 70°C Δfdco_t — ±0.5 ±1 %fdco 11 D FLL acquisition time2 tacquire 1 ms 12 D DCO output clock long term jitter (over 2mS interval)3 CJitter — 0.02 0.2 %fdco 1 TRIM register at default value (0x80) and FTRIM control bit at default value (0x0). 2 ThisspecificationappliestoanytimetheFLLreferencesourceorreferencedividerischanged,trimvaluechangedorchanging from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 3 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f . BUS Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry via V and V and variation in crystal oscillator frequency increase the C percentage for a DD SS Jitter given interval. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 303

AppendixA Electrical Characteristics y c n+2% e u q e Fr+1% d e m m 0 Tri m o r–1% n f o ati vi–2% e D –40 0 25 85 105 125 Temperature (˚C) FigureA-8.Typical Frequency Deviation vs Temperature (ICS Trimmed to 16MHz bus@25°C, 5V, FEI)1 1.Based on the average of several hundred units from a typical characterization lot. MC9S08SH8MCUSeriesDataSheet,Rev.3 304 Freescale Semiconductor

AppendixA Electrical Characteristics A.10 Analog Comparator (ACMP) Electricals TableA-10. Analog Comparator Electrical Specification Num C Rating Symbol Min Typical Max Unit 1 — Supply voltage VDD 2.7 — 5.5 V 2 C/T Supply current (active) IDDAC — 20 35 μA 3 D Analog input voltage V V – 0.3 — V V AIN SS DD 4 D Analog input offset voltage V 20 40 mV AIO 5 D Analog Comparator hysteresis VH 3.0 6.0 20.0 mV 6 D Analog input leakage current IALKG -- -- 1.0 μA 7 D Analog Comparator initialization delay t — — 1.0 μs AINIT MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 305

AppendixA Electrical Characteristics A.11 ADC Characteristics TableA-11. ADC Operating Conditions Characteristic Conditions Symb Min Typ1 Max Unit Comment Supply voltage Absolute V 2.7 — 5.5 V DDAD Input Voltage V V — V V ADIN REFL REFH Input C — 4.5 5.5 ADIN pF Capacitance Input R — 3 5 ADIN kΩ Resistance Analog Source 10 bit mode R AS Resistance f > 4MHz — — 5 ADCK f < 4MHz — — 10 kΩ External to MCU ADCK 8 bit mode (all valid f ) — — 10 ADCK ADC High Speed (ADLPC=0) f 0.4 — 8.0 ADCK Conversion MHz Clock Freq. Low Power (ADLPC=1) 0.4 — 4.0 1 Typical values assume V = V = 5.0V, Temp = 25°C, fADCK=1.0MHz unless otherwise stated. Typical values are for DDAD DD reference only and are not tested in production. SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT ZADIN SIMPLIFIED Pad ZAS leakage CHANNEL SELECT due to CIRCUIT ADC SAR R input R ENGINE AS protection ADIN + V ADIN – C V + AS AS – R ADIN INPUT PIN R ADIN INPUT PIN R ADIN INPUT PIN C ADIN FigureA-9. ADC Input Impedance Equivalency Diagram MC9S08SH8MCUSeriesDataSheet,Rev.3 306 Freescale Semiconductor

AppendixA Electrical Characteristics TableA-12. ADC Characteristics Characteristic Conditions C Symb Min Typ1 Max Unit Comment Supply current ADLPC=1 T I + — 133 — μA ADC current DD ADLSMP=1 I only DDAD ADCO=1 Supply current ADLPC=1 T I + — 218 — μA ADC current DD ADLSMP=0 I only DDAD ADCO=1 Supply current ADLPC=0 T I + — 327 — μA ADC current DD ADLSMP=1 I only DDAD ADCO=1 Supply current ADLPC=0 P I + — 0.582 1 mA ADC current DD ADLSMP=0 I only DDAD ADCO=1 ADC High speed (ADLPC=0) 2 3.3 5 t = asynchronous P f MHz ADACK clock source Low power (ADLPC=1) ADACK 1.25 2 3.3 1/fADACK Conversion time Short sample (ADLSMP=0) — 20 — ADCK (including sample Long sample (ADLSMP=1) D tADC — 40 — cycles See ADC time) Chapter for conversion Sample time Short sample (ADLSMP=0) — 3.5 — ADCK time variances D t ADS cycles Long sample (ADLSMP=1) — 23.5 — Total unadjusted 10 bit mode — ±1.5 ±3.5 LSB2 error (Includes P E quantization) 8 bit mode TUE — ±0.7 ±1.5 LSB2 Differential 10 bit mode — ±0.5 ±1.0 Non-Linearity P DNL LSB2 8 bit mode — ±0.3 ±0.5 Monotonicity and No-Missing-Codes guaranteed Integral 10 bit mode — ±0.5 ±1.0 non-linearity T INL LSB2 8 bit mode — ±0.3 ±0.5 Zero-scale error 10 bit mode — ±1.5 ±2.5 P E LSB2 ZS 8 bit mode — ±0.5 ±0.7 Full-scale error 10 bit mode 0 ±1.0 ±1.5 (VADIN = VDD) 8 bit mode T EFS 0 ±0.5 ±0.5 LSB2 Quantization error 10 bit mode — — ±0.5 D E LSB2 Q 8 bit mode — — ±0.5 Inputleakageerror 10 bit mode 0 ±0.2 ±2.5 Padleakage2* 8 bit mode D EIL 0 ±0.1 ±1 LSB2 RAS MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 307

AppendixA Electrical Characteristics TableA-12. ADC Characteristics (continued) Characteristic Conditions C Symb Min Typ1 Max Unit Comment Temp sensor –40°C to25°C — 3.266 — slope D m mV/°C 25°C to125°C — 3.638 — Temp sensor 25°C D V — 1.396 — mV TEMP25 voltage 1 TypicalvaluesassumeV =5.0V,Temp=25°C,f =1.0MHzunlessotherwisestated.Typicalvaluesareforreferenceonly DD ADCK and are not tested in production. 2 Based on input pad leakage current. Refer to pad electricals. MC9S08SH8MCUSeriesDataSheet,Rev.3 308 Freescale Semiconductor

AppendixA Electrical Characteristics A.12 AC Characteristics This section describes ac timing characteristics for each peripheral system. A.12.1 Control Timing TableA-13. Control Timing Nu C Rating Symbol Min Typ1 Max Unit m 1 D Bus frequency (tcyc = 1/fBus) fBus dc — 20 MHz 2 D Internal low power oscillator period tLPO 800 1500 μs 3 D External reset pulse width2 textrst 100 — ns 4 D Reset low drive3 trstdrv 66 x tcyc — ns Pin interrupt pulse width 8 D Asynchronous path2 t t 100 — — ns ILIH, IHIL Synchronous path5 1.5 x t cyc Port rise and fall time — Low output drive (PTxDS = 0) (load = 50 pF)4 Slew rate control disabled (PTxSE = 0) tRise, tFall — 40 — ns Slew rate control enabled (PTxSE = 1) — 75 — 9 C Port rise and fall time — High output drive (PTxDS = 1) (load = 50 pF)6 Slew rate control disabled (PTxSE = 0) tRise, tFall — 11 — ns Slew rate control enabled (PTxSE = 1) — 35 — 1 Typical values are based on characterization data at V = 5.0V, 25°C unless otherwise stated. DD 2 This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to override reset requests from internal sources. 3 Whenanyresetisinitiated,internalcircuitrydrivestheresetpinlowforabout66cyclesoft .AfterPORresetthebusclock cyc frequency changes to the untrimmed DCO frequency (f = (f )/4) because TRIM is reset to 0x80 and FTRIM is reset reset dco_ut to 0, and there is an extra divide-by-two because BDIV is reset to 0:1. After other resets trim stays at the pre-reset value. 4 Timing is shown with respect to 20% V and 80% V levels. Temperature range –40°C to 125°C. DD DD t extrst RESET PIN FigureA-10. Reset Timing MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 309

AppendixA Electrical Characteristics t IHIL IRQ/Pin Interrupts IRQ/Pin Interrupts t ILIH FigureA-11. IRQ/Pin Interrupt Timing MC9S08SH8MCUSeriesDataSheet,Rev.3 310 Freescale Semiconductor

AppendixA Electrical Characteristics A.12.2 TPM/MTIM Module Timing Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock. TableA-14. TPM Input Timing Num C Rating Symbol Min Max Unit 1 — External clock frequency (1/tTCLK) fTCLK dc fBus/4 MHz 2 — External clock period tTCLK 4 — tcyc 3 — External clock high time tclkh 1.5 — tcyc 4 — External clock low time tclkl 1.5 — tcyc 5 — Input capture pulse width tICPW 1.5 — tcyc t TCLK t clkh TCLK t clkl FigureA-12. Timer External Clock t ICPW TPMCHn TPMCHn t ICPW FigureA-13. Timer Input Capture Pulse MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 311

AppendixA Electrical Characteristics A.12.3 SPI TableA-15 andFigureA-14 through FigureA-17 describe the timing requirements for the SPI system. TableA-15. SPI Electrical Characteristic Num1 C Rating2 Symbol Min Max Unit 1 D Cycle time Master tSCK 2 2048 tcyc Slave tSCK 4 — tcyc 2 D Enablelead time Master t — 1/2 t Lead SCK Slave t 1/2 — t Lead SCK 3 D Enable lag time Master t — 1/2 t Lag SCK Slave t 1/2 — t Lag SCK 4 D Clock (SPSCK)high time Master and Slave t 1/2 t – 25 — ns SCKH SCK 5 D Clock (SPSCK) low time Master and Slave tSCKL 1/2 tSCK – 25 — ns 6 D Datasetup time (inputs) Master t 30 — ns SI(M) Slave t 30 — ns SI(S) 7 D Datahold time (inputs) Master t 30 — ns HI(M) Slave t 30 — ns HI(S) 8 D Accesstime, slave3 t 0 40 ns A 9 D Disabletime, slave4 t — 40 ns dis 10 D Datasetup time (outputs) Master t 25 — ns SO Slave t 25 — ns SO 11 D Datahold time (outputs) Master t –10 — ns HO Slave t –10 — ns HO 12 D Operating frequency Master f f /2048 55 MHz op Bus Slave f dc f /4 op Bus 1 Refer toFigureA-14 throughFigureA-17. 2 Alltimingisshownwithrespectto20%V and70%V ,unlessnoted;100pFloadonallSPI DD DD pins.AlltimingassumesslewratecontroldisabledandhighdrivestrengthenabledforSPIoutput pins. 3 Time to data active from high-impedance state. 4 Hold time to high-impedance state. 5 Maximum baud rate must be limited to 5 MHz due to input filter characteristics. MC9S08SH8MCUSeriesDataSheet,Rev.3 312 Freescale Semiconductor

AppendixA Electrical Characteristics SS1 (OUTPUT) 2 1 3 SCK 5 (CPOL = 0) (OUTPUT) 4 SCK 5 (CPOL = 1) 4 (OUTPUT) 6 7 MISO (INPUT) MSB IN2 BIT 6 . . . 1 LSB IN 10 10 11 MOSI MSB OUT2 BIT 6 . . . 1 LSB OUT (OUTPUT) NOTES: 1.SS output mode (MODFEN = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. FigureA-14. SPI Master Timing (CPHA = 0) SS(1) (OUTPUT) 1 2 3 SCK 5 (CPOL = 0) (OUTPUT) 4 SCK 5 (CPOL = 1) 4 (OUTPUT) 6 7 MISO (INPUT) MSB IN(2) BIT 6 . . . 1 LSB IN 10 11 MOSI MSB OUT(2) BIT 6 . . . 1 LSB OUT (OUTPUT) NOTES: 1.SS output mode (MODFEN = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. FigureA-15. SPI Master Timing (CPHA = 1) MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 313

AppendixA Electrical Characteristics SS (INPUT) 1 3 SCK 5 (CPOL = 0) (INPUT) 4 2 SCK 5 (CPOL = 1) (INPUT) 4 9 8 10 11 MISO SEE (OUTPUT) SLAVE MSB OUT BIT 6 . . . 1 SLAVE LSB OUT NOTE 6 7 MOSI (INPUT) MSB IN BIT 6 . . . 1 LSB IN NOTE: 1. Not defined but normally MSB of character just received FigureA-16. SPI Slave Timing (CPHA = 0) SS (INPUT) 1 3 2 SCK (CPOL = 0) 5 (INPUT) 4 SCK 5 (CPOL = 1) 4 (INPUT) 10 11 9 MISO SEE (OUTPUT) NOTE SLAVE MSB OUT BIT 6 . . . 1 SLAVE LSB OUT 8 6 7 MOSI (INPUT) MSB IN BIT 6 . . . 1 LSB IN NOTE: 1. Not defined but normally LSB of character just received FigureA-17. SPI Slave Timing (CPHA = 1) MC9S08SH8MCUSeriesDataSheet,Rev.3 314 Freescale Semiconductor

AppendixA Electrical Characteristics A.13 FLASH Specification This section provides details about program/erase times and program-erase endurance for the FLASH memory. ProgramanderaseoperationsdonotrequireanyspecialpowersourcesotherthanthenormalV supply. DD For more detailed information about program/erase operations, see the Memory section. TableA-16. FLASH Characteristics Num C Characteristic Symbol Min Typical Max Unit 1 — Supply voltage for program/erase V 2.7 5.5 V prog/erase 2 — Supply voltage for read operation V 2.7 5.5 V Read 3 — Internal FCLK frequency1 f 150 200 kHz FCLK 4 — Internal FCLK period (1/f ) t 5 6.67 μs FCLK Fcyc 5 — Byte program time (random location)2 t 9 t prog Fcyc 6 — Byte program time (burst mode)2 t 4 t Burst Fcyc 7 — Page erase time2 t 4000 t Page Fcyc 8 — Mass erase time2 t 20,000 t Mass Fcyc Program/erase endurance3 9 C TL to TH = –40°C to +125°C nFLPE 10,000 — — cycles T = 25°C — 100,000 — 10 C Data retention4 t 15 100 — years D_ret 1 The frequency of this clock is controlled by a software setting. 2 Thesevaluesarehardwarestatemachinecontrolled.Usercodedoesnotneedtocountcycles.Thisinformationsuppliedfor calculating approximate time to program and erase. 3 Typical endurance for FLASHis based on the intrinsic bit cell performance. For additional information on howFreescale defines typical endurance, please refer to Engineering Bulletin EB619/D, Typical Endurance for Nonvolatile Memory. 4 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to25°CusingtheArrheniusequation.ForadditionalinformationonhowFreescaledefinestypicaldataretention,pleaserefer to Engineering Bulletin EB618/D, Typical Data Retention for Nonvolatile Memory. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 315

AppendixA Electrical Characteristics A.14 EMC Performance Electromagneticcompatibility(EMC)performanceishighlydependantontheenvironmentinwhichthe MCU resides. Board design and layout, circuit topology choices, location and characteristics of external components as well as MCU software operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC performance. A.14.1 Radiated Emissions MicrocontrollerradiatedRFemissionsaremeasuredfrom150kHzto1GHzusingtheTEM/GTEMCell methodinaccordancewiththeIEC61967-2andSAEJ1752/3standards.Themeasurementisperformed withthemicrocontrollerinstalledonacustomEMCevaluationboardwhilerunningspecializedEMCtest software. The radiated emissions from the microcontroller are measured in a TEM cell in two package orientations (North and East). The maximum radiated RF emissions of the tested configuration in all orientations are less than or equal to the reported emissions levels. TableA-17. Radiated Emissions, Electric Field Level1 Parameter Symbol Conditions Frequency f /f Unit OSC BUS (Max) V V =5 V 0.15 – 50 MHz 4 MHz crystal 0 dBμV RE_TEM DD T = +25oC 16 MHzbus A 50 – 150 MHz 0 package type 16-TSSOP 150 – 500 MHz –6 Radiated emissions, electric field 500 – 1000 MHz –9 IEC Level N — SAE Level 1 — 1 Data based on qualification test results. A.14.2 Conducted Transient Susceptibility Microcontroller transient conducted susceptibility is measured in accordance with an internal Freescale test method. The measurement is performed with the microcontroller installed on a custom EMC evaluationboardandrunningspecializedEMCtestsoftwaredesignedincompliancewiththetestmethod. The conducted susceptibility is determined by injecting the transient susceptibility signal on each pin of the microcontroller. The transient waveform and injection methodology is based on IEC 61000-4-4 (EFT/B). The transient voltage required to cause performance degradation on any pin in the tested configurationisgreaterthanorequaltothereportedlevelsunlessotherwiseindicatedbyfootnotesbelow TableA-18. MC9S08SH8MCUSeriesDataSheet,Rev.3 316 Freescale Semiconductor

AppendixA Electrical Characteristics TableA-18. Conducted Susceptibility, EFT/B Amplitude1 Parameter Symbol Conditions fOSC/fBUS Result Unit (Min) A 4 V =5 V 4 MHz Conducted susceptibility, electrical TD=D +25oC crystal B N/A fast transient/burst (EFT/B) VCS_EFT paAckage type 16 MHz bus kV C N/A 16-TSSOP D N/A 1 Data based on qualification test results. Not tested in production. The susceptibility performance classification is described inTable A-19. TableA-19. Susceptibility Performance Classificatio Result Performance Criteria A No failure The MCU performs as designed during and after exposure. B Self-recovering The MCU does not perform as designed during exposure. The MCU returns failure automatically to normal operation after exposure is removed. C Soft failure TheMCUdoesnotperformasdesignedduringexposure.TheMCUdoesnotreturnto normal operation until exposure is removed and the RESET pin is asserted. D Hard failure TheMCUdoesnotperformasdesignedduringexposure.TheMCUdoesnotreturnto normal operation until exposure is removed and the power to the MCU is cycled. E Damage The MCU does not perform as designed during and after exposure. The MCU cannot be returned to proper operation due to physical damage or other permanent performance degradation. MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 317

AppendixA Electrical Characteristics MC9S08SH8MCUSeriesDataSheet,Rev.3 318 Freescale Semiconductor

Appendix B Ordering Information and Mechanical Drawings B.1 Ordering Information This section contains ordering information for MC9S08SH8 and MC9S08SH4 devices. TableB-1. Device Numbering System Memory Available Packages2 Device Number1 FLASH RAM 24-Pin 20-Pin 16-Pin 8-Pin MC9S08SH8 8K 512 20 PDIP 24-QFN 20 TSSOP 16 TSSOP 8 NB SOIC MC9S08SH4 4K 256 20 SOIC 1 SeeTable1-1 for a complete description of modules included on each device. 2 SeeTableB-2 for package information. B.1.1 Device Numbering Scheme MC 9 S08 SH 8 C TG R Status Tape and Reel Suffi (optional) -MC =Consumer & Industirial Fully Qualified Package Designator Two letter descriptor MainMemoryType (refer toTableB-2). - 9 = Flash-based Temperature Option - C = -40 to 85°C Core - M = -40 to 125°C SH Family Memory Size - 8 Kbytes -4 Kbytes MC9S08SH8MCUSeriesDataSheet,Rev.3 Freescale Semiconductor 319

AppendixB Ordering Information and Mechanical Drawings B.2 Mechanical Drawings The following pages are mechanical specifications for MC9S08SH8 package options. SeeTable B-2 for the document number for each package type. TableB-2. Package Information Pin Type Designator Document No. Count 24 QFN FK 98ARE10714D 20 PDIP PJ 98ASB42899B 20 TSSOP TJ 98ASH70169A 20 SOIC WJ 98ASB42343B 16 TSSOP TG 98ASH70247A 8 NB SOIC SC 98ASB42564B MC9S08SH8MCUSeriesDataSheet,Rev.3 320 Freescale Semiconductor

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