Freescale Semiconductor Document Number: MC9S08MP16 Data Sheet: Technical Data Rev. 2, 08/2011 MC9S08MP16 Series Data 48-LQFP 32-LQFP Sheet Case 932-03 Case 873A-03 28-SOIC Features Case 751F-05 • 8-Bit HCS08 Central Processor Unit (CPU) – Up to 51.34 MHz CPU at 2.7V to 5.5V across temperature range of –40°C to 105°C – PGA — Differential programmable gain amplifier with – Up to 40 MHz CPU at 2.7V to 5.5V across temperature range programmable gain (x1, x2, x4, x8, x16, or x32) of –40°C to 125°C – HSCMP — Three fast analog comparators with positive and – HC08 instruction set with added BGND instruction and negative inputs; separately selectable interrupt on rising and additional addressing modes for LDHX and STHX falling comparator output; filtering; windowing; HSCMP1 and – Support for up to 48 interrupt/reset sources HSCMP2 outputs can be optionally routed to FTM1 module; • On-Chip Memory runs in stop3 – Up to 16KB flash memory; read/program/erase over full – DAC — Three 5-bit digital to analog convertor used as a operating voltage and temperature 32-tap voltage reference for each comparator – Up to 1KB random-access memory (RAM) – PDB — Two programmable delay blocks: PDB1 synchronizes – Security circuitry to prevent unauthorized access to RAM and PWM with samples of ADC; PDB2 synchronizes PWM with flash memory contents comparing window of analog comparators • Power-Saving Modes – SCI — Full duplex non-return to zero (NRZ); LIN master – Two low power stop modes; reduced power wait mode extended break generation; LIN slave extended break – Peripheral clock gating can disable clocks to unused modules detection; wake up on active edge • Clock Source Options – SPI — Full-duplex or single-wire bidirectional; – Oscillator (XOSC) — Loop-control Pierce oscillator; Crystal Double-buffered transmit and receive; Master or Slave mode; or ceramic resonator range of 31.25–38.4kHz or 1–16MHz MSB-first or LSB-first shifting – Internal Clock Source (ICS) — Containing a – IIC/SMBus — Up to 400 kbps; Multi-master operation; frequency-locked-loop (FLL) controlled by internal or Programmable slave address; Interrupt driven byte-by-byte external reference; precision trimming of internal reference data transfer; supports broadcast mode and 10-bit addressing; allows 0.2% resolutions and 2% deviation over temperature SMBus compatible and voltage; supports CPU frequencies up to 51.34 MHz – FTM — Two Flextimers with total of 8 channels; One • System Protection 2-channel (FTM1) and one 6-channel (FTM2); supports – Watchdog computer operating properly (COP) reset running operation up to 2x bus clock; selectable input capture, output from dedicated 1-kHz internal clock source or bus clock compare, edge- or center-aligned PWM; dead time insertion; – Low-voltage detection with reset or interrupt; selectable trip fault inputs points – MTIM — 8-bit modulo counter with 8-bit prescaler – Illegal opcode and illegal address detection with reset – RTC — (Real-time counter) 8-bit modulus counter with – Flash memory block protection binary or decimal based prescaler; External clock source for • Development Support precise time base, time-of-day, calendar or task scheduling; – Single-wire background debug interface Free running on-chip low power oscillator (1kHz) for cyclic – Breakpoint capability to allow single breakpoint setting during wake-up without external components, runs in all MCU modes in-circuit debugging (plus three more breakpoints in on-chip – CRC — Cyclic redundancy check generator debug module) – KBI — Three 8 channel keyboard interrupt module with – On-chip in-circuit emulator (ICE) debug module containing software selectable polarity on edge or edge/level modes three comparators and nine trigger modes. Eight deep FIFO for • Input/Output storing change-of-flow addresses and event-only data. Debug – 40 GPIOs, 2 output-only pins. module supports both tag and force breakpoints – Hysteresis and configurable pull up device on input pins; • Peripherals Configurable slew rate and drive strength on output pins; – IPC — Interrupt Priority Controller with 4 programmable Sink/Source current up to 20mA interrupt priority levels • Package Options – ADC — 13-channel, 12-bit resolution; 2.5 s conversion time; – 48-LQFP, 32-LQFP, 28-SOIC automatic compare function; 1.7 mV/C temperature sensor; – 48-LQFP qualified for automotive usage internal bandgap reference channel; operation in stop3 Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. ©Freescale Semiconductor, Inc., 2009-2011. All rights reserved.

Table of Contents 1 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2.13 Programmable Gain Amplifier (PGA) Characteristics . 26 2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.14 AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.14.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.2 Parameter Classification. . . . . . . . . . . . . . . . . . . . . . . . .9 2.14.2 FTM Module Timing. . . . . . . . . . . . . . . . . . . . . 28 2.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . .9 2.14.3 MTIM Module Timing. . . . . . . . . . . . . . . . . . . . 29 2.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .10 2.14.4 SPI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.5 ESD Protection and Latch-Up Immunity. . . . . . . . . . . .11 2.15 Flash Memory Specifications. . . . . . . . . . . . . . . . . . . . 33 2.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.16 EMC Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.7 Supply Current Characteristics. . . . . . . . . . . . . . . . . . .15 2.16.1 Radiated Emissions. . . . . . . . . . . . . . . . . . . . . 33 2.8 External Oscillator (XOSC) Characteristics . . . . . . . . .20 3 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.9 Internal Clock Source (ICS) Characteristics. . . . . . . . .21 3.1 Device Numbering Scheme. . . . . . . . . . . . . . . . . . . . . 35 2.10 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .23 4 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.11 Digital to Analog (DAC) Characteristics . . . . . . . . . . . .26 5 Related Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.12 High Speed Comparator (HSCMP) Characteristics . . .26 6 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 MC9S08MP16 Series Data Sheet, Rev. 2 2 Freescale Semiconductor

ON-CHIP ICE Interrupt Priority Controller DEBUG MODULE (DBG) (IPC) CYCLIC REDUNDANCY HCS08 CORE CHECK (CRC) CPU INT 8-BIT KEYBOARD KBI1P[7:0] PTA7/SPSCK BKGD BKP INTERRUPT (KBI1) PTA6/MOSI PTA5/SCL/MISO HCS08 SYSTEM CONTROL 8-BIT KEYBOARD KBI2P[7:0] T A PTA4/TCLK/SDA/SS RESETS AND INTERRUPTS INTERRUPT (KBI2) R PTA3/SCL/FTM1CH1 O MODES OF OPERATION BKGD/MS 8-BIT KEYBOARD KBI3P[7:0] P PTA2/SDA/FTM1CH0 POWER MANAGEMENT PTA1/SCL/RxD INTERRUPT (KBI3) PTA0/SDA/TxD COP SCL RESET IIC MODULE (IIC) PTB7/KBI1P7/ADP7/C3IN4 LVD (Only on MC9S08MP16) SDA PTB6/KBI1P6/CMP3OUT/ADP6/C3IN3 PTB5/KBI1P5/CMP2OUT/ADP5/C2IN4 USER FLASH 2-CHANNEL FLEXTIMER FTTCMLK1CH[1:0] RT B PPTTBB43//KKBBII11PP43//AADDPP43//CC23IINN32/PGA- (MC9S08MP16 = 16384 BYTES) (FTM1) FTM1FAULT PO PTB2/KBI1P2/ADP2/C1IN2/PGA+ (MC9S08MP12 = 12288 BYTES) FTM2CH[5:0] PTB1/KBI1P1/ADP1/C2IN2 6-CHANNEL FLEXTIMER TCLK PTB0/KBI1P0/ADP0/CIN1 USER RAM (FTM2) FTM2FAULT PTC7/KBI2P7/TCLK (MC9S08MP16 = 1024 BYTES) PTC6/KBI2P6/FTM2FAULT (MC9S08MP12 = 512 BYTES) 8-BIT MODULO TIMER TCLK PTC5/KBI2P5/FTM2CH5 (MTIM) T C PTC4/KBI2P4/FTM2CH4 R PTC3/KBI2P3/FTM2CH3 O 50.33MHz INTERNAL CLOCK TxD P PTC2/KBI2P2/FTM2CH2 SOURCE (ICS) SERIAL COMMUNICATIONS PTC1/KBI2P1/FTM2CH1 RxD INTERFACE (SCI) PTC0/KBI2P0/FTM2CH0 XTAL LOW-POWER OSCILLATOR SS PTD7/KBI3P7/CMP3OUT 31.12 5M kHHzz t oto 1 368 M.4H kzHz EXTAL SERIAL PERIPHERAL SPSCK PTD6/KBI3P6/CMP2OUT (XOSC) INTERFACE (SPI) MISO PTD5/KBI3P5/CMP1OUT MOSI T D PTD4/KBI3P4/PDB2OUT REAL TIME PROGRAMMABLE DELAY PDB1OUT OR PTD3/KBI3P3/FTM1FAULT COUNTER (RTC) BLOCK (PDB1) P PTD2/KBI3P2/PDB1OUT PTD1/KBI3P1/SCL PROGRAMMABLE DELAY PDB2OUT PTD0/KBI3P0/SDA BLOCK (PDB2) V REFH PTE6/EXTAL VVDSDSAA//VVRREEFFHL VREFL ACNOANLVOEG1R2-TT-BOEIR-TD (IAGDITCA)L ADP12–ADP0 RT E PPPTTTEEE345///AAXDDTAPPL1112//CC11IINN34 V O PTE2/ADP10 VDSDS11 VOLTAGE PROGRAMMABLE PGA+ P PTE1/ADP9 VDD2 REGULATOR GAIN AMPLIFIER (PGA) PGA– PTE0/ADP8 VSS2 (Only on MC9S08MP16) CIN1 PTF2 C1IN2 F DIGITAL-TO-ANALOG HIGH SPEED ANALOG C1IN3 RT PTF1/RESET CONVERTER (DAC1) COMPARATOR (HSCMP1) C1IN4 O PTF0/BKGD/MS P CMP1OUT C2IN2 DIGITAL-TO-ANALOG HIGH SPEED ANALOG C2IN3 CONVERTER (DAC2) COMPARATOR (HSCMP2) C2IN4 pins not available on 28-pin packages CMP2OUT pins not available on 32-pin or 28-pin packages C3IN2 DIGITAL-TO-ANALOG HIGH SPEED ANALOG C3IN3 CONVERTER (DAC3) COMPARATOR (HSCMP3) C3IN4 CMP3OUT Notes: When PTF1 is configured as RESET, pin becomes bi-directional with output being open-drain drive containing an internal pull-up device. When PTF0 is configured as BKGD, pin becomes bi-directional. V pad is tied internally on 32-pin and 28-pin packages, DD2 V pad is tied internally on 28-pin packages SS2 Figure1. MC9S08MP16 Series Block Diagram MC9S08MP16 Series Data Sheet, Rev. 2 Freescale Semiconductor 3

Pin Assignments 1 Pin Assignments This section shows the pin assignments for the MC9S08MP16 Series devices. 3 4 N N 3I 2I C C 6/ 5/ P P D D 4 A A H3 H2 H1 H0 3IN UT/ UT/ C C C C C O O 2 2 2 2 7/ 3 2 M M M M P P P T T T T D M M F F F F S A C C BI2P3/ BI2P2/ BI2P1/ BI2P0/ KGD/M XTAL TAL BI1P7/ BI1P6/ BI1P5/ K K K K B E X K K K C3/ C2/ C1/ C0/ F0/ D2 S2 E6/ E5/ B7/ B6/ B5/ T T T T T D S T T T T T P P P P P V V P P P P P 8 7 6 5 4 3 2 1 0 9 8 7 4 4 4 4 4 4 4 4 4 3 3 3 PTC4/KBI2P4/FTM2CH4 1 36 PTB4/KBI1P4/ADP4/C2IN3 PTC5/KBI2P5/FTM2CH5 2 35 PTE4/ADP12/C1IN4 PTC6/KBI2P6/FTM2FAULT 3 34 PTE3/ADP11/C1IN3 PTC7/KBI2P7/TCLK 4 33 VSSA/VREFL PTD0/KBI3P0/SDA 5 32 VDDA/VREFH PTD1/KBI3P1/SCL 6 31 PTB3/KBI1P3/ADP3/C3IN2/PGA– PTD2/KBI3P2/PDB1OUT 7 30 PTB2/KBI1P2/ADP2/C1IN2/PGA+ PTD3/KBI3P3/FTM1FAULT 8 29 PTB1/KBI1P1/ADP1/C2IN2 VSS1 9 28 PTB0/KBI1P0/ADP0/CIN1 VDD1 10 27 PTE2/ADP10 PTA0/SDA/TxD 11 26 PTE1/ADP9 PTA1/SCL/RxD 12 25 PTE0/ADP8 3 4 5 6 7 8 9 0 1 2 3 4 1 1 1 1 1 1 1 2 2 2 2 2 FTM1CH0 FTM1CH1 PDB2OUT CMP1OUT CMP2OUT CMP3OUT F1/RESET PTF2 K/SDA/SS SCL/MISO TA6/MOSI A7/SPSCK PTA2/SDA/ PTA3/SCL/ D4/KBI3P4/ D5/KBI3P5/ D6/KBI3P6/ D7/KBI3P7/ PT PTA4/TCL PTA5/ P PT T T T T P P P P Note:Pins in bold are lost in the next lower pin count package. Figure2. MC9S08MP16 Series in 48-LQFP MC9S08MP16 Series Data Sheet, Rev. 2 4 Freescale Semiconductor

Pin Assignments 3 N 3I C 6/ P D 4 A M2CH1 M2CH0 P7/C3IN P3OUT/ FT FT S AD CM BI2P1/ BI2P0/ KGD/M XTAL TAL BI1P7/ BI1P6/ K K B E X K K C1/ C0/ F0/ S2 E6/ E5/ B7/ B6/ T T T S T T T T P P P V P P P P 32 31 30 29 28 27 26 25 PTC2/KBI2P2/FTM2CH2 1 24 PTB5/KBI1P5/CMP2OUT/ADP5/C2IN4 PTC3/KBI2P3/FTM2CH3 2 23 PTB4/KBI1P4/ADP4/C2IN3 PTC4/KBI2P4/FTM2CH4 3 22 VSSA/VREFL PTC5/KBI2P5/FTM2CH5 4 21 VDDA/VREFH PTC6/KBI2P6/FTM2FAULT 5 20 PTB3/KBI1P3/ADP3/C3IN2/PGA– VSS1 6 19 PTB2/KBI1P2/ADP2/C1IN2/PGA+ VDD1 7 18 PTB1/KBI1P1/ADP1/C2IN2 PTA0/SDA/TxD 8 17 PTB0/KBI1P0/ADP0/CIN1 9 10 11 12 13 14 15 16 TA1/SCL/RxD DA/FTM1CH0 CL/FTM1CH1 PTF1/RESET CL:K/SDA/SS A5/SCL/MISO PTA6/MOSI PTA7/SPSCK P S S T T 2/ 3/ 4/ P TA TA TA Note:Pins in bold are lost in the next P P P lower pin count package. Figure3. MC9S08MP16 Series in 32-Pin LQFP Package MC9S08MP16 Series Data Sheet, Rev. 2 Freescale Semiconductor 5

Pin Assignments PTC0/KBI2P0/FTM2CH0 1 28 PTF0/BKGD/MS PTC1/KBI2P1/FTM2CH1 2 27 PTB6/KBI1P6/CMP3OUT/ADP6/C3IN3 PTC2/KBI2P2/FTM2CH2 3 26 PTB5/KBI1P5/CMP2OUT/ADP5/C2IN4 PTC3/KBI2P3/FTM2CH3 4 25 PTB4/KBI1P4/ADP4/C2IN3 PTC4/KBI2P4/FTM2CH4 5 24 VSSA/VREFL PTC5/KBI2P5/FTM2CH5 6 23 VDDA/VREFH PTC6/KBI2P6/FTM2FAULT 7 22 PTB3/KBI1P3/ADP3/C3IN2/PGA– VSS1 8 21 PTB2/KBI1P2/ADP2/C1IN2/PGA+ VDD1 9 20 PTB1/KBI1P1/ADP1/C2IN2 PTA0/SDA/TxD 10 19 PTB0/KBI1P0/ADP0/CIN1 PTA1/SCL/RxD 11 18 PTA7/SPSCK PTA2/SDA/FTM1CH0 12 17 PTA6/MOSI PTA3/SCL/FTM1CH1 13 16 PTA5/SCL/MISO PTF1/RESET 14 15 PTA4/TCLK/SDA/SS Figure4. MC9S08MP16 Series in 28-Pin SOIC Package MC9S08MP16 Series Data Sheet, Rev. 2 6 Freescale Semiconductor

Pin Assignments Table1. Pin Availability by Package Pin-Count Pin Number <-- Lowest Priority --> Highest 32 48 28 Port Pin Alt 1 Alt 2 Alt3 Alt4 LQFP 1 3 5 PTC4 KBI2P4 FTM2CH4 2 4 6 PTC5 KBI2P5 FTM2CH5 3 5 7 PTC6 KBI2P6 FTM2FAULT 4 — — PTC7 KBI2P7 TCLK1 5 — — PTD0 KBI3P0 SDA5 6 — — PTD1 KBI3P1 SCL5 7 — — PTD2 KBI3P2 PDB1OUT 8 — — PTD3 KBI3P3 FTM1FAULT 9 6 8 V SS1 10 7 9 V DD1 11 8 10 PTA0 SDA5 TxD 12 9 11 PTA1 SCL5 RxD 13 10 12 PTA2 SDA5 FTM1CH0 14 11 13 PTA3 SCL5 FTM1CH1 15 — — PTD4 KBI3P4 PDB2OUT 16 — — PTD5 KBI3P5 CMP1OUT 17 — — PTD6 KBI3P6 CMP2OUT2 18 — — PTD7 KBI3P7 CMP3OUT3 19 12 14 PTF1 RESET4 20 — — PTF2 21 13 15 PTA4 TCLK1 SDA5 SS 22 14 16 PTA5 SCL5 MISO 23 15 17 PTA6 MOSI 24 16 18 PTA7 SPSCK 25 — — PTE0 ADP8 26 — — PTE1 ADP9 27 — — PTE2 ADP10 28 17 19 PTB0 KBI1P0 ADP06 CIN16 29 18 20 PTB1 KBI1P1 ADP16 C2IN26 30 19 21 PTB2 KBI1P2 ADP26 C1IN26 PGA+6 31 20 22 PTB3 KBI1P3 ADP36 C3IN26 PGA–6 32 21 23 V /V DDA REFH 33 22 24 V /V SSA REFL 34 — — PTE3 ADP116 C1IN36 MC9S08MP16 Series Data Sheet, Rev. 2 Freescale Semiconductor 7

Electrical Characteristics Table1. Pin Availability by Package Pin-Count (continued) Pin Number <-- Lowest Priority --> Highest 32 48 28 Port Pin Alt 1 Alt 2 Alt3 Alt4 LQFP 35 — — PTE4 ADP126 C1IN46 36 23 25 PTB4 KBI1P4 ADP46 C2IN36 37 24 26 PTB5 KBI1P5 CMP2OUT2 ADP56 C2IN46 38 25 27 PTB6 KBI1P6 CMP3OUT3 ADP66 C3IN36 39 26 — PTB7 KBI1P7 ADP76 C3IN46 40 27 — PTE5 XTAL 41 28 — PTE6 EXTAL 42 29 — V SS2 43 — — V DD2 44 30 28 PTF0 BKGD MS 45 31 1 PTC0 KBI2P0 FTM2CH0 46 32 2 PTC1 KBI2P1 FTM2CH1 47 1 3 PTC2 KBI2P2 FTM2CH2 48 2 4 PTC3 KBI2P3 FTM2CH3 1 TCLK pin can be repositioned using TCLKPS in SOPT2. Default reset location is PTC7. 2 HSCMP2 output CMP2OUT can be repositioned using the CMP2OPS in the SOPT2 register. Default reset location is PTD6. 3 HSCMP3 output CMP3OUT can be repositioned using the CMP3OPS in the SOPT2 register. Default reset location is PTD7. 4 Pin is open drain with an internal pullup that is always enabled. Pin does not contain a clamp diode to V and should not be driven above V . The voltage measured on the internally DD DD pulled up RESET will not be pulled to V . The internal gates connected to this pin are pulled DD to V . DD 5 IIC pins SDA and SCL can be repositioned using IICPS in SOPT2. Default reset locations are PTD0 and PTD1. 6 If ADC, HSCMP, or PGA is enabling a shared analog input pin, each has access to the pin. 2 Electrical Characteristics 2.1 Introduction This section contains electrical and timing specifications for the MC9S08MP16 Series of microcontrollers available at the time of publication. MC9S08MP16 Series Data Sheet, Rev. 2 8 Freescale Semiconductor

Electrical Characteristics 2.2 Parameter Classification The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate: Table2. Parameter Classifications P Those parameters that are guaranteed during production testing on each individual device. Those parameters that are achieved by the design characterization by measuring a statistically relevant C sample size across process variations. Those parameters that are achieved by design characterization on a small sample size from typical T devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. D Those parameters that are derived mainly from simulations. NOTE The classification is shown in the column labeled “C” in the parameter tables where appropriate. 2.3 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in Table3 may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either V or V ) or the programmable pull-up resistor associated with the pin is enabled. SS DD Table3. Absolute Maximum Ratings Rating Symbol Value Unit Supply voltage V –0.3 to +5.8 V DD Maximum current into V I 120 mA DD DD Digital input voltage V –0.3 to V +0.3 V In DD Instantaneous maximum current I  25 mA D Single pin limit (applies to all port pins)1,2,3 Storage temperature range T –55 to 150 C stg 1 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive (V ) and negative (V ) clamp DD SS voltages, then use the larger of the two resistance values. 2 All functional non-supply pins, except for PTF1/RESET are internally clamped to V and V . SS DD 3 Power supply must maintain regulation within operating V range during instantaneous and DD operating maximum current conditions. If positive injection current (V > V ) is greater than In DD I , the injection current may flow out of V and could result in external power supply going DD DD out of regulation. Ensure external V load will shunt current greater than maximum injection DD current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if the clock rate is very low (which would reduce overall power consumption). MC9S08MP16 Series Data Sheet, Rev. 2 Freescale Semiconductor 9

Electrical Characteristics 2.4 Thermal Characteristics This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the MCU design. To take P into account in power calculations, determine I/O the difference between actual pin voltage and V or V and multiply by the pin current for each I/O pin. Except in cases of SS DD unusually high pin current (heavy loads), the difference between pin voltage and V or V will be very small. SS DD Table4. Thermal Characteristics Consumer & Num C Rating Symbol Automotive Unit Industrial 1 — Operating temperature range (packaged) T –40 to 105 –40 to 125 C A 2 D Maximum junction temperature T 115 135 C J 3 D Thermal resistance 1,2 single-layer board 48-pin LQFP 80 80 32-pin LQFP  85 — C/W JA 28-pin SOIC 71 — 4 D Thermal resistance 1,2 four-layer board 48-pin LQFP 56 56 32-pin LQFP  57 — C/W JA 28-pin SOIC 48 — 1 Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2 Junction-to-ambient natural convection The average chip-junction temperature (T ) in C can be obtained from: J T = T + (P   ) Eqn.1 J A D JA where: T = Ambient temperature, C A  = Package thermal resistance, junction-to-ambient, C/W JA P = P P D int I/O P = I  V , Watts — chip internal power int DD DD P = Power dissipation on input and output pins — user determined I/O For most applications, P  P and can be neglected. An approximate relationship between P and T (if P is neglected) I/O int D J I/O is: P = K  (T + 273C) Eqn.2 D J Solving Equation1 and Equation2 for K gives: K = P  (T + 273C) +   (P )2 Eqn.3 D A JA D MC9S08MP16 Series Data Sheet, Rev. 2 10 Freescale Semiconductor

Electrical Characteristics where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring P (at equilibrium) D for a known T . Using this value of K, the values of P and T can be obtained by solving Equation1 and Equation2 iteratively A D J for any value of T . A 2.5 ESD Protection and Latch-Up Immunity Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits, normal handling precautions should be taken to avoid exposure to static discharge. Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage. All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During the device qualification, ESD stresses were performed for the human body model (HBM) and the charge device model (CDM). A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless instructed otherwise in the device specification. Table5. ESD and Latch-up Test Conditions Model Description Symbol Value Unit Human Series resistance R1 1500  Body Storage capacitance C 100 pF Number of pulses per pin — 3 Latch-up Minimum input voltage limit – 2.5 V Maximum input voltage limit 7.5 V Table6. ESD and Latch-Up Protection Characteristics No. Rating1 Symbol Min Max Unit 1 Human body model (HBM) V 2000 — V HBM 2 Charge device model (CDM) V 500 — V CDM 3 Latch-up current at T = 125C I 100 — mA A LAT 1 Parameter is achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. 2.6 DC Characteristics This section includes information about power supply requirements and I/O pin characteristics. Table7. DC Characteristics Num C Characteristic Symbol Condition Min Typ1 Max Unit 1 — Operating Voltage V 2.7 — 5.5 V DD 2 — Analog Supply voltage delta to V (V –V )(2) V — 0 100 mV DD DD DDA DDA 3 — Analog Ground voltage delta to V (V –V )(2) V — 0 100 mV SS SS SSA SSA MC9S08MP16 Series Data Sheet, Rev. 2 Freescale Semiconductor 11

Electrical Characteristics Table7. DC Characteristics (continued) Num C Characteristic Symbol Condition Min Typ1 Max Unit C All I/O pins (except PTF1/RESET) 5 V, I = –4 mA V – 1.5 — — Load DD P low-drive strength 5 V, I = –2 mA V – 0.8 — — Load DD C Output high V 3 V, I = –1 mA V – 0.8 — — V OH Load DD 4 C voltage 5 V, I = –20 mA V – 1.5 — — Load DD P high-drive strength 5 V, I = –10 mA V – 0.8 — — Load DD C 3 V, I = –5 mA V – 0.8 — — Load DD 5 D Output high current Max total I for all ports I V < V 0 — –100 mA OH OHT OUT DD C All I/O pins 5 V, I = 4 mA — — 1.5 Load P (except PTF1/RESET) 5 V, I = 2 mA — — 0.8 Load C low-drive strength V 3 V, I = 1 mA — — 0.8 V OL Load 6 C All I/O pins 5 V, I = 20 mA — — 1.5 Load P Output low (Except PTF1/RESET) 5 V, I = 10 mA — — 0.8 Load C voltage high-drive strength 3 V, I = 5 mA — — 0.8 Load 7 C PTF1/RESET 5 V, I = 3.2 mA — — 1.5 Load 8 P 5 V, I = 1.6 mA — — 0.8 Load 9 C 3 V, I = 0.8 mA — — 0.8 Load 10 D Output low current Max total I for all ports I V > V 0 — 100 mA OL OLT OUT SS P Input high voltage; all digital inputs V 5V 0.65 x V — — V IH DD 11 C 3V 0.7 x V — — DD P Input low voltage; all digital inputs V 5V — — 0.35 x V V IL DD 12 C 3V — — 0.35 x V DD 13 C Input hysteresis V 0.06 x V V hys DD   14 P Input leakage current (per pin) I V = V or V — — 1 A In In DD SS P Hi-Z (off-state) leakage current (per pin)   15 input/output port pins IOZ VIn = VDD or VSS — — 1 A PTF1/RESET, V = V or V — — 2 A In DD SS PTE5/XTAL pins Pullup or Pulldown3 resistors; when enabled 16 P I/O pins R ,R 17 37 52 k PU PD C PTF1/RESET4 R 17 37 52 k PU D DC injection current 5, 6, 7, 8 Single pin limit V > V 0 — 2 mA IN DD 17 I V < V 0 — –0.2 mA IC IN SS Total MCU limit, includes V > V 0 — 25 mA IN DD sum of all stressed pins V < V 0 — –5 mA IN SS MC9S08MP16 Series Data Sheet, Rev. 2 12 Freescale Semiconductor

Electrical Characteristics Table7. DC Characteristics (continued) Num C Characteristic Symbol Condition Min Typ1 Max Unit 13 C Input Capacitance, all pins C — — 8 pF In 14 C RAM retention voltage V — 0.6 1.0 V RAM 15 C POR re-arm voltage9 V 0.9 1.4 2.0 V POR 16 D POR re-arm time t 10 — — s POR P Low-voltage detection threshold — high range V 17 LVD1 V falling 3.9 4.0 4.1 V DD V rising 4.0 4.1 4.2 DD P Low-voltage detection threshold — low range V 18 LVD0 V falling 2.48 2.56 2.64 V DD V rising 2.54 2.62 2.70 DD P Low-voltage warning threshold — high range 1 V 19 LVW3 V falling 4.5 4.6 4.7 V DD V rising 4.6 4.7 4.8 DD P Low-voltage warning threshold — high range 0 V 20 LVW2 V falling 4.2 4.3 4.4 V DD V rising 4.3 4.4 4.5 DD P Low-voltage warning threshold low range 1 V 21 LVW1 V falling 2.84 2.92 3.00 V DD V rising 2.90 2.98 3.06 DD P Low-voltage warning threshold — low range 0 V 22 LVW0 V falling 2.66 2.74 2.82 V DD V rising 2.72 2.80 2.88 DD T Low-voltage inhibit reset/recover hysteresis V 5 V — 100 — hys 23 mV 3 V — 60 — 24 P Bandgap voltage reference at 25C10 1.18 1.202 1.21 V Bandgap voltage reference across temperature VBG 1.17 — 1.22 25 P V range10 1 Typical values are measured at 25C. Characterized, not tested 2 DC potential difference. 3 When keyboard interrupt is configured to detect rising edges, pulldown resistors are used in place of pullup resistors. 4 The specified resistor value is the actual value internal to the device. The pullup value may measure higher when measured externally on the pin. 5 Power supply must maintain regulation within operating V range during instantaneous and operating maximum current conditions. If DD positive injection current (V > V ) is greater than I , the injection current may flow out of V and could result in external power supply In DD DD DD going out of regulation. Ensure external V load will shunt current greater than maximum injection current. This will be the greatest risk DD when the MCU is not consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption). 6 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. MC9S08MP16 Series Data Sheet, Rev. 2 Freescale Semiconductor 13

Electrical Characteristics 7 All functional non-supply pins except PTF1/RESET are internally clamped to V and V . SS DD 8 The PTF1/RESET pin does not have a clamp diode to V . Do not drive this pin above V . DD DD 9 Maximum is highest voltage that POR is guaranteed. 10Factory trimmed at V = 5.0 V DD 2 1.0 12255°°CC Max 1.5V@20mA 12255°°CC Max 0.8V@5mA –40°C –40°C 0.8 1.5 ) )0.6 V V (L 1 (L O O V V0.4 0.5 0.2 0 0 0 5 10 15 20 25 0 2 4 6 8 10 I (mA) I (mA) OL OL a) V = 5V, High Drive b) V = 3V, High Drive DD DD Figure5. Typical V vs I , High Drive Strength (except PTF1/RESET) OL OL 2 1.0 12255°°CC Max 1.5V@4mA 12255°°CC Max 0.8V@1mA –40°C –40°C 0.8 1.5 ) )0.6 V V (L 1 (L O O V V0.4 0.5 0.2 0 0 0 1 2 3 4 5 0 0.4 0.8 1.2 1.6 2.0 I (mA) I (mA) OL OL a) V = 5V, Low Drive b) V = 3V, Low Drive DD DD Figure6. Typical V vs I , Low Drive Strength (except PTF1/RESET) OL OL MC9S08MP16 Series Data Sheet, Rev. 2 14 Freescale Semiconductor

Electrical Characteristics 2 1.0 12255°°CC Max 1.5V@ –20mA 12255°°CC Max 0.8V@ –5mA –40°C –40°C 0.8 1.5 V) V) (H (H 0.6 O O V 1 V – – D D 0.4 D D V V 0.5 0.2 0 0 0 –5 –10 –15 –20 –25 0 –2 –4 –6 –8 –10 I (mA) I (mA) OH OH a) V = 5V, High Drive b) V = 3V, High Drive DD DD Figure7. Typical V – V vs I , High Drive Strength DD OH OH 2 1.0 12255°°CC Max 1.5V@ –4mA 12255°°CC Max 0.8V@ –1mA –40°C –40°C 0.8 1.5 V) V) (H (H 0.6 O O V 1 V – – D D 0.4 D D V V 0.5 0.2 0 0 0 –1 –2 –3 –4 –5 0 –0.4 –0.8 –1.2 –1.6 –2.0 I (mA) I (mA) OH OH a) V = 5V, Low Drive b) V = 3V, Low Drive DD DD Figure8. Typical V – V vs I , Low Drive Strength DD OH OH 2.7 Supply Current Characteristics This section includes information about power supply current in various operating modes. Table8. Supply Current Characteristics V Num C Parameter Symbol DD Typ1 Max2 Unit (V) 3 C Run supply current measured at 5 2.16 3 1 C (CPU clock = 4MHz, fBus = 2 MHz) RIDD 3 1.8 2.5 mA P Run supply current3 measured at 5 5.26 7.5 2 C (CPU clock = 16MHz, fBus = 8 MHz) RIDD 3 4.92 7 mA MC9S08MP16 Series Data Sheet, Rev. 2 Freescale Semiconductor 15

Electrical Characteristics Table8. Supply Current Characteristics (continued) V Num C Parameter Symbol DD Typ1 Max2 Unit (V) 4 C Run supply current measured at 5 9.4 10 3 C (CPU clock = 32MHz, fBus = 16MHz) RIDD 3 9 10 mA 5 P Run supply current measured at 5 14.3 30 4 C (CPU clock = 51.34MHz, fBus = 25.67 MHz) RIDD 3 13.9 20 mA P Run supply current measured at 5 16 30 5 (CPU clock = 40MHz, f = 20MHz) RIDD mA — Bus 3 — — Wait mode supply current measured at 6 C (CPU clock = 8MHz, f = 4MHz) WI 5 2.7 — mA Bus DD (FEI mode, all modules off) Stop3 mode supply current C –40C 0.96 — P 25C 1.3 — C 85C 5 7.5 25 A P6 105C 37 90 7 P 125C 65 150 S3I DD C –40C 0.85 — P 25C 1.2 — C 85C 3 6.5 20 A P6 105C 32.7 80 P 125C 58 130 Stop2 mode supply current C –40C 0.94 — P 25C 1.25 — C 85C 5 7 25 A P6 105C 30 65 8 P 125C 64 120 S2I DD C –40C 0.83 — P 25C 1.1 — C 85C 3 6.3 20 A P6 105C 25 55 P 125C 57 100 C RTC adder to stop2 or stop37 S23I 5 300 500 nA 9 DDRTC 3 300 500 nA MC9S08MP16 Series Data Sheet, Rev. 2 16 Freescale Semiconductor

Electrical Characteristics Table8. Supply Current Characteristics (continued) V Num C Parameter Symbol DD Typ1 Max2 Unit (V) C LVD adder to stop3 (LVDE = LVDSE = 1) S3I 5 110 180 A 10 DDLVD 3 90 160 A C Adder to stop3 for oscillator enabled8 S3I 11 DDOSC 5,3 5 8 A (EREFSTEN =1) 1 Typical values are based on characterization data at 25C. See Figure9 through Figure14 for typical curves across temperature and voltage. 2 Max values in this column apply for the full operating temperature range of the device unless otherwise noted. 3 All modules except ADC active, ICS configured for FBELP, and does not include any dc loads on port pins 4 All modules except ADC active, ICS configured for FEI, and does not include any dc loads on port pins 5 All modules except ADC active, ICS configured for FEI, and does not include any dc loads on port pins 6 Stop currents are tested in production for 25C on all parts. Tests at other temperatures depend upon the part number suffix and maturity of the product. Freescale may eliminate a test insertion at a particular temperature from the production test flow once sufficient data has been collected and is approved. 7 Most customers are expected to find that auto-wakeup from stop2 or stop3 can be used instead of the higher current wait mode. 8 Values given under the following conditions: low range operation (RANGE = 0) with a 32.768kHz crystal and low power mode (HGO = 0). 16 FBE FEI 14 12 A) 10 m ( d 8 d n I u 6 R 4 2 0 2 8 16 20 25 fbus (MHz) Figure9. Typical Run I vs. Bus Frequency (V = 5V) DD DD MC9S08MP16 Series Data Sheet, Rev. 2 Freescale Semiconductor 17

Electrical Characteristics 6 FBE FEI 5 A) m 4 ( D D n I 3 u R 2 1 -40 0 25 85 105 125 Temperature (C) Figure10. Typical Run I vs. Temperature (V = 5V, f = 8MHz) DD DD bus 16 FBE FEI 14 12 A) 10 m ( d 8 d I n u 6 R 4 2 0 2 8 16 20 25 fbus (MHz) Figure11. Typical Run I vs. Bus Frequency (V = 3V) DD DD MC9S08MP16 Series Data Sheet, Rev. 2 18 Freescale Semiconductor

Electrical Characteristics 6 FBE FEI 5 A) m 4 ( D D n I 3 u R 2 1 -40 0 25 85 105 125 Temperature (C) Figure12. Typical Run I vs. Temperature (V = 3V, f = 8MHz) DD DD bus 70 STOP2 STOP3 60 50 A) u ( 40 D D p I 30 o t S 20 10 0 -40 25 85 105 125 Temperature (C) Figure13. Typical Stop I vs. Temperature (V = 5V) DD DD MC9S08MP16 Series Data Sheet, Rev. 2 Freescale Semiconductor 19

Electrical Characteristics 70 STOP2 STOP3 60 50 A) u ( 40 D D p I 30 o t S 20 10 0 -40 25 85 105 125 Temperature (C) Figure14. Typical Stop I vs. Temperature (V = 3V) DD DD 2.8 External Oscillator (XOSC) Characteristics Table9. Oscillator Electrical Specifications Num C Rating Symbol Min Typ1 Max Unit Oscillator crystal or resonator (EREFS=1, ERCLKEN = 1) Low range (RANGE = 0) flo 32 — 38.4 kHz 1 C High range (RANGE = 1) FEE2 or FBE3 mode fhi 1 — 16 MHz High range (RANGE = 1, HGO = 1) FBELP mode fhi-hgo 1 — 16 MHz High range (RANGE = 1, HGO = 0) FBELP mode fhi-lp 1 — 8 MHz Load capacitors See crystal or resonator 2 — C1, C2 manufacturer’s recommendation. Feedback resistor 3 — Low range (32 kHz to 100 kHz) RF — 10 — M High range (1 MHz to 16 MHz) — 1 — Series resistor Low range, low gain (RANGE = 0, HGO = 0) — 0 — Low range, high gain (RANGE = 0, HGO = 1) — 100 — High range, low gain (RANGE = 1, HGO = 0) — 0 — 4 — RS k High range, high gain (RANGE = 1, HGO = 1)  8 MHz — 0 0  MHz — 0 10  MHz — 0 20 MC9S08MP16 Series Data Sheet, Rev. 2 20 Freescale Semiconductor

Electrical Characteristics Table9. Oscillator Electrical Specifications (continued) Num C Rating Symbol Min Typ1 Max Unit Crystal start-up time 4 Low range, low gain (RANGE = 0, HGO = 0) t — 200 — CSTL-LP 5 T Low range, high gain (RANGE = 0, HGO = 1) tCSTL-HGO — 400 — ms High range, low gain (RANGE = 1, HGO = 0)5 t — 5 — CSTH-LP High range, high gain (RANGE = 1, HGO = 1)4 t — 20 — CSTH-HGO Square wave input clock frequency (EREFS=0, ERCLKEN = 1) FEE mode 2 0.03125 — 51.34 MHz 6 T fextal FBE mode 3 0 — 51.34 MHz FBELP mode 0 — 51.34 MHz 1 Typical data was characterized at 5.0 V, 25C or is recommended value. 2 The input clock source must be divided using RDIV to within the range of 31.25 kHz to 39.0625 kHz. 3 The input clock source must be divided using RDIV to less than or equal to 39.0625 kHz. 4 This parameter is characterized and not tested on each device. Proper PC board layout procedures must be followed to achieve specifications. 5 4 MHz crystal MCU EXTAL XTAL R R S F C1 Crystal or Resonator C2 2.9 Internal Clock Source (ICS) Characteristics Table10. ICS Frequency Specifications Num C Characteristic Symbol Min Typ1 Max Unit Average internal reference frequency — factory trimmed 1a P (consumer- and industrial-qualified devices) fint_t — 32.768 — kHz at V = 5 V and temperature = 25C DD Average internal reference frequency — factory trimmed 1b P (automotive-qualified devices) fint_t — 31.25 — kHz at V = 5 V and temperature = 25C DD 2 P Internal reference frequency — user trimmed fint_t 31.25 — 39.06 kHz 3 T Internal reference start-up time tirefst — 60 100 s MC9S08MP16 Series Data Sheet, Rev. 2 Freescale Semiconductor 21

Electrical Characteristics Table10. ICS Frequency Specifications (continued) Num C Characteristic Symbol Min Typ1 Max Unit P Low range (DRS=00) 16 — 20 DCO output frequency range — 4 C trimmed 2 Mid range (DRS=01) fdco_t 32 — 40 MHz P High range (DRS=10) 48 — 60 P Low range (DRS=00) — 19.92 — DCO output frequency 2 5 P Reference = 32768 Hz and Mid range (DRS=01) fdco_DMX32 — 39.85 — MHz DMX32 = 1 P High range (DRS=10) — 59.77 — Resolution of trimmed DCO output frequency at fixed voltage and 6 C temperature (using FTRIM) fdco_res_t — 0.1 0.2 %fdco Resolution of trimmed DCO output frequency at fixed voltage and 7 C temperature (not using FTRIM) fdco_res_t — 0.2 0.4 %fdco Total deviation of trimmed DCO output frequency over voltage and 8 P temperature fdco_t — 0.8 2 %fdco Total deviation of trimmed DCO output frequency over fixed voltage 9 C and temperature range of 0C to 70 C fdco_t — 0.5 1 %fdco 10 C FLL acquisition time 3 tAcquire — — 1 ms 11 C Long term jitter of DCO output clock (averaged over 2-ms interval) 4 CJitter — 0.02 0.2 %fdco 1 Data in Typical column was characterized at 3.0 V, 25C or is typical recommended value. 2 The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device. 3 This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 4 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f . Bus Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry via V and V and variation in crystal oscillator frequency increase the C percentage for a given DD SS Jitter interval. MC9S08MP16 Series Data Sheet, Rev. 2 22 Freescale Semiconductor

Electrical Characteristics 3% y c n 2% e u q e r F 1% d e m m 0% ri T m o -1% r f n o ati -2% vi e D -3% -40 -20 0 20 40 60 80 100 120 Temperature (C) Figure15. Typical Frequency Deviation vs Temperature (ICS Trimmed to 25 MHz bus@25°C, 5V, FEI)1 2.10 ADC Characteristics Table11. 12-bit ADC Operating Conditions Characteristic Conditions Symbol Min Typ1 Max Unit Comment Supply voltage Absolute V 2.7 — 5.5 V DDA Input Voltage V V — V V ADIN REFL REFH Input Capacitance C — 4.5 5.5 pF ADIN Input Resistance R — 3 5 k ADIN Analog Source 12 bit mode R k External to MCU AS Resistance f > 4MHz — — 2 ADCK f < 4MHz — — 5 ADCK 10 bit mode f > 4MHz — — 5 ADCK f < 4MHz — — 10 ADCK 8 bit mode (all valid f ) — — 10 ADCK ADC Conversion High Speed (ADLPC=0) f 0.4 — 8.0 MHz ADCK Clock Freq. Low Power (ADLPC=1) 0.4 — 4.0 1 Typical values assume V = 5.0V, Temp = 25C, f =1.0MHz unless otherwise stated. Typical values are for reference DDAD ADCK only and are not tested in production. 1.Based on the average of several hundred units from a typical characterization lot. MC9S08MP16 Series Data Sheet, Rev. 2 Freescale Semiconductor 23

Electrical Characteristics SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT ZADIN SIMPLIFIED Pad ZAS leakage CHANNEL SELECT due to CIRCUIT ADC SAR R input R ENGINE AS protection ADIN + V ADIN – C V + AS AS – R ADIN INPUT PIN R ADIN INPUT PIN R ADIN INPUT PIN C ADIN Figure16. ADC Input Impedance Equivalency Diagram Table12. 12-bit ADC Characteristics (V = V , V = V ) REFH DDAD REFL SSAD C Characteristic Conditions Symb Min Typ1 Max Unit Comment T Supply Current I — 133 — A DDA ADLPC=1 ADLSMP=1 ADCO=1 T Supply Current I — 218 — A DDA ADLPC=1 ADLSMP=0 ADCO=1 T Supply Current I — 327 — A DDA ADLPC=0 ADLSMP=1 ADCO=1 T Supply Current I — 0.582 — mA DDA ADLPC=0 ADLSMP=0 ADCO=1 P ADC Asynchronous High Speed (ADLPC=0) f 2 3.3 5 MHz t = ADACK ADACK Clock Source 1/f Low Power (ADLPC=1) 1.25 2 3.3 ADACK MC9S08MP16 Series Data Sheet, Rev. 2 24 Freescale Semiconductor

Electrical Characteristics Table12. 12-bit ADC Characteristics (V = V , V = V ) (continued) REFH DDAD REFL SSAD C Characteristic Conditions Symb Min Typ1 Max Unit Comment D Conversion Time Short Sample (ADLSMP=0) t — 20 — ADCK See ADC ADC (Including sample cycles chapter in the Long Sample (ADLSMP=1) — 40 — time) Reference Manual for D Sample Time Short Sample (ADLSMP=0) t — 3.5 — ADCK ADS conversion time cycles Long Sample (ADLSMP=1) — 23.5 — variances T Temp Sensor -40C to 25C m — 3.266 — mV/C Slope 25C to 125C — 3.638 — T Temp Sensor 25C V — 1.396 — mV TEMP25 Voltage T Total Unadjusted 12 bit mode E — 3.0 6.5 LSB2 Includes TUE Error quantization P 10 bit mode — 1 2.5 T 8 bit mode — 0.5 1.0 T Differential 12 bit mode DNL — 1.75 3.5 LSB2 Non-Linearity P 10 bit mode3 — 0.5 1.0 T 8 bit mode3 — 0.3 0.5 T Integral 12 bit mode INL — 1.5 4.5 LSB2 Non-Linearity P 10 bit mode — 0.5 1.0 T 8 bit mode — 0.3 0.5 T Zero-Scale Error 12 bit mode E — 1.5 0.0/ LSB2 V = V ZS ADIN SSAD -3.0 P 10 bit mode — 0.5 1.5 T 8 bit mode — 0.5 0.5 T Full-Scale Error 12 bit mode E — 1.0 +1.75/ LSB2 V = V FS ADIN DDAD 1.25 T 10 bit mode — 0.5 1 T 8 bit mode — 0.5 0.5 D Quantization Error 12 bit mode E — -1 to 0 — LSB2 Q 10 bit mode — — 0.5 8 bit mode — — 0.5 D Input Leakage Error 12 bit mode E — 1 — LSB2 Pad leakage4 * IL R 10 bit mode — 0.2 2.5 AS 8 bit mode — 0.1 1 1 Typical values assume V = 5.0V, Temp = 25C, f =1.0MHz unless otherwise stated. Typical values are for reference DDAD ADCK only and are not tested in production. 2 1 LSB = (V - V )/2N REFH REFL 3 Monotonicity and No-Missing-Codes guaranteed in 10 bit and 8 bit modes 4 Based on input pad leakage current. Refer to pad electricals. MC9S08MP16 Series Data Sheet, Rev. 2 Freescale Semiconductor 25

Electrical Characteristics 2.11 Digital to Analog (DAC) Characteristics • The accuracy at worst case: +/- 1.5% maximum • The settling time must be less than 100ns • When changing the output voltage level, the voltage glitch cannot be completely eliminated Table13. 5-bit DAC Characteristics Num C Characteristic Symbol Min Typical Max Unit 2 D Supply current adder (enabled) I — — 20 A DDAC 3 D DAC reference inputs Vin V — V V SSA DDA 5 D DAC step size V 0.75V /32 V /32 1.25V /32 V step in in in 6 D DAC voltage range V V /32 — V V dacout in in 2.12 High Speed Comparator (HSCMP) Characteristics Table14. High Speed Comparator Electrical Specifications Num C Characteristic1 Symbol Min Typical Max Unit 1 D Supply current, High Speed Mode I — 200 A DDAHS (EN=1, PMODE=1) 2 D Supply current, Low Speed Mode I — 10 A DDALS (EN=1, PMODE=0) 3 — Analog input voltage V V — V V AIN SSA DDA 4 P Analog input offset voltage V — 5 40 mV AIO 5 C Analog Comparator hysteresis V 3.0 9 20.0 mV H 6 T Propagation Delay, High Speed Mode t 2 — 70 120 ns DHS (EN=1, PMODE=1) 7 T Propagation Delay, Low Speed Mode t 2 — 400 600 ns DLS (EN=1, PMODE=0) 8 D Analog comparator initialization delay t — 400 — ns AINIT 1 All timing assumes slew rate control disabled and high drive strength enabled. 2 Delay from analog input to the CMPxOUT output pin. Measured with an input waveform that switches 30mV above and below the reference. 2.13 Programmable Gain Amplifier (PGA) Characteristics Table15. Programmable Gain Amplifier Electrical Specifications Num C Parameter Symbol Min Typical Max Unit 1 T Supply current adder I uA DDON (cid:129) normal mode (LP=0) — 450 550 (cid:129) low power mode (LP=1) — 250 300 2 T Supply current adder (stand-by) I — 1 10 nA DDAOFF 3 T Absolute analog input level V V V /2 V V IL SSA DDA DDA MC9S08MP16 Series Data Sheet, Rev. 2 26 Freescale Semiconductor

Electrical Characteristics Table15. Programmable Gain Amplifier Electrical Specifications (continued) Num C Parameter Symbol Min Typical Max Unit 4 D Differential input voltage VDIFFMAX 0 V –1.4 V (V –1.4) -----D----D----A----------------- – -----D----D----A----------------- 2Gain 2Gain 5 T Linearity (@ voltage gain)1 L V/V V (cid:129) 1x 1 – 1/2 LSB 1 1 + 1/2 LSB (cid:129) 2x 2 – 1/2 LSB 2 2 + 1/2 LSB (cid:129) 4x 4 – 1 LSB 4 4 + 1 LSB (cid:129) 8x 8 – 1 LSB 8 8 + 1 LSB (cid:129) 16x 16 – 4 LSB 16 16 + 4 LSB (cid:129) 32x 32 – 4 LSB 32 32 + 4 LSB 6 T Max gain error E — 1 2 % G 7a D PGA clock f MHz PGA (cid:129) normal mode (LP=0) — 82 82 (cid:129) low power mode (LP=1) — 4 4 7b D PGA sampling frequency3 fSAMPL — 1 — Samples ---------------------------------------------------------------------------------------------------- 1----2-----+-----1---8----------N----U----M-----_----C----L---K----_----G----S---+----4---3------+------5------- per second  f  f f PGA ADC BUS 8 D Input signal bandwidth BW 0 f 8 f 2 Hz SAMPL SAMPL 9 D Charge pump clock frequency f 100 f 4 — Hz cpclk PGA 1 LSB in 12-bit resolution 2 8 MHz is required for PGA achieving 1 s sampling time. 3 ADC in 12-bit mode, long sampling time, f =f ADC PGA 2.14 AC Characteristics This section describes timing characteristics for each peripheral system. 2.14.1 Control Timing Table16. Control Timing Num C Rating Symbol Min Typ1 Max Unit Bus frequency –40 to 105 C fBus DC — 25.67 MHz 1 D (tcyc = 1/fBus) –40 to 125 C fBus DC — 20 MHz 2 P Internal low power oscillator period t 700 — 1300 s LPO 3 D External reset pulse width2 t 100 — — ns extrst 4 D Reset low drive t 34 x t — — ns rstdrv cyc 5 D BKGD/MS setup time after issuing background debug force t 500 — — ns MSSU reset to enter user or BDM modes 6 D BKGD/MS hold time after issuing background debug force t 100 — — s MSH reset to enter user or BDM modes 3 MC9S08MP16 Series Data Sheet, Rev. 2 Freescale Semiconductor 27

Electrical Characteristics Table16. Control Timing (continued) Num C Rating Symbol Min Typ1 Max Unit 7 D Keyboard interrupt pulse width ns Asynchronous path4 t t 100 — — ILIH, IHIL Synchronous path5 1.5 x t — — cyc 8 C Port rise and fall time — t , t ns Rise Fall Low output drive (PTxDS = 0) (load = 50 pF)6 Slew rate control disabled (PTxSE = 0) — 40 — Slew rate control enabled (PTxSE = 1) — 75 — Port rise and fall time — t , t ns Rise Fall High output drive (PTxDS = 1) (load = 50 pF)6 Slew rate control disabled (PTxSE = 0) — 11 — Slew rate control enabled (PTxSE = 1) — 35 — 1 Typical values are based on characterization data at V = 5.0V, 25C unless otherwise stated. DD 2 This is the shortest pulse that is guaranteed to be recognized as a reset pin request. 3 To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of t after V rises MSH DD above V . LVD 4 This is the minimum pulse width that is guaranteed to be recognized as a keyboard interrupt request in stop mode. 5 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case. 6 Timing is shown with respect to 20% V and 80% V levels. Temperature range –40C to 125C. DD DD t extrst RESET PIN Figure17. Reset Timing t IHIL KBIxPn KBIxPn t ILIH Figure18. KBIxPn Timing 2.14.2 FTM Module Timing Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the FTM timer counter. These synchronizers operate from the current ICSOUT clock. The ICSOUT clock period = 0.5  t = 1/(f  2). cyc Bus Table17. FTM Input Timing No. C Function Symbol Min Max Unit 1 D External clock frequency f 0 f /41 Hz TCLK ICSOUT 2 D External clock period t 2 — t TCLK cyc 3 D External clock high time t 0.75 — t clkh cyc MC9S08MP16 Series Data Sheet, Rev. 2 28 Freescale Semiconductor

Electrical Characteristics Table17. FTM Input Timing (continued) No. C Function Symbol Min Max Unit 4 D External clock low time t 0.75 — t clkl cyc 5 D Input capture pulse width t 0.75 — t ICPW cyc 1 The maximum external clock frequency is limited to 10MHz due to input filter characteristics. t TCLK t clkh TCLK t clkl Figure19. FTM External Clock t ICPW FTMxCHn FTMxCHn t ICPW Figure20. FTM Input Capture Pulse 2.14.3 MTIM Module Timing Synchronizer circuits determine the fastest clock that can be used as the optional external clock source to the MTIM timer counter. These synchronizers operate from the current bus rate clock. Table18. MTIM Input Timing No. C Function Symbol Min Max Unit 1 D External clock frequency f 0 f /4 Hz TCLK Bus 2 D External clock period t 4 — t TCLK cyc 3 D External clock high time t 1.5 — t clkh cyc 4 D External clock low time t 1.5 — t clkl cyc t TCLK t clkh TCLK t clkl Figure21. MTIM Timer External Clock MC9S08MP16 Series Data Sheet, Rev. 2 Freescale Semiconductor 29

Electrical Characteristics 2.14.4 SPI Table19 and Figure22 through Figure25 describe the timing requirements for the SPI system. Table19. SPI Electrical Characteristics Num1 C Rating2 Symbol Min Max Unit Cycle time 1 D Master tSCK 2 4096 tcyc Slave tSCK 4 — tcyc Enable lead time 2 D Master t — 1/2 t Lead SCK Slave t 1/2 — t Lead SCK Enable lag time 3 D Master t — 1/2 t Lag SCK Slave t 1/2 — t Lag SCK Clock (SPSCK) high time 4 D Master and Slave tSCKH 1/2 tSCK – 25 — ns Clock (SPSCK) low time 5 D Master and Slave tSCKL 1/2 tSCK – 25 — ns Data setup time (inputs) 6 D Master t 30 — ns SI(M) Slave t 30 — ns SI(S) Data hold time (inputs) 7 D Master t 30 — ns HI(M) Slave t 30 — ns HI(S) 8 D Access time, slave3 t 0 40 ns A 9 D Disable time, slave4 t — 40 ns dis Data setup time (outputs) 10 D Master t — 25 ns SO Slave t — 25 ns SO Data hold time (outputs) 11 D Master t –10 — ns HO Slave t –10 — ns HO Operating frequency f op Master (SPIFE=0) f /4096 85 MHz Bus 12 D Slave (SPIFE=0) dc fBus/4 Master (SPIFE=1) f /4096 56 MHz Bus Slave (SPIFE=1) dc 56 MHz 1 Refer to Figure22 through Figure25. 2 All timing is shown with respect to 20% V and 70% V , unless noted; 100 pF load on all SPI pins. All DD DD timing assumes slew rate control disabled and high drive strength enabled for SPI output pins. 3 Time to data active from high-impedance state. 4 Hold time to high-impedance state. 5 Maximum baud rate must be limited to 8 MHz. 6 Maximum baud rate must be limited to 5 MHz due to input filter characteristics. MC9S08MP16 Series Data Sheet, Rev. 2 30 Freescale Semiconductor

Electrical Characteristics SS1 (OUTPUT) 2 1 3 SCK 5 (CPOL = 0) (OUTPUT) 4 SCK 5 (CPOL = 1) 4 (OUTPUT) 6 7 MISO (INPUT) MSB IN2 BIT 6 . . . 1 LSB IN 10 10 11 MOSI MSB OUT2 BIT 6 . . . 1 LSB OUT (OUTPUT) NOTES: 1. SS output mode (MODFEN = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure22. SPI Master Timing (CPHA = 0) SS(1) (OUTPUT) 1 2 3 SCK 5 (CPOL = 0) (OUTPUT) 4 SCK 5 (CPOL = 1) 4 (OUTPUT) 6 7 MISO (INPUT) MSB IN(2) BIT 6 . . . 1 LSB IN 10 11 MOSI MSB OUT(2) BIT 6 . . . 1 LSB OUT (OUTPUT) NOTES: 1. SS output mode (MODFEN = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure23. SPI Master Timing (CPHA = 1) MC9S08MP16 Series Data Sheet, Rev. 2 Freescale Semiconductor 31

Electrical Characteristics SS (INPUT) 1 3 SCK 5 (CPOL = 0) (INPUT) 4 2 SCK 5 (CPOL = 1) (INPUT) 4 9 8 10 11 MISO SEE (OUTPUT) SLAVE MSB OUT BIT 6 . . . 1 SLAVE LSB OUT NOTE 6 7 MOSI (INPUT) MSB IN BIT 6 . . . 1 LSB IN NOTE: 1. Not defined but normally MSB of character just received Figure24. SPI Slave Timing (CPHA = 0) SS (INPUT) 1 3 2 SCK (CPOL = 0) 5 (INPUT) 4 SCK 5 (CPOL = 1) 4 (INPUT) 10 11 9 MISO SEE (OUTPUT) NOTE SLAVE MSB OUT BIT 6 . . . 1 SLAVE LSB OUT 8 6 7 MOSI (INPUT) MSB IN BIT 6 . . . 1 LSB IN NOTE: 1. Not defined but normally LSB of character just received Figure25. SPI Slave Timing (CPHA = 1) MC9S08MP16 Series Data Sheet, Rev. 2 32 Freescale Semiconductor

Electrical Characteristics 2.15 Flash Memory Specifications This section provides details about program/erase times and program-erase endurance for the flash memory. Program and erase operations do not require any special power sources other than the normal V supply. For more detailed DD information about program/erase operations, see the Memory section. Table20. Flash Memory Characteristics Num C Characteristic Symbol Min Typical Max Unit — Supply voltage for program/erase 1 2.7 5.5 -40C to 125C V V prog/erase 2 — Supply voltage for read operation V 2.7 5.5 V Read 3 — Internal FCLK frequency1 f 150 200 kHz FCLK 4 — Internal FCLK period (1/FCLK) t 5 6.67 s Fcyc 5 C Byte program time (random location)2 t 9 t prog Fcyc 6 — Byte program time (burst mode)2 t 4 t Burst Fcyc 7 D Page erase time2 t 4000 t Page Fcyc 8 D Mass erase time2 t 20,000 t Mass Fcyc 9 C Byte program current3 R — 4 — mA IDDBP 10 C Page erase current3 R — 6 — mA IDDPE Program/erase endurance4 11 C T to T = –40C to + 125C 10,000 — — cycles L H T = 25C 100,000 — 12 C Data retention5 t 15 100 — years D_ret 1 The frequency of this clock is controlled by a software setting. 2 These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for calculating approximate time to program and erase. 3 The program and erase currents are additional to the standard run I . These values are measured at room temperatures with DD V = 5.0 V, bus frequency = 4.0 MHz. DD 4 Typical endurance for Flash is based upon the intrinsic bit cell performance. For additional information on how Freescale defines typical endurance, please refer to Engineering Bulletin EB619/D, Typical Endurance for Nonvolatile Memory. 5 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25C using the Arrhenius equation. For additional information on how Freescale defines typical data retention, please refer to Engineering Bulletin EB618/D, Typical Data Retention for Nonvolatile Memory. 2.16 EMC Performance Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the MCU resides. Board design and layout, circuit topology choices, location and characteristics of external components as well as MCU software operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC performance. 2.16.1 Radiated Emissions Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM Cell method in accordance with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed with the microcontroller installed on a MC9S08MP16 Series Data Sheet, Rev. 2 Freescale Semiconductor 33

Ordering Information custom EMC evaluation board while running specialized EMC test software. The radiated emissions from the microcontroller are measured in a TEM cell in two package orientations (North and East). The maximum radiated RF emissions of the tested configuration in all orientations are less than or equal to the reported emissions levels. Table21. Radiated Emissions, Electric Field Level1 Parameter Symbol Conditions Frequency f /f Unit OSC BUS (Max) 0.15 – 50 MHz 3 50 – 150 MHz 8 V = 5V dBV DD 150 – 500 MHz –4 Radiated emissions, TA = +25C 4 MHz crystal V electric field RE_TEM package type 500 – 1000 MHz 2 MHz bus –8 48 LQFP IEC Level2 N — SAE Level3 1 — 1 Data based on qualification test results. The reported emission level is the value of the maximum emission, rounded up to the next whole number, from among the measured orientations in each frequency range. 2 IEC level maximums: N  12 dBV, L  24 dBV, I  36 dBV 3 SAE level maximums: 1  10 dBV, 2  20 dBV, 3  30 dBV, 4  40 dBV 3 Ordering Information This section contains ordering information for MC9S08MP16 and MC9S08MP12 devices. Table22. Device and Package Options Memory Available Packages2 Temp Device Number1 Range Flash RAM 48-Pin 32-Pin 28-Pin Consumer and Industrial Qualification MC9S08MP16 V 16K 1024 48 LQFP 32 LQFP 28 SOIC MC9S08MP12 V 12K 512 — — 28 SOIC Automotive Qualification S9S08MP16 C, V, M 16K 1024 48 LQFP — — 1 See the MC9S08MP16RM Reference Manual (MC9S08MP16RM) for a complete description of modules included on each device. 2 See Table23 for package information. MC9S08MP16 Series Data Sheet, Rev. 2 34 Freescale Semiconductor

Package Information 3.1 Device Numbering Scheme Example of the device numbering system: xx 9 S08 MP nn E2 y zz Package designator (see Table23) Status MC = Consumer & Temperature range Industrial C = –40C to 85C S = Automotive Qualified V = –40C to 105C Memory M = –40C to 125C 9 = Flash-based Wafer fab site and mask revision Core (this field appears only in automotive-qualified part numbers) Family Flash size 16 KBytes 12 KBytes 4 Package Information The latest package outline drawings are available on the product summary pages on our web site: http://www.freescale.com/8bit. The following table lists the document numbers per package. Use these numbers in the web page’s keyword search engine to find the latest package outline drawings. NOTE The 32 LQFP and 28 SOIC are not qualified to meet automotive requirements. Table23. Package Descriptions Pin Count Package Type Abbreviation Designator Case No. Document No. 48 Low Quad Flat Pack LQFP LF 932-03 98ASH00962A 32 Low Quad Flat Pack LQFP LC 873A-03 98ASH70029A 28 Small Outline Integrated Circuit SOIC WL 751F-05 98ASB42345B 5 Related Documentation Find the most current versions of all documents at http://www.freescale.com. Reference Manual (MC9S08MP16RM) Contains extensive product information including modes of operation, memory, resets and interrupts, register definition, port pins, CPU, and all module information. 6 Revision History To provide the most up-to-date information, the revision of our documents on the World Wide Web are the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://www.freescale.com MC9S08MP16 Series Data Sheet, Rev. 2 Freescale Semiconductor 35

Table24 summarizes changes contained in this document. Table24. Revision History Rev Date Description of Changes 1 10/15/2009 Initial public revision 2 08/09/2011 Updated Table 10. Changed the value of row 8 column “C” from to C to P. How to Reach Us: Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or Home Page: implied copyright licenses granted hereunder to design or fabricate any integrated www.freescale.com circuits or integrated circuits based on the information in this document. Web Support: http://www.freescale.com/support Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or USA/Europe or Locations Not Listed: guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor, Inc. Freescale Semiconductor assume any liability arising out of the application or use of any Technical Information Center, EL516 product or circuit, and specifically disclaims any and all liability, including without 2100 East Elliot Road Tempe, Arizona 85284 limitation consequential or incidental damages. “Typical” parameters that may be +1-800-521-6274 or +1-480-768-2130 provided in Freescale Semiconductor data sheets and/or specifications can and do vary www.freescale.com/support in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by Europe, Middle East, and Africa: customer’s technical experts. Freescale Semiconductor does not convey any license Freescale Halbleiter Deutschland GmbH under its patent rights nor the rights of others. Freescale Semiconductor products are Technical Information Center not designed, intended, or authorized for use as components in systems intended for Schatzbogen 7 surgical implant into the body, or other applications intended to support or sustain life, 81829 Muenchen, Germany +44 1296 380 456 (English) or for any other application in which the failure of the Freescale Semiconductor product +46 8 52200080 (English) could create a situation where personal injury or death may occur. Should Buyer +49 89 92103 559 (German) purchase or use Freescale Semiconductor products for any such unintended or +33 1 69 35 48 48 (French) unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and www.freescale.com/support its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, Japan: directly or indirectly, any claim of personal injury or death associated with such Freescale Semiconductor Japan Ltd. unintended or unauthorized use, even if such claim alleges that Freescale Headquarters ARCO Tower 15F Semiconductor was negligent regarding the design or manufacture of the part. 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 RoHS-compliant and/or Pb-free versions of Freescale products have the functionality Japan and electrical characteristics as their non-RoHS-compliant and/or non-Pb-free 0120 191014 or +81 3 5437 9125 support.japan@freescale.com counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. Asia/Pacific: Freescale Semiconductor China Ltd. For information on Freescale’s Environmental Products program, go to Exchange Building 23F No. 118 Jianguo Road http://www.freescale.com/epp. Chaoyang District Beijing 100022 Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. China All other product or service names are the property of their respective owners. +86 10 5879 8000 support.asia@freescale.com © Freescale Semiconductor, Inc. 2009-2011. All rights reserved. For Literature Requests Only: Freescale Semiconductor Literature Distribution Center 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com Document Number: MC9S08MP16 Rev. 2 08/2011

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